FRDM-IMX93

Board Overview

FRDM-IMX93

Name:

frdm_imx93

Vendor:

NXP Semiconductors

Architecture:

arm64

SoC:

mimx9352

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Overview

The FRDM-IMX93 board is a low-cost and compact platform designed to show the most commonly used features of the i.MX 93 Applications Processor in a small and low cost package. The FRDM-IMX93 board is an entry-level development board, which helps developers to get familiar with the processor before investing a large amount of resources in more specific designs.

i.MX93 MPU is composed of one cluster of 2x Cortex®-A55 cores and a single Cortex®-M33 core. Zephyr RTOS is ported on Cortex®-A55 core.

Hardware

• i.MX 93 applications processor

  • The processor integrates up to two Arm Cortex-A55 cores, and supports built-in Arm Cortex-M33 core.

• RAM: 2GB LPDDR4

• Storage:

  • SanDisk 16GB eMMC5.1

  • microSD Socket

• Wireless:

  • Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, and 802.15.4

• USB:

  • One USB 2.0 Type C connector

  • One USB 2.0 Type A connector

• Ethernet

• PCI-E M.2

• Connectors:

  • 40-Pin Dual Row Header

• LEDs:

  • 1x Power status LED

  • 1x RGB LED

• Debug

  • JTAG 3-pin connector

  • USB-C port for UART debug, two COM ports for A55 and M33

Supported Features

The frdm_imx93 board supports the hardware features listed below.

on-chip / on-board

Feature integrated in the SoC / present on the board.

2 / 2

Number of instances that are enabled / disabled.
Click on the label to see the first instance of this feature in the board/SoC DTS files.

vnd,foo

Compatible string for the Devicetree binding matching the feature.
Click on the link to view the binding documentation.

frdm_imx93/mimx9352/a55 target

Type	Location	Description	Compatible
CPU	on-chip	ARM Cortex-A55 CPU1 1	arm,cortex-a55
CAN	on-chip	NXP FlexCAN CANFD controller1 1	nxp,flexcan-fd
Clock control	on-chip	i.MX CCM Rev2 (Clock Controller Module) IP node1	nxp,imx-ccm-rev2
	on-chip	Generic fixed-rate clock provider4	fixed-clock
Counter	on-chip	NXP Timer/PWM Module (TPM) used as timer6	nxp,tpm-timer
DAI	on-chip	NXP Synchronous Audio Interface (SAI)1	nxp,dai-sai
DMA	on-chip	NXP enhanced Direct Memory Access (eDMA)1	nxp,edma
Ethernet	on-chip	NXP ENET1G IP Module1	nxp,enet1g
	on-chip	NXP ENET MAC/L2 Device1	nxp,enet-mac
	on-chip	NXP ENET PTP (Precision Time Protocol) Clock1	nxp,enet-ptp-clock
GPIO & Headers	on-chip	i.MX RGPIO4	nxp,imx-rgpio
	on-board	NXP PCAL6408 I2C GPIO expander1	nxp,pcal6408
	on-board	NXP PCAL6524 I2C GPIO expander1	nxp,pcal6524
I2C	on-chip	NXP LPI2C controller2 6	nxp,lpi2c
Input	on-board	Group of GPIO-bound input keys1	gpio-keys
Interrupt controller	on-chip	ARM Generic Interrupt Controller v31	arm,gic-v3
LED	on-board	Group of GPIO-controlled LEDs1	gpio-leds
MDIO	on-chip	NXP ENET MDIO Features1	nxp,enet-mdio
PHY	on-board	Simple GPIO controlled CAN transceiver1	can-transceiver-gpio
Pin control	on-chip	This compatible binding should be applied to the device’s iomuxc DTS node1	nxp,imx-iomuxc
	on-chip	The node has the ‘pinctrl’ node label set in MCUX SoC’s devicetree1	nxp,imx93-pinctrl
Power management CPU operations	on-chip	Power State Coordination Interface (PSCI) version 1.11	arm,psci-1.1
SDHC	on-chip	NXP imx USDHC controller2	nxp,imx-usdhc
Serial controller	on-chip	NXP LPUART1 1	nxp,lpuart
SPI	on-chip	NXP LPSPI controller8	nxp,lpspi
Timer	on-chip	per-core ARM architected timer1	arm,armv8-timer
Watchdog	on-chip	NXP watchdog (WDOG32)1 1	nxp,wdog32

Devices

System Clock

This board configuration uses a system clock frequency of 24 MHz. Cortex-A55 Core runs up to 1.7 GHz. Cortex-M33 Core runs up to 200MHz in which SYSTICK runs on same frequency.

Serial Port

This board configuration uses a single serial communication channel with the CPU’s UART2 for A55 core and M33 core.

uSDHC (SD or eMMC Interface on A55)

i.MX 93 processor has three Ultra Secure Digital Host Controller (uSDHC) modules for SD/eMMC interface support. On the FRDM-IMX93 board, the uSDHC2 interface of the processor connects to the MicroSD card slot (P13), and uSDHC1 interface connects to the eMMC memory (located at the SOM board). DTS overlay file “usdhc1.overlay” and “usdhc2.overlay” are provided to enable specified the uSDHC controller.

Currently it relies on U-boot or Linux to boot Zephyr on Cortex-A Core, so Zephyr needs to use a different uSDHC controller from U-boot or Linux to avoid resource conflict. For example, if FRDM-IMX93 board boots from SD Card which uses uSDHC2, Zephyr can use MMC which uses uSDHC1 for testing:

# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 tests/subsys/sd/mmc -- -DEXTRA_DTC_OVERLAY_FILE=usdhc1.overlay

And if FRDM-IMX93 board boots from MMC which uses uSDHC1, Zephyr can use SD Card which uses uSDHC2 for testing:

# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 tests/subsys/sd/sdmmc -- -DEXTRA_DTC_OVERLAY_FILE=usdhc2.overlay

User Button GPIO Option

The user buttons USER_BTN1 and USER_BTN2 are connected to onboard GPIO expander PCAL6524 by default, but can be changed to connect to FRDM-IMX93 GPIO. A devicetree overlay is included to support this.

Run following command to test user buttons connected to FRDM-IMX93 GPIO:

# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 samples/basic/button -- -DEXTRA_DTC_OVERLAY_FILE=frdm_imx93_mimx9352_native_btn.overlay

Note: The overlay only supports mimx9352/a55, but can be extended to support mimx9352/m33 if I2C and PCAL6524 is enabled.

Programming and Debugging (A55)

U-Boot “cpu” command is used to load and kick Zephyr to Cortex-A secondary Core, Currently it is supported in : Real-Time Edge U-Boot (use the branch “uboot_vxxxx.xx-y.y.y, xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example “uboot_v2023.04-2.9.0” branch is U-Boot v2023.04 used in Real-Time Edge Software release v2.9.0), and pre-build images and user guide can be found at Real-Time Edge Software.

Copy the compiled zephyr.bin to the first FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot execution at prompt.

Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:

fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000

Or use the following command to kick zephyr.bin to Cortex-A55 Core0:

fatload mmc 1:1 0xd0000000 zephyr.bin; dcache off; icache flush; go 0xd0000000

Use this configuration to run basic Zephyr applications and kernel tests, for example, with the Basic Synchronization sample:

# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 samples/synchronization

This will build an image with the synchronization sample app, boot it and display the following console output:

*** Booting Zephyr OS build v4.1.0-41-g6395333e3d18 ***
thread_a: Hello World from cpu 0 on frdm_imx93!
thread_b: Hello World from cpu 0 on frdm_imx93!
thread_a: Hello World from cpu 0 on frdm_imx93!
thread_b: Hello World from cpu 0 on frdm_imx93!

System Reboot (A55)

Currently i.MX93 only support cold reboot and doesn’t support warm reboot. Use this configuratiuon to verify cold reboot with Custom Shell module sample:

# From the root of the zephyr repository
west build -b frdm_imx93/mimx9352/a55 samples/subsys/shell/shell_module

This will build an image with the shell sample app, boot it and execute kernel reboot command in shell command line:

uart:~$ kernel reboot cold

Support Resources for Zephyr

• NXP Zephyr Downstream Software Development Kit

• MCUXpresso for VS Code, wiki documentation and Zephyr lab guides

• NXP Zephyr Knowledge Hub

• NXP’s Zephyr landing page (including training resources)

• NXP Support Community forum for Zephyr