|
1242 | 1242 | },
|
1243 | 1243 | "lpuart_clock_source": {
|
1244 | 1244 | "help": "Define the LPUART clock source. Mask values: USE_LPUART_CLK_LSE, USE_LPUART_CLK_PCLK1, USE_LPUART_CLK_HSI",
|
1245 |
| - "value": "USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1" |
| 1245 | + "value": "USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1|USE_LPUART_CLK_PCLK3" |
1246 | 1246 | },
|
1247 | 1247 | "stdio_uart_tx": {
|
1248 | 1248 | "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden"
|
|
4221 | 4221 | "0854"
|
4222 | 4222 | ]
|
4223 | 4223 | },
|
| 4224 | + "MCU_STM32U5": { |
| 4225 | + "inherits": [ |
| 4226 | + "MCU_STM32" |
| 4227 | + ], |
| 4228 | + "public": false, |
| 4229 | + "core": "Cortex-M33FE", |
| 4230 | + "extra_labels_add": [ |
| 4231 | + "STM32U5" |
| 4232 | + ], |
| 4233 | + "components_add": [ |
| 4234 | + "FLASHIAP" |
| 4235 | + ], |
| 4236 | + "macros_add": [ |
| 4237 | + "MBED_TICKLESS", |
| 4238 | + "EXTRA_IDLE_STACK_REQUIRED" |
| 4239 | + ], |
| 4240 | + "config": { |
| 4241 | + "clock_source": { |
| 4242 | + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", |
| 4243 | + "value": "USE_PLL_MSI", |
| 4244 | + "macro_name": "CLOCK_SOURCE" |
| 4245 | + }, |
| 4246 | + "lpticker_lptim": { |
| 4247 | + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", |
| 4248 | + "value": 1 |
| 4249 | + }, |
| 4250 | + "lse_drive_load_level": { |
| 4251 | + "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", |
| 4252 | + "value": "RCC_LSEDRIVE_LOW" |
| 4253 | + }, |
| 4254 | + "i2c_timing_value_algo": { |
| 4255 | + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", |
| 4256 | + "value": false |
| 4257 | + } |
| 4258 | + }, |
| 4259 | + "overrides": { |
| 4260 | + "lpticker_delay_ticks": 0, |
| 4261 | + "lpuart_clock_source": "USE_LPUART_CLK_HSI" |
| 4262 | + }, |
| 4263 | + "device_has_add": [ |
| 4264 | + "ANALOGOUT", |
| 4265 | + "CRC", |
| 4266 | + "FLASH", |
| 4267 | + "MPU", |
| 4268 | + "TRNG", |
| 4269 | + "SERIAL_ASYNCH" |
| 4270 | + ] |
| 4271 | + }, |
| 4272 | + "MCU_STM32U575xI": { |
| 4273 | + "inherits": [ |
| 4274 | + "MCU_STM32U5" |
| 4275 | + ], |
| 4276 | + "public": false, |
| 4277 | + "extra_labels_add": [ |
| 4278 | + "STM32U575xI" |
| 4279 | + ], |
| 4280 | + "macros_add": [ |
| 4281 | + "STM32U575xx" |
| 4282 | + ] |
| 4283 | + }, |
| 4284 | + "NUCLEO_U575ZI_Q": { |
| 4285 | + "inherits": [ |
| 4286 | + "MCU_STM32U575xI" |
| 4287 | + ], |
| 4288 | + "supported_form_factors": [ |
| 4289 | + "ARDUINO_UNO" |
| 4290 | + ], |
| 4291 | + "device_name": "STM32U575ZITx", |
| 4292 | + "detect_code": [ |
| 4293 | + "886" |
| 4294 | + ] |
| 4295 | + }, |
| 4296 | + "MCU_STM32U585xI": { |
| 4297 | + "inherits": [ |
| 4298 | + "MCU_STM32U5" |
| 4299 | + ], |
| 4300 | + "public": false, |
| 4301 | + "extra_labels_add": [ |
| 4302 | + "STM32U585xI" |
| 4303 | + ], |
| 4304 | + "macros_add": [ |
| 4305 | + "STM32U585xx" |
| 4306 | + ] |
| 4307 | + }, |
| 4308 | + "B_U585I_IOT02A": { |
| 4309 | + "inherits": [ |
| 4310 | + "MCU_STM32U585xI" |
| 4311 | + ], |
| 4312 | + "supported_form_factors": [ |
| 4313 | + "STMOD", |
| 4314 | + "PMOD", |
| 4315 | + "ARDUINO_UNO" |
| 4316 | + ], |
| 4317 | + "device_name": "STM32U585AIIx", |
| 4318 | + "detect_code": [ |
| 4319 | + "887" |
| 4320 | + ] |
| 4321 | + }, |
4224 | 4322 | "MCU_STM32WB": {
|
4225 | 4323 | "inherits": [
|
4226 | 4324 | "MCU_STM32"
|
|
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