Fix ARMCC & IAR compile errors

Author: Archcady

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct

@@ -38,6 +38,9 @@ LR_RAM 0x10006000 0x6FFFF  {
    .ANY (+ZI)
   }
 
+  ARM_LIB_STACK (0x10070000 - 0x1000) EMPTY 0x1000 {
+  }
+
   TCM_OVERLAY 0x1FFF0000 0x10000{
     lwip_mem.o(.bss*)
     lwip_memp.o(.bss*)

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c

@@ -105,15 +105,15 @@ void __TRAP_HardFaultHandler_Patch(uint32_t addr)
     uint32_t stackpc;
     uint16_t asmcode;
 
-    cfsr = __HAL_READ32(0xE000ED28, 0x0);
+    cfsr = HAL_READ32(0xE000ED28, 0x0);
 
     // Violation to memory access protection
     if (cfsr & 0x82) {
 
-        bfar = __HAL_READ32(0xE000ED38, 0x0);
+        bfar = HAL_READ32(0xE000ED38, 0x0);
 
         // invalid access to wifi register, usually happened in LPS 32K or IPS
-        if (bfar >= WLAN_BASE && bfar < WLAN_BASE + 0x40000) {
+        if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) {
 
             //__BKPT(0);
 
@@ -128,18 +128,18 @@ void __TRAP_HardFaultHandler_Patch(uint32_t addr)
              * However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
              * So the register value is un-predictable.
              **/
-            stackpc = __HAL_READ32(addr, 0x18);
-            asmcode = __HAL_READ16(stackpc, 0);
+            stackpc = HAL_READ32(addr, 0x18);
+            asmcode = HAL_READ16(stackpc, 0);
             if ((asmcode & 0xF800) > 0xE000) {
                 // 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101)
-                __HAL_WRITE32(addr, 0x18, stackpc + 4);
+                HAL_WRITE32(addr, 0x18, stackpc + 4);
             } else {
                 // 16-bit instruction
-                __HAL_WRITE32(addr, 0x18, stackpc + 2);
+                HAL_WRITE32(addr, 0x18, stackpc + 2);
             }
 
             // clear Hard Fault Status Register
-            __HAL_WRITE32(0xE000ED2C, 0x0, __HAL_READ32(0xE000ED2C, 0x0));
+            HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0));
             return;
         }
     }
@@ -181,11 +181,11 @@ void PLAT_Start(void)
 #endif
 
     // Clear RAM BSS
-#ifdef __GNUC__
+#if defined (__ICCARM__) || defined (__CC_ARM)
+    __memset((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
+#else
     __memset((void *)__bss_sram1_start__, 0, __bss_sram1_end__ - __bss_sram1_start__);
     __memset((void *)__bss_sram2_start__, 0, __bss_sram2_end__ - __bss_sram2_start__);
-#else
-    __memset((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
 #endif
 
 #if defined (__CC_ARM)

targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c

@@ -104,7 +104,7 @@ uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data)
         shift = start - addr;
         count = MIN(FLASH_SECTOR_SIZE - shift, len);
         flash_ext_stream_read(&flash_obj, addr, shift, buf);
-        memcpy((void *)buf + shift, (void *)pdata, count);
+        memcpy((void *)(buf + shift), (void *)pdata, count);
 
         flash_ext_erase_sector(&flash_obj, addr);
         flash_ext_stream_write(&flash_obj, addr, FLASH_SECTOR_SIZE, buf);

tools/targets/REALTEK_RTL8195AM.py

@@ -59,9 +59,6 @@ def get_version_by_time():
     secs = int((datetime.now()-datetime(2016,11,1)).total_seconds())
     return RAM2_VER + secs
 
-# ----------------------------
-#       main function
-# ----------------------------
 def prepend(image, entry, segment, image_ram2, image_ota):
 
     # parse input arguments
@@ -229,6 +226,13 @@ def parse_load_segment(toolchain, image_elf):
 
 def write_load_segment(image_elf, image_bin, segment):
     file_elf = open(image_elf, "rb")
+    #delete folder with same name when using ARMCC
+    if os.path.isfile(image_bin):
+        pass
+    else:
+        for i in os.listdir(image_bin):
+            os.remove(os.path.join(image_bin, i))
+        os.removedirs(image_bin)
     file_bin = open(image_bin, "wb")
     for (offset, addr, size) in segment:
         file_elf.seek(offset)