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Commits on Sep 24, 2018

• DEMUX done, Some stuff in MUX fixed

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Commits on Sep 23, 2018

• MUXs done

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Commits on Sep 16, 2018

• Started Combinational Logic and made sure images where in git

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Commits on Sep 14, 2018

• Finshed Shift Regesters, add videos, continuing working on myHDL PYNQ

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Commits on Sep 10, 2018

• Update with links to youtube videos of deplyment

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Commits on Sep 2, 2018

• Basic Logic Gates in myHDL redone

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Commits on Aug 30, 2018

• renamed

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• Added TOC to BitwiseBehavior

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• Added myHDL Bitwise behavior notebook Bitselect, shift, concat, slice

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• Finshed Bit Behavior for myHDL

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Commits on Aug 20, 2018

• Added video links to board verification

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• Notebook for myhdl to pynq-z1 just Fabric only

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• Aux, source files for myHDL_PYNQZ12_FabricOnly

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Commits on Aug 14, 2018

• Refactored and added Counters

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• Reorginized files and had issue with rebository

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Commits on Aug 9, 2018

• Create README.md

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• FIFO memory added

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Commits on Jun 30, 2018

• Added images for Arithmetic notebook

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• Redid, made it .10 compatible and added to verilog testbnechs

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• Added version info

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Commits on Jun 28, 2018

• Added Verilog/VHDL outputable testbenches

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• Generated and Aux files for/from Memory.ipynb

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Commits on May 25, 2018

• Made grammatical fixes to Memeory

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• added meomery tutorial

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Commits on May 23, 2018

• Have implemented the full filter structer but have overflow issues that need to be resolved

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• Create README.md

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Commits on May 22, 2018

• Added a 4/5 freq divider

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Commits on May 17, 2018

• Finsihed most of the work on PLL phase detecters and freq dividers

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Commits on Apr 13, 2018

• Added SawWave, and DAC, also refactored file structure

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Commits on Feb 27, 2018

• Initial Publication of CIC

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Commits on Feb 7, 2018

• Create README.md

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• Add files via upload

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Commits on Oct 26, 2017

• Pushing some inprogress work to hub

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Commits on Oct 10, 2017

• Added MSI and Arthmtic

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Commits on Oct 9, 2017

• Added Material

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