Skip to content

Commit d42b9b3

Browse files
ozersaozersa
committed
Apply MAX32660 delta
Update mbed hal function as per of SDK update Signed-off-by: Sadik.Ozer <[email protected]>
1 parent 3f4b177 commit d42b9b3

37 files changed

+231
-184
lines changed

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/dma_regs.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -99,7 +97,7 @@ typedef struct {
9997
typedef struct {
10098
__IO uint32_t int_en; /**< <tt>\b 0x000:</tt> DMA INT_EN Register */
10199
__I uint32_t int_fl; /**< <tt>\b 0x004:</tt> DMA INT_FL Register */
102-
__R uint32_t rsv_0x8_0xff[62];
100+
__I uint32_t rsv_0x8_0xff[62];
103101
__IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */
104102
} mxc_dma_regs_t;
105103

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/fcr_regs.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/flc_regs.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -89,9 +87,9 @@ typedef struct {
8987
__IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */
9088
__IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */
9189
__IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */
92-
__R uint32_t rsv_0xc_0x23[6];
90+
__I uint32_t rsv_0xc_0x23[6];
9391
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
94-
__R uint32_t rsv_0x28_0x2f[2];
92+
__I uint32_t rsv_0x28_0x2f[2];
9593
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
9694
__O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */
9795
} mxc_flc_regs_t;

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gcr_regs.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -90,11 +88,11 @@ typedef struct {
9088
__IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */
9189
__IO uint32_t clk_ctrl; /**< <tt>\b 0x08:</tt> GCR CLK_CTRL Register */
9290
__IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
93-
__R uint32_t rsv_0x10_0x23[5];
91+
__I uint32_t rsv_0x10_0x23[5];
9492
__IO uint32_t pclk_dis0; /**< <tt>\b 0x24:</tt> GCR PCLK_DIS0 Register */
9593
__IO uint32_t mem_ctrl; /**< <tt>\b 0x28:</tt> GCR MEM_CTRL Register */
9694
__IO uint32_t mem_zctrl; /**< <tt>\b 0x2C:</tt> GCR MEM_ZCTRL Register */
97-
__R uint32_t rsv_0x30_0x3f[4];
95+
__I uint32_t rsv_0x30_0x3f[4];
9896
__IO uint32_t sys_stat; /**< <tt>\b 0x40:</tt> GCR SYS_STAT Register */
9997
__IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */
10098
__IO uint32_t pclk_dis1; /**< <tt>\b 0x48:</tt> GCR PCLK_DIS1 Register */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/gpio_regs.h

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,6 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
7370
/// @endcond
7471

7572
/* **** Definitions **** */
@@ -102,13 +99,13 @@ typedef struct {
10299
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
103100
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
104101
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
105-
__I uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
106-
__R uint32_t rsv_0x44;
102+
__IO uint32_t int_stat; /**< <tt>\b 0x40:</tt> GPIO INT_STAT Register */
103+
__I uint32_t rsv_0x44;
107104
__IO uint32_t int_clr; /**< <tt>\b 0x48:</tt> GPIO INT_CLR Register */
108105
__IO uint32_t wake_en; /**< <tt>\b 0x4C:</tt> GPIO WAKE_EN Register */
109106
__IO uint32_t wake_en_set; /**< <tt>\b 0x50:</tt> GPIO WAKE_EN_SET Register */
110107
__IO uint32_t wake_en_clr; /**< <tt>\b 0x54:</tt> GPIO WAKE_EN_CLR Register */
111-
__R uint32_t rsv_0x58;
108+
__I uint32_t rsv_0x58;
112109
__IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:</tt> GPIO INT_DUAL_EDGE Register */
113110
__IO uint32_t pad_cfg1; /**< <tt>\b 0x60:</tt> GPIO PAD_CFG1 Register */
114111
__IO uint32_t pad_cfg2; /**< <tt>\b 0x64:</tt> GPIO PAD_CFG2 Register */
@@ -118,13 +115,13 @@ typedef struct {
118115
__IO uint32_t en2; /**< <tt>\b 0x74:</tt> GPIO EN2 Register */
119116
__IO uint32_t en2_set; /**< <tt>\b 0x78:</tt> GPIO EN2_SET Register */
120117
__IO uint32_t en2_clr; /**< <tt>\b 0x7C:</tt> GPIO EN2_CLR Register */
121-
__R uint32_t rsv_0x80_0xa7[10];
118+
__I uint32_t rsv_0x80_0xa7[10];
122119
__IO uint32_t is; /**< <tt>\b 0xA8:</tt> GPIO IS Register */
123120
__IO uint32_t sr; /**< <tt>\b 0xAC:</tt> GPIO SR Register */
124121
__IO uint32_t ds0; /**< <tt>\b 0xB0:</tt> GPIO DS0 Register */
125122
__IO uint32_t ds1; /**< <tt>\b 0xB4:</tt> GPIO DS1 Register */
126123
__IO uint32_t ps; /**< <tt>\b 0xB8:</tt> GPIO PS Register */
127-
__R uint32_t rsv_0xbc;
124+
__I uint32_t rsv_0xbc;
128125
__IO uint32_t vssel; /**< <tt>\b 0xC0:</tt> GPIO VSSEL Register */
129126
} mxc_gpio_regs_t;
130127

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/i2c_regs.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/icc_regs.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -88,9 +86,9 @@ extern "C" {
8886
typedef struct {
8987
__I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> ICC CACHE_ID Register */
9088
__I uint32_t mem_size; /**< <tt>\b 0x0004:</tt> ICC MEM_SIZE Register */
91-
__R uint32_t rsv_0x8_0xff[62];
89+
__I uint32_t rsv_0x8_0xff[62];
9290
__IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> ICC CACHE_CTRL Register */
93-
__R uint32_t rsv_0x104_0x6ff[383];
91+
__I uint32_t rsv_0x104_0x6ff[383];
9492
__IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> ICC INVALIDATE Register */
9593
} mxc_icc_regs_t;
9694

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/pwrseq_regs.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -89,7 +87,7 @@ typedef struct {
8987
__IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */
9088
__IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */
9189
__IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */
92-
__R uint32_t rsv_0xc_0x3f[13];
90+
__I uint32_t rsv_0xc_0x3f[13];
9391
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
9492
} mxc_pwrseq_regs_t;
9593

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spi_regs.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -92,7 +90,7 @@ typedef struct {
9290
__IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */
9391
__IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */
9492
__IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */
95-
__R uint32_t rsv_0x18;
93+
__I uint32_t rsv_0x18;
9694
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */
9795
__IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */
9896
__IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/spimss_regs.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */
@@ -87,11 +85,11 @@ extern "C" {
8785
*/
8886
typedef struct {
8987
__IO uint16_t data; /**< <tt>\b 0x00:</tt> SPIMSS DATA Register */
90-
__R uint16_t rsv_0x2;
88+
__I uint16_t rsv_0x2;
9189
__IO uint32_t ctrl; /**< <tt>\b 0x04:</tt> SPIMSS CTRL Register */
9290
__IO uint32_t int_fl; /**< <tt>\b 0x08:</tt> SPIMSS INT_FL Register */
9391
__IO uint32_t mode; /**< <tt>\b 0x0C:</tt> SPIMSS MODE Register */
94-
__R uint32_t rsv_0x10;
92+
__I uint32_t rsv_0x10;
9593
__IO uint32_t brg; /**< <tt>\b 0x14:</tt> SPIMSS BRG Register */
9694
__IO uint32_t dma; /**< <tt>\b 0x18:</tt> SPIMSS DMA Register */
9795
__IO uint32_t i2s_ctrl; /**< <tt>\b 0x1C:</tt> SPIMSS I2S_CTRL Register */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/tmr_regs.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/uart_regs.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Include/wdt_regs.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,9 +67,7 @@ extern "C" {
6767
#ifndef __O
6868
#define __O volatile
6969
#endif
70-
#ifndef __R
71-
#define __R volatile const
72-
#endif
70+
7371
/// @endcond
7472

7573
/* **** Definitions **** */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c

Lines changed: 18 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,6 @@
4646
#include "wdt_regs.h"
4747
#include "mxc_sys.h"
4848

49-
extern void (*const __isr_vector[])(void);
5049
uint32_t SystemCoreClock = HIRC96_FREQ;
5150

5251
__weak void SystemCoreClockUpdate(void)
@@ -76,7 +75,7 @@ __weak void SystemCoreClockUpdate(void)
7675
}
7776

7877
// Get the clock divider
79-
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_PSC) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
78+
div = (MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_CLKSEL) >> MXC_F_GCR_CLK_CTRL_PSC_POS;
8079

8180
SystemCoreClock = base_freq >> div;
8281
}
@@ -91,7 +90,12 @@ __weak void SystemCoreClockUpdate(void)
9190
*/
9291
__weak int PreInit(void)
9392
{
94-
/* Do nothing */
93+
/* Switch system clock to HIRC, 96 MHz*/
94+
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
95+
96+
/* Enable cache here to reduce boot time */
97+
MXC_ICC_Enable();
98+
9599
return 0;
96100
}
97101

@@ -102,6 +106,12 @@ __weak int Board_Init(void)
102106
return 0;
103107
}
104108

109+
/* Override this function for early platform initialization */
110+
__weak void low_level_init(void)
111+
{
112+
/* Do nothing */
113+
}
114+
105115
/* This function is called just before control is transferred to main().
106116
*
107117
* You may over-ride this function in your program by defining a custom
@@ -110,23 +120,16 @@ __weak int Board_Init(void)
110120
*/
111121
__weak void SystemInit(void)
112122
{
113-
/* Configure the interrupt controller to use the application vector table in */
114-
/* the application space */
115-
/* IAR & Keil must set vector table after all memory initialization. */
116-
SCB->VTOR = (uint32_t)__isr_vector;
117-
118-
MXC_WDT0->ctrl &=
119-
~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
123+
MXC_WDT0->ctrl &= ~MXC_F_WDT_CTRL_WDT_EN; /* Turn off watchdog. Application can re-enable as needed. */
120124

125+
#if (__FPU_PRESENT == 1)
121126
/* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
122127
/* Grant full access, per "Table B3-24 CPACR bit assignments". */
123128
/* DDI0403D "ARMv7-M Architecture Reference Manual" */
124129
SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
125130
__DSB();
126131
__ISB();
127-
128-
/* Switch system clock to HIRC */
129-
MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC);
132+
#endif
130133

131134
/* Disable clocks to peripherals by default to reduce power */
132135
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_DMA);
@@ -140,26 +143,6 @@ __weak void SystemInit(void)
140143
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2);
141144
MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1);
142145

143-
Board_Init();
144-
}
145-
146-
#if defined(__CC_ARM)
147-
/* Global variable initialization does not occur until post scatterload in Keil tools.*/
148-
149-
/* External function called after our post scatterload function implementation. */
150-
extern void $Super$$__main_after_scatterload(void);
151-
152-
/**
153-
* @brief Initialization function for SystemCoreClock and Board_Init.
154-
* @details $Sub$$__main_after_scatterload is called during system startup in the Keil
155-
* toolset. Global variable and static variable space must be set up by the compiler
156-
* prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
157-
* require global memory for variable storage and are called from this function in
158-
* the Keil tool chain.
159-
*/
160-
void $Sub$$__main_after_scatterload(void)
161-
{
162-
SystemInit();
163-
$Super$$__main_after_scatterload();
146+
/* Early platform initialization */
147+
low_level_init();
164148
}
165-
#endif /* __CC_ARM */

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/lp.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -160,18 +160,18 @@ void MXC_LP_DisableSysRAM0LightSleep(void);
160160
* @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode.
161161
* Call this function multiple times to enable pins on multiple ports. This function does not configure
162162
* the GPIO pins nor does it setup their interrupt functionality.
163-
* @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the
164-
* structure are used. The func and pad fields are ignored.
163+
* @param port The port to configure as wakeup sources.
164+
* @param mask The pins to configure as wakeup sources.
165165
*/
166-
void MXC_LP_EnableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
166+
void MXC_LP_EnableGPIOWakeup(unsigned int port, unsigned int mask);
167167

168168
/**
169169
* @brief Disables the selected GPIO port and its selected pins as a wake up source.
170170
* Call this function multiple times to disable pins on multiple ports.
171-
* @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the
172-
* structure are used. The func and pad fields are ignored.
171+
* @param port The port to configure as wakeup sources.
172+
* @param mask The pins to configure as wakeup sources.
173173
*/
174-
void MXC_LP_DisableGPIOWakeup(const mxc_gpio_cfg_t *wu_pins);
174+
void MXC_LP_DisableGPIOWakeup(unsigned int port, unsigned int mask);
175175

176176
/**
177177
* @brief Enables the RTC alarm to wake up the device from any low power mode.

‎targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Include/MAX32660/mxc_device.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,9 @@
4949
// Create a string definition for the TARGET
5050
#define STRING_ARG(arg) #arg
5151
#define STRING_NAME(name) STRING_ARG(name)
52+
#if MBED_VERSION && MBED_VERSION < 51200
5253
#define TARGET_NAME STRING_NAME(TARGET)
54+
#endif
5355

5456
// Define which revisions of the IP we are using
5557
#ifndef TARGET_REV

0 commit comments

Comments
 (0)