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Commits on Jan 8, 2023

• Systematically initialize registers to zero (and not only in BENCH mode)

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• Still testing what happens in VIVADO: included display of current

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• Fixes for VIVADO

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• * added step7 with disassembler for testing what happens with Vivado (issue #87)

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Commits on Nov 24, 2022

• Precision: for Ubuntu

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• New script to install YOSYS/NEXTPNR for ICE40-based FPGAs

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Commits on Oct 12, 2022

• * Added precompiled RAYSTONES, DHRYSONES and COREMARK

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Commits on Oct 2, 2022

• * Added new frequencies in PLL (now we got something that runs

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Commits on Sep 26, 2022

• typos.

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Commits on Sep 25, 2022

• Added step on RV32M

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• typo !

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• Small fixes in step 9

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• BRAM, not DRAM !

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• Finished writing tutorial for step 9 (RAS)

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Commits on Sep 19, 2022

• Restored % 21 instead of & 15 (now we have div/rem in pipelineY.v)

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• better "progress bar"...

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• * added missing .section DATA in assembly programs

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Commits on Sep 18, 2022

• cCleanup, comments.

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• Ooops, `ifdef RV32M instead of CONFIG_RV32M broke everything !!!

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• Comments

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• Made RV32M optional

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• Replaced several imbrications of muxes with big "or" expression in

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• Added comments.

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• cleaner division.

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• cleaner divide, without divResult reg (now uses mux on

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• - Removed registered branch prediction (does not gain anything)

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• 300 iterations (else not enough to measure timings)

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• Fixed load-after-store bug by inserting a bubble :

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• Found bug in pipelineX and pipelineY: when storing at an address and

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Commits on Sep 17, 2022

• - Added reg fwd display in debug.

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Commits on Sep 16, 2022

• pipelineY: added MUL instructions

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• Added "debugger"

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• Comment.

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• Fixed computation of load hazard statistics

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• Added statistic in bench mode.

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