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‎CE224285_PSoC_6MCU_ExternalFlashAccess_in_XIP_Mode_with_QSPI/CE224285_PSoC_6MCU_ExternalFlashAccess_in_XIP_Mode_with_QSPI.pdf

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‎CE224285_PSoC_6MCU_ExternalFlashAccess_in_XIP_Mode_with_QSPI/GeneratedSource/cycfg_qspi_memslot.c

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/*******************************************************************************
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* File Name: cycfg_qspi_memslot.c
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*
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* Description:
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* Provides definitions of the SMIF-driver memory configuration.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_qspi_memslot.h"
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0xEBU,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_QUAD,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0x01U,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_QUAD,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 4U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_QUAD
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x06U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x04U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0xD8U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x60U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x38U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_QUAD,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_QUAD
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x35U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x05U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x01U,
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/* The width of the command transfer. */
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.cmdWidth = CY_SMIF_WIDTH_SINGLE,
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/* The width of the address transfer. */
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.addrWidth = CY_SMIF_WIDTH_SINGLE,
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/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
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.mode = 0xFFFFFFFFU,
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/* The width of the mode command transfer. */
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.modeWidth = CY_SMIF_WIDTH_SINGLE,
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/* The number of dummy cycles. A zero value suggests no dummy cycles. */
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.dummyCycles = 0U,
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/* The width of the data transfer. */
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
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{
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/* Specifies the number of address bytes used by the memory slave device. */
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.numOfAddrBytes = 0x03U,
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/* The size of the memory. */
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.memSize = 0x04000000U,
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/* Specifies the Read command. */
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.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
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/* Specifies the Write Enable command. */
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.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
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/* Specifies the Write Disable command. */
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.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
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/* Specifies the Erase command. */
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.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
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/* Specifies the sector size of each erase. */
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.eraseSize = 0x00040000U,
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/* Specifies the Chip Erase command. */
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.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
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/* Specifies the Program command. */
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.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
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/* Specifies the page size for programming. */
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.programSize = 0x00000200U,
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/* Specifies the command to read the QE-containing status register. */
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.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
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/* Specifies the command to read the WIP-containing status register. */
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.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
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/* Specifies the command to write into the QE-containing status register. */
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.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
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/* The mask for the status register. */
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.stsRegBusyMask = 0x01U,
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/* The mask for the status register. */
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.stsRegQuadEnableMask = 0x02U,
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/* The max time for the erase type-1 cycle-time in ms. */
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.eraseTime = 520U,
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/* The max time for the chip-erase cycle-time in ms. */
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.chipEraseTime = 134000U,
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/* The max time for the page-program cycle-time in us. */
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.programTime = 340U
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};
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const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
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{
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/* Determines the slot number where the memory device is placed. */
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.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
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/* Flags. */
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.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
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/* The data-line selection options for a slave device. */
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.dataSelect = CY_SMIF_DATA_SEL0,
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/* The base address the memory slave is mapped to in the PSoC memory map.
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Valid when the memory-mapped mode is enabled. */
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.baseAddress = 0x18000000U,
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/* The size allocated in the PSoC memory map, for the memory slave device.
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The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
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.memMappedSize = 0x10000U,
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/* If this memory device is one of the devices in the dual quad SPI configuration.
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Valid when the memory mapped mode is enabled. */
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.dualQuadSlots = 0,
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/* The configuration of the device. */
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.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
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};
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const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
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&S25FL512S_SlaveSlot_0
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};
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const cy_stc_smif_block_config_t smifBlockConfig =
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{
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/* The number of SMIF memories defined. */
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.memCount = CY_SMIF_DEVICE_NUM,
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/* The pointer to the array of memory config structures of size memCount. */
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.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
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/* The version of the SMIF driver. */
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.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
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/* The version of the SMIF driver. */
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.minorVersion = CY_SMIF_DRV_VERSION_MINOR
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};

‎CE224285_PSoC_6MCU_ExternalFlashAccess_in_XIP_Mode_with_QSPI/GeneratedSource/cycfg_qspi_memslot.h

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/*******************************************************************************
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* File Name: cycfg_qspi_memslot.h
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*
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* Description:
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* Provides declarations of the SMIF-driver memory configuration.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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/*******************************************************************************
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QSPI_CONFIG_START
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<CySMIFConfiguration>
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<DevicePath>PSoC 6.xml</DevicePath>
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<SlotConfigs>
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<SlotConfig>
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<SlaveSlot>0</SlaveSlot>
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<PartNumber>S25FL512S</PartNumber>
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<MemoryMapped>true</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18000000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1800FFFF</EndAddress>
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<WriteEnable>true</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
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<MemoryConfigsPath>S25FL512S</MemoryConfigsPath>
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<ConfigDataInFlash>true</ConfigDataInFlash>
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</SlotConfig>
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<SlotConfig>
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<SlaveSlot>1</SlaveSlot>
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<PartNumber>Not used</PartNumber>
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<MemoryMapped>false</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18010000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1801FFFF</EndAddress>
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<WriteEnable>false</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
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<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
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<ConfigDataInFlash>false</ConfigDataInFlash>
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</SlotConfig>
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<SlotConfig>
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<SlaveSlot>2</SlaveSlot>
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<PartNumber>Not used</PartNumber>
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<MemoryMapped>false</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18020000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1802FFFF</EndAddress>
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<WriteEnable>false</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
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<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
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<ConfigDataInFlash>false</ConfigDataInFlash>
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</SlotConfig>
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<SlotConfig>
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<SlaveSlot>3</SlaveSlot>
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<PartNumber>Not used</PartNumber>
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<MemoryMapped>false</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18030000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1803FFFF</EndAddress>
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<WriteEnable>false</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
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<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
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<ConfigDataInFlash>false</ConfigDataInFlash>
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</SlotConfig>
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</SlotConfigs>
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</CySMIFConfiguration>
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QSPI_CONFIG_END
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*******************************************************************************/
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#ifndef CYCFG_QSPI_MEMSLOT_H
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#define CYCFG_QSPI_MEMSLOT_H
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#include "cy_smif_memslot.h"
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#define CY_SMIF_DEVICE_NUM 1
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
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extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
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extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
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extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
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extern const cy_stc_smif_block_config_t smifBlockConfig;
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#endif /*CY_SMIF_MEMCONFIG_H*/

‎CE224285_PSoC_6MCU_ExternalFlashAccess_in_XIP_Mode_with_QSPI/GeneratedSource/qspi_config.cfg

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set SMIF_BANKS {
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0 {addr 0x18000000 size 0x10000 psize 0x00000200 esize 0x00040000}
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}

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