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micromintmicromint
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Updates to LPC4330_M4 drivers
1 parent 6d2c15e commit 4e82296

26 files changed

+6885
-2037
lines changed

‎build.log

Lines changed: 220 additions & 0 deletions
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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/LPC43xx.h

Lines changed: 1615 additions & 1489 deletions
Large diffs are not rendered by default.

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/LPC43xx_spifi.ini

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
2+
FUNC void Setup (unsigned int region) {
3+
region &= 0xFF000000;
4+
_WDWORD(0x40043100, region); // Set the shadow pointer
5+
_WDWORD(0xE000ED08, 0); // Set the vector table offset to 0
6+
SP = _RDWORD(0); // Setup Stack Pointer
7+
PC = _RDWORD(4); // Setup Program Counter
8+
}
9+
10+
LOAD %L INCREMENTAL
11+
Setup(0x14000000); // Get ready to execute image in QSPI
12+

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_ARM_STD/startup_LPC43xx.s

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,8 @@
2929
; * this code.
3030
; */
3131

32-
__initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX
32+
; __initial_sp EQU 0x10020000 ; Top of first RAM segment for LPC43XX (IRAM1)
33+
__initial_sp EQU 0x10092000 ; Top of first RAM segment for LPC43XX (IRAM2)
3334

3435
PRESERVE8
3536
THUMB
@@ -121,19 +122,21 @@ __Vectors DCD __initial_sp ; 0 Top of Stack
121122

122123
AREA |.text|, CODE, READONLY
123124

125+
124126
; Reset Handler
125127

126128
Reset_Handler PROC
127129
EXPORT Reset_Handler [WEAK]
130+
IMPORT SystemInit
128131
IMPORT __main
129-
IMPORT SystemInit
130-
LDR R0, =SystemInit
131-
BLX R0
132+
LDR R0, =SystemInit
133+
BLX R0
132134
LDR R0, =__main
133135
BX R0
134136
ENDP
135137

136-
; Dummy Exception Handlers (infinite loops which can be modified)
138+
139+
; Dummy Exception Handlers (infinite loops which can be modified)
137140

138141
NMI_Handler PROC
139142
EXPORT NMI_Handler [WEAK]

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC43XX/TOOLCHAIN_GCC_CR/LPC43xx.ld

Lines changed: 273 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,281 @@
1-
/*
2-
* LPC43XX Dual core Blinky stand-alone Cortex-M4 LD script
3-
*/
1+
/* mbed - LPC4330_M4 linker script
2+
* Based linker script generated by Code Red Technologies Red Suite 7.0
3+
*/
4+
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
45

56
MEMORY
67
{
78
/* Define each memory region */
8-
RO_MEM (rx) : ORIGIN = 0x14000000, LENGTH = 0x40000 /* 256K */
9-
RW_MEM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x8000 /* 32k */
10-
RW_MEM1 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x4000 /* 16K */
11-
SH_MEM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x2000 /* 8k */
12-
FAT12_MEM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 /* 8k */
9+
RamLoc128 (rwx) : ORIGIN = 0x10000118, LENGTH = 0x1FEE8 /* 128K bytes */
10+
RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */
11+
RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes */
12+
RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes */
13+
RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes */
14+
SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes */
15+
1316

1417
}
18+
/* Define a symbol for the top of each memory region */
19+
__top_RamLoc128 = 0x10000000 + 0x20000;
20+
__top_RamLoc72 = 0x10080000 + 0x12000;
21+
__top_RamAHB32 = 0x20000000 + 0x8000;
22+
__top_RamAHB16 = 0x20008000 + 0x4000;
23+
__top_RamAHB_ETB16 = 0x2000c000 + 0x4000;
24+
__top_SPIFI = 0x14000000 + 0x400000;
25+
26+
ENTRY(ResetISR)
27+
28+
SECTIONS
29+
{
30+
31+
/* MAIN TEXT SECTION */
32+
.text : ALIGN(4)
33+
{
34+
FILL(0xff)
35+
__vectors_start__ = ABSOLUTE(.) ;
36+
KEEP(*(.isr_vector))
37+
38+
/* Global Section Table */
39+
. = ALIGN(4) ;
40+
__section_table_start = .;
41+
__data_section_table = .;
42+
LONG(LOADADDR(.data));
43+
LONG( ADDR(.data));
44+
LONG( SIZEOF(.data));
45+
LONG(LOADADDR(.data_RAM2));
46+
LONG( ADDR(.data_RAM2));
47+
LONG( SIZEOF(.data_RAM2));
48+
LONG(LOADADDR(.data_RAM3));
49+
LONG( ADDR(.data_RAM3));
50+
LONG( SIZEOF(.data_RAM3));
51+
LONG(LOADADDR(.data_RAM4));
52+
LONG( ADDR(.data_RAM4));
53+
LONG( SIZEOF(.data_RAM4));
54+
LONG(LOADADDR(.data_RAM5));
55+
LONG( ADDR(.data_RAM5));
56+
LONG( SIZEOF(.data_RAM5));
57+
__data_section_table_end = .;
58+
__bss_section_table = .;
59+
LONG( ADDR(.bss));
60+
LONG( SIZEOF(.bss));
61+
LONG( ADDR(.bss_RAM2));
62+
LONG( SIZEOF(.bss_RAM2));
63+
LONG( ADDR(.bss_RAM3));
64+
LONG( SIZEOF(.bss_RAM3));
65+
LONG( ADDR(.bss_RAM4));
66+
LONG( SIZEOF(.bss_RAM4));
67+
LONG( ADDR(.bss_RAM5));
68+
LONG( SIZEOF(.bss_RAM5));
69+
__bss_section_table_end = .;
70+
__section_table_end = . ;
71+
/* End of Global Section Table */
72+
1573

16-
__top_RW_MEM = 0x10000000 + 0x8000;
74+
*(.after_vectors*)
75+
76+
} >SPIFI
77+
78+
.text : ALIGN(4)
79+
{
80+
*(.text*)
81+
*(.rodata .rodata.* .constdata .constdata.*)
82+
. = ALIGN(4);
83+
84+
/* C++ constructors etc */
85+
. = ALIGN(4);
86+
KEEP(*(.init))
87+
88+
. = ALIGN(4);
89+
__preinit_array_start = .;
90+
KEEP (*(.preinit_array))
91+
__preinit_array_end = .;
92+
93+
. = ALIGN(4);
94+
__init_array_start = .;
95+
KEEP (*(SORT(.init_array.*)))
96+
KEEP (*(.init_array))
97+
__init_array_end = .;
98+
99+
KEEP(*(.fini));
100+
101+
. = ALIGN(4);
102+
KEEP (*crtbegin.o(.ctors))
103+
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
104+
KEEP (*(SORT(.ctors.*)))
105+
KEEP (*crtend.o(.ctors))
106+
107+
. = ALIGN(4);
108+
KEEP (*crtbegin.o(.dtors))
109+
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
110+
KEEP (*(SORT(.dtors.*)))
111+
KEEP (*crtend.o(.dtors))
112+
/* End C++ */
113+
} > SPIFI
17114

18-
INCLUDE "lpc43xx_dualcore_lib.ld"
19-
INCLUDE "lpc43xx_dualcore.ld"
115+
/*
116+
* for exception handling/unwind - some Newlib functions (in common
117+
* with C++ and STDC++) use this.
118+
*/
119+
.ARM.extab : ALIGN(4)
120+
{
121+
*(.ARM.extab* .gnu.linkonce.armextab.*)
122+
} > SPIFI
123+
__exidx_start = .;
124+
125+
.ARM.exidx : ALIGN(4)
126+
{
127+
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
128+
} > SPIFI
129+
__exidx_end = .;
130+
131+
_etext = .;
132+
133+
134+
/* DATA section for RamLoc72 */
135+
.data_RAM2 : ALIGN(4)
136+
{
137+
FILL(0xff)
138+
*(.ramfunc.$RAM2)
139+
*(.ramfunc.$RamLoc72)
140+
*(.data.$RAM2*)
141+
*(.data.$RamLoc72*)
142+
. = ALIGN(4) ;
143+
} > RamLoc72 AT>SPIFI
144+
145+
/* DATA section for RamAHB32 */
146+
.data_RAM3 : ALIGN(4)
147+
{
148+
FILL(0xff)
149+
*(.ramfunc.$RAM3)
150+
*(.ramfunc.$RamAHB32)
151+
*(.data.$RAM3*)
152+
*(.data.$RamAHB32*)
153+
. = ALIGN(4) ;
154+
} > RamAHB32 AT>SPIFI
155+
156+
/* DATA section for RamAHB16 */
157+
.data_RAM4 : ALIGN(4)
158+
{
159+
FILL(0xff)
160+
*(.ramfunc.$RAM4)
161+
*(.ramfunc.$RamAHB16)
162+
*(.data.$RAM4*)
163+
*(.data.$RamAHB16*)
164+
. = ALIGN(4) ;
165+
} > RamAHB16 AT>SPIFI
166+
167+
/* DATA section for RamAHB_ETB16 */
168+
.data_RAM5 : ALIGN(4)
169+
{
170+
FILL(0xff)
171+
*(.ramfunc.$RAM5)
172+
*(.ramfunc.$RamAHB_ETB16)
173+
*(.data.$RAM5*)
174+
*(.data.$RamAHB_ETB16*)
175+
. = ALIGN(4) ;
176+
} > RamAHB_ETB16 AT>SPIFI
177+
178+
/* MAIN DATA SECTION */
179+
180+
181+
.uninit_RESERVED : ALIGN(4)
182+
{
183+
KEEP(*(.bss.$RESERVED*))
184+
. = ALIGN(4) ;
185+
_end_uninit_RESERVED = .;
186+
} > RamLoc128
187+
188+
189+
/* Main DATA section (RamLoc128) */
190+
.data : ALIGN(4)
191+
{
192+
FILL(0xff)
193+
_data = . ;
194+
*(vtable)
195+
*(.ramfunc*)
196+
*(.data*)
197+
. = ALIGN(4) ;
198+
_edata = . ;
199+
} > RamLoc128 AT>SPIFI
200+
201+
/* BSS section for RamLoc72 */
202+
.bss_RAM2 : ALIGN(4)
203+
{
204+
*(.bss.$RAM2*)
205+
*(.bss.$RamLoc72*)
206+
. = ALIGN(4) ;
207+
} > RamLoc72
208+
/* BSS section for RamAHB32 */
209+
.bss_RAM3 : ALIGN(4)
210+
{
211+
*(.bss.$RAM3*)
212+
*(.bss.$RamAHB32*)
213+
. = ALIGN(4) ;
214+
} > RamAHB32
215+
/* BSS section for RamAHB16 */
216+
.bss_RAM4 : ALIGN(4)
217+
{
218+
*(.bss.$RAM4*)
219+
*(.bss.$RamAHB16*)
220+
. = ALIGN(4) ;
221+
} > RamAHB16
222+
/* BSS section for RamAHB_ETB16 */
223+
.bss_RAM5 : ALIGN(4)
224+
{
225+
*(.bss.$RAM5*)
226+
*(.bss.$RamAHB_ETB16*)
227+
. = ALIGN(4) ;
228+
} > RamAHB_ETB16
229+
230+
/* MAIN BSS SECTION */
231+
.bss : ALIGN(4)
232+
{
233+
_bss = .;
234+
*(.bss*)
235+
*(COMMON)
236+
. = ALIGN(4) ;
237+
_ebss = .;
238+
PROVIDE(end = .);
239+
} > RamLoc128
240+
241+
/* NOINIT section for RamLoc72 */
242+
.noinit_RAM2 (NOLOAD) : ALIGN(4)
243+
{
244+
*(.noinit.$RAM2*)
245+
*(.noinit.$RamLoc72*)
246+
. = ALIGN(4) ;
247+
} > RamLoc72
248+
/* NOINIT section for RamAHB32 */
249+
.noinit_RAM3 (NOLOAD) : ALIGN(4)
250+
{
251+
*(.noinit.$RAM3*)
252+
*(.noinit.$RamAHB32*)
253+
. = ALIGN(4) ;
254+
} > RamAHB32
255+
/* NOINIT section for RamAHB16 */
256+
.noinit_RAM4 (NOLOAD) : ALIGN(4)
257+
{
258+
*(.noinit.$RAM4*)
259+
*(.noinit.$RamAHB16*)
260+
. = ALIGN(4) ;
261+
} > RamAHB16
262+
/* NOINIT section for RamAHB_ETB16 */
263+
.noinit_RAM5 (NOLOAD) : ALIGN(4)
264+
{
265+
*(.noinit.$RAM5*)
266+
*(.noinit.$RamAHB_ETB16*)
267+
. = ALIGN(4) ;
268+
} > RamAHB_ETB16
269+
270+
/* DEFAULT NOINIT SECTION */
271+
.noinit (NOLOAD): ALIGN(4)
272+
{
273+
_noinit = .;
274+
*(.noinit*)
275+
. = ALIGN(4) ;
276+
_end_noinit = .;
277+
} > RamLoc128
278+
279+
PROVIDE(_pvHeapStart = .);
280+
PROVIDE(_vStackTop = __top_RamLoc128 - 0);
281+
}

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