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nRF51822 mbed SDK with working GPIO, RawSerial, and timer
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‎libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_nRF51822/TOOLCHAIN_ARM_STD/nRF51822.sct

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; *************************************************************
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; *** Scatter-Loading Description File generated by uVision ***
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; *************************************************************
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LR_IROM1 0x00000000 0x00040000 {
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ER_IROM1 0x00000000 0x00040000 {
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 0x20000000 0x00004000 {
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.ANY (+RW +ZI)
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}
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}
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‎libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_nRF51822/TOOLCHAIN_ARM_STD/startup_nRF51822.s

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; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
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;
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; The information contained herein is property of Nordic Semiconductor ASA.
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; Terms and conditions of usage are described in detail in NORDIC
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; SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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;
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; Licensees are granted free, non-transferable use of the information. NO
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; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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; the file.
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; NOTE: Template files (including this one) are application specific and therefore
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; expected to be copied into the application project folder prior to its use!
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; Description message
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Stack_Size EQU 2048
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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Heap_Size EQU 2048
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
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DCD RADIO_IRQHandler ;RADIO
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DCD UART0_IRQHandler ;UART0
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DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
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DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
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DCD 0 ;Reserved
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DCD GPIOTE_IRQHandler ;GPIOTE
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DCD ADC_IRQHandler ;ADC
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DCD TIMER0_IRQHandler ;TIMER0
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DCD TIMER1_IRQHandler ;TIMER1
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DCD TIMER2_IRQHandler ;TIMER2
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DCD RTC0_IRQHandler ;RTC0
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DCD TEMP_IRQHandler ;TEMP
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DCD RNG_IRQHandler ;RNG
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DCD ECB_IRQHandler ;ECB
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DCD CCM_AAR_IRQHandler ;CCM_AAR
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DCD WDT_IRQHandler ;WDT
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DCD RTC1_IRQHandler ;RTC1
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DCD QDEC_IRQHandler ;QDEC
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DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
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DCD SWI0_IRQHandler ;SWI0
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DCD SWI1_IRQHandler ;SWI1
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DCD SWI2_IRQHandler ;SWI2
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DCD SWI3_IRQHandler ;SWI3
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DCD SWI4_IRQHandler ;SWI4
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DCD SWI5_IRQHandler ;SWI5
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
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NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =NRF_POWER_RAMON_ADDRESS
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LDR R2, [R0]
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MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
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ORRS R2, R2, R1
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STR R2, [R0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT POWER_CLOCK_IRQHandler [WEAK]
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EXPORT RADIO_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT SPI0_TWI0_IRQHandler [WEAK]
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EXPORT SPI1_TWI1_IRQHandler [WEAK]
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EXPORT GPIOTE_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT RTC0_IRQHandler [WEAK]
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EXPORT TEMP_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT ECB_IRQHandler [WEAK]
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EXPORT CCM_AAR_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT RTC1_IRQHandler [WEAK]
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EXPORT QDEC_IRQHandler [WEAK]
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EXPORT LPCOMP_COMP_IRQHandler [WEAK]
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EXPORT SWI0_IRQHandler [WEAK]
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EXPORT SWI1_IRQHandler [WEAK]
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EXPORT SWI2_IRQHandler [WEAK]
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EXPORT SWI3_IRQHandler [WEAK]
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EXPORT SWI4_IRQHandler [WEAK]
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EXPORT SWI5_IRQHandler [WEAK]
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POWER_CLOCK_IRQHandler
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RADIO_IRQHandler
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UART0_IRQHandler
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SPI0_TWI0_IRQHandler
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SPI1_TWI1_IRQHandler
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GPIOTE_IRQHandler
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ADC_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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RTC0_IRQHandler
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TEMP_IRQHandler
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RNG_IRQHandler
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ECB_IRQHandler
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CCM_AAR_IRQHandler
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WDT_IRQHandler
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RTC1_IRQHandler
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QDEC_IRQHandler
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LPCOMP_COMP_IRQHandler
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SWI0_IRQHandler
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SWI1_IRQHandler
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SWI2_IRQHandler
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SWI3_IRQHandler
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SWI4_IRQHandler
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SWI5_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, = (Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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‎libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_nRF51822/TOOLCHAIN_ARM_STD/sys.cpp

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/* mbed Microcontroller Library - stackheap
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* Setup a fixed single stack/heap memory model,
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* between the top of the RW/ZI region and the stackpointer
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif

‎libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_nRF51822/TOOLCHAIN_ARM_STD/uicr_config.h

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/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
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*
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* The information contained herein is property of Nordic Semiconductor ASA.
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* Terms and conditions of usage are described in detail in NORDIC
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* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information. NO
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* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
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* the file.
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*
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*/
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/* Template files (including this one) are application specific and therefore expected to
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be copied into the application project folder prior to its use! */
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#ifndef _UICR_CONFIG_H
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#define _UICR_CONFIG_H
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/*lint ++flb "Enter library region" */
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#include <stdint.h>
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/*
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* Include this file in your project if you want to include in your compiled code files data
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* for the User Information Configuration Registers (UICR) area; see nRF51 Series Reference
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* Manual chapter User Information Configuration Registers. This file declares one variable
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* per register of the UICR area and informs the linker where to place them. To include
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* the desired value in the desired address, uncomment the variable with the proper address
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* at the target area and update the assignment value.
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*
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* Please note that UICR values are stored in a reserved area of the flash and should only be
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* stored into when downloading a hex file. Do not use these defined variables to store data
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* at run time.
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*
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* Note as well that this file uses one non-standard attribute ("at"). It will only function
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* with the ARMCC compiler toolset.
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*
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* Note that the hex file generated when this file is included will fail to download when using
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* the standard download algorithm provided by Nordic. See example project "uicr_config_example"
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* in any of the board example folders for an example of the recommended download method as well
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* as the documentation that follows with the SDK. nrfjprog can be used as normal.
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*
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* Please note as well that if you are using a SoftDevice the UICR_CLENR0 address will
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* already be in use. Do not uncomment that line.
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*/
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// const uint32_t UICR_CLENR0 __attribute__((at(0x10001000))) __attribute__((used)) = 0xFFFFFFFF; // WARNING: This address might be used by the SoftDevice. Use with care.
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// const uint32_t UICR_RBPCONF __attribute__((at(0x10001004))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_XTALFREQ __attribute__((at(0x10001008))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x80 __attribute__((at(0x10001080))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x84 __attribute__((at(0x10001084))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x88 __attribute__((at(0x10001088))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x8C __attribute__((at(0x1000108C))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x90 __attribute__((at(0x10001090))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x94 __attribute__((at(0x10001094))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x98 __attribute__((at(0x10001098))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0x9C __attribute__((at(0x1000109C))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xA0 __attribute__((at(0x100010A0))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xA4 __attribute__((at(0x100010A4))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xA8 __attribute__((at(0x100010A8))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xAC __attribute__((at(0x100010AC))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xB0 __attribute__((at(0x100010B0))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xB4 __attribute__((at(0x100010B4))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xB8 __attribute__((at(0x100010B8))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xBC __attribute__((at(0x100010BC))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xC0 __attribute__((at(0x100010C0))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xC4 __attribute__((at(0x100010C4))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xC8 __attribute__((at(0x100010C8))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xCC __attribute__((at(0x100010CC))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xD0 __attribute__((at(0x100010D0))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xD4 __attribute__((at(0x100010D4))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xD8 __attribute__((at(0x100010D8))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xDC __attribute__((at(0x100010DC))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xE0 __attribute__((at(0x100010E0))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xE4 __attribute__((at(0x100010E4))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xE8 __attribute__((at(0x100010E8))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xEC __attribute__((at(0x100010EC))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xF0 __attribute__((at(0x100010F0))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xF4 __attribute__((at(0x100010F4))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xF8 __attribute__((at(0x100010F8))) __attribute__((used)) = 0xFFFFFFFF;
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// const uint32_t UICR_ADDR_0xFC __attribute__((at(0x100010FC))) __attribute__((used)) = 0xFFFFFFFF;
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/*lint --flb "Leave library region" */
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#endif //_UICR_CONFIG_H

‎libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_nRF51822/cmsis.h

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/* mbed Microcontroller Library - CMSIS
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* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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*
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* A generic CMSIS include header, pulling in LPC407x_8x specifics
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*/
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#ifndef MBED_CMSIS_H
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#define MBED_CMSIS_H
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#include "nRF51822.h"
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#include "cmsis_nvic.h"
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#endif

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