Skip to content

Commit 50ea398

Browse files
dpgeorgedpgeorge
committed
stm32/boards/NUCLEO_N657X0: Add new board definition files.
Signed-off-by: Damien George <[email protected]>
1 parent 3189e49 commit 50ea398

File tree

8 files changed

+395
-0
lines changed

8 files changed

+395
-0
lines changed

‎ports/stm32/boards/NUCLEO_N657X0/bdev.c‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2025 Damien P. George
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "py/obj.h"
28+
#include "storage.h"
29+
#include "xspi.h"
30+
31+
#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
32+
#error "Cannot enable MICROPY_HW_SPIFLASH_ENABLE_CACHE"
33+
#endif
34+
35+
// External SPI flash uses hardware XSPI interface.
36+
const mp_spiflash_config_t spiflash_config = {
37+
.bus_kind = MP_SPIFLASH_BUS_QSPI,
38+
.bus.u_qspi.data = (void *)&xspi_flash2,
39+
.bus.u_qspi.proto = &xspi_proto,
40+
};
41+
42+
spi_bdev_t spi_bdev;

‎ports/stm32/boards/NUCLEO_N657X0/board.c‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2024-2025 Damien P. George
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "py/mphal.h"
28+
#include "boardctrl.h"
29+
#include "xspi.h"
30+
31+
// Values for OTP fuses for VDDIO3, to select low voltage mode (<2.5V).
32+
// See RM0486, Section 5, Table 18.
33+
#define BSEC_HW_CONFIG_ID (124U)
34+
#define BSEC_HWS_HSLV_VDDIO3 (1U << 15)
35+
36+
static void board_config_vdd(void) {
37+
// TODO: move some of the below code to a common location for all N6 boards?
38+
39+
// Enable PWR, BSEC and SYSCFG clocks.
40+
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
41+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
42+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
43+
44+
// Program high speed IO optimization fuses if they aren't already set.
45+
uint32_t fuse;
46+
BSEC_HandleTypeDef hbsec = { .Instance = BSEC };
47+
const uint32_t mask = BSEC_HWS_HSLV_VDDIO3;
48+
if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
49+
fuse = 0;
50+
} else if ((fuse & mask) != mask) {
51+
// Program the fuse, and read back the set value.
52+
if (HAL_BSEC_OTP_Program(&hbsec, BSEC_HW_CONFIG_ID, fuse | mask, HAL_BSEC_NORMAL_PROG) != HAL_OK) {
53+
fuse = 0;
54+
} else if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
55+
fuse = 0;
56+
}
57+
}
58+
59+
// Enable Vdd ADC, needed for the ADC to work.
60+
LL_PWR_EnableVddADC();
61+
62+
// Configure VDDIO2.
63+
LL_PWR_EnableVddIO2();
64+
LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
65+
SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
66+
67+
// Configure VDDIO3. Only enable 1.8V mode if the fuse is set.
68+
LL_PWR_EnableVddIO3();
69+
if (fuse & BSEC_HWS_HSLV_VDDIO3) {
70+
LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
71+
}
72+
SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
73+
74+
// Configure VDDIO4.
75+
LL_PWR_EnableVddIO4();
76+
LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
77+
SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
78+
79+
// Enable VDD for ADC and USB.
80+
LL_PWR_EnableVddADC();
81+
LL_PWR_EnableVddUSB();
82+
}
83+
84+
void mboot_board_early_init(void) {
85+
board_config_vdd();
86+
xspi_init();
87+
}
88+
89+
void board_early_init(void) {
90+
#if !MICROPY_HW_RUNS_FROM_EXT_FLASH
91+
// Firmware runs directly from SRAM, so configure VDD and enable XSPI flash.
92+
board_config_vdd();
93+
xspi_init();
94+
#endif
95+
}
96+
97+
void board_leave_standby(void) {
98+
// TODO: move some of the below code to a common location for all N6 boards?
99+
100+
// Enable PWR, BSEC and SYSCFG clocks.
101+
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
102+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
103+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
104+
105+
// Configure VDDIO2.
106+
LL_PWR_EnableVddIO2();
107+
LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
108+
SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
109+
110+
// Configure VDDIO3 (1.8V mode selection is retained).
111+
LL_PWR_EnableVddIO3();
112+
SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
113+
114+
// Configure VDDIO4.
115+
LL_PWR_EnableVddIO4();
116+
LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
117+
SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
118+
119+
// Enable VDD for ADC and USB.
120+
LL_PWR_EnableVddADC();
121+
LL_PWR_EnableVddUSB();
122+
}

‎ports/stm32/boards/NUCLEO_N657X0/board.md‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
The mboot bootloader must first be built and deployed to this board. Make sure that
2+
CN9 is in position 1-2 to select STLK as the 5V power source, that JP1 is in position
3+
1-2 (lower position) and JP2 is in position 2-3 (upper position). Then plug in a USB
4+
cable into the ST-LINK port CN10. This will allow mboot firmware to be programmed to
5+
the external SPI flash via ST's tools, eg:
6+
7+
make -C ports/stm32/mboot BOARD=NUCLEO_N657X0 deploy-trusted
8+
9+
Once mboot is installed, change CN9 to position 3-4 to select USB as the 5V power
10+
source, change JP2 back to position 1-2 (lower position) and change the USB cable to
11+
CN8. mboot will present a USB DFU device on this USB port, and the red LED2 should be
12+
blinking at 1Hz to indicate that mboot is active. If it's not active then hold the
13+
USER button and press NRST, and wait until all three LEDs are on, then release USER.
14+
Now mboot will be active.
15+
16+
Once the USB DFU port can be seen, the firmware below can be programmed as usual with
17+
any DFU loader.

‎ports/stm32/boards/NUCLEO_N657X0/mpconfigboard.h‎

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,103 @@
1+
#define MICROPY_HW_BOARD_NAME "NUCLEO-N657X0"
2+
#define MICROPY_HW_MCU_NAME "STM32N657X0"
3+
4+
#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t
5+
#define MICROPY_ALLOC_GC_STACK_SIZE (128)
6+
#define MICROPY_FATFS_EXFAT (1)
7+
8+
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
9+
#define MICROPY_HW_HAS_SWITCH (1)
10+
#define MICROPY_HW_HAS_FLASH (1)
11+
#define MICROPY_HW_ENABLE_RNG (1)
12+
#define MICROPY_HW_ENABLE_RTC (1)
13+
#define MICROPY_HW_ENABLE_DAC (0)
14+
#define MICROPY_HW_ENABLE_USB (1)
15+
#define MICROPY_PY_PYB_LEGACY (0)
16+
17+
#define MICROPY_BOARD_EARLY_INIT board_early_init
18+
#define MICROPY_BOARD_LEAVE_STANDBY board_leave_standby()
19+
20+
// HSE is 48MHz, this gives a CPU frequency of 800MHz.
21+
#define MICROPY_HW_CLK_PLLM (6)
22+
#define MICROPY_HW_CLK_PLLN (100)
23+
#define MICROPY_HW_CLK_PLLP1 (1)
24+
#define MICROPY_HW_CLK_PLLP2 (1)
25+
#define MICROPY_HW_CLK_PLLFRAC (0)
26+
27+
// The LSE is a 32kHz crystal.
28+
#define MICROPY_HW_RTC_USE_LSE (1)
29+
#define MICROPY_HW_RTC_USE_US (1)
30+
31+
// External SPI flash, MX25UM51245GXDI00.
32+
#define MICROPY_HW_XSPIFLASH_SIZE_BITS_LOG2 (29)
33+
34+
// SPI flash, block device config.
35+
#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev)
36+
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev)
37+
#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config)
38+
#define MICROPY_HW_BDEV_SPIFLASH_OFFSET_BYTES (4 * 1024 * 1024)
39+
#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (60 * 1024 * 1024)
40+
41+
// UART buses
42+
#define MICROPY_HW_UART1_TX (pyb_pin_UART1_TX)
43+
#define MICROPY_HW_UART1_RX (pyb_pin_UART1_RX)
44+
#define MICROPY_HW_UART3_TX (pyb_pin_UART3_TX)
45+
#define MICROPY_HW_UART3_RX (pyb_pin_UART3_RX)
46+
#define MICROPY_HW_UART_REPL (PYB_UART_1)
47+
#define MICROPY_HW_UART_REPL_BAUD (115200)
48+
49+
// I2C buses
50+
#define MICROPY_HW_I2C1_SCL (pyb_pin_I2C1_SCL)
51+
#define MICROPY_HW_I2C1_SDA (pyb_pin_I2C1_SDA)
52+
53+
// SPI buses
54+
#define MICROPY_HW_SPI5_NSS (pyb_pin_SPI5_CS)
55+
#define MICROPY_HW_SPI5_SCK (pyb_pin_SPI5_SCK)
56+
#define MICROPY_HW_SPI5_MISO (pyb_pin_SPI5_MISO)
57+
#define MICROPY_HW_SPI5_MOSI (pyb_pin_SPI5_MOSI)
58+
59+
// USER2 is floating, and pressing the button makes the input go high.
60+
#define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON)
61+
#define MICROPY_HW_USRSW_PULL (GPIO_PULLDOWN)
62+
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_RISING)
63+
#define MICROPY_HW_USRSW_PRESSED (1)
64+
65+
// LEDs
66+
#define MICROPY_HW_LED1 (pyb_pin_LED_RED)
67+
#define MICROPY_HW_LED2 (pyb_pin_LED_GREEN)
68+
#define MICROPY_HW_LED3 (pyb_pin_LED_BLUE)
69+
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
70+
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
71+
72+
// USB config
73+
#define MICROPY_HW_USB_HS (1)
74+
#define MICROPY_HW_USB_HS_IN_FS (1)
75+
#define MICROPY_HW_USB_MAIN_DEV (USB_PHY_HS_ID)
76+
77+
/******************************************************************************/
78+
// Bootloader configuration
79+
80+
#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init()
81+
82+
#define MBOOT_SPIFLASH_CS (pyb_pin_XSPIM_P2_CS)
83+
#define MBOOT_SPIFLASH_SCK (pyb_pin_XSPIM_P2_SCK)
84+
#define MBOOT_SPIFLASH_MOSI (pyb_pin_XSPIM_P2_IO0)
85+
#define MBOOT_SPIFLASH_MISO (pyb_pin_XSPIM_P2_IO1)
86+
#define MBOOT_SPIFLASH_ADDR (0x70000000)
87+
#define MBOOT_SPIFLASH_BYTE_SIZE (64 * 1024 * 1024)
88+
#define MBOOT_SPIFLASH_LAYOUT "/0x70000000/16384*4Kg"
89+
#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
90+
#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash)
91+
#define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
92+
93+
/******************************************************************************/
94+
// Function and variable declarations
95+
96+
extern const struct _mp_spiflash_config_t spiflash_config;
97+
extern struct _spi_bdev_t spi_bdev;
98+
99+
void mboot_board_early_init(void);
100+
void mboot_board_entry_init(void);
101+
102+
void board_early_init(void);
103+
void board_leave_standby(void);

‎ports/stm32/boards/NUCLEO_N657X0/mpconfigboard.mk‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
# Without mboot, the main firmware must fit in 512k flash, will be copied to SRAM by
2+
# the hardware bootloader, and will run from SRAM. With mboot, the main firmware can
3+
# be much larger and will run from flash via XSPI in memory-mapped mode.
4+
USE_MBOOT ?= 1
5+
6+
MCU_SERIES = n6
7+
CMSIS_MCU = STM32N657xx
8+
AF_FILE = boards/stm32n657_af.csv
9+
ifeq ($(BUILDING_MBOOT),1)
10+
SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_fsbl.o
11+
else
12+
SYSTEM_FILE = $(STM32LIB_CMSIS_BASE)/Source/Templates/system_stm32$(MCU_SERIES)xx_s.o
13+
endif
14+
STM32_N6_HEADER_VERSION = 2.1
15+
DKEL = $(STM32_CUBE_PROGRAMMER)/bin/ExternalLoader/MX25UM51245G_STM32N6570-NUCLEO.stldr
16+
17+
ifeq ($(USE_MBOOT),1)
18+
LD_FILES = boards/stm32n657x0.ld boards/common_n6_flash.ld
19+
TEXT0_ADDR = 0x70080000
20+
else
21+
LD_FILES = boards/stm32n657x0.ld boards/common_basic.ld
22+
TEXT0_ADDR = 0x34180400
23+
endif
24+
25+
# MicroPython settings
26+
MICROPY_FLOAT_IMPL = double

‎ports/stm32/boards/NUCLEO_N657X0/partition_stm32n657xx.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
// This board does not use any security settings, so can just stay in secure
2+
// mode without configuring the SAU.
3+
4+
static inline void TZ_SAU_Setup(void) {
5+
}

‎ports/stm32/boards/NUCLEO_N657X0/pins.csv‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
D0,PD9
2+
D1,PD8
3+
D2,PD0
4+
D3,PE9
5+
D4,PE0
6+
D5,PE10
7+
D6,PD5
8+
D7,PE11
9+
D8,PD12
10+
D9,PD7
11+
D10,PA3
12+
D11,PG2
13+
D12,PG1
14+
D13,PE15
15+
D14,PC1
16+
D15,PH9
17+
18+
# Ax header pins are connected directly to the following digital IO
19+
A0D,PF5
20+
A1D,PC10
21+
A2D,PF6
22+
A3D,PA2
23+
A4D,PC12
24+
A5D,PH2
25+
26+
# Ax header pins are connected to the following analog IO via an op-amp in voltage-follower mode running at 1.8V
27+
A0,PA8
28+
A1,PA9
29+
A2,PA10
30+
A3,PA12
31+
A4,PF3
32+
A5,PG15
33+
34+
-UART1_TX,PE5
35+
-UART1_RX,PE6
36+
-UART3_TX,PD8
37+
-UART3_RX,PD9
38+
39+
-I2C1_SCL,PH9
40+
-I2C1_SDA,PC1
41+
42+
-SPI5_CS,PA3
43+
-SPI5_SCK,PE15
44+
-SPI5_MISO,PG1
45+
-SPI5_MOSI,PG2
46+
47+
-BUTTON,PC13
48+
LED_BLUE,PG8
49+
LED_RED,PG10
50+
LED_GREEN,PG0
51+
52+
-XSPIM_P2_DQS,PN0
53+
-XSPIM_P2_CS,PN1
54+
-XSPIM_P2_IO0,PN2
55+
-XSPIM_P2_IO1,PN3
56+
-XSPIM_P2_IO2,PN4
57+
-XSPIM_P2_IO3,PN5
58+
-XSPIM_P2_SCK,PN6
59+
-XSPIM_P2_IO4,PN8
60+
-XSPIM_P2_IO5,PN9
61+
-XSPIM_P2_IO6,PN10
62+
-XSPIM_P2_IO7,PN11

0 commit comments

Comments
 (0)