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* @note TX PDM can only be set to the following two upsampling rate configurations:
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* 1: fp = 960, fs = sample_rate / 100, in this case, Fpdm = 128*48000
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* 2: fp = 960, fs = 480, in this case, Fpdm = 128*Fpcm = 128*sample_rate
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* If the pdm receiver do not care the pdm serial clock, it's recommended set Fpdm = 128*48000.
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* Otherwise, the second configuration should be applied.
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*/
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typedefstruct {
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intsample_rate; /*!< I2S PDM sample rate */
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intfp; /*!< I2S PDM TX upsampling paramater. Normally it should be set to 960 */
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intfs; /*!< I2S PDM TX upsampling paramater. When it is set to 480, the pdm clock frequency Fpdm = 128 * sample_rate, when it is set to sample_rate / 100， Fpdm will be fixed to 128*48000 */
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} i2s_pdm_tx_upsample_cfg_t;
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#endif
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/**
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* @brief I2S pin number for i2s_set_pin
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*
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*/
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typedefstruct {
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intmck_io_num; /*!< MCK in out pin*/
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intbck_io_num; /*!< BCK in out pin*/
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intws_io_num; /*!< WS in out pin*/
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intdata_out_num; /*!< DATA out pin*/
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intdata_in_num; /*!< DATA in pin*/
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} i2s_pin_config_t;
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/**
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* @brief I2S driver configuration parameters
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*
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*/
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typedefstruct {
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i2s_mode_tmode; /*!< I2S work mode */
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uint32_tsample_rate; /*!< I2S sample rate */
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i2s_bits_per_sample_tbits_per_sample; /*!< I2S sample bits in one channel */
i2s_comm_format_tcommunication_format; /*!< I2S communication format */
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intintr_alloc_flags; /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */
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intdma_buf_count; /*!< I2S DMA Buffer Count */
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intdma_buf_len; /*!< I2S DMA Buffer Length */
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booluse_apll; /*!< I2S using APLL as main I2S clock, enable it to get accurate clock */
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booltx_desc_auto_clear; /*!< I2S auto clear tx descriptor if there is underflow condition (helps in avoiding noise in case of data unavailability) */
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intfixed_mclk; /*!< I2S using fixed MCLK output. If use_apll = true and fixed_mclk > 0, then the clock output for i2s is fixed and equal to the fixed_mclk value. If fixed_mclk set, mclk_multiple won't take effect */
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i2s_mclk_multiple_tmclk_multiple; /*!< The multiple of I2S master clock(MCLK) to sample rate */
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i2s_bits_per_chan_tbits_per_chan; /*!< I2S total bits in one channel， only take effect when larger than 'bits_per_sample', default '0' means equal to 'bits_per_sample' */
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#ifSOC_I2S_SUPPORTS_TDM
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i2s_channel_tchan_mask; /*!< I2S active channel bit mask, set value in `i2s_channel_t` to enable specific channel, the bit map of active channel can not exceed (0x1<<total_chan). */
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uint32_ttotal_chan; /*!< I2S Total number of channels. If it is smaller than the biggest active channel number, it will be set to this number automatically. */
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boolleft_align; /*!< Set to enable left alignment */
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boolbig_edin; /*!< Set to enable big edin */
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boolbit_order_msb; /*!< Set to enable msb order */
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boolskip_msk; /*!< Set to enable skip mask. If it is enabled, only the data of the enabled channels will be sent, otherwise all data stored in DMA TX buffer will be sent */
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#endif// SOC_I2S_SUPPORTS_TDM
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} i2s_driver_config_t;
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typedefi2s_driver_config_ti2s_config_t; // for backward compatible
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typedefintr_handle_ti2s_isr_handle_t; // for backward compatible
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/**
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* @brief I2S event queue types
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*
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*/
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typedefenum {
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I2S_EVENT_DMA_ERROR,
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I2S_EVENT_TX_DONE, /*!< I2S DMA finish sent 1 buffer*/
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I2S_EVENT_RX_DONE, /*!< I2S DMA finish received 1 buffer*/
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I2S_EVENT_TX_Q_OVF, /*!< I2S DMA sent queue overflow*/
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