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Sir Richard
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[NTOS]: Use SYSTEM_PD_SIZE instead of assuming that this is PAGE_SIZE, since this is not the case on (future) ARM and (current) AMD64 ports.
[NTOS]: Remove some magic numbers in the pool code, using PTE_COUNT, MiAddressToPde, when needed. Also, the expansion code uses PDEs, not PTEs, so differentiate this, because on some systems (ARM), there are different structures for both. [NTOS]: Use MI_WRITE_INVALID_PTE. ARM3 paged pool now works, the expansion bug has been fixed (and the code is more portable). Expect to see it gradually enabled soon. svn path=/trunk/; revision=48939
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reactos/ntoskrnl/mm/ARM3/pagfault.c

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -107,16 +107,11 @@ MiCheckPdeForPagedPool(IN PVOID Address)
107107
#ifdef _M_AMD64
108108
ASSERT(FALSE);
109109
#else
110-
/* This seems to be making the assumption that one PDE is one page long */
111-
C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
112-
113110
//
114111
// Copy it from our double-mapped system page directory
115112
//
116113
InterlockedExchangePte(PointerPde,
117-
MmSystemPagePtes[((ULONG_PTR)PointerPde &
118-
(PAGE_SIZE - 1)) /
119-
sizeof(MMPTE)].u.Long);
114+
MmSystemPagePtes[(ULONG_PTR)PointerPde & (SYSTEM_PD_SIZE - 1)].u.Long);
120115
#endif
121116
}
122117

reactos/ntoskrnl/mm/ARM3/pool.c

Lines changed: 31 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -377,7 +377,10 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
377377
KIRQL OldIrql;
378378
PLIST_ENTRY NextEntry, NextHead, LastHead;
379379
PMMPTE PointerPte, StartPte;
380+
PMMPDE PointerPde;
381+
ULONG EndAllocation;
380382
MMPTE TempPte;
383+
MMPDE TempPde;
381384
PMMPFN Pfn1;
382385
PVOID BaseVa, BaseVaStart;
383386
PMMFREE_POOL_ENTRY FreeEntry;
@@ -409,7 +412,7 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
409412
//
410413
// Get the page bit count
411414
//
412-
i = ((SizeInPages - 1) / 1024) + 1;
415+
i = ((SizeInPages - 1) / PTE_COUNT) + 1;
413416
DPRINT1("Paged pool expansion: %d %x\n", i, SizeInPages);
414417

415418
//
@@ -450,15 +453,15 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
450453
}
451454

452455
//
453-
// Get the template PTE we'll use to expand
456+
// Get the template PDE we'll use to expand
454457
//
455-
TempPte = ValidKernelPte;
458+
TempPde = ValidKernelPde;
456459

457460
//
458461
// Get the first PTE in expansion space
459462
//
460-
PointerPte = MmPagedPoolInfo.NextPdeForPagedPoolExpansion;
461-
BaseVa = MiPteToAddress(PointerPte);
463+
PointerPde = MmPagedPoolInfo.NextPdeForPagedPoolExpansion;
464+
BaseVa = MiPteToAddress(PointerPde);
462465
BaseVaStart = BaseVa;
463466

464467
//
@@ -470,11 +473,13 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
470473
//
471474
// It should not already be valid
472475
//
473-
ASSERT(PointerPte->u.Hard.Valid == 0);
476+
ASSERT(PointerPde->u.Hard.Valid == 0);
474477

475478
/* Request a page */
479+
DPRINT1("Requesting %d PDEs\n", i);
476480
PageFrameNumber = MiRemoveAnyPage(MI_GET_NEXT_COLOR());
477-
TempPte.u.Hard.PageFrameNumber = PageFrameNumber;
481+
TempPde.u.Hard.PageFrameNumber = PageFrameNumber;
482+
DPRINT1("We have a PDE: %lx\n", PageFrameNumber);
478483

479484
#if (_MI_PAGING_LEVELS >= 3)
480485
/* On PAE/x64 systems, there's no double-buffering */
@@ -483,38 +488,38 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
483488
//
484489
// Save it into our double-buffered system page directory
485490
//
486-
/* This seems to be making the assumption that one PDE is one page long */
487-
C_ASSERT(PAGE_SIZE == (PD_COUNT * (sizeof(MMPTE) * PDE_COUNT)));
488-
MmSystemPagePtes[(ULONG_PTR)PointerPte & (PAGE_SIZE - 1) /
489-
sizeof(MMPTE)] = TempPte;
490-
491+
MmSystemPagePtes[(ULONG_PTR)PointerPde & (SYSTEM_PD_SIZE - 1)] = TempPde;
492+
491493
/* Initialize the PFN */
492494
MiInitializePfnForOtherProcess(PageFrameNumber,
493-
PointerPte,
494-
MmSystemPageDirectory[(PointerPte - (PMMPTE)PDE_BASE) / PDE_COUNT]);
495+
PointerPde,
496+
MmSystemPageDirectory[(PointerPde - MiAddressToPde(NULL)) / PDE_COUNT]);
495497

496-
/* Write the actual PTE now */
497-
MI_WRITE_VALID_PTE(PointerPte++, TempPte);
498+
/* Write the actual PDE now */
499+
MI_WRITE_VALID_PTE(PointerPde, TempPde);
498500
#endif
499501
//
500502
// Move on to the next expansion address
501503
//
504+
PointerPde++;
502505
BaseVa = (PVOID)((ULONG_PTR)BaseVa + PAGE_SIZE);
503-
} while (--i > 0);
506+
i--;
507+
} while (i > 0);
504508

505509
//
506510
// Release the PFN database lock
507511
//
508512
KeReleaseQueuedSpinLock(LockQueuePfnLock, OldIrql);
509-
513+
510514
//
511515
// These pages are now available, clear their availablity bits
512516
//
517+
EndAllocation = (MmPagedPoolInfo.NextPdeForPagedPoolExpansion -
518+
MiAddressToPte(MmPagedPoolInfo.FirstPteForPagedPool)) *
519+
PTE_COUNT;
513520
RtlClearBits(MmPagedPoolInfo.PagedPoolAllocationMap,
514-
(MmPagedPoolInfo.NextPdeForPagedPoolExpansion -
515-
MiAddressToPte(MmPagedPoolInfo.FirstPteForPagedPool)) *
516-
1024,
517-
SizeInPages * 1024);
521+
EndAllocation,
522+
SizeInPages * PTE_COUNT);
518523

519524
//
520525
// Update the next expansion location
@@ -553,7 +558,8 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
553558
// Update the end bitmap so we know the bounds of this allocation when
554559
// the time comes to free it
555560
//
556-
RtlSetBit(MmPagedPoolInfo.EndOfPagedPoolBitmap, i + SizeInPages - 1);
561+
EndAllocation = i + SizeInPages - 1;
562+
RtlSetBit(MmPagedPoolInfo.EndOfPagedPoolBitmap, EndAllocation);
557563

558564
//
559565
// Now we can release the lock (it mainly protects the bitmap)
@@ -583,9 +589,8 @@ MiAllocatePoolPages(IN POOL_TYPE PoolType,
583589
//
584590
// Write the demand zero PTE and keep going
585591
//
586-
ASSERT(PointerPte->u.Hard.Valid == 0);
587-
*PointerPte++ = TempPte;
588-
} while (PointerPte < StartPte);
592+
MI_WRITE_INVALID_PTE(PointerPte, TempPte);
593+
} while (++PointerPte < StartPte);
589594

590595
//
591596
// Return the allocation address to the caller

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