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- Add an OLPC-specific pci-hack: some of its "PCI" devices are in fact not accessible via usual pci configuration space read/write mechanism, so a simulation should be done. The olpcpci.c file is taken from OLPC's dev.laptop.org tree, and modified by me.
- USB driver now finds the EHCI controller, but still some problems. svn path=/branches/olpc/; revision=27787
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‎hal/halx86/generic/generic.rbuild

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Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@
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<file>dma.c</file>
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<file>drive.c</file>
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<file>misc.c</file>
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<file>olpcpci.c</file>
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<file>pci.c</file>
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<file>portio.c</file>
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<file>profil.c</file>

‎hal/halx86/generic/olpcpci.c

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@@ -0,0 +1,294 @@
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/*
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* olpcpci.c - Low-level PCI config space access for OLPC systems
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* without the VSA PCI virtualization software.
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*
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* The AMD Geode chipset (GX2 processor, cs5536 I/O companion device)
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* has some I/O functions (display, southbridge, sound, USB HCIs, etc)
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* that more or less behave like PCI devices, but the hardware doesn't
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* directly implement the PCI configuration space headers. AMD provides
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* "VSA" (Virtual System Architecture) software that emulates PCI config
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* space for these devices, by trapping I/O accesses to PCI config register
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* (CF8/CFC) and running some code in System Management Mode interrupt state.
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* On the OLPC platform, we don't want to use that VSA code because
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* (a) it slows down suspend/resume, and (b) recompiling it requires special
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* compilers that are hard to get. So instead of letting the complex VSA
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* code simulate the PCI config registers for the on-chip devices, we
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* just simulate them the easy way, by inserting the code into the
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* pci_write_config and pci_read_config path. Most of the config registers
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* are read-only anyway, so the bulk of the simulation is just table lookup.
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*/
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//#include <linux/pci.h>
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//#include <linux/init.h>
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//#include <asm/olpc.h>
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//#include <asm/geode.h>
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//#include "pci.h"
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/* INCLUDES ******************************************************************/
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#include <hal.h>
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#define NDEBUG
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#include <debug.h>
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/* GLOBALS *******************************************************************/
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static int is_lx = FALSE; //FIXME: Support LX too!
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#define PCI_SLOT(dev, fn) ((((fn) & 0x7) << 5) | ((dev) & 0x1F))
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/*
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* In the tables below, the first two line (8 longwords) are the
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* size masks that are used when the higher level PCI code determines
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* the size of the region by writing ~0 to a base address register
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* and reading back the result.
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*
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* The following lines are the values that are read during normal
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* PCI config access cycles, i.e. not after just having written
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* ~0 to a base address register.
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*/
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static const ULONG lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x281022 , 0x2200005 , 0x6000021 , 0x80f808 , /* AMD Vendor ID */
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0x0 , 0x0 , 0x0 , 0x0 , /* No virtual registers, hence no BAR for them */
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0x0 , 0x0 , 0x0 , 0x28100b ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
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static const ULONG gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
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0xfffffffd , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x28100b , 0x2200005 , 0x6000021 , 0x80f808 , /* NSC Vendor ID */
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0xac1d , 0x0 , 0x0 , 0x0 , /* I/O BAR - base of virtual registers */
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0x0 , 0x0 , 0x0 , 0x28100b ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
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static const ULONG lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
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0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x20811022 , 0x2200003 , 0x3000000 , 0x0 , /* AMD Vendor ID */
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0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */
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0xfe00c000 , 0x0 , 0x0 , 0x30100b , /* VIP */
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0x0 , 0x0 , 0x0 , 0x10e , /* INTA, IRQ14 for graphics accel */
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
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static const ULONG gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
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0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x30100b , 0x2200003 , 0x3000000 , 0x0 , /* NSC Vendor ID */
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0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */
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0x0 , 0x0 , 0x0 , 0x30100b ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
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static const ULONG aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */
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0xffffc000 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x20821022 , 0x2a00006 , 0x10100000 , 0x8 , /* NSC Vendor ID */
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0xfe010000 , 0x0 , 0x0 , 0x0 , /* AES registers */
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0x0 , 0x0 , 0x0 , 0x20821022 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
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static const ULONG isa_hdr[] = { /* dev f function 0 - devfn = 78 */
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0xfffffff9 , 0xffffff01 , 0xffffffc1 , 0xffffffe1 ,
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0xffffff81 , 0xffffffc1 , 0x0 , 0x0 ,
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0x20901022 , 0x2a00049 , 0x6010003 , 0x802000 ,
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0x18b1 , 0x1001 , 0x1801 , 0x1881 , /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */
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0x1401 , 0x1841 , 0x0 , 0x20901022 , /* PMS-128 ACPI-64 */
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0xaa5b , /* interrupt steering */
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
128+
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static const ULONG ac97_hdr[] = { /* dev f function 3 - devfn = 7b */
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0xffffff81 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x20931022 , 0x2a00041 , 0x4010001 , 0x0 ,
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0x1481 , 0x0 , 0x0 , 0x0 , /* I/O BAR-128 */
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0x0 , 0x0 , 0x0 , 0x20931022 ,
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0x0 , 0x0 , 0x0 , 0x205 , /* IntB , IRQ5 */
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
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static const ULONG ohci_hdr[] = { /* dev f function 4 - devfn = 7c */
143+
0xfffff000 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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146+
0x20941022 , 0x2300006 , 0xc031002 , 0x0 ,
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0xfe01a000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */
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0x0 , 0x0 , 0x0 , 0x20941022 ,
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0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */
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0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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};
154+
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static const ULONG ehci_hdr[] = { /* dev f function 5 - devfn = 7d */
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0xfffff000 , 0x0 , 0x0 , 0x0 ,
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0x0 , 0x0 , 0x0 , 0x0 ,
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0x20951022 , 0x2300006 , 0xc032002 , 0x0 ,
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0xfe01b000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */
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0x0 , 0x0 , 0x0 , 0x20951022 ,
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0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */
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0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */
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#if 0
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0x1 , 0x40080000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */
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#endif
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0x01000001 , 0x00000000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */
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0x2020 , 0x0 , 0x0 , 0x0 , /* (EHCI page 8) 60 SBRN (R/O), 61 FLADJ (R/W), PORTWAKECAP */
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};
170+
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static ULONG ff_loc = ~0;
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static ULONG zero_loc = 0;
173+
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static int bar_probing = 0; /* Set after a write of ~0 to a BAR */
175+
176+
static ULONG *hdr_addr(const ULONG *hdr, int reg)
177+
{
178+
ULONG addr;
179+
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/*
181+
* This is a little bit tricky. The header maps consist of
182+
* 0x20 bytes of size masks, followed by 0x70 bytes of header data.
183+
* In the normal case, when not probing a BAR's size, we want
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* to access the header data, so we add 0x20 to the reg offset,
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* thus skipping the size mask area.
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* In the BAR probing case, we want to access the size mask for
187+
* the BAR, so we subtract 0x10 (the config header offset for
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* BAR0), and don't skip the size mask area.
189+
*/
190+
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addr = (ULONG)hdr + reg + (bar_probing ? -0x10 : 0x20);
192+
193+
if ( ((ULONG)addr - (ULONG)hdr) >= 0x90 )
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{
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DPRINT1("WARNING: out of bounds access: 0x%x, bar_probing %d, offset 0x%x\n",
196+
(ULONG)addr - (ULONG)hdr, bar_probing, reg);
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}
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bar_probing = 0;
200+
return (ULONG *)addr;
201+
}
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VOID NTAPI
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pci_olpc_read(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value)
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{
206+
ULONG *addr;
207+
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/*
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* No device has config registers past 0x70, so we save table space
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* by not storing entries for the nonexistent registers
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*/
212+
if (reg >= 0x70)
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{
214+
addr = &zero_loc;
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}
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else
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{
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if (devfn.u.bits.DeviceNumber == 1)
219+
{
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switch (devfn.u.bits.FunctionNumber)
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{
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case 0 /* 0x8*/:
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addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg);
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break;
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case 1 /*0x9*/:
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addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg);
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break;
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case 2 /* 0xa*/:
229+
addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc;
230+
break;
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default:
232+
addr = &ff_loc;
233+
break;
234+
}
235+
}
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else
237+
if (devfn.u.bits.DeviceNumber == 0xF)
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{
239+
switch (devfn.u.bits.FunctionNumber)
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{
241+
case 0 /*0x78*/:
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addr = hdr_addr(isa_hdr, reg);
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break;
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case 3 /*0x7b*/:
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addr = hdr_addr(ac97_hdr, reg);
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break;
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case 4 /*0x7c*/:
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addr = hdr_addr(ohci_hdr, reg);
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break;
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case 5 /*0x7d*/:
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addr = hdr_addr(ehci_hdr, reg);
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break;
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default:
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addr = &zero_loc;
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break;
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}
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}
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else
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{
260+
addr = &ff_loc;
261+
}
262+
}
263+
264+
ASSERT(len == 1 || len == 2 || len == 4)
265+
RtlCopyMemory(value, addr, len);
266+
}
267+
268+
VOID NTAPI
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pci_olpc_write(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value)
270+
{
271+
/* XXX we may want to extend this to simulate EHCI power management */
272+
273+
/*
274+
* Mostly we just discard writes, but if the write is a size probe
275+
* (i.e. writing ~0 to a BAR), we remember it and arrange to return
276+
* the appropriate size mask on the next read. This is cheating
277+
* to some extent, because it depends on the fact that the next
278+
* access after such a write will always be a read to the same BAR.
279+
*/
280+
281+
if ((reg >= 0x10) && (reg < 0x2c)) {
282+
/* Write is to a BAR */
283+
if (*(PULONG)value == ~0)
284+
bar_probing = 1;
285+
} else {
286+
/*
287+
* No warning on writes to ROM BAR, CMD, LATENCY_TIMER,
288+
* CACHE_LINE_SIZE, or PM registers.
289+
*/
290+
if ((reg != 0x30) && (reg != 0x04) && (reg != 0x0d) &&
291+
(reg != 0x0c) && (reg != 0x44))
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DbgPrint("OLPC PCI: Config write to devfn %x reg %x value %x\n", devfn, reg, *value);
293+
}
294+
}

‎hal/halx86/generic/pci.c

Lines changed: 28 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,10 @@ ULONG HalpMinPciBus, HalpMaxPciBus;
1919
KSPIN_LOCK HalpPCIConfigLock;
2020
PCI_CONFIG_HANDLER PCIConfigHandler;
2121

22+
#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */
23+
#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */
24+
#define OLPC_SIMULATED(bus, devfn) ( ( (bus) == 0 ) && ( (devfn.u.bits.DeviceNumber == NB_SLOT) || (devfn.u.bits.DeviceNumber == SB_SLOT) ) )
25+
2226
/* PCI Operation Matrix */
2327
UCHAR PCIDeref[4][4] =
2428
{
@@ -107,6 +111,10 @@ BUS_HANDLER HalpFakePciBusHandler =
107111
NULL
108112
};
109113

114+
VOID NTAPI pci_olpc_read(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value);
115+
VOID NTAPI pci_olpc_write(ULONG bus, PCI_SLOT_NUMBER devfn, ULONG reg, ULONG len, PUCHAR value);
116+
117+
110118
/* TYPE 1 FUNCTIONS **********************************************************/
111119

112120
VOID
@@ -234,11 +242,26 @@ HalpPCIConfig(IN PBUS_HANDLER BusHandler,
234242
/* Find out the type of read/write we need to do */
235243
i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
236244

237-
/* Do the read/write and return the number of bytes */
238-
i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
239-
State,
240-
Buffer,
241-
Offset);
245+
if (OLPC_SIMULATED(BusHandler->BusNumber, Slot))
246+
{
247+
/* Convert 0->ulong, 1->char, 2->short */
248+
if (i == 0)
249+
i = 4;
250+
251+
/* FIXME: Not really a good way to know if it's read or write... */
252+
if (ConfigIO == PCIConfigHandler.ConfigRead)
253+
pci_olpc_read(BusHandler->BusNumber, Slot, Offset, i, (PUCHAR)Buffer);
254+
else
255+
pci_olpc_write(BusHandler->BusNumber, Slot, Offset, i, (PUCHAR)Buffer);
256+
}
257+
else
258+
{
259+
/* Do the read/write and return the number of bytes */
260+
i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
261+
State,
262+
Buffer,
263+
Offset);
264+
}
242265

243266
/* Increment the buffer position and offset, and decrease the length */
244267
Offset += i;

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