test for assignment statement with multiple assignments

Author: kroening

regression/verilog/assignments/assignment_statement1.sv

@@ -0,0 +1,9 @@
+module main;
+
+  wire [31:0] x, y;
+
+  assign x = 1, y = 2;
+
+  assert final (x == 1 && y == 2);
+
+endmodule