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Verilog: use zero_extend_exprt
This replaces two typecasts by zero_extend_exprt.
1 parent e565db7 commit b777433

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6 files changed

+51
-15
lines changed

6 files changed

+51
-15
lines changed

src/verilog/aval_bval_encoding.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -470,3 +470,8 @@ exprt aval_bval(const shift_exprt &expr)
470470
auto x = make_x(expr.type());
471471
return if_exprt{distance_has_xz, x, combined};
472472
}
473+
474+
exprt aval_bval(const zero_extend_exprt &expr)
475+
{
476+
abort();
477+
}

src/verilog/aval_bval_encoding.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,5 +65,7 @@ exprt aval_bval(const verilog_implies_exprt &);
6565
exprt aval_bval(const typecast_exprt &);
6666
/// lowering for shifts
6767
exprt aval_bval(const shift_exprt &);
68+
/// lowering for zero extension
69+
exprt aval_bval(const zero_extend_exprt &);
6870

6971
#endif

src/verilog/expr2verilog.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -896,6 +896,25 @@ expr2verilogt::resultt expr2verilogt::convert_explicit_size_cast(
896896

897897
/*******************************************************************\
898898
899+
Function: expr2verilogt::convert_zero_extend
900+
901+
Inputs:
902+
903+
Outputs:
904+
905+
Purpose:
906+
907+
\*******************************************************************/
908+
909+
expr2verilogt::resultt
910+
expr2verilogt::convert_zero_extend(const zero_extend_exprt &src)
911+
{
912+
// added by the type checker; igore
913+
return convert_rec(src.op());
914+
}
915+
916+
/*******************************************************************\
917+
899918
Function: expr2verilogt::convert_index
900919
901920
Inputs:
@@ -1664,6 +1683,9 @@ expr2verilogt::resultt expr2verilogt::convert_rec(const exprt &src)
16641683
else if(src.id()==ID_typecast)
16651684
return convert_typecast(to_typecast_expr(src));
16661685

1686+
else if(src.id() == ID_zero_extend)
1687+
return convert_zero_extend(to_zero_extend_expr(src));
1688+
16671689
else if(src.id()==ID_and)
16681690
return convert_binary(
16691691
to_multi_ary_expr(src), "&&", precedence = verilog_precedencet::AND);

src/verilog/expr2verilog_class.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,8 @@ class expr2verilogt
117117

118118
resultt convert_typecast(const typecast_exprt &);
119119

120+
resultt convert_zero_extend(const zero_extend_exprt &);
121+
120122
resultt
121123
convert_explicit_size_cast(const class verilog_explicit_size_cast_exprt &);
122124

src/verilog/verilog_lowering.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -615,6 +615,20 @@ exprt verilog_lowering(exprt expr)
615615
else
616616
return expr;
617617
}
618+
else if(expr.id() == ID_zero_extend)
619+
{
620+
auto &zero_extend = to_zero_extend_expr(expr);
621+
622+
if(
623+
is_four_valued(zero_extend.type()) ||
624+
is_four_valued(zero_extend.op().type()))
625+
{
626+
// encode into aval/bval
627+
return aval_bval(zero_extend);
628+
}
629+
else
630+
return expr; // leave as is
631+
}
618632
else
619633
return expr; // leave as is
620634

src/verilog/verilog_typecheck_expr.cpp

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2316,23 +2316,14 @@ Function: zero_extend
23162316

23172317
static exprt zero_extend(const exprt &expr, const typet &type)
23182318
{
2319-
auto old_width = expr.type().id() == ID_bool ? 1
2320-
: expr.type().id() == ID_integer
2321-
? 32
2322-
: to_bitvector_type(expr.type()).get_width();
2319+
exprt result = expr;
23232320

2324-
// first make unsigned
2325-
typet tmp_type;
2321+
if(expr.type().id() == ID_bool)
2322+
result = typecast_exprt{expr, unsignedbv_typet{1}};
2323+
else if(expr.type().id() == ID_integer)
2324+
result = typecast_exprt{expr, unsignedbv_typet{32}};
23262325

2327-
if(type.id() == ID_unsignedbv)
2328-
tmp_type = unsignedbv_typet{old_width};
2329-
else if(type.id() == ID_verilog_unsignedbv)
2330-
tmp_type = verilog_unsignedbv_typet{old_width};
2331-
else
2332-
PRECONDITION(false);
2333-
2334-
return typecast_exprt::conditional_cast(
2335-
typecast_exprt::conditional_cast(expr, tmp_type), type);
2326+
return zero_extend_exprt{std::move(result), type};
23362327
}
23372328

23382329
/*******************************************************************\

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