SystemVerilog: fixup for #952

Author: kroening

regression/verilog/packages/package_typedef1.desc

@@ -1,8 +1,7 @@
-KNOWNBUG
+CORE
 package_typedef1.sv
 
 ^EXIT=0$
 ^SIGNAL=0$
 --
 --
-Support for typedefs in packages is missing.

src/verilog/parser.y

@@ -1551,7 +1551,7 @@ data_type:
                   $$ = $2; }
 	| package_scope type_identifier packed_dimension_brace
 		{ mto($1, $2);
-		  add_as_subtype(stack_type($3), stack_type($2));
+		  add_as_subtype(stack_type($3), stack_type($1));
 		  $$ = $3; }
 //	| class_type
 	| TOK_EVENT