symbol_table API

Author: Daniel Kroening

src/verilog/verilog_interfaces.cpp

@@ -177,7 +177,9 @@ void verilog_typecheckt::interface_ports(irept::subt &ports)
 
   // check that all declared ports are also in the port list
 
-  forall_symbol_module_map(it, symbol_table.symbol_module_map, module_identifier)
+  for(auto it=symbol_table.symbol_module_map.lower_bound(module_identifier);
+           it!=symbol_table.symbol_module_map.upper_bound(module_identifier);
+           it++)
   {
     const symbolt &symbol=ns.lookup(it->second);
 
@@ -265,7 +267,7 @@ void verilog_typecheckt::interface_function_or_task(
 
     return_symbol.pretty_name=strip_verilog_prefix(return_symbol.name);
 
-    symbol_table.move(return_symbol);
+    symbol_table.add(return_symbol);
   }
 
   // do the declarations within the task/function
@@ -419,10 +421,9 @@ void verilog_typecheckt::interface_function_or_task_decl(const verilog_declt &de
       // in Verilog terminology, but inputs and outputs.
       // We'll use the C terminology, and call them parameters.
       // Not to be confused with module parameters.
-      symbol_tablet::symbolst::iterator s_it=
-        symbol_table.symbols.find(function_or_task_name);
-      assert(s_it!=symbol_table.symbols.end());
-      symbolt &function_or_task_symbol=s_it->second;
+      auto s_it=symbol_table.get_writeable(function_or_task_name);
+      CHECK_RETURN(s_it!=nullptr);
+      symbolt &function_or_task_symbol=*s_it;
       code_typet::parameterst &parameters=
         to_code_type(function_or_task_symbol.type).parameters();
       parameters.push_back(code_typet::parametert());
@@ -434,7 +435,7 @@ void verilog_typecheckt::interface_function_or_task_decl(const verilog_declt &de
       parameter.set(ID_input, input);
     }
 
-    symbol_tablet::symbolst::iterator result=
+    symbol_tablet::symbolst::const_iterator result=
       symbol_table.symbols.find(symbol.name);
 
     if(result!=symbol_table.symbols.end())
@@ -584,16 +585,15 @@ void verilog_typecheckt::interface_module_decl(
     symbol.pretty_name=
       strip_verilog_prefix(symbol.name);
 
-    symbol_tablet::symbolst::iterator result=
-      symbol_table.symbols.find(symbol.name);
+    auto result=symbol_table.get_writeable(symbol.name);
 
-    if(result==symbol_table.symbols.end())
+    if(result==nullptr)
     {
       symbol_table.add(symbol);
     }
     else
     {
-      symbolt &osymbol=result->second;
+      symbolt &osymbol=*result;
 
       if(osymbol.type.id()==ID_code)
       {

src/verilog/verilog_symbol_table.cpp

@@ -22,10 +22,10 @@ Function: verilog_symbol_tablet::symbol_table_lookup
 
 symbolt &verilog_symbol_tablet::symbol_table_lookup(const irep_idt &identifier)
 {
-  symbol_tablet::symbolst::iterator it=symbol_table.symbols.find(identifier);
+  auto it=symbol_table.get_writeable(identifier);
 
-  if(it==symbol_table.symbols.end())
+  if(it==nullptr)
     throw "symbol "+id2string(identifier)+" not found";
 
-  return it->second;
+  return *it;
 }

src/verilog/verilog_synthesis.cpp

@@ -603,7 +603,7 @@ void verilog_synthesist::replace_by_wire(
   assignment.next.value=what;
   new_wires.insert(new_symbol.name);
 
-  if(symbol_table.move(new_symbol))
+  if(symbol_table.add(new_symbol))
   {
     error() << "failed to add replace_by_wire symbol" << eom;
     throw 0;
@@ -783,7 +783,7 @@ Function: verilog_synthesist::assignment_symbol
 
 \*******************************************************************/
 
-symbolt &verilog_synthesist::assignment_symbol(const exprt &lhs)
+const symbolt &verilog_synthesist::assignment_symbol(const exprt &lhs)
 {
   const exprt *e=&lhs;
 
@@ -831,7 +831,7 @@ symbolt &verilog_synthesist::assignment_symbol(const exprt &lhs)
 
       const irep_idt &identifier=e->get(ID_identifier);
 
-      symbol_tablet::symbolst::iterator it=
+      symbol_tablet::symbolst::const_iterator it=
         symbol_table.symbols.find(identifier);
 
       if(it==symbol_table.symbols.end())
@@ -1248,7 +1248,9 @@ void verilog_synthesist::expand_module_instance(
 
   std::list<irep_idt> new_symbols;
 
-  forall_symbol_module_map(it, symbol_table.symbol_module_map, symbol.module)
+  for(auto it=symbol_table.symbol_module_map.lower_bound(symbol.module);
+      it!=symbol_table.symbol_module_map.upper_bound(symbol.module);
+      it++)
   {
     const symbolt &symbol=ns.lookup(it->second);
 
@@ -1619,7 +1621,7 @@ void verilog_synthesist::synth_force_rec(
 
   // get symbol
 
-  symbolt &symbol=assignment_symbol(lhs);
+  const symbolt &symbol=assignment_symbol(lhs);
 
   assignmentt &assignment=assignments[symbol.name];
 
@@ -2950,7 +2952,9 @@ void verilog_synthesist::convert_module_items(symbolt &symbol)
 
   // find out about symbols of this module
 
-  forall_symbol_module_map(it, symbol_table.symbol_module_map, module)
+  for(auto it=symbol_table.symbol_module_map.lower_bound(module);
+      it!=symbol_table.symbol_module_map.upper_bound(module);
+      it++)
     local_symbols.insert(it->second);
 
   // now convert the module items

src/verilog/verilog_synthesis_class.h

@@ -185,7 +185,7 @@ class verilog_synthesist:
     exprt &rhs,
     exprt &new_value);
 
-  symbolt &assignment_symbol(const exprt &lhs);
+  const symbolt &assignment_symbol(const exprt &lhs);
 
   void assignment_member_rec(
     const exprt &lhs,