Verilog: package imports

Author: kroening

regression/verilog/package/package1.desc renamed to regression/verilog/packages/package1.desc

@@ -3,4 +3,5 @@ package my_pkg;
 endpackage
 
 module main;
+  import my_pkg::*;
 endmodule

regression/verilog/package/package1.sv renamed to regression/verilog/packages/package1.sv

@@ -139,8 +139,10 @@ IREP_ID_ONE(iff)
 IREP_ID_ONE(offset)
 IREP_ID_ONE(xnor)
 IREP_ID_ONE(specify)
-IREP_ID_ONE(verilog_module)
 IREP_ID_ONE(verilog_empty_item)
+IREP_ID_ONE(verilog_import_item)
+IREP_ID_ONE(verilog_module)
+IREP_ID_ONE(verilog_package_import)
 IREP_ID_ONE(module_source)
 IREP_ID_ONE(module_items)
 IREP_ID_ONE(parameter_port_list)

src/hw_cbmc_irep_ids.h

@@ -662,31 +662,33 @@ module_nonansi_header:
 	  attribute_instance_brace
 	  module_keyword
 	  module_identifier_with_scope
+	  package_import_declaration_brace
 	  parameter_port_list_opt
 	  list_of_ports_opt ';'
           {
             init($$); stack_expr($$).operands().resize(5);
             stack_expr($$).operands()[0].swap(stack_expr($1));
             stack_expr($$).operands()[1].swap(stack_expr($2));
             stack_expr($$).operands()[2].swap(stack_expr($3));
-            stack_expr($$).operands()[3].swap(stack_expr($4));
-            stack_expr($$).operands()[4].swap(stack_expr($5));
+            stack_expr($$).operands()[3].swap(stack_expr($5));
+            stack_expr($$).operands()[4].swap(stack_expr($6));
           }
         ;
 
 module_ansi_header:
           attribute_instance_brace
 	  module_keyword
 	  module_identifier_with_scope
+	  package_import_declaration_brace
 	  parameter_port_list_opt
 	  list_of_port_declarations ';'
           {
             init($$); stack_expr($$).operands().resize(5);
             stack_expr($$).operands()[0].swap(stack_expr($1));
             stack_expr($$).operands()[1].swap(stack_expr($2));
             stack_expr($$).operands()[2].swap(stack_expr($3));
-            stack_expr($$).operands()[3].swap(stack_expr($4));
-            stack_expr($$).operands()[4].swap(stack_expr($5));
+            stack_expr($$).operands()[3].swap(stack_expr($5));
+            stack_expr($$).operands()[4].swap(stack_expr($6));
           }
         ;
 
@@ -1165,6 +1167,33 @@ data_declaration:
 		  addswap($$, ID_type, $2);
 		  swapop($$, $3); }
 	| type_declaration
+	| package_import_declaration
+	;
+
+package_import_declaration_brace:
+	  /* Optional */
+		{ init($$); }
+	| package_import_declaration_brace package_import_declaration
+		{ $$ = $1; mts($$, $2); }
+	;
+
+package_import_declaration:
+	  TOK_IMPORT package_import_item_brace ';'
+		{ init($$, ID_verilog_package_import); swapop($$, $2); }
+	;
+
+package_import_item_brace:
+	  package_import_item
+		{ init($$); mts($$, $1); }
+	| package_import_item_brace ',' package_import_item
+		{ $$ = $1; mts($$, $3); }
+	;
+
+package_import_item:
+	  package_identifier "::" identifier
+		{ init($$, ID_verilog_import_item); mto($$, $1); mto($$, $3); }
+	| package_identifier "::" "*"
+		{ init($$, ID_verilog_import_item); mto($$, $1); }
 	;
 
 genvar_declaration:

src/verilog/parser.y

@@ -778,6 +778,9 @@ void verilog_typecheckt::collect_symbols(
   else if(module_item.id() == ID_verilog_empty_item)
   {
   }
+  else if(module_item.id() == ID_verilog_package_import)
+  {
+  }
   else
     DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());
 }

src/verilog/verilog_elaborate.cpp

@@ -284,6 +284,9 @@ void verilog_typecheckt::interface_module_item(
   else if(module_item.id() == ID_verilog_empty_item)
   {
   }
+  else if(module_item.id() == ID_verilog_package_import)
+  {
+  }
   else
   {
     DATA_INVARIANT(false, "unexpected module item: " + module_item.id_string());

src/verilog/verilog_interfaces.cpp

@@ -2684,6 +2684,10 @@ void verilog_synthesist::synth_module_item(
   else if(module_item.id() == ID_verilog_empty_item)
   {
   }
+  else if(module_item.id() == ID_verilog_package_import)
+  {
+    // done already
+  }
   else
   {
     throw errort().with_location(module_item.source_location())

src/verilog/verilog_synthesis.cpp

@@ -1642,6 +1642,9 @@ void verilog_typecheckt::convert_module_item(
   else if(module_item.id() == ID_verilog_empty_item)
   {
   }
+  else if(module_item.id() == ID_verilog_package_import)
+  {
+  }
   else
   {
     throw errort().with_location(module_item.source_location())