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Commits on Aug 7, 2024

• Merge pull request #621 from diffblue/bump-verion-to-5-1

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• add CHANGELOG

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• bump version number to 5.1

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• Merge pull request #615 from diffblue/sva_and_not_or

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• Merge pull request #620 from diffblue/decoder1

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• Merge pull request #618 from diffblue/sva-abort-properties

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• SystemVerilog: SVA abort properties

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Commits on Aug 6, 2024

• Verilog: KNOWNBUG test for recursive module instantiation

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• Merge pull request #619 from diffblue/countones1

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Commits on Aug 5, 2024

• SystemVerilog: $countones

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Commits on Aug 4, 2024

• Merge pull request #617 from diffblue/disable_iff1

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• SystemVerilog: disable iff

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Commits on Aug 2, 2024

• Merge pull request #616 from diffblue/sequence-repetition

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• SystemVerilog: sequence repetition operators

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Commits on Aug 1, 2024

• Verilog: introduce sva_and_exprt, sva_or_exprt, sva_not_exprt

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Commits on Jul 31, 2024

• Merge pull request #614 from diffblue/bmc-sva-sequence

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• add word-level BMC encoding for SVA sequences

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• Merge pull request #613 from diffblue/sequence_implication1

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• Verilog: KNOWNBUG test for sequence implication

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Commits on Jul 30, 2024

• Merge pull request #612 from diffblue/benchmark-syntax-fixes

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• Fix mismatching parentheses in benchmarks

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Commits on Jul 29, 2024

• Merge pull request #611 from diffblue/bump-cbmc3

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• bump CBMC dependency

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• Merge pull request #607 from diffblue/range_type6

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• Merge pull request #608 from diffblue/CTL-AU-AR-EU-ER

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• Merge pull request #609 from diffblue/submodules-module-source

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Commits on Jul 26, 2024

• Verilog: parse tree now uses verilog_module_sourcet

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• Verilog: use verilog_module_sourcet to discover instantiated modules

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Commits on Jul 25, 2024

• SMV: parsing and type checking for CTL AR, ER, AU, EU

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• Add KNOWNBUG test for SMV ranges

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Commits on Jul 23, 2024

• Merge pull request #606 from diffblue/use_verilog_module_source

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Commits on Jul 22, 2024

• Verilog typechecker now uses verilog_module_sourcet

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• Merge pull request #599 from diffblue/ebmc-5-0-formula

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• Merge pull request #600 from diffblue/verilog_blocking_assign

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• Merge pull request #603 from diffblue/exception-constructors

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