diff --git a/examples/NeurIPS2025/Liveness/PWM_1-l1.sv b/examples/NeurIPS2025/Liveness/PWM_1-l1.sv
new file mode 100644
index 000000000..a0d553e5e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_1-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 10;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 5'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 5'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 5'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_10-l1.sv b/examples/NeurIPS2025/Liveness/PWM_10-l1.sv
new file mode 100644
index 000000000..fb2116df7
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_10-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 19;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 14'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 14'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 14'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_11-l1.sv b/examples/NeurIPS2025/Liveness/PWM_11-l1.sv
new file mode 100644
index 000000000..f496e16da
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_11-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 20;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 15'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 15'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 15'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_12-l1.sv b/examples/NeurIPS2025/Liveness/PWM_12-l1.sv
new file mode 100644
index 000000000..31669fde0
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_12-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 21;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 16'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 16'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 16'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_2-l1.sv b/examples/NeurIPS2025/Liveness/PWM_2-l1.sv
new file mode 100644
index 000000000..50ffe78cc
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_2-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 11;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 6'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 6'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 6'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_3-l1.sv b/examples/NeurIPS2025/Liveness/PWM_3-l1.sv
new file mode 100644
index 000000000..e479575a7
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_3-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 12;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 7'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 7'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 7'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_4-l1.sv b/examples/NeurIPS2025/Liveness/PWM_4-l1.sv
new file mode 100644
index 000000000..fe01772e1
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_4-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 13;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 8'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 8'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 8'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_5-l1.sv b/examples/NeurIPS2025/Liveness/PWM_5-l1.sv
new file mode 100644
index 000000000..a3c62ffca
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_5-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 14;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 9'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 9'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 9'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_6-l1.sv b/examples/NeurIPS2025/Liveness/PWM_6-l1.sv
new file mode 100644
index 000000000..985c63233
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_6-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 15;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 10'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 10'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 10'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_7-l1.sv b/examples/NeurIPS2025/Liveness/PWM_7-l1.sv
new file mode 100644
index 000000000..93afc4959
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_7-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 16;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 11'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 11'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 11'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_8-l1.sv b/examples/NeurIPS2025/Liveness/PWM_8-l1.sv
new file mode 100644
index 000000000..078921cd9
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_8-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 17;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 12'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 12'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 12'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/PWM_9-l1.sv b/examples/NeurIPS2025/Liveness/PWM_9-l1.sv
new file mode 100644
index 000000000..eb3e84977
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/PWM_9-l1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 18;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 13'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 13'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 13'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC G F Verilog.PWM_TOP.pulse_red = FALSE
+  assert property (@(posedge clk) always s_eventually pulse_red == 0);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_1-l1.sv b/examples/NeurIPS2025/Liveness/blink_1-l1.sv
new file mode 100644
index 000000000..a23b68415
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_1-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 8) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_10-l1.sv b/examples/NeurIPS2025/Liveness/blink_10-l1.sv
new file mode 100644
index 000000000..c30f0b9c7
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_10-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 17) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_11-l1.sv b/examples/NeurIPS2025/Liveness/blink_11-l1.sv
new file mode 100644
index 000000000..f44201a2f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_11-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 18) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_12-l1.sv b/examples/NeurIPS2025/Liveness/blink_12-l1.sv
new file mode 100644
index 000000000..a137b11ce
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_12-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 19) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_13-l1.sv b/examples/NeurIPS2025/Liveness/blink_13-l1.sv
new file mode 100644
index 000000000..f6058ade8
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_13-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 20) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_14-l1.sv b/examples/NeurIPS2025/Liveness/blink_14-l1.sv
new file mode 100644
index 000000000..c13641b91
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_14-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 21) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_15-l1.sv b/examples/NeurIPS2025/Liveness/blink_15-l1.sv
new file mode 100644
index 000000000..9a8fc855b
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_15-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 22) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_16-l1.sv b/examples/NeurIPS2025/Liveness/blink_16-l1.sv
new file mode 100644
index 000000000..da3af08db
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_16-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 23) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_17-l1.sv b/examples/NeurIPS2025/Liveness/blink_17-l1.sv
new file mode 100644
index 000000000..a8b8b98f8
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_17-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 24) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_18-l1.sv b/examples/NeurIPS2025/Liveness/blink_18-l1.sv
new file mode 100644
index 000000000..d71cca476
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_18-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 25) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_19-l1.sv b/examples/NeurIPS2025/Liveness/blink_19-l1.sv
new file mode 100644
index 000000000..9bc3d0a0c
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_19-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 26) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_2-l1.sv b/examples/NeurIPS2025/Liveness/blink_2-l1.sv
new file mode 100644
index 000000000..6b8420ab8
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_2-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 9) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_20-l1.sv b/examples/NeurIPS2025/Liveness/blink_20-l1.sv
new file mode 100644
index 000000000..7f0dd7faf
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_20-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 27) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_21-l1.sv b/examples/NeurIPS2025/Liveness/blink_21-l1.sv
new file mode 100644
index 000000000..69d47c7d5
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_21-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 28) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_22-l1.sv b/examples/NeurIPS2025/Liveness/blink_22-l1.sv
new file mode 100644
index 000000000..26a5d702d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_22-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 29) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_23-l1.sv b/examples/NeurIPS2025/Liveness/blink_23-l1.sv
new file mode 100644
index 000000000..0db59c1d8
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_23-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 30) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_24-l1.sv b/examples/NeurIPS2025/Liveness/blink_24-l1.sv
new file mode 100644
index 000000000..cf89d9e4f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_24-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 31) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_25-l1.sv b/examples/NeurIPS2025/Liveness/blink_25-l1.sv
new file mode 100644
index 000000000..6e37e7946
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_25-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 32) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_3-l1.sv b/examples/NeurIPS2025/Liveness/blink_3-l1.sv
new file mode 100644
index 000000000..aea977f3a
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_3-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 10) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_4-l1.sv b/examples/NeurIPS2025/Liveness/blink_4-l1.sv
new file mode 100644
index 000000000..4bbc61c82
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_4-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 11) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_5-l1.sv b/examples/NeurIPS2025/Liveness/blink_5-l1.sv
new file mode 100644
index 000000000..f7e1eb699
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_5-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 12) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_6-l1.sv b/examples/NeurIPS2025/Liveness/blink_6-l1.sv
new file mode 100644
index 000000000..51e7aeeff
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_6-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 13) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_7-l1.sv b/examples/NeurIPS2025/Liveness/blink_7-l1.sv
new file mode 100644
index 000000000..81f8f87d2
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_7-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 14) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_8-l1.sv b/examples/NeurIPS2025/Liveness/blink_8-l1.sv
new file mode 100644
index 000000000..1734ad9b6
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_8-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 15) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/blink_9-l1.sv b/examples/NeurIPS2025/Liveness/blink_9-l1.sv
new file mode 100644
index 000000000..f7ffded9c
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/blink_9-l1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 16) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC F G (Verilog.BLINK.rst = FALSE) -> G F (Verilog.BLINK.led = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> led);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_1-l1.sv b/examples/NeurIPS2025/Liveness/delay_1-l1.sv
new file mode 100644
index 000000000..3f772379d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_1-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 750;
+  localparam CBITS = 10;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_1-l2.sv b/examples/NeurIPS2025/Liveness/delay_1-l2.sv
new file mode 100644
index 000000000..da6cafd57
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_1-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 750;
+  localparam CBITS = 10;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_10-l1.sv b/examples/NeurIPS2025/Liveness/delay_10-l1.sv
new file mode 100644
index 000000000..197ee6fd4
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_10-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 20000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_10-l2.sv b/examples/NeurIPS2025/Liveness/delay_10-l2.sv
new file mode 100644
index 000000000..8262bb06d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_10-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 20000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_11-l1.sv b/examples/NeurIPS2025/Liveness/delay_11-l1.sv
new file mode 100644
index 000000000..d0be5ab05
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_11-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 22500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_11-l2.sv b/examples/NeurIPS2025/Liveness/delay_11-l2.sv
new file mode 100644
index 000000000..ce02c0ae3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_11-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 22500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_12-l1.sv b/examples/NeurIPS2025/Liveness/delay_12-l1.sv
new file mode 100644
index 000000000..42b961aa2
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_12-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 25000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_12-l2.sv b/examples/NeurIPS2025/Liveness/delay_12-l2.sv
new file mode 100644
index 000000000..b01e30146
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_12-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 25000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_13-l1.sv b/examples/NeurIPS2025/Liveness/delay_13-l1.sv
new file mode 100644
index 000000000..9a84dd998
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_13-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 50000;
+  localparam CBITS = 16;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_13-l2.sv b/examples/NeurIPS2025/Liveness/delay_13-l2.sv
new file mode 100644
index 000000000..9c17d710f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_13-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 50000;
+  localparam CBITS = 16;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_14-l1.sv b/examples/NeurIPS2025/Liveness/delay_14-l1.sv
new file mode 100644
index 000000000..2e9824736
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_14-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 100000;
+  localparam CBITS = 17;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_14-l2.sv b/examples/NeurIPS2025/Liveness/delay_14-l2.sv
new file mode 100644
index 000000000..59b920539
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_14-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 100000;
+  localparam CBITS = 17;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_15-l1.sv b/examples/NeurIPS2025/Liveness/delay_15-l1.sv
new file mode 100644
index 000000000..fa80dda7f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_15-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 200000;
+  localparam CBITS = 18;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_15-l2.sv b/examples/NeurIPS2025/Liveness/delay_15-l2.sv
new file mode 100644
index 000000000..82ba0ec81
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_15-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 200000;
+  localparam CBITS = 18;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_16-l1.sv b/examples/NeurIPS2025/Liveness/delay_16-l1.sv
new file mode 100644
index 000000000..7f0fa05c3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_16-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 400000;
+  localparam CBITS = 19;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_16-l2.sv b/examples/NeurIPS2025/Liveness/delay_16-l2.sv
new file mode 100644
index 000000000..4fd17b6fe
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_16-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 400000;
+  localparam CBITS = 19;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_2-l1.sv b/examples/NeurIPS2025/Liveness/delay_2-l1.sv
new file mode 100644
index 000000000..537c7d0d0
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_2-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 1250;
+  localparam CBITS = 11;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_2-l2.sv b/examples/NeurIPS2025/Liveness/delay_2-l2.sv
new file mode 100644
index 000000000..c11e71738
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_2-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 1250;
+  localparam CBITS = 11;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_3-l1.sv b/examples/NeurIPS2025/Liveness/delay_3-l1.sv
new file mode 100644
index 000000000..f67218d94
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_3-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 2500;
+  localparam CBITS = 12;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/delay_3-l2.sv b/examples/NeurIPS2025/Liveness/delay_3-l2.sv
new file mode 100644
index 000000000..04b87f20e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_3-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 2500;
+  localparam CBITS = 12;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/delay_4-l1.sv b/examples/NeurIPS2025/Liveness/delay_4-l1.sv
new file mode 100644
index 000000000..c6b342719
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_4-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 5000;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_4-l2.sv b/examples/NeurIPS2025/Liveness/delay_4-l2.sv
new file mode 100644
index 000000000..c32967d27
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_4-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 5000;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_5-l1.sv b/examples/NeurIPS2025/Liveness/delay_5-l1.sv
new file mode 100644
index 000000000..b6caab2ab
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_5-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 7500;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_5-l2.sv b/examples/NeurIPS2025/Liveness/delay_5-l2.sv
new file mode 100644
index 000000000..6d8d0476d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_5-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 7500;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_6-l1.sv b/examples/NeurIPS2025/Liveness/delay_6-l1.sv
new file mode 100644
index 000000000..b78bd6eec
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_6-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 10000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_6-l2.sv b/examples/NeurIPS2025/Liveness/delay_6-l2.sv
new file mode 100644
index 000000000..4fc5d7357
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_6-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 10000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_7-l1.sv b/examples/NeurIPS2025/Liveness/delay_7-l1.sv
new file mode 100644
index 000000000..16716175d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_7-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 12500;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_7-l2.sv b/examples/NeurIPS2025/Liveness/delay_7-l2.sv
new file mode 100644
index 000000000..27afc4b99
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_7-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 12500;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_8-l1.sv b/examples/NeurIPS2025/Liveness/delay_8-l1.sv
new file mode 100644
index 000000000..5d481fb0b
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_8-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 15000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_8-l2.sv b/examples/NeurIPS2025/Liveness/delay_8-l2.sv
new file mode 100644
index 000000000..113a521fc
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_8-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 15000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_9-l1.sv b/examples/NeurIPS2025/Liveness/delay_9-l1.sv
new file mode 100644
index 000000000..7dc14b007
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_9-l1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 17500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/delay_9-l2.sv b/examples/NeurIPS2025/Liveness/delay_9-l2.sv
new file mode 100644
index 000000000..cbbee46ef
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/delay_9-l2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 17500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> G F (Verilog.DELAY.sig = TRUE & X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/gray_1-l1.sv b/examples/NeurIPS2025/Liveness/gray_1-l1.sv
new file mode 100644
index 000000000..1f043eb06
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_1-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_1-l2.sv b/examples/NeurIPS2025/Liveness/gray_1-l2.sv
new file mode 100644
index 000000000..cab5a56c3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_1-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_1-l3.sv b/examples/NeurIPS2025/Liveness/gray_1-l3.sv
new file mode 100644
index 000000000..773c555ad
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_1-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_10-l1.sv b/examples/NeurIPS2025/Liveness/gray_10-l1.sv
new file mode 100644
index 000000000..c0747d364
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_10-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_10-l2.sv b/examples/NeurIPS2025/Liveness/gray_10-l2.sv
new file mode 100644
index 000000000..0c87ad21b
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_10-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_10-l3.sv b/examples/NeurIPS2025/Liveness/gray_10-l3.sv
new file mode 100644
index 000000000..9e2522fc3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_10-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_11-l1.sv b/examples/NeurIPS2025/Liveness/gray_11-l1.sv
new file mode 100644
index 000000000..21fa8a95f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_11-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_11-l2.sv b/examples/NeurIPS2025/Liveness/gray_11-l2.sv
new file mode 100644
index 000000000..a1acecee2
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_11-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_11-l3.sv b/examples/NeurIPS2025/Liveness/gray_11-l3.sv
new file mode 100644
index 000000000..7ccfcd854
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_11-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_2-l1.sv b/examples/NeurIPS2025/Liveness/gray_2-l1.sv
new file mode 100644
index 000000000..ffff3d645
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_2-l1.sv
@@ -0,0 +1,18 @@
+module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Liveness/gray_2-l2.sv b/examples/NeurIPS2025/Liveness/gray_2-l2.sv
new file mode 100644
index 000000000..c9408ec6d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_2-l2.sv
@@ -0,0 +1,18 @@
+module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Liveness/gray_2-l3.sv b/examples/NeurIPS2025/Liveness/gray_2-l3.sv
new file mode 100644
index 000000000..352af8501
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_2-l3.sv
@@ -0,0 +1,18 @@
+module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Liveness/gray_3-l1.sv b/examples/NeurIPS2025/Liveness/gray_3-l1.sv
new file mode 100644
index 000000000..0289d9189
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_3-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_3-l2.sv b/examples/NeurIPS2025/Liveness/gray_3-l2.sv
new file mode 100644
index 000000000..2f87d3663
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_3-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_3-l3.sv b/examples/NeurIPS2025/Liveness/gray_3-l3.sv
new file mode 100644
index 000000000..1fc75f246
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_3-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_4-l1.sv b/examples/NeurIPS2025/Liveness/gray_4-l1.sv
new file mode 100644
index 000000000..95fbcee82
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_4-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_4-l2.sv b/examples/NeurIPS2025/Liveness/gray_4-l2.sv
new file mode 100644
index 000000000..695eb15a1
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_4-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_4-l3.sv b/examples/NeurIPS2025/Liveness/gray_4-l3.sv
new file mode 100644
index 000000000..6784633d7
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_4-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_5-l1.sv b/examples/NeurIPS2025/Liveness/gray_5-l1.sv
new file mode 100644
index 000000000..a86576647
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_5-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_5-l2.sv b/examples/NeurIPS2025/Liveness/gray_5-l2.sv
new file mode 100644
index 000000000..dffb7c258
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_5-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_5-l3.sv b/examples/NeurIPS2025/Liveness/gray_5-l3.sv
new file mode 100644
index 000000000..f04a9ef42
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_5-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_6-l1.sv b/examples/NeurIPS2025/Liveness/gray_6-l1.sv
new file mode 100644
index 000000000..10c70af6b
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_6-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_6-l2.sv b/examples/NeurIPS2025/Liveness/gray_6-l2.sv
new file mode 100644
index 000000000..941ae5317
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_6-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_6-l3.sv b/examples/NeurIPS2025/Liveness/gray_6-l3.sv
new file mode 100644
index 000000000..061076993
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_6-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_7-l1.sv b/examples/NeurIPS2025/Liveness/gray_7-l1.sv
new file mode 100644
index 000000000..2231cb591
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_7-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_7-l2.sv b/examples/NeurIPS2025/Liveness/gray_7-l2.sv
new file mode 100644
index 000000000..2f3fe6de2
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_7-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_7-l3.sv b/examples/NeurIPS2025/Liveness/gray_7-l3.sv
new file mode 100644
index 000000000..82f94a898
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_7-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_8-l1.sv b/examples/NeurIPS2025/Liveness/gray_8-l1.sv
new file mode 100644
index 000000000..097c0eccd
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_8-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_8-l2.sv b/examples/NeurIPS2025/Liveness/gray_8-l2.sv
new file mode 100644
index 000000000..a77ca742e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_8-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_8-l3.sv b/examples/NeurIPS2025/Liveness/gray_8-l3.sv
new file mode 100644
index 000000000..4fb7e6777
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_8-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_9-l1.sv b/examples/NeurIPS2025/Liveness/gray_9-l1.sv
new file mode 100644
index 000000000..8f2e936e0
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_9-l1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_9-l2.sv b/examples/NeurIPS2025/Liveness/gray_9-l2.sv
new file mode 100644
index 000000000..fae0df9f6
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_9-l2.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/gray_9-l3.sv b/examples/NeurIPS2025/Liveness/gray_9-l3.sv
new file mode 100644
index 000000000..27550085e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/gray_9-l3.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC F G (Verilog.GRAY.rst = FALSE) -> G F (Verilog.GRAY.sig = TRUE & F Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/lcd_1-l1.sv b/examples/NeurIPS2025/Liveness/lcd_1-l1.sv
new file mode 100644
index 000000000..535ab1a45
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_1-l1.sv
@@ -0,0 +1,110 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 1;
+	localparam CBITS = 9;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+				busy = 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+				busy = 1;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_10-l1.sv b/examples/NeurIPS2025/Liveness/lcd_10-l1.sv
new file mode 100644
index 000000000..0587be12b
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_10-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 35;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_11-l1.sv b/examples/NeurIPS2025/Liveness/lcd_11-l1.sv
new file mode 100644
index 000000000..c9ab72275
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_11-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 40;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_12-l1.sv b/examples/NeurIPS2025/Liveness/lcd_12-l1.sv
new file mode 100644
index 000000000..a62311e75
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_12-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 45;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_13-l1.sv b/examples/NeurIPS2025/Liveness/lcd_13-l1.sv
new file mode 100644
index 000000000..ff55d4455
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_13-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 180;
+	localparam CBITS = 17;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_14-l1.sv b/examples/NeurIPS2025/Liveness/lcd_14-l1.sv
new file mode 100644
index 000000000..01dc1484a
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_14-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 360;
+	localparam CBITS = 18;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_2-l1.sv b/examples/NeurIPS2025/Liveness/lcd_2-l1.sv
new file mode 100644
index 000000000..9878f3cd5
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_2-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 2;
+	localparam CBITS = 10;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_3-l1.sv b/examples/NeurIPS2025/Liveness/lcd_3-l1.sv
new file mode 100644
index 000000000..a831f6e75
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_3-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 3;
+	localparam CBITS = 11;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_4-l1.sv b/examples/NeurIPS2025/Liveness/lcd_4-l1.sv
new file mode 100644
index 000000000..7d145684e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_4-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 5;
+	localparam CBITS = 12;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_5-l1.sv b/examples/NeurIPS2025/Liveness/lcd_5-l1.sv
new file mode 100644
index 000000000..4d3b4648d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_5-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 10;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_6-l1.sv b/examples/NeurIPS2025/Liveness/lcd_6-l1.sv
new file mode 100644
index 000000000..9b0811120
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_6-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 15;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_7-l1.sv b/examples/NeurIPS2025/Liveness/lcd_7-l1.sv
new file mode 100644
index 000000000..ebff48b85
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_7-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 20;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_8-l1.sv b/examples/NeurIPS2025/Liveness/lcd_8-l1.sv
new file mode 100644
index 000000000..a42d7d241
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_8-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 25;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/lcd_9-l1.sv b/examples/NeurIPS2025/Liveness/lcd_9-l1.sv
new file mode 100644
index 000000000..cfb369d0e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/lcd_9-l1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 30;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.LCD.lcd_enable = TRUE) -> G F (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) s_eventually lcd_enable -> state == 2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Liveness/load_store_1-l1.sv b/examples/NeurIPS2025/Liveness/load_store_1-l1.sv
new file mode 100644
index 000000000..0fe652a06
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_1-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 750;
+    localparam CBITS = 10;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_10-l1.sv b/examples/NeurIPS2025/Liveness/load_store_10-l1.sv
new file mode 100644
index 000000000..01dc56cf3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_10-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 20000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_11-l1.sv b/examples/NeurIPS2025/Liveness/load_store_11-l1.sv
new file mode 100644
index 000000000..1a3a5a781
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_11-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 22500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_12-l1.sv b/examples/NeurIPS2025/Liveness/load_store_12-l1.sv
new file mode 100644
index 000000000..d29da9d82
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_12-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 25000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_13-l1.sv b/examples/NeurIPS2025/Liveness/load_store_13-l1.sv
new file mode 100644
index 000000000..80ab947bd
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_13-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 50000;
+    localparam CBITS = 16;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_14-l1.sv b/examples/NeurIPS2025/Liveness/load_store_14-l1.sv
new file mode 100644
index 000000000..d91d3f288
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_14-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 100000;
+    localparam CBITS = 17;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_15-l1.sv b/examples/NeurIPS2025/Liveness/load_store_15-l1.sv
new file mode 100644
index 000000000..d27152187
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_15-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 200000;
+    localparam CBITS = 18;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_16-l1.sv b/examples/NeurIPS2025/Liveness/load_store_16-l1.sv
new file mode 100644
index 000000000..f4fd89460
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_16-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 400000;
+    localparam CBITS = 19;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_2-l1.sv b/examples/NeurIPS2025/Liveness/load_store_2-l1.sv
new file mode 100644
index 000000000..c40b75e41
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_2-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 1250;
+    localparam CBITS = 11;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_3-l1.sv b/examples/NeurIPS2025/Liveness/load_store_3-l1.sv
new file mode 100644
index 000000000..a0e06ef59
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_3-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 2500;
+    localparam CBITS = 12;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_4-l1.sv b/examples/NeurIPS2025/Liveness/load_store_4-l1.sv
new file mode 100644
index 000000000..547bec2e1
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_4-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 5000;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_5-l1.sv b/examples/NeurIPS2025/Liveness/load_store_5-l1.sv
new file mode 100644
index 000000000..684549e16
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_5-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 7500;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_6-l1.sv b/examples/NeurIPS2025/Liveness/load_store_6-l1.sv
new file mode 100644
index 000000000..ac4030095
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_6-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 10000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_7-l1.sv b/examples/NeurIPS2025/Liveness/load_store_7-l1.sv
new file mode 100644
index 000000000..603c79428
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_7-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 12500;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_8-l1.sv b/examples/NeurIPS2025/Liveness/load_store_8-l1.sv
new file mode 100644
index 000000000..3419e97fe
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_8-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 15000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/load_store_9-l1.sv b/examples/NeurIPS2025/Liveness/load_store_9-l1.sv
new file mode 100644
index 000000000..1cbe96df3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/load_store_9-l1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 17500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC F G (Verilog.Load_Store.rst = FALSE) -> G F (Verilog.Load_Store.sig = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_1-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_1-l1.sv
new file mode 100644
index 000000000..79dcb5d98
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_1-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 250;
+	localparam CBITS = 8;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_1-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_1-l2.sv
new file mode 100644
index 000000000..f2b033fca
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_1-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 250;
+	localparam CBITS = 8;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_10-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_10-l1.sv
new file mode 100644
index 000000000..b5f7997c6
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_10-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 15000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_10-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_10-l2.sv
new file mode 100644
index 000000000..e3356f089
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_10-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 15000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_11-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_11-l1.sv
new file mode 100644
index 000000000..1d11b0638
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_11-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 17500;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_11-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_11-l2.sv
new file mode 100644
index 000000000..ea2cc192c
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_11-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 17500;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_12-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_12-l1.sv
new file mode 100644
index 000000000..850f4aede
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_12-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 20000;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_12-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_12-l2.sv
new file mode 100644
index 000000000..9b599c8b5
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_12-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 20000;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_13-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_13-l1.sv
new file mode 100644
index 000000000..0fb1d6a4d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_13-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 40000;
+	localparam CBITS = 16;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_13-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_13-l2.sv
new file mode 100644
index 000000000..0bdd7a173
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_13-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 40000;
+	localparam CBITS = 16;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_14-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_14-l1.sv
new file mode 100644
index 000000000..8e2c32ce4
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_14-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 80000;
+	localparam CBITS = 17;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_14-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_14-l2.sv
new file mode 100644
index 000000000..57a413198
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_14-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 80000;
+	localparam CBITS = 17;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_15-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_15-l1.sv
new file mode 100644
index 000000000..7bf6f2237
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_15-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 160000;
+	localparam CBITS = 18;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_15-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_15-l2.sv
new file mode 100644
index 000000000..a250b69cf
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_15-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 160000;
+	localparam CBITS = 18;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_2-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_2-l1.sv
new file mode 100644
index 000000000..90bc2cada
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_2-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 500;
+	localparam CBITS = 9;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_2-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_2-l2.sv
new file mode 100644
index 000000000..60c4e7c48
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_2-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 500;
+	localparam CBITS = 9;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_3-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_3-l1.sv
new file mode 100644
index 000000000..8beb14aab
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_3-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 750;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_3-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_3-l2.sv
new file mode 100644
index 000000000..e59c561de
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_3-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 750;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_4-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_4-l1.sv
new file mode 100644
index 000000000..e0265115e
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_4-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 1000;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_4-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_4-l2.sv
new file mode 100644
index 000000000..5b7a58198
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_4-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 1000;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_5-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_5-l1.sv
new file mode 100644
index 000000000..a0baf2bd5
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_5-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 2500;
+	localparam CBITS = 12;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_5-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_5-l2.sv
new file mode 100644
index 000000000..d26be1de4
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_5-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 2500;
+	localparam CBITS = 12;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_6-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_6-l1.sv
new file mode 100644
index 000000000..190fa0faa
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_6-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 5000;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_6-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_6-l2.sv
new file mode 100644
index 000000000..a839bfce5
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_6-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 5000;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_7-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_7-l1.sv
new file mode 100644
index 000000000..8f9065b20
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_7-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 7500;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_7-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_7-l2.sv
new file mode 100644
index 000000000..db7547e57
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_7-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 7500;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_8-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_8-l1.sv
new file mode 100644
index 000000000..d95e8c421
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_8-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 10000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_8-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_8-l2.sv
new file mode 100644
index 000000000..2421b72de
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_8-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 10000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_9-l1.sv b/examples/NeurIPS2025/Liveness/seven_seg_9-l1.sv
new file mode 100644
index 000000000..3f7a04336
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_9-l1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 12500;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> (G F (Verilog.SEVEN.digit_select = TRUE))
+  assert property (@(posedge clk) s_eventually !rst -> digit_select);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/seven_seg_9-l2.sv b/examples/NeurIPS2025/Liveness/seven_seg_9-l2.sv
new file mode 100644
index 000000000..f800c892d
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/seven_seg_9-l2.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 12500;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC F G (Verilog.SEVEN.rst = FALSE) -> ( (G F (Verilog.SEVEN.digit_select = FALSE)) & (G F (Verilog.SEVEN.digit_select = TRUE)))
+  assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_1-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_1-l1.sv
new file mode 100644
index 000000000..718484d99
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_1-l1.sv
@@ -0,0 +1,50 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 10;
+	localparam CBITS = 6;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_10-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_10-l1.sv
new file mode 100644
index 000000000..d5eb00e4f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_10-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 3000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_11-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_11-l1.sv
new file mode 100644
index 000000000..861924d66
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_11-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 4000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_12-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_12-l1.sv
new file mode 100644
index 000000000..6e9eae129
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_12-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 5000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_13-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_13-l1.sv
new file mode 100644
index 000000000..69bee379f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_13-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 6000;
+	localparam CBITS = 15;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_14-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_14-l1.sv
new file mode 100644
index 000000000..08a2d3ad3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_14-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 12000;
+	localparam CBITS = 16;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_15-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_15-l1.sv
new file mode 100644
index 000000000..dda2e60d0
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_15-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 24000;
+	localparam CBITS = 17;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_16-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_16-l1.sv
new file mode 100644
index 000000000..7aebb1d6f
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_16-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 48000;
+	localparam CBITS = 18;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_17-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_17-l1.sv
new file mode 100644
index 000000000..a87e90dec
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_17-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 96000;
+	localparam CBITS = 19;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_2-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_2-l1.sv
new file mode 100644
index 000000000..df8b6efaf
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_2-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 100;
+	localparam CBITS = 9;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_3-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_3-l1.sv
new file mode 100644
index 000000000..817e232cd
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_3-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 200;
+	localparam CBITS = 10;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_4-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_4-l1.sv
new file mode 100644
index 000000000..d4bd259c3
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_4-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 300;
+	localparam CBITS = 10;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_5-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_5-l1.sv
new file mode 100644
index 000000000..dd245b283
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_5-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 400;
+	localparam CBITS = 11;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_6-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_6-l1.sv
new file mode 100644
index 000000000..48305e124
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_6-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 600;
+	localparam CBITS = 11;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_7-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_7-l1.sv
new file mode 100644
index 000000000..a73874fab
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_7-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 800;
+	localparam CBITS = 12;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_8-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_8-l1.sv
new file mode 100644
index 000000000..1d33cb216
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_8-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 1000;
+	localparam CBITS = 12;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/thermocouple_9-l1.sv b/examples/NeurIPS2025/Liveness/thermocouple_9-l1.sv
new file mode 100644
index 000000000..9e0882ad8
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/thermocouple_9-l1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 2000;
+	localparam CBITS = 13;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC F G (Verilog.Thermocouple.rst = FALSE) -> G F (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE)
+  assert property (@(posedge clk) s_eventually !rst -> state);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_1-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_1-l1.sv
new file mode 100644
index 000000000..30850be7c
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_1-l1.sv
@@ -0,0 +1,37 @@
+module UART_T #(localparam d_width = 4, c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+	assign tx_busy = tx_state;
+	always @(posedge clk) begin
+		
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_10-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_10-l1.sv
new file mode 100644
index 000000000..f4d3f2bec
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_10-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 15, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_2-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_2-l1.sv
new file mode 100644
index 000000000..8d1dbed00
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_2-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 6, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_3-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_3-l1.sv
new file mode 100644
index 000000000..a82ea6675
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_3-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 8, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_4-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_4-l1.sv
new file mode 100644
index 000000000..429075ccb
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_4-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 9, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_5-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_5-l1.sv
new file mode 100644
index 000000000..715467e41
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_5-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 10, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_6-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_6-l1.sv
new file mode 100644
index 000000000..f87a1f61c
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_6-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 11, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_7-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_7-l1.sv
new file mode 100644
index 000000000..7ca7399f1
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_7-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 12, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_8-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_8-l1.sv
new file mode 100644
index 000000000..d5e599b6b
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_8-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 13, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Liveness/uart_transmit_9-l1.sv b/examples/NeurIPS2025/Liveness/uart_transmit_9-l1.sv
new file mode 100644
index 000000000..8ccd39fc2
--- /dev/null
+++ b/examples/NeurIPS2025/Liveness/uart_transmit_9-l1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 14, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC F G (Verilog.UART_T.rst = FALSE) -> G F (Verilog.UART_T.tx_state = FALSE)
+  assert property (@(posedge clk) s_eventually !rst -> !tx_state);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_1-sl1.sv
new file mode 100644
index 000000000..dee5f73bd
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_1-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 8) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_10-sl1.sv
new file mode 100644
index 000000000..591640a3a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_10-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 17) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_11-sl1.sv
new file mode 100644
index 000000000..21761461c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_11-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 18) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_12-sl1.sv
new file mode 100644
index 000000000..e202cba3a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_12-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 19) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_13-sl1.sv
new file mode 100644
index 000000000..b37c545ae
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_13-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 20) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_14-sl1.sv
new file mode 100644
index 000000000..85703e0c4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_14-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 21) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_15-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_15-sl1.sv
new file mode 100644
index 000000000..18c739ad4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_15-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 22) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_16-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_16-sl1.sv
new file mode 100644
index 000000000..9872b4e04
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_16-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 23) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_17-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_17-sl1.sv
new file mode 100644
index 000000000..ec49163b1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_17-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 24) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_18-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_18-sl1.sv
new file mode 100644
index 000000000..7f82d5062
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_18-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 25) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_19-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_19-sl1.sv
new file mode 100644
index 000000000..130dfd06e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_19-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 26) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_2-sl1.sv
new file mode 100644
index 000000000..c65fd78ec
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_2-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 9) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_20-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_20-sl1.sv
new file mode 100644
index 000000000..5735d4483
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_20-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 27) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_21-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_21-sl1.sv
new file mode 100644
index 000000000..916ae22eb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_21-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 28) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_22-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_22-sl1.sv
new file mode 100644
index 000000000..6ad765620
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_22-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 29) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_23-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_23-sl1.sv
new file mode 100644
index 000000000..d64872280
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_23-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 30) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_24-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_24-sl1.sv
new file mode 100644
index 000000000..48816e85f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_24-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 31) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_25-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_25-sl1.sv
new file mode 100644
index 000000000..8e05b2007
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_25-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 32) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_3-sl1.sv
new file mode 100644
index 000000000..6a4e74ee2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_3-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 10) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_4-sl1.sv
new file mode 100644
index 000000000..70443cbdc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_4-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 11) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_5-sl1.sv
new file mode 100644
index 000000000..486f7be01
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_5-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 12) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_6-sl1.sv
new file mode 100644
index 000000000..2d97abe45
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_6-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 13) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_7-sl1.sv
new file mode 100644
index 000000000..f86a15c67
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_7-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 14) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_8-sl1.sv
new file mode 100644
index 000000000..bf4194426
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_8-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 15) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/blink_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/blink_9-sl1.sv
new file mode 100644
index 000000000..a8cd7d4f9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/blink_9-sl1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 16) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G Verilog.BLINK.rst = FALSE -> G ( Verilog.BLINK.led = TRUE -> (Verilog.BLINK.led = TRUE U Verilog.BLINK.mode = FALSE))
+  assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_1-sl1.sv
new file mode 100644
index 000000000..85da70483
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_1-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 750;
+  localparam CBITS = 10;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_1-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_1-sl2.sv
new file mode 100644
index 000000000..553da38ab
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_1-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 750;
+  localparam CBITS = 10;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_10-sl1.sv
new file mode 100644
index 000000000..7f202be94
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_10-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 20000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_10-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_10-sl2.sv
new file mode 100644
index 000000000..ddd718018
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_10-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 20000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_11-sl1.sv
new file mode 100644
index 000000000..c440b75af
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_11-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 22500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_11-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_11-sl2.sv
new file mode 100644
index 000000000..2de043a59
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_11-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 22500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_12-sl1.sv
new file mode 100644
index 000000000..7019dd254
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_12-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 25000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_12-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_12-sl2.sv
new file mode 100644
index 000000000..aec041609
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_12-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 25000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_13-sl1.sv
new file mode 100644
index 000000000..8961b5a4d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_13-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 50000;
+  localparam CBITS = 16;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_13-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_13-sl2.sv
new file mode 100644
index 000000000..5383f0290
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_13-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 50000;
+  localparam CBITS = 16;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_14-sl1.sv
new file mode 100644
index 000000000..28f1c7d3d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_14-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 100000;
+  localparam CBITS = 17;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_14-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_14-sl2.sv
new file mode 100644
index 000000000..ccb9a8404
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_14-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 100000;
+  localparam CBITS = 17;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_15-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_15-sl1.sv
new file mode 100644
index 000000000..e310b1421
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_15-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 200000;
+  localparam CBITS = 18;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_15-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_15-sl2.sv
new file mode 100644
index 000000000..6d87a5752
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_15-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 200000;
+  localparam CBITS = 18;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_16-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_16-sl1.sv
new file mode 100644
index 000000000..93896b7f4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_16-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 400000;
+  localparam CBITS = 19;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_16-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_16-sl2.sv
new file mode 100644
index 000000000..5ba1792fa
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_16-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 400000;
+  localparam CBITS = 19;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_2-sl1.sv
new file mode 100644
index 000000000..80e6afaa0
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_2-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 1250;
+  localparam CBITS = 11;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_2-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_2-sl2.sv
new file mode 100644
index 000000000..b244559f5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_2-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 1250;
+  localparam CBITS = 11;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_3-sl1.sv
new file mode 100644
index 000000000..6c17bf090
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_3-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 2500;
+  localparam CBITS = 12;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_3-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_3-sl2.sv
new file mode 100644
index 000000000..2eaabbe93
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_3-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 2500;
+  localparam CBITS = 12;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_4-sl1.sv
new file mode 100644
index 000000000..ae61e6303
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_4-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 5000;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_4-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_4-sl2.sv
new file mode 100644
index 000000000..5c5999f01
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_4-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 5000;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_5-sl1.sv
new file mode 100644
index 000000000..354bac868
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_5-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 7500;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_5-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_5-sl2.sv
new file mode 100644
index 000000000..cc9a7f209
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_5-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 7500;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_6-sl1.sv
new file mode 100644
index 000000000..2d52a2516
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_6-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 10000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_6-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_6-sl2.sv
new file mode 100644
index 000000000..9398c0eee
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_6-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 10000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_7-sl1.sv
new file mode 100644
index 000000000..f1f9ed87a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_7-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 12500;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_7-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_7-sl2.sv
new file mode 100644
index 000000000..8981db4ab
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_7-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 12500;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_8-sl1.sv
new file mode 100644
index 000000000..89c9f0a81
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_8-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 15000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_8-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_8-sl2.sv
new file mode 100644
index 000000000..27489a857
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_8-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 15000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/delay_9-sl1.sv
new file mode 100644
index 000000000..7755f3901
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_9-sl1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 17500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> X G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/delay_9-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/delay_9-sl2.sv
new file mode 100644
index 000000000..282770611
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/delay_9-sl2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 17500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC F G (Verilog.DELAY.rst = FALSE) -> F G ((Verilog.DELAY.flg = TRUE) U (Verilog.DELAY.sig = TRUE))
+  assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_1-sl1.sv
new file mode 100644
index 000000000..e43d7ed1c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_1-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 3;
+	localparam CBITS = 4;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_10-sl1.sv
new file mode 100644
index 000000000..19eaca60b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_10-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 4000;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_11-sl1.sv
new file mode 100644
index 000000000..1435aa886
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_11-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 4500;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_12-sl1.sv
new file mode 100644
index 000000000..7080dcd44
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_12-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 5000;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_13-sl1.sv
new file mode 100644
index 000000000..e6cce6e2e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_13-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 5500;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_14-sl1.sv
new file mode 100644
index 000000000..9c1b64045
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_14-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 6000;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_15-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_15-sl1.sv
new file mode 100644
index 000000000..44f04a6f4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_15-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 6500;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_16-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_16-sl1.sv
new file mode 100644
index 000000000..7a1933e31
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_16-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 7000;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_17-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_17-sl1.sv
new file mode 100644
index 000000000..8bee2062c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_17-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 10000;
+	localparam CBITS = 16;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_18-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_18-sl1.sv
new file mode 100644
index 000000000..aeaf672e1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_18-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 17500;
+	localparam CBITS = 17;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_19-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_19-sl1.sv
new file mode 100644
index 000000000..aedeb8381
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_19-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 35000;
+	localparam CBITS = 18;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_2-sl1.sv
new file mode 100644
index 000000000..5782788e1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_2-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 250;
+	localparam CBITS = 10;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_20-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_20-sl1.sv
new file mode 100644
index 000000000..3d1dd43bf
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_20-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 70000;
+	localparam CBITS = 19;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_3-sl1.sv
new file mode 100644
index 000000000..3781c55a3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_3-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 500;
+	localparam CBITS = 11;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_4-sl1.sv
new file mode 100644
index 000000000..039b67617
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_4-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 1000;
+	localparam CBITS = 12;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_5-sl1.sv
new file mode 100644
index 000000000..f633077d9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_5-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 1500;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_6-sl1.sv
new file mode 100644
index 000000000..8009ab3d2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_6-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 2000;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_7-sl1.sv
new file mode 100644
index 000000000..3a28eefb5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_7-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 2500;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_8-sl1.sv
new file mode 100644
index 000000000..0011f4a49
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_8-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 3000;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/i2c_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/i2c_9-sl1.sv
new file mode 100644
index 000000000..1a5b91cb5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/i2c_9-sl1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 3500;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC G (Verilog.i2cStrech.rst = FALSE) -> G  ((Verilog.i2cStrech.stretch = FALSE) -> (Verilog.i2cStrech.stretch = FALSE U Verilog.i2cStrech.switch_range = TRUE))
+  assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_1-sl1.sv
new file mode 100644
index 000000000..5665af7c3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_1-sl1.sv
@@ -0,0 +1,110 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 1;
+	localparam CBITS = 9;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+				busy = 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+				busy = 1;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_10-sl1.sv
new file mode 100644
index 000000000..0588d08ec
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_10-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 35;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_11-sl1.sv
new file mode 100644
index 000000000..45d3c0ef8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_11-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 40;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_12-sl1.sv
new file mode 100644
index 000000000..980fa3df8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_12-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 45;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_13-sl1.sv
new file mode 100644
index 000000000..953ebe19f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_13-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 180;
+	localparam CBITS = 17;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_14-sl1.sv
new file mode 100644
index 000000000..2a9545253
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_14-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 360;
+	localparam CBITS = 18;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_2-sl1.sv
new file mode 100644
index 000000000..3d438e513
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_2-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 2;
+	localparam CBITS = 10;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_3-sl1.sv
new file mode 100644
index 000000000..e8136e195
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_3-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 3;
+	localparam CBITS = 11;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_4-sl1.sv
new file mode 100644
index 000000000..763128d3f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_4-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 5;
+	localparam CBITS = 12;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_5-sl1.sv
new file mode 100644
index 000000000..f57573f92
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_5-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 10;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_6-sl1.sv
new file mode 100644
index 000000000..09b462736
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_6-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 15;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_7-sl1.sv
new file mode 100644
index 000000000..61bb4c6ca
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_7-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 20;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_8-sl1.sv
new file mode 100644
index 000000000..4857e8df7
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_8-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 25;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/lcd_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/lcd_9-sl1.sv
new file mode 100644
index 000000000..715351a8e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/lcd_9-sl1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 30;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC G ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) -> ((Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = TRUE) U (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)))
+  assert property (@(posedge clk) state==3 implies (state==3 s_until state==2));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_1-sl1.sv
new file mode 100644
index 000000000..6a9100857
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_1-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 750;
+    localparam CBITS = 10;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_1-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_1-sl2.sv
new file mode 100644
index 000000000..dffaa2074
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_1-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 750;
+    localparam CBITS = 10;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_10-sl1.sv
new file mode 100644
index 000000000..f27e8ef41
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_10-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 20000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_10-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_10-sl2.sv
new file mode 100644
index 000000000..13c177bb6
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_10-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 20000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_11-sl1.sv
new file mode 100644
index 000000000..05ee6eb5f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_11-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 22500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_11-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_11-sl2.sv
new file mode 100644
index 000000000..2fca31f7b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_11-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 22500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_12-sl1.sv
new file mode 100644
index 000000000..fcbfd70b9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_12-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 25000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_12-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_12-sl2.sv
new file mode 100644
index 000000000..525bd2c01
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_12-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 25000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_13-sl1.sv
new file mode 100644
index 000000000..d679a67e1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_13-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 50000;
+    localparam CBITS = 16;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_13-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_13-sl2.sv
new file mode 100644
index 000000000..c9cc00aba
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_13-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 50000;
+    localparam CBITS = 16;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_14-sl1.sv
new file mode 100644
index 000000000..bd9a53ea0
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_14-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 100000;
+    localparam CBITS = 17;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_14-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_14-sl2.sv
new file mode 100644
index 000000000..7441ee1c7
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_14-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 100000;
+    localparam CBITS = 17;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_15-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_15-sl1.sv
new file mode 100644
index 000000000..6cd808431
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_15-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 200000;
+    localparam CBITS = 18;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_15-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_15-sl2.sv
new file mode 100644
index 000000000..17deb46b1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_15-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 200000;
+    localparam CBITS = 18;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_16-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_16-sl1.sv
new file mode 100644
index 000000000..436764e3e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_16-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 400000;
+    localparam CBITS = 19;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_16-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_16-sl2.sv
new file mode 100644
index 000000000..77d052c36
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_16-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 400000;
+    localparam CBITS = 19;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_2-sl1.sv
new file mode 100644
index 000000000..911c054fb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_2-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 1250;
+    localparam CBITS = 11;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_2-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_2-sl2.sv
new file mode 100644
index 000000000..07fea0489
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_2-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 1250;
+    localparam CBITS = 11;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_3-sl1.sv
new file mode 100644
index 000000000..9b58b1634
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_3-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 2500;
+    localparam CBITS = 12;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_3-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_3-sl2.sv
new file mode 100644
index 000000000..b147de4d9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_3-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 2500;
+    localparam CBITS = 12;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_4-sl1.sv
new file mode 100644
index 000000000..c5d2039ec
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_4-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 5000;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_4-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_4-sl2.sv
new file mode 100644
index 000000000..4ded86db8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_4-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 5000;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_5-sl1.sv
new file mode 100644
index 000000000..0d9e16f48
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_5-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 7500;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_5-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_5-sl2.sv
new file mode 100644
index 000000000..7e9d4426a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_5-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 7500;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_6-sl1.sv
new file mode 100644
index 000000000..babfbdf71
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_6-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 10000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_6-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_6-sl2.sv
new file mode 100644
index 000000000..f1cd19e91
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_6-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 10000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_7-sl1.sv
new file mode 100644
index 000000000..6d860b94c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_7-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 12500;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_7-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_7-sl2.sv
new file mode 100644
index 000000000..06638892a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_7-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 12500;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_8-sl1.sv
new file mode 100644
index 000000000..02d3fcd47
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_8-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 15000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_8-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_8-sl2.sv
new file mode 100644
index 000000000..5b6140ecd
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_8-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 15000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_9-sl1.sv
new file mode 100644
index 000000000..2a7d99676
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_9-sl1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 17500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.m = TRUE U Verilog.Load_Store.sig = TRUE)))
+  assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/load_store_9-sl2.sv b/examples/NeurIPS2025/Safety+Liveness/load_store_9-sl2.sv
new file mode 100644
index 000000000..509ebd456
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/load_store_9-sl2.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 17500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC G (Verilog.Load_Store.rst = FALSE) -> X G  (((Verilog.Load_Store.m = TRUE) -> (Verilog.Load_Store.sig = FALSE U (X Verilog.Load_Store.m = FALSE))))
+  assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_1-sl1.sv
new file mode 100644
index 000000000..2298b3e50
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_1-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 250;
+	localparam CBITS = 8;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_10-sl1.sv
new file mode 100644
index 000000000..6992da571
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_10-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 15000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_11-sl1.sv
new file mode 100644
index 000000000..1ad814a77
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_11-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 17500;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_12-sl1.sv
new file mode 100644
index 000000000..09e9bb56c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_12-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 20000;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_13-sl1.sv
new file mode 100644
index 000000000..a2b372683
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_13-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 40000;
+	localparam CBITS = 16;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_14-sl1.sv
new file mode 100644
index 000000000..2a778c97c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_14-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 80000;
+	localparam CBITS = 17;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_15-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_15-sl1.sv
new file mode 100644
index 000000000..5ffb4bbdb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_15-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 160000;
+	localparam CBITS = 18;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_2-sl1.sv
new file mode 100644
index 000000000..262183c25
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_2-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 500;
+	localparam CBITS = 9;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_3-sl1.sv
new file mode 100644
index 000000000..400599fde
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_3-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 750;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_4-sl1.sv
new file mode 100644
index 000000000..cc450d0a9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_4-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 1000;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_5-sl1.sv
new file mode 100644
index 000000000..79bceb2dd
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_5-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 2500;
+	localparam CBITS = 12;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_6-sl1.sv
new file mode 100644
index 000000000..75af2ca72
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_6-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 5000;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_7-sl1.sv
new file mode 100644
index 000000000..1df1f5cb3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_7-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 7500;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_8-sl1.sv
new file mode 100644
index 000000000..751fb943f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_8-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 10000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/seven_seg_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/seven_seg_9-sl1.sv
new file mode 100644
index 000000000..ae580e50c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/seven_seg_9-sl1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 12500;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC G (Verilog.SEVEN.rst = FALSE) -> G  ( ((Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE ) | (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE )) U X Verilog.SEVEN.sig = TRUE) 
+  assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_1-sl1.sv
new file mode 100644
index 000000000..cff3b34c2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_1-sl1.sv
@@ -0,0 +1,50 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 10;
+	localparam CBITS = 6;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_10-sl1.sv
new file mode 100644
index 000000000..1151f2224
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_10-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 3000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_11-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_11-sl1.sv
new file mode 100644
index 000000000..c4925c1f1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_11-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 4000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_12-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_12-sl1.sv
new file mode 100644
index 000000000..5b33273ab
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_12-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 5000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_13-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_13-sl1.sv
new file mode 100644
index 000000000..faae91aa2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_13-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 6000;
+	localparam CBITS = 15;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_14-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_14-sl1.sv
new file mode 100644
index 000000000..ce62cbbc1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_14-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 12000;
+	localparam CBITS = 16;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_15-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_15-sl1.sv
new file mode 100644
index 000000000..edacee652
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_15-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 24000;
+	localparam CBITS = 17;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_16-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_16-sl1.sv
new file mode 100644
index 000000000..7455da3da
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_16-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 48000;
+	localparam CBITS = 18;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_17-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_17-sl1.sv
new file mode 100644
index 000000000..3e08422e4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_17-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 96000;
+	localparam CBITS = 19;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_2-sl1.sv
new file mode 100644
index 000000000..955987864
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_2-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 100;
+	localparam CBITS = 9;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_3-sl1.sv
new file mode 100644
index 000000000..dfd7106e2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_3-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 200;
+	localparam CBITS = 10;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_4-sl1.sv
new file mode 100644
index 000000000..9b91ae9c2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_4-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 300;
+	localparam CBITS = 10;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_5-sl1.sv
new file mode 100644
index 000000000..a56588084
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_5-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 400;
+	localparam CBITS = 11;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_6-sl1.sv
new file mode 100644
index 000000000..e6fdcef2d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_6-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 600;
+	localparam CBITS = 11;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_7-sl1.sv
new file mode 100644
index 000000000..06ec72100
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_7-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 800;
+	localparam CBITS = 12;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_8-sl1.sv
new file mode 100644
index 000000000..790c26683
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_8-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 1000;
+	localparam CBITS = 12;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/thermocouple_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/thermocouple_9-sl1.sv
new file mode 100644
index 000000000..1f076439f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/thermocouple_9-sl1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 2000;
+	localparam CBITS = 13;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC  (G (Verilog.Thermocouple.rst = FALSE) -> G ( ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) -> ((Verilog.Thermocouple.state[1] = TRUE & Verilog.Thermocouple.state[0] = TRUE) U (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))) ))
+  assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_1-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_1-sl1.sv
new file mode 100644
index 000000000..fe239116a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_1-sl1.sv
@@ -0,0 +1,37 @@
+module UART_T #(localparam d_width = 4, c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+	assign tx_busy = tx_state;
+	always @(posedge clk) begin
+		
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_10-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_10-sl1.sv
new file mode 100644
index 000000000..30f6cbadc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_10-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 15, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_2-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_2-sl1.sv
new file mode 100644
index 000000000..3334468af
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_2-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 6, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_3-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_3-sl1.sv
new file mode 100644
index 000000000..2d2d1cc92
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_3-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 8, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_4-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_4-sl1.sv
new file mode 100644
index 000000000..d6d738ab7
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_4-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 9, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_5-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_5-sl1.sv
new file mode 100644
index 000000000..4a7e10d77
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_5-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 10, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_6-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_6-sl1.sv
new file mode 100644
index 000000000..699b979ca
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_6-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 11, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_7-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_7-sl1.sv
new file mode 100644
index 000000000..4a4077024
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_7-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 12, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_8-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_8-sl1.sv
new file mode 100644
index 000000000..3fe1d8d60
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_8-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 13, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety+Liveness/uart_transmit_9-sl1.sv b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_9-sl1.sv
new file mode 100644
index 000000000..efbbf0f07
--- /dev/null
+++ b/examples/NeurIPS2025/Safety+Liveness/uart_transmit_9-sl1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 14, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC G (Verilog.UART_T.rst = FALSE) -> G  ((Verilog.UART_T.tx_busy = TRUE) -> (Verilog.UART_T.tx_busy = TRUE U Verilog.UART_T.tx_state = FALSE))
+  assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state)));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/PWM_1-s1.sv b/examples/NeurIPS2025/Safety/PWM_1-s1.sv
new file mode 100644
index 000000000..5499c0205
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_1-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 10;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 5'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 5'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 5'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_10-s1.sv b/examples/NeurIPS2025/Safety/PWM_10-s1.sv
new file mode 100644
index 000000000..27781c875
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_10-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 19;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 14'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 14'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 14'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_11-s1.sv b/examples/NeurIPS2025/Safety/PWM_11-s1.sv
new file mode 100644
index 000000000..c8afb2c51
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_11-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 20;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 15'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 15'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 15'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_12-s1.sv b/examples/NeurIPS2025/Safety/PWM_12-s1.sv
new file mode 100644
index 000000000..ab7011b3d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_12-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 21;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 16'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 16'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 16'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_2-s1.sv b/examples/NeurIPS2025/Safety/PWM_2-s1.sv
new file mode 100644
index 000000000..90d0bc874
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_2-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 11;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 6'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 6'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 6'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_3-s1.sv b/examples/NeurIPS2025/Safety/PWM_3-s1.sv
new file mode 100644
index 000000000..7f4ec1b02
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_3-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 12;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 7'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 7'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 7'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_4-s1.sv b/examples/NeurIPS2025/Safety/PWM_4-s1.sv
new file mode 100644
index 000000000..682df6a7c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_4-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 13;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 8'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 8'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 8'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_5-s1.sv b/examples/NeurIPS2025/Safety/PWM_5-s1.sv
new file mode 100644
index 000000000..c75ce2a29
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_5-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 14;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 9'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 9'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 9'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_6-s1.sv b/examples/NeurIPS2025/Safety/PWM_6-s1.sv
new file mode 100644
index 000000000..50a3bcfcd
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_6-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 15;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 10'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 10'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 10'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_7-s1.sv b/examples/NeurIPS2025/Safety/PWM_7-s1.sv
new file mode 100644
index 000000000..bb48593e8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_7-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 16;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 11'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 11'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 11'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_8-s1.sv b/examples/NeurIPS2025/Safety/PWM_8-s1.sv
new file mode 100644
index 000000000..27d88ca5d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_8-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 17;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 12'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 12'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 12'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/PWM_9-s1.sv b/examples/NeurIPS2025/Safety/PWM_9-s1.sv
new file mode 100644
index 000000000..7118f3619
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/PWM_9-s1.sv
@@ -0,0 +1,35 @@
+module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse);
+
+  localparam CBITS = 18;    // Change pulse_wideR accordingly
+  
+  wire [CBITS-1:0] pulse_wideR;
+  assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 13'd0};     // (CBTIS-5)
+  assign lbR = {1'b0, 4'b0000, 1'b1, 13'd0};
+  assign ubR = {1'b0, 4'b1111, 1'b1, 13'd0};
+
+  reg [CBITS-1:0] cnt_R;
+
+  always @(posedge clk) begin
+    cnt_R <= cnt_R + 1;
+    
+    if (cnt_R < pulse_wideR)
+      pulse_red = 1;
+    else
+      pulse_red = 0;
+
+    if (cnt_R < lbR)
+      lb_pulse = 1;
+    else
+      lb_pulse = 0;
+    
+    if (cnt_R < ubR)
+      ub_pulse = 1;
+    else
+      ub_pulse = 0;
+  end
+
+
+  // LTLSPEC X G ((Verilog.PWM_TOP.lb_pulse = TRUE -> Verilog.PWM_TOP.pulse_red = TRUE) & (Verilog.PWM_TOP.ub_pulse = FALSE -> Verilog.PWM_TOP.pulse_red = FALSE))
+  assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red)));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_1-s1.sv b/examples/NeurIPS2025/Safety/blink_1-s1.sv
new file mode 100644
index 000000000..0540931b5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_1-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 8) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_10-s1.sv b/examples/NeurIPS2025/Safety/blink_10-s1.sv
new file mode 100644
index 000000000..463aa02e5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_10-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 17) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_11-s1.sv b/examples/NeurIPS2025/Safety/blink_11-s1.sv
new file mode 100644
index 000000000..62d8b6655
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_11-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 18) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_12-s1.sv b/examples/NeurIPS2025/Safety/blink_12-s1.sv
new file mode 100644
index 000000000..e2e8c3f47
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_12-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 19) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_13-s1.sv b/examples/NeurIPS2025/Safety/blink_13-s1.sv
new file mode 100644
index 000000000..1d5886c58
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_13-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 20) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_14-s1.sv b/examples/NeurIPS2025/Safety/blink_14-s1.sv
new file mode 100644
index 000000000..a90f7e57a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_14-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 21) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_15-s1.sv b/examples/NeurIPS2025/Safety/blink_15-s1.sv
new file mode 100644
index 000000000..594b28586
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_15-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 22) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_16-s1.sv b/examples/NeurIPS2025/Safety/blink_16-s1.sv
new file mode 100644
index 000000000..e1c3f9a71
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_16-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 23) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_17-s1.sv b/examples/NeurIPS2025/Safety/blink_17-s1.sv
new file mode 100644
index 000000000..f41619698
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_17-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 24) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_18-s1.sv b/examples/NeurIPS2025/Safety/blink_18-s1.sv
new file mode 100644
index 000000000..c9455a28a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_18-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 25) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_19-s1.sv b/examples/NeurIPS2025/Safety/blink_19-s1.sv
new file mode 100644
index 000000000..ebb1ab9d8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_19-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 26) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_2-s1.sv b/examples/NeurIPS2025/Safety/blink_2-s1.sv
new file mode 100644
index 000000000..697bc9e8b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_2-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 9) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_20-s1.sv b/examples/NeurIPS2025/Safety/blink_20-s1.sv
new file mode 100644
index 000000000..b4fa6ecca
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_20-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 27) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_21-s1.sv b/examples/NeurIPS2025/Safety/blink_21-s1.sv
new file mode 100644
index 000000000..25eec1364
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_21-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 28) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_22-s1.sv b/examples/NeurIPS2025/Safety/blink_22-s1.sv
new file mode 100644
index 000000000..9b18ccf22
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_22-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 29) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_23-s1.sv b/examples/NeurIPS2025/Safety/blink_23-s1.sv
new file mode 100644
index 000000000..d754b71b3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_23-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 30) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_24-s1.sv b/examples/NeurIPS2025/Safety/blink_24-s1.sv
new file mode 100644
index 000000000..dfed22418
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_24-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 31) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_25-s1.sv b/examples/NeurIPS2025/Safety/blink_25-s1.sv
new file mode 100644
index 000000000..cb750c6a3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_25-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 32) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_3-s1.sv b/examples/NeurIPS2025/Safety/blink_3-s1.sv
new file mode 100644
index 000000000..fbcdbfe48
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_3-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 10) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_4-s1.sv b/examples/NeurIPS2025/Safety/blink_4-s1.sv
new file mode 100644
index 000000000..4ae2fddbb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_4-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 11) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_5-s1.sv b/examples/NeurIPS2025/Safety/blink_5-s1.sv
new file mode 100644
index 000000000..4800006d4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_5-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 12) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_6-s1.sv b/examples/NeurIPS2025/Safety/blink_6-s1.sv
new file mode 100644
index 000000000..ad8bf259e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_6-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 13) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_7-s1.sv b/examples/NeurIPS2025/Safety/blink_7-s1.sv
new file mode 100644
index 000000000..8afa662f1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_7-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 14) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_8-s1.sv b/examples/NeurIPS2025/Safety/blink_8-s1.sv
new file mode 100644
index 000000000..b4885edcf
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_8-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 15) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/blink_9-s1.sv b/examples/NeurIPS2025/Safety/blink_9-s1.sv
new file mode 100644
index 000000000..6783c71b0
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/blink_9-s1.sv
@@ -0,0 +1,21 @@
+module BLINK #(localparam CBITS = 16) (input clk, input rst, output reg led, output reg flg);
+    reg [CBITS-1:0] cnt;
+    reg mode;
+    always@(posedge clk, posedge rst) begin
+        if (rst) begin
+            cnt <= 0;
+            mode <= 0;
+        end
+        else begin
+            cnt <= cnt + 1;
+            if (cnt == 0)
+                mode <= ~mode;
+            flg = (cnt == 0);
+            led = mode;
+        end       
+    end
+
+  // LTLSPEC G ((Verilog.BLINK.mode = TRUE & X Verilog.BLINK.mode = TRUE ) -> X Verilog.BLINK.flg = FALSE)
+  assert property (@(posedge clk) (mode ##1 mode |-> !flg));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_1-s1.sv b/examples/NeurIPS2025/Safety/delay_1-s1.sv
new file mode 100644
index 000000000..d1ae8629c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_1-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 750;
+  localparam CBITS = 10;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_1-s2.sv b/examples/NeurIPS2025/Safety/delay_1-s2.sv
new file mode 100644
index 000000000..ed3f8fdca
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_1-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 750;
+  localparam CBITS = 10;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_10-s1.sv b/examples/NeurIPS2025/Safety/delay_10-s1.sv
new file mode 100644
index 000000000..a86d7d94d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_10-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 20000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_10-s2.sv b/examples/NeurIPS2025/Safety/delay_10-s2.sv
new file mode 100644
index 000000000..485cb8c81
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_10-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 20000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_11-s1.sv b/examples/NeurIPS2025/Safety/delay_11-s1.sv
new file mode 100644
index 000000000..78f4284cb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_11-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 22500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_11-s2.sv b/examples/NeurIPS2025/Safety/delay_11-s2.sv
new file mode 100644
index 000000000..fa29b287c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_11-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 22500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_12-s1.sv b/examples/NeurIPS2025/Safety/delay_12-s1.sv
new file mode 100644
index 000000000..ea0303337
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_12-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 25000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_12-s2.sv b/examples/NeurIPS2025/Safety/delay_12-s2.sv
new file mode 100644
index 000000000..709fd9c32
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_12-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 25000;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_13-s1.sv b/examples/NeurIPS2025/Safety/delay_13-s1.sv
new file mode 100644
index 000000000..12d731f55
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_13-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 50000;
+  localparam CBITS = 16;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_13-s2.sv b/examples/NeurIPS2025/Safety/delay_13-s2.sv
new file mode 100644
index 000000000..fb256fff9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_13-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 50000;
+  localparam CBITS = 16;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_14-s1.sv b/examples/NeurIPS2025/Safety/delay_14-s1.sv
new file mode 100644
index 000000000..a003c1aac
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_14-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 100000;
+  localparam CBITS = 17;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_14-s2.sv b/examples/NeurIPS2025/Safety/delay_14-s2.sv
new file mode 100644
index 000000000..da2805c9c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_14-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 100000;
+  localparam CBITS = 17;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_15-s1.sv b/examples/NeurIPS2025/Safety/delay_15-s1.sv
new file mode 100644
index 000000000..03066402c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_15-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 200000;
+  localparam CBITS = 18;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_15-s2.sv b/examples/NeurIPS2025/Safety/delay_15-s2.sv
new file mode 100644
index 000000000..ef3eb7c2c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_15-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 200000;
+  localparam CBITS = 18;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_16-s1.sv b/examples/NeurIPS2025/Safety/delay_16-s1.sv
new file mode 100644
index 000000000..b5c1388cf
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_16-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 400000;
+  localparam CBITS = 19;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_16-s2.sv b/examples/NeurIPS2025/Safety/delay_16-s2.sv
new file mode 100644
index 000000000..5989bd332
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_16-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 400000;
+  localparam CBITS = 19;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_2-s1.sv b/examples/NeurIPS2025/Safety/delay_2-s1.sv
new file mode 100644
index 000000000..ac833e5ff
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_2-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 1250;
+  localparam CBITS = 11;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_2-s2.sv b/examples/NeurIPS2025/Safety/delay_2-s2.sv
new file mode 100644
index 000000000..3dc68d541
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_2-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 1250;
+  localparam CBITS = 11;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_3-s1.sv b/examples/NeurIPS2025/Safety/delay_3-s1.sv
new file mode 100644
index 000000000..b23b777b9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_3-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 2500;
+  localparam CBITS = 12;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/delay_3-s2.sv b/examples/NeurIPS2025/Safety/delay_3-s2.sv
new file mode 100644
index 000000000..3d6b77895
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_3-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 2500;
+  localparam CBITS = 12;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/delay_4-s1.sv b/examples/NeurIPS2025/Safety/delay_4-s1.sv
new file mode 100644
index 000000000..97a2d7f94
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_4-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 5000;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_4-s2.sv b/examples/NeurIPS2025/Safety/delay_4-s2.sv
new file mode 100644
index 000000000..577fd25ff
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_4-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 5000;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_5-s1.sv b/examples/NeurIPS2025/Safety/delay_5-s1.sv
new file mode 100644
index 000000000..38a579ee8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_5-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 7500;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_5-s2.sv b/examples/NeurIPS2025/Safety/delay_5-s2.sv
new file mode 100644
index 000000000..c4d739fcd
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_5-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 7500;
+  localparam CBITS = 13;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_6-s1.sv b/examples/NeurIPS2025/Safety/delay_6-s1.sv
new file mode 100644
index 000000000..7435f853e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_6-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 10000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_6-s2.sv b/examples/NeurIPS2025/Safety/delay_6-s2.sv
new file mode 100644
index 000000000..17ed5fa3b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_6-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 10000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_7-s1.sv b/examples/NeurIPS2025/Safety/delay_7-s1.sv
new file mode 100644
index 000000000..fa4d5d9dc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_7-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 12500;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_7-s2.sv b/examples/NeurIPS2025/Safety/delay_7-s2.sv
new file mode 100644
index 000000000..8a28896e6
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_7-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 12500;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_8-s1.sv b/examples/NeurIPS2025/Safety/delay_8-s1.sv
new file mode 100644
index 000000000..01dc690c2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_8-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 15000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_8-s2.sv b/examples/NeurIPS2025/Safety/delay_8-s2.sv
new file mode 100644
index 000000000..517e09bd9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_8-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 15000;
+  localparam CBITS = 14;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_9-s1.sv b/examples/NeurIPS2025/Safety/delay_9-s1.sv
new file mode 100644
index 000000000..c0b08314d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_9-s1.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 17500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC X G Verilog.DELAY.err = FALSE
+  assert property (@(posedge clk) ##1 !err);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/delay_9-s2.sv b/examples/NeurIPS2025/Safety/delay_9-s2.sv
new file mode 100644
index 000000000..f9728c6f0
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/delay_9-s2.sv
@@ -0,0 +1,16 @@
+module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg);
+  localparam N = 17500;
+  localparam CBITS = 15;
+  reg [CBITS-1 :0] cnt;
+  assign sig = (cnt >= N);
+  assign err = (cnt > N);
+  assign flg = (cnt < N);
+  always @(posedge clk) begin
+    if (rst || cnt >= N) cnt <= 0;
+    else cnt <= cnt + 1; 
+  end
+
+  // LTLSPEC G (Verilog.DELAY.sig = TRUE -> X Verilog.DELAY.sig = FALSE)
+  assert property (@(posedge clk) sig |=> !sig);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/gray_1-s1.sv b/examples/NeurIPS2025/Safety/gray_1-s1.sv
new file mode 100644
index 000000000..addc2cf25
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_1-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_10-s1.sv b/examples/NeurIPS2025/Safety/gray_10-s1.sv
new file mode 100644
index 000000000..cf2cb663f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_10-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_11-s1.sv b/examples/NeurIPS2025/Safety/gray_11-s1.sv
new file mode 100644
index 000000000..7531b545b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_11-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_2-s1.sv b/examples/NeurIPS2025/Safety/gray_2-s1.sv
new file mode 100644
index 000000000..1dd41b6ba
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_2-s1.sv
@@ -0,0 +1,18 @@
+module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/gray_3-s1.sv b/examples/NeurIPS2025/Safety/gray_3-s1.sv
new file mode 100644
index 000000000..23b45f7f6
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_3-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_4-s1.sv b/examples/NeurIPS2025/Safety/gray_4-s1.sv
new file mode 100644
index 000000000..6237adce2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_4-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_5-s1.sv b/examples/NeurIPS2025/Safety/gray_5-s1.sv
new file mode 100644
index 000000000..bafbe2764
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_5-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_6-s1.sv b/examples/NeurIPS2025/Safety/gray_6-s1.sv
new file mode 100644
index 000000000..5f217af7c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_6-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_7-s1.sv b/examples/NeurIPS2025/Safety/gray_7-s1.sv
new file mode 100644
index 000000000..c27e7814e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_7-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_8-s1.sv b/examples/NeurIPS2025/Safety/gray_8-s1.sv
new file mode 100644
index 000000000..48e30f5de
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_8-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/gray_9-s1.sv b/examples/NeurIPS2025/Safety/gray_9-s1.sv
new file mode 100644
index 000000000..8f3e5ac4b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/gray_9-s1.sv
@@ -0,0 +1,17 @@
+module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg);
+  reg [CBITS-1:0] cnt;
+  assign sig = (cnt == 0) & ~rst;
+  assign flg = (cnt >= 0);
+  always@(posedge clk, posedge rst) begin
+    if (rst)
+      cnt <= 0;
+    else begin
+      cnt <= cnt + 1;
+      gray_c = (cnt) ^ ((cnt) >> 1);
+    end
+  end
+
+  // LTLSPEC X G ((Verilog.GRAY.sig = TRUE & Verilog.GRAY.rst = FALSE) -> X Verilog.GRAY.sig = FALSE)
+  assert property (@(posedge clk) sig && !rst |=> !sig);
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/i2c_1-s1.sv b/examples/NeurIPS2025/Safety/i2c_1-s1.sv
new file mode 100644
index 000000000..f49ef46fa
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_1-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 3;
+	localparam CBITS = 4;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_10-s1.sv b/examples/NeurIPS2025/Safety/i2c_10-s1.sv
new file mode 100644
index 000000000..39efae7a8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_10-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 4000;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_11-s1.sv b/examples/NeurIPS2025/Safety/i2c_11-s1.sv
new file mode 100644
index 000000000..dfd07ce38
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_11-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 4500;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_12-s1.sv b/examples/NeurIPS2025/Safety/i2c_12-s1.sv
new file mode 100644
index 000000000..c88d412e3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_12-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 5000;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_13-s1.sv b/examples/NeurIPS2025/Safety/i2c_13-s1.sv
new file mode 100644
index 000000000..958240bec
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_13-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 5500;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_14-s1.sv b/examples/NeurIPS2025/Safety/i2c_14-s1.sv
new file mode 100644
index 000000000..bea8ee703
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_14-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 6000;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_15-s1.sv b/examples/NeurIPS2025/Safety/i2c_15-s1.sv
new file mode 100644
index 000000000..56d45b511
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_15-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 6500;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_16-s1.sv b/examples/NeurIPS2025/Safety/i2c_16-s1.sv
new file mode 100644
index 000000000..1d88e6be8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_16-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 7000;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_17-s1.sv b/examples/NeurIPS2025/Safety/i2c_17-s1.sv
new file mode 100644
index 000000000..cbf77ecbb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_17-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 10000;
+	localparam CBITS = 16;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_18-s1.sv b/examples/NeurIPS2025/Safety/i2c_18-s1.sv
new file mode 100644
index 000000000..847b3058c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_18-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 17500;
+	localparam CBITS = 17;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_19-s1.sv b/examples/NeurIPS2025/Safety/i2c_19-s1.sv
new file mode 100644
index 000000000..651a30bdc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_19-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 35000;
+	localparam CBITS = 18;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_2-s1.sv b/examples/NeurIPS2025/Safety/i2c_2-s1.sv
new file mode 100644
index 000000000..159a4bc92
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_2-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 250;
+	localparam CBITS = 10;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_20-s1.sv b/examples/NeurIPS2025/Safety/i2c_20-s1.sv
new file mode 100644
index 000000000..488faec26
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_20-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 70000;
+	localparam CBITS = 19;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_3-s1.sv b/examples/NeurIPS2025/Safety/i2c_3-s1.sv
new file mode 100644
index 000000000..a6cdba7a7
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_3-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 500;
+	localparam CBITS = 11;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_4-s1.sv b/examples/NeurIPS2025/Safety/i2c_4-s1.sv
new file mode 100644
index 000000000..6b51a7d22
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_4-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 1000;
+	localparam CBITS = 12;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_5-s1.sv b/examples/NeurIPS2025/Safety/i2c_5-s1.sv
new file mode 100644
index 000000000..eddf0addb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_5-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 1500;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_6-s1.sv b/examples/NeurIPS2025/Safety/i2c_6-s1.sv
new file mode 100644
index 000000000..079db2fb2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_6-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 2000;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_7-s1.sv b/examples/NeurIPS2025/Safety/i2c_7-s1.sv
new file mode 100644
index 000000000..17f841209
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_7-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 2500;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_8-s1.sv b/examples/NeurIPS2025/Safety/i2c_8-s1.sv
new file mode 100644
index 000000000..e1fb89fd2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_8-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 3000;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/i2c_9-s1.sv b/examples/NeurIPS2025/Safety/i2c_9-s1.sv
new file mode 100644
index 000000000..a8d5ae226
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/i2c_9-s1.sv
@@ -0,0 +1,46 @@
+module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range);
+	localparam divider = 3500;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;	//0 to 4*divider
+	reg scl_clk;
+	reg stretch;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			stretch = 0;
+			cnt = 0;
+		end
+		if(cnt >= divider*4 - 1)
+			cnt = 0;
+		else if(stretch == 0)
+			cnt = cnt + 1;
+
+		if( cnt <= divider - 1) begin
+			scl_clk = 0;
+			data_clk = 0;
+		end
+		else if( divider <= cnt && cnt <= 2*divider - 1) begin
+			scl_clk = 0;
+			data_clk = 1;
+		end
+		else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin
+			if(scl_clk == 0 & scl_not_ena == 0)
+				stretch = 1;
+			else
+				stretch = 0;
+			scl_clk = 1;
+			data_clk = 1;
+		end
+		else begin
+			scl_clk = 1;
+			data_clk = 0;
+		end
+		if(2*divider <= cnt && cnt <= 3*divider - 1)
+        	switch_range = 1;
+      	else
+        	switch_range = 0;
+	end
+
+  // LTLSPEC X G ((Verilog.i2cStrech.stretch = FALSE & X Verilog.i2cStrech.stretch = TRUE) -> X Verilog.i2cStrech.switch_range = TRUE)
+  assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range);
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/lcd_1-s1.sv b/examples/NeurIPS2025/Safety/lcd_1-s1.sv
new file mode 100644
index 000000000..29b85ed2e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_1-s1.sv
@@ -0,0 +1,110 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 1;
+	localparam CBITS = 9;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+				busy = 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+				busy = 1;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_1-s2.sv b/examples/NeurIPS2025/Safety/lcd_1-s2.sv
new file mode 100644
index 000000000..778d99d2f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_1-s2.sv
@@ -0,0 +1,110 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 1;
+	localparam CBITS = 9;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+				busy = 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+				busy = 1;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_10-s1.sv b/examples/NeurIPS2025/Safety/lcd_10-s1.sv
new file mode 100644
index 000000000..1b527ed4c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_10-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 35;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_10-s2.sv b/examples/NeurIPS2025/Safety/lcd_10-s2.sv
new file mode 100644
index 000000000..ae0122547
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_10-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 35;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_11-s1.sv b/examples/NeurIPS2025/Safety/lcd_11-s1.sv
new file mode 100644
index 000000000..269bb2c18
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_11-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 40;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_11-s2.sv b/examples/NeurIPS2025/Safety/lcd_11-s2.sv
new file mode 100644
index 000000000..8878d4489
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_11-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 40;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_12-s1.sv b/examples/NeurIPS2025/Safety/lcd_12-s1.sv
new file mode 100644
index 000000000..056947b13
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_12-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 45;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_12-s2.sv b/examples/NeurIPS2025/Safety/lcd_12-s2.sv
new file mode 100644
index 000000000..1ac3aef03
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_12-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 45;
+	localparam CBITS = 15;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_13-s1.sv b/examples/NeurIPS2025/Safety/lcd_13-s1.sv
new file mode 100644
index 000000000..30580a0cf
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_13-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 180;
+	localparam CBITS = 17;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_13-s2.sv b/examples/NeurIPS2025/Safety/lcd_13-s2.sv
new file mode 100644
index 000000000..88575785f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_13-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 180;
+	localparam CBITS = 17;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_14-s1.sv b/examples/NeurIPS2025/Safety/lcd_14-s1.sv
new file mode 100644
index 000000000..b5ae83455
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_14-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 360;
+	localparam CBITS = 18;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_14-s2.sv b/examples/NeurIPS2025/Safety/lcd_14-s2.sv
new file mode 100644
index 000000000..866ec86f5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_14-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 360;
+	localparam CBITS = 18;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_2-s1.sv b/examples/NeurIPS2025/Safety/lcd_2-s1.sv
new file mode 100644
index 000000000..8fdde738a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_2-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 2;
+	localparam CBITS = 10;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_2-s2.sv b/examples/NeurIPS2025/Safety/lcd_2-s2.sv
new file mode 100644
index 000000000..c6e8e082d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_2-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 2;
+	localparam CBITS = 10;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_3-s1.sv b/examples/NeurIPS2025/Safety/lcd_3-s1.sv
new file mode 100644
index 000000000..0eb8e47ef
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_3-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 3;
+	localparam CBITS = 11;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_3-s2.sv b/examples/NeurIPS2025/Safety/lcd_3-s2.sv
new file mode 100644
index 000000000..4e3b6656b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_3-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 3;
+	localparam CBITS = 11;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_4-s1.sv b/examples/NeurIPS2025/Safety/lcd_4-s1.sv
new file mode 100644
index 000000000..e002024ad
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_4-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 5;
+	localparam CBITS = 12;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_4-s2.sv b/examples/NeurIPS2025/Safety/lcd_4-s2.sv
new file mode 100644
index 000000000..dffec1b0f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_4-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 5;
+	localparam CBITS = 12;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_5-s1.sv b/examples/NeurIPS2025/Safety/lcd_5-s1.sv
new file mode 100644
index 000000000..253e04148
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_5-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 10;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_5-s2.sv b/examples/NeurIPS2025/Safety/lcd_5-s2.sv
new file mode 100644
index 000000000..f343c5d71
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_5-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 10;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_6-s1.sv b/examples/NeurIPS2025/Safety/lcd_6-s1.sv
new file mode 100644
index 000000000..d05b5ed3e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_6-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 15;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_6-s2.sv b/examples/NeurIPS2025/Safety/lcd_6-s2.sv
new file mode 100644
index 000000000..520c3b6b8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_6-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 15;
+	localparam CBITS = 13;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_7-s1.sv b/examples/NeurIPS2025/Safety/lcd_7-s1.sv
new file mode 100644
index 000000000..05354563b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_7-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 20;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_7-s2.sv b/examples/NeurIPS2025/Safety/lcd_7-s2.sv
new file mode 100644
index 000000000..711e95ee3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_7-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 20;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_8-s1.sv b/examples/NeurIPS2025/Safety/lcd_8-s1.sv
new file mode 100644
index 000000000..008641cb1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_8-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 25;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_8-s2.sv b/examples/NeurIPS2025/Safety/lcd_8-s2.sv
new file mode 100644
index 000000000..8cb6b3619
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_8-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 25;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_9-s1.sv b/examples/NeurIPS2025/Safety/lcd_9-s1.sv
new file mode 100644
index 000000000..49091fccf
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_9-s1.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 30;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G (Verilog.LCD.lcd_enable = FALSE & Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE) -> X (Verilog.LCD.state[1] = TRUE & Verilog.LCD.state[0] = FALSE)
+  assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2);
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/lcd_9-s2.sv b/examples/NeurIPS2025/Safety/lcd_9-s2.sv
new file mode 100644
index 000000000..6e97146d5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/lcd_9-s2.sv
@@ -0,0 +1,108 @@
+module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy);
+	//in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift}
+	localparam clk_freq = 30;
+	localparam CBITS = 14;
+	reg [CBITS - 1:0] cnt;			// 0 to 500*clk_freg
+	reg [1:0] state;
+
+	always @(posedge clk) begin
+		rw = 0;
+		rs = 0;
+		busy = 0;
+		lcd_data = 0;
+		e = 0;
+		if(state == 0) begin
+			busy = 1;
+			if(cnt < 500*clk_freq)				// wait 500
+				cnt = cnt + 1;
+			else begin							// power-up completed
+				cnt = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00110000;
+				state = 1;
+			end
+		end
+		if(state == 1) begin
+			busy = 1;
+			cnt = cnt + 1;
+			if(cnt < (10*clk_freq))begin			//function set
+				lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00};
+				e = 1;
+			end
+			else if(cnt < (60*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (70*clk_freq))begin		//display on/off control
+				lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]};
+				e = 1;
+			end
+			else if(cnt < (120*clk_freq))begin		// wait 50
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (130*clk_freq))begin		// display clear
+				lcd_data = 8'b00000001;
+				e = 1;
+			end
+			else if(cnt < (330*clk_freq))begin		// wait 200
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else if(cnt < (340*clk_freq))begin		// entry mode set
+				lcd_data = {6'b000001, in_data[1], in_data[0]};
+				e = 1;
+			end
+			else if(cnt < (440*clk_freq))begin		// wait 100
+				lcd_data = 8'b00000000;
+				e = 0;
+			end
+			else begin								// initialization complete
+				cnt = 0;
+				busy = 0;
+				state = 2;
+			end
+		end
+		if(state == 2) begin
+			if(lcd_enable == 1) begin
+				busy = 1;
+				rs = lcd_bus[9];
+				rw = lcd_bus[8];
+				lcd_data = lcd_bus[7:0];
+				cnt = 0;
+				state = 3;
+			end
+			else begin
+				busy = 0;
+				rs = 0;
+				rw = 0;
+				lcd_data = 8'b00000000;
+				cnt = 0;
+			end
+		end
+		if(state == 3) begin
+			if(cnt < 50* clk_freq) begin 		// do not exit for 50
+				if(cnt < clk_freq)
+					e = 0;
+				else if(cnt < 14*clk_freq)		// positive enable half-cycle
+					e = 1;
+				else if(cnt < 27*clk_freq)		// negative enable half-cycle
+					e = 0;
+				cnt = cnt + 1;
+			end
+			else begin
+				cnt = 0;
+				state = 2;
+			end
+		end
+	end
+
+  // LTLSPEC X G ( X ( Verilog.LCD.state[1] = FALSE &  Verilog.LCD.state[0] = TRUE)  ->  (Verilog.LCD.busy = TRUE))
+  assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy));
+
+endmodule
+
+
+
+
diff --git a/examples/NeurIPS2025/Safety/load_store_1-s1.sv b/examples/NeurIPS2025/Safety/load_store_1-s1.sv
new file mode 100644
index 000000000..aa59e8c79
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_1-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 750;
+    localparam CBITS = 10;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_10-s1.sv b/examples/NeurIPS2025/Safety/load_store_10-s1.sv
new file mode 100644
index 000000000..e82651cfa
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_10-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 20000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_11-s1.sv b/examples/NeurIPS2025/Safety/load_store_11-s1.sv
new file mode 100644
index 000000000..7111231e9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_11-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 22500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_12-s1.sv b/examples/NeurIPS2025/Safety/load_store_12-s1.sv
new file mode 100644
index 000000000..100d51cd9
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_12-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 25000;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_13-s1.sv b/examples/NeurIPS2025/Safety/load_store_13-s1.sv
new file mode 100644
index 000000000..96638ad18
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_13-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 50000;
+    localparam CBITS = 16;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_14-s1.sv b/examples/NeurIPS2025/Safety/load_store_14-s1.sv
new file mode 100644
index 000000000..35ce3d7da
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_14-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 100000;
+    localparam CBITS = 17;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_15-s1.sv b/examples/NeurIPS2025/Safety/load_store_15-s1.sv
new file mode 100644
index 000000000..c4fa9854c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_15-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 200000;
+    localparam CBITS = 18;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_16-s1.sv b/examples/NeurIPS2025/Safety/load_store_16-s1.sv
new file mode 100644
index 000000000..868b92b9f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_16-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 400000;
+    localparam CBITS = 19;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_2-s1.sv b/examples/NeurIPS2025/Safety/load_store_2-s1.sv
new file mode 100644
index 000000000..a58ee02ae
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_2-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 1250;
+    localparam CBITS = 11;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_3-s1.sv b/examples/NeurIPS2025/Safety/load_store_3-s1.sv
new file mode 100644
index 000000000..4a6d92b4f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_3-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 2500;
+    localparam CBITS = 12;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_4-s1.sv b/examples/NeurIPS2025/Safety/load_store_4-s1.sv
new file mode 100644
index 000000000..af2e19a1c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_4-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 5000;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_5-s1.sv b/examples/NeurIPS2025/Safety/load_store_5-s1.sv
new file mode 100644
index 000000000..8d5670ddb
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_5-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 7500;
+    localparam CBITS = 13;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_6-s1.sv b/examples/NeurIPS2025/Safety/load_store_6-s1.sv
new file mode 100644
index 000000000..0b4f4e05d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_6-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 10000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_7-s1.sv b/examples/NeurIPS2025/Safety/load_store_7-s1.sv
new file mode 100644
index 000000000..ef798cd0c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_7-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 12500;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_8-s1.sv b/examples/NeurIPS2025/Safety/load_store_8-s1.sv
new file mode 100644
index 000000000..8528b2b6f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_8-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 15000;
+    localparam CBITS = 14;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/load_store_9-s1.sv b/examples/NeurIPS2025/Safety/load_store_9-s1.sv
new file mode 100644
index 000000000..c54835933
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/load_store_9-s1.sv
@@ -0,0 +1,26 @@
+module Load_Store (input clk, input rst, output reg sig);
+    localparam N = 17500;
+    localparam CBITS = 15;
+    reg [CBITS-1:0] vol;
+    reg m;
+    always @(posedge clk) begin
+        if (rst) begin m = 0; vol = 0; sig = 0;
+        end else begin
+            if (m) begin
+                if (vol >= N) m = 0; else vol = vol + 1;
+            end else begin
+                if (vol <= 0) m = 1; else vol = vol - 1;
+            end
+            if (vol >= N) begin
+                sig = 1;
+                vol = N;
+            end
+            else
+                sig = 0; 
+        end 
+    end
+
+  // LTLSPEC X G (Verilog.Load_Store.sig = TRUE  -> X X Verilog.Load_Store.sig = FALSE)
+  assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/seven_seg_1-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_1-s1.sv
new file mode 100644
index 000000000..139fe0b32
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_1-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 250;
+	localparam CBITS = 8;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_10-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_10-s1.sv
new file mode 100644
index 000000000..d4d59b976
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_10-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 15000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_11-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_11-s1.sv
new file mode 100644
index 000000000..0a55ba5da
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_11-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 17500;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_12-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_12-s1.sv
new file mode 100644
index 000000000..555b4a253
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_12-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 20000;
+	localparam CBITS = 15;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_13-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_13-s1.sv
new file mode 100644
index 000000000..5eed44bb3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_13-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 40000;
+	localparam CBITS = 16;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_14-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_14-s1.sv
new file mode 100644
index 000000000..131ebd9e1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_14-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 80000;
+	localparam CBITS = 17;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_15-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_15-s1.sv
new file mode 100644
index 000000000..15f37b0bc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_15-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 160000;
+	localparam CBITS = 18;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_2-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_2-s1.sv
new file mode 100644
index 000000000..a51b41e32
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_2-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 500;
+	localparam CBITS = 9;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_3-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_3-s1.sv
new file mode 100644
index 000000000..8f1f8e55d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_3-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 750;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_4-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_4-s1.sv
new file mode 100644
index 000000000..62e62398a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_4-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 1000;
+	localparam CBITS = 10;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_5-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_5-s1.sv
new file mode 100644
index 000000000..f510a7b57
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_5-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 2500;
+	localparam CBITS = 12;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_6-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_6-s1.sv
new file mode 100644
index 000000000..d396858b6
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_6-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 5000;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_7-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_7-s1.sv
new file mode 100644
index 000000000..64e283191
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_7-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 7500;
+	localparam CBITS = 13;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_8-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_8-s1.sv
new file mode 100644
index 000000000..5e13fc819
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_8-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 10000;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/seven_seg_9-s1.sv b/examples/NeurIPS2025/Safety/seven_seg_9-s1.sv
new file mode 100644
index 000000000..a63b09f7f
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/seven_seg_9-s1.sv
@@ -0,0 +1,35 @@
+module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig);
+	localparam freq = 12500;
+	localparam CBITS = 14;
+
+	reg [CBITS-1:0] cnt;
+	reg digit_select;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			cnt = 0;
+			digit_select = 0;
+			segment = 0;
+		end
+		if(cnt < freq) begin
+			cnt = cnt + 1;
+			sig = 0;
+		end
+		else begin
+			sig = 1;
+			cnt = 0;
+			if(digit_select == 0) begin
+				digit_select = 1;
+				segment = both7seg[13:7];
+			end
+			else begin
+				digit_select = 0;
+				segment = both7seg[6:0];
+			end
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.SEVEN.sig = FALSE & X Verilog.SEVEN.sig = FALSE & Verilog.SEVEN.rst = FALSE) -> ( (Verilog.SEVEN.digit_select = TRUE & X Verilog.SEVEN.digit_select = TRUE) | (Verilog.SEVEN.digit_select = FALSE & X Verilog.SEVEN.digit_select = FALSE) ) )
+  assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/thermocouple_1-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_1-s1.sv
new file mode 100644
index 000000000..b35986b69
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_1-s1.sv
@@ -0,0 +1,50 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 10;
+	localparam CBITS = 6;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/thermocouple_10-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_10-s1.sv
new file mode 100644
index 000000000..89531eba5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_10-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 3000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_11-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_11-s1.sv
new file mode 100644
index 000000000..ed5867dd1
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_11-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 4000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_12-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_12-s1.sv
new file mode 100644
index 000000000..af0f20246
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_12-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 5000;
+	localparam CBITS = 14;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_13-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_13-s1.sv
new file mode 100644
index 000000000..072739b3e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_13-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 6000;
+	localparam CBITS = 15;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_14-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_14-s1.sv
new file mode 100644
index 000000000..06169cb3e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_14-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 12000;
+	localparam CBITS = 16;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_15-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_15-s1.sv
new file mode 100644
index 000000000..2790df49e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_15-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 24000;
+	localparam CBITS = 17;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_16-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_16-s1.sv
new file mode 100644
index 000000000..c59e1d264
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_16-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 48000;
+	localparam CBITS = 18;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_17-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_17-s1.sv
new file mode 100644
index 000000000..7bd00fb3b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_17-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 96000;
+	localparam CBITS = 19;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_2-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_2-s1.sv
new file mode 100644
index 000000000..0f676d63d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_2-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 100;
+	localparam CBITS = 9;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_3-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_3-s1.sv
new file mode 100644
index 000000000..0a2c1ac7b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_3-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 200;
+	localparam CBITS = 10;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_4-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_4-s1.sv
new file mode 100644
index 000000000..dd6ebb198
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_4-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 300;
+	localparam CBITS = 10;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_5-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_5-s1.sv
new file mode 100644
index 000000000..81c437b72
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_5-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 400;
+	localparam CBITS = 11;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_6-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_6-s1.sv
new file mode 100644
index 000000000..0a3ebd3ca
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_6-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 600;
+	localparam CBITS = 11;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_7-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_7-s1.sv
new file mode 100644
index 000000000..d34ad6b3a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_7-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 800;
+	localparam CBITS = 12;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_8-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_8-s1.sv
new file mode 100644
index 000000000..6a246faf6
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_8-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 1000;
+	localparam CBITS = 12;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/thermocouple_9-s1.sv b/examples/NeurIPS2025/Safety/thermocouple_9-s1.sv
new file mode 100644
index 000000000..dba92ad2d
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/thermocouple_9-s1.sv
@@ -0,0 +1,49 @@
+module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits);
+	localparam clk_freq = 2000;
+	localparam CBITS = 13;			// 2^CBITS > clk_freq*3
+	reg spi_ena;
+	reg [1:0] state;
+	reg [CBITS-1:0] cnt;
+	always @(posedge clk)
+		if(rst == 1) begin
+			spi_ena = 0;
+			tc_temp_data = 0;
+			junction_temp_data = 0;
+			fault_bits = 0;
+			state = 0;
+			cnt = 0;
+		end
+		else if(state == 0) begin
+			if(cnt < clk_freq * 3)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else if(state == 1) begin
+			if(spi_not_busy == 1)
+				spi_ena = 1;
+			else begin
+				spi_ena = 0;
+				state = 2;
+			end
+		end
+		else if(state == 2) begin
+			tc_temp_data = spi_rx_data [31:18];
+			junction_temp_data = spi_rx_data [15:4];
+			fault_bits = {spi_rx_data[16], spi_rx_data[2:0]};
+			if(cnt < clk_freq * 1)
+				cnt = cnt + 1;
+			else begin
+				cnt = 0;
+				state = 1;
+			end
+		end
+		else
+			state = 1;
+
+  // LTLSPEC X G ((Verilog.Thermocouple.spi_not_busy = TRUE & Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE & Verilog.Thermocouple.rst = FALSE) -> X (Verilog.Thermocouple.state[1] = FALSE & Verilog.Thermocouple.state[0] = TRUE))
+  assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1));
+
+endmodule
\ No newline at end of file
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_1-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_1-s1.sv
new file mode 100644
index 000000000..4584b6aed
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_1-s1.sv
@@ -0,0 +1,37 @@
+module UART_T #(localparam d_width = 4, c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+	assign tx_busy = tx_state;
+	always @(posedge clk) begin
+		
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_10-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_10-s1.sv
new file mode 100644
index 000000000..da28f6734
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_10-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 15, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_2-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_2-s1.sv
new file mode 100644
index 000000000..da30b6283
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_2-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 6, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_3-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_3-s1.sv
new file mode 100644
index 000000000..c9b6a07fc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_3-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 8, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_4-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_4-s1.sv
new file mode 100644
index 000000000..a278fec3e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_4-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 9, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_5-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_5-s1.sv
new file mode 100644
index 000000000..b87ccf8b2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_5-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 10, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_6-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_6-s1.sv
new file mode 100644
index 000000000..4fd64960b
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_6-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 11, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_7-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_7-s1.sv
new file mode 100644
index 000000000..d5c6eb0d6
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_7-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 12, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_8-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_8-s1.sv
new file mode 100644
index 000000000..0efe88d30
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_8-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 13, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/uart_transmit_9-s1.sv b/examples/NeurIPS2025/Safety/uart_transmit_9-s1.sv
new file mode 100644
index 000000000..5528884e3
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/uart_transmit_9-s1.sv
@@ -0,0 +1,42 @@
+module UART_T #(localparam d_width = 14, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy);
+	//2^c_width > d_width+3
+	reg [c_width-1:0] tx_cnt;
+	reg tx_state;
+	reg [d_width+1:0] tx_buffer;
+
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			tx_cnt = 0;
+			tx = 1;
+			tx_busy = 0;
+			tx_state = 0;
+		end
+		if(tx_state == 0) begin
+			if(tx_ena == 1) begin
+				tx_buffer = {tx_data, 2'b01};
+				tx_busy = 1;
+				tx_cnt = 0;
+				tx_state = 1;
+			end
+			else
+				tx_busy = 0;
+		end
+		else if(tx_state == 1) begin
+			if(tx_cnt < d_width+3) begin
+				tx_busy = 1;
+				tx_cnt = tx_cnt + 1;
+				tx_buffer = {1'b1, tx_buffer[d_width+1:1]};
+			end
+			else begin
+				tx_cnt = 0;
+				tx_state = 0;
+				tx_busy = 0;
+			end
+		end
+		tx = tx_buffer[0];
+	end
+
+  // LTLSPEC X G ((Verilog.UART_T.tx_state = TRUE -> Verilog.UART_T.tx_busy = TRUE) & (Verilog.UART_T.tx_state = FALSE -> Verilog.UART_T.tx_busy = FALSE))
+  assert property (@(posedge clk) ##1 (tx_state <-> tx_busy));
+
+endmodule
diff --git a/examples/NeurIPS2025/Safety/vga_1-s1.sv b/examples/NeurIPS2025/Safety/vga_1-s1.sv
new file mode 100644
index 000000000..739a75dd7
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_1-s1.sv
@@ -0,0 +1,70 @@
+module VGA #(localparam  size = 1, h_bits =7, v_bits = 5)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
+
+
diff --git a/examples/NeurIPS2025/Safety/vga_1-s2.sv b/examples/NeurIPS2025/Safety/vga_1-s2.sv
new file mode 100644
index 000000000..dc7ee5161
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_1-s2.sv
@@ -0,0 +1,70 @@
+module VGA #(localparam  size = 1, h_bits =7, v_bits = 5)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
+
+
diff --git a/examples/NeurIPS2025/Safety/vga_10-s1.sv b/examples/NeurIPS2025/Safety/vga_10-s1.sv
new file mode 100644
index 000000000..d70e581d5
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_10-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 16, h_bits =11, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_10-s2.sv b/examples/NeurIPS2025/Safety/vga_10-s2.sv
new file mode 100644
index 000000000..9ac6e9dbc
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_10-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 16, h_bits =11, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_2-s1.sv b/examples/NeurIPS2025/Safety/vga_2-s1.sv
new file mode 100644
index 000000000..93041b63a
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_2-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 2, h_bits =8, v_bits = 6)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_2-s2.sv b/examples/NeurIPS2025/Safety/vga_2-s2.sv
new file mode 100644
index 000000000..b4f04fc99
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_2-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 2, h_bits =8, v_bits = 6)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_3-s1.sv b/examples/NeurIPS2025/Safety/vga_3-s1.sv
new file mode 100644
index 000000000..b36350215
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_3-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 3, h_bits =8, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_3-s2.sv b/examples/NeurIPS2025/Safety/vga_3-s2.sv
new file mode 100644
index 000000000..fa485078c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_3-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 3, h_bits =8, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_4-s1.sv b/examples/NeurIPS2025/Safety/vga_4-s1.sv
new file mode 100644
index 000000000..6c952aef7
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_4-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 4, h_bits =9, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_4-s2.sv b/examples/NeurIPS2025/Safety/vga_4-s2.sv
new file mode 100644
index 000000000..8bde4fba8
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_4-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 4, h_bits =9, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_5-s1.sv b/examples/NeurIPS2025/Safety/vga_5-s1.sv
new file mode 100644
index 000000000..4a5123151
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_5-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 5, h_bits =9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_5-s2.sv b/examples/NeurIPS2025/Safety/vga_5-s2.sv
new file mode 100644
index 000000000..6fda0a2df
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_5-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 5, h_bits =9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_6-s1.sv b/examples/NeurIPS2025/Safety/vga_6-s1.sv
new file mode 100644
index 000000000..8359cc77c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_6-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 6, h_bits = 9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_6-s2.sv b/examples/NeurIPS2025/Safety/vga_6-s2.sv
new file mode 100644
index 000000000..59eb99ab4
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_6-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 6, h_bits = 9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_7-s1.sv b/examples/NeurIPS2025/Safety/vga_7-s1.sv
new file mode 100644
index 000000000..e137cc90c
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_7-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 8, h_bits = 10, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_7-s2.sv b/examples/NeurIPS2025/Safety/vga_7-s2.sv
new file mode 100644
index 000000000..f243935a0
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_7-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 8, h_bits = 10, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_8-s1.sv b/examples/NeurIPS2025/Safety/vga_8-s1.sv
new file mode 100644
index 000000000..0b0da6a4e
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_8-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 10, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_8-s2.sv b/examples/NeurIPS2025/Safety/vga_8-s2.sv
new file mode 100644
index 000000000..6f2bd3449
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_8-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 10, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_9-s1.sv b/examples/NeurIPS2025/Safety/vga_9-s1.sv
new file mode 100644
index 000000000..7bd34ace2
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_9-s1.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 12, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.h_sync = TRUE <-> X Verilog.VGA.h_sync = FALSE) | (Verilog.VGA.h_sync = FALSE <-> X Verilog.VGA.h_sync = TRUE)))
+  assert property (@(posedge clk)  (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) ));
+
+endmodule
+
diff --git a/examples/NeurIPS2025/Safety/vga_9-s2.sv b/examples/NeurIPS2025/Safety/vga_9-s2.sv
new file mode 100644
index 000000000..c4d9077fe
--- /dev/null
+++ b/examples/NeurIPS2025/Safety/vga_9-s2.sv
@@ -0,0 +1,68 @@
+module VGA #(localparam  size = 12, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row);
+	localparam h_pixels = 50*size;
+	localparam h_pulse = 5*size;
+	localparam h_bp = 8*size;
+	localparam h_fp = 3*size;
+	localparam h_pol = 0;
+
+	localparam v_pixels =  25*size;
+	localparam v_pulse = size;
+	localparam v_bp = 1*size;
+	localparam v_fp = size;
+	localparam v_pol = 1;
+
+	localparam h_period = h_pulse + h_bp + h_pixels + h_fp;
+	localparam v_period = v_pulse + v_bp + v_pixels + v_fp;
+
+	reg [h_bits-1:0] h_cnt;
+	reg [v_bits-1:0] v_cnt;
+	reg h_sync;
+	reg v_sync;
+	always @(posedge clk) begin
+		if(rst == 1) begin
+			h_cnt = 0;
+			v_cnt = 0;
+			h_sync = ~h_sync;
+			v_sync = ~v_sync;
+			disp_ena = 0;
+			col = 0;
+			row = 0;
+		end
+		else begin
+			if(h_cnt < h_period - 1)
+				h_cnt = h_cnt + 1;
+			else begin
+				h_cnt = 0;
+				if(v_cnt < v_period - 1)
+					v_cnt = v_cnt + 1;
+				else
+					v_cnt = 0;
+			end
+			if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse)))
+				h_sync = ~h_sync;
+			else
+				h_sync = h_pol;
+
+			if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse)))
+				v_sync = ~v_sync;
+			else
+				v_sync = v_pol;
+
+			if(h_cnt < h_pixels)
+				col = h_cnt;
+
+			if(v_cnt < v_pixels)
+				row = v_cnt;
+
+			if(h_cnt < h_pixels & v_cnt < v_pixels)
+				disp_ena = 1;
+			else
+				disp_ena = 0;
+		end
+	end
+
+  // LTLSPEC X G ((Verilog.VGA.disp_ena = TRUE & Verilog.VGA.rst = FALSE) -> ((Verilog.VGA.v_sync = TRUE <-> X Verilog.VGA.v_sync = FALSE) | (Verilog.VGA.v_sync = FALSE <-> X Verilog.VGA.v_sync = TRUE)))
+  assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync)));
+
+endmodule
+