diff --git a/examples/Benchmarks/PWM_1-s1.sv b/examples/Benchmarks/PWM_1-s1.sv new file mode 100644 index 000000000..c7ced2a82 --- /dev/null +++ b/examples/Benchmarks/PWM_1-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 10; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 5'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 5'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 5'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_1-sl1.sv b/examples/Benchmarks/PWM_1-sl1.sv new file mode 100644 index 000000000..c731b4992 --- /dev/null +++ b/examples/Benchmarks/PWM_1-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 10; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 5'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 5'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 5'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_1.sv b/examples/Benchmarks/PWM_1.sv index 9e6f627d7..70659590e 100644 --- a/examples/Benchmarks/PWM_1.sv +++ b/examples/Benchmarks/PWM_1.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 10) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 10; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 6'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 5'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 5'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 5'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_10-s1.sv b/examples/Benchmarks/PWM_10-s1.sv new file mode 100644 index 000000000..68110dda4 --- /dev/null +++ b/examples/Benchmarks/PWM_10-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 19; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 14'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 14'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 14'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_10-sl1.sv b/examples/Benchmarks/PWM_10-sl1.sv new file mode 100644 index 000000000..64c77d851 --- /dev/null +++ b/examples/Benchmarks/PWM_10-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 19; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 14'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 14'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 14'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_10.sv b/examples/Benchmarks/PWM_10.sv new file mode 100644 index 000000000..23adf2198 --- /dev/null +++ b/examples/Benchmarks/PWM_10.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 19; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 14'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 14'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 14'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_11-s1.sv b/examples/Benchmarks/PWM_11-s1.sv new file mode 100644 index 000000000..b9eb6b666 --- /dev/null +++ b/examples/Benchmarks/PWM_11-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 20; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 15'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 15'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 15'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_11-sl1.sv b/examples/Benchmarks/PWM_11-sl1.sv new file mode 100644 index 000000000..2113b0ba1 --- /dev/null +++ b/examples/Benchmarks/PWM_11-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 20; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 15'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 15'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 15'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_11.sv b/examples/Benchmarks/PWM_11.sv new file mode 100644 index 000000000..0038137b5 --- /dev/null +++ b/examples/Benchmarks/PWM_11.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 20; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 15'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 15'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 15'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_12-s1.sv b/examples/Benchmarks/PWM_12-s1.sv new file mode 100644 index 000000000..c0d22a8b6 --- /dev/null +++ b/examples/Benchmarks/PWM_12-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 21; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 16'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 16'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 16'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_12-sl1.sv b/examples/Benchmarks/PWM_12-sl1.sv new file mode 100644 index 000000000..68dd2df1e --- /dev/null +++ b/examples/Benchmarks/PWM_12-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 21; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 16'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 16'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 16'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_12.sv b/examples/Benchmarks/PWM_12.sv new file mode 100644 index 000000000..9baa3c1b9 --- /dev/null +++ b/examples/Benchmarks/PWM_12.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 21; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 16'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 16'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 16'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_2-s1.sv b/examples/Benchmarks/PWM_2-s1.sv new file mode 100644 index 000000000..1e045af9b --- /dev/null +++ b/examples/Benchmarks/PWM_2-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 11; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 6'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 6'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 6'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_2-sl1.sv b/examples/Benchmarks/PWM_2-sl1.sv new file mode 100644 index 000000000..f83957d86 --- /dev/null +++ b/examples/Benchmarks/PWM_2-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 11; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 6'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 6'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 6'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_2.sv b/examples/Benchmarks/PWM_2.sv index e2594daef..c42968007 100644 --- a/examples/Benchmarks/PWM_2.sv +++ b/examples/Benchmarks/PWM_2.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 11) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 11; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 7'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 6'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 6'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 6'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_3-s1.sv b/examples/Benchmarks/PWM_3-s1.sv new file mode 100644 index 000000000..e66c1a7f5 --- /dev/null +++ b/examples/Benchmarks/PWM_3-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 12; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 7'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 7'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 7'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_3-sl1.sv b/examples/Benchmarks/PWM_3-sl1.sv new file mode 100644 index 000000000..b1de44630 --- /dev/null +++ b/examples/Benchmarks/PWM_3-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 12; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 7'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 7'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 7'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_3.sv b/examples/Benchmarks/PWM_3.sv index cd50c8fca..ee57ce752 100644 --- a/examples/Benchmarks/PWM_3.sv +++ b/examples/Benchmarks/PWM_3.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 12) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 12; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 8'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 7'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 7'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 7'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_4-s1.sv b/examples/Benchmarks/PWM_4-s1.sv new file mode 100644 index 000000000..697987d43 --- /dev/null +++ b/examples/Benchmarks/PWM_4-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 13; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 8'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 8'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 8'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_4-sl1.sv b/examples/Benchmarks/PWM_4-sl1.sv new file mode 100644 index 000000000..ae2a425a7 --- /dev/null +++ b/examples/Benchmarks/PWM_4-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 13; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 8'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 8'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 8'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_4.sv b/examples/Benchmarks/PWM_4.sv index 12c69b0a9..176787b7f 100644 --- a/examples/Benchmarks/PWM_4.sv +++ b/examples/Benchmarks/PWM_4.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 13) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 13; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 9'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 8'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 8'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 8'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_5-s1.sv b/examples/Benchmarks/PWM_5-s1.sv new file mode 100644 index 000000000..95e55e0af --- /dev/null +++ b/examples/Benchmarks/PWM_5-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 14; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 9'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 9'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 9'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_5-sl1.sv b/examples/Benchmarks/PWM_5-sl1.sv new file mode 100644 index 000000000..a1f67c1d9 --- /dev/null +++ b/examples/Benchmarks/PWM_5-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 14; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 9'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 9'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 9'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_5.sv b/examples/Benchmarks/PWM_5.sv index 4716e0d08..101738310 100644 --- a/examples/Benchmarks/PWM_5.sv +++ b/examples/Benchmarks/PWM_5.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 14) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 14; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 10'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 9'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 9'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 9'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_6-s1.sv b/examples/Benchmarks/PWM_6-s1.sv new file mode 100644 index 000000000..67da97634 --- /dev/null +++ b/examples/Benchmarks/PWM_6-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 15; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 10'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 10'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 10'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_6-sl1.sv b/examples/Benchmarks/PWM_6-sl1.sv new file mode 100644 index 000000000..0c564f2e3 --- /dev/null +++ b/examples/Benchmarks/PWM_6-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 15; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 10'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 10'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 10'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_6.sv b/examples/Benchmarks/PWM_6.sv index 135bf0739..e140cfe48 100644 --- a/examples/Benchmarks/PWM_6.sv +++ b/examples/Benchmarks/PWM_6.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 15) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 15; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 11'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 10'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 10'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 10'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_7-s1.sv b/examples/Benchmarks/PWM_7-s1.sv new file mode 100644 index 000000000..7e526ce9f --- /dev/null +++ b/examples/Benchmarks/PWM_7-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 16; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 11'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 11'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 11'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_7-sl1.sv b/examples/Benchmarks/PWM_7-sl1.sv new file mode 100644 index 000000000..8014fd65a --- /dev/null +++ b/examples/Benchmarks/PWM_7-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 16; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 11'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 11'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 11'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_7.sv b/examples/Benchmarks/PWM_7.sv index 77ced4a37..12192f455 100644 --- a/examples/Benchmarks/PWM_7.sv +++ b/examples/Benchmarks/PWM_7.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 16) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 16; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 12'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 11'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 11'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 11'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_8-s1.sv b/examples/Benchmarks/PWM_8-s1.sv new file mode 100644 index 000000000..f23c347b5 --- /dev/null +++ b/examples/Benchmarks/PWM_8-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 17; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 12'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 12'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 12'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_8-sl1.sv b/examples/Benchmarks/PWM_8-sl1.sv new file mode 100644 index 000000000..0c9dd70f8 --- /dev/null +++ b/examples/Benchmarks/PWM_8-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 17; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 12'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 12'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 12'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_8.sv b/examples/Benchmarks/PWM_8.sv index 162078bd1..e0af670b2 100644 --- a/examples/Benchmarks/PWM_8.sv +++ b/examples/Benchmarks/PWM_8.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 17) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 17; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 13'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 12'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 12'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 12'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/PWM_9-s1.sv b/examples/Benchmarks/PWM_9-s1.sv new file mode 100644 index 000000000..6269d0e37 --- /dev/null +++ b/examples/Benchmarks/PWM_9-s1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 18; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 13'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 13'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 13'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + s1: assert property (@(posedge clk) ##1 ((lb_pulse -> pulse_red) && (!ub_pulse -> !pulse_red))); + // X G ((lb_p -> pulse) & (!ub_p -> !pulse)) +endmodule diff --git a/examples/Benchmarks/PWM_9-sl1.sv b/examples/Benchmarks/PWM_9-sl1.sv new file mode 100644 index 000000000..b943120ef --- /dev/null +++ b/examples/Benchmarks/PWM_9-sl1.sv @@ -0,0 +1,33 @@ +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 18; // Change pulse_wideR accordingly + + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 13'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 13'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 13'd0}; + + reg [CBITS-1:0] cnt_R; + + always @(posedge clk) begin + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; + + if (cnt_R < ubR) + ub_pulse = 1; + else + ub_pulse = 0; + end + + sl1: assert property None; + // GF !ub_p & X G (!ub_p -> !pulse) +endmodule diff --git a/examples/Benchmarks/PWM_9.sv b/examples/Benchmarks/PWM_9.sv index 36210cd0d..18e48a765 100644 --- a/examples/Benchmarks/PWM_9.sv +++ b/examples/Benchmarks/PWM_9.sv @@ -1,19 +1,33 @@ -module PWM_TOP #(localparam CBITS = 18) (input clk, input [3:0] sw, output reg pulse); +module PWM_TOP (input clk, input [3:0] sw, output reg pulse_red, output reg lb_pulse, output reg ub_pulse); + + localparam CBITS = 18; // Change pulse_wideR accordingly - wire [CBITS-1:0] pulse_wide; - assign pulse_wide = {1'b0, sw[3:1], 14'd0}; // (CBTIS-4) + wire [CBITS-1:0] pulse_wideR; + assign pulse_wideR = {1'b0, sw[3:1], 1'b1, 13'd0}; // (CBTIS-5) + assign lbR = {1'b0, 4'b0000, 1'b1, 13'd0}; + assign ubR = {1'b0, 4'b1111, 1'b1, 13'd0}; - reg [CBITS-1:0] cntR; + reg [CBITS-1:0] cnt_R; always @(posedge clk) begin - cntR <= cntR + 1; + cnt_R <= cnt_R + 1; + + if (cnt_R < pulse_wideR) + pulse_red = 1; + else + pulse_red = 0; + + if (cnt_R < lbR) + lb_pulse = 1; + else + lb_pulse = 0; - if (cntR < pulse_wide) - pulse = 1'b1; + if (cnt_R < ubR) + ub_pulse = 1; else - pulse = 1'b0; + ub_pulse = 0; end - p1: assert property (@(posedge clk) (always s_eventually pulse == 0)) ; - // G F (pulse = F) - // G F (pulse = F) is instantaneous for EBMC-BDD but G F (pulse = T) isn't -endmodule \ No newline at end of file + + p1: assert property (@(posedge clk) s_eventually pulse_red == 0); + // GF !p_red +endmodule diff --git a/examples/Benchmarks/blink_1-s1.sv b/examples/Benchmarks/blink_1-s1.sv new file mode 100644 index 000000000..4653b0603 --- /dev/null +++ b/examples/Benchmarks/blink_1-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 8) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_1-sl1.sv b/examples/Benchmarks/blink_1-sl1.sv new file mode 100644 index 000000000..11628acfb --- /dev/null +++ b/examples/Benchmarks/blink_1-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 8) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_1.sv b/examples/Benchmarks/blink_1.sv new file mode 100644 index 000000000..928dcc8c5 --- /dev/null +++ b/examples/Benchmarks/blink_1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 8) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_10-s1.sv b/examples/Benchmarks/blink_10-s1.sv new file mode 100644 index 000000000..baa9bbf37 --- /dev/null +++ b/examples/Benchmarks/blink_10-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 17) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_10-sl1.sv b/examples/Benchmarks/blink_10-sl1.sv new file mode 100644 index 000000000..e7e18a359 --- /dev/null +++ b/examples/Benchmarks/blink_10-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 17) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_10.sv b/examples/Benchmarks/blink_10.sv new file mode 100644 index 000000000..77ec6813e --- /dev/null +++ b/examples/Benchmarks/blink_10.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 17) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_11-s1.sv b/examples/Benchmarks/blink_11-s1.sv new file mode 100644 index 000000000..1507e11d8 --- /dev/null +++ b/examples/Benchmarks/blink_11-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 18) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_11-sl1.sv b/examples/Benchmarks/blink_11-sl1.sv new file mode 100644 index 000000000..120ed7a79 --- /dev/null +++ b/examples/Benchmarks/blink_11-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 18) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_11.sv b/examples/Benchmarks/blink_11.sv new file mode 100644 index 000000000..77c395a4d --- /dev/null +++ b/examples/Benchmarks/blink_11.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 18) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_12-s1.sv b/examples/Benchmarks/blink_12-s1.sv new file mode 100644 index 000000000..ba3cf14b8 --- /dev/null +++ b/examples/Benchmarks/blink_12-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 19) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_12-sl1.sv b/examples/Benchmarks/blink_12-sl1.sv new file mode 100644 index 000000000..3471e8a29 --- /dev/null +++ b/examples/Benchmarks/blink_12-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 19) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_12.sv b/examples/Benchmarks/blink_12.sv new file mode 100644 index 000000000..0ab83284f --- /dev/null +++ b/examples/Benchmarks/blink_12.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 19) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_13-s1.sv b/examples/Benchmarks/blink_13-s1.sv new file mode 100644 index 000000000..ff4b4c098 --- /dev/null +++ b/examples/Benchmarks/blink_13-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 20) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_13-sl1.sv b/examples/Benchmarks/blink_13-sl1.sv new file mode 100644 index 000000000..821ea11f2 --- /dev/null +++ b/examples/Benchmarks/blink_13-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 20) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_13.sv b/examples/Benchmarks/blink_13.sv new file mode 100644 index 000000000..54718c366 --- /dev/null +++ b/examples/Benchmarks/blink_13.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 20) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_14-s1.sv b/examples/Benchmarks/blink_14-s1.sv new file mode 100644 index 000000000..6e449e089 --- /dev/null +++ b/examples/Benchmarks/blink_14-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 21) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_14-sl1.sv b/examples/Benchmarks/blink_14-sl1.sv new file mode 100644 index 000000000..cb23e3fc7 --- /dev/null +++ b/examples/Benchmarks/blink_14-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 21) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_14.sv b/examples/Benchmarks/blink_14.sv new file mode 100644 index 000000000..971ddd777 --- /dev/null +++ b/examples/Benchmarks/blink_14.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 21) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_15-s1.sv b/examples/Benchmarks/blink_15-s1.sv new file mode 100644 index 000000000..53d1c1018 --- /dev/null +++ b/examples/Benchmarks/blink_15-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 22) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_15-sl1.sv b/examples/Benchmarks/blink_15-sl1.sv new file mode 100644 index 000000000..8e569aaee --- /dev/null +++ b/examples/Benchmarks/blink_15-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 22) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_15.sv b/examples/Benchmarks/blink_15.sv new file mode 100644 index 000000000..04b146468 --- /dev/null +++ b/examples/Benchmarks/blink_15.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 22) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_16-s1.sv b/examples/Benchmarks/blink_16-s1.sv new file mode 100644 index 000000000..6055b5a7f --- /dev/null +++ b/examples/Benchmarks/blink_16-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 23) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_16-sl1.sv b/examples/Benchmarks/blink_16-sl1.sv new file mode 100644 index 000000000..38d8d9f7e --- /dev/null +++ b/examples/Benchmarks/blink_16-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 23) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_16.sv b/examples/Benchmarks/blink_16.sv new file mode 100644 index 000000000..fea0465be --- /dev/null +++ b/examples/Benchmarks/blink_16.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 23) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_17-s1.sv b/examples/Benchmarks/blink_17-s1.sv new file mode 100644 index 000000000..1327d987d --- /dev/null +++ b/examples/Benchmarks/blink_17-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 24) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_17-sl1.sv b/examples/Benchmarks/blink_17-sl1.sv new file mode 100644 index 000000000..d399d7489 --- /dev/null +++ b/examples/Benchmarks/blink_17-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 24) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_17.sv b/examples/Benchmarks/blink_17.sv new file mode 100644 index 000000000..4cce97585 --- /dev/null +++ b/examples/Benchmarks/blink_17.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 24) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_18-s1.sv b/examples/Benchmarks/blink_18-s1.sv new file mode 100644 index 000000000..9f6633885 --- /dev/null +++ b/examples/Benchmarks/blink_18-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 25) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_18-sl1.sv b/examples/Benchmarks/blink_18-sl1.sv new file mode 100644 index 000000000..4b5b1cbca --- /dev/null +++ b/examples/Benchmarks/blink_18-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 25) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_18.sv b/examples/Benchmarks/blink_18.sv new file mode 100644 index 000000000..1024ec3d6 --- /dev/null +++ b/examples/Benchmarks/blink_18.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 25) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_19-s1.sv b/examples/Benchmarks/blink_19-s1.sv new file mode 100644 index 000000000..c49f85793 --- /dev/null +++ b/examples/Benchmarks/blink_19-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 26) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_19-sl1.sv b/examples/Benchmarks/blink_19-sl1.sv new file mode 100644 index 000000000..79d7410b0 --- /dev/null +++ b/examples/Benchmarks/blink_19-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 26) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_19.sv b/examples/Benchmarks/blink_19.sv new file mode 100644 index 000000000..1c4fbd313 --- /dev/null +++ b/examples/Benchmarks/blink_19.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 26) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_2-s1.sv b/examples/Benchmarks/blink_2-s1.sv new file mode 100644 index 000000000..c91ee98a3 --- /dev/null +++ b/examples/Benchmarks/blink_2-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 9) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_2-sl1.sv b/examples/Benchmarks/blink_2-sl1.sv new file mode 100644 index 000000000..66560779c --- /dev/null +++ b/examples/Benchmarks/blink_2-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 9) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_2.sv b/examples/Benchmarks/blink_2.sv new file mode 100644 index 000000000..4e09aec6d --- /dev/null +++ b/examples/Benchmarks/blink_2.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 9) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_20-s1.sv b/examples/Benchmarks/blink_20-s1.sv new file mode 100644 index 000000000..d0000a567 --- /dev/null +++ b/examples/Benchmarks/blink_20-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 27) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_20-sl1.sv b/examples/Benchmarks/blink_20-sl1.sv new file mode 100644 index 000000000..9e6ac6bab --- /dev/null +++ b/examples/Benchmarks/blink_20-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 27) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_20.sv b/examples/Benchmarks/blink_20.sv new file mode 100644 index 000000000..bf96a378a --- /dev/null +++ b/examples/Benchmarks/blink_20.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 27) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_21-s1.sv b/examples/Benchmarks/blink_21-s1.sv new file mode 100644 index 000000000..4858a3fd6 --- /dev/null +++ b/examples/Benchmarks/blink_21-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 28) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_21-sl1.sv b/examples/Benchmarks/blink_21-sl1.sv new file mode 100644 index 000000000..8b55fcd11 --- /dev/null +++ b/examples/Benchmarks/blink_21-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 28) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_21.sv b/examples/Benchmarks/blink_21.sv new file mode 100644 index 000000000..274e31bd8 --- /dev/null +++ b/examples/Benchmarks/blink_21.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 28) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_22-s1.sv b/examples/Benchmarks/blink_22-s1.sv new file mode 100644 index 000000000..fc53c127b --- /dev/null +++ b/examples/Benchmarks/blink_22-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 29) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_22-sl1.sv b/examples/Benchmarks/blink_22-sl1.sv new file mode 100644 index 000000000..bca72b465 --- /dev/null +++ b/examples/Benchmarks/blink_22-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 29) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_22.sv b/examples/Benchmarks/blink_22.sv new file mode 100644 index 000000000..ce1a6c14d --- /dev/null +++ b/examples/Benchmarks/blink_22.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 29) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_23-s1.sv b/examples/Benchmarks/blink_23-s1.sv new file mode 100644 index 000000000..a4f41844b --- /dev/null +++ b/examples/Benchmarks/blink_23-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 30) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_23-sl1.sv b/examples/Benchmarks/blink_23-sl1.sv new file mode 100644 index 000000000..14d35141c --- /dev/null +++ b/examples/Benchmarks/blink_23-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 30) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_23.sv b/examples/Benchmarks/blink_23.sv new file mode 100644 index 000000000..2e3b76ba7 --- /dev/null +++ b/examples/Benchmarks/blink_23.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 30) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_24-s1.sv b/examples/Benchmarks/blink_24-s1.sv new file mode 100644 index 000000000..fa5770bc6 --- /dev/null +++ b/examples/Benchmarks/blink_24-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 31) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_24-sl1.sv b/examples/Benchmarks/blink_24-sl1.sv new file mode 100644 index 000000000..066169f1a --- /dev/null +++ b/examples/Benchmarks/blink_24-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 31) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_24.sv b/examples/Benchmarks/blink_24.sv new file mode 100644 index 000000000..3b0a8a217 --- /dev/null +++ b/examples/Benchmarks/blink_24.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 31) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_25-s1.sv b/examples/Benchmarks/blink_25-s1.sv new file mode 100644 index 000000000..0b9e87d74 --- /dev/null +++ b/examples/Benchmarks/blink_25-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 32) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_25-sl1.sv b/examples/Benchmarks/blink_25-sl1.sv new file mode 100644 index 000000000..7899e6eba --- /dev/null +++ b/examples/Benchmarks/blink_25-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 32) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_25.sv b/examples/Benchmarks/blink_25.sv new file mode 100644 index 000000000..3b0e8c319 --- /dev/null +++ b/examples/Benchmarks/blink_25.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 32) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_3-s1.sv b/examples/Benchmarks/blink_3-s1.sv new file mode 100644 index 000000000..973a34a92 --- /dev/null +++ b/examples/Benchmarks/blink_3-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 10) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_3-sl1.sv b/examples/Benchmarks/blink_3-sl1.sv new file mode 100644 index 000000000..77d497a09 --- /dev/null +++ b/examples/Benchmarks/blink_3-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 10) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_3.sv b/examples/Benchmarks/blink_3.sv new file mode 100644 index 000000000..7f819047a --- /dev/null +++ b/examples/Benchmarks/blink_3.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 10) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_4-s1.sv b/examples/Benchmarks/blink_4-s1.sv new file mode 100644 index 000000000..55339e4c8 --- /dev/null +++ b/examples/Benchmarks/blink_4-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 11) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_4-sl1.sv b/examples/Benchmarks/blink_4-sl1.sv new file mode 100644 index 000000000..8e37a57f7 --- /dev/null +++ b/examples/Benchmarks/blink_4-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 11) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_4.sv b/examples/Benchmarks/blink_4.sv new file mode 100644 index 000000000..4b017ba80 --- /dev/null +++ b/examples/Benchmarks/blink_4.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 11) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_5-s1.sv b/examples/Benchmarks/blink_5-s1.sv new file mode 100644 index 000000000..2621f93bf --- /dev/null +++ b/examples/Benchmarks/blink_5-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 12) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_5-sl1.sv b/examples/Benchmarks/blink_5-sl1.sv new file mode 100644 index 000000000..b1d74928a --- /dev/null +++ b/examples/Benchmarks/blink_5-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 12) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_5.sv b/examples/Benchmarks/blink_5.sv new file mode 100644 index 000000000..d5bfe8f53 --- /dev/null +++ b/examples/Benchmarks/blink_5.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 12) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_6-s1.sv b/examples/Benchmarks/blink_6-s1.sv new file mode 100644 index 000000000..0d6e1e25a --- /dev/null +++ b/examples/Benchmarks/blink_6-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 13) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_6-sl1.sv b/examples/Benchmarks/blink_6-sl1.sv new file mode 100644 index 000000000..97bc0ca6d --- /dev/null +++ b/examples/Benchmarks/blink_6-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 13) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_6.sv b/examples/Benchmarks/blink_6.sv new file mode 100644 index 000000000..376497c53 --- /dev/null +++ b/examples/Benchmarks/blink_6.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 13) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_7-s1.sv b/examples/Benchmarks/blink_7-s1.sv new file mode 100644 index 000000000..e6fda573d --- /dev/null +++ b/examples/Benchmarks/blink_7-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 14) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_7-sl1.sv b/examples/Benchmarks/blink_7-sl1.sv new file mode 100644 index 000000000..b0d4fcb96 --- /dev/null +++ b/examples/Benchmarks/blink_7-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 14) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_7.sv b/examples/Benchmarks/blink_7.sv new file mode 100644 index 000000000..8f73d3138 --- /dev/null +++ b/examples/Benchmarks/blink_7.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 14) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_8-s1.sv b/examples/Benchmarks/blink_8-s1.sv new file mode 100644 index 000000000..9b42c85a3 --- /dev/null +++ b/examples/Benchmarks/blink_8-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 15) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_8-sl1.sv b/examples/Benchmarks/blink_8-sl1.sv new file mode 100644 index 000000000..c85ccb275 --- /dev/null +++ b/examples/Benchmarks/blink_8-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 15) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_8.sv b/examples/Benchmarks/blink_8.sv new file mode 100644 index 000000000..8997de25c --- /dev/null +++ b/examples/Benchmarks/blink_8.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 15) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/blink_9-s1.sv b/examples/Benchmarks/blink_9-s1.sv new file mode 100644 index 000000000..95b45db07 --- /dev/null +++ b/examples/Benchmarks/blink_9-s1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 16) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + s1: assert property (@(posedge clk) (mode ##1 mode |-> !flg)); + // G ((mode1 & X mode1) -> X !flg) +endmodule diff --git a/examples/Benchmarks/blink_9-sl1.sv b/examples/Benchmarks/blink_9-sl1.sv new file mode 100644 index 000000000..18c0e9684 --- /dev/null +++ b/examples/Benchmarks/blink_9-sl1.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 16) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + sl1: assert property (@(posedge clk) !rst implies always (led implies (led s_until !mode))); + // G !rst -> G(led -> (led U !mode1)) +endmodule diff --git a/examples/Benchmarks/blink_9.sv b/examples/Benchmarks/blink_9.sv new file mode 100644 index 000000000..7a5843a89 --- /dev/null +++ b/examples/Benchmarks/blink_9.sv @@ -0,0 +1,19 @@ +module BLINK #(localparam CBITS = 16) (input clk, input rst, output reg led, output reg flg); + reg [CBITS-1:0] cnt; + reg mode; + always@(posedge clk, posedge rst) begin + if (rst) begin + cnt <= 0; + mode <= 0; + end + else begin + cnt <= cnt + 1; + if (cnt == 0) + mode <= ~mode; + flg = (cnt == 0); + led = mode; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> led); + // FG !rst -> (GF led) +endmodule diff --git a/examples/Benchmarks/delay_1-p2.sv b/examples/Benchmarks/delay_1-p2.sv new file mode 100644 index 000000000..78662b30b --- /dev/null +++ b/examples/Benchmarks/delay_1-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_1-s1.sv b/examples/Benchmarks/delay_1-s1.sv new file mode 100644 index 000000000..f2c9d6c4f --- /dev/null +++ b/examples/Benchmarks/delay_1-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_1-s2.sv b/examples/Benchmarks/delay_1-s2.sv new file mode 100644 index 000000000..18cfed534 --- /dev/null +++ b/examples/Benchmarks/delay_1-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_1-sl1.sv b/examples/Benchmarks/delay_1-sl1.sv new file mode 100644 index 000000000..285483dda --- /dev/null +++ b/examples/Benchmarks/delay_1-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_1-sl2.sv b/examples/Benchmarks/delay_1-sl2.sv new file mode 100644 index 000000000..cf0c82b16 --- /dev/null +++ b/examples/Benchmarks/delay_1-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_1.sv b/examples/Benchmarks/delay_1.sv index c42b595cb..a49c9ddc8 100644 --- a/examples/Benchmarks/delay_1.sv +++ b/examples/Benchmarks/delay_1.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 750, localparam CBITS = 10) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 750; + localparam CBITS = 10; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1) ; - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_10-p2.sv b/examples/Benchmarks/delay_10-p2.sv new file mode 100644 index 000000000..b306df9c3 --- /dev/null +++ b/examples/Benchmarks/delay_10-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_10-s1.sv b/examples/Benchmarks/delay_10-s1.sv new file mode 100644 index 000000000..05d166416 --- /dev/null +++ b/examples/Benchmarks/delay_10-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_10-s2.sv b/examples/Benchmarks/delay_10-s2.sv new file mode 100644 index 000000000..abdbd41bd --- /dev/null +++ b/examples/Benchmarks/delay_10-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_10-sl1.sv b/examples/Benchmarks/delay_10-sl1.sv new file mode 100644 index 000000000..2fd226b67 --- /dev/null +++ b/examples/Benchmarks/delay_10-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_10-sl2.sv b/examples/Benchmarks/delay_10-sl2.sv new file mode 100644 index 000000000..c6f7c7e32 --- /dev/null +++ b/examples/Benchmarks/delay_10-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_10.sv b/examples/Benchmarks/delay_10.sv index 5775244cc..dff565dec 100644 --- a/examples/Benchmarks/delay_10.sv +++ b/examples/Benchmarks/delay_10.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 20000, localparam CBITS = 15) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 20000; + localparam CBITS = 15; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_11-p2.sv b/examples/Benchmarks/delay_11-p2.sv new file mode 100644 index 000000000..c05e57856 --- /dev/null +++ b/examples/Benchmarks/delay_11-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_11-s1.sv b/examples/Benchmarks/delay_11-s1.sv new file mode 100644 index 000000000..21853d346 --- /dev/null +++ b/examples/Benchmarks/delay_11-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_11-s2.sv b/examples/Benchmarks/delay_11-s2.sv new file mode 100644 index 000000000..097382ca2 --- /dev/null +++ b/examples/Benchmarks/delay_11-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_11-sl1.sv b/examples/Benchmarks/delay_11-sl1.sv new file mode 100644 index 000000000..141e86d51 --- /dev/null +++ b/examples/Benchmarks/delay_11-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_11-sl2.sv b/examples/Benchmarks/delay_11-sl2.sv new file mode 100644 index 000000000..0952d80b0 --- /dev/null +++ b/examples/Benchmarks/delay_11-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_11.sv b/examples/Benchmarks/delay_11.sv index 53aecde15..44c77d6c0 100644 --- a/examples/Benchmarks/delay_11.sv +++ b/examples/Benchmarks/delay_11.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 22500, localparam CBITS = 15) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 22500; + localparam CBITS = 15; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_12-p2.sv b/examples/Benchmarks/delay_12-p2.sv new file mode 100644 index 000000000..fda7ed45b --- /dev/null +++ b/examples/Benchmarks/delay_12-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_12-s1.sv b/examples/Benchmarks/delay_12-s1.sv new file mode 100644 index 000000000..a6f4ea896 --- /dev/null +++ b/examples/Benchmarks/delay_12-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_12-s2.sv b/examples/Benchmarks/delay_12-s2.sv new file mode 100644 index 000000000..e9a6177c3 --- /dev/null +++ b/examples/Benchmarks/delay_12-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_12-sl1.sv b/examples/Benchmarks/delay_12-sl1.sv new file mode 100644 index 000000000..b376e83fa --- /dev/null +++ b/examples/Benchmarks/delay_12-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_12-sl2.sv b/examples/Benchmarks/delay_12-sl2.sv new file mode 100644 index 000000000..5d0919fe8 --- /dev/null +++ b/examples/Benchmarks/delay_12-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_12.sv b/examples/Benchmarks/delay_12.sv index e6cde43f7..75f8c987b 100644 --- a/examples/Benchmarks/delay_12.sv +++ b/examples/Benchmarks/delay_12.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 25000, localparam CBITS = 15) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 25000; + localparam CBITS = 15; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_13-p2.sv b/examples/Benchmarks/delay_13-p2.sv new file mode 100644 index 000000000..7789e15db --- /dev/null +++ b/examples/Benchmarks/delay_13-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_13-s1.sv b/examples/Benchmarks/delay_13-s1.sv new file mode 100644 index 000000000..2405241f5 --- /dev/null +++ b/examples/Benchmarks/delay_13-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_13-s2.sv b/examples/Benchmarks/delay_13-s2.sv new file mode 100644 index 000000000..d68b301db --- /dev/null +++ b/examples/Benchmarks/delay_13-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_13-sl1.sv b/examples/Benchmarks/delay_13-sl1.sv new file mode 100644 index 000000000..de6dbb1a3 --- /dev/null +++ b/examples/Benchmarks/delay_13-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_13-sl2.sv b/examples/Benchmarks/delay_13-sl2.sv new file mode 100644 index 000000000..d4366e631 --- /dev/null +++ b/examples/Benchmarks/delay_13-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_13.sv b/examples/Benchmarks/delay_13.sv index 917c4e58b..f91935dd7 100644 --- a/examples/Benchmarks/delay_13.sv +++ b/examples/Benchmarks/delay_13.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 50000, localparam CBITS = 16) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 50000; + localparam CBITS = 16; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_14-p2.sv b/examples/Benchmarks/delay_14-p2.sv new file mode 100644 index 000000000..681534fa8 --- /dev/null +++ b/examples/Benchmarks/delay_14-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_14-s1.sv b/examples/Benchmarks/delay_14-s1.sv new file mode 100644 index 000000000..a88eb2a0f --- /dev/null +++ b/examples/Benchmarks/delay_14-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_14-s2.sv b/examples/Benchmarks/delay_14-s2.sv new file mode 100644 index 000000000..0bb95663a --- /dev/null +++ b/examples/Benchmarks/delay_14-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_14-sl1.sv b/examples/Benchmarks/delay_14-sl1.sv new file mode 100644 index 000000000..e97c8702f --- /dev/null +++ b/examples/Benchmarks/delay_14-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_14-sl2.sv b/examples/Benchmarks/delay_14-sl2.sv new file mode 100644 index 000000000..aad0e8126 --- /dev/null +++ b/examples/Benchmarks/delay_14-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_14.sv b/examples/Benchmarks/delay_14.sv index dde2ff39f..e501c71d2 100644 --- a/examples/Benchmarks/delay_14.sv +++ b/examples/Benchmarks/delay_14.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 100000, localparam CBITS = 17) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 100000; + localparam CBITS = 17; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_15-p2.sv b/examples/Benchmarks/delay_15-p2.sv new file mode 100644 index 000000000..39f633079 --- /dev/null +++ b/examples/Benchmarks/delay_15-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_15-s1.sv b/examples/Benchmarks/delay_15-s1.sv new file mode 100644 index 000000000..4414d13b5 --- /dev/null +++ b/examples/Benchmarks/delay_15-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_15-s2.sv b/examples/Benchmarks/delay_15-s2.sv new file mode 100644 index 000000000..71eb19195 --- /dev/null +++ b/examples/Benchmarks/delay_15-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_15-sl1.sv b/examples/Benchmarks/delay_15-sl1.sv new file mode 100644 index 000000000..0c4b954bd --- /dev/null +++ b/examples/Benchmarks/delay_15-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_15-sl2.sv b/examples/Benchmarks/delay_15-sl2.sv new file mode 100644 index 000000000..12de5e510 --- /dev/null +++ b/examples/Benchmarks/delay_15-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_15.sv b/examples/Benchmarks/delay_15.sv index c07d1a8f2..dc170ea6a 100644 --- a/examples/Benchmarks/delay_15.sv +++ b/examples/Benchmarks/delay_15.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 200000, localparam CBITS = 18) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 200000; + localparam CBITS = 18; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_16-p2.sv b/examples/Benchmarks/delay_16-p2.sv new file mode 100644 index 000000000..c995538ea --- /dev/null +++ b/examples/Benchmarks/delay_16-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_16-s1.sv b/examples/Benchmarks/delay_16-s1.sv new file mode 100644 index 000000000..f67708fa2 --- /dev/null +++ b/examples/Benchmarks/delay_16-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_16-s2.sv b/examples/Benchmarks/delay_16-s2.sv new file mode 100644 index 000000000..3d4b2f50d --- /dev/null +++ b/examples/Benchmarks/delay_16-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_16-sl1.sv b/examples/Benchmarks/delay_16-sl1.sv new file mode 100644 index 000000000..d85b15674 --- /dev/null +++ b/examples/Benchmarks/delay_16-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_16-sl2.sv b/examples/Benchmarks/delay_16-sl2.sv new file mode 100644 index 000000000..97cb10470 --- /dev/null +++ b/examples/Benchmarks/delay_16-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_16.sv b/examples/Benchmarks/delay_16.sv index 5c8923647..273a6cdab 100644 --- a/examples/Benchmarks/delay_16.sv +++ b/examples/Benchmarks/delay_16.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 400000, localparam CBITS = 19) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 400000; + localparam CBITS = 19; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_2-p2.sv b/examples/Benchmarks/delay_2-p2.sv new file mode 100644 index 000000000..539a2468a --- /dev/null +++ b/examples/Benchmarks/delay_2-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_2-s1.sv b/examples/Benchmarks/delay_2-s1.sv new file mode 100644 index 000000000..a068702d6 --- /dev/null +++ b/examples/Benchmarks/delay_2-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_2-s2.sv b/examples/Benchmarks/delay_2-s2.sv new file mode 100644 index 000000000..1d3ef62a6 --- /dev/null +++ b/examples/Benchmarks/delay_2-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_2-sl1.sv b/examples/Benchmarks/delay_2-sl1.sv new file mode 100644 index 000000000..f65bfc0c4 --- /dev/null +++ b/examples/Benchmarks/delay_2-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_2-sl2.sv b/examples/Benchmarks/delay_2-sl2.sv new file mode 100644 index 000000000..38ae8fd85 --- /dev/null +++ b/examples/Benchmarks/delay_2-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_2.sv b/examples/Benchmarks/delay_2.sv index 1d65265c6..df09dd14e 100644 --- a/examples/Benchmarks/delay_2.sv +++ b/examples/Benchmarks/delay_2.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 1250, localparam CBITS = 11) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 1250; + localparam CBITS = 11; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_3-p2.sv b/examples/Benchmarks/delay_3-p2.sv new file mode 100644 index 000000000..9fb2dc54e --- /dev/null +++ b/examples/Benchmarks/delay_3-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_3-s1.sv b/examples/Benchmarks/delay_3-s1.sv new file mode 100644 index 000000000..9c620173b --- /dev/null +++ b/examples/Benchmarks/delay_3-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_3-s2.sv b/examples/Benchmarks/delay_3-s2.sv new file mode 100644 index 000000000..2f1bd7cfe --- /dev/null +++ b/examples/Benchmarks/delay_3-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_3-sl1.sv b/examples/Benchmarks/delay_3-sl1.sv new file mode 100644 index 000000000..a9383f139 --- /dev/null +++ b/examples/Benchmarks/delay_3-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_3-sl2.sv b/examples/Benchmarks/delay_3-sl2.sv new file mode 100644 index 000000000..cbf13f925 --- /dev/null +++ b/examples/Benchmarks/delay_3-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_3.sv b/examples/Benchmarks/delay_3.sv index 522f3cab2..19d3a225d 100644 --- a/examples/Benchmarks/delay_3.sv +++ b/examples/Benchmarks/delay_3.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 2500, localparam CBITS = 12) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 2500; + localparam CBITS = 12; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_4-p2.sv b/examples/Benchmarks/delay_4-p2.sv new file mode 100644 index 000000000..364714265 --- /dev/null +++ b/examples/Benchmarks/delay_4-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_4-s1.sv b/examples/Benchmarks/delay_4-s1.sv new file mode 100644 index 000000000..a4ab78021 --- /dev/null +++ b/examples/Benchmarks/delay_4-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_4-s2.sv b/examples/Benchmarks/delay_4-s2.sv new file mode 100644 index 000000000..0f8879efb --- /dev/null +++ b/examples/Benchmarks/delay_4-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_4-sl1.sv b/examples/Benchmarks/delay_4-sl1.sv new file mode 100644 index 000000000..c75b903b7 --- /dev/null +++ b/examples/Benchmarks/delay_4-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_4-sl2.sv b/examples/Benchmarks/delay_4-sl2.sv new file mode 100644 index 000000000..5fba25d75 --- /dev/null +++ b/examples/Benchmarks/delay_4-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_4.sv b/examples/Benchmarks/delay_4.sv index 0a4bebd1f..46b212d23 100644 --- a/examples/Benchmarks/delay_4.sv +++ b/examples/Benchmarks/delay_4.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 5000, localparam CBITS = 13) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 5000; + localparam CBITS = 13; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_5-p2.sv b/examples/Benchmarks/delay_5-p2.sv new file mode 100644 index 000000000..abcac345b --- /dev/null +++ b/examples/Benchmarks/delay_5-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_5-s1.sv b/examples/Benchmarks/delay_5-s1.sv new file mode 100644 index 000000000..117dca257 --- /dev/null +++ b/examples/Benchmarks/delay_5-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_5-s2.sv b/examples/Benchmarks/delay_5-s2.sv new file mode 100644 index 000000000..541bca567 --- /dev/null +++ b/examples/Benchmarks/delay_5-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_5-sl1.sv b/examples/Benchmarks/delay_5-sl1.sv new file mode 100644 index 000000000..95bd9a0c7 --- /dev/null +++ b/examples/Benchmarks/delay_5-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_5-sl2.sv b/examples/Benchmarks/delay_5-sl2.sv new file mode 100644 index 000000000..4c7d321bb --- /dev/null +++ b/examples/Benchmarks/delay_5-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_5.sv b/examples/Benchmarks/delay_5.sv index 46bb14ee5..20cda2a35 100644 --- a/examples/Benchmarks/delay_5.sv +++ b/examples/Benchmarks/delay_5.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 7500, localparam CBITS = 13) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 7500; + localparam CBITS = 13; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_6-p2.sv b/examples/Benchmarks/delay_6-p2.sv new file mode 100644 index 000000000..0fc9858aa --- /dev/null +++ b/examples/Benchmarks/delay_6-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_6-s1.sv b/examples/Benchmarks/delay_6-s1.sv new file mode 100644 index 000000000..5cb83ce48 --- /dev/null +++ b/examples/Benchmarks/delay_6-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_6-s2.sv b/examples/Benchmarks/delay_6-s2.sv new file mode 100644 index 000000000..a6129b563 --- /dev/null +++ b/examples/Benchmarks/delay_6-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_6-sl1.sv b/examples/Benchmarks/delay_6-sl1.sv new file mode 100644 index 000000000..04eab36a1 --- /dev/null +++ b/examples/Benchmarks/delay_6-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_6-sl2.sv b/examples/Benchmarks/delay_6-sl2.sv new file mode 100644 index 000000000..598789e2b --- /dev/null +++ b/examples/Benchmarks/delay_6-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_6.sv b/examples/Benchmarks/delay_6.sv index 31113e8b3..f16396958 100644 --- a/examples/Benchmarks/delay_6.sv +++ b/examples/Benchmarks/delay_6.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 10000, localparam CBITS = 14) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 10000; + localparam CBITS = 14; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_7-p2.sv b/examples/Benchmarks/delay_7-p2.sv new file mode 100644 index 000000000..e801aaf5e --- /dev/null +++ b/examples/Benchmarks/delay_7-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_7-s1.sv b/examples/Benchmarks/delay_7-s1.sv new file mode 100644 index 000000000..e33e98115 --- /dev/null +++ b/examples/Benchmarks/delay_7-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_7-s2.sv b/examples/Benchmarks/delay_7-s2.sv new file mode 100644 index 000000000..649321aef --- /dev/null +++ b/examples/Benchmarks/delay_7-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_7-sl1.sv b/examples/Benchmarks/delay_7-sl1.sv new file mode 100644 index 000000000..09c11c153 --- /dev/null +++ b/examples/Benchmarks/delay_7-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_7-sl2.sv b/examples/Benchmarks/delay_7-sl2.sv new file mode 100644 index 000000000..a19b2b3df --- /dev/null +++ b/examples/Benchmarks/delay_7-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_7.sv b/examples/Benchmarks/delay_7.sv index 6d2fd19b4..72ebeba5e 100644 --- a/examples/Benchmarks/delay_7.sv +++ b/examples/Benchmarks/delay_7.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 12500, localparam CBITS = 14) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 12500; + localparam CBITS = 14; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_8-p2.sv b/examples/Benchmarks/delay_8-p2.sv new file mode 100644 index 000000000..72c8a0fdf --- /dev/null +++ b/examples/Benchmarks/delay_8-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_8-s1.sv b/examples/Benchmarks/delay_8-s1.sv new file mode 100644 index 000000000..058380ffb --- /dev/null +++ b/examples/Benchmarks/delay_8-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_8-s2.sv b/examples/Benchmarks/delay_8-s2.sv new file mode 100644 index 000000000..654967554 --- /dev/null +++ b/examples/Benchmarks/delay_8-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_8-sl1.sv b/examples/Benchmarks/delay_8-sl1.sv new file mode 100644 index 000000000..f45f4e560 --- /dev/null +++ b/examples/Benchmarks/delay_8-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_8-sl2.sv b/examples/Benchmarks/delay_8-sl2.sv new file mode 100644 index 000000000..ce3a38cd5 --- /dev/null +++ b/examples/Benchmarks/delay_8-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_8.sv b/examples/Benchmarks/delay_8.sv index 1145f7fb4..276b6d669 100644 --- a/examples/Benchmarks/delay_8.sv +++ b/examples/Benchmarks/delay_8.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 15000, localparam CBITS = 14) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 15000; + localparam CBITS = 14; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/delay_9-p2.sv b/examples/Benchmarks/delay_9-p2.sv new file mode 100644 index 000000000..ba01431fb --- /dev/null +++ b/examples/Benchmarks/delay_9-p2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // F G !rst -> G F (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/delay_9-s1.sv b/examples/Benchmarks/delay_9-s1.sv new file mode 100644 index 000000000..01196e641 --- /dev/null +++ b/examples/Benchmarks/delay_9-s1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s1: assert property (@(posedge clk) ##1 !err); + // X G !err +endmodule diff --git a/examples/Benchmarks/delay_9-s2.sv b/examples/Benchmarks/delay_9-s2.sv new file mode 100644 index 000000000..fd4e25146 --- /dev/null +++ b/examples/Benchmarks/delay_9-s2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + s2: assert property (@(posedge clk) sig |=> !sig); + // G (sig -> X !sig) +endmodule diff --git a/examples/Benchmarks/delay_9-sl1.sv b/examples/Benchmarks/delay_9-sl1.sv new file mode 100644 index 000000000..bc60470ca --- /dev/null +++ b/examples/Benchmarks/delay_9-sl1.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (flg s_until sig)); + // (G !rst -> X G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_9-sl2.sv b/examples/Benchmarks/delay_9-sl2.sv new file mode 100644 index 000000000..e000f09bc --- /dev/null +++ b/examples/Benchmarks/delay_9-sl2.sv @@ -0,0 +1,14 @@ +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); + always @(posedge clk) begin + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/delay_9.sv b/examples/Benchmarks/delay_9.sv index 82e315802..0622f76be 100644 --- a/examples/Benchmarks/delay_9.sv +++ b/examples/Benchmarks/delay_9.sv @@ -1,12 +1,14 @@ -module DELAY #(localparam N = 17500, localparam CBITS = 15) (input clk, input rst, output reg sig); +module DELAY (input clk, input rst, output reg sig ,output reg err, output reg flg); + localparam N = 17500; + localparam CBITS = 15; reg [CBITS-1 :0] cnt; + assign sig = (cnt >= N); + assign err = (cnt > N); + assign flg = (cnt < N); always @(posedge clk) begin - if (rst) cnt = 0; - else cnt = cnt + 1; - if (cnt > N) begin sig = 1; - cnt = 0; end - else sig = 0; + if (rst || cnt >= N) cnt <= 0; + else cnt <= cnt + 1; end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // F G !rst -> G F sig endmodule diff --git a/examples/Benchmarks/exmp_1-sl1.sv b/examples/Benchmarks/exmp_1-sl1.sv new file mode 100644 index 000000000..9ff4d1546 --- /dev/null +++ b/examples/Benchmarks/exmp_1-sl1.sv @@ -0,0 +1,11 @@ +module MODEL (input clk, output reg a, b); + reg [5:0] c; + reg b; + assign a = (c < 50); + assign b = (c == 50); + always @(posedge clk) begin + c <= c + 1; + end + sl1: assert property None; + // (a U b) +endmodule diff --git a/examples/Benchmarks/experiments.sh b/examples/Benchmarks/experiments.sh index 80eab2d97..c26b12684 100755 --- a/examples/Benchmarks/experiments.sh +++ b/examples/Benchmarks/experiments.sh @@ -2,7 +2,7 @@ for BM in *.sv do - TOP=$(grep -w module $BM | awk '{print $2}') + TOP=$(grep -w module $BM | awk '{print $2}' | sed 's/(.*//') echo "BENCHMARK: $BM ($TOP)" cat > $BM.jg.tcl << EOF clear -all @@ -18,7 +18,7 @@ done for BM in *.sv do - TOP=$(grep -w module $BM | awk '{print $2}') + TOP=$(grep -w module $BM | awk '{print $2}' | sed 's/(.*//') echo "BENCHMARK: $BM ($TOP)" cat > $BM.vcf.tcl << EOF set CPU_per_lic 12 diff --git a/examples/Benchmarks/gray_1-p2.sv b/examples/Benchmarks/gray_1-p2.sv new file mode 100644 index 000000000..91dd0f7a4 --- /dev/null +++ b/examples/Benchmarks/gray_1-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_1-p3.sv b/examples/Benchmarks/gray_1-p3.sv new file mode 100644 index 000000000..4f2fcdfa9 --- /dev/null +++ b/examples/Benchmarks/gray_1-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_1-s1.sv b/examples/Benchmarks/gray_1-s1.sv new file mode 100644 index 000000000..ecb5c3803 --- /dev/null +++ b/examples/Benchmarks/gray_1-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_1-sl1.sv b/examples/Benchmarks/gray_1-sl1.sv new file mode 100644 index 000000000..577d29911 --- /dev/null +++ b/examples/Benchmarks/gray_1-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_1-sl2.sv b/examples/Benchmarks/gray_1-sl2.sv new file mode 100644 index 000000000..3fa7385b4 --- /dev/null +++ b/examples/Benchmarks/gray_1-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_1.sv b/examples/Benchmarks/gray_1.sv index 0ba67d2ef..fb34cbe6b 100644 --- a/examples/Benchmarks/gray_1.sv +++ b/examples/Benchmarks/gray_1.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 8) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_10-p2.sv b/examples/Benchmarks/gray_10-p2.sv new file mode 100644 index 000000000..f55ffb315 --- /dev/null +++ b/examples/Benchmarks/gray_10-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_10-p3.sv b/examples/Benchmarks/gray_10-p3.sv new file mode 100644 index 000000000..a4ec3ccd3 --- /dev/null +++ b/examples/Benchmarks/gray_10-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_10-s1.sv b/examples/Benchmarks/gray_10-s1.sv new file mode 100644 index 000000000..695cd0609 --- /dev/null +++ b/examples/Benchmarks/gray_10-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_10-sl1.sv b/examples/Benchmarks/gray_10-sl1.sv new file mode 100644 index 000000000..61945624a --- /dev/null +++ b/examples/Benchmarks/gray_10-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_10-sl2.sv b/examples/Benchmarks/gray_10-sl2.sv new file mode 100644 index 000000000..db1dc4c88 --- /dev/null +++ b/examples/Benchmarks/gray_10-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_10.sv b/examples/Benchmarks/gray_10.sv index e3b362248..c89d21dbb 100644 --- a/examples/Benchmarks/gray_10.sv +++ b/examples/Benchmarks/gray_10.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 17) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_11-p2.sv b/examples/Benchmarks/gray_11-p2.sv new file mode 100644 index 000000000..7e1f92d9c --- /dev/null +++ b/examples/Benchmarks/gray_11-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_11-p3.sv b/examples/Benchmarks/gray_11-p3.sv new file mode 100644 index 000000000..9f8a672ce --- /dev/null +++ b/examples/Benchmarks/gray_11-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_11-s1.sv b/examples/Benchmarks/gray_11-s1.sv new file mode 100644 index 000000000..9242e2f9d --- /dev/null +++ b/examples/Benchmarks/gray_11-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_11-sl1.sv b/examples/Benchmarks/gray_11-sl1.sv new file mode 100644 index 000000000..45aaadf4c --- /dev/null +++ b/examples/Benchmarks/gray_11-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_11-sl2.sv b/examples/Benchmarks/gray_11-sl2.sv new file mode 100644 index 000000000..d58dbe6d8 --- /dev/null +++ b/examples/Benchmarks/gray_11-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_11.sv b/examples/Benchmarks/gray_11.sv index 25a2be400..5e262ef3a 100644 --- a/examples/Benchmarks/gray_11.sv +++ b/examples/Benchmarks/gray_11.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 18) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_2-p2.sv b/examples/Benchmarks/gray_2-p2.sv new file mode 100644 index 000000000..0336ff687 --- /dev/null +++ b/examples/Benchmarks/gray_2-p2.sv @@ -0,0 +1,16 @@ +module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_2-p3.sv b/examples/Benchmarks/gray_2-p3.sv new file mode 100644 index 000000000..083f6e658 --- /dev/null +++ b/examples/Benchmarks/gray_2-p3.sv @@ -0,0 +1,16 @@ +module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_2-s1.sv b/examples/Benchmarks/gray_2-s1.sv new file mode 100644 index 000000000..3647a2126 --- /dev/null +++ b/examples/Benchmarks/gray_2-s1.sv @@ -0,0 +1,16 @@ +module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_2-sl1.sv b/examples/Benchmarks/gray_2-sl1.sv new file mode 100644 index 000000000..9db98db26 --- /dev/null +++ b/examples/Benchmarks/gray_2-sl1.sv @@ -0,0 +1,16 @@ +module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_2-sl2.sv b/examples/Benchmarks/gray_2-sl2.sv new file mode 100644 index 000000000..931a110f7 --- /dev/null +++ b/examples/Benchmarks/gray_2-sl2.sv @@ -0,0 +1,16 @@ +module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_2.sv b/examples/Benchmarks/gray_2.sv index a9e655167..6062a758e 100644 --- a/examples/Benchmarks/gray_2.sv +++ b/examples/Benchmarks/gray_2.sv @@ -1,18 +1,16 @@ -module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 9) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_3-p2.sv b/examples/Benchmarks/gray_3-p2.sv new file mode 100644 index 000000000..946a9d9b8 --- /dev/null +++ b/examples/Benchmarks/gray_3-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_3-p3.sv b/examples/Benchmarks/gray_3-p3.sv new file mode 100644 index 000000000..8b677a9a6 --- /dev/null +++ b/examples/Benchmarks/gray_3-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_3-s1.sv b/examples/Benchmarks/gray_3-s1.sv new file mode 100644 index 000000000..ef533a885 --- /dev/null +++ b/examples/Benchmarks/gray_3-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_3-sl1.sv b/examples/Benchmarks/gray_3-sl1.sv new file mode 100644 index 000000000..fa7fa4e96 --- /dev/null +++ b/examples/Benchmarks/gray_3-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_3-sl2.sv b/examples/Benchmarks/gray_3-sl2.sv new file mode 100644 index 000000000..f57dac229 --- /dev/null +++ b/examples/Benchmarks/gray_3-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_3.sv b/examples/Benchmarks/gray_3.sv index 3e9f25c2f..fbbe8063d 100644 --- a/examples/Benchmarks/gray_3.sv +++ b/examples/Benchmarks/gray_3.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 10) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_4-p2.sv b/examples/Benchmarks/gray_4-p2.sv new file mode 100644 index 000000000..959d0d06a --- /dev/null +++ b/examples/Benchmarks/gray_4-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_4-p3.sv b/examples/Benchmarks/gray_4-p3.sv new file mode 100644 index 000000000..91b2d2e10 --- /dev/null +++ b/examples/Benchmarks/gray_4-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_4-s1.sv b/examples/Benchmarks/gray_4-s1.sv new file mode 100644 index 000000000..957fcefd8 --- /dev/null +++ b/examples/Benchmarks/gray_4-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_4-sl1.sv b/examples/Benchmarks/gray_4-sl1.sv new file mode 100644 index 000000000..5f7df92af --- /dev/null +++ b/examples/Benchmarks/gray_4-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_4-sl2.sv b/examples/Benchmarks/gray_4-sl2.sv new file mode 100644 index 000000000..617eabf22 --- /dev/null +++ b/examples/Benchmarks/gray_4-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_4.sv b/examples/Benchmarks/gray_4.sv index eb87a49ae..8aefe7cb8 100644 --- a/examples/Benchmarks/gray_4.sv +++ b/examples/Benchmarks/gray_4.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 11) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_5-p2.sv b/examples/Benchmarks/gray_5-p2.sv new file mode 100644 index 000000000..c5d9b68e5 --- /dev/null +++ b/examples/Benchmarks/gray_5-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_5-p3.sv b/examples/Benchmarks/gray_5-p3.sv new file mode 100644 index 000000000..2bb60a484 --- /dev/null +++ b/examples/Benchmarks/gray_5-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_5-s1.sv b/examples/Benchmarks/gray_5-s1.sv new file mode 100644 index 000000000..56d4ae49b --- /dev/null +++ b/examples/Benchmarks/gray_5-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_5-sl1.sv b/examples/Benchmarks/gray_5-sl1.sv new file mode 100644 index 000000000..2b5f901c4 --- /dev/null +++ b/examples/Benchmarks/gray_5-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_5-sl2.sv b/examples/Benchmarks/gray_5-sl2.sv new file mode 100644 index 000000000..d8da1437e --- /dev/null +++ b/examples/Benchmarks/gray_5-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_5.sv b/examples/Benchmarks/gray_5.sv index 63c69e56b..2a2f2d815 100644 --- a/examples/Benchmarks/gray_5.sv +++ b/examples/Benchmarks/gray_5.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 12) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_6-p2.sv b/examples/Benchmarks/gray_6-p2.sv new file mode 100644 index 000000000..124f7866f --- /dev/null +++ b/examples/Benchmarks/gray_6-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_6-p3.sv b/examples/Benchmarks/gray_6-p3.sv new file mode 100644 index 000000000..76b3196ef --- /dev/null +++ b/examples/Benchmarks/gray_6-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_6-s1.sv b/examples/Benchmarks/gray_6-s1.sv new file mode 100644 index 000000000..d436a5658 --- /dev/null +++ b/examples/Benchmarks/gray_6-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_6-sl1.sv b/examples/Benchmarks/gray_6-sl1.sv new file mode 100644 index 000000000..da3271e61 --- /dev/null +++ b/examples/Benchmarks/gray_6-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_6-sl2.sv b/examples/Benchmarks/gray_6-sl2.sv new file mode 100644 index 000000000..40a86ea43 --- /dev/null +++ b/examples/Benchmarks/gray_6-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_6.sv b/examples/Benchmarks/gray_6.sv index 3cfb0527e..9b737114d 100644 --- a/examples/Benchmarks/gray_6.sv +++ b/examples/Benchmarks/gray_6.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 13) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_7-p2.sv b/examples/Benchmarks/gray_7-p2.sv new file mode 100644 index 000000000..a5cb8e3c2 --- /dev/null +++ b/examples/Benchmarks/gray_7-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_7-p3.sv b/examples/Benchmarks/gray_7-p3.sv new file mode 100644 index 000000000..14a66e7a2 --- /dev/null +++ b/examples/Benchmarks/gray_7-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_7-s1.sv b/examples/Benchmarks/gray_7-s1.sv new file mode 100644 index 000000000..77d1eec2b --- /dev/null +++ b/examples/Benchmarks/gray_7-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_7-sl1.sv b/examples/Benchmarks/gray_7-sl1.sv new file mode 100644 index 000000000..7345018b2 --- /dev/null +++ b/examples/Benchmarks/gray_7-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_7-sl2.sv b/examples/Benchmarks/gray_7-sl2.sv new file mode 100644 index 000000000..bee2cf6b2 --- /dev/null +++ b/examples/Benchmarks/gray_7-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_7.sv b/examples/Benchmarks/gray_7.sv index 3225c66df..6c31ae6e8 100644 --- a/examples/Benchmarks/gray_7.sv +++ b/examples/Benchmarks/gray_7.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 14) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_8-p2.sv b/examples/Benchmarks/gray_8-p2.sv new file mode 100644 index 000000000..8b479e958 --- /dev/null +++ b/examples/Benchmarks/gray_8-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_8-p3.sv b/examples/Benchmarks/gray_8-p3.sv new file mode 100644 index 000000000..e7c196f1f --- /dev/null +++ b/examples/Benchmarks/gray_8-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_8-s1.sv b/examples/Benchmarks/gray_8-s1.sv new file mode 100644 index 000000000..777290e5e --- /dev/null +++ b/examples/Benchmarks/gray_8-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_8-sl1.sv b/examples/Benchmarks/gray_8-sl1.sv new file mode 100644 index 000000000..02caf4a40 --- /dev/null +++ b/examples/Benchmarks/gray_8-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_8-sl2.sv b/examples/Benchmarks/gray_8-sl2.sv new file mode 100644 index 000000000..6f64801a2 --- /dev/null +++ b/examples/Benchmarks/gray_8-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_8.sv b/examples/Benchmarks/gray_8.sv index a2418d857..ab5802373 100644 --- a/examples/Benchmarks/gray_8.sv +++ b/examples/Benchmarks/gray_8.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 15) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/gray_9-p2.sv b/examples/Benchmarks/gray_9-p2.sv new file mode 100644 index 000000000..33986b2ad --- /dev/null +++ b/examples/Benchmarks/gray_9-p2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p2: assert property (@(posedge clk) s_eventually (!rst implies (sig and s_nexttime !sig))); + // FG !rst -> GF (sig & X !sig) +endmodule diff --git a/examples/Benchmarks/gray_9-p3.sv b/examples/Benchmarks/gray_9-p3.sv new file mode 100644 index 000000000..d49685d7a --- /dev/null +++ b/examples/Benchmarks/gray_9-p3.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + p3: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually sig) and (s_eventually !sig))); + // FG !rst -> (GF sig & GF !sig) +endmodule diff --git a/examples/Benchmarks/gray_9-s1.sv b/examples/Benchmarks/gray_9-s1.sv new file mode 100644 index 000000000..c13193877 --- /dev/null +++ b/examples/Benchmarks/gray_9-s1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + s1: assert property (@(posedge clk) sig && !rst |=> !sig); + // X G ((sig & !rst) -> X !sig) +endmodule diff --git a/examples/Benchmarks/gray_9-sl1.sv b/examples/Benchmarks/gray_9-sl1.sv new file mode 100644 index 000000000..8751b5246 --- /dev/null +++ b/examples/Benchmarks/gray_9-sl1.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl1: assert property (@(posedge clk) (always !rst) implies s_nexttime always (cnt>0 s_until sig)); + // (G !rst -> X G (cnt > 0 U sig)) +endmodule diff --git a/examples/Benchmarks/gray_9-sl2.sv b/examples/Benchmarks/gray_9-sl2.sv new file mode 100644 index 000000000..72c27a94c --- /dev/null +++ b/examples/Benchmarks/gray_9-sl2.sv @@ -0,0 +1,15 @@ +module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); + reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); + always@(posedge clk, posedge rst) begin + if (rst) + cnt <= 0; + else begin + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); + end + end + sl2: assert property (@(posedge clk) (s_eventually always !rst) implies s_eventually always (flg s_until sig)); + // (FG !rst -> F G (flg U sig)) +endmodule diff --git a/examples/Benchmarks/gray_9.sv b/examples/Benchmarks/gray_9.sv index 776f7c4dd..a7d9b2f8d 100644 --- a/examples/Benchmarks/gray_9.sv +++ b/examples/Benchmarks/gray_9.sv @@ -1,18 +1,15 @@ -module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_cnt, output reg sig); +module GRAY #(localparam CBITS = 16) (input clk, input rst, output reg [CBITS-1:0] gray_c, output reg sig, output reg flg); reg [CBITS-1:0] cnt; + assign sig = (cnt == 0) & ~rst; + assign flg = (cnt >= 0); always@(posedge clk, posedge rst) begin - if (rst) begin - cnt = 0; - end + if (rst) + cnt <= 0; else begin - cnt = cnt + 1; - gray_cnt = (cnt) ^ ((cnt) >> 1); - if(gray_cnt == 0) - sig = 1; - else - sig = 0; + cnt <= cnt + 1; + gray_c = (cnt) ^ ((cnt) >> 1); end end - p1: assert property (@(posedge clk) s_eventually rst || sig == 1); - // F G (rst = F) -> G F (sig = T) + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> (GF sig) endmodule diff --git a/examples/Benchmarks/i2c_1-s1.sv b/examples/Benchmarks/i2c_1-s1.sv new file mode 100644 index 000000000..0a64b33a8 --- /dev/null +++ b/examples/Benchmarks/i2c_1-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3; + localparam CBITS = 4; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_1-sl1.sv b/examples/Benchmarks/i2c_1-sl1.sv new file mode 100644 index 000000000..bbf31fb71 --- /dev/null +++ b/examples/Benchmarks/i2c_1-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3; + localparam CBITS = 4; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_1.sv b/examples/Benchmarks/i2c_1.sv index 3c7c48d1d..eb4b868c0 100644 --- a/examples/Benchmarks/i2c_1.sv +++ b/examples/Benchmarks/i2c_1.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 125, localparam CBITS = 9) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3; + localparam CBITS = 4; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,19 +34,11 @@ module i2cStrech #(localparam divider = 125, localparam CBITS = 9) (input clk, i scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - - p1: assert property (@(posedge clk) s_eventually rst == 1 || scl_not_ena == 1 || stretch == 1); - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) - -wire [8:0] rank1 = - cnt>=divider*4 ? 3 : // 500 - !scl_clk && cnt>=3*divider-1 ? 2 : - scl_clk ? 1 : - 0 ; - -wire [8:0] rank2 = 500 - cnt; - -wire [31:0] rank = {rank1, rank2}; - + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch endmodule diff --git a/examples/Benchmarks/i2c_10-s1.sv b/examples/Benchmarks/i2c_10-s1.sv new file mode 100644 index 000000000..c12f4db21 --- /dev/null +++ b/examples/Benchmarks/i2c_10-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 4000; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_10-sl1.sv b/examples/Benchmarks/i2c_10-sl1.sv new file mode 100644 index 000000000..fe775a037 --- /dev/null +++ b/examples/Benchmarks/i2c_10-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 4000; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_10.sv b/examples/Benchmarks/i2c_10.sv index 5dbd2cd39..7be44e1f6 100644 --- a/examples/Benchmarks/i2c_10.sv +++ b/examples/Benchmarks/i2c_10.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 4000, localparam CBITS = 14) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 4000; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 4000, localparam CBITS = 14) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) s_eventually (rst == 1 || scl_not_ena == 1 || stretch == 1)) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch endmodule diff --git a/examples/Benchmarks/i2c_11-s1.sv b/examples/Benchmarks/i2c_11-s1.sv new file mode 100644 index 000000000..e3ed2d15b --- /dev/null +++ b/examples/Benchmarks/i2c_11-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 4500; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_11-sl1.sv b/examples/Benchmarks/i2c_11-sl1.sv new file mode 100644 index 000000000..697534747 --- /dev/null +++ b/examples/Benchmarks/i2c_11-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 4500; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_11.sv b/examples/Benchmarks/i2c_11.sv index f8b6a1612..cc38836f2 100644 --- a/examples/Benchmarks/i2c_11.sv +++ b/examples/Benchmarks/i2c_11.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 4500, localparam CBITS = 15) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 4500; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 4500, localparam CBITS = 15) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_12-s1.sv b/examples/Benchmarks/i2c_12-s1.sv new file mode 100644 index 000000000..3b4bccc36 --- /dev/null +++ b/examples/Benchmarks/i2c_12-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 5000; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_12-sl1.sv b/examples/Benchmarks/i2c_12-sl1.sv new file mode 100644 index 000000000..b83e36d3c --- /dev/null +++ b/examples/Benchmarks/i2c_12-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 5000; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_12.sv b/examples/Benchmarks/i2c_12.sv index 7e3e52b03..e7d8e71bc 100644 --- a/examples/Benchmarks/i2c_12.sv +++ b/examples/Benchmarks/i2c_12.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 5000, localparam CBITS = 15) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 5000; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 5000, localparam CBITS = 15) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_13-s1.sv b/examples/Benchmarks/i2c_13-s1.sv new file mode 100644 index 000000000..cab0ce1a0 --- /dev/null +++ b/examples/Benchmarks/i2c_13-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 5500; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_13-sl1.sv b/examples/Benchmarks/i2c_13-sl1.sv new file mode 100644 index 000000000..9dae40c37 --- /dev/null +++ b/examples/Benchmarks/i2c_13-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 5500; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_13.sv b/examples/Benchmarks/i2c_13.sv index bb8044cee..f93453667 100644 --- a/examples/Benchmarks/i2c_13.sv +++ b/examples/Benchmarks/i2c_13.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 5500, localparam CBITS = 15) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 5500; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 5500, localparam CBITS = 15) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_14-s1.sv b/examples/Benchmarks/i2c_14-s1.sv new file mode 100644 index 000000000..ec4c01620 --- /dev/null +++ b/examples/Benchmarks/i2c_14-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 6000; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_14-sl1.sv b/examples/Benchmarks/i2c_14-sl1.sv new file mode 100644 index 000000000..d5535a936 --- /dev/null +++ b/examples/Benchmarks/i2c_14-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 6000; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_14.sv b/examples/Benchmarks/i2c_14.sv index 7fa750fbc..7b9d3dcac 100644 --- a/examples/Benchmarks/i2c_14.sv +++ b/examples/Benchmarks/i2c_14.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 6000, localparam CBITS = 15) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 6000; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 6000, localparam CBITS = 15) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_15-s1.sv b/examples/Benchmarks/i2c_15-s1.sv new file mode 100644 index 000000000..c9ec10a92 --- /dev/null +++ b/examples/Benchmarks/i2c_15-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 6500; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_15-sl1.sv b/examples/Benchmarks/i2c_15-sl1.sv new file mode 100644 index 000000000..7334bdb25 --- /dev/null +++ b/examples/Benchmarks/i2c_15-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 6500; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_15.sv b/examples/Benchmarks/i2c_15.sv index 4ebb92885..49ef63fd2 100644 --- a/examples/Benchmarks/i2c_15.sv +++ b/examples/Benchmarks/i2c_15.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 6500, localparam CBITS = 15) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 6500; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 6500, localparam CBITS = 15) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_16-s1.sv b/examples/Benchmarks/i2c_16-s1.sv new file mode 100644 index 000000000..914e129f4 --- /dev/null +++ b/examples/Benchmarks/i2c_16-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 7000; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_16-sl1.sv b/examples/Benchmarks/i2c_16-sl1.sv new file mode 100644 index 000000000..99d3f5e2a --- /dev/null +++ b/examples/Benchmarks/i2c_16-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 7000; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_16.sv b/examples/Benchmarks/i2c_16.sv index cd1e5739f..0fb0431ef 100644 --- a/examples/Benchmarks/i2c_16.sv +++ b/examples/Benchmarks/i2c_16.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 7000, localparam CBITS = 15) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 7000; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 7000, localparam CBITS = 15) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_17-s1.sv b/examples/Benchmarks/i2c_17-s1.sv new file mode 100644 index 000000000..b60a45811 --- /dev/null +++ b/examples/Benchmarks/i2c_17-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 10000; + localparam CBITS = 16; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_17-sl1.sv b/examples/Benchmarks/i2c_17-sl1.sv new file mode 100644 index 000000000..e7dda1be6 --- /dev/null +++ b/examples/Benchmarks/i2c_17-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 10000; + localparam CBITS = 16; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_17.sv b/examples/Benchmarks/i2c_17.sv index f867667c4..3a1d3d228 100644 --- a/examples/Benchmarks/i2c_17.sv +++ b/examples/Benchmarks/i2c_17.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 10000, localparam CBITS = 16) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 10000; + localparam CBITS = 16; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 10000, localparam CBITS = 16) (input clk scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_18-s1.sv b/examples/Benchmarks/i2c_18-s1.sv new file mode 100644 index 000000000..3cbccd147 --- /dev/null +++ b/examples/Benchmarks/i2c_18-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 17500; + localparam CBITS = 17; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_18-sl1.sv b/examples/Benchmarks/i2c_18-sl1.sv new file mode 100644 index 000000000..06de4fca8 --- /dev/null +++ b/examples/Benchmarks/i2c_18-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 17500; + localparam CBITS = 17; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_18.sv b/examples/Benchmarks/i2c_18.sv index 2da846bd7..ba3601dc7 100644 --- a/examples/Benchmarks/i2c_18.sv +++ b/examples/Benchmarks/i2c_18.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 17500, localparam CBITS = 17) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 17500; + localparam CBITS = 17; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 17500, localparam CBITS = 17) (input clk scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_19-s1.sv b/examples/Benchmarks/i2c_19-s1.sv new file mode 100644 index 000000000..b5370deaf --- /dev/null +++ b/examples/Benchmarks/i2c_19-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 35000; + localparam CBITS = 18; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_19-sl1.sv b/examples/Benchmarks/i2c_19-sl1.sv new file mode 100644 index 000000000..368e8d661 --- /dev/null +++ b/examples/Benchmarks/i2c_19-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 35000; + localparam CBITS = 18; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_19.sv b/examples/Benchmarks/i2c_19.sv index cdfdd0c0c..105e15f95 100644 --- a/examples/Benchmarks/i2c_19.sv +++ b/examples/Benchmarks/i2c_19.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 35000, localparam CBITS = 18) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 35000; + localparam CBITS = 18; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 35000, localparam CBITS = 18) (input clk scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_2-s1.sv b/examples/Benchmarks/i2c_2-s1.sv new file mode 100644 index 000000000..61608ccd8 --- /dev/null +++ b/examples/Benchmarks/i2c_2-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 250; + localparam CBITS = 10; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_2-sl1.sv b/examples/Benchmarks/i2c_2-sl1.sv new file mode 100644 index 000000000..ba0f4ffab --- /dev/null +++ b/examples/Benchmarks/i2c_2-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 250; + localparam CBITS = 10; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_2.sv b/examples/Benchmarks/i2c_2.sv index 8726535d9..f31b7b32f 100644 --- a/examples/Benchmarks/i2c_2.sv +++ b/examples/Benchmarks/i2c_2.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 250, localparam CBITS = 10) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 250; + localparam CBITS = 10; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 250, localparam CBITS = 10) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) s_eventually (rst == 1 || scl_not_ena == 1 || stretch == 1)) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch endmodule diff --git a/examples/Benchmarks/i2c_20-s1.sv b/examples/Benchmarks/i2c_20-s1.sv new file mode 100644 index 000000000..2d79f8779 --- /dev/null +++ b/examples/Benchmarks/i2c_20-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 70000; + localparam CBITS = 19; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_20-sl1.sv b/examples/Benchmarks/i2c_20-sl1.sv new file mode 100644 index 000000000..bb2ffa094 --- /dev/null +++ b/examples/Benchmarks/i2c_20-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 70000; + localparam CBITS = 19; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_20.sv b/examples/Benchmarks/i2c_20.sv index 5433eb7ad..befc87a5e 100644 --- a/examples/Benchmarks/i2c_20.sv +++ b/examples/Benchmarks/i2c_20.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 70000, localparam CBITS = 19) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 70000; + localparam CBITS = 19; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 70000, localparam CBITS = 19) (input clk scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_3-s1.sv b/examples/Benchmarks/i2c_3-s1.sv new file mode 100644 index 000000000..451964ed8 --- /dev/null +++ b/examples/Benchmarks/i2c_3-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 500; + localparam CBITS = 11; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_3-sl1.sv b/examples/Benchmarks/i2c_3-sl1.sv new file mode 100644 index 000000000..32de21d07 --- /dev/null +++ b/examples/Benchmarks/i2c_3-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 500; + localparam CBITS = 11; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_3.sv b/examples/Benchmarks/i2c_3.sv index eda54f1a7..5a8110f7b 100644 --- a/examples/Benchmarks/i2c_3.sv +++ b/examples/Benchmarks/i2c_3.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 500, localparam CBITS = 11) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 500; + localparam CBITS = 11; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 500, localparam CBITS = 11) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_4-s1.sv b/examples/Benchmarks/i2c_4-s1.sv new file mode 100644 index 000000000..876e8b042 --- /dev/null +++ b/examples/Benchmarks/i2c_4-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 1000; + localparam CBITS = 12; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_4-sl1.sv b/examples/Benchmarks/i2c_4-sl1.sv new file mode 100644 index 000000000..2b5d5a23c --- /dev/null +++ b/examples/Benchmarks/i2c_4-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 1000; + localparam CBITS = 12; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_4.sv b/examples/Benchmarks/i2c_4.sv index 93af7eecd..16a555011 100644 --- a/examples/Benchmarks/i2c_4.sv +++ b/examples/Benchmarks/i2c_4.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 1000, localparam CBITS = 12) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 1000; + localparam CBITS = 12; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 1000, localparam CBITS = 12) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_5-s1.sv b/examples/Benchmarks/i2c_5-s1.sv new file mode 100644 index 000000000..4424b17d0 --- /dev/null +++ b/examples/Benchmarks/i2c_5-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 1500; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_5-sl1.sv b/examples/Benchmarks/i2c_5-sl1.sv new file mode 100644 index 000000000..7f9efcb91 --- /dev/null +++ b/examples/Benchmarks/i2c_5-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 1500; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_5.sv b/examples/Benchmarks/i2c_5.sv index 2a33e8e9e..58db69fa2 100644 --- a/examples/Benchmarks/i2c_5.sv +++ b/examples/Benchmarks/i2c_5.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 1500, localparam CBITS = 13) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 1500; + localparam CBITS = 13; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 1500, localparam CBITS = 13) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_6-s1.sv b/examples/Benchmarks/i2c_6-s1.sv new file mode 100644 index 000000000..3ea501b7f --- /dev/null +++ b/examples/Benchmarks/i2c_6-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 2000; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_6-sl1.sv b/examples/Benchmarks/i2c_6-sl1.sv new file mode 100644 index 000000000..18f6cd7f7 --- /dev/null +++ b/examples/Benchmarks/i2c_6-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 2000; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_6.sv b/examples/Benchmarks/i2c_6.sv index 437f796de..a01a16a2f 100644 --- a/examples/Benchmarks/i2c_6.sv +++ b/examples/Benchmarks/i2c_6.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 2000, localparam CBITS = 13) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 2000; + localparam CBITS = 13; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 2000, localparam CBITS = 13) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_7-s1.sv b/examples/Benchmarks/i2c_7-s1.sv new file mode 100644 index 000000000..94c4e749a --- /dev/null +++ b/examples/Benchmarks/i2c_7-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 2500; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_7-sl1.sv b/examples/Benchmarks/i2c_7-sl1.sv new file mode 100644 index 000000000..fc4ca2509 --- /dev/null +++ b/examples/Benchmarks/i2c_7-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 2500; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_7.sv b/examples/Benchmarks/i2c_7.sv index cdb48bb7e..81663c66c 100644 --- a/examples/Benchmarks/i2c_7.sv +++ b/examples/Benchmarks/i2c_7.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 2500, localparam CBITS = 14) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 2500; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 2500, localparam CBITS = 14) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_8-s1.sv b/examples/Benchmarks/i2c_8-s1.sv new file mode 100644 index 000000000..934b8d397 --- /dev/null +++ b/examples/Benchmarks/i2c_8-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3000; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_8-sl1.sv b/examples/Benchmarks/i2c_8-sl1.sv new file mode 100644 index 000000000..14ce7db61 --- /dev/null +++ b/examples/Benchmarks/i2c_8-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3000; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_8.sv b/examples/Benchmarks/i2c_8.sv index 4b9960de5..c33708c9a 100644 --- a/examples/Benchmarks/i2c_8.sv +++ b/examples/Benchmarks/i2c_8.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 3000, localparam CBITS = 14) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3000; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 3000, localparam CBITS = 14) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/i2c_9-s1.sv b/examples/Benchmarks/i2c_9-s1.sv new file mode 100644 index 000000000..f259bc94d --- /dev/null +++ b/examples/Benchmarks/i2c_9-s1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3500; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + s1: assert property (@(posedge clk) !stretch ##1 stretch |-> switch_range); + // XG ((!s & X s) -> X sw) +endmodule diff --git a/examples/Benchmarks/i2c_9-sl1.sv b/examples/Benchmarks/i2c_9-sl1.sv new file mode 100644 index 000000000..b4f443e1d --- /dev/null +++ b/examples/Benchmarks/i2c_9-sl1.sv @@ -0,0 +1,44 @@ +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3500; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; //0 to 4*divider + reg scl_clk; + reg stretch; + always @(posedge clk) begin + if(rst == 1) begin + stretch = 0; + cnt = 0; + end + if(cnt >= divider*4 - 1) + cnt = 0; + else if(stretch == 0) + cnt = cnt + 1; + + if( cnt <= divider - 1) begin + scl_clk = 0; + data_clk = 0; + end + else if( divider <= cnt && cnt <= 2*divider - 1) begin + scl_clk = 0; + data_clk = 1; + end + else if( 2*divider <= cnt && cnt <= 3*divider - 1) begin + if(scl_clk == 0 & scl_not_ena == 0) + stretch = 1; + else + stretch = 0; + scl_clk = 1; + data_clk = 1; + end + else begin + scl_clk = 1; + data_clk = 0; + end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (!stretch implies (!stretch s_until switch_range))); + // ((G !rst -> G (!stretch -> !stretch U switch_range))) +endmodule diff --git a/examples/Benchmarks/i2c_9.sv b/examples/Benchmarks/i2c_9.sv index 089a8d6d6..646fa1425 100644 --- a/examples/Benchmarks/i2c_9.sv +++ b/examples/Benchmarks/i2c_9.sv @@ -1,4 +1,6 @@ -module i2cStrech #(localparam divider = 3500, localparam CBITS = 14) (input clk, input rst, input scl_not_ena, output reg data_clk); +module i2cStrech(input clk, input rst, input scl_not_ena, output reg data_clk, output reg switch_range); + localparam divider = 3500; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; //0 to 4*divider reg scl_clk; reg stretch; @@ -32,7 +34,11 @@ module i2cStrech #(localparam divider = 3500, localparam CBITS = 14) (input clk, scl_clk = 1; data_clk = 0; end + if(2*divider <= cnt && cnt <= 3*divider - 1) + switch_range = 1; + else + switch_range = 0; end - p1: assert property (@(posedge clk) ((always s_eventually (rst == 1 or scl_not_ena == 1)) or (always s_eventually stretch == 1))) ; - //F G (rst = F & scl_not_ena = F) -> G F (stretch = T) -endmodule \ No newline at end of file + p1: assert property None #(@(posedge clk) s_eventually rst || scl_not_ena || stretch); + // FG (!rst & enable) -> GF stretch +endmodule diff --git a/examples/Benchmarks/lcd_1-s1.sv b/examples/Benchmarks/lcd_1-s1.sv new file mode 100644 index 000000000..8d25c422d --- /dev/null +++ b/examples/Benchmarks/lcd_1-s1.sv @@ -0,0 +1,108 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 1; + localparam CBITS = 9; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + busy = 1; + end + else begin + cnt = 0; + state = 2; + busy = 1; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_1-s2.sv b/examples/Benchmarks/lcd_1-s2.sv new file mode 100644 index 000000000..c250cef3f --- /dev/null +++ b/examples/Benchmarks/lcd_1-s2.sv @@ -0,0 +1,108 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 1; + localparam CBITS = 9; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + busy = 1; + end + else begin + cnt = 0; + state = 2; + busy = 1; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_1-sl1.sv b/examples/Benchmarks/lcd_1-sl1.sv new file mode 100644 index 000000000..c9f152f38 --- /dev/null +++ b/examples/Benchmarks/lcd_1-sl1.sv @@ -0,0 +1,108 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 1; + localparam CBITS = 9; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + busy = 1; + end + else begin + cnt = 0; + state = 2; + busy = 1; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_1.sv b/examples/Benchmarks/lcd_1.sv index 5d7bac753..4314365a9 100644 --- a/examples/Benchmarks/lcd_1.sv +++ b/examples/Benchmarks/lcd_1.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 1, localparam CBITS = 9) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 1; + localparam CBITS = 9; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -87,14 +90,19 @@ module LCD #(localparam clk_freq = 1, localparam CBITS = 9) (input clk, input [6 else if(cnt < 27*clk_freq) // negative enable half-cycle e = 0; cnt = cnt + 1; + busy = 1; end else begin cnt = 0; state = 2; + busy = 1; end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_10-s1.sv b/examples/Benchmarks/lcd_10-s1.sv new file mode 100644 index 000000000..e0893e464 --- /dev/null +++ b/examples/Benchmarks/lcd_10-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 35; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_10-s2.sv b/examples/Benchmarks/lcd_10-s2.sv new file mode 100644 index 000000000..06795da30 --- /dev/null +++ b/examples/Benchmarks/lcd_10-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 35; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_10-sl1.sv b/examples/Benchmarks/lcd_10-sl1.sv new file mode 100644 index 000000000..00cd5f6bb --- /dev/null +++ b/examples/Benchmarks/lcd_10-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 35; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_10.sv b/examples/Benchmarks/lcd_10.sv index cfa66305b..c10be4422 100644 --- a/examples/Benchmarks/lcd_10.sv +++ b/examples/Benchmarks/lcd_10.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 35, localparam CBITS = 15) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 35; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 35, localparam CBITS = 15) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_11-s1.sv b/examples/Benchmarks/lcd_11-s1.sv new file mode 100644 index 000000000..fb116db20 --- /dev/null +++ b/examples/Benchmarks/lcd_11-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 40; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_11-s2.sv b/examples/Benchmarks/lcd_11-s2.sv new file mode 100644 index 000000000..13fe541be --- /dev/null +++ b/examples/Benchmarks/lcd_11-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 40; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_11-sl1.sv b/examples/Benchmarks/lcd_11-sl1.sv new file mode 100644 index 000000000..3c0a8e9a7 --- /dev/null +++ b/examples/Benchmarks/lcd_11-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 40; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_11.sv b/examples/Benchmarks/lcd_11.sv index ab36bfe01..42442319a 100644 --- a/examples/Benchmarks/lcd_11.sv +++ b/examples/Benchmarks/lcd_11.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 40, localparam CBITS = 15) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 40; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 40, localparam CBITS = 15) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_12-s1.sv b/examples/Benchmarks/lcd_12-s1.sv new file mode 100644 index 000000000..544126195 --- /dev/null +++ b/examples/Benchmarks/lcd_12-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 45; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_12-s2.sv b/examples/Benchmarks/lcd_12-s2.sv new file mode 100644 index 000000000..ba6475433 --- /dev/null +++ b/examples/Benchmarks/lcd_12-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 45; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_12-sl1.sv b/examples/Benchmarks/lcd_12-sl1.sv new file mode 100644 index 000000000..fbd24c0ad --- /dev/null +++ b/examples/Benchmarks/lcd_12-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 45; + localparam CBITS = 15; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_12.sv b/examples/Benchmarks/lcd_12.sv index e02b43fa4..c7fd063bc 100644 --- a/examples/Benchmarks/lcd_12.sv +++ b/examples/Benchmarks/lcd_12.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 45, localparam CBITS = 15) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 45; + localparam CBITS = 15; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 45, localparam CBITS = 15) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_13-s1.sv b/examples/Benchmarks/lcd_13-s1.sv new file mode 100644 index 000000000..16e40c8a0 --- /dev/null +++ b/examples/Benchmarks/lcd_13-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 180; + localparam CBITS = 17; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_13-s2.sv b/examples/Benchmarks/lcd_13-s2.sv new file mode 100644 index 000000000..e34fa39db --- /dev/null +++ b/examples/Benchmarks/lcd_13-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 180; + localparam CBITS = 17; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_13-sl1.sv b/examples/Benchmarks/lcd_13-sl1.sv new file mode 100644 index 000000000..f7fa2c929 --- /dev/null +++ b/examples/Benchmarks/lcd_13-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 180; + localparam CBITS = 17; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_13.sv b/examples/Benchmarks/lcd_13.sv index 1129ebbb5..02fa09af5 100644 --- a/examples/Benchmarks/lcd_13.sv +++ b/examples/Benchmarks/lcd_13.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 180, localparam CBITS = 17) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 180; + localparam CBITS = 17; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,10 +97,10 @@ module LCD #(localparam clk_freq = 180, localparam CBITS = 17) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) -endmodule + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) +endmodule diff --git a/examples/Benchmarks/lcd_14-s1.sv b/examples/Benchmarks/lcd_14-s1.sv new file mode 100644 index 000000000..9fe6d2ce9 --- /dev/null +++ b/examples/Benchmarks/lcd_14-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 360; + localparam CBITS = 18; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_14-s2.sv b/examples/Benchmarks/lcd_14-s2.sv new file mode 100644 index 000000000..535ffd645 --- /dev/null +++ b/examples/Benchmarks/lcd_14-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 360; + localparam CBITS = 18; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_14-sl1.sv b/examples/Benchmarks/lcd_14-sl1.sv new file mode 100644 index 000000000..c13c39592 --- /dev/null +++ b/examples/Benchmarks/lcd_14-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 360; + localparam CBITS = 18; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_14.sv b/examples/Benchmarks/lcd_14.sv index d01cfb47d..76946b4fa 100644 --- a/examples/Benchmarks/lcd_14.sv +++ b/examples/Benchmarks/lcd_14.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 360, localparam CBITS = 18) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 360; + localparam CBITS = 18; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,10 +97,10 @@ module LCD #(localparam clk_freq = 360, localparam CBITS = 18) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) -endmodule + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) +endmodule diff --git a/examples/Benchmarks/lcd_2-s1.sv b/examples/Benchmarks/lcd_2-s1.sv new file mode 100644 index 000000000..237c1ddbe --- /dev/null +++ b/examples/Benchmarks/lcd_2-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 2; + localparam CBITS = 10; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_2-s2.sv b/examples/Benchmarks/lcd_2-s2.sv new file mode 100644 index 000000000..c9e992981 --- /dev/null +++ b/examples/Benchmarks/lcd_2-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 2; + localparam CBITS = 10; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_2-sl1.sv b/examples/Benchmarks/lcd_2-sl1.sv new file mode 100644 index 000000000..da3b9465d --- /dev/null +++ b/examples/Benchmarks/lcd_2-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 2; + localparam CBITS = 10; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_2.sv b/examples/Benchmarks/lcd_2.sv index 1134e3540..719d7997e 100644 --- a/examples/Benchmarks/lcd_2.sv +++ b/examples/Benchmarks/lcd_2.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 2, localparam CBITS = 10) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 2; + localparam CBITS = 10; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 2, localparam CBITS = 10) (input clk, input [ end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_3-s1.sv b/examples/Benchmarks/lcd_3-s1.sv new file mode 100644 index 000000000..ba3d3502a --- /dev/null +++ b/examples/Benchmarks/lcd_3-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 3; + localparam CBITS = 11; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_3-s2.sv b/examples/Benchmarks/lcd_3-s2.sv new file mode 100644 index 000000000..bacb6a810 --- /dev/null +++ b/examples/Benchmarks/lcd_3-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 3; + localparam CBITS = 11; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_3-sl1.sv b/examples/Benchmarks/lcd_3-sl1.sv new file mode 100644 index 000000000..4e2e05f52 --- /dev/null +++ b/examples/Benchmarks/lcd_3-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 3; + localparam CBITS = 11; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_3.sv b/examples/Benchmarks/lcd_3.sv index 87fb455b9..52d635354 100644 --- a/examples/Benchmarks/lcd_3.sv +++ b/examples/Benchmarks/lcd_3.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 3, localparam CBITS = 11) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 3; + localparam CBITS = 11; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,10 +97,10 @@ module LCD #(localparam clk_freq = 3, localparam CBITS = 11) (input clk, input [ end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) -endmodule + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) +endmodule diff --git a/examples/Benchmarks/lcd_4-s1.sv b/examples/Benchmarks/lcd_4-s1.sv new file mode 100644 index 000000000..890a4fe27 --- /dev/null +++ b/examples/Benchmarks/lcd_4-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 5; + localparam CBITS = 12; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_4-s2.sv b/examples/Benchmarks/lcd_4-s2.sv new file mode 100644 index 000000000..6d9be105d --- /dev/null +++ b/examples/Benchmarks/lcd_4-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 5; + localparam CBITS = 12; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_4-sl1.sv b/examples/Benchmarks/lcd_4-sl1.sv new file mode 100644 index 000000000..e3c665110 --- /dev/null +++ b/examples/Benchmarks/lcd_4-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 5; + localparam CBITS = 12; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_4.sv b/examples/Benchmarks/lcd_4.sv index d26cba24a..6665e4842 100644 --- a/examples/Benchmarks/lcd_4.sv +++ b/examples/Benchmarks/lcd_4.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 5, localparam CBITS = 12) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 5; + localparam CBITS = 12; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 5, localparam CBITS = 12) (input clk, input [ end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_5-s1.sv b/examples/Benchmarks/lcd_5-s1.sv new file mode 100644 index 000000000..8f56a251f --- /dev/null +++ b/examples/Benchmarks/lcd_5-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 10; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_5-s2.sv b/examples/Benchmarks/lcd_5-s2.sv new file mode 100644 index 000000000..79df5e51f --- /dev/null +++ b/examples/Benchmarks/lcd_5-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 10; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_5-sl1.sv b/examples/Benchmarks/lcd_5-sl1.sv new file mode 100644 index 000000000..bf1538cbe --- /dev/null +++ b/examples/Benchmarks/lcd_5-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 10; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_5.sv b/examples/Benchmarks/lcd_5.sv index f57b28c13..e4102628a 100644 --- a/examples/Benchmarks/lcd_5.sv +++ b/examples/Benchmarks/lcd_5.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 10, localparam CBITS = 13) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 10; + localparam CBITS = 13; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,10 +97,10 @@ module LCD #(localparam clk_freq = 10, localparam CBITS = 13) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2) ; - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) -endmodule + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) +endmodule diff --git a/examples/Benchmarks/lcd_6-s1.sv b/examples/Benchmarks/lcd_6-s1.sv new file mode 100644 index 000000000..70dda75b1 --- /dev/null +++ b/examples/Benchmarks/lcd_6-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 15; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_6-s2.sv b/examples/Benchmarks/lcd_6-s2.sv new file mode 100644 index 000000000..7e75ded11 --- /dev/null +++ b/examples/Benchmarks/lcd_6-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 15; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_6-sl1.sv b/examples/Benchmarks/lcd_6-sl1.sv new file mode 100644 index 000000000..da1324dda --- /dev/null +++ b/examples/Benchmarks/lcd_6-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 15; + localparam CBITS = 13; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_6.sv b/examples/Benchmarks/lcd_6.sv index 4190ff996..6a65bc161 100644 --- a/examples/Benchmarks/lcd_6.sv +++ b/examples/Benchmarks/lcd_6.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 15, localparam CBITS = 13) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 15; + localparam CBITS = 13; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 15, localparam CBITS = 13) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_7-s1.sv b/examples/Benchmarks/lcd_7-s1.sv new file mode 100644 index 000000000..cc617e3d0 --- /dev/null +++ b/examples/Benchmarks/lcd_7-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 20; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_7-s2.sv b/examples/Benchmarks/lcd_7-s2.sv new file mode 100644 index 000000000..6b89b08e3 --- /dev/null +++ b/examples/Benchmarks/lcd_7-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 20; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_7-sl1.sv b/examples/Benchmarks/lcd_7-sl1.sv new file mode 100644 index 000000000..7aec02da4 --- /dev/null +++ b/examples/Benchmarks/lcd_7-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 20; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_7.sv b/examples/Benchmarks/lcd_7.sv index a1044ce00..7e80c3c62 100644 --- a/examples/Benchmarks/lcd_7.sv +++ b/examples/Benchmarks/lcd_7.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 20, localparam CBITS = 14) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 20; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 20, localparam CBITS = 14) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_8-s1.sv b/examples/Benchmarks/lcd_8-s1.sv new file mode 100644 index 000000000..e19165300 --- /dev/null +++ b/examples/Benchmarks/lcd_8-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 25; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_8-s2.sv b/examples/Benchmarks/lcd_8-s2.sv new file mode 100644 index 000000000..696a5199b --- /dev/null +++ b/examples/Benchmarks/lcd_8-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 25; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_8-sl1.sv b/examples/Benchmarks/lcd_8-sl1.sv new file mode 100644 index 000000000..80bc85a55 --- /dev/null +++ b/examples/Benchmarks/lcd_8-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 25; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_8.sv b/examples/Benchmarks/lcd_8.sv index 6dd2dd3cd..7ecdc8f0a 100644 --- a/examples/Benchmarks/lcd_8.sv +++ b/examples/Benchmarks/lcd_8.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 25, localparam CBITS = 14) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 25; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 25, localparam CBITS = 14) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/lcd_9-s1.sv b/examples/Benchmarks/lcd_9-s1.sv new file mode 100644 index 000000000..096adec45 --- /dev/null +++ b/examples/Benchmarks/lcd_9-s1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 30; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s1: assert property (@(posedge clk) !lcd_enable && state==2 |=> state==2); + // XG ((!enable & state2) -> (X state2)) +endmodule diff --git a/examples/Benchmarks/lcd_9-s2.sv b/examples/Benchmarks/lcd_9-s2.sv new file mode 100644 index 000000000..71d7b9336 --- /dev/null +++ b/examples/Benchmarks/lcd_9-s2.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 30; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + s2: assert property (@(posedge clk) s_nexttime ((s_nexttime state==1) implies busy)); + // XG ((X state1) -> (busy)) +endmodule diff --git a/examples/Benchmarks/lcd_9-sl1.sv b/examples/Benchmarks/lcd_9-sl1.sv new file mode 100644 index 000000000..3749137b0 --- /dev/null +++ b/examples/Benchmarks/lcd_9-sl1.sv @@ -0,0 +1,106 @@ +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 30; + localparam CBITS = 14; + reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg + reg [1:0] state; + + always @(posedge clk) begin + rw = 0; + rs = 0; + busy = 0; + lcd_data = 0; + e = 0; + if(state == 0) begin + busy = 1; + if(cnt < 500*clk_freq) // wait 500 + cnt = cnt + 1; + else begin // power-up completed + cnt = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00110000; + state = 1; + end + end + if(state == 1) begin + busy = 1; + cnt = cnt + 1; + if(cnt < (10*clk_freq))begin //function set + lcd_data = {4'b0011, in_data[6], in_data[5], 2'b00}; + e = 1; + end + else if(cnt < (60*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (70*clk_freq))begin //display on/off control + lcd_data = {5'b00001, in_data[4], in_data[3], in_data[2]}; + e = 1; + end + else if(cnt < (120*clk_freq))begin // wait 50 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (130*clk_freq))begin // display clear + lcd_data = 8'b00000001; + e = 1; + end + else if(cnt < (330*clk_freq))begin // wait 200 + lcd_data = 8'b00000000; + e = 0; + end + else if(cnt < (340*clk_freq))begin // entry mode set + lcd_data = {6'b000001, in_data[1], in_data[0]}; + e = 1; + end + else if(cnt < (440*clk_freq))begin // wait 100 + lcd_data = 8'b00000000; + e = 0; + end + else begin // initialization complete + cnt = 0; + busy = 0; + state = 2; + end + end + if(state == 2) begin + if(lcd_enable == 1) begin + busy = 1; + rs = lcd_bus[9]; + rw = lcd_bus[8]; + lcd_data = lcd_bus[7:0]; + cnt = 0; + state = 3; + end + else begin + busy = 0; + rs = 0; + rw = 0; + lcd_data = 8'b00000000; + cnt = 0; + end + end + if(state == 3) begin + if(cnt < 50* clk_freq) begin // do not exit for 50 + if(cnt < clk_freq) + e = 0; + else if(cnt < 14*clk_freq) // positive enable half-cycle + e = 1; + else if(cnt < 27*clk_freq) // negative enable half-cycle + e = 0; + cnt = cnt + 1; + end + else begin + cnt = 0; + state = 2; + end + end + end + + + + + sl1: assert property (@(posedge clk) state==3 implies (state==3 s_until state==2)); + // G (state3 -> state3 U state2) +endmodule diff --git a/examples/Benchmarks/lcd_9.sv b/examples/Benchmarks/lcd_9.sv index 7a9ba9af4..e0792c855 100644 --- a/examples/Benchmarks/lcd_9.sv +++ b/examples/Benchmarks/lcd_9.sv @@ -1,4 +1,7 @@ -module LCD #(localparam clk_freq = 30, localparam CBITS = 14) (input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); +module LCD(input clk, input [6:0] in_data, input lcd_enable, input [9:0] lcd_bus, output reg e, output reg[7:0] lcd_data, output reg rw, output reg rs, output reg busy); + //in_data -> {display_lines, character_font, display_on_off, cursor, blink, inc_dec, shift} + localparam clk_freq = 30; + localparam CBITS = 14; reg [CBITS - 1:0] cnt; // 0 to 500*clk_freg reg [1:0] state; @@ -94,6 +97,10 @@ module LCD #(localparam clk_freq = 30, localparam CBITS = 14) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually lcd_enable == 0 || state == 2); - //F G (lcd_enable = T) -> G F (state[1] = T & state[0] = F) + + + + + p1: assert property (@(posedge clk) s_eventually lcd_enable -> state == 2); + // FG enable -> (GF state = 2) endmodule diff --git a/examples/Benchmarks/load_store_1-s1.sv b/examples/Benchmarks/load_store_1-s1.sv new file mode 100644 index 000000000..c113689b0 --- /dev/null +++ b/examples/Benchmarks/load_store_1-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_1-sl1.sv b/examples/Benchmarks/load_store_1-sl1.sv new file mode 100644 index 000000000..1046d2f9f --- /dev/null +++ b/examples/Benchmarks/load_store_1-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_1-sl2.sv b/examples/Benchmarks/load_store_1-sl2.sv new file mode 100644 index 000000000..46feb7088 --- /dev/null +++ b/examples/Benchmarks/load_store_1-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_1.sv b/examples/Benchmarks/load_store_1.sv new file mode 100644 index 000000000..77f916c4b --- /dev/null +++ b/examples/Benchmarks/load_store_1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 750; + localparam CBITS = 10; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_10-s1.sv b/examples/Benchmarks/load_store_10-s1.sv new file mode 100644 index 000000000..5ccfe6175 --- /dev/null +++ b/examples/Benchmarks/load_store_10-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_10-sl1.sv b/examples/Benchmarks/load_store_10-sl1.sv new file mode 100644 index 000000000..dd2c656a3 --- /dev/null +++ b/examples/Benchmarks/load_store_10-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_10-sl2.sv b/examples/Benchmarks/load_store_10-sl2.sv new file mode 100644 index 000000000..69da40094 --- /dev/null +++ b/examples/Benchmarks/load_store_10-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_10.sv b/examples/Benchmarks/load_store_10.sv new file mode 100644 index 000000000..d08eae2f8 --- /dev/null +++ b/examples/Benchmarks/load_store_10.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 20000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_11-s1.sv b/examples/Benchmarks/load_store_11-s1.sv new file mode 100644 index 000000000..f1f4d29ae --- /dev/null +++ b/examples/Benchmarks/load_store_11-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_11-sl1.sv b/examples/Benchmarks/load_store_11-sl1.sv new file mode 100644 index 000000000..9ffb6a0ac --- /dev/null +++ b/examples/Benchmarks/load_store_11-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_11-sl2.sv b/examples/Benchmarks/load_store_11-sl2.sv new file mode 100644 index 000000000..0e34564f1 --- /dev/null +++ b/examples/Benchmarks/load_store_11-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_11.sv b/examples/Benchmarks/load_store_11.sv new file mode 100644 index 000000000..2f291f097 --- /dev/null +++ b/examples/Benchmarks/load_store_11.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 22500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_12-s1.sv b/examples/Benchmarks/load_store_12-s1.sv new file mode 100644 index 000000000..c9966bf27 --- /dev/null +++ b/examples/Benchmarks/load_store_12-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_12-sl1.sv b/examples/Benchmarks/load_store_12-sl1.sv new file mode 100644 index 000000000..6caf17dcf --- /dev/null +++ b/examples/Benchmarks/load_store_12-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_12-sl2.sv b/examples/Benchmarks/load_store_12-sl2.sv new file mode 100644 index 000000000..f648eb40a --- /dev/null +++ b/examples/Benchmarks/load_store_12-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_12.sv b/examples/Benchmarks/load_store_12.sv new file mode 100644 index 000000000..c79db71a5 --- /dev/null +++ b/examples/Benchmarks/load_store_12.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 25000; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_13-s1.sv b/examples/Benchmarks/load_store_13-s1.sv new file mode 100644 index 000000000..3066696ef --- /dev/null +++ b/examples/Benchmarks/load_store_13-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_13-sl1.sv b/examples/Benchmarks/load_store_13-sl1.sv new file mode 100644 index 000000000..0bb408b9c --- /dev/null +++ b/examples/Benchmarks/load_store_13-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_13-sl2.sv b/examples/Benchmarks/load_store_13-sl2.sv new file mode 100644 index 000000000..64a1c3d09 --- /dev/null +++ b/examples/Benchmarks/load_store_13-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_13.sv b/examples/Benchmarks/load_store_13.sv new file mode 100644 index 000000000..1a0719543 --- /dev/null +++ b/examples/Benchmarks/load_store_13.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 50000; + localparam CBITS = 16; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_14-s1.sv b/examples/Benchmarks/load_store_14-s1.sv new file mode 100644 index 000000000..6d2ffeb51 --- /dev/null +++ b/examples/Benchmarks/load_store_14-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_14-sl1.sv b/examples/Benchmarks/load_store_14-sl1.sv new file mode 100644 index 000000000..4b7bbeb90 --- /dev/null +++ b/examples/Benchmarks/load_store_14-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_14-sl2.sv b/examples/Benchmarks/load_store_14-sl2.sv new file mode 100644 index 000000000..3a26b415c --- /dev/null +++ b/examples/Benchmarks/load_store_14-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_14.sv b/examples/Benchmarks/load_store_14.sv new file mode 100644 index 000000000..fde96577f --- /dev/null +++ b/examples/Benchmarks/load_store_14.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 100000; + localparam CBITS = 17; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_15-s1.sv b/examples/Benchmarks/load_store_15-s1.sv new file mode 100644 index 000000000..9fb6f2d13 --- /dev/null +++ b/examples/Benchmarks/load_store_15-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_15-sl1.sv b/examples/Benchmarks/load_store_15-sl1.sv new file mode 100644 index 000000000..d8d7e82f9 --- /dev/null +++ b/examples/Benchmarks/load_store_15-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_15-sl2.sv b/examples/Benchmarks/load_store_15-sl2.sv new file mode 100644 index 000000000..6027c88a5 --- /dev/null +++ b/examples/Benchmarks/load_store_15-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_15.sv b/examples/Benchmarks/load_store_15.sv new file mode 100644 index 000000000..d08ccafd6 --- /dev/null +++ b/examples/Benchmarks/load_store_15.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 200000; + localparam CBITS = 18; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_16-s1.sv b/examples/Benchmarks/load_store_16-s1.sv new file mode 100644 index 000000000..5458ddd3a --- /dev/null +++ b/examples/Benchmarks/load_store_16-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_16-sl1.sv b/examples/Benchmarks/load_store_16-sl1.sv new file mode 100644 index 000000000..88f6747ef --- /dev/null +++ b/examples/Benchmarks/load_store_16-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_16-sl2.sv b/examples/Benchmarks/load_store_16-sl2.sv new file mode 100644 index 000000000..f70540ab7 --- /dev/null +++ b/examples/Benchmarks/load_store_16-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_16.sv b/examples/Benchmarks/load_store_16.sv new file mode 100644 index 000000000..7f3e74099 --- /dev/null +++ b/examples/Benchmarks/load_store_16.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 400000; + localparam CBITS = 19; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_2-s1.sv b/examples/Benchmarks/load_store_2-s1.sv new file mode 100644 index 000000000..d5895a44a --- /dev/null +++ b/examples/Benchmarks/load_store_2-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_2-sl1.sv b/examples/Benchmarks/load_store_2-sl1.sv new file mode 100644 index 000000000..44585f444 --- /dev/null +++ b/examples/Benchmarks/load_store_2-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_2-sl2.sv b/examples/Benchmarks/load_store_2-sl2.sv new file mode 100644 index 000000000..f9bf35844 --- /dev/null +++ b/examples/Benchmarks/load_store_2-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_2.sv b/examples/Benchmarks/load_store_2.sv new file mode 100644 index 000000000..4931396e2 --- /dev/null +++ b/examples/Benchmarks/load_store_2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 1250; + localparam CBITS = 11; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_3-s1.sv b/examples/Benchmarks/load_store_3-s1.sv new file mode 100644 index 000000000..66a333f0f --- /dev/null +++ b/examples/Benchmarks/load_store_3-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_3-sl1.sv b/examples/Benchmarks/load_store_3-sl1.sv new file mode 100644 index 000000000..2576dfd57 --- /dev/null +++ b/examples/Benchmarks/load_store_3-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_3-sl2.sv b/examples/Benchmarks/load_store_3-sl2.sv new file mode 100644 index 000000000..c1e628223 --- /dev/null +++ b/examples/Benchmarks/load_store_3-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_3.sv b/examples/Benchmarks/load_store_3.sv new file mode 100644 index 000000000..d1c737476 --- /dev/null +++ b/examples/Benchmarks/load_store_3.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 2500; + localparam CBITS = 12; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_4-s1.sv b/examples/Benchmarks/load_store_4-s1.sv new file mode 100644 index 000000000..e30ba06d6 --- /dev/null +++ b/examples/Benchmarks/load_store_4-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_4-sl1.sv b/examples/Benchmarks/load_store_4-sl1.sv new file mode 100644 index 000000000..d1965a135 --- /dev/null +++ b/examples/Benchmarks/load_store_4-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_4-sl2.sv b/examples/Benchmarks/load_store_4-sl2.sv new file mode 100644 index 000000000..2ac0ade01 --- /dev/null +++ b/examples/Benchmarks/load_store_4-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_4.sv b/examples/Benchmarks/load_store_4.sv new file mode 100644 index 000000000..40f571137 --- /dev/null +++ b/examples/Benchmarks/load_store_4.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 5000; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_5-s1.sv b/examples/Benchmarks/load_store_5-s1.sv new file mode 100644 index 000000000..cfa91591f --- /dev/null +++ b/examples/Benchmarks/load_store_5-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_5-sl1.sv b/examples/Benchmarks/load_store_5-sl1.sv new file mode 100644 index 000000000..423c8e3aa --- /dev/null +++ b/examples/Benchmarks/load_store_5-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_5-sl2.sv b/examples/Benchmarks/load_store_5-sl2.sv new file mode 100644 index 000000000..b3d24aef9 --- /dev/null +++ b/examples/Benchmarks/load_store_5-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_5.sv b/examples/Benchmarks/load_store_5.sv new file mode 100644 index 000000000..2db36c3fa --- /dev/null +++ b/examples/Benchmarks/load_store_5.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 7500; + localparam CBITS = 13; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_6-s1.sv b/examples/Benchmarks/load_store_6-s1.sv new file mode 100644 index 000000000..86394502f --- /dev/null +++ b/examples/Benchmarks/load_store_6-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_6-sl1.sv b/examples/Benchmarks/load_store_6-sl1.sv new file mode 100644 index 000000000..de4939521 --- /dev/null +++ b/examples/Benchmarks/load_store_6-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_6-sl2.sv b/examples/Benchmarks/load_store_6-sl2.sv new file mode 100644 index 000000000..c3c4c2edd --- /dev/null +++ b/examples/Benchmarks/load_store_6-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_6.sv b/examples/Benchmarks/load_store_6.sv new file mode 100644 index 000000000..b854c8e02 --- /dev/null +++ b/examples/Benchmarks/load_store_6.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 10000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_7-s1.sv b/examples/Benchmarks/load_store_7-s1.sv new file mode 100644 index 000000000..e3ba95c1e --- /dev/null +++ b/examples/Benchmarks/load_store_7-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_7-sl1.sv b/examples/Benchmarks/load_store_7-sl1.sv new file mode 100644 index 000000000..31fc54b87 --- /dev/null +++ b/examples/Benchmarks/load_store_7-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_7-sl2.sv b/examples/Benchmarks/load_store_7-sl2.sv new file mode 100644 index 000000000..4134786e4 --- /dev/null +++ b/examples/Benchmarks/load_store_7-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_7.sv b/examples/Benchmarks/load_store_7.sv new file mode 100644 index 000000000..211cf8bf5 --- /dev/null +++ b/examples/Benchmarks/load_store_7.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 12500; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_8-s1.sv b/examples/Benchmarks/load_store_8-s1.sv new file mode 100644 index 000000000..d14876f36 --- /dev/null +++ b/examples/Benchmarks/load_store_8-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_8-sl1.sv b/examples/Benchmarks/load_store_8-sl1.sv new file mode 100644 index 000000000..556a61631 --- /dev/null +++ b/examples/Benchmarks/load_store_8-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_8-sl2.sv b/examples/Benchmarks/load_store_8-sl2.sv new file mode 100644 index 000000000..d6c7f086b --- /dev/null +++ b/examples/Benchmarks/load_store_8-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_8.sv b/examples/Benchmarks/load_store_8.sv new file mode 100644 index 000000000..9c0ad1980 --- /dev/null +++ b/examples/Benchmarks/load_store_8.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 15000; + localparam CBITS = 14; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/load_store_9-s1.sv b/examples/Benchmarks/load_store_9-s1.sv new file mode 100644 index 000000000..eb260c10c --- /dev/null +++ b/examples/Benchmarks/load_store_9-s1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + s1: assert property (@(posedge clk) s_nexttime (sig |-> ##2 !sig)); + // XG (sig -> X X !sig) +endmodule diff --git a/examples/Benchmarks/load_store_9-sl1.sv b/examples/Benchmarks/load_store_9-sl1.sv new file mode 100644 index 000000000..7db43b172 --- /dev/null +++ b/examples/Benchmarks/load_store_9-sl1.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always (m implies (m s_until sig))); + // G !rst -> G (m -> (m U s)) +endmodule diff --git a/examples/Benchmarks/load_store_9-sl2.sv b/examples/Benchmarks/load_store_9-sl2.sv new file mode 100644 index 000000000..63526296d --- /dev/null +++ b/examples/Benchmarks/load_store_9-sl2.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + sl2: assert property (@(posedge clk) (always !rst) implies s_nexttime always (m implies (!sig s_until s_nexttime !m))); + // G !rst -> X G (m -> (!s U X !m)) +endmodule diff --git a/examples/Benchmarks/load_store_9.sv b/examples/Benchmarks/load_store_9.sv new file mode 100644 index 000000000..49dd99a66 --- /dev/null +++ b/examples/Benchmarks/load_store_9.sv @@ -0,0 +1,24 @@ +module Load_Store (input clk, input rst, output reg sig); + localparam N = 17500; + localparam CBITS = 15; + reg [CBITS-1:0] vol; + reg m; + always @(posedge clk) begin + if (rst) begin m = 0; vol = 0; sig = 0; + end else begin + if (m) begin + if (vol >= N) m = 0; else vol = vol + 1; + end else begin + if (vol <= 0) m = 1; else vol = vol - 1; + end + if (vol >= N) begin + sig = 1; + vol = N; + end + else + sig = 0; + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> sig); + // FG !rst -> GF (vol = N) +endmodule diff --git a/examples/Benchmarks/seven_seg_1-p2.sv b/examples/Benchmarks/seven_seg_1-p2.sv new file mode 100644 index 000000000..46f02fd8c --- /dev/null +++ b/examples/Benchmarks/seven_seg_1-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 250; + localparam CBITS = 8; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_1-s1.sv b/examples/Benchmarks/seven_seg_1-s1.sv new file mode 100644 index 000000000..19ee71bc6 --- /dev/null +++ b/examples/Benchmarks/seven_seg_1-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 250; + localparam CBITS = 8; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_1-sl1.sv b/examples/Benchmarks/seven_seg_1-sl1.sv new file mode 100644 index 000000000..15b1aa2f0 --- /dev/null +++ b/examples/Benchmarks/seven_seg_1-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 250; + localparam CBITS = 8; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_1.sv b/examples/Benchmarks/seven_seg_1.sv index 09c0a2241..be4c84720 100644 --- a/examples/Benchmarks/seven_seg_1.sv +++ b/examples/Benchmarks/seven_seg_1.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 250, localparam CBITS = 8) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 250; + localparam CBITS = 8; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 250, localparam CBITS = 8) (input clk, input rs digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 250, localparam CBITS = 8) (input clk, input rs end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_10-p2.sv b/examples/Benchmarks/seven_seg_10-p2.sv new file mode 100644 index 000000000..e991e3f66 --- /dev/null +++ b/examples/Benchmarks/seven_seg_10-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 15000; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_10-s1.sv b/examples/Benchmarks/seven_seg_10-s1.sv new file mode 100644 index 000000000..951069b6a --- /dev/null +++ b/examples/Benchmarks/seven_seg_10-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 15000; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_10-sl1.sv b/examples/Benchmarks/seven_seg_10-sl1.sv new file mode 100644 index 000000000..3006f1bb7 --- /dev/null +++ b/examples/Benchmarks/seven_seg_10-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 15000; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_10.sv b/examples/Benchmarks/seven_seg_10.sv index eb819f3b0..bfa4ae0ee 100644 --- a/examples/Benchmarks/seven_seg_10.sv +++ b/examples/Benchmarks/seven_seg_10.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 15000, localparam CBITS = 14) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 15000; + localparam CBITS = 14; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 15000, localparam CBITS = 14) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 15000, localparam CBITS = 14) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_11-p2.sv b/examples/Benchmarks/seven_seg_11-p2.sv new file mode 100644 index 000000000..daa96f345 --- /dev/null +++ b/examples/Benchmarks/seven_seg_11-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 17500; + localparam CBITS = 15; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_11-s1.sv b/examples/Benchmarks/seven_seg_11-s1.sv new file mode 100644 index 000000000..6279d3913 --- /dev/null +++ b/examples/Benchmarks/seven_seg_11-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 17500; + localparam CBITS = 15; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_11-sl1.sv b/examples/Benchmarks/seven_seg_11-sl1.sv new file mode 100644 index 000000000..4a1f2c7ed --- /dev/null +++ b/examples/Benchmarks/seven_seg_11-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 17500; + localparam CBITS = 15; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_11.sv b/examples/Benchmarks/seven_seg_11.sv index 03da8a9bc..28c901f7c 100644 --- a/examples/Benchmarks/seven_seg_11.sv +++ b/examples/Benchmarks/seven_seg_11.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 17500, localparam CBITS = 15) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 17500; + localparam CBITS = 15; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 17500, localparam CBITS = 15) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 17500, localparam CBITS = 15) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_12-p2.sv b/examples/Benchmarks/seven_seg_12-p2.sv new file mode 100644 index 000000000..a4fdf6cc7 --- /dev/null +++ b/examples/Benchmarks/seven_seg_12-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 20000; + localparam CBITS = 15; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_12-s1.sv b/examples/Benchmarks/seven_seg_12-s1.sv new file mode 100644 index 000000000..e6e91c7a5 --- /dev/null +++ b/examples/Benchmarks/seven_seg_12-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 20000; + localparam CBITS = 15; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_12-sl1.sv b/examples/Benchmarks/seven_seg_12-sl1.sv new file mode 100644 index 000000000..4180c1e9e --- /dev/null +++ b/examples/Benchmarks/seven_seg_12-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 20000; + localparam CBITS = 15; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_12.sv b/examples/Benchmarks/seven_seg_12.sv index aff53baae..054ec5aee 100644 --- a/examples/Benchmarks/seven_seg_12.sv +++ b/examples/Benchmarks/seven_seg_12.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 20000, localparam CBITS = 15) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 20000; + localparam CBITS = 15; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 20000, localparam CBITS = 15) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 20000, localparam CBITS = 15) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_13-p2.sv b/examples/Benchmarks/seven_seg_13-p2.sv new file mode 100644 index 000000000..dc1bb0318 --- /dev/null +++ b/examples/Benchmarks/seven_seg_13-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 40000; + localparam CBITS = 16; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_13-s1.sv b/examples/Benchmarks/seven_seg_13-s1.sv new file mode 100644 index 000000000..c9d3efbd6 --- /dev/null +++ b/examples/Benchmarks/seven_seg_13-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 40000; + localparam CBITS = 16; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_13-sl1.sv b/examples/Benchmarks/seven_seg_13-sl1.sv new file mode 100644 index 000000000..64267fe47 --- /dev/null +++ b/examples/Benchmarks/seven_seg_13-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 40000; + localparam CBITS = 16; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_13.sv b/examples/Benchmarks/seven_seg_13.sv new file mode 100644 index 000000000..47372f0eb --- /dev/null +++ b/examples/Benchmarks/seven_seg_13.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 40000; + localparam CBITS = 16; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_14-p2.sv b/examples/Benchmarks/seven_seg_14-p2.sv new file mode 100644 index 000000000..b92fcb11d --- /dev/null +++ b/examples/Benchmarks/seven_seg_14-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 80000; + localparam CBITS = 17; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_14-s1.sv b/examples/Benchmarks/seven_seg_14-s1.sv new file mode 100644 index 000000000..7956823a0 --- /dev/null +++ b/examples/Benchmarks/seven_seg_14-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 80000; + localparam CBITS = 17; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_14-sl1.sv b/examples/Benchmarks/seven_seg_14-sl1.sv new file mode 100644 index 000000000..0174d8a89 --- /dev/null +++ b/examples/Benchmarks/seven_seg_14-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 80000; + localparam CBITS = 17; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_14.sv b/examples/Benchmarks/seven_seg_14.sv new file mode 100644 index 000000000..e400f7851 --- /dev/null +++ b/examples/Benchmarks/seven_seg_14.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 80000; + localparam CBITS = 17; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_15-p2.sv b/examples/Benchmarks/seven_seg_15-p2.sv new file mode 100644 index 000000000..1a335c2fc --- /dev/null +++ b/examples/Benchmarks/seven_seg_15-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 160000; + localparam CBITS = 18; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_15-s1.sv b/examples/Benchmarks/seven_seg_15-s1.sv new file mode 100644 index 000000000..cbf55624b --- /dev/null +++ b/examples/Benchmarks/seven_seg_15-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 160000; + localparam CBITS = 18; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_15-sl1.sv b/examples/Benchmarks/seven_seg_15-sl1.sv new file mode 100644 index 000000000..5be1e5229 --- /dev/null +++ b/examples/Benchmarks/seven_seg_15-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 160000; + localparam CBITS = 18; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_15.sv b/examples/Benchmarks/seven_seg_15.sv new file mode 100644 index 000000000..5f0cf4627 --- /dev/null +++ b/examples/Benchmarks/seven_seg_15.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 160000; + localparam CBITS = 18; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_16.sv b/examples/Benchmarks/seven_seg_16.sv deleted file mode 100644 index 989fb518d..000000000 --- a/examples/Benchmarks/seven_seg_16.sv +++ /dev/null @@ -1,29 +0,0 @@ -module SEVEN #(localparam freq = 40000, localparam CBITS = 16) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); - reg [CBITS-1:0] cnt; - reg digit_select; - - always @(posedge clk) begin - if(rst == 1) begin - cnt = 0; - digit_select = 0; - segment = 0; - end - if(cnt < freq) - cnt = cnt + 1; - else begin - cnt = 0; - if(digit_select == 0) begin - digit_select = 1; - segment = both7seg[13:7]; - end - else begin - digit_select = 0; - segment = both7seg[6:0]; - end - end - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) -endmodule diff --git a/examples/Benchmarks/seven_seg_17.sv b/examples/Benchmarks/seven_seg_17.sv deleted file mode 100644 index c3d1aab6a..000000000 --- a/examples/Benchmarks/seven_seg_17.sv +++ /dev/null @@ -1,29 +0,0 @@ -module SEVEN #(localparam freq = 80000, localparam CBITS = 17) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); - reg [CBITS-1:0] cnt; - reg digit_select; - - always @(posedge clk) begin - if(rst == 1) begin - cnt = 0; - digit_select = 0; - segment = 0; - end - if(cnt < freq) - cnt = cnt + 1; - else begin - cnt = 0; - if(digit_select == 0) begin - digit_select = 1; - segment = both7seg[13:7]; - end - else begin - digit_select = 0; - segment = both7seg[6:0]; - end - end - end - p1: assert property (@(posedge clk) s_eventually rst || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) -endmodule diff --git a/examples/Benchmarks/seven_seg_18.sv b/examples/Benchmarks/seven_seg_18.sv deleted file mode 100644 index a4b54ba7a..000000000 --- a/examples/Benchmarks/seven_seg_18.sv +++ /dev/null @@ -1,29 +0,0 @@ -module SEVEN #(localparam freq = 160000, localparam CBITS = 18) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); - reg [CBITS-1:0] cnt; - reg digit_select; - - always @(posedge clk) begin - if(rst == 1) begin - cnt = 0; - digit_select = 0; - segment = 0; - end - if(cnt < freq) - cnt = cnt + 1; - else begin - cnt = 0; - if(digit_select == 0) begin - digit_select = 1; - segment = both7seg[13:7]; - end - else begin - digit_select = 0; - segment = both7seg[6:0]; - end - end - end - p1: assert property (@(posedge clk) s_eventually rst || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) -endmodule diff --git a/examples/Benchmarks/seven_seg_2-p2.sv b/examples/Benchmarks/seven_seg_2-p2.sv new file mode 100644 index 000000000..bbe596f26 --- /dev/null +++ b/examples/Benchmarks/seven_seg_2-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 500; + localparam CBITS = 9; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_2-s1.sv b/examples/Benchmarks/seven_seg_2-s1.sv new file mode 100644 index 000000000..867c1ecc7 --- /dev/null +++ b/examples/Benchmarks/seven_seg_2-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 500; + localparam CBITS = 9; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_2-sl1.sv b/examples/Benchmarks/seven_seg_2-sl1.sv new file mode 100644 index 000000000..777759413 --- /dev/null +++ b/examples/Benchmarks/seven_seg_2-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 500; + localparam CBITS = 9; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_2.sv b/examples/Benchmarks/seven_seg_2.sv index 65c8052e0..e8673444c 100644 --- a/examples/Benchmarks/seven_seg_2.sv +++ b/examples/Benchmarks/seven_seg_2.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 500, localparam CBITS = 9) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 500; + localparam CBITS = 9; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 500, localparam CBITS = 9) (input clk, input rs digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 500, localparam CBITS = 9) (input clk, input rs end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_3-p2.sv b/examples/Benchmarks/seven_seg_3-p2.sv new file mode 100644 index 000000000..9e2a73478 --- /dev/null +++ b/examples/Benchmarks/seven_seg_3-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 750; + localparam CBITS = 10; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_3-s1.sv b/examples/Benchmarks/seven_seg_3-s1.sv new file mode 100644 index 000000000..b341a1e9d --- /dev/null +++ b/examples/Benchmarks/seven_seg_3-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 750; + localparam CBITS = 10; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_3-sl1.sv b/examples/Benchmarks/seven_seg_3-sl1.sv new file mode 100644 index 000000000..aa89ba564 --- /dev/null +++ b/examples/Benchmarks/seven_seg_3-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 750; + localparam CBITS = 10; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_3.sv b/examples/Benchmarks/seven_seg_3.sv index bd3d2597e..992447dc8 100644 --- a/examples/Benchmarks/seven_seg_3.sv +++ b/examples/Benchmarks/seven_seg_3.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 750, localparam CBITS = 10) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 750; + localparam CBITS = 10; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 750, localparam CBITS = 10) (input clk, input r digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 750, localparam CBITS = 10) (input clk, input r end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_4-p2.sv b/examples/Benchmarks/seven_seg_4-p2.sv new file mode 100644 index 000000000..3fa6abac8 --- /dev/null +++ b/examples/Benchmarks/seven_seg_4-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 1000; + localparam CBITS = 10; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_4-s1.sv b/examples/Benchmarks/seven_seg_4-s1.sv new file mode 100644 index 000000000..0b75b50c5 --- /dev/null +++ b/examples/Benchmarks/seven_seg_4-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 1000; + localparam CBITS = 10; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_4-sl1.sv b/examples/Benchmarks/seven_seg_4-sl1.sv new file mode 100644 index 000000000..cfbf9ded4 --- /dev/null +++ b/examples/Benchmarks/seven_seg_4-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 1000; + localparam CBITS = 10; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_4.sv b/examples/Benchmarks/seven_seg_4.sv index 3bebb31c4..e1b685aae 100644 --- a/examples/Benchmarks/seven_seg_4.sv +++ b/examples/Benchmarks/seven_seg_4.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 1000, localparam CBITS = 10) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 1000; + localparam CBITS = 10; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 1000, localparam CBITS = 10) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 1000, localparam CBITS = 10) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_5-p2.sv b/examples/Benchmarks/seven_seg_5-p2.sv new file mode 100644 index 000000000..81b5bc7ed --- /dev/null +++ b/examples/Benchmarks/seven_seg_5-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 2500; + localparam CBITS = 12; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_5-s1.sv b/examples/Benchmarks/seven_seg_5-s1.sv new file mode 100644 index 000000000..746fb615d --- /dev/null +++ b/examples/Benchmarks/seven_seg_5-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 2500; + localparam CBITS = 12; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_5-sl1.sv b/examples/Benchmarks/seven_seg_5-sl1.sv new file mode 100644 index 000000000..c704b00d4 --- /dev/null +++ b/examples/Benchmarks/seven_seg_5-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 2500; + localparam CBITS = 12; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_5.sv b/examples/Benchmarks/seven_seg_5.sv index 3723770d4..6ba6b51c3 100644 --- a/examples/Benchmarks/seven_seg_5.sv +++ b/examples/Benchmarks/seven_seg_5.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 2500, localparam CBITS = 12) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 2500; + localparam CBITS = 12; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 2500, localparam CBITS = 12) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 2500, localparam CBITS = 12) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_6-p2.sv b/examples/Benchmarks/seven_seg_6-p2.sv new file mode 100644 index 000000000..57421ea90 --- /dev/null +++ b/examples/Benchmarks/seven_seg_6-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 5000; + localparam CBITS = 13; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_6-s1.sv b/examples/Benchmarks/seven_seg_6-s1.sv new file mode 100644 index 000000000..05a4b7c94 --- /dev/null +++ b/examples/Benchmarks/seven_seg_6-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 5000; + localparam CBITS = 13; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_6-sl1.sv b/examples/Benchmarks/seven_seg_6-sl1.sv new file mode 100644 index 000000000..01ec60119 --- /dev/null +++ b/examples/Benchmarks/seven_seg_6-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 5000; + localparam CBITS = 13; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_6.sv b/examples/Benchmarks/seven_seg_6.sv index b97be2486..cb29cd49a 100644 --- a/examples/Benchmarks/seven_seg_6.sv +++ b/examples/Benchmarks/seven_seg_6.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 5000, localparam CBITS = 13) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 5000; + localparam CBITS = 13; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 5000, localparam CBITS = 13) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 5000, localparam CBITS = 13) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_7-p2.sv b/examples/Benchmarks/seven_seg_7-p2.sv new file mode 100644 index 000000000..38866944d --- /dev/null +++ b/examples/Benchmarks/seven_seg_7-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 7500; + localparam CBITS = 13; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_7-s1.sv b/examples/Benchmarks/seven_seg_7-s1.sv new file mode 100644 index 000000000..eabb64e7f --- /dev/null +++ b/examples/Benchmarks/seven_seg_7-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 7500; + localparam CBITS = 13; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_7-sl1.sv b/examples/Benchmarks/seven_seg_7-sl1.sv new file mode 100644 index 000000000..f4eecde8a --- /dev/null +++ b/examples/Benchmarks/seven_seg_7-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 7500; + localparam CBITS = 13; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_7.sv b/examples/Benchmarks/seven_seg_7.sv index aa13d7d1b..37b441391 100644 --- a/examples/Benchmarks/seven_seg_7.sv +++ b/examples/Benchmarks/seven_seg_7.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 7500, localparam CBITS = 13) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 7500; + localparam CBITS = 13; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 7500, localparam CBITS = 13) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 7500, localparam CBITS = 13) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_8-p2.sv b/examples/Benchmarks/seven_seg_8-p2.sv new file mode 100644 index 000000000..37812f65a --- /dev/null +++ b/examples/Benchmarks/seven_seg_8-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 10000; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_8-s1.sv b/examples/Benchmarks/seven_seg_8-s1.sv new file mode 100644 index 000000000..a6e9ceb50 --- /dev/null +++ b/examples/Benchmarks/seven_seg_8-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 10000; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_8-sl1.sv b/examples/Benchmarks/seven_seg_8-sl1.sv new file mode 100644 index 000000000..51b181436 --- /dev/null +++ b/examples/Benchmarks/seven_seg_8-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 10000; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_8.sv b/examples/Benchmarks/seven_seg_8.sv index 85bb9ad50..3d5469f24 100644 --- a/examples/Benchmarks/seven_seg_8.sv +++ b/examples/Benchmarks/seven_seg_8.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 10000, localparam CBITS = 14) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 10000; + localparam CBITS = 14; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 10000, localparam CBITS = 14) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 10000, localparam CBITS = 14) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/seven_seg_9-p2.sv b/examples/Benchmarks/seven_seg_9-p2.sv new file mode 100644 index 000000000..1248dbcb8 --- /dev/null +++ b/examples/Benchmarks/seven_seg_9-p2.sv @@ -0,0 +1,34 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 12500; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + p2: assert property (@(posedge clk) s_eventually !rst implies ((s_eventually digit_select) and (s_eventually !digit_select))); + // FG !rst -> (GF ds & GF !ds) +FG !rst -> (GF ds & GF !ds) +endmodule diff --git a/examples/Benchmarks/seven_seg_9-s1.sv b/examples/Benchmarks/seven_seg_9-s1.sv new file mode 100644 index 000000000..dcb7906d3 --- /dev/null +++ b/examples/Benchmarks/seven_seg_9-s1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 12500; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + s1: assert property (@(posedge clk) (!sig and !rst and s_nexttime !sig) implies (digit_select iff s_nexttime digit_select)); + // X G ((!sig & X !sig & !rst) -> ( (!ds & X !ds) | (ds & X ds) ) ) +endmodule diff --git a/examples/Benchmarks/seven_seg_9-sl1.sv b/examples/Benchmarks/seven_seg_9-sl1.sv new file mode 100644 index 000000000..3984cb65e --- /dev/null +++ b/examples/Benchmarks/seven_seg_9-sl1.sv @@ -0,0 +1,33 @@ +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 12500; + localparam CBITS = 14; + + reg [CBITS-1:0] cnt; + reg digit_select; + + always @(posedge clk) begin + if(rst == 1) begin + cnt = 0; + digit_select = 0; + segment = 0; + end + if(cnt < freq) begin + cnt = cnt + 1; + sig = 0; + end + else begin + sig = 1; + cnt = 0; + if(digit_select == 0) begin + digit_select = 1; + segment = both7seg[13:7]; + end + else begin + digit_select = 0; + segment = both7seg[6:0]; + end + end + end + sl1: assert property (@(posedge clk) (always !rst) implies always ((digit_select iff s_nexttime digit_select) s_until s_nexttime sig)); + // G !rst -> G (((!ds & X !ds) | (ds & X ds)) U X s) +endmodule diff --git a/examples/Benchmarks/seven_seg_9.sv b/examples/Benchmarks/seven_seg_9.sv index e9f9f68a6..0e4468c71 100644 --- a/examples/Benchmarks/seven_seg_9.sv +++ b/examples/Benchmarks/seven_seg_9.sv @@ -1,4 +1,7 @@ -module SEVEN #(localparam freq = 12500, localparam CBITS = 14) (input clk, input rst, input [13:0] both7seg, output reg[6:0] segment); +module SEVEN(input clk, input rst, input [13:0] both7seg, output reg[6:0] segment, output reg sig); + localparam freq = 12500; + localparam CBITS = 14; + reg [CBITS-1:0] cnt; reg digit_select; @@ -8,9 +11,12 @@ module SEVEN #(localparam freq = 12500, localparam CBITS = 14) (input clk, input digit_select = 0; segment = 0; end - if(cnt < freq) + if(cnt < freq) begin cnt = cnt + 1; + sig = 0; + end else begin + sig = 1; cnt = 0; if(digit_select == 0) begin digit_select = 1; @@ -22,8 +28,6 @@ module SEVEN #(localparam freq = 12500, localparam CBITS = 14) (input clk, input end end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 1); - p2: assert property (@(posedge clk) s_eventually rst == 1 || digit_select == 0); - //F G (rst = FALSE) -> G F (digit_select = TRUE) - //F G (rst = FALSE) -> G F (digit_select = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> digit_select); + // FG !rst -> (GF ds) endmodule diff --git a/examples/Benchmarks/thermocouple_1-s1.sv b/examples/Benchmarks/thermocouple_1-s1.sv new file mode 100644 index 000000000..caa40e51e --- /dev/null +++ b/examples/Benchmarks/thermocouple_1-s1.sv @@ -0,0 +1,48 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 10; + localparam CBITS = 6; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_1-sl1.sv b/examples/Benchmarks/thermocouple_1-sl1.sv new file mode 100644 index 000000000..d8355023d --- /dev/null +++ b/examples/Benchmarks/thermocouple_1-sl1.sv @@ -0,0 +1,48 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 10; + localparam CBITS = 6; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_1.sv b/examples/Benchmarks/thermocouple_1.sv index e791e5e3e..59029da34 100644 --- a/examples/Benchmarks/thermocouple_1.sv +++ b/examples/Benchmarks/thermocouple_1.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 10, localparam CBITS = 5) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 10; + localparam CBITS = 6; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,7 @@ module Thermocouple #(localparam clk_freq = 10, localparam CBITS = 5) (input clk end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_10-s1.sv b/examples/Benchmarks/thermocouple_10-s1.sv new file mode 100644 index 000000000..ca0e0f33c --- /dev/null +++ b/examples/Benchmarks/thermocouple_10-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 3000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_10-sl1.sv b/examples/Benchmarks/thermocouple_10-sl1.sv new file mode 100644 index 000000000..a18eb6808 --- /dev/null +++ b/examples/Benchmarks/thermocouple_10-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 3000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_10.sv b/examples/Benchmarks/thermocouple_10.sv index cad97e7a7..d0d8e07cc 100644 --- a/examples/Benchmarks/thermocouple_10.sv +++ b/examples/Benchmarks/thermocouple_10.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 3000, localparam CBITS = 14) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 3000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 3000, localparam CBITS = 14) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_11-s1.sv b/examples/Benchmarks/thermocouple_11-s1.sv new file mode 100644 index 000000000..c04b344d5 --- /dev/null +++ b/examples/Benchmarks/thermocouple_11-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 4000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_11-sl1.sv b/examples/Benchmarks/thermocouple_11-sl1.sv new file mode 100644 index 000000000..dea8c8d62 --- /dev/null +++ b/examples/Benchmarks/thermocouple_11-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 4000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_11.sv b/examples/Benchmarks/thermocouple_11.sv index d71e5d2d1..b4a12236e 100644 --- a/examples/Benchmarks/thermocouple_11.sv +++ b/examples/Benchmarks/thermocouple_11.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 4000, localparam CBITS = 14) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 4000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 4000, localparam CBITS = 14) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_12-s1.sv b/examples/Benchmarks/thermocouple_12-s1.sv new file mode 100644 index 000000000..a8d536008 --- /dev/null +++ b/examples/Benchmarks/thermocouple_12-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 5000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_12-sl1.sv b/examples/Benchmarks/thermocouple_12-sl1.sv new file mode 100644 index 000000000..fd5986aa0 --- /dev/null +++ b/examples/Benchmarks/thermocouple_12-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 5000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_12.sv b/examples/Benchmarks/thermocouple_12.sv index c08d08430..2d9268401 100644 --- a/examples/Benchmarks/thermocouple_12.sv +++ b/examples/Benchmarks/thermocouple_12.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 5000, localparam CBITS = 14) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 5000; + localparam CBITS = 14; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 5000, localparam CBITS = 14) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_13-s1.sv b/examples/Benchmarks/thermocouple_13-s1.sv new file mode 100644 index 000000000..bdc972bdd --- /dev/null +++ b/examples/Benchmarks/thermocouple_13-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 6000; + localparam CBITS = 15; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_13-sl1.sv b/examples/Benchmarks/thermocouple_13-sl1.sv new file mode 100644 index 000000000..73da4d376 --- /dev/null +++ b/examples/Benchmarks/thermocouple_13-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 6000; + localparam CBITS = 15; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_13.sv b/examples/Benchmarks/thermocouple_13.sv index e4b3eb4ce..224a9f289 100644 --- a/examples/Benchmarks/thermocouple_13.sv +++ b/examples/Benchmarks/thermocouple_13.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 6000, localparam CBITS = 15) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 6000; + localparam CBITS = 15; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 6000, localparam CBITS = 15) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_14-s1.sv b/examples/Benchmarks/thermocouple_14-s1.sv new file mode 100644 index 000000000..fb7d6647e --- /dev/null +++ b/examples/Benchmarks/thermocouple_14-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 12000; + localparam CBITS = 16; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_14-sl1.sv b/examples/Benchmarks/thermocouple_14-sl1.sv new file mode 100644 index 000000000..13b1c9aac --- /dev/null +++ b/examples/Benchmarks/thermocouple_14-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 12000; + localparam CBITS = 16; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_14.sv b/examples/Benchmarks/thermocouple_14.sv index 6e6b061d5..411d21b06 100644 --- a/examples/Benchmarks/thermocouple_14.sv +++ b/examples/Benchmarks/thermocouple_14.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 12000, localparam CBITS = 16) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 12000; + localparam CBITS = 16; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 12000, localparam CBITS = 16) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_15-s1.sv b/examples/Benchmarks/thermocouple_15-s1.sv new file mode 100644 index 000000000..96407919f --- /dev/null +++ b/examples/Benchmarks/thermocouple_15-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 24000; + localparam CBITS = 17; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_15-sl1.sv b/examples/Benchmarks/thermocouple_15-sl1.sv new file mode 100644 index 000000000..f7e7ed2e9 --- /dev/null +++ b/examples/Benchmarks/thermocouple_15-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 24000; + localparam CBITS = 17; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_15.sv b/examples/Benchmarks/thermocouple_15.sv index bcc353125..f3b5f4a46 100644 --- a/examples/Benchmarks/thermocouple_15.sv +++ b/examples/Benchmarks/thermocouple_15.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 24000, localparam CBITS = 17) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 24000; + localparam CBITS = 17; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 24000, localparam CBITS = 17) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_16-s1.sv b/examples/Benchmarks/thermocouple_16-s1.sv new file mode 100644 index 000000000..268903e9e --- /dev/null +++ b/examples/Benchmarks/thermocouple_16-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 48000; + localparam CBITS = 18; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_16-sl1.sv b/examples/Benchmarks/thermocouple_16-sl1.sv new file mode 100644 index 000000000..48a694c61 --- /dev/null +++ b/examples/Benchmarks/thermocouple_16-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 48000; + localparam CBITS = 18; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_16.sv b/examples/Benchmarks/thermocouple_16.sv index da9a94e43..da624f387 100644 --- a/examples/Benchmarks/thermocouple_16.sv +++ b/examples/Benchmarks/thermocouple_16.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 48000, localparam CBITS = 18) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 48000; + localparam CBITS = 18; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 48000, localparam CBITS = 18) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_17-s1.sv b/examples/Benchmarks/thermocouple_17-s1.sv new file mode 100644 index 000000000..004736856 --- /dev/null +++ b/examples/Benchmarks/thermocouple_17-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 96000; + localparam CBITS = 19; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_17-sl1.sv b/examples/Benchmarks/thermocouple_17-sl1.sv new file mode 100644 index 000000000..0b2ba3a2d --- /dev/null +++ b/examples/Benchmarks/thermocouple_17-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 96000; + localparam CBITS = 19; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_17.sv b/examples/Benchmarks/thermocouple_17.sv index 4584e2beb..35c1d8cdb 100644 --- a/examples/Benchmarks/thermocouple_17.sv +++ b/examples/Benchmarks/thermocouple_17.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 96000, localparam CBITS = 19) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 96000; + localparam CBITS = 19; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 96000, localparam CBITS = 19) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_2-s1.sv b/examples/Benchmarks/thermocouple_2-s1.sv new file mode 100644 index 000000000..d5d99762d --- /dev/null +++ b/examples/Benchmarks/thermocouple_2-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 100; + localparam CBITS = 9; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_2-sl1.sv b/examples/Benchmarks/thermocouple_2-sl1.sv new file mode 100644 index 000000000..1253c7755 --- /dev/null +++ b/examples/Benchmarks/thermocouple_2-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 100; + localparam CBITS = 9; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_2.sv b/examples/Benchmarks/thermocouple_2.sv index 912ec4f8d..9a633047a 100644 --- a/examples/Benchmarks/thermocouple_2.sv +++ b/examples/Benchmarks/thermocouple_2.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 100, localparam CBITS = 9) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 100; + localparam CBITS = 9; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 100, localparam CBITS = 9) (input cl end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_3-s1.sv b/examples/Benchmarks/thermocouple_3-s1.sv new file mode 100644 index 000000000..7334a1a4c --- /dev/null +++ b/examples/Benchmarks/thermocouple_3-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 200; + localparam CBITS = 10; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_3-sl1.sv b/examples/Benchmarks/thermocouple_3-sl1.sv new file mode 100644 index 000000000..bec697339 --- /dev/null +++ b/examples/Benchmarks/thermocouple_3-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 200; + localparam CBITS = 10; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_3.sv b/examples/Benchmarks/thermocouple_3.sv index 1b2997d44..87a210262 100644 --- a/examples/Benchmarks/thermocouple_3.sv +++ b/examples/Benchmarks/thermocouple_3.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 200, localparam CBITS = 10) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 200; + localparam CBITS = 10; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 200, localparam CBITS = 10) (input c end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_4-s1.sv b/examples/Benchmarks/thermocouple_4-s1.sv new file mode 100644 index 000000000..e5a6d3ae0 --- /dev/null +++ b/examples/Benchmarks/thermocouple_4-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 300; + localparam CBITS = 10; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_4-sl1.sv b/examples/Benchmarks/thermocouple_4-sl1.sv new file mode 100644 index 000000000..20528d6ca --- /dev/null +++ b/examples/Benchmarks/thermocouple_4-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 300; + localparam CBITS = 10; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_4.sv b/examples/Benchmarks/thermocouple_4.sv index adf6341d0..5c73a20fb 100644 --- a/examples/Benchmarks/thermocouple_4.sv +++ b/examples/Benchmarks/thermocouple_4.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 300, localparam CBITS = 10) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 300; + localparam CBITS = 10; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 300, localparam CBITS = 10) (input c end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_5-s1.sv b/examples/Benchmarks/thermocouple_5-s1.sv new file mode 100644 index 000000000..6dfef9986 --- /dev/null +++ b/examples/Benchmarks/thermocouple_5-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 400; + localparam CBITS = 11; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_5-sl1.sv b/examples/Benchmarks/thermocouple_5-sl1.sv new file mode 100644 index 000000000..bf9964cda --- /dev/null +++ b/examples/Benchmarks/thermocouple_5-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 400; + localparam CBITS = 11; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_5.sv b/examples/Benchmarks/thermocouple_5.sv index ffb88801e..b104b538e 100644 --- a/examples/Benchmarks/thermocouple_5.sv +++ b/examples/Benchmarks/thermocouple_5.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 400, localparam CBITS = 11) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 400; + localparam CBITS = 11; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 400, localparam CBITS = 11) (input c end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_6-s1.sv b/examples/Benchmarks/thermocouple_6-s1.sv new file mode 100644 index 000000000..f74a9938a --- /dev/null +++ b/examples/Benchmarks/thermocouple_6-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 600; + localparam CBITS = 11; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_6-sl1.sv b/examples/Benchmarks/thermocouple_6-sl1.sv new file mode 100644 index 000000000..4835dbd31 --- /dev/null +++ b/examples/Benchmarks/thermocouple_6-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 600; + localparam CBITS = 11; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_6.sv b/examples/Benchmarks/thermocouple_6.sv index c83a38c27..367641ccf 100644 --- a/examples/Benchmarks/thermocouple_6.sv +++ b/examples/Benchmarks/thermocouple_6.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 600, localparam CBITS = 11) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 600; + localparam CBITS = 11; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 600, localparam CBITS = 11) (input c end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_7-s1.sv b/examples/Benchmarks/thermocouple_7-s1.sv new file mode 100644 index 000000000..c04873195 --- /dev/null +++ b/examples/Benchmarks/thermocouple_7-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 800; + localparam CBITS = 12; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_7-sl1.sv b/examples/Benchmarks/thermocouple_7-sl1.sv new file mode 100644 index 000000000..c00b1498d --- /dev/null +++ b/examples/Benchmarks/thermocouple_7-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 800; + localparam CBITS = 12; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_7.sv b/examples/Benchmarks/thermocouple_7.sv index 2e554d11f..4e370acc9 100644 --- a/examples/Benchmarks/thermocouple_7.sv +++ b/examples/Benchmarks/thermocouple_7.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 800, localparam CBITS = 12) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 800; + localparam CBITS = 12; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 800, localparam CBITS = 12) (input c end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_8-s1.sv b/examples/Benchmarks/thermocouple_8-s1.sv new file mode 100644 index 000000000..439f76d68 --- /dev/null +++ b/examples/Benchmarks/thermocouple_8-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 1000; + localparam CBITS = 12; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_8-sl1.sv b/examples/Benchmarks/thermocouple_8-sl1.sv new file mode 100644 index 000000000..c8f7e9b55 --- /dev/null +++ b/examples/Benchmarks/thermocouple_8-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 1000; + localparam CBITS = 12; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_8.sv b/examples/Benchmarks/thermocouple_8.sv index 13906a161..01f19957a 100644 --- a/examples/Benchmarks/thermocouple_8.sv +++ b/examples/Benchmarks/thermocouple_8.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 1000, localparam CBITS = 12) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 1000; + localparam CBITS = 12; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 1000, localparam CBITS = 12) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/thermocouple_9-s1.sv b/examples/Benchmarks/thermocouple_9-s1.sv new file mode 100644 index 000000000..da6611c9a --- /dev/null +++ b/examples/Benchmarks/thermocouple_9-s1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 2000; + localparam CBITS = 13; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + s1: assert property (@(posedge clk) spi_not_busy && (state == 1) && !rst |=> (state == 1)); + // X G ((spi_not_busy & state1 & !rst) -> X state1) +endmodule diff --git a/examples/Benchmarks/thermocouple_9-sl1.sv b/examples/Benchmarks/thermocouple_9-sl1.sv new file mode 100644 index 000000000..fd8aa9212 --- /dev/null +++ b/examples/Benchmarks/thermocouple_9-sl1.sv @@ -0,0 +1,47 @@ +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 2000; + localparam CBITS = 13; // 2^CBITS > clk_freq*3 + reg spi_ena; + reg [1:0] state; + reg [CBITS-1:0] cnt; + always @(posedge clk) + if(rst == 1) begin + spi_ena = 0; + tc_temp_data = 0; + junction_temp_data = 0; + fault_bits = 0; + state = 0; + cnt = 0; + end + else if(state == 0) begin + if(cnt < clk_freq * 3) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else if(state == 1) begin + if(spi_not_busy == 1) + spi_ena = 1; + else begin + spi_ena = 0; + state = 2; + end + end + else if(state == 2) begin + tc_temp_data = spi_rx_data [31:18]; + junction_temp_data = spi_rx_data [15:4]; + fault_bits = {spi_rx_data[16], spi_rx_data[2:0]}; + if(cnt < clk_freq * 1) + cnt = cnt + 1; + else begin + cnt = 0; + state = 1; + end + end + else + state = 1; + sl1: assert property (@(posedge clk) (always !rst) implies always (state==2 implies (state==2 s_until state==1))); + // ((G !rst -> G (s2 -> s2 U s1))) +endmodule diff --git a/examples/Benchmarks/thermocouple_9.sv b/examples/Benchmarks/thermocouple_9.sv index 93cdea285..de5ff7fc6 100644 --- a/examples/Benchmarks/thermocouple_9.sv +++ b/examples/Benchmarks/thermocouple_9.sv @@ -1,8 +1,10 @@ -module Thermocouple #(localparam clk_freq = 2000, localparam CBITS = 13) (input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); +module Thermocouple(input clk, input rst, input spi_not_busy, input [31:0] spi_rx_data, output reg [13:0] tc_temp_data, output reg [11:0] junction_temp_data, output reg [3:0] fault_bits); + localparam clk_freq = 2000; + localparam CBITS = 13; // 2^CBITS > clk_freq*3 reg spi_ena; reg [1:0] state; reg [CBITS-1:0] cnt; - always @(posedge clk) begin + always @(posedge clk) if(rst == 1) begin spi_ena = 0; tc_temp_data = 0; @@ -40,7 +42,6 @@ module Thermocouple #(localparam clk_freq = 2000, localparam CBITS = 13) (input end else state = 1; - end - p1: assert property (@(posedge clk) s_eventually rst == 1 || state == 1); - //F G (rst = F) -> G F (state[1] = F & state[0] = T) + p1: assert property (@(posedge clk) s_eventually !rst -> state); + // FG !rst -> (GF state = 1) endmodule diff --git a/examples/Benchmarks/uart_transmit_1-s1.sv b/examples/Benchmarks/uart_transmit_1-s1.sv new file mode 100644 index 000000000..e82a94c52 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_1-s1.sv @@ -0,0 +1,35 @@ +module UART_T #(localparam d_width = 4, c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + assign tx_busy = tx_state; + always @(posedge clk) begin + + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_cnt = 0; + tx_state = 1; + end + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_1-sl1.sv b/examples/Benchmarks/uart_transmit_1-sl1.sv new file mode 100644 index 000000000..84b7454d6 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_1-sl1.sv @@ -0,0 +1,35 @@ +module UART_T #(localparam d_width = 4, c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + assign tx_busy = tx_state; + always @(posedge clk) begin + + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_cnt = 0; + tx_state = 1; + end + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_1.sv b/examples/Benchmarks/uart_transmit_1.sv index 08704d7b5..9faab55a1 100644 --- a/examples/Benchmarks/uart_transmit_1.sv +++ b/examples/Benchmarks/uart_transmit_1.sv @@ -1,28 +1,25 @@ -module UART_T #(localparam d_width = 4, localparam c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 4, c_width = 3) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; - + assign tx_busy = tx_state; always @(posedge clk) begin + if(rst == 1) begin tx_cnt = 0; tx = 1; - tx_busy = 0; tx_state = 0; end if(tx_state == 0) begin if(tx_ena == 1) begin tx_buffer = {tx_data, 2'b01}; - tx_busy = 1; tx_cnt = 0; tx_state = 1; end - else - tx_busy = 0; end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end @@ -33,6 +30,6 @@ module UART_T #(localparam d_width = 4, localparam c_width = 3) (input clk, inpu end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_10-s1.sv b/examples/Benchmarks/uart_transmit_10-s1.sv new file mode 100644 index 000000000..34dcd361b --- /dev/null +++ b/examples/Benchmarks/uart_transmit_10-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 15, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_10-sl1.sv b/examples/Benchmarks/uart_transmit_10-sl1.sv new file mode 100644 index 000000000..27ddf3dce --- /dev/null +++ b/examples/Benchmarks/uart_transmit_10-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 15, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_10.sv b/examples/Benchmarks/uart_transmit_10.sv index b93714c3f..9752cef9d 100644 --- a/examples/Benchmarks/uart_transmit_10.sv +++ b/examples/Benchmarks/uart_transmit_10.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 15, localparam c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 15, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 15, localparam c_width = 5) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_11-s1.sv b/examples/Benchmarks/uart_transmit_11-s1.sv new file mode 100644 index 000000000..beb5e0890 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_11-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 16, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_11-sl1.sv b/examples/Benchmarks/uart_transmit_11-sl1.sv new file mode 100644 index 000000000..9adb397bc --- /dev/null +++ b/examples/Benchmarks/uart_transmit_11-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 16, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_11.sv b/examples/Benchmarks/uart_transmit_11.sv index 4f2d3e29f..9d784c3ec 100644 --- a/examples/Benchmarks/uart_transmit_11.sv +++ b/examples/Benchmarks/uart_transmit_11.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 16, localparam c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 16, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 16, localparam c_width = 5) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_12.sv b/examples/Benchmarks/uart_transmit_12.sv index 1071fc197..c9e053b03 100644 --- a/examples/Benchmarks/uart_transmit_12.sv +++ b/examples/Benchmarks/uart_transmit_12.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 28, localparam c_width = 6) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 28, c_width = 6) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -33,6 +34,6 @@ module UART_T #(localparam d_width = 28, localparam c_width = 6) (input clk, inp end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); + p1: assert property (@(posedge clk) (always s_eventually rst == 1) or (always s_eventually tx_state == 0)) ; // F G (rst = FALSE) -> G F (tx_state = FALSE) endmodule diff --git a/examples/Benchmarks/uart_transmit_2-s1.sv b/examples/Benchmarks/uart_transmit_2-s1.sv new file mode 100644 index 000000000..736c92543 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_2-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 6, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_2-sl1.sv b/examples/Benchmarks/uart_transmit_2-sl1.sv new file mode 100644 index 000000000..a9a7ed6bb --- /dev/null +++ b/examples/Benchmarks/uart_transmit_2-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 6, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_2.sv b/examples/Benchmarks/uart_transmit_2.sv index c3912d717..77d0583d0 100644 --- a/examples/Benchmarks/uart_transmit_2.sv +++ b/examples/Benchmarks/uart_transmit_2.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 6, localparam c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 6, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 6, localparam c_width = 4) (input clk, inpu end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_3-s1.sv b/examples/Benchmarks/uart_transmit_3-s1.sv new file mode 100644 index 000000000..8bfabc6f9 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_3-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 8, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_3-sl1.sv b/examples/Benchmarks/uart_transmit_3-sl1.sv new file mode 100644 index 000000000..cd749b721 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_3-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 8, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_3.sv b/examples/Benchmarks/uart_transmit_3.sv index 47a1e374c..175bce575 100644 --- a/examples/Benchmarks/uart_transmit_3.sv +++ b/examples/Benchmarks/uart_transmit_3.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 8, localparam c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 8, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 8, localparam c_width = 4) (input clk, inpu end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_4-s1.sv b/examples/Benchmarks/uart_transmit_4-s1.sv new file mode 100644 index 000000000..7d72efed6 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_4-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 9, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_4-sl1.sv b/examples/Benchmarks/uart_transmit_4-sl1.sv new file mode 100644 index 000000000..634e0c499 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_4-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 9, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_4.sv b/examples/Benchmarks/uart_transmit_4.sv index 5f9f04017..43d3d4a92 100644 --- a/examples/Benchmarks/uart_transmit_4.sv +++ b/examples/Benchmarks/uart_transmit_4.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 9, localparam c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 9, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 9, localparam c_width = 4) (input clk, inpu end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_5-s1.sv b/examples/Benchmarks/uart_transmit_5-s1.sv new file mode 100644 index 000000000..b378caef0 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_5-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 10, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_5-sl1.sv b/examples/Benchmarks/uart_transmit_5-sl1.sv new file mode 100644 index 000000000..cf38f93d8 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_5-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 10, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_5.sv b/examples/Benchmarks/uart_transmit_5.sv index 4d539db19..e2a29e171 100644 --- a/examples/Benchmarks/uart_transmit_5.sv +++ b/examples/Benchmarks/uart_transmit_5.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 10, localparam c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 10, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 10, localparam c_width = 4) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_6-s1.sv b/examples/Benchmarks/uart_transmit_6-s1.sv new file mode 100644 index 000000000..6ce1c93a3 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_6-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 11, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_6-sl1.sv b/examples/Benchmarks/uart_transmit_6-sl1.sv new file mode 100644 index 000000000..589ff57a5 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_6-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 11, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_6.sv b/examples/Benchmarks/uart_transmit_6.sv index cd6060a08..6aa0a4115 100644 --- a/examples/Benchmarks/uart_transmit_6.sv +++ b/examples/Benchmarks/uart_transmit_6.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 11, localparam c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 11, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 11, localparam c_width = 4) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_7-s1.sv b/examples/Benchmarks/uart_transmit_7-s1.sv new file mode 100644 index 000000000..1a83af625 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_7-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 12, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_7-sl1.sv b/examples/Benchmarks/uart_transmit_7-sl1.sv new file mode 100644 index 000000000..f0c1904f3 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_7-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 12, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_7.sv b/examples/Benchmarks/uart_transmit_7.sv index c3081248b..18826ab29 100644 --- a/examples/Benchmarks/uart_transmit_7.sv +++ b/examples/Benchmarks/uart_transmit_7.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 12, localparam c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 12, c_width = 4) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 12, localparam c_width = 4) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_8-s1.sv b/examples/Benchmarks/uart_transmit_8-s1.sv new file mode 100644 index 000000000..39e8e245a --- /dev/null +++ b/examples/Benchmarks/uart_transmit_8-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 13, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_8-sl1.sv b/examples/Benchmarks/uart_transmit_8-sl1.sv new file mode 100644 index 000000000..65b0fceb2 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_8-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 13, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_8.sv b/examples/Benchmarks/uart_transmit_8.sv index e936e293d..ff026af7a 100644 --- a/examples/Benchmarks/uart_transmit_8.sv +++ b/examples/Benchmarks/uart_transmit_8.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 13, localparam c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 13, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 13, localparam c_width = 5) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/uart_transmit_9-s1.sv b/examples/Benchmarks/uart_transmit_9-s1.sv new file mode 100644 index 000000000..ce8885536 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_9-s1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 14, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + s1: assert property (@(posedge clk) ##1 (tx_state <-> tx_busy)); + // X G ((tx_state -> tx_busy) & (!tx_state -> !tx_busy)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_9-sl1.sv b/examples/Benchmarks/uart_transmit_9-sl1.sv new file mode 100644 index 000000000..5e1972158 --- /dev/null +++ b/examples/Benchmarks/uart_transmit_9-sl1.sv @@ -0,0 +1,40 @@ +module UART_T #(localparam d_width = 14, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 + reg [c_width-1:0] tx_cnt; + reg tx_state; + reg [d_width+1:0] tx_buffer; + + always @(posedge clk) begin + if(rst == 1) begin + tx_cnt = 0; + tx = 1; + tx_busy = 0; + tx_state = 0; + end + if(tx_state == 0) begin + if(tx_ena == 1) begin + tx_buffer = {tx_data, 2'b01}; + tx_busy = 1; + tx_cnt = 0; + tx_state = 1; + end + else + tx_busy = 0; + end + else if(tx_state == 1) begin + if(tx_cnt < d_width+3) begin + tx_busy = 1; + tx_cnt = tx_cnt + 1; + tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; + end + else begin + tx_cnt = 0; + tx_state = 0; + tx_busy = 0; + end + end + tx = tx_buffer[0]; + end + sl1: assert property (@(posedge clk) (always !rst) implies always (tx_busy implies (tx_busy s_until !tx_state))); + // G !rst -> G (busy -> (busy U wait)) +endmodule diff --git a/examples/Benchmarks/uart_transmit_9.sv b/examples/Benchmarks/uart_transmit_9.sv index 683fed1cf..c5e048f6b 100644 --- a/examples/Benchmarks/uart_transmit_9.sv +++ b/examples/Benchmarks/uart_transmit_9.sv @@ -1,4 +1,5 @@ -module UART_T #(localparam d_width = 14, localparam c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); +module UART_T #(localparam d_width = 14, c_width = 5) (input clk, input rst, input tx_ena, input [d_width - 1: 0] tx_data, output reg tx, output reg tx_busy); + //2^c_width > d_width+3 reg [c_width-1:0] tx_cnt; reg tx_state; reg [d_width+1:0] tx_buffer; @@ -22,17 +23,18 @@ module UART_T #(localparam d_width = 14, localparam c_width = 5) (input clk, inp end else if(tx_state == 1) begin if(tx_cnt < d_width+3) begin - tx_state = 1; + tx_busy = 1; tx_cnt = tx_cnt + 1; tx_buffer = {1'b1, tx_buffer[d_width+1:1]}; end else begin tx_cnt = 0; tx_state = 0; + tx_busy = 0; end end tx = tx_buffer[0]; end - p1: assert property (@(posedge clk) s_eventually rst == 1 || tx_state == 0); - // F G (rst = FALSE) -> G F (tx_state = FALSE) + p1: assert property (@(posedge clk) s_eventually !rst -> !tx_state); + // FG !rst -> GF tx_state == 0 endmodule diff --git a/examples/Benchmarks/vga_1-s1.sv b/examples/Benchmarks/vga_1-s1.sv new file mode 100644 index 000000000..1bf2f4687 --- /dev/null +++ b/examples/Benchmarks/vga_1-s1.sv @@ -0,0 +1,68 @@ +module VGA #(localparam size = 1, h_bits =7, v_bits = 5)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_1-s2.sv b/examples/Benchmarks/vga_1-s2.sv new file mode 100644 index 000000000..4f28fa470 --- /dev/null +++ b/examples/Benchmarks/vga_1-s2.sv @@ -0,0 +1,68 @@ +module VGA #(localparam size = 1, h_bits =7, v_bits = 5)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_1-sl1.sv b/examples/Benchmarks/vga_1-sl1.sv new file mode 100644 index 000000000..39d38ff15 --- /dev/null +++ b/examples/Benchmarks/vga_1-sl1.sv @@ -0,0 +1,68 @@ +module VGA #(localparam size = 1, h_bits =7, v_bits = 5)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_1.sv b/examples/Benchmarks/vga_1.sv index 1d82170ea..8a5c9c0e4 100644 --- a/examples/Benchmarks/vga_1.sv +++ b/examples/Benchmarks/vga_1.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 1, localparam h_bits = 7, localparam v_bits = 5) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 1, h_bits =7, v_bits = 5)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,7 +60,9 @@ module VGA #(localparam size = 1, localparam h_bits = 7, localparam v_bits = 5) disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena -endmodule + + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena +endmodule diff --git a/examples/Benchmarks/vga_10-s1.sv b/examples/Benchmarks/vga_10-s1.sv new file mode 100644 index 000000000..dcce3b6e9 --- /dev/null +++ b/examples/Benchmarks/vga_10-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 16, h_bits =11, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_10-s2.sv b/examples/Benchmarks/vga_10-s2.sv new file mode 100644 index 000000000..1a9beea9c --- /dev/null +++ b/examples/Benchmarks/vga_10-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 16, h_bits =11, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_10-sl1.sv b/examples/Benchmarks/vga_10-sl1.sv new file mode 100644 index 000000000..0453458bb --- /dev/null +++ b/examples/Benchmarks/vga_10-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 16, h_bits =11, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_10.sv b/examples/Benchmarks/vga_10.sv new file mode 100644 index 000000000..acef08c98 --- /dev/null +++ b/examples/Benchmarks/vga_10.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 16, h_bits =11, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena +endmodule diff --git a/examples/Benchmarks/vga_2-s1.sv b/examples/Benchmarks/vga_2-s1.sv new file mode 100644 index 000000000..7aee5504a --- /dev/null +++ b/examples/Benchmarks/vga_2-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 2, h_bits =8, v_bits = 6)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_2-s2.sv b/examples/Benchmarks/vga_2-s2.sv new file mode 100644 index 000000000..b8ec3f647 --- /dev/null +++ b/examples/Benchmarks/vga_2-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 2, h_bits =8, v_bits = 6)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_2-sl1.sv b/examples/Benchmarks/vga_2-sl1.sv new file mode 100644 index 000000000..f413adb07 --- /dev/null +++ b/examples/Benchmarks/vga_2-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 2, h_bits =8, v_bits = 6)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_2.sv b/examples/Benchmarks/vga_2.sv index 06c476d4f..fd03433a5 100644 --- a/examples/Benchmarks/vga_2.sv +++ b/examples/Benchmarks/vga_2.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 2, localparam h_bits = 8, localparam v_bits = 6) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 2, h_bits =8, v_bits = 6)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,7 +60,7 @@ module VGA #(localparam size = 2, localparam h_bits = 8, localparam v_bits = 6) disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena -endmodule + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena +endmodule diff --git a/examples/Benchmarks/vga_3-s1.sv b/examples/Benchmarks/vga_3-s1.sv new file mode 100644 index 000000000..7ad1dd8fe --- /dev/null +++ b/examples/Benchmarks/vga_3-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 3, h_bits =8, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_3-s2.sv b/examples/Benchmarks/vga_3-s2.sv new file mode 100644 index 000000000..d5b181e55 --- /dev/null +++ b/examples/Benchmarks/vga_3-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 3, h_bits =8, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_3-sl1.sv b/examples/Benchmarks/vga_3-sl1.sv new file mode 100644 index 000000000..c8a1d9bee --- /dev/null +++ b/examples/Benchmarks/vga_3-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 3, h_bits =8, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_3.sv b/examples/Benchmarks/vga_3.sv index 54fb46eaf..0379b8de4 100644 --- a/examples/Benchmarks/vga_3.sv +++ b/examples/Benchmarks/vga_3.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 3, localparam h_bits = 8, localparam v_bits = 7) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 3, h_bits =8, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,7 +60,7 @@ module VGA #(localparam size = 3, localparam h_bits = 8, localparam v_bits = 7) disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena -endmodule + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena +endmodule diff --git a/examples/Benchmarks/vga_4-s1.sv b/examples/Benchmarks/vga_4-s1.sv new file mode 100644 index 000000000..36dabb1ae --- /dev/null +++ b/examples/Benchmarks/vga_4-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 4, h_bits =9, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_4-s2.sv b/examples/Benchmarks/vga_4-s2.sv new file mode 100644 index 000000000..885821838 --- /dev/null +++ b/examples/Benchmarks/vga_4-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 4, h_bits =9, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_4-sl1.sv b/examples/Benchmarks/vga_4-sl1.sv new file mode 100644 index 000000000..a0b73b842 --- /dev/null +++ b/examples/Benchmarks/vga_4-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 4, h_bits =9, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_4.sv b/examples/Benchmarks/vga_4.sv index 6f1f83afa..c9f4e2820 100644 --- a/examples/Benchmarks/vga_4.sv +++ b/examples/Benchmarks/vga_4.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 4, localparam h_bits = 9, localparam v_bits = 7) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 4, h_bits =9, v_bits = 7)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,6 +60,7 @@ module VGA #(localparam size = 4, localparam h_bits = 9, localparam v_bits = 7) disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena endmodule diff --git a/examples/Benchmarks/vga_5-s1.sv b/examples/Benchmarks/vga_5-s1.sv new file mode 100644 index 000000000..684aadd48 --- /dev/null +++ b/examples/Benchmarks/vga_5-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 5, h_bits =9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_5-s2.sv b/examples/Benchmarks/vga_5-s2.sv new file mode 100644 index 000000000..ac15133f1 --- /dev/null +++ b/examples/Benchmarks/vga_5-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 5, h_bits =9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_5-sl1.sv b/examples/Benchmarks/vga_5-sl1.sv new file mode 100644 index 000000000..b0fbf0250 --- /dev/null +++ b/examples/Benchmarks/vga_5-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 5, h_bits =9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_5.sv b/examples/Benchmarks/vga_5.sv index bae1cd199..6299d860a 100644 --- a/examples/Benchmarks/vga_5.sv +++ b/examples/Benchmarks/vga_5.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 5, localparam h_bits = 9, localparam v_bits = 8) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 5, h_bits =9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,6 +60,7 @@ module VGA #(localparam size = 5, localparam h_bits = 9, localparam v_bits = 8) disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena endmodule diff --git a/examples/Benchmarks/vga_6-s1.sv b/examples/Benchmarks/vga_6-s1.sv new file mode 100644 index 000000000..c7cfc53ba --- /dev/null +++ b/examples/Benchmarks/vga_6-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 6, h_bits = 9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_6-s2.sv b/examples/Benchmarks/vga_6-s2.sv new file mode 100644 index 000000000..0fd04d7e6 --- /dev/null +++ b/examples/Benchmarks/vga_6-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 6, h_bits = 9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_6-sl1.sv b/examples/Benchmarks/vga_6-sl1.sv new file mode 100644 index 000000000..14ecb9e0a --- /dev/null +++ b/examples/Benchmarks/vga_6-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 6, h_bits = 9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_6.sv b/examples/Benchmarks/vga_6.sv index d6eff87ff..b795a8538 100644 --- a/examples/Benchmarks/vga_6.sv +++ b/examples/Benchmarks/vga_6.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 6, localparam h_bits = 9, localparam v_bits = 8) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 6, h_bits = 9, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,6 +60,7 @@ module VGA #(localparam size = 6, localparam h_bits = 9, localparam v_bits = 8) disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena endmodule diff --git a/examples/Benchmarks/vga_7-s1.sv b/examples/Benchmarks/vga_7-s1.sv new file mode 100644 index 000000000..9819fbc7a --- /dev/null +++ b/examples/Benchmarks/vga_7-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 8, h_bits = 10, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_7-s2.sv b/examples/Benchmarks/vga_7-s2.sv new file mode 100644 index 000000000..86de29198 --- /dev/null +++ b/examples/Benchmarks/vga_7-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 8, h_bits = 10, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_7-sl1.sv b/examples/Benchmarks/vga_7-sl1.sv new file mode 100644 index 000000000..414106234 --- /dev/null +++ b/examples/Benchmarks/vga_7-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 8, h_bits = 10, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_7.sv b/examples/Benchmarks/vga_7.sv index ed481a0b8..04cfdaceb 100644 --- a/examples/Benchmarks/vga_7.sv +++ b/examples/Benchmarks/vga_7.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 8, localparam h_bits = 10, localparam v_bits = 8) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 8, h_bits = 10, v_bits = 8)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,6 +60,7 @@ module VGA #(localparam size = 8, localparam h_bits = 10, localparam v_bits = 8 disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena endmodule diff --git a/examples/Benchmarks/vga_8-s1.sv b/examples/Benchmarks/vga_8-s1.sv new file mode 100644 index 000000000..a88ba61d2 --- /dev/null +++ b/examples/Benchmarks/vga_8-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 10, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_8-s2.sv b/examples/Benchmarks/vga_8-s2.sv new file mode 100644 index 000000000..52d1c20d3 --- /dev/null +++ b/examples/Benchmarks/vga_8-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 10, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_8-sl1.sv b/examples/Benchmarks/vga_8-sl1.sv new file mode 100644 index 000000000..0a944edd1 --- /dev/null +++ b/examples/Benchmarks/vga_8-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 10, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_8.sv b/examples/Benchmarks/vga_8.sv index b16cb5cde..282c39caf 100644 --- a/examples/Benchmarks/vga_8.sv +++ b/examples/Benchmarks/vga_8.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 10, localparam h_bits = 10, localparam v_bits = 9) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 10, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,6 +60,7 @@ module VGA #(localparam size = 10, localparam h_bits = 10, localparam v_bits = disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena + + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena endmodule diff --git a/examples/Benchmarks/vga_9-s1.sv b/examples/Benchmarks/vga_9-s1.sv new file mode 100644 index 000000000..3e941936f --- /dev/null +++ b/examples/Benchmarks/vga_9-s1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 12, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s1: assert property (@(posedge clk) (##1 disp_ena & !rst |-> (h_sync iff s_nexttime !h_sync) )); + // X G ((disp_ena & !rst) -> ((h_sync <-> X !h_sync) | (!h_sync <-> X h_sync))) +endmodule diff --git a/examples/Benchmarks/vga_9-s2.sv b/examples/Benchmarks/vga_9-s2.sv new file mode 100644 index 000000000..c3e3399b6 --- /dev/null +++ b/examples/Benchmarks/vga_9-s2.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 12, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + s2: assert property (@(posedge clk) s_nexttime (disp_ena && !rst |-> (v_sync iff s_nexttime !v_sync))); + // X G ((disp_ena & !rst) -> ((v_sync <-> X !v_sync) | (!v_sync <-> X v_sync))) +endmodule diff --git a/examples/Benchmarks/vga_9-sl1.sv b/examples/Benchmarks/vga_9-sl1.sv new file mode 100644 index 000000000..57c8a48b0 --- /dev/null +++ b/examples/Benchmarks/vga_9-sl1.sv @@ -0,0 +1,66 @@ +module VGA #(localparam size = 12, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); + localparam h_pixels = 50*size; + localparam h_pulse = 5*size; + localparam h_bp = 8*size; + localparam h_fp = 3*size; + localparam h_pol = 0; + + localparam v_pixels = 25*size; + localparam v_pulse = size; + localparam v_bp = 1*size; + localparam v_fp = size; + localparam v_pol = 1; + + localparam h_period = h_pulse + h_bp + h_pixels + h_fp; + localparam v_period = v_pulse + v_bp + v_pixels + v_fp; + + reg [h_bits-1:0] h_cnt; + reg [v_bits-1:0] v_cnt; + reg h_sync; + reg v_sync; + always @(posedge clk) begin + if(rst == 1) begin + h_cnt = 0; + v_cnt = 0; + h_sync = ~h_sync; + v_sync = ~v_sync; + disp_ena = 0; + col = 0; + row = 0; + end + else begin + if(h_cnt < h_period - 1) + h_cnt = h_cnt + 1; + else begin + h_cnt = 0; + if(v_cnt < v_period - 1) + v_cnt = v_cnt + 1; + else + v_cnt = 0; + end + if((h_cnt < (h_pixels + h_fp)) | (h_cnt >= (h_pixels + h_fp + h_pulse))) + h_sync = ~h_sync; + else + h_sync = h_pol; + + if((v_cnt < (v_pixels + v_fp)) | (v_cnt >= (v_pixels + v_fp + v_pulse))) + v_sync = ~v_sync; + else + v_sync = v_pol; + + if(h_cnt < h_pixels) + col = h_cnt; + + if(v_cnt < v_pixels) + row = v_cnt; + + if(h_cnt < h_pixels & v_cnt < v_pixels) + disp_ena = 1; + else + disp_ena = 0; + end + end + + sl1: assert property (@(posedge clk) v_cnt==0 implies (v_cnt==0 s_until h_cnt==0)); + // G (Vcnt0 -> (Vcnt0 U Hcnt0)))) +endmodule diff --git a/examples/Benchmarks/vga_9.sv b/examples/Benchmarks/vga_9.sv index 91361e30e..d68bfff91 100644 --- a/examples/Benchmarks/vga_9.sv +++ b/examples/Benchmarks/vga_9.sv @@ -1,5 +1,4 @@ -module VGA #(localparam size = 16, localparam h_bits = 11, localparam v_bits = 9) (input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); - +module VGA #(localparam size = 12, h_bits = 10, v_bits = 9)(input clk, input rst, output reg disp_ena, output reg n_blank, output reg n_sync, output reg [h_bits-1:0] col, output reg [v_bits-1:0] row); localparam h_pixels = 50*size; localparam h_pulse = 5*size; localparam h_bp = 8*size; @@ -61,7 +60,7 @@ module VGA #(localparam size = 16, localparam h_bits = 11, localparam v_bits = disp_ena = 0; end end - p1: assert property (@(posedge clk) s_eventually rst == 1 || disp_ena == 1); - // F G !rst -> G F disp_ena -endmodule + p1: assert property (@(posedge clk) s_eventually !rst -> disp_ena); + // F G ! rst-> G F disp_ena +endmodule