diff --git a/components/arduino_tinyusb/Kconfig.projbuild b/components/arduino_tinyusb/Kconfig.projbuild index 65d9c37be..f0a1b4dc6 100755 --- a/components/arduino_tinyusb/Kconfig.projbuild +++ b/components/arduino_tinyusb/Kconfig.projbuild @@ -42,6 +42,14 @@ menu "Arduino TinyUSB" help CDC FIFO size of TX + config TINYUSB_CDC_MAX_PORTS + int "Maximum enabled CDC ports" + range 1 2 + default 1 + depends on TINYUSB_CDC_ENABLED + help + Maximum enabled CDC ports + endmenu menu "Mass Storage (MSC) driver" diff --git a/components/arduino_tinyusb/include/tusb_config.h b/components/arduino_tinyusb/include/tusb_config.h index 458c78cf1..7802bea8f 100755 --- a/components/arduino_tinyusb/include/tusb_config.h +++ b/components/arduino_tinyusb/include/tusb_config.h @@ -115,7 +115,11 @@ extern "C" { #define CFG_TUD_ENDOINT0_SIZE 64 // Enabled Drivers -#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_ENABLED +#ifdef CONFIG_TINYUSB_CDC_MAX_PORTS +#define CFG_TUD_CDC CONFIG_TINYUSB_CDC_MAX_PORTS +#else +#define CFG_TUD_CDC 0 +#endif #define CFG_TUD_MSC CONFIG_TINYUSB_MSC_ENABLED #define CFG_TUD_HID CONFIG_TINYUSB_HID_ENABLED #define CFG_TUD_MIDI CONFIG_TINYUSB_MIDI_ENABLED diff --git a/components/arduino_tinyusb/patches/dcd_dwc2.patch b/components/arduino_tinyusb/patches/dcd_dwc2.patch index 11c1c05c0..2521a38e5 100755 --- a/components/arduino_tinyusb/patches/dcd_dwc2.patch +++ b/components/arduino_tinyusb/patches/dcd_dwc2.patch @@ -19,11 +19,11 @@ dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); @@ -266,7 +277,18 @@ - depctl.bm.set_data0_iso_even = 1; + depctl.set_data0_iso_even = 1; } if (dir == TUSB_DIR_IN) { -- depctl.bm.tx_fifo_num = epnum; -+ //depctl.bm.tx_fifo_num = epnum; +- depctl.tx_fifo_num = epnum; ++ //depctl.tx_fifo_num = epnum; + uint8_t fifo_num = epnum; +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + // Special Case for EP5, which is used by CDC but not actually called by the driver @@ -34,7 +34,7 @@ + fifo_num = get_free_fifo(); + } +#endif -+ depctl.bm.tx_fifo_num = fifo_num; ++ depctl.tx_fifo_num = fifo_num; } dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; @@ -56,9 +56,9 @@ +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + _allocated_fifos = 1; +#endif + + usbd_spin_lock(true); handle_bus_reset(rhport); - } - @@ -1008,7 +1037,11 @@ if (gintsts & GINTSTS_USBSUSP) { diff --git a/components/arduino_tinyusb/src/dcd_dwc2.c b/components/arduino_tinyusb/src/dcd_dwc2.c index d6796641a..b6c3b1b22 100644 --- a/components/arduino_tinyusb/src/dcd_dwc2.c +++ b/components/arduino_tinyusb/src/dcd_dwc2.c @@ -39,14 +39,9 @@ #define DWC2_DEBUG 2 #include "device/dcd.h" +#include "device/usbd_pvt.h" #include "dwc2_common.h" -#if TU_CHECK_MCU(OPT_MCU_GD32VF103) - #define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX -#else - #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1) -#endif - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -58,6 +53,7 @@ typedef struct { uint8_t interval; } xfer_ctl_t; +// This variable is modified from ISR context, so it must be protected by critical section static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) @@ -79,6 +75,16 @@ CFG_TUD_MEM_SECTION static struct { TUD_EPBUF_DEF(setup_packet, 8); } _dcd_usbbuf; +TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) { + #if TU_CHECK_MCU(OPT_MCU_GD32VF103) + return DWC2_EP_MAX; + #else + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + return ghwcfg2.num_dev_ep + 1; + #endif +} + + //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- @@ -102,7 +108,8 @@ bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; // Internal DMA only - return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + return CFG_TUD_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA; } static void dma_setup_prepare(uint8_t rhport) { @@ -261,20 +268,15 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint xfer->interval = p_endpoint_desc->bInterval; // Endpoint control - union { - uint32_t value; - dwc2_depctl_t bm; - } depctl; - depctl.value = 0; - - depctl.bm.mps = xfer->max_size; - depctl.bm.active = 1; - depctl.bm.type = p_endpoint_desc->bmAttributes.xfer; + dwc2_depctl_t depctl = {.value = 0}; + depctl.mps = xfer->max_size; + depctl.active = 1; + depctl.type = p_endpoint_desc->bmAttributes.xfer; if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) { - depctl.bm.set_data0_iso_even = 1; + depctl.set_data0_iso_even = 1; } if (dir == TUSB_DIR_IN) { - //depctl.bm.tx_fifo_num = epnum; + //depctl.tx_fifo_num = epnum; uint8_t fifo_num = epnum; #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) // Special Case for EP5, which is used by CDC but not actually called by the driver @@ -285,7 +287,7 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint fifo_num = get_free_fifo(); } #endif - depctl.bm.tx_fifo_num = fifo_num; + depctl.tx_fifo_num = fifo_num; } dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; @@ -343,6 +345,9 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } +// Since this function returns void, it is not possible to return a boolean success message +// We must make sure that this function is not called when the EP is disabled +// Must be called from critical section static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); @@ -365,31 +370,22 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin } // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC. - union { - uint32_t value; - dwc2_ep_tsize_t bm; - } deptsiz; - deptsiz.value = 0; - deptsiz.bm.xfer_size = total_bytes; - deptsiz.bm.packet_count = num_packets; - + dwc2_ep_tsize_t deptsiz = {.value = 0}; + deptsiz.xfer_size = total_bytes; + deptsiz.packet_count = num_packets; dep->tsiz = deptsiz.value; // control - union { - dwc2_depctl_t bm; - uint32_t value; - } depctl; - depctl.value = dep->ctl; - - depctl.bm.clear_nak = 1; - depctl.bm.enable = 1; - if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { - const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u); + dwc2_depctl_t depctl = {.value = dep->ctl}; + depctl.clear_nak = 1; + depctl.enable = 1; + if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { + const dwc2_dsts_t dsts = {.value = dwc2->dsts}; + const uint32_t odd_now = dsts.frame_number & 1u; if (odd_now) { - depctl.bm.set_data0_iso_even = 1; + depctl.set_data0_iso_even = 1; } else { - depctl.bm.set_data1_iso_odd = 1; + depctl.set_data1_iso_odd = 1; } } @@ -432,7 +428,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + if (ghwcfg2.hs_phy_type == GHWCFG2_HSPHY_ULPI) { dcfg |= DCFG_XCVRDLY; } } else { @@ -561,6 +558,8 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + usbd_spin_lock(false); + _dcd_data.allocated_epin_count = 0; // Disable non-control interrupt @@ -582,8 +581,9 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_tx(dwc2, 0x10); // all tx fifo dfifo_flush_rx(dwc2); - dfifo_device_init(rhport); // re-init dfifo + + usbd_spin_unlock(false); } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -601,21 +601,31 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - xfer->ff = NULL; - xfer->total_len = total_bytes; + bool ret; - // EP0 can only handle one packet - if (epnum == 0) { - _dcd_data.ep0_pending[dir] = total_bytes; + usbd_spin_lock(false); + + if (xfer->max_size == 0) { + ret = false; // Endpoint is closed + } else { + xfer->buffer = buffer; + xfer->ff = NULL; + xfer->total_len = total_bytes; + + // EP0 can only handle one packet + if (epnum == 0) { + _dcd_data.ep0_pending[dir] = total_bytes; + } + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir); + ret = true; } - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir); + usbd_spin_unlock(false); - return true; + return ret; } // The number of bytes has to be given explicitly to allow more flexible control of how many @@ -628,17 +638,27 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = NULL; - xfer->ff = ff; - xfer->total_len = total_bytes; + bool ret; - // Schedule packets to be sent within interrupt - // TODO xfer fifo may only available for slave mode - edpt_schedule_packets(rhport, epnum, dir); + usbd_spin_lock(false); - return true; + if (xfer->max_size == 0) { + ret = false; // Endpoint is closed + } else { + xfer->buffer = NULL; + xfer->ff = ff; + xfer->total_len = total_bytes; + + // Schedule packets to be sent within interrupt + // TODO xfer fifo may only available for slave mode + edpt_schedule_packets(rhport, epnum, dir); + ret = true; + } + + usbd_spin_unlock(false); + + return ret; } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { @@ -665,9 +685,10 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { //-------------------------------------------------------------------- // 7.4.1 Initialization on USB Reset +// Must be called from critical section static void handle_bus_reset(uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); - const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + const uint8_t ep_count = dwc2_ep_count(dwc2); tu_memclr(xfer_status, sizeof(xfer_status)); @@ -697,7 +718,9 @@ static void handle_bus_reset(uint8_t rhport) { dfifo_device_init(rhport); // 5. Reset device address - dwc2->dcfg_bm.address = 0; + dwc2_dcfg_t dcfg = {.value = dwc2->dcfg}; + dcfg.address = 0; + dwc2->dcfg = dcfg.value; // Fixed both control EP0 size to 64 bytes dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -717,8 +740,9 @@ static void handle_bus_reset(uint8_t rhport) { static void handle_enum_done(uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); + const dwc2_dsts_t dsts = {.value = dwc2->dsts}; tusb_speed_t speed; - switch (dwc2->dsts_bm.enum_speed) { + switch (dsts.enum_speed) { case DCFG_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; @@ -763,12 +787,12 @@ static void handle_rxflvl_irq(uint8_t rhport) { const volatile uint32_t* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; - const uint8_t epnum = grxstsp_bm.ep_ch_num; + const dwc2_grxstsp_t grxstsp = {.value = dwc2->grxstsp}; + const uint8_t epnum = grxstsp.ep_ch_num; dwc2_dep_t* epout = &dwc2->epout[epnum]; - switch (grxstsp_bm.packet_status) { + switch (grxstsp.packet_status) { case GRXSTS_PKTSTS_GLOBAL_OUT_NAK: // Global OUT NAK: do nothing break; @@ -790,7 +814,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_RX_DATA: { // Out packet received - const uint16_t byte_count = grxstsp_bm.byte_count; + const uint16_t byte_count = grxstsp.byte_count; xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); if (byte_count) { @@ -804,7 +828,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { // short packet, minus remaining bytes (xfer_size) if (byte_count < xfer->max_size) { - xfer->total_len -= epout->tsiz_bm.xfer_size; + const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz}; + xfer->total_len -= tsiz.xfer_size; if (epnum == 0) { xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT]; _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0; @@ -866,11 +891,13 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep // - 64 bytes or // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) { - const uint16_t remain_packets = epin->tsiz_bm.packet_count; + dwc2_ep_tsize_t tsiz = {.value = epin->tsiz}; + const uint16_t remain_packets = tsiz.packet_count; // Process every single packet (only whole packets can be written to fifo) for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size; + tsiz.value = epin->tsiz; + const uint16_t remain_bytes = (uint16_t) tsiz.xfer_size; const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); // Check if dtxfsts has enough space available @@ -889,7 +916,8 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep } // Turn off TXFE if all bytes are written. - if (epin->tsiz_bm.xfer_size == 0) { + tsiz.value = epin->tsiz; + if (tsiz.xfer_size == 0) { dwc2->diepempmsk &= ~(1 << epnum); } } @@ -920,7 +948,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); // determine actual received bytes - const uint16_t remain = epout->tsiz_bm.xfer_size; + const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz}; + const uint16_t remain = tsiz.xfer_size; xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup @@ -956,7 +985,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin static void handle_ep_irq(uint8_t rhport, uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_device_enabled(dwc2); - const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + const uint8_t ep_count = dwc2_ep_count(dwc2); const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos; dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0]; @@ -1009,7 +1038,6 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) { */ void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint32_t gintmask = dwc2->gintmsk; const uint32_t gintsts = dwc2->gintsts & gintmask; @@ -1019,7 +1047,10 @@ void dcd_int_handler(uint8_t rhport) { #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) _allocated_fifos = 1; #endif + + usbd_spin_lock(true); handle_bus_reset(rhport); + usbd_spin_unlock(true); } if (gintsts & GINTSTS_ENUMDNE) { diff --git a/configs/builds.json b/configs/builds.json index 5ec2470cc..026c8d23b 100644 --- a/configs/builds.json +++ b/configs/builds.json @@ -36,6 +36,12 @@ "out":"lib/libesp_hw_support.a", "targets":["esp32s3"] }, + { + "file":"libesp_lcd.a", + "src":"build/esp-idf/esp_lcd/libesp_lcd.a", + "out":"lib/libesp_lcd.a", + "targets":["esp32s3"] + }, { "file":"sections.ld", "src":"build/esp-idf/esp_system/ld/sections.ld", diff --git a/configs/defconfig.40m b/configs/defconfig.40m index ffc4b5c1c..f265bd780 100644 --- a/configs/defconfig.40m +++ b/configs/defconfig.40m @@ -1 +1,3 @@ CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_SPEED=40 diff --git a/configs/defconfig.80m b/configs/defconfig.80m index 7014fa954..2cc7bd0ef 100644 --- a/configs/defconfig.80m +++ b/configs/defconfig.80m @@ -1 +1,3 @@ CONFIG_ESPTOOLPY_FLASHFREQ_80M=y +CONFIG_SPIRAM_SPEED_80M=y +CONFIG_SPIRAM_SPEED=80 diff --git a/configs/defconfig.common b/configs/defconfig.common index ba567d3fc..ae30e71f4 100644 --- a/configs/defconfig.common +++ b/configs/defconfig.common @@ -38,6 +38,7 @@ CONFIG_ESP_IPC_TASK_STACK_SIZE=1024 CONFIG_ESP_MAIN_TASK_STACK_SIZE=4096 CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE=2048 CONFIG_ESP_TASK_WDT_PANIC=y +# CONFIG_ESP_SYSTEM_HW_STACK_GUARD is not set CONFIG_ESP_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y CONFIG_ESPTOOLPY_HEADER_FLASHSIZE_UPDATE=y @@ -77,7 +78,7 @@ CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=2304 CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y CONFIG_FREERTOS_PLACE_SNAPSHOT_FUNS_INTO_FLASH=y CONFIG_HAL_ASSERTION_DISABLE=y -CONFIG_HEAP_POISONING_LIGHT=y +CONFIG_HEAP_POISONING_DISABLED=y CONFIG_HTTPD_MAX_REQ_HDR_LEN=1024 CONFIG_HTTPD_WS_SUPPORT=y CONFIG_LOG_DEFAULT_LEVEL_NONE=y @@ -157,7 +158,7 @@ CONFIG_MBEDTLS_ROM_MD5=y CONFIG_MBEDTLS_HARDWARE_ECC=y CONFIG_MBEDTLS_HARDWARE_AES=y CONFIG_MBEDTLS_HARDWARE_MPI=y -CONFIG_MBEDTLS_HARDWARE_SHA=y +# CONFIG_MBEDTLS_HARDWARE_SHA is not set # CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK is not set # CONFIG_MBEDTLS_HAVE_TIME is not set # CONFIG_MBEDTLS_ECDSA_DETERMINISTIC is not set @@ -177,6 +178,8 @@ CONFIG_MBEDTLS_ECP_C=y CONFIG_MBEDTLS_ECDH_C=y CONFIG_MBEDTLS_ECDSA_C=y CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +# CONFIG_MBEDTLS_SHA1_C is not set +# CONFIG_MBEDTLS_SHA1_ALT is not set # CONFIG_MBEDTLS_DHM_C is not set # CONFIG_MBEDTLS_ECJPAKE_C is not set # CONFIG_MBEDTLS_CLIENT_SSL_SESSION_TICKETS is not set @@ -226,6 +229,14 @@ CONFIG_LITTLEFS_MAX_PARTITIONS=2 CONFIG_LITTLEFS_MULTIVERSION=y CONFIG_LITTLEFS_DISK_VERSION_2_0=y +# +# TinyUSB Config +# +CONFIG_TINYUSB_CDC_MAX_PORTS=2 +CONFIG_USB_HOST_HUBS_SUPPORTED=y +CONFIG_USB_HOST_HUB_MULTI_LEVEL=y +CONFIG_USB_HOST_HW_BUFFER_BIAS_PERIODIC_OUT=y + # # Disable Cameras not used # diff --git a/configs/defconfig.esp32 b/configs/defconfig.esp32 index 92f4dbe4e..ccd403ef6 100644 --- a/configs/defconfig.esp32 +++ b/configs/defconfig.esp32 @@ -7,7 +7,7 @@ CONFIG_BT_STACK_NO_LOG=y # CONFIG_BLE_MESH is not set CONFIG_BT_NIMBLE_ENABLED=y CONFIG_BT_NIMBLE_LOG_LEVEL_NONE=y -CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1 +CONFIG_BT_NIMBLE_MAX_CONNECTIONS=2 # CONFIG_BT_NIMBLE_NVS_PERSIST is not set # CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS is not set # CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY is not set @@ -33,7 +33,6 @@ CONFIG_ETH_USE_SPI_ETHERNET=y CONFIG_SPIRAM=y CONFIG_SPIRAM_OCCUPY_HSPI_HOST=y -CONFIG_ULP_COPROC_ENABLED=y # CONFIG_ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 is not set # CONFIG_UNITY_ENABLE_FLOAT is not set # CONFIG_UNITY_ENABLE_DOUBLE is not set diff --git a/configs/defconfig.esp32c2 b/configs/defconfig.esp32c2 index 943a7a45f..9357c8008 100644 --- a/configs/defconfig.esp32c2 +++ b/configs/defconfig.esp32c2 @@ -12,7 +12,7 @@ CONFIG_BT_STACK_NO_LOG=y # CONFIG_BLE_MESH is not set CONFIG_BT_NIMBLE_ENABLED=y CONFIG_BT_NIMBLE_LOG_LEVEL_NONE=y -CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1 +CONFIG_BT_NIMBLE_MAX_CONNECTIONS=2 # CONFIG_BT_NIMBLE_NVS_PERSIST is not set # CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS is not set # CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY is not set diff --git a/configs/defconfig.esp32c3 b/configs/defconfig.esp32c3 index c3c5f8518..304af275e 100644 --- a/configs/defconfig.esp32c3 +++ b/configs/defconfig.esp32c3 @@ -7,7 +7,7 @@ CONFIG_BT_STACK_NO_LOG=y # CONFIG_BLE_MESH is not set CONFIG_BT_NIMBLE_ENABLED=y CONFIG_BT_NIMBLE_LOG_LEVEL_NONE=y -CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1 +CONFIG_BT_NIMBLE_MAX_CONNECTIONS=2 # CONFIG_BT_NIMBLE_NVS_PERSIST is not set # CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS is not set # CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY is not set diff --git a/configs/defconfig.esp32c6 b/configs/defconfig.esp32c6 index 06615dccd..d956f0abd 100644 --- a/configs/defconfig.esp32c6 +++ b/configs/defconfig.esp32c6 @@ -20,7 +20,7 @@ CONFIG_BT_STACK_NO_LOG=y # CONFIG_BLE_MESH is not set CONFIG_BT_NIMBLE_ENABLED=y CONFIG_BT_NIMBLE_LOG_LEVEL_NONE=y -CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1 +CONFIG_BT_NIMBLE_MAX_CONNECTIONS=2 # CONFIG_BT_NIMBLE_NVS_PERSIST is not set # CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS is not set # CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY is not set diff --git a/configs/defconfig.esp32h2 b/configs/defconfig.esp32h2 index 6d18ad8cc..bd5412692 100644 --- a/configs/defconfig.esp32h2 +++ b/configs/defconfig.esp32h2 @@ -7,7 +7,7 @@ CONFIG_BT_STACK_NO_LOG=y # CONFIG_BLE_MESH is not set CONFIG_BT_NIMBLE_ENABLED=y CONFIG_BT_NIMBLE_LOG_LEVEL_NONE=y -CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1 +CONFIG_BT_NIMBLE_MAX_CONNECTIONS=2 # CONFIG_BT_NIMBLE_NVS_PERSIST is not set # CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS is not set # CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY is not set diff --git a/configs/defconfig.esp32p4 b/configs/defconfig.esp32p4 index 94618d831..5fcdb5616 100644 --- a/configs/defconfig.esp32p4 +++ b/configs/defconfig.esp32p4 @@ -20,6 +20,10 @@ CONFIG_FREERTOS_TIMER_TASK_STACK_DEPTH=3120 CONFIG_CACHE_L2_CACHE_256KB=y CONFIG_CACHE_L2_CACHE_LINE_128B=y +# RGB Display Optimizations +CONFIG_LCD_RGB_ISR_IRAM_SAFE=y +CONFIG_LCD_RGB_RESTART_IN_VSYNC=y + CONFIG_SLAVE_IDF_TARGET_ESP32C6=y CONFIG_ESP_SDIO_BUS_WIDTH=4 CONFIG_ESP_SDIO_CLOCK_FREQ_KHZ=40000 @@ -30,17 +34,6 @@ CONFIG_ESP_SDIO_PIN_D1=15 CONFIG_ESP_SDIO_PIN_D2=16 CONFIG_ESP_SDIO_PIN_D3=17 -# -# Chip revision -# -CONFIG_ESP32P4_REV_MIN_0=y -# CONFIG_ESP32P4_REV_MIN_1 is not set -CONFIG_ESP32P4_REV_MIN_FULL=0 -CONFIG_ESP_REV_MIN_FULL=0 -CONFIG_ESP32P4_REV_MAX_FULL=99 -CONFIG_ESP_REV_MAX_FULL=99 -# end of Chip revision - # # PPP # diff --git a/configs/defconfig.esp32s3 b/configs/defconfig.esp32s3 index 758a1c9c4..dc98e0243 100644 --- a/configs/defconfig.esp32s3 +++ b/configs/defconfig.esp32s3 @@ -7,6 +7,8 @@ CONFIG_ULP_COPROC_RESERVE_MEM=4096 CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240=y CONFIG_SPIRAM=y CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP=y +CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB=y +CONFIG_ESP32S3_DATA_CACHE_16KB=y CONFIG_RTC_CLK_CAL_CYCLES=576 CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES_TWO=y # CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND is not set @@ -30,7 +32,7 @@ CONFIG_BT_STACK_NO_LOG=y # CONFIG_BLE_MESH is not set CONFIG_BT_NIMBLE_ENABLED=y CONFIG_BT_NIMBLE_LOG_LEVEL_NONE=y -CONFIG_BT_NIMBLE_MAX_CONNECTIONS=1 +CONFIG_BT_NIMBLE_MAX_CONNECTIONS=2 # CONFIG_BT_NIMBLE_NVS_PERSIST is not set # CONFIG_BT_NIMBLE_CRYPTO_STACK_MBEDTLS is not set # CONFIG_BT_NIMBLE_LL_CFG_FEAT_LE_2M_PHY is not set diff --git a/configs/defconfig.opi_ram b/configs/defconfig.opi_ram index 7b94edaf9..f1f2238cd 100644 --- a/configs/defconfig.opi_ram +++ b/configs/defconfig.opi_ram @@ -7,5 +7,6 @@ CONFIG_GDMA_CTRL_FUNC_IN_IRAM=y # I2S_ISR_IRAM_SAFE has to be set!! Done in common config CONFIG_GDMA_ISR_IRAM_SAFE=y # Enable the XIP-PSRAM feature, so the ext-mem cache won't be disabled when SPI1 is operating the main flash +CONFIG_SPIRAM_XIP_FROM_PSRAM=y CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y CONFIG_SPIRAM_RODATA=y diff --git a/configs/pio_end.txt b/configs/pio_end.txt index f942d442d..d9b5d5467 100644 --- a/configs/pio_end.txt +++ b/configs/pio_end.txt @@ -1,4 +1,5 @@ "ARDUINO_ARCH_ESP32", + "CHIP_HAVE_CONFIG_H", ("ESP32", "ESP32"), ("F_CPU", "$BOARD_F_CPU"), ("ARDUINO", 10812), diff --git a/tools/archive-build.sh b/tools/archive-build.sh index 139d720bf..1a999662e 100755 --- a/tools/archive-build.sh +++ b/tools/archive-build.sh @@ -61,7 +61,7 @@ mv arduino-esp32/ framework-arduinoespressif32/ cd framework-arduinoespressif32/libraries rm -rf **/examples cd ../tools/esp32-arduino-libs -rm -rf **/flags +# rm -rf **/flags cd ../../../ # If the framework is needed as tar.gz uncomment next line # tar --exclude=.* -zcf ../$pio_archive_path framework-arduinoespressif32/ diff --git a/tools/config.sh b/tools/config.sh index cac07c340..17b5c13ae 100755 --- a/tools/config.sh +++ b/tools/config.sh @@ -11,7 +11,7 @@ fi # Arduino branch to use if [ -z $AR_BRANCH ]; then - AR_BRANCH="main" + AR_BRANCH="release/v3.1.x" fi if [ -z $IDF_TARGET ]; then diff --git a/tools/copy-libs.sh b/tools/copy-libs.sh index 9513e862a..573b83076 100755 --- a/tools/copy-libs.sh +++ b/tools/copy-libs.sh @@ -122,7 +122,7 @@ for item in "${@:2:${#@}-5}"; do INCLUDES+="$item " fi elif [ "$prefix" = "-D" ]; then - if [[ "${item:2:7}" != "ARDUINO" ]] && [[ "$item" != "-DESP32=ESP32" ]]; then #skip ARDUINO defines + if [[ "${item:2:7}" != "ARDUINO" ]] && [[ "$item" != "-DESP32=ESP32" ]] && [[ "$item" != "-DNDEBUG" ]]; then #skip ARDUINO defines DEFINES+="$item " fi elif [ "$prefix" = "-O" ]; then @@ -489,7 +489,8 @@ echo "" >> "$AR_PLATFORMIO_PY" echo " CPPDEFINES=[" >> "$AR_PLATFORMIO_PY" set -- $DEFINES for item; do - item="${item:2}" #remove -D + item="${item:2}" #remove -D + item="${item/NDEBUG}" #remove NDEBUG if [[ $item == *"="* ]]; then item=(${item//=/ }) re='^[+-]?[0-9]+([.][0-9]+)?$' diff --git a/tools/install-esp-idf.sh b/tools/install-esp-idf.sh index f79f5c7f9..ca0c46660 100755 --- a/tools/install-esp-idf.sh +++ b/tools/install-esp-idf.sh @@ -49,10 +49,24 @@ else fi if [ "$IDF_TAG" ]; then + cd $IDF_PATH git -C "$IDF_PATH" checkout "tags/$IDF_TAG" + git reset --hard "tags/$IDF_TAG" + git submodule update --recursive + git rm -r $IDF_PATH/components/wifi_provisioning + git rm -r $IDF_PATH/components/spiffs + git commit -m "delete components SPIFFS and wifi-provisioning" + cd - idf_was_installed="1" elif [ "$IDF_COMMIT" ]; then + cd $IDF_PATH git -C "$IDF_PATH" checkout "$IDF_COMMIT" + git reset --hard $IDF_COMMIT + git submodule update --recursive + git rm -r $IDF_PATH/components/wifi_provisioning + git rm -r $IDF_PATH/components/spiffs + git commit -m "delete components SPIFFS and wifi-provisioning" + cd - commit_predefined="1" fi @@ -62,7 +76,8 @@ fi if [ ! -x $idf_was_installed ] || [ ! -x $commit_predefined ]; then git submodule update --recursive - $IDF_PATH/install.sh + echo "Installing ESP-IDF..." + $IDF_PATH/install.sh > /dev/null # 1) Temporarily patch the ESP32-S2 I2C LL driver to keep the clock source # 2) Temporarily fix for mmu map and late init of psram https://github.com/espressif/arduino-esp32/issues/9936 diff --git a/tools/prepare-ci.sh b/tools/prepare-ci.sh index 0855e8496..7e5a29f1f 100755 --- a/tools/prepare-ci.sh +++ b/tools/prepare-ci.sh @@ -10,7 +10,7 @@ brew install gsed brew install gawk brew install gperf -brew install ninja +#brew install ninja brew install ccache python -m pip install --upgrade pip pip install wheel future pyelftools