2121#define  FLAG_RXnIF (n )              (0x01  << n)
2222#define  FLAG_TXnIF (n )              (0x04  << n)
2323
24+ #define  REG_RXFnSIDH (n )            (0x00  + (n * 4 ))
25+ #define  REG_RXFnSIDL (n )            (0x01  + (n * 4 ))
26+ #define  REG_RXFnEID8 (n )            (0x02  + (n * 4 ))
27+ #define  REG_RXFnEID0 (n )            (0x03  + (n * 4 ))
28+ 
29+ #define  REG_RXMnSIDH (n )            (0x20  + (n * 0x04 ))
30+ #define  REG_RXMnSIDL (n )            (0x21  + (n * 0x04 ))
31+ #define  REG_RXMnEID8 (n )            (0x22  + (n * 0x04 ))
32+ #define  REG_RXMnEID0 (n )            (0x23  + (n * 0x04 ))
33+ 
2434#define  REG_TXBnCTRL (n )            (0x30  + (n * 0x10 ))
2535#define  REG_TXBnSIDH (n )            (0x31  + (n * 0x10 ))
2636#define  REG_TXBnSIDL (n )            (0x32  + (n * 0x10 ))
4555#define  FLAG_RXM0                   0x20 
4656#define  FLAG_RXM1                   0x40 
4757
48- #define  REG_RXB0CTRL                0x60 
49- #define  REG_RXB1CTRL                0x70 
5058
5159MCP2515Class::MCP2515Class () :
5260  CANControllerClass(),
@@ -129,8 +137,8 @@ int MCP2515Class::begin(long baudRate)
129137  writeRegister (REG_CANINTE, FLAG_RXnIE (1 ) | FLAG_RXnIE (0 ));
130138  writeRegister (REG_BFPCTRL, 0x00 );
131139  writeRegister (REG_TXRTSCTRL, 0x00 );
132-   writeRegister (REG_RXB0CTRL , FLAG_RXM1 | FLAG_RXM0);
133-   writeRegister (REG_RXB1CTRL , FLAG_RXM1 | FLAG_RXM0);
140+   writeRegister (REG_RXBnCTRL ( 0 ) , FLAG_RXM1 | FLAG_RXM0);
141+   writeRegister (REG_RXBnCTRL ( 1 ) , FLAG_RXM1 | FLAG_RXM0);
134142
135143  writeRegister (REG_CANCTRL, 0x00 );
136144  if  (readRegister (REG_CANCTRL) != 0x00 ) {
@@ -157,7 +165,7 @@ int MCP2515Class::endPacket()
157165
158166  if  (_txExtended) {
159167    writeRegister (REG_TXBnSIDH (n), _txId >> 21 );
160-     writeRegister (REG_TXBnSIDL (n), (((_txId >> 18 ) & 0x03 ) << 5 ) | FLAG_EXIDE | ((_txId >> 16 ) & 0x03 ));
168+     writeRegister (REG_TXBnSIDL (n), (((_txId >> 18 ) & 0x07 ) << 5 ) | FLAG_EXIDE | ((_txId >> 16 ) & 0x03 ));
161169    writeRegister (REG_TXBnEID8 (n), (_txId >> 8 ) & 0xff );
162170    writeRegister (REG_TXBnEID0 (n), _txId & 0xff );
163171  } else  {
@@ -213,7 +221,7 @@ int MCP2515Class::parsePacket()
213221
214222  _rxExtended = (readRegister (REG_RXBnSIDL (n)) & FLAG_IDE) ? true  : false ;
215223
216-   uint32_t  idA = ((readRegister (REG_RXBnSIDH (n)) << 3 ) & 0xf8 ) | ((readRegister (REG_RXBnSIDL (n)) >> 5 ) & 0x07 );
224+   uint32_t  idA = ((readRegister (REG_RXBnSIDH (n)) << 3 ) & 0x07f8 ) | ((readRegister (REG_RXBnSIDL (n)) >> 5 ) & 0x07 );
217225  if  (_rxExtended) {
218226    uint32_t  idB = (((uint32_t )(readRegister (REG_RXBnSIDL (n)) & 0x03 ) << 16 ) & 0x30000 ) | ((readRegister (REG_RXBnEID8 (n)) << 8 ) & 0xff00 ) | readRegister (REG_RXBnEID0 (n));
219227
@@ -258,6 +266,82 @@ void MCP2515Class::onReceive(void(*callback)(int))
258266  }
259267}
260268
269+ int  MCP2515Class::filter (int  id, int  mask)
270+ {
271+   id &= 0x7ff ;
272+   mask &= 0x7ff ;
273+ 
274+   //  config mode
275+   writeRegister (REG_CANCTRL, 0x80 );
276+   if  (readRegister (REG_CANCTRL) != 0x80 ) {
277+     return  0 ;
278+   }
279+ 
280+   for  (int  n = 0 ; n < 2 ; n++) {
281+     //  standard only
282+     writeRegister (REG_RXBnCTRL (n), FLAG_RXM0);
283+     writeRegister (REG_RXBnCTRL (n), FLAG_RXM0);
284+ 
285+     writeRegister (REG_RXMnSIDH (n), mask >> 3 );
286+     writeRegister (REG_RXMnSIDL (n), mask << 5 );
287+     writeRegister (REG_RXMnEID8 (n), 0 );
288+     writeRegister (REG_RXMnEID0 (n), 0 );
289+   }
290+ 
291+   for  (int  n = 0 ; n < 6 ; n++) {
292+     writeRegister (REG_RXFnSIDH (n), id >> 3 );
293+     writeRegister (REG_RXFnSIDL (n), id << 5 );
294+     writeRegister (REG_RXFnEID8 (n), 0 );
295+     writeRegister (REG_RXFnEID0 (n), 0 );
296+   }
297+ 
298+   //  normal mode
299+   writeRegister (REG_CANCTRL, 0x00 );
300+   if  (readRegister (REG_CANCTRL) != 0x00 ) {
301+     return  0 ;
302+   }
303+ 
304+   return  1 ;
305+ }
306+ 
307+ int  MCP2515Class::filterExtended (long  id, long  mask)
308+ {
309+   id &= 0x1FFFFFFF ;
310+   mask &= 0x1FFFFFFF ;
311+ 
312+   //  config mode
313+   writeRegister (REG_CANCTRL, 0x80 );
314+   if  (readRegister (REG_CANCTRL) != 0x80 ) {
315+     return  0 ;
316+   }
317+ 
318+   for  (int  n = 0 ; n < 2 ; n++) {
319+     //  extended only
320+     writeRegister (REG_RXBnCTRL (n), FLAG_RXM1);
321+     writeRegister (REG_RXBnCTRL (n), FLAG_RXM1);
322+ 
323+     writeRegister (REG_RXMnSIDH (n), mask >> 21 );
324+     writeRegister (REG_RXMnSIDL (n), (((mask >> 18 ) & 0x03 ) << 5 ) | FLAG_EXIDE | ((mask >> 16 ) & 0x03 ));
325+     writeRegister (REG_RXMnEID8 (n), (mask >> 8 ) & 0xff );
326+     writeRegister (REG_RXMnEID0 (n), mask & 0xff );
327+   }
328+ 
329+   for  (int  n = 0 ; n < 6 ; n++) {
330+     writeRegister (REG_RXFnSIDH (n), id >> 21 );
331+     writeRegister (REG_RXFnSIDL (n), (((id >> 18 ) & 0x03 ) << 5 ) | FLAG_EXIDE | ((id >> 16 ) & 0x03 ));
332+     writeRegister (REG_RXFnEID8 (n), (id >> 8 ) & 0xff );
333+     writeRegister (REG_RXFnEID0 (n), id & 0xff );
334+   }
335+ 
336+   //  normal mode
337+   writeRegister (REG_CANCTRL, 0x00 );
338+   if  (readRegister (REG_CANCTRL) != 0x00 ) {
339+     return  0 ;
340+   }
341+ 
342+   return  1 ;
343+ }
344+ 
261345int  MCP2515Class::observe ()
262346{
263347  writeRegister (REG_CANCTRL, 0x80 );
0 commit comments