IDF release/v5.1 3fd0eff833

Author: me-no-dev

esp32/bin/bootloader_dio_40m.elf

@@ -60,6 +60,7 @@
 #define CONFIG_SOC_ADC_RTC_MIN_BITWIDTH 9
 #define CONFIG_SOC_ADC_RTC_MAX_BITWIDTH 12
 #define CONFIG_SOC_SHARED_IDCACHE_SUPPORTED 1
+#define CONFIG_SOC_IDCACHE_PER_CORE 1
 #define CONFIG_SOC_CPU_CORES_NUM 2
 #define CONFIG_SOC_CPU_INTR_NUM 32
 #define CONFIG_SOC_CPU_HAS_FPU 1
@@ -1083,5 +1084,5 @@
 #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
 #define CONFIG_WPA_MBEDTLS_CRYPTO CONFIG_ESP_WIFI_MBEDTLS_CRYPTO
 #define CONFIG_WPA_MBEDTLS_TLS_CLIENT CONFIG_ESP_WIFI_MBEDTLS_TLS_CLIENT
-#define CONFIG_ARDUINO_IDF_COMMIT "79b1379662"
+#define CONFIG_ARDUINO_IDF_COMMIT "3fd0eff833"
 #define CONFIG_ARDUINO_IDF_BRANCH "release/v5.1"

esp32/bin/bootloader_dio_80m.elf

@@ -1 +1 @@
--DESP_PLATFORM -DIDF_VER=\"v5.1-480-g79b1379662\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DSOC_XTAL_FREQ_MHZ=CONFIG_XTAL_FREQ -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 -DTF_LITE_STATIC_MEMORY 
+-DESP_PLATFORM -DIDF_VER=\"v5.1-552-g3fd0eff833\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DUNITY_INCLUDE_CONFIG_H -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DconfigENABLE_FREERTOS_DEBUG_OCDAWARE=1 -DTF_LITE_STATIC_MEMORY 

esp32/bin/bootloader_qio_40m.elf

@@ -393,9 +393,9 @@ namespace dl
             void print()
             {
 #if DL_LOG_LATENCY_UNIT
-                printf("latency: %15u cycle\n", this->get_average_period());
+                printf("latency: %15lu cycle\n", this->get_average_period());
 #else
-                printf("latency: %15u us\n", this->get_average_period());
+                printf("latency: %15lu us\n", this->get_average_period());
 #endif
             }
 
@@ -407,9 +407,9 @@ namespace dl
             void print(const char *message)
             {
 #if DL_LOG_LATENCY_UNIT
-                printf("%s: %15u cycle\n", message, this->get_average_period());
+                printf("%s: %15lu cycle\n", message, this->get_average_period());
 #else
-                printf("%s: %15u us\n", message, this->get_average_period());
+                printf("%s: %15lu us\n", message, this->get_average_period());
 #endif
             }
 
@@ -422,9 +422,9 @@ namespace dl
             void print(const char *prefix, const char *key)
             {
 #if DL_LOG_LATENCY_UNIT
-                printf("%s::%s: %u cycle\n", prefix, key, this->get_average_period());
+                printf("%s::%s: %lu cycle\n", prefix, key, this->get_average_period());
 #else
-                printf("%s::%s: %u us\n", prefix, key, this->get_average_period());
+                printf("%s::%s: %lu us\n", prefix, key, this->get_average_period());
 #endif
             }
         };

esp32/bin/bootloader_qio_80m.elf

@@ -0,0 +1,19 @@
+#ifndef ESP_KERNEL_H
+#define ESP_KERNEL_H
+#include <stdint.h>
+#include <stdio.h>
+#include <assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+	void esp_dl_nn_conv2d_s8_wrapper(int8_t* input, int8_t* kernel, int8_t* bias, int input_shape[], int kernel_shape[], int output_shape[], int padding[], int dilation[], int strides[], int input_exponent, int kernel_exponent, int output_exponent, char activation_sym[], int8_t* output);
+	void esp_dl_nn_depthwise_conv2d_s8_wrapper(int8_t* input, int8_t* kernel, int8_t* bias, int input_shape[], int kernel_shape[], int output_shape[], int padding[], int dilation[], int strides[], int input_exponent, int kernel_exponent, int output_exponent, char activation_sym[], int8_t* output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // ESP_KERNEL_H
+

esp32/dio_qspi/include/sdkconfig.h

@@ -9,9 +9,9 @@
 extern "C" {
 #endif
 
-#define ESP_LITTLEFS_VERSION_NUMBER "1.6.0"
+#define ESP_LITTLEFS_VERSION_NUMBER "1.7.0"
 #define ESP_LITTLEFS_VERSION_MAJOR 1
-#define ESP_LITTLEFS_VERSION_MINOR 6
+#define ESP_LITTLEFS_VERSION_MINOR 7
 #define ESP_LITTLEFS_VERSION_PATCH 0
 
 #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 4, 2) && CONFIG_VFS_SUPPORT_DIR

esp32/dio_qspi/libspi_flash.a

@@ -65,6 +65,8 @@ typedef struct {
     char *model;
     /** Subtype (Optional). */
     char *subtype;
+    /** An array of digests read from efuse. Should be freed after use*/
+    char **secure_boot_digest;
 } esp_rmaker_node_info_t;
 
 /** ESP RainMaker Configuration */

esp32/flags/defines

@@ -87,6 +87,7 @@ extern "C" {
 #define ESP_ERR_WIFI_TWT_SETUP_TIMEOUT (ESP_ERR_WIFI_BASE + 24)  /*!< Timeout of receiving twt setup response frame, timeout times can be set during twt setup */
 #define ESP_ERR_WIFI_TWT_SETUP_TXFAIL  (ESP_ERR_WIFI_BASE + 25)  /*!< TWT setup frame tx failed */
 #define ESP_ERR_WIFI_TWT_SETUP_REJECT  (ESP_ERR_WIFI_BASE + 26)  /*!< The twt setup request was rejected by the AP */
+#define ESP_ERR_WIFI_DISCARD           (ESP_ERR_WIFI_BASE + 27)  /*!< Discard frame */
 
 /**
  * @brief WiFi stack configuration parameters passed to esp_wifi_init call.

esp32/flags/includes

@@ -19,6 +19,66 @@
 extern "C" {
 #endif
 
+/**
+ * @brief enable a cache unit
+ *
+ * @param cache_id  cache ID (when l1 cache is per core)
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l1_enable_cache(uint32_t cache_id)
+{
+    HAL_ASSERT(cache_id == 0 || cache_id == 1);
+
+    if (cache_id == 0) {
+        DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
+    } else {
+        DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
+    }
+}
+
+/**
+ * @brief disable a cache unit
+ *
+ * @param cache_id  cache ID (when l1 cache is per core)
+ */
+__attribute__((always_inline))
+static inline void cache_ll_l1_disable_cache(uint32_t cache_id)
+{
+    if (cache_id == 0) {
+        while (DPORT_GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1){
+            ;
+        }
+        DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
+    } else {
+        while (DPORT_GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1){
+            ;
+        }
+        DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
+    }
+}
+
+/**
+ * @brief Get the status of cache if it is enabled or not
+ *
+ * @param   cache_id    cache ID (when l1 cache is per core)
+ * @param   type        see `cache_type_t`
+ * @return  enabled or not
+ */
+__attribute__((always_inline))
+static inline bool cache_ll_l1_is_cache_enabled(uint32_t cache_id, cache_type_t type)
+{
+    HAL_ASSERT(cache_id == 0 || cache_id == 1);
+    (void) type;    //On 32 it shares between I and D cache
+
+    bool enabled;
+    if (cache_id == 0) {
+        enabled = DPORT_REG_GET_BIT(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_CACHE_ENABLE);
+    } else {
+        enabled = DPORT_REG_GET_BIT(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_CACHE_ENABLE);
+    }
+    return enabled;
+}
+
 /**
  * @brief Get the buses of a particular cache that are mapped to a virtual address range
  *

esp32/include/esp-dl/include/tool/dl_tool.hpp

@@ -1,12 +1,13 @@
 
 /*
- * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include <stdbool.h>
 #include "hal/cache_types.h"
 
 #ifdef __cplusplus
@@ -39,6 +40,35 @@ void cache_hal_disable(cache_type_t type);
  */
 void cache_hal_enable(cache_type_t type);
 
+/**
+ * @brief Suspend cache
+ *
+ * Suspend the ICache or DCache or both，suspends the CPU access to cache for a while, without invalidation.
+ *
+ * @param type  see `cache_type_t`
+ *
+ * @return  Current status of corresponding Cache(s)
+ */
+void cache_hal_suspend(cache_type_t type);
+
+/**
+ * @brief Resume cache
+ *
+ * Resume the ICache or DCache or both.
+ *
+ * @param type  see `cache_type_t`
+ */
+void cache_hal_resume(cache_type_t type);
+
+/**
+ * @brief Check if corresponding cache is enabled or not
+ *
+ * @param type  see `cache_type_t`
+ *
+ * @return true: enabled; false: disabled
+ */
+bool cache_hal_is_cache_enabled(cache_type_t type);
+
 /**
  * @brief Invalidate cache supported addr
  *

esp32/include/esp-dl/include/tvm/esp_kernel.h

@@ -159,7 +159,6 @@
 #define  CPU_CLK_FREQ_MHZ_BTLD                       (80)               // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
 #define  CPU_CLK_FREQ                                APB_CLK_FREQ       //this may be incorrect, please refer to ESP_DEFAULT_CPU_FREQ_MHZ
 #define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
-#define  MODEM_REQUIRED_MIN_APB_CLK_FREQ             ( 80*1000000 )
 #define  REF_CLK_FREQ                                ( 1000000 )
 #define  UART_CLK_FREQ                               APB_CLK_FREQ
 #define  WDT_CLK_FREQ                                APB_CLK_FREQ

esp32/include/esp_littlefs/include/esp_littlefs.h

@@ -138,7 +138,8 @@
 #endif
 
 /*-------------------------- CACHE CAPS --------------------------------------*/
-#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data within one core
+#define SOC_IDCACHE_PER_CORE                    1   //Independent Cache unit pre core
 
 /*-------------------------- CPU CAPS ----------------------------------------*/
 #define SOC_CPU_CORES_NUM               2

esp32/include/esp_rainmaker/include/esp_rmaker_core.h

@@ -0,0 +1,25 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef SIGNAL_MICRO_KERNELS_DELAY_FLEXBUFFERS_GENERATED_DATA_H_
+#define SIGNAL_MICRO_KERNELS_DELAY_FLEXBUFFERS_GENERATED_DATA_H_
+
+extern const int g_gen_data_size_3_delay;
+extern const unsigned char g_gen_data_3_delay[];
+
+extern const int g_gen_data_size_5_delay;
+extern const unsigned char g_gen_data_5_delay[];
+
+#endif  // SIGNAL_MICRO_KERNELS_DELAY_FLEXBUFFERS_GENERATED_DATA_H_

esp32/include/esp_wifi/include/esp_wifi.h

@@ -0,0 +1,28 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_ENERGY_FLEXBUFFERS_DATA_H_
+#define SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_ENERGY_FLEXBUFFERS_DATA_H_
+
+extern const int g_gen_data_size_start_index_2_end_index_4;
+extern const unsigned char g_gen_data_start_index_2_end_index_4[];
+
+extern const int g_gen_data_size_start_index_0_end_index_4;
+extern const unsigned char g_gen_data_start_index_0_end_index_4[];
+
+extern const int g_gen_data_size_start_index_4_end_index_8;
+extern const unsigned char g_gen_data_start_index_4_end_index_8[];
+
+#endif  // SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_ENERGY_FLEXBUFFERS_DATA_H_

esp32/include/hal/esp32/include/hal/cache_ll.h

@@ -0,0 +1,25 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_FLEXBUFFERS_DATA_H_
+#define SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_FLEXBUFFERS_DATA_H_
+
+extern const int g_gen_data_size_filter_bank_32_channel;
+extern const unsigned char g_gen_data_filter_bank_32_channel[];
+
+extern const int g_gen_data_size_filter_bank_16_channel;
+extern const unsigned char g_gen_data_filter_bank_16_channel[];
+
+#endif  // SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_FLEXBUFFERS_DATA_H_

esp32/include/hal/include/hal/cache_hal.h

@@ -0,0 +1,27 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_LOG_FLEXBUFFERS_DATA_H_
+#define SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_LOG_FLEXBUFFERS_DATA_H_
+
+extern const int g_gen_data_size_filter_bank_log_scale_1600_correction_bits_3;
+extern const unsigned char
+    g_gen_data_filter_bank_log_scale_1600_correction_bits_3[];
+
+extern const int g_gen_data_size_filter_bank_log_scale_32768_correction_bits_5;
+extern const unsigned char
+    g_gen_data_filter_bank_log_scale_32768_correction_bits_5[];
+
+#endif  // SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_LOG_FLEXBUFFERS_DATA_H_

esp32/include/soc/esp32/include/soc/soc.h

@@ -0,0 +1,26 @@
+/* Copyright 2020 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_SPECTRAL_SUBTRACTION_FLEXBUFFERS_DATA_H_
+#define SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_SPECTRAL_SUBTRACTION_FLEXBUFFERS_DATA_H_
+
+extern const int g_gen_data_size_filter_bank_spectral_subtraction_32_channel;
+extern const unsigned char
+    g_gen_data_filter_bank_spectral_subtraction_32_channel[];
+extern const int g_gen_data_size_filter_bank_spectral_subtraction_16_channel;
+extern const unsigned char
+    g_gen_data_filter_bank_spectral_subtraction_16_channel[];
+
+#endif  // SIGNAL_MICRO_KERNELS_TEST_DATA_GENERATION_GENERATE_FILTER_BANK_SPECTRAL_SUBTRACTION_FLEXBUFFERS_DATA_H_