diff --git a/codereview.cfg b/codereview.cfg index 77a74f108eae36..e59a1c89121b4c 100644 --- a/codereview.cfg +++ b/codereview.cfg @@ -1 +1,2 @@ -branch: master +branch: dev.simd +parent-branch: master diff --git a/src/cmd/compile/internal/abi/abiutils.go b/src/cmd/compile/internal/abi/abiutils.go index c013aba19c41a6..cef78858151501 100644 --- a/src/cmd/compile/internal/abi/abiutils.go +++ b/src/cmd/compile/internal/abi/abiutils.go @@ -150,12 +150,12 @@ func appendParamTypes(rts []*types.Type, t *types.Type) []*types.Type { if w == 0 { return rts } - if t.IsScalar() || t.IsPtrShaped() { + if t.IsScalar() || t.IsPtrShaped() || t.IsSIMD() { if t.IsComplex() { c := types.FloatForComplex(t) return append(rts, c, c) } else { - if int(t.Size()) <= types.RegSize { + if int(t.Size()) <= types.RegSize || t.IsSIMD() { return append(rts, t) } // assume 64bit int on 32-bit machine @@ -199,6 +199,9 @@ func appendParamOffsets(offsets []int64, at int64, t *types.Type) ([]int64, int6 if w == 0 { return offsets, at } + if t.IsSIMD() { + return append(offsets, at), at + w + } if t.IsScalar() || t.IsPtrShaped() { if t.IsComplex() || int(t.Size()) > types.RegSize { // complex and *int64 on 32-bit s := w / 2 @@ -521,11 +524,11 @@ func (state *assignState) allocateRegs(regs []RegIndex, t *types.Type) []RegInde } ri := state.rUsed.intRegs rf := state.rUsed.floatRegs - if t.IsScalar() || t.IsPtrShaped() { + if t.IsScalar() || t.IsPtrShaped() || t.IsSIMD() { if t.IsComplex() { regs = append(regs, RegIndex(rf+state.rTotal.intRegs), RegIndex(rf+1+state.rTotal.intRegs)) rf += 2 - } else if t.IsFloat() { + } else if t.IsFloat() || t.IsSIMD() { regs = append(regs, RegIndex(rf+state.rTotal.intRegs)) rf += 1 } else { diff --git a/src/cmd/compile/internal/amd64/simdssa.go b/src/cmd/compile/internal/amd64/simdssa.go new file mode 100644 index 00000000000000..5fc068c895c6b7 --- /dev/null +++ b/src/cmd/compile/internal/amd64/simdssa.go @@ -0,0 +1,1312 @@ +// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT. + +package amd64 + +import ( + "cmd/compile/internal/ssa" + "cmd/compile/internal/ssagen" + "cmd/internal/obj" + "cmd/internal/obj/x86" +) + +func ssaGenSIMDValue(s *ssagen.State, v *ssa.Value) bool { + var p *obj.Prog + switch v.Op { + case ssa.OpAMD64VPABSW256, + ssa.OpAMD64VPABSW128, + ssa.OpAMD64VPABSD128, + ssa.OpAMD64VPABSD256, + ssa.OpAMD64VPABSB128, + ssa.OpAMD64VPABSB256, + ssa.OpAMD64VPABSW512, + ssa.OpAMD64VPABSD512, + ssa.OpAMD64VPABSQ128, + ssa.OpAMD64VPABSQ256, + ssa.OpAMD64VPABSQ512, + ssa.OpAMD64VPABSB512, + ssa.OpAMD64VRCP14PS512, + ssa.OpAMD64VRCP14PS128, + ssa.OpAMD64VRCP14PS256, + ssa.OpAMD64VRCP14PD128, + ssa.OpAMD64VRCP14PD256, + ssa.OpAMD64VRCP14PD512, + ssa.OpAMD64VRSQRTPS128, + ssa.OpAMD64VRSQRTPS256, + ssa.OpAMD64VRSQRT14PS512, + ssa.OpAMD64VRSQRT14PD128, + ssa.OpAMD64VRSQRT14PD256, + ssa.OpAMD64VRSQRT14PD512, + ssa.OpAMD64VPOPCNTW256, + ssa.OpAMD64VPOPCNTW512, + ssa.OpAMD64VPOPCNTW128, + ssa.OpAMD64VPOPCNTD512, + ssa.OpAMD64VPOPCNTD128, + ssa.OpAMD64VPOPCNTD256, + ssa.OpAMD64VPOPCNTQ128, + ssa.OpAMD64VPOPCNTQ256, + ssa.OpAMD64VPOPCNTQ512, + ssa.OpAMD64VPOPCNTB128, + ssa.OpAMD64VPOPCNTB256, + ssa.OpAMD64VPOPCNTB512, + ssa.OpAMD64VSQRTPS128, + ssa.OpAMD64VSQRTPS256, + ssa.OpAMD64VSQRTPD128, + ssa.OpAMD64VSQRTPD256, + ssa.OpAMD64VSQRTPS512, + ssa.OpAMD64VSQRTPD512: + p = simdFp11(s, v) + + case ssa.OpAMD64VADDPS128, + ssa.OpAMD64VADDPS256, + ssa.OpAMD64VADDPD128, + ssa.OpAMD64VADDPD256, + ssa.OpAMD64VPADDW256, + ssa.OpAMD64VPADDW128, + ssa.OpAMD64VPADDD128, + ssa.OpAMD64VPADDD256, + ssa.OpAMD64VPADDQ128, + ssa.OpAMD64VPADDQ256, + ssa.OpAMD64VPADDB128, + ssa.OpAMD64VPADDB256, + ssa.OpAMD64VADDPS512, + ssa.OpAMD64VADDPD512, + ssa.OpAMD64VPADDW512, + ssa.OpAMD64VPADDD512, + ssa.OpAMD64VPADDQ512, + ssa.OpAMD64VPADDB512, + ssa.OpAMD64VADDSUBPS128, + ssa.OpAMD64VADDSUBPS256, + ssa.OpAMD64VADDSUBPD128, + ssa.OpAMD64VADDSUBPD256, + ssa.OpAMD64VANDPS128, + ssa.OpAMD64VANDPS256, + ssa.OpAMD64VANDPD128, + ssa.OpAMD64VANDPD256, + ssa.OpAMD64VPAND256, + ssa.OpAMD64VPAND128, + ssa.OpAMD64VANDPS512, + ssa.OpAMD64VANDPD512, + ssa.OpAMD64VPANDD512, + ssa.OpAMD64VPANDQ512, + ssa.OpAMD64VANDNPS128, + ssa.OpAMD64VANDNPS256, + ssa.OpAMD64VANDNPD128, + ssa.OpAMD64VANDNPD256, + ssa.OpAMD64VPANDN256, + ssa.OpAMD64VPANDN128, + ssa.OpAMD64VANDNPS512, + ssa.OpAMD64VANDNPD512, + ssa.OpAMD64VPANDND512, + ssa.OpAMD64VPANDNQ512, + ssa.OpAMD64VPAVGW256, + ssa.OpAMD64VPAVGW128, + ssa.OpAMD64VPAVGB128, + ssa.OpAMD64VPAVGB256, + ssa.OpAMD64VPAVGW512, + ssa.OpAMD64VPAVGB512, + ssa.OpAMD64VDIVPS128, + ssa.OpAMD64VDIVPS256, + ssa.OpAMD64VDIVPD128, + ssa.OpAMD64VDIVPD256, + ssa.OpAMD64VDIVPS512, + ssa.OpAMD64VDIVPD512, + ssa.OpAMD64VPCMPEQW256, + ssa.OpAMD64VPCMPEQW128, + ssa.OpAMD64VPCMPEQD128, + ssa.OpAMD64VPCMPEQD256, + ssa.OpAMD64VPCMPEQQ128, + ssa.OpAMD64VPCMPEQQ256, + ssa.OpAMD64VPCMPEQB128, + ssa.OpAMD64VPCMPEQB256, + ssa.OpAMD64VPCMPGTW256, + ssa.OpAMD64VPCMPGTW128, + ssa.OpAMD64VPCMPGTD128, + ssa.OpAMD64VPCMPGTD256, + ssa.OpAMD64VPCMPGTQ256, + ssa.OpAMD64VPCMPGTB128, + ssa.OpAMD64VPCMPGTB256, + ssa.OpAMD64VMAXPS128, + ssa.OpAMD64VMAXPS256, + ssa.OpAMD64VMAXPD128, + ssa.OpAMD64VMAXPD256, + ssa.OpAMD64VPMAXSW256, + ssa.OpAMD64VPMAXSW128, + ssa.OpAMD64VPMAXSD128, + ssa.OpAMD64VPMAXSD256, + ssa.OpAMD64VPMAXSB128, + ssa.OpAMD64VPMAXSB256, + ssa.OpAMD64VPMAXUW256, + ssa.OpAMD64VPMAXUW128, + ssa.OpAMD64VPMAXUD128, + ssa.OpAMD64VPMAXUD256, + ssa.OpAMD64VPMAXUB128, + ssa.OpAMD64VPMAXUB256, + ssa.OpAMD64VMAXPS512, + ssa.OpAMD64VMAXPD512, + ssa.OpAMD64VPMAXSW512, + ssa.OpAMD64VPMAXSD512, + ssa.OpAMD64VPMAXSQ128, + ssa.OpAMD64VPMAXSQ256, + ssa.OpAMD64VPMAXSQ512, + ssa.OpAMD64VPMAXSB512, + ssa.OpAMD64VPMAXUW512, + ssa.OpAMD64VPMAXUD512, + ssa.OpAMD64VPMAXUQ128, + ssa.OpAMD64VPMAXUQ256, + ssa.OpAMD64VPMAXUQ512, + ssa.OpAMD64VPMAXUB512, + ssa.OpAMD64VMINPS128, + ssa.OpAMD64VMINPS256, + ssa.OpAMD64VMINPD128, + ssa.OpAMD64VMINPD256, + ssa.OpAMD64VPMINSW256, + ssa.OpAMD64VPMINSW128, + ssa.OpAMD64VPMINSD128, + ssa.OpAMD64VPMINSD256, + ssa.OpAMD64VPMINSB128, + ssa.OpAMD64VPMINSB256, + ssa.OpAMD64VPMINUW256, + ssa.OpAMD64VPMINUW128, + ssa.OpAMD64VPMINUD128, + ssa.OpAMD64VPMINUD256, + ssa.OpAMD64VPMINUB128, + ssa.OpAMD64VPMINUB256, + ssa.OpAMD64VMINPS512, + ssa.OpAMD64VMINPD512, + ssa.OpAMD64VPMINSW512, + ssa.OpAMD64VPMINSD512, + ssa.OpAMD64VPMINSQ128, + ssa.OpAMD64VPMINSQ256, + ssa.OpAMD64VPMINSQ512, + ssa.OpAMD64VPMINSB512, + ssa.OpAMD64VPMINUW512, + ssa.OpAMD64VPMINUD512, + ssa.OpAMD64VPMINUQ128, + ssa.OpAMD64VPMINUQ256, + ssa.OpAMD64VPMINUQ512, + ssa.OpAMD64VPMINUB512, + ssa.OpAMD64VMULPS128, + ssa.OpAMD64VMULPS256, + ssa.OpAMD64VMULPD128, + ssa.OpAMD64VMULPD256, + ssa.OpAMD64VMULPS512, + ssa.OpAMD64VMULPD512, + ssa.OpAMD64VSCALEFPS512, + ssa.OpAMD64VSCALEFPS128, + ssa.OpAMD64VSCALEFPS256, + ssa.OpAMD64VSCALEFPD128, + ssa.OpAMD64VSCALEFPD256, + ssa.OpAMD64VSCALEFPD512, + ssa.OpAMD64VPMULDQ128, + ssa.OpAMD64VPMULDQ256, + ssa.OpAMD64VPMULUDQ128, + ssa.OpAMD64VPMULUDQ256, + ssa.OpAMD64VPMULDQ512, + ssa.OpAMD64VPMULUDQ512, + ssa.OpAMD64VPMULHW256, + ssa.OpAMD64VPMULHW128, + ssa.OpAMD64VPMULHUW256, + ssa.OpAMD64VPMULHUW128, + ssa.OpAMD64VPMULHW512, + ssa.OpAMD64VPMULHUW512, + ssa.OpAMD64VPMULLW256, + ssa.OpAMD64VPMULLW128, + ssa.OpAMD64VPMULLD128, + ssa.OpAMD64VPMULLD256, + ssa.OpAMD64VPMULLW512, + ssa.OpAMD64VPMULLD512, + ssa.OpAMD64VPMULLQ128, + ssa.OpAMD64VPMULLQ256, + ssa.OpAMD64VPMULLQ512, + ssa.OpAMD64VORPS128, + ssa.OpAMD64VORPS256, + ssa.OpAMD64VORPD128, + ssa.OpAMD64VORPD256, + ssa.OpAMD64VPOR256, + ssa.OpAMD64VPOR128, + ssa.OpAMD64VORPS512, + ssa.OpAMD64VORPD512, + ssa.OpAMD64VPORD512, + ssa.OpAMD64VPORQ512, + ssa.OpAMD64VPMADDWD256, + ssa.OpAMD64VPMADDWD128, + ssa.OpAMD64VPMADDWD512, + ssa.OpAMD64VHADDPS128, + ssa.OpAMD64VHADDPS256, + ssa.OpAMD64VHADDPD128, + ssa.OpAMD64VHADDPD256, + ssa.OpAMD64VPHADDW256, + ssa.OpAMD64VPHADDW128, + ssa.OpAMD64VPHADDD128, + ssa.OpAMD64VPHADDD256, + ssa.OpAMD64VHSUBPS128, + ssa.OpAMD64VHSUBPS256, + ssa.OpAMD64VHSUBPD128, + ssa.OpAMD64VHSUBPD256, + ssa.OpAMD64VPHSUBW256, + ssa.OpAMD64VPHSUBW128, + ssa.OpAMD64VPHSUBD128, + ssa.OpAMD64VPHSUBD256, + ssa.OpAMD64VPADDSW256, + ssa.OpAMD64VPADDSW128, + ssa.OpAMD64VPADDSB128, + ssa.OpAMD64VPADDSB256, + ssa.OpAMD64VPADDSW512, + ssa.OpAMD64VPADDSB512, + ssa.OpAMD64VPHADDSW256, + ssa.OpAMD64VPHADDSW128, + ssa.OpAMD64VPHSUBSW256, + ssa.OpAMD64VPHSUBSW128, + ssa.OpAMD64VPSUBSW256, + ssa.OpAMD64VPSUBSW128, + ssa.OpAMD64VPSUBSB128, + ssa.OpAMD64VPSUBSB256, + ssa.OpAMD64VPSUBSW512, + ssa.OpAMD64VPSUBSB512, + ssa.OpAMD64VPMADDUBSW128, + ssa.OpAMD64VPMADDUBSW256, + ssa.OpAMD64VPMADDUBSW512, + ssa.OpAMD64VPSIGNW256, + ssa.OpAMD64VPSIGNW128, + ssa.OpAMD64VPSIGND128, + ssa.OpAMD64VPSIGND256, + ssa.OpAMD64VPSIGNB128, + ssa.OpAMD64VPSIGNB256, + ssa.OpAMD64VPSUBW256, + ssa.OpAMD64VPSUBW128, + ssa.OpAMD64VPSUBD128, + ssa.OpAMD64VPSUBD256, + ssa.OpAMD64VPSUBQ128, + ssa.OpAMD64VPSUBQ256, + ssa.OpAMD64VPSUBB128, + ssa.OpAMD64VPSUBB256, + ssa.OpAMD64VPSUBW512, + ssa.OpAMD64VPSUBD512, + ssa.OpAMD64VPSUBQ512, + ssa.OpAMD64VPSUBB512, + ssa.OpAMD64VXORPS128, + ssa.OpAMD64VXORPS256, + ssa.OpAMD64VXORPD128, + ssa.OpAMD64VXORPD256, + ssa.OpAMD64VPXOR256, + ssa.OpAMD64VPXOR128, + ssa.OpAMD64VXORPS512, + ssa.OpAMD64VXORPD512, + ssa.OpAMD64VPXORD512, + ssa.OpAMD64VPXORQ512: + p = simdFp21(s, v) + + case ssa.OpAMD64VPCMPEQW512, + ssa.OpAMD64VPCMPEQD512, + ssa.OpAMD64VPCMPEQQ512, + ssa.OpAMD64VPCMPEQB512, + ssa.OpAMD64VPCMPGTW512, + ssa.OpAMD64VPCMPGTD512, + ssa.OpAMD64VPCMPGTQ128, + ssa.OpAMD64VPCMPGTQ512, + ssa.OpAMD64VPCMPGTB512: + p = simdFp2k1(s, v) + + case ssa.OpAMD64VADDPSMasked512, + ssa.OpAMD64VADDPSMasked128, + ssa.OpAMD64VADDPSMasked256, + ssa.OpAMD64VADDPDMasked128, + ssa.OpAMD64VADDPDMasked256, + ssa.OpAMD64VADDPDMasked512, + ssa.OpAMD64VPADDWMasked256, + ssa.OpAMD64VPADDWMasked512, + ssa.OpAMD64VPADDWMasked128, + ssa.OpAMD64VPADDDMasked512, + ssa.OpAMD64VPADDDMasked128, + ssa.OpAMD64VPADDDMasked256, + ssa.OpAMD64VPADDQMasked128, + ssa.OpAMD64VPADDQMasked256, + ssa.OpAMD64VPADDQMasked512, + ssa.OpAMD64VPADDBMasked128, + ssa.OpAMD64VPADDBMasked256, + ssa.OpAMD64VPADDBMasked512, + ssa.OpAMD64VANDPSMasked512, + ssa.OpAMD64VANDPSMasked128, + ssa.OpAMD64VANDPSMasked256, + ssa.OpAMD64VANDPDMasked128, + ssa.OpAMD64VANDPDMasked256, + ssa.OpAMD64VANDPDMasked512, + ssa.OpAMD64VPANDDMasked512, + ssa.OpAMD64VPANDDMasked128, + ssa.OpAMD64VPANDDMasked256, + ssa.OpAMD64VPANDQMasked128, + ssa.OpAMD64VPANDQMasked256, + ssa.OpAMD64VPANDQMasked512, + ssa.OpAMD64VANDNPSMasked512, + ssa.OpAMD64VANDNPSMasked128, + ssa.OpAMD64VANDNPSMasked256, + ssa.OpAMD64VANDNPDMasked128, + ssa.OpAMD64VANDNPDMasked256, + ssa.OpAMD64VANDNPDMasked512, + ssa.OpAMD64VPANDNDMasked512, + ssa.OpAMD64VPANDNDMasked128, + ssa.OpAMD64VPANDNDMasked256, + ssa.OpAMD64VPANDNQMasked128, + ssa.OpAMD64VPANDNQMasked256, + ssa.OpAMD64VPANDNQMasked512, + ssa.OpAMD64VPAVGWMasked256, + ssa.OpAMD64VPAVGWMasked512, + ssa.OpAMD64VPAVGWMasked128, + ssa.OpAMD64VPAVGBMasked128, + ssa.OpAMD64VPAVGBMasked256, + ssa.OpAMD64VPAVGBMasked512, + ssa.OpAMD64VDIVPSMasked512, + ssa.OpAMD64VDIVPSMasked128, + ssa.OpAMD64VDIVPSMasked256, + ssa.OpAMD64VDIVPDMasked128, + ssa.OpAMD64VDIVPDMasked256, + ssa.OpAMD64VDIVPDMasked512, + ssa.OpAMD64VMAXPSMasked512, + ssa.OpAMD64VMAXPSMasked128, + ssa.OpAMD64VMAXPSMasked256, + ssa.OpAMD64VMAXPDMasked128, + ssa.OpAMD64VMAXPDMasked256, + ssa.OpAMD64VMAXPDMasked512, + ssa.OpAMD64VPMAXSWMasked256, + ssa.OpAMD64VPMAXSWMasked512, + ssa.OpAMD64VPMAXSWMasked128, + ssa.OpAMD64VPMAXSDMasked512, + ssa.OpAMD64VPMAXSDMasked128, + ssa.OpAMD64VPMAXSDMasked256, + ssa.OpAMD64VPMAXSQMasked128, + ssa.OpAMD64VPMAXSQMasked256, + ssa.OpAMD64VPMAXSQMasked512, + ssa.OpAMD64VPMAXSBMasked128, + ssa.OpAMD64VPMAXSBMasked256, + ssa.OpAMD64VPMAXSBMasked512, + ssa.OpAMD64VPMAXUWMasked256, + ssa.OpAMD64VPMAXUWMasked512, + ssa.OpAMD64VPMAXUWMasked128, + ssa.OpAMD64VPMAXUDMasked512, + ssa.OpAMD64VPMAXUDMasked128, + ssa.OpAMD64VPMAXUDMasked256, + ssa.OpAMD64VPMAXUQMasked128, + ssa.OpAMD64VPMAXUQMasked256, + ssa.OpAMD64VPMAXUQMasked512, + ssa.OpAMD64VPMAXUBMasked128, + ssa.OpAMD64VPMAXUBMasked256, + ssa.OpAMD64VPMAXUBMasked512, + ssa.OpAMD64VMINPSMasked512, + ssa.OpAMD64VMINPSMasked128, + ssa.OpAMD64VMINPSMasked256, + ssa.OpAMD64VMINPDMasked128, + ssa.OpAMD64VMINPDMasked256, + ssa.OpAMD64VMINPDMasked512, + ssa.OpAMD64VPMINSWMasked256, + ssa.OpAMD64VPMINSWMasked512, + ssa.OpAMD64VPMINSWMasked128, + ssa.OpAMD64VPMINSDMasked512, + ssa.OpAMD64VPMINSDMasked128, + ssa.OpAMD64VPMINSDMasked256, + ssa.OpAMD64VPMINSQMasked128, + ssa.OpAMD64VPMINSQMasked256, + ssa.OpAMD64VPMINSQMasked512, + ssa.OpAMD64VPMINSBMasked128, + ssa.OpAMD64VPMINSBMasked256, + ssa.OpAMD64VPMINSBMasked512, + ssa.OpAMD64VPMINUWMasked256, + ssa.OpAMD64VPMINUWMasked512, + ssa.OpAMD64VPMINUWMasked128, + ssa.OpAMD64VPMINUDMasked512, + ssa.OpAMD64VPMINUDMasked128, + ssa.OpAMD64VPMINUDMasked256, + ssa.OpAMD64VPMINUQMasked128, + ssa.OpAMD64VPMINUQMasked256, + ssa.OpAMD64VPMINUQMasked512, + ssa.OpAMD64VPMINUBMasked128, + ssa.OpAMD64VPMINUBMasked256, + ssa.OpAMD64VPMINUBMasked512, + ssa.OpAMD64VMULPSMasked512, + ssa.OpAMD64VMULPSMasked128, + ssa.OpAMD64VMULPSMasked256, + ssa.OpAMD64VMULPDMasked128, + ssa.OpAMD64VMULPDMasked256, + ssa.OpAMD64VMULPDMasked512, + ssa.OpAMD64VSCALEFPSMasked512, + ssa.OpAMD64VSCALEFPSMasked128, + ssa.OpAMD64VSCALEFPSMasked256, + ssa.OpAMD64VSCALEFPDMasked128, + ssa.OpAMD64VSCALEFPDMasked256, + ssa.OpAMD64VSCALEFPDMasked512, + ssa.OpAMD64VPMULDQMasked128, + ssa.OpAMD64VPMULDQMasked256, + ssa.OpAMD64VPMULDQMasked512, + ssa.OpAMD64VPMULUDQMasked128, + ssa.OpAMD64VPMULUDQMasked256, + ssa.OpAMD64VPMULUDQMasked512, + ssa.OpAMD64VPMULHWMasked256, + ssa.OpAMD64VPMULHWMasked512, + ssa.OpAMD64VPMULHWMasked128, + ssa.OpAMD64VPMULHUWMasked256, + ssa.OpAMD64VPMULHUWMasked512, + ssa.OpAMD64VPMULHUWMasked128, + ssa.OpAMD64VPMULLWMasked256, + ssa.OpAMD64VPMULLWMasked512, + ssa.OpAMD64VPMULLWMasked128, + ssa.OpAMD64VPMULLDMasked512, + ssa.OpAMD64VPMULLDMasked128, + ssa.OpAMD64VPMULLDMasked256, + ssa.OpAMD64VPMULLQMasked128, + ssa.OpAMD64VPMULLQMasked256, + ssa.OpAMD64VPMULLQMasked512, + ssa.OpAMD64VORPSMasked512, + ssa.OpAMD64VORPSMasked128, + ssa.OpAMD64VORPSMasked256, + ssa.OpAMD64VORPDMasked128, + ssa.OpAMD64VORPDMasked256, + ssa.OpAMD64VORPDMasked512, + ssa.OpAMD64VPORDMasked512, + ssa.OpAMD64VPORDMasked128, + ssa.OpAMD64VPORDMasked256, + ssa.OpAMD64VPORQMasked128, + ssa.OpAMD64VPORQMasked256, + ssa.OpAMD64VPORQMasked512, + ssa.OpAMD64VPMADDWDMasked256, + ssa.OpAMD64VPMADDWDMasked512, + ssa.OpAMD64VPMADDWDMasked128, + ssa.OpAMD64VPADDSWMasked256, + ssa.OpAMD64VPADDSWMasked512, + ssa.OpAMD64VPADDSWMasked128, + ssa.OpAMD64VPADDSBMasked128, + ssa.OpAMD64VPADDSBMasked256, + ssa.OpAMD64VPADDSBMasked512, + ssa.OpAMD64VPSUBSWMasked256, + ssa.OpAMD64VPSUBSWMasked512, + ssa.OpAMD64VPSUBSWMasked128, + ssa.OpAMD64VPSUBSBMasked128, + ssa.OpAMD64VPSUBSBMasked256, + ssa.OpAMD64VPSUBSBMasked512, + ssa.OpAMD64VPMADDUBSWMasked256, + ssa.OpAMD64VPMADDUBSWMasked512, + ssa.OpAMD64VPMADDUBSWMasked128, + ssa.OpAMD64VPSUBWMasked256, + ssa.OpAMD64VPSUBWMasked512, + ssa.OpAMD64VPSUBWMasked128, + ssa.OpAMD64VPSUBDMasked512, + ssa.OpAMD64VPSUBDMasked128, + ssa.OpAMD64VPSUBDMasked256, + ssa.OpAMD64VPSUBQMasked128, + ssa.OpAMD64VPSUBQMasked256, + ssa.OpAMD64VPSUBQMasked512, + ssa.OpAMD64VPSUBBMasked128, + ssa.OpAMD64VPSUBBMasked256, + ssa.OpAMD64VPSUBBMasked512, + ssa.OpAMD64VXORPSMasked512, + ssa.OpAMD64VXORPSMasked128, + ssa.OpAMD64VXORPSMasked256, + ssa.OpAMD64VXORPDMasked128, + ssa.OpAMD64VXORPDMasked256, + ssa.OpAMD64VXORPDMasked512, + ssa.OpAMD64VPXORDMasked512, + ssa.OpAMD64VPXORDMasked128, + ssa.OpAMD64VPXORDMasked256, + ssa.OpAMD64VPXORQMasked128, + ssa.OpAMD64VPXORQMasked256, + ssa.OpAMD64VPXORQMasked512: + p = simdFp2k1fp1(s, v) + + case ssa.OpAMD64VPCMPEQWMasked256, + ssa.OpAMD64VPCMPEQWMasked512, + ssa.OpAMD64VPCMPEQWMasked128, + ssa.OpAMD64VPCMPEQDMasked512, + ssa.OpAMD64VPCMPEQDMasked128, + ssa.OpAMD64VPCMPEQDMasked256, + ssa.OpAMD64VPCMPEQQMasked128, + ssa.OpAMD64VPCMPEQQMasked256, + ssa.OpAMD64VPCMPEQQMasked512, + ssa.OpAMD64VPCMPEQBMasked128, + ssa.OpAMD64VPCMPEQBMasked256, + ssa.OpAMD64VPCMPEQBMasked512, + ssa.OpAMD64VPCMPGTWMasked256, + ssa.OpAMD64VPCMPGTWMasked512, + ssa.OpAMD64VPCMPGTWMasked128, + ssa.OpAMD64VPCMPGTDMasked512, + ssa.OpAMD64VPCMPGTDMasked128, + ssa.OpAMD64VPCMPGTDMasked256, + ssa.OpAMD64VPCMPGTQMasked128, + ssa.OpAMD64VPCMPGTQMasked256, + ssa.OpAMD64VPCMPGTQMasked512, + ssa.OpAMD64VPCMPGTBMasked128, + ssa.OpAMD64VPCMPGTBMasked256, + ssa.OpAMD64VPCMPGTBMasked512: + p = simdFp2k1k1(s, v) + + case ssa.OpAMD64VPABSWMasked256, + ssa.OpAMD64VPABSWMasked512, + ssa.OpAMD64VPABSWMasked128, + ssa.OpAMD64VPABSDMasked512, + ssa.OpAMD64VPABSDMasked128, + ssa.OpAMD64VPABSDMasked256, + ssa.OpAMD64VPABSQMasked128, + ssa.OpAMD64VPABSQMasked256, + ssa.OpAMD64VPABSQMasked512, + ssa.OpAMD64VPABSBMasked128, + ssa.OpAMD64VPABSBMasked256, + ssa.OpAMD64VPABSBMasked512, + ssa.OpAMD64VRCP14PSMasked512, + ssa.OpAMD64VRCP14PSMasked128, + ssa.OpAMD64VRCP14PSMasked256, + ssa.OpAMD64VRCP14PDMasked128, + ssa.OpAMD64VRCP14PDMasked256, + ssa.OpAMD64VRCP14PDMasked512, + ssa.OpAMD64VRSQRT14PSMasked512, + ssa.OpAMD64VRSQRT14PSMasked128, + ssa.OpAMD64VRSQRT14PSMasked256, + ssa.OpAMD64VRSQRT14PDMasked128, + ssa.OpAMD64VRSQRT14PDMasked256, + ssa.OpAMD64VRSQRT14PDMasked512, + ssa.OpAMD64VPOPCNTWMasked256, + ssa.OpAMD64VPOPCNTWMasked512, + ssa.OpAMD64VPOPCNTWMasked128, + ssa.OpAMD64VPOPCNTDMasked512, + ssa.OpAMD64VPOPCNTDMasked128, + ssa.OpAMD64VPOPCNTDMasked256, + ssa.OpAMD64VPOPCNTQMasked128, + ssa.OpAMD64VPOPCNTQMasked256, + ssa.OpAMD64VPOPCNTQMasked512, + ssa.OpAMD64VPOPCNTBMasked128, + ssa.OpAMD64VPOPCNTBMasked256, + ssa.OpAMD64VPOPCNTBMasked512, + ssa.OpAMD64VSQRTPSMasked512, + ssa.OpAMD64VSQRTPSMasked128, + ssa.OpAMD64VSQRTPSMasked256, + ssa.OpAMD64VSQRTPDMasked128, + ssa.OpAMD64VSQRTPDMasked256, + ssa.OpAMD64VSQRTPDMasked512: + p = simdFp1k1fp1(s, v) + + case ssa.OpAMD64VROUNDPS128, + ssa.OpAMD64VROUNDPS256, + ssa.OpAMD64VROUNDPD128, + ssa.OpAMD64VROUNDPD256, + ssa.OpAMD64VRNDSCALEPS512, + ssa.OpAMD64VRNDSCALEPS128, + ssa.OpAMD64VRNDSCALEPS256, + ssa.OpAMD64VRNDSCALEPD128, + ssa.OpAMD64VRNDSCALEPD256, + ssa.OpAMD64VRNDSCALEPD512, + ssa.OpAMD64VREDUCEPS512, + ssa.OpAMD64VREDUCEPS128, + ssa.OpAMD64VREDUCEPS256, + ssa.OpAMD64VREDUCEPD128, + ssa.OpAMD64VREDUCEPD256, + ssa.OpAMD64VREDUCEPD512: + p = simdFp11Imm8(s, v) + + case ssa.OpAMD64VRNDSCALEPSMasked512, + ssa.OpAMD64VRNDSCALEPSMasked128, + ssa.OpAMD64VRNDSCALEPSMasked256, + ssa.OpAMD64VRNDSCALEPDMasked128, + ssa.OpAMD64VRNDSCALEPDMasked256, + ssa.OpAMD64VRNDSCALEPDMasked512, + ssa.OpAMD64VREDUCEPSMasked512, + ssa.OpAMD64VREDUCEPSMasked128, + ssa.OpAMD64VREDUCEPSMasked256, + ssa.OpAMD64VREDUCEPDMasked128, + ssa.OpAMD64VREDUCEPDMasked256, + ssa.OpAMD64VREDUCEPDMasked512: + p = simdFp1k1fp1Imm8(s, v) + + case ssa.OpAMD64VDPPD128, + ssa.OpAMD64VCMPPS128, + ssa.OpAMD64VCMPPS256, + ssa.OpAMD64VCMPPD128, + ssa.OpAMD64VCMPPD256: + p = simdFp21Imm8(s, v) + + case ssa.OpAMD64VCMPPS512, + ssa.OpAMD64VCMPPD512, + ssa.OpAMD64VPCMPUW256, + ssa.OpAMD64VPCMPUW512, + ssa.OpAMD64VPCMPUW128, + ssa.OpAMD64VPCMPUD512, + ssa.OpAMD64VPCMPUD128, + ssa.OpAMD64VPCMPUD256, + ssa.OpAMD64VPCMPUQ128, + ssa.OpAMD64VPCMPUQ256, + ssa.OpAMD64VPCMPUQ512, + ssa.OpAMD64VPCMPUB128, + ssa.OpAMD64VPCMPUB256, + ssa.OpAMD64VPCMPUB512, + ssa.OpAMD64VPCMPW256, + ssa.OpAMD64VPCMPW512, + ssa.OpAMD64VPCMPW128, + ssa.OpAMD64VPCMPD512, + ssa.OpAMD64VPCMPD128, + ssa.OpAMD64VPCMPD256, + ssa.OpAMD64VPCMPQ128, + ssa.OpAMD64VPCMPQ256, + ssa.OpAMD64VPCMPQ512, + ssa.OpAMD64VPCMPB128, + ssa.OpAMD64VPCMPB256, + ssa.OpAMD64VPCMPB512: + p = simdFp2k1Imm8(s, v) + + case ssa.OpAMD64VCMPPSMasked512, + ssa.OpAMD64VCMPPSMasked128, + ssa.OpAMD64VCMPPSMasked256, + ssa.OpAMD64VCMPPDMasked128, + ssa.OpAMD64VCMPPDMasked256, + ssa.OpAMD64VCMPPDMasked512, + ssa.OpAMD64VPCMPUWMasked256, + ssa.OpAMD64VPCMPUWMasked512, + ssa.OpAMD64VPCMPUWMasked128, + ssa.OpAMD64VPCMPUDMasked512, + ssa.OpAMD64VPCMPUDMasked128, + ssa.OpAMD64VPCMPUDMasked256, + ssa.OpAMD64VPCMPUQMasked128, + ssa.OpAMD64VPCMPUQMasked256, + ssa.OpAMD64VPCMPUQMasked512, + ssa.OpAMD64VPCMPUBMasked128, + ssa.OpAMD64VPCMPUBMasked256, + ssa.OpAMD64VPCMPUBMasked512, + ssa.OpAMD64VPCMPWMasked256, + ssa.OpAMD64VPCMPWMasked512, + ssa.OpAMD64VPCMPWMasked128, + ssa.OpAMD64VPCMPDMasked512, + ssa.OpAMD64VPCMPDMasked128, + ssa.OpAMD64VPCMPDMasked256, + ssa.OpAMD64VPCMPQMasked128, + ssa.OpAMD64VPCMPQMasked256, + ssa.OpAMD64VPCMPQMasked512, + ssa.OpAMD64VPCMPBMasked128, + ssa.OpAMD64VPCMPBMasked256, + ssa.OpAMD64VPCMPBMasked512: + p = simdFp2k1k1Imm8(s, v) + + case ssa.OpAMD64VFMADD132PS512, + ssa.OpAMD64VFMADD132PS128, + ssa.OpAMD64VFMADD132PS256, + ssa.OpAMD64VFMADD132PD128, + ssa.OpAMD64VFMADD132PD256, + ssa.OpAMD64VFMADD132PD512, + ssa.OpAMD64VFMADD213PS512, + ssa.OpAMD64VFMADD213PS128, + ssa.OpAMD64VFMADD213PS256, + ssa.OpAMD64VFMADD213PD128, + ssa.OpAMD64VFMADD213PD256, + ssa.OpAMD64VFMADD213PD512, + ssa.OpAMD64VFMADD231PS512, + ssa.OpAMD64VFMADD231PS128, + ssa.OpAMD64VFMADD231PS256, + ssa.OpAMD64VFMADD231PD128, + ssa.OpAMD64VFMADD231PD256, + ssa.OpAMD64VFMADD231PD512, + ssa.OpAMD64VFMADDSUB132PS512, + ssa.OpAMD64VFMADDSUB132PS128, + ssa.OpAMD64VFMADDSUB132PS256, + ssa.OpAMD64VFMADDSUB132PD128, + ssa.OpAMD64VFMADDSUB132PD256, + ssa.OpAMD64VFMADDSUB132PD512, + ssa.OpAMD64VFMADDSUB213PS512, + ssa.OpAMD64VFMADDSUB213PS128, + ssa.OpAMD64VFMADDSUB213PS256, + ssa.OpAMD64VFMADDSUB213PD128, + ssa.OpAMD64VFMADDSUB213PD256, + ssa.OpAMD64VFMADDSUB213PD512, + ssa.OpAMD64VFMADDSUB231PS512, + ssa.OpAMD64VFMADDSUB231PS128, + ssa.OpAMD64VFMADDSUB231PS256, + ssa.OpAMD64VFMADDSUB231PD128, + ssa.OpAMD64VFMADDSUB231PD256, + ssa.OpAMD64VFMADDSUB231PD512, + ssa.OpAMD64VFMSUB132PS512, + ssa.OpAMD64VFMSUB132PS128, + ssa.OpAMD64VFMSUB132PS256, + ssa.OpAMD64VFMSUB132PD128, + ssa.OpAMD64VFMSUB132PD256, + ssa.OpAMD64VFMSUB132PD512, + ssa.OpAMD64VFMSUB213PS512, + ssa.OpAMD64VFMSUB213PS128, + ssa.OpAMD64VFMSUB213PS256, + ssa.OpAMD64VFMSUB213PD128, + ssa.OpAMD64VFMSUB213PD256, + ssa.OpAMD64VFMSUB213PD512, + ssa.OpAMD64VFMSUB231PS512, + ssa.OpAMD64VFMSUB231PS128, + ssa.OpAMD64VFMSUB231PS256, + ssa.OpAMD64VFMSUB231PD128, + ssa.OpAMD64VFMSUB231PD256, + ssa.OpAMD64VFMSUB231PD512, + ssa.OpAMD64VFMSUBADD132PS512, + ssa.OpAMD64VFMSUBADD132PS128, + ssa.OpAMD64VFMSUBADD132PS256, + ssa.OpAMD64VFMSUBADD132PD128, + ssa.OpAMD64VFMSUBADD132PD256, + ssa.OpAMD64VFMSUBADD132PD512, + ssa.OpAMD64VFMSUBADD213PS512, + ssa.OpAMD64VFMSUBADD213PS128, + ssa.OpAMD64VFMSUBADD213PS256, + ssa.OpAMD64VFMSUBADD213PD128, + ssa.OpAMD64VFMSUBADD213PD256, + ssa.OpAMD64VFMSUBADD213PD512, + ssa.OpAMD64VFMSUBADD231PS512, + ssa.OpAMD64VFMSUBADD231PS128, + ssa.OpAMD64VFMSUBADD231PS256, + ssa.OpAMD64VFMSUBADD231PD128, + ssa.OpAMD64VFMSUBADD231PD256, + ssa.OpAMD64VFMSUBADD231PD512, + ssa.OpAMD64VFNMADD132PS512, + ssa.OpAMD64VFNMADD132PS128, + ssa.OpAMD64VFNMADD132PS256, + ssa.OpAMD64VFNMADD132PD128, + ssa.OpAMD64VFNMADD132PD256, + ssa.OpAMD64VFNMADD132PD512, + ssa.OpAMD64VFNMADD213PS512, + ssa.OpAMD64VFNMADD213PS128, + ssa.OpAMD64VFNMADD213PS256, + ssa.OpAMD64VFNMADD213PD128, + ssa.OpAMD64VFNMADD213PD256, + ssa.OpAMD64VFNMADD213PD512, + ssa.OpAMD64VFNMADD231PS512, + ssa.OpAMD64VFNMADD231PS128, + ssa.OpAMD64VFNMADD231PS256, + ssa.OpAMD64VFNMADD231PD128, + ssa.OpAMD64VFNMADD231PD256, + ssa.OpAMD64VFNMADD231PD512, + ssa.OpAMD64VFNMSUB132PS512, + ssa.OpAMD64VFNMSUB132PS128, + ssa.OpAMD64VFNMSUB132PS256, + ssa.OpAMD64VFNMSUB132PD128, + ssa.OpAMD64VFNMSUB132PD256, + ssa.OpAMD64VFNMSUB132PD512, + ssa.OpAMD64VFNMSUB213PS512, + ssa.OpAMD64VFNMSUB213PS128, + ssa.OpAMD64VFNMSUB213PS256, + ssa.OpAMD64VFNMSUB213PD128, + ssa.OpAMD64VFNMSUB213PD256, + ssa.OpAMD64VFNMSUB213PD512, + ssa.OpAMD64VFNMSUB231PS512, + ssa.OpAMD64VFNMSUB231PS128, + ssa.OpAMD64VFNMSUB231PS256, + ssa.OpAMD64VFNMSUB231PD128, + ssa.OpAMD64VFNMSUB231PD256, + ssa.OpAMD64VFNMSUB231PD512, + ssa.OpAMD64VPDPWSSD128, + ssa.OpAMD64VPDPWSSD256, + ssa.OpAMD64VPDPWSSD512, + ssa.OpAMD64VPDPWSSDS128, + ssa.OpAMD64VPDPWSSDS256, + ssa.OpAMD64VPDPWSSDS512, + ssa.OpAMD64VPDPBUSDS128, + ssa.OpAMD64VPDPBUSDS256, + ssa.OpAMD64VPDPBUSDS512, + ssa.OpAMD64VPDPBUSD128, + ssa.OpAMD64VPDPBUSD256, + ssa.OpAMD64VPDPBUSD512: + p = simdFp31ResultInArg0(s, v) + + case ssa.OpAMD64VFMADD132PSMasked512, + ssa.OpAMD64VFMADD132PSMasked128, + ssa.OpAMD64VFMADD132PSMasked256, + ssa.OpAMD64VFMADD132PDMasked128, + ssa.OpAMD64VFMADD132PDMasked256, + ssa.OpAMD64VFMADD132PDMasked512, + ssa.OpAMD64VFMADD213PSMasked512, + ssa.OpAMD64VFMADD213PSMasked128, + ssa.OpAMD64VFMADD213PSMasked256, + ssa.OpAMD64VFMADD213PDMasked128, + ssa.OpAMD64VFMADD213PDMasked256, + ssa.OpAMD64VFMADD213PDMasked512, + ssa.OpAMD64VFMADD231PSMasked512, + ssa.OpAMD64VFMADD231PSMasked128, + ssa.OpAMD64VFMADD231PSMasked256, + ssa.OpAMD64VFMADD231PDMasked128, + ssa.OpAMD64VFMADD231PDMasked256, + ssa.OpAMD64VFMADD231PDMasked512, + ssa.OpAMD64VFMADDSUB132PSMasked512, + ssa.OpAMD64VFMADDSUB132PSMasked128, + ssa.OpAMD64VFMADDSUB132PSMasked256, + ssa.OpAMD64VFMADDSUB132PDMasked128, + ssa.OpAMD64VFMADDSUB132PDMasked256, + ssa.OpAMD64VFMADDSUB132PDMasked512, + ssa.OpAMD64VFMADDSUB213PSMasked512, + ssa.OpAMD64VFMADDSUB213PSMasked128, + ssa.OpAMD64VFMADDSUB213PSMasked256, + ssa.OpAMD64VFMADDSUB213PDMasked128, + ssa.OpAMD64VFMADDSUB213PDMasked256, + ssa.OpAMD64VFMADDSUB213PDMasked512, + ssa.OpAMD64VFMADDSUB231PSMasked512, + ssa.OpAMD64VFMADDSUB231PSMasked128, + ssa.OpAMD64VFMADDSUB231PSMasked256, + ssa.OpAMD64VFMADDSUB231PDMasked128, + ssa.OpAMD64VFMADDSUB231PDMasked256, + ssa.OpAMD64VFMADDSUB231PDMasked512, + ssa.OpAMD64VFMSUB132PSMasked512, + ssa.OpAMD64VFMSUB132PSMasked128, + ssa.OpAMD64VFMSUB132PSMasked256, + ssa.OpAMD64VFMSUB132PDMasked128, + ssa.OpAMD64VFMSUB132PDMasked256, + ssa.OpAMD64VFMSUB132PDMasked512, + ssa.OpAMD64VFMSUB213PSMasked512, + ssa.OpAMD64VFMSUB213PSMasked128, + ssa.OpAMD64VFMSUB213PSMasked256, + ssa.OpAMD64VFMSUB213PDMasked128, + ssa.OpAMD64VFMSUB213PDMasked256, + ssa.OpAMD64VFMSUB213PDMasked512, + ssa.OpAMD64VFMSUB231PSMasked512, + ssa.OpAMD64VFMSUB231PSMasked128, + ssa.OpAMD64VFMSUB231PSMasked256, + ssa.OpAMD64VFMSUB231PDMasked128, + ssa.OpAMD64VFMSUB231PDMasked256, + ssa.OpAMD64VFMSUB231PDMasked512, + ssa.OpAMD64VFMSUBADD132PSMasked512, + ssa.OpAMD64VFMSUBADD132PSMasked128, + ssa.OpAMD64VFMSUBADD132PSMasked256, + ssa.OpAMD64VFMSUBADD132PDMasked128, + ssa.OpAMD64VFMSUBADD132PDMasked256, + ssa.OpAMD64VFMSUBADD132PDMasked512, + ssa.OpAMD64VFMSUBADD213PSMasked512, + ssa.OpAMD64VFMSUBADD213PSMasked128, + ssa.OpAMD64VFMSUBADD213PSMasked256, + ssa.OpAMD64VFMSUBADD213PDMasked128, + ssa.OpAMD64VFMSUBADD213PDMasked256, + ssa.OpAMD64VFMSUBADD213PDMasked512, + ssa.OpAMD64VFMSUBADD231PSMasked512, + ssa.OpAMD64VFMSUBADD231PSMasked128, + ssa.OpAMD64VFMSUBADD231PSMasked256, + ssa.OpAMD64VFMSUBADD231PDMasked128, + ssa.OpAMD64VFMSUBADD231PDMasked256, + ssa.OpAMD64VFMSUBADD231PDMasked512, + ssa.OpAMD64VFNMADD132PSMasked512, + ssa.OpAMD64VFNMADD132PSMasked128, + ssa.OpAMD64VFNMADD132PSMasked256, + ssa.OpAMD64VFNMADD132PDMasked128, + ssa.OpAMD64VFNMADD132PDMasked256, + ssa.OpAMD64VFNMADD132PDMasked512, + ssa.OpAMD64VFNMADD213PSMasked512, + ssa.OpAMD64VFNMADD213PSMasked128, + ssa.OpAMD64VFNMADD213PSMasked256, + ssa.OpAMD64VFNMADD213PDMasked128, + ssa.OpAMD64VFNMADD213PDMasked256, + ssa.OpAMD64VFNMADD213PDMasked512, + ssa.OpAMD64VFNMADD231PSMasked512, + ssa.OpAMD64VFNMADD231PSMasked128, + ssa.OpAMD64VFNMADD231PSMasked256, + ssa.OpAMD64VFNMADD231PDMasked128, + ssa.OpAMD64VFNMADD231PDMasked256, + ssa.OpAMD64VFNMADD231PDMasked512, + ssa.OpAMD64VFNMSUB132PSMasked512, + ssa.OpAMD64VFNMSUB132PSMasked128, + ssa.OpAMD64VFNMSUB132PSMasked256, + ssa.OpAMD64VFNMSUB132PDMasked128, + ssa.OpAMD64VFNMSUB132PDMasked256, + ssa.OpAMD64VFNMSUB132PDMasked512, + ssa.OpAMD64VFNMSUB213PSMasked512, + ssa.OpAMD64VFNMSUB213PSMasked128, + ssa.OpAMD64VFNMSUB213PSMasked256, + ssa.OpAMD64VFNMSUB213PDMasked128, + ssa.OpAMD64VFNMSUB213PDMasked256, + ssa.OpAMD64VFNMSUB213PDMasked512, + ssa.OpAMD64VFNMSUB231PSMasked512, + ssa.OpAMD64VFNMSUB231PSMasked128, + ssa.OpAMD64VFNMSUB231PSMasked256, + ssa.OpAMD64VFNMSUB231PDMasked128, + ssa.OpAMD64VFNMSUB231PDMasked256, + ssa.OpAMD64VFNMSUB231PDMasked512, + ssa.OpAMD64VPDPWSSDMasked512, + ssa.OpAMD64VPDPWSSDMasked128, + ssa.OpAMD64VPDPWSSDMasked256, + ssa.OpAMD64VPDPWSSDSMasked512, + ssa.OpAMD64VPDPWSSDSMasked128, + ssa.OpAMD64VPDPWSSDSMasked256, + ssa.OpAMD64VPDPBUSDSMasked512, + ssa.OpAMD64VPDPBUSDSMasked128, + ssa.OpAMD64VPDPBUSDSMasked256, + ssa.OpAMD64VPDPBUSDMasked512, + ssa.OpAMD64VPDPBUSDMasked128, + ssa.OpAMD64VPDPBUSDMasked256: + p = simdFp3k1fp1ResultInArg0(s, v) + + default: + // Unknown reg shape + return false + } + + // Masked operation are always compiled with zeroing. + switch v.Op { + case ssa.OpAMD64VPABSWMasked256, + ssa.OpAMD64VPABSWMasked512, + ssa.OpAMD64VPABSWMasked128, + ssa.OpAMD64VPABSDMasked512, + ssa.OpAMD64VPABSDMasked128, + ssa.OpAMD64VPABSDMasked256, + ssa.OpAMD64VPABSQMasked128, + ssa.OpAMD64VPABSQMasked256, + ssa.OpAMD64VPABSQMasked512, + ssa.OpAMD64VPABSBMasked128, + ssa.OpAMD64VPABSBMasked256, + ssa.OpAMD64VPABSBMasked512, + ssa.OpAMD64VADDPSMasked512, + ssa.OpAMD64VADDPSMasked128, + ssa.OpAMD64VADDPSMasked256, + ssa.OpAMD64VADDPDMasked128, + ssa.OpAMD64VADDPDMasked256, + ssa.OpAMD64VADDPDMasked512, + ssa.OpAMD64VPADDWMasked256, + ssa.OpAMD64VPADDWMasked512, + ssa.OpAMD64VPADDWMasked128, + ssa.OpAMD64VPADDDMasked512, + ssa.OpAMD64VPADDDMasked128, + ssa.OpAMD64VPADDDMasked256, + ssa.OpAMD64VPADDQMasked128, + ssa.OpAMD64VPADDQMasked256, + ssa.OpAMD64VPADDQMasked512, + ssa.OpAMD64VPADDBMasked128, + ssa.OpAMD64VPADDBMasked256, + ssa.OpAMD64VPADDBMasked512, + ssa.OpAMD64VANDPSMasked512, + ssa.OpAMD64VANDPSMasked128, + ssa.OpAMD64VANDPSMasked256, + ssa.OpAMD64VANDPDMasked128, + ssa.OpAMD64VANDPDMasked256, + ssa.OpAMD64VANDPDMasked512, + ssa.OpAMD64VPANDDMasked512, + ssa.OpAMD64VPANDDMasked128, + ssa.OpAMD64VPANDDMasked256, + ssa.OpAMD64VPANDQMasked128, + ssa.OpAMD64VPANDQMasked256, + ssa.OpAMD64VPANDQMasked512, + ssa.OpAMD64VANDNPSMasked512, + ssa.OpAMD64VANDNPSMasked128, + ssa.OpAMD64VANDNPSMasked256, + ssa.OpAMD64VANDNPDMasked128, + ssa.OpAMD64VANDNPDMasked256, + ssa.OpAMD64VANDNPDMasked512, + ssa.OpAMD64VPANDNDMasked512, + ssa.OpAMD64VPANDNDMasked128, + ssa.OpAMD64VPANDNDMasked256, + ssa.OpAMD64VPANDNQMasked128, + ssa.OpAMD64VPANDNQMasked256, + ssa.OpAMD64VPANDNQMasked512, + ssa.OpAMD64VRCP14PSMasked512, + ssa.OpAMD64VRCP14PSMasked128, + ssa.OpAMD64VRCP14PSMasked256, + ssa.OpAMD64VRCP14PDMasked128, + ssa.OpAMD64VRCP14PDMasked256, + ssa.OpAMD64VRCP14PDMasked512, + ssa.OpAMD64VRSQRT14PSMasked512, + ssa.OpAMD64VRSQRT14PSMasked128, + ssa.OpAMD64VRSQRT14PSMasked256, + ssa.OpAMD64VRSQRT14PDMasked128, + ssa.OpAMD64VRSQRT14PDMasked256, + ssa.OpAMD64VRSQRT14PDMasked512, + ssa.OpAMD64VPAVGWMasked256, + ssa.OpAMD64VPAVGWMasked512, + ssa.OpAMD64VPAVGWMasked128, + ssa.OpAMD64VPAVGBMasked128, + ssa.OpAMD64VPAVGBMasked256, + ssa.OpAMD64VPAVGBMasked512, + ssa.OpAMD64VRNDSCALEPSMasked512, + ssa.OpAMD64VRNDSCALEPSMasked128, + ssa.OpAMD64VRNDSCALEPSMasked256, + ssa.OpAMD64VRNDSCALEPDMasked128, + ssa.OpAMD64VRNDSCALEPDMasked256, + ssa.OpAMD64VRNDSCALEPDMasked512, + ssa.OpAMD64VREDUCEPSMasked512, + ssa.OpAMD64VREDUCEPSMasked128, + ssa.OpAMD64VREDUCEPSMasked256, + ssa.OpAMD64VREDUCEPDMasked128, + ssa.OpAMD64VREDUCEPDMasked256, + ssa.OpAMD64VREDUCEPDMasked512, + ssa.OpAMD64VDIVPSMasked512, + ssa.OpAMD64VDIVPSMasked128, + ssa.OpAMD64VDIVPSMasked256, + ssa.OpAMD64VDIVPDMasked128, + ssa.OpAMD64VDIVPDMasked256, + ssa.OpAMD64VDIVPDMasked512, + ssa.OpAMD64VFMADD132PSMasked512, + ssa.OpAMD64VFMADD132PSMasked128, + ssa.OpAMD64VFMADD132PSMasked256, + ssa.OpAMD64VFMADD132PDMasked128, + ssa.OpAMD64VFMADD132PDMasked256, + ssa.OpAMD64VFMADD132PDMasked512, + ssa.OpAMD64VFMADD213PSMasked512, + ssa.OpAMD64VFMADD213PSMasked128, + ssa.OpAMD64VFMADD213PSMasked256, + ssa.OpAMD64VFMADD213PDMasked128, + ssa.OpAMD64VFMADD213PDMasked256, + ssa.OpAMD64VFMADD213PDMasked512, + ssa.OpAMD64VFMADD231PSMasked512, + ssa.OpAMD64VFMADD231PSMasked128, + ssa.OpAMD64VFMADD231PSMasked256, + ssa.OpAMD64VFMADD231PDMasked128, + ssa.OpAMD64VFMADD231PDMasked256, + ssa.OpAMD64VFMADD231PDMasked512, + ssa.OpAMD64VFMADDSUB132PSMasked512, + ssa.OpAMD64VFMADDSUB132PSMasked128, + ssa.OpAMD64VFMADDSUB132PSMasked256, + ssa.OpAMD64VFMADDSUB132PDMasked128, + ssa.OpAMD64VFMADDSUB132PDMasked256, + ssa.OpAMD64VFMADDSUB132PDMasked512, + ssa.OpAMD64VFMADDSUB213PSMasked512, + ssa.OpAMD64VFMADDSUB213PSMasked128, + ssa.OpAMD64VFMADDSUB213PSMasked256, + ssa.OpAMD64VFMADDSUB213PDMasked128, + ssa.OpAMD64VFMADDSUB213PDMasked256, + ssa.OpAMD64VFMADDSUB213PDMasked512, + ssa.OpAMD64VFMADDSUB231PSMasked512, + ssa.OpAMD64VFMADDSUB231PSMasked128, + ssa.OpAMD64VFMADDSUB231PSMasked256, + ssa.OpAMD64VFMADDSUB231PDMasked128, + ssa.OpAMD64VFMADDSUB231PDMasked256, + ssa.OpAMD64VFMADDSUB231PDMasked512, + ssa.OpAMD64VFMSUB132PSMasked512, + ssa.OpAMD64VFMSUB132PSMasked128, + ssa.OpAMD64VFMSUB132PSMasked256, + ssa.OpAMD64VFMSUB132PDMasked128, + ssa.OpAMD64VFMSUB132PDMasked256, + ssa.OpAMD64VFMSUB132PDMasked512, + ssa.OpAMD64VFMSUB213PSMasked512, + ssa.OpAMD64VFMSUB213PSMasked128, + ssa.OpAMD64VFMSUB213PSMasked256, + ssa.OpAMD64VFMSUB213PDMasked128, + ssa.OpAMD64VFMSUB213PDMasked256, + ssa.OpAMD64VFMSUB213PDMasked512, + ssa.OpAMD64VFMSUB231PSMasked512, + ssa.OpAMD64VFMSUB231PSMasked128, + ssa.OpAMD64VFMSUB231PSMasked256, + ssa.OpAMD64VFMSUB231PDMasked128, + ssa.OpAMD64VFMSUB231PDMasked256, + ssa.OpAMD64VFMSUB231PDMasked512, + ssa.OpAMD64VFMSUBADD132PSMasked512, + ssa.OpAMD64VFMSUBADD132PSMasked128, + ssa.OpAMD64VFMSUBADD132PSMasked256, + ssa.OpAMD64VFMSUBADD132PDMasked128, + ssa.OpAMD64VFMSUBADD132PDMasked256, + ssa.OpAMD64VFMSUBADD132PDMasked512, + ssa.OpAMD64VFMSUBADD213PSMasked512, + ssa.OpAMD64VFMSUBADD213PSMasked128, + ssa.OpAMD64VFMSUBADD213PSMasked256, + ssa.OpAMD64VFMSUBADD213PDMasked128, + ssa.OpAMD64VFMSUBADD213PDMasked256, + ssa.OpAMD64VFMSUBADD213PDMasked512, + ssa.OpAMD64VFMSUBADD231PSMasked512, + ssa.OpAMD64VFMSUBADD231PSMasked128, + ssa.OpAMD64VFMSUBADD231PSMasked256, + ssa.OpAMD64VFMSUBADD231PDMasked128, + ssa.OpAMD64VFMSUBADD231PDMasked256, + ssa.OpAMD64VFMSUBADD231PDMasked512, + ssa.OpAMD64VFNMADD132PSMasked512, + ssa.OpAMD64VFNMADD132PSMasked128, + ssa.OpAMD64VFNMADD132PSMasked256, + ssa.OpAMD64VFNMADD132PDMasked128, + ssa.OpAMD64VFNMADD132PDMasked256, + ssa.OpAMD64VFNMADD132PDMasked512, + ssa.OpAMD64VFNMADD213PSMasked512, + ssa.OpAMD64VFNMADD213PSMasked128, + ssa.OpAMD64VFNMADD213PSMasked256, + ssa.OpAMD64VFNMADD213PDMasked128, + ssa.OpAMD64VFNMADD213PDMasked256, + ssa.OpAMD64VFNMADD213PDMasked512, + ssa.OpAMD64VFNMADD231PSMasked512, + ssa.OpAMD64VFNMADD231PSMasked128, + ssa.OpAMD64VFNMADD231PSMasked256, + ssa.OpAMD64VFNMADD231PDMasked128, + ssa.OpAMD64VFNMADD231PDMasked256, + ssa.OpAMD64VFNMADD231PDMasked512, + ssa.OpAMD64VFNMSUB132PSMasked512, + ssa.OpAMD64VFNMSUB132PSMasked128, + ssa.OpAMD64VFNMSUB132PSMasked256, + ssa.OpAMD64VFNMSUB132PDMasked128, + ssa.OpAMD64VFNMSUB132PDMasked256, + ssa.OpAMD64VFNMSUB132PDMasked512, + ssa.OpAMD64VFNMSUB213PSMasked512, + ssa.OpAMD64VFNMSUB213PSMasked128, + ssa.OpAMD64VFNMSUB213PSMasked256, + ssa.OpAMD64VFNMSUB213PDMasked128, + ssa.OpAMD64VFNMSUB213PDMasked256, + ssa.OpAMD64VFNMSUB213PDMasked512, + ssa.OpAMD64VFNMSUB231PSMasked512, + ssa.OpAMD64VFNMSUB231PSMasked128, + ssa.OpAMD64VFNMSUB231PSMasked256, + ssa.OpAMD64VFNMSUB231PDMasked128, + ssa.OpAMD64VFNMSUB231PDMasked256, + ssa.OpAMD64VFNMSUB231PDMasked512, + ssa.OpAMD64VMAXPSMasked512, + ssa.OpAMD64VMAXPSMasked128, + ssa.OpAMD64VMAXPSMasked256, + ssa.OpAMD64VMAXPDMasked128, + ssa.OpAMD64VMAXPDMasked256, + ssa.OpAMD64VMAXPDMasked512, + ssa.OpAMD64VPMAXSWMasked256, + ssa.OpAMD64VPMAXSWMasked512, + ssa.OpAMD64VPMAXSWMasked128, + ssa.OpAMD64VPMAXSDMasked512, + ssa.OpAMD64VPMAXSDMasked128, + ssa.OpAMD64VPMAXSDMasked256, + ssa.OpAMD64VPMAXSQMasked128, + ssa.OpAMD64VPMAXSQMasked256, + ssa.OpAMD64VPMAXSQMasked512, + ssa.OpAMD64VPMAXSBMasked128, + ssa.OpAMD64VPMAXSBMasked256, + ssa.OpAMD64VPMAXSBMasked512, + ssa.OpAMD64VPMAXUWMasked256, + ssa.OpAMD64VPMAXUWMasked512, + ssa.OpAMD64VPMAXUWMasked128, + ssa.OpAMD64VPMAXUDMasked512, + ssa.OpAMD64VPMAXUDMasked128, + ssa.OpAMD64VPMAXUDMasked256, + ssa.OpAMD64VPMAXUQMasked128, + ssa.OpAMD64VPMAXUQMasked256, + ssa.OpAMD64VPMAXUQMasked512, + ssa.OpAMD64VPMAXUBMasked128, + ssa.OpAMD64VPMAXUBMasked256, + ssa.OpAMD64VPMAXUBMasked512, + ssa.OpAMD64VMINPSMasked512, + ssa.OpAMD64VMINPSMasked128, + ssa.OpAMD64VMINPSMasked256, + ssa.OpAMD64VMINPDMasked128, + ssa.OpAMD64VMINPDMasked256, + ssa.OpAMD64VMINPDMasked512, + ssa.OpAMD64VPMINSWMasked256, + ssa.OpAMD64VPMINSWMasked512, + ssa.OpAMD64VPMINSWMasked128, + ssa.OpAMD64VPMINSDMasked512, + ssa.OpAMD64VPMINSDMasked128, + ssa.OpAMD64VPMINSDMasked256, + ssa.OpAMD64VPMINSQMasked128, + ssa.OpAMD64VPMINSQMasked256, + ssa.OpAMD64VPMINSQMasked512, + ssa.OpAMD64VPMINSBMasked128, + ssa.OpAMD64VPMINSBMasked256, + ssa.OpAMD64VPMINSBMasked512, + ssa.OpAMD64VPMINUWMasked256, + ssa.OpAMD64VPMINUWMasked512, + ssa.OpAMD64VPMINUWMasked128, + ssa.OpAMD64VPMINUDMasked512, + ssa.OpAMD64VPMINUDMasked128, + ssa.OpAMD64VPMINUDMasked256, + ssa.OpAMD64VPMINUQMasked128, + ssa.OpAMD64VPMINUQMasked256, + ssa.OpAMD64VPMINUQMasked512, + ssa.OpAMD64VPMINUBMasked128, + ssa.OpAMD64VPMINUBMasked256, + ssa.OpAMD64VPMINUBMasked512, + ssa.OpAMD64VMULPSMasked512, + ssa.OpAMD64VMULPSMasked128, + ssa.OpAMD64VMULPSMasked256, + ssa.OpAMD64VMULPDMasked128, + ssa.OpAMD64VMULPDMasked256, + ssa.OpAMD64VMULPDMasked512, + ssa.OpAMD64VSCALEFPSMasked512, + ssa.OpAMD64VSCALEFPSMasked128, + ssa.OpAMD64VSCALEFPSMasked256, + ssa.OpAMD64VSCALEFPDMasked128, + ssa.OpAMD64VSCALEFPDMasked256, + ssa.OpAMD64VSCALEFPDMasked512, + ssa.OpAMD64VPMULDQMasked128, + ssa.OpAMD64VPMULDQMasked256, + ssa.OpAMD64VPMULDQMasked512, + ssa.OpAMD64VPMULUDQMasked128, + ssa.OpAMD64VPMULUDQMasked256, + ssa.OpAMD64VPMULUDQMasked512, + ssa.OpAMD64VPMULHWMasked256, + ssa.OpAMD64VPMULHWMasked512, + ssa.OpAMD64VPMULHWMasked128, + ssa.OpAMD64VPMULHUWMasked256, + ssa.OpAMD64VPMULHUWMasked512, + ssa.OpAMD64VPMULHUWMasked128, + ssa.OpAMD64VPMULLWMasked256, + ssa.OpAMD64VPMULLWMasked512, + ssa.OpAMD64VPMULLWMasked128, + ssa.OpAMD64VPMULLDMasked512, + ssa.OpAMD64VPMULLDMasked128, + ssa.OpAMD64VPMULLDMasked256, + ssa.OpAMD64VPMULLQMasked128, + ssa.OpAMD64VPMULLQMasked256, + ssa.OpAMD64VPMULLQMasked512, + ssa.OpAMD64VORPSMasked512, + ssa.OpAMD64VORPSMasked128, + ssa.OpAMD64VORPSMasked256, + ssa.OpAMD64VORPDMasked128, + ssa.OpAMD64VORPDMasked256, + ssa.OpAMD64VORPDMasked512, + ssa.OpAMD64VPORDMasked512, + ssa.OpAMD64VPORDMasked128, + ssa.OpAMD64VPORDMasked256, + ssa.OpAMD64VPORQMasked128, + ssa.OpAMD64VPORQMasked256, + ssa.OpAMD64VPORQMasked512, + ssa.OpAMD64VPMADDWDMasked256, + ssa.OpAMD64VPMADDWDMasked512, + ssa.OpAMD64VPMADDWDMasked128, + ssa.OpAMD64VPDPWSSDMasked512, + ssa.OpAMD64VPDPWSSDMasked128, + ssa.OpAMD64VPDPWSSDMasked256, + ssa.OpAMD64VPOPCNTWMasked256, + ssa.OpAMD64VPOPCNTWMasked512, + ssa.OpAMD64VPOPCNTWMasked128, + ssa.OpAMD64VPOPCNTDMasked512, + ssa.OpAMD64VPOPCNTDMasked128, + ssa.OpAMD64VPOPCNTDMasked256, + ssa.OpAMD64VPOPCNTQMasked128, + ssa.OpAMD64VPOPCNTQMasked256, + ssa.OpAMD64VPOPCNTQMasked512, + ssa.OpAMD64VPOPCNTBMasked128, + ssa.OpAMD64VPOPCNTBMasked256, + ssa.OpAMD64VPOPCNTBMasked512, + ssa.OpAMD64VPADDSWMasked256, + ssa.OpAMD64VPADDSWMasked512, + ssa.OpAMD64VPADDSWMasked128, + ssa.OpAMD64VPADDSBMasked128, + ssa.OpAMD64VPADDSBMasked256, + ssa.OpAMD64VPADDSBMasked512, + ssa.OpAMD64VPDPWSSDSMasked512, + ssa.OpAMD64VPDPWSSDSMasked128, + ssa.OpAMD64VPDPWSSDSMasked256, + ssa.OpAMD64VPSUBSWMasked256, + ssa.OpAMD64VPSUBSWMasked512, + ssa.OpAMD64VPSUBSWMasked128, + ssa.OpAMD64VPSUBSBMasked128, + ssa.OpAMD64VPSUBSBMasked256, + ssa.OpAMD64VPSUBSBMasked512, + ssa.OpAMD64VPMADDUBSWMasked256, + ssa.OpAMD64VPMADDUBSWMasked512, + ssa.OpAMD64VPMADDUBSWMasked128, + ssa.OpAMD64VPDPBUSDSMasked512, + ssa.OpAMD64VPDPBUSDSMasked128, + ssa.OpAMD64VPDPBUSDSMasked256, + ssa.OpAMD64VSQRTPSMasked512, + ssa.OpAMD64VSQRTPSMasked128, + ssa.OpAMD64VSQRTPSMasked256, + ssa.OpAMD64VSQRTPDMasked128, + ssa.OpAMD64VSQRTPDMasked256, + ssa.OpAMD64VSQRTPDMasked512, + ssa.OpAMD64VPSUBWMasked256, + ssa.OpAMD64VPSUBWMasked512, + ssa.OpAMD64VPSUBWMasked128, + ssa.OpAMD64VPSUBDMasked512, + ssa.OpAMD64VPSUBDMasked128, + ssa.OpAMD64VPSUBDMasked256, + ssa.OpAMD64VPSUBQMasked128, + ssa.OpAMD64VPSUBQMasked256, + ssa.OpAMD64VPSUBQMasked512, + ssa.OpAMD64VPSUBBMasked128, + ssa.OpAMD64VPSUBBMasked256, + ssa.OpAMD64VPSUBBMasked512, + ssa.OpAMD64VPDPBUSDMasked512, + ssa.OpAMD64VPDPBUSDMasked128, + ssa.OpAMD64VPDPBUSDMasked256, + ssa.OpAMD64VXORPSMasked512, + ssa.OpAMD64VXORPSMasked128, + ssa.OpAMD64VXORPSMasked256, + ssa.OpAMD64VXORPDMasked128, + ssa.OpAMD64VXORPDMasked256, + ssa.OpAMD64VXORPDMasked512, + ssa.OpAMD64VPXORDMasked512, + ssa.OpAMD64VPXORDMasked128, + ssa.OpAMD64VPXORDMasked256, + ssa.OpAMD64VPXORQMasked128, + ssa.OpAMD64VPXORQMasked256, + ssa.OpAMD64VPXORQMasked512: + x86.ParseSuffix(p, "Z") + } + + return true +} diff --git a/src/cmd/compile/internal/amd64/ssa.go b/src/cmd/compile/internal/amd64/ssa.go index 3af513773d3b2e..2962fe1698e164 100644 --- a/src/cmd/compile/internal/amd64/ssa.go +++ b/src/cmd/compile/internal/amd64/ssa.go @@ -67,6 +67,8 @@ func storeByType(t *types.Type) obj.As { case 8: return x86.AMOVSD } + } else if t.IsSIMD() { + return simdMov(width) } else { switch width { case 1: @@ -92,6 +94,8 @@ func moveByType(t *types.Type) obj.As { // There is no xmm->xmm move with 1 byte opcode, // so use movups, which has 2 byte opcode. return x86.AMOVUPS + } else if t.IsSIMD() { + return simdMov(t.Size()) } else { switch t.Size() { case 1: @@ -1038,6 +1042,10 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { } x := v.Args[0].Reg() y := v.Reg() + if v.Type.IsSIMD() { + x = simdReg(v.Args[0]) + y = simdReg(v) + } if x != y { opregreg(s, moveByType(v.Type), y, x) } @@ -1049,16 +1057,24 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p := s.Prog(loadByType(v.Type)) ssagen.AddrAuto(&p.From, v.Args[0]) p.To.Type = obj.TYPE_REG - p.To.Reg = v.Reg() + r := v.Reg() + if v.Type.IsSIMD() { + r = simdReg(v) + } + p.To.Reg = r case ssa.OpStoreReg: if v.Type.IsFlags() { v.Fatalf("store flags not implemented: %v", v.LongString()) return } + r := v.Args[0].Reg() + if v.Type.IsSIMD() { + r = simdReg(v.Args[0]) + } p := s.Prog(storeByType(v.Type)) p.From.Type = obj.TYPE_REG - p.From.Reg = v.Args[0].Reg() + p.From.Reg = r ssagen.AddrAuto(&p.To, v) case ssa.OpAMD64LoweredHasCPUFeature: p := s.Prog(x86.AMOVBLZX) @@ -1426,11 +1442,260 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) { p.From.Offset = int64(x) p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg() + + // XXX SIMD + // XXX may change depending on how we handle aliased registers + case ssa.OpAMD64Zero128, ssa.OpAMD64Zero256, ssa.OpAMD64Zero512: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v) + p.AddRestSourceReg(simdReg(v)) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + case ssa.OpAMD64VPADDD4: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + case ssa.OpAMD64VMOVDQUload128, ssa.OpAMD64VMOVDQUload256, ssa.OpAMD64VMOVDQUload512: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_MEM + p.From.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.From, v) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + case ssa.OpAMD64VMOVDQUstore128, ssa.OpAMD64VMOVDQUstore256, ssa.OpAMD64VMOVDQUstore512: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + p.To.Type = obj.TYPE_MEM + p.To.Reg = v.Args[0].Reg() + ssagen.AddAux(&p.To, v) + + case ssa.OpAMD64VPMOVMToVec8x16, + ssa.OpAMD64VPMOVMToVec8x32, + ssa.OpAMD64VPMOVMToVec8x64, + ssa.OpAMD64VPMOVMToVec16x8, + ssa.OpAMD64VPMOVMToVec16x16, + ssa.OpAMD64VPMOVMToVec16x32, + ssa.OpAMD64VPMOVMToVec32x4, + ssa.OpAMD64VPMOVMToVec32x8, + ssa.OpAMD64VPMOVMToVec32x16, + ssa.OpAMD64VPMOVMToVec64x2, + ssa.OpAMD64VPMOVMToVec64x4, + ssa.OpAMD64VPMOVMToVec64x8: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = v.Args[0].Reg() + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + + case ssa.OpAMD64VPMOVVec8x16ToM, + ssa.OpAMD64VPMOVVec8x32ToM, + ssa.OpAMD64VPMOVVec8x64ToM, + ssa.OpAMD64VPMOVVec16x8ToM, + ssa.OpAMD64VPMOVVec16x16ToM, + ssa.OpAMD64VPMOVVec16x32ToM, + ssa.OpAMD64VPMOVVec32x4ToM, + ssa.OpAMD64VPMOVVec32x8ToM, + ssa.OpAMD64VPMOVVec32x16ToM, + ssa.OpAMD64VPMOVVec64x2ToM, + ssa.OpAMD64VPMOVVec64x4ToM, + ssa.OpAMD64VPMOVVec64x8ToM: + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.To.Type = obj.TYPE_REG + p.To.Reg = v.Reg() + default: - v.Fatalf("genValue not implemented: %s", v.LongString()) + if !ssaGenSIMDValue(s, v) { + v.Fatalf("genValue not implemented: %s", v.LongString()) + } } } +// Example instruction: VRSQRTPS X1, X1 +func simdFp11(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPSUBD X1, X2, X3 +func simdFp21(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + // Vector registers operands follows a right-to-left order. + // e.g. VPSUBD X1, X2, X3 means X3 = X2 - X1. + p.From.Reg = simdReg(v.Args[1]) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPCMPEQW Z26, Z30, K4 +func simdFp2k1(s *ssagen.State, v *ssa.Value) *obj.Prog { + // simdReg handles mask and vector registers altogether + return simdFp21(s, v) +} + +// Example instruction: VPMINUQ X21, X3, K3, X31 +func simdFp2k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[1]) + p.AddRestSourceReg(simdReg(v.Args[0])) + // These "simd*" series of functions assumes: + // Any "K" register that serves as the write-mask + // or "predicate" for "predicated AVX512 instructions" + // sits right at the end of the operand list. + // TODO: verify this assumption. + p.AddRestSourceReg(simdReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPCMPEQW Z26, Z30, K1, K4 +func simdFp2k1k1(s *ssagen.State, v *ssa.Value) *obj.Prog { + return simdFp2k1fp1(s, v) +} + +// Example instruction: VPOPCNTB X14, K4, X16 +func simdFp1k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[0]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VROUNDPD $7, X2, X2 +func simdFp11Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + imm := v.AuxInt + if imm < 0 || imm > 255 { + v.Fatalf("Invalid source selection immediate") + } + p.From.Offset = imm + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VREDUCEPD $126, X1, K3, X31 +func simdFp1k1fp1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + imm := v.AuxInt + if imm < 0 || imm > 255 { + v.Fatalf("Invalid source selection immediate") + } + p.From.Offset = imm + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VCMPPS $7, X2, X9, X2 +func simdFp21Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + imm := v.AuxInt + if imm < 0 || imm > 255 { + v.Fatalf("Invalid source selection immediate") + } + p.From.Offset = imm + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VPCMPD $1, Z1, Z2, K1 +func simdFp2k1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + return simdFp21Imm8(s, v) +} + +// Example instruction: VPCMPD $1, Z1, Z2, K2, K1 +func simdFp2k1k1Imm8(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + imm := v.AuxInt + if imm < 0 || imm > 255 { + v.Fatalf("Invalid source selection immediate") + } + p.From.Offset = imm + p.From.Type = obj.TYPE_CONST + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(simdReg(v.Args[2])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VFMADD213PD Z2, Z1, Z0 +func simdFp31ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Example instruction: VFMADD213PD Z2, Z1, K1, Z0 +func simdFp3k1fp1ResultInArg0(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[3])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Currently unused +func simdFp31(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + +// Currently unused +func simdFp3k1fp1(s *ssagen.State, v *ssa.Value) *obj.Prog { + p := s.Prog(v.Op.Asm()) + p.From.Type = obj.TYPE_REG + p.From.Reg = simdReg(v.Args[2]) + p.AddRestSourceReg(simdReg(v.Args[1])) + p.AddRestSourceReg(simdReg(v.Args[0])) + p.AddRestSourceReg(simdReg(v.Args[3])) + p.To.Type = obj.TYPE_REG + p.To.Reg = simdReg(v) + return p +} + var blockJump = [...]struct { asm, invasm obj.As }{ @@ -1532,3 +1797,32 @@ func spillArgReg(pp *objw.Progs, p *obj.Prog, f *ssa.Func, t *types.Type, reg in p.Pos = p.Pos.WithNotStmt() return p } + +// XXX maybe make this part of v.Reg? +// On the other hand, it is architecture-specific. +func simdReg(v *ssa.Value) int16 { + t := v.Type + if !t.IsSIMD() { + panic("simdReg: not a simd type") + } + switch t.Size() { + case 8: + return v.Reg() // K registers + case 16: + return v.Reg() + case 32: + return v.Reg() + (x86.REG_Y0 - x86.REG_X0) + case 64: + return v.Reg() + (x86.REG_Z0 - x86.REG_X0) + } + panic("unreachable") +} + +func simdMov(width int64) obj.As { + if width >= 64 { + return x86.AVMOVDQU64 + } else if width >= 16 { + return x86.AVMOVDQU + } + return x86.AKMOVQ +} diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64.rules b/src/cmd/compile/internal/ssa/_gen/AMD64.rules index d55dfe70acc155..2972eae87d5479 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64.rules +++ b/src/cmd/compile/internal/ssa/_gen/AMD64.rules @@ -1680,3 +1680,36 @@ // If we don't use the flags any more, just use the standard op. (Select0 a:(ADD(Q|L)constflags [c] x)) && a.Uses == 1 => (ADD(Q|L)const [c] x) + +// XXX SIMD +(Load ptr mem) && t.Size() == 16 => (VMOVDQUload128 ptr mem) + +(Store {t} ptr val mem) && t.Size() == 16 => (VMOVDQUstore128 ptr val mem) + +(Load ptr mem) && t.Size() == 32 => (VMOVDQUload256 ptr mem) + +(Store {t} ptr val mem) && t.Size() == 32 => (VMOVDQUstore256 ptr val mem) + +(Load ptr mem) && t.Size() == 64 => (VMOVDQUload512 ptr mem) + +(Store {t} ptr val mem) && t.Size() == 64 => (VMOVDQUstore512 ptr val mem) + +(ZeroSIMD ) && t.Size() == 16 => (Zero128 ) +(ZeroSIMD ) && t.Size() == 32 => (Zero256 ) +(ZeroSIMD ) && t.Size() == 64 => (Zero512 ) + +(VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) => x +(VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) => x +(VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) => x + +(VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) => x +(VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) => x +(VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) => x + +(VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) => x +(VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) => x +(VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) => x + +(VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) => x +(VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) => x +(VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) => x diff --git a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go index 0f17843565276a..99d0d0ec740063 100644 --- a/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go +++ b/src/cmd/compile/internal/ssa/_gen/AMD64Ops.go @@ -63,6 +63,16 @@ var regNamesAMD64 = []string{ "X14", "X15", // constant 0 in ABIInternal + // TODO: update asyncPreempt for K registers. + // asyncPreempt also needs to store Z0-Z15 properly. + "K0", + "K1", + "K2", + "K3", + "K4", + "K5", + "K6", + "K7", // If you add registers, update asyncPreempt in runtime // pseudo-registers @@ -100,6 +110,7 @@ func init() { g = buildReg("g") fp = buildReg("X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14") x15 = buildReg("X15") + mask = buildReg("K1 K2 K3 K4 K5 K6 K7") gpsp = gp | buildReg("SP") gpspsb = gpsp | buildReg("SB") gpspsbg = gpspsb | g @@ -107,8 +118,9 @@ func init() { ) // Common slices of register masks var ( - gponly = []regMask{gp} - fponly = []regMask{fp} + gponly = []regMask{gp} + fponly = []regMask{fp} + maskonly = []regMask{mask} ) // Common regInfo @@ -170,6 +182,15 @@ func init() { fpstore = regInfo{inputs: []regMask{gpspsb, fp, 0}} fpstoreidx = regInfo{inputs: []regMask{gpspsb, gpsp, fp, 0}} + fp1k1 = regInfo{inputs: fponly, outputs: maskonly} + k1fp1 = regInfo{inputs: maskonly, outputs: fponly} + fp2k1 = regInfo{inputs: []regMask{fp, fp}, outputs: maskonly} + fp1k1fp1 = regInfo{inputs: []regMask{fp, mask}, outputs: fponly} + fp2k1fp1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: fponly} + fp2k1k1 = regInfo{inputs: []regMask{fp, fp, mask}, outputs: maskonly} + fp3fp1 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: fponly} + fp3k1fp1 = regInfo{inputs: []regMask{fp, fp, fp, mask}, outputs: fponly} + prefreg = regInfo{inputs: []regMask{gpspsbg}} ) @@ -1199,6 +1220,54 @@ func init() { // // output[i] = (input[i] >> 7) & 1 {name: "PMOVMSKB", argLength: 1, reg: fpgp, asm: "PMOVMSKB"}, + + // XXX SIMD + {name: "VPADDD4", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true}, // arg0 + arg1 + + {name: "VMOVDQUload128", argLength: 2, reg: fpload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem + {name: "VMOVDQUstore128", argLength: 3, reg: fpstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem + + {name: "VMOVDQUload256", argLength: 2, reg: fpload, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem + {name: "VMOVDQUstore256", argLength: 3, reg: fpstore, asm: "VMOVDQU", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem + + {name: "VMOVDQUload512", argLength: 2, reg: fpload, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Read"}, // load from arg0+auxint+aux, arg1 = mem + {name: "VMOVDQUstore512", argLength: 3, reg: fpstore, asm: "VMOVDQU64", aux: "SymOff", faultOnNilArg0: true, symEffect: "Write"}, // store, *(arg0+auxint+aux) = arg1, arg2 = mem + + {name: "VPMOVMToVec8x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"}, + {name: "VPMOVMToVec8x32", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"}, + {name: "VPMOVMToVec8x64", argLength: 1, reg: k1fp1, asm: "VPMOVM2B"}, + + {name: "VPMOVMToVec16x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"}, + {name: "VPMOVMToVec16x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"}, + {name: "VPMOVMToVec16x32", argLength: 1, reg: k1fp1, asm: "VPMOVM2W"}, + + {name: "VPMOVMToVec32x4", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"}, + {name: "VPMOVMToVec32x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"}, + {name: "VPMOVMToVec32x16", argLength: 1, reg: k1fp1, asm: "VPMOVM2D"}, + + {name: "VPMOVMToVec64x2", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"}, + {name: "VPMOVMToVec64x4", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"}, + {name: "VPMOVMToVec64x8", argLength: 1, reg: k1fp1, asm: "VPMOVM2Q"}, + + {name: "VPMOVVec8x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"}, + {name: "VPMOVVec8x32ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"}, + {name: "VPMOVVec8x64ToM", argLength: 1, reg: fp1k1, asm: "VPMOVB2M"}, + + {name: "VPMOVVec16x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"}, + {name: "VPMOVVec16x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"}, + {name: "VPMOVVec16x32ToM", argLength: 1, reg: fp1k1, asm: "VPMOVW2M"}, + + {name: "VPMOVVec32x4ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"}, + {name: "VPMOVVec32x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"}, + {name: "VPMOVVec32x16ToM", argLength: 1, reg: fp1k1, asm: "VPMOVD2M"}, + + {name: "VPMOVVec64x2ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"}, + {name: "VPMOVVec64x4ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"}, + {name: "VPMOVVec64x8ToM", argLength: 1, reg: fp1k1, asm: "VPMOVQ2M"}, + + {name: "Zero128", argLength: 0, reg: fp01, asm: "VPXOR"}, + {name: "Zero256", argLength: 0, reg: fp01, asm: "VPXOR"}, + {name: "Zero512", argLength: 0, reg: fp01, asm: "VPXORQ"}, } var AMD64blocks = []blockData{ @@ -1230,14 +1299,15 @@ func init() { name: "AMD64", pkg: "cmd/internal/obj/x86", genfile: "../../amd64/ssa.go", - ops: AMD64ops, + genSIMDfile: "../../amd64/simdssa.go", + ops: append(AMD64ops, simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp3fp1, fp3k1fp1)...), // AMD64ops, blocks: AMD64blocks, regnames: regNamesAMD64, ParamIntRegNames: "AX BX CX DI SI R8 R9 R10 R11", ParamFloatRegNames: "X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14", gpregmask: gp, fpregmask: fp, - specialregmask: x15, + specialregmask: x15 | mask, framepointerreg: int8(num["BP"]), linkreg: -1, // not used }) diff --git a/src/cmd/compile/internal/ssa/_gen/README b/src/cmd/compile/internal/ssa/_gen/README index 74b81c2814330c..a8242f93527097 100644 --- a/src/cmd/compile/internal/ssa/_gen/README +++ b/src/cmd/compile/internal/ssa/_gen/README @@ -9,3 +9,8 @@ more information. To regenerate everything, run "go generate" on the ssa package in the parent directory. + +The parent directory contains a test in generate_test.go that will fail +if the generated files are not up-to-date, and to allow that test to +run in no-network environments, golang.org/x/tools/go/ast/astutil is +vendored. diff --git a/src/cmd/compile/internal/ssa/_gen/allocators.go b/src/cmd/compile/internal/ssa/_gen/allocators.go index 682fc5f20217e9..38acc5133abe86 100644 --- a/src/cmd/compile/internal/ssa/_gen/allocators.go +++ b/src/cmd/compile/internal/ssa/_gen/allocators.go @@ -155,7 +155,7 @@ func genAllocators() { panic(err) } - if err := os.WriteFile("../allocators.go", b, 0666); err != nil { + if err := os.WriteFile(outFile("allocators.go"), b, 0666); err != nil { log.Fatalf("can't write output: %v\n", err) } } diff --git a/src/cmd/compile/internal/ssa/_gen/generic.rules b/src/cmd/compile/internal/ssa/_gen/generic.rules index b178a1add6de29..1077921f93400c 100644 --- a/src/cmd/compile/internal/ssa/_gen/generic.rules +++ b/src/cmd/compile/internal/ssa/_gen/generic.rules @@ -910,7 +910,7 @@ // struct operations (StructSelect [i] x:(StructMake ___)) => x.Args[i] -(Load _ _) && t.IsStruct() && CanSSA(t) => rewriteStructLoad(v) +(Load _ _) && t.IsStruct() && CanSSA(t) && !t.IsSIMD() => rewriteStructLoad(v) (Store _ (StructMake ___) _) => rewriteStructStore(v) (StructSelect [i] x:(Load ptr mem)) && !CanSSA(t) => diff --git a/src/cmd/compile/internal/ssa/_gen/genericOps.go b/src/cmd/compile/internal/ssa/_gen/genericOps.go index 1f6ad4e16d98f8..2d44cc85f8242e 100644 --- a/src/cmd/compile/internal/ssa/_gen/genericOps.go +++ b/src/cmd/compile/internal/ssa/_gen/genericOps.go @@ -662,6 +662,10 @@ var genericOps = []opData{ // Prefetch instruction {name: "PrefetchCache", argLength: 2, hasSideEffects: true}, // Do prefetch arg0 to cache. arg0=addr, arg1=memory. {name: "PrefetchCacheStreamed", argLength: 2, hasSideEffects: true}, // Do non-temporal or streamed prefetch arg0 to cache. arg0=addr, arg1=memory. + + // XXX SIMD + {name: "Add32x4", argLength: 2}, // arg0 + arg1 + {name: "ZeroSIMD", argLength: 0}, } // kind controls successors implicit exit @@ -689,6 +693,7 @@ var genericBlocks = []blockData{ } func init() { + genericOps = append(genericOps, simdGenericOps()...) archs = append(archs, arch{ name: "generic", ops: genericOps, diff --git a/src/cmd/compile/internal/ssa/_gen/main.go b/src/cmd/compile/internal/ssa/_gen/main.go index 3f65831b6e02b5..5b85cec79c0e93 100644 --- a/src/cmd/compile/internal/ssa/_gen/main.go +++ b/src/cmd/compile/internal/ssa/_gen/main.go @@ -32,6 +32,7 @@ type arch struct { name string pkg string // obj package to import for this arch. genfile string // source file containing opcode code generation. + genSIMDfile string // source file containing opcode code generation for SIMD. ops []opData blocks []blockData regnames []string @@ -113,6 +114,7 @@ var archs []arch var cpuprofile = flag.String("cpuprofile", "", "write cpu profile to `file`") var memprofile = flag.String("memprofile", "", "write memory profile to `file`") var tracefile = flag.String("trace", "", "write trace to `file`") +var outDir = flag.String("outdir", "..", "directory in which to write generated files") func main() { flag.Parse() @@ -144,6 +146,13 @@ func main() { defer trace.Stop() } + if *outDir != ".." { + err := os.MkdirAll(*outDir, 0755) + if err != nil { + log.Fatalf("failed to create output directory: %v", err) + } + } + slices.SortFunc(archs, func(a, b arch) int { return strings.Compare(a.name, b.name) }) @@ -193,6 +202,10 @@ func main() { } } +func outFile(file string) string { + return *outDir + "/" + file +} + func genOp() { w := new(bytes.Buffer) fmt.Fprintf(w, "// Code generated from _gen/*Ops.go using 'go generate'; DO NOT EDIT.\n") @@ -500,7 +513,7 @@ func genOp() { panic(err) } - if err := os.WriteFile("../opGen.go", b, 0666); err != nil { + if err := os.WriteFile(outFile("opGen.go"), b, 0666); err != nil { log.Fatalf("can't write output: %v\n", err) } @@ -525,6 +538,15 @@ func genOp() { if err != nil { log.Fatalf("can't read %s: %v", a.genfile, err) } + // Append the file of simd operations, too + if a.genSIMDfile != "" { + simdSrc, err := os.ReadFile(a.genSIMDfile) + if err != nil { + log.Fatalf("can't read %s: %v", a.genSIMDfile, err) + } + src = append(src, simdSrc...) + } + seen := make(map[string]bool, len(a.ops)) for _, m := range rxOp.FindAllSubmatch(src, -1) { seen[string(m[1])] = true diff --git a/src/cmd/compile/internal/ssa/_gen/rulegen.go b/src/cmd/compile/internal/ssa/_gen/rulegen.go index c2891da6c8d368..5e66398927793b 100644 --- a/src/cmd/compile/internal/ssa/_gen/rulegen.go +++ b/src/cmd/compile/internal/ssa/_gen/rulegen.go @@ -95,6 +95,7 @@ func genLateLowerRules(arch arch) { genRulesSuffix(arch, "latelower") } func genRulesSuffix(arch arch, suff string) { // Open input file. + var text io.Reader text, err := os.Open(arch.name + suff + ".rules") if err != nil { if suff == "" { @@ -105,6 +106,14 @@ func genRulesSuffix(arch arch, suff string) { return } + // Check for file of SIMD rules to add + if suff == "" { + simdtext, err := os.Open("simd" + arch.name + ".rules") + if err == nil { + text = io.MultiReader(text, simdtext) + } + } + // oprules contains a list of rules for each block and opcode blockrules := map[string][]Rule{} oprules := map[string][]Rule{} @@ -322,7 +331,7 @@ func genRulesSuffix(arch arch, suff string) { file = astutil.Apply(file, pre, post).(*ast.File) // Write the well-formatted source to file - f, err := os.Create("../rewrite" + arch.name + suff + ".go") + f, err := os.Create(outFile("rewrite" + arch.name + suff + ".go")) if err != nil { log.Fatalf("can't write output: %v", err) } diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules new file mode 100644 index 00000000000000..add066a3b6dcff --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64.rules @@ -0,0 +1,1553 @@ +// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT. + +(AbsoluteInt16x16 ...) => (VPABSW256 ...) +(AbsoluteInt16x32 ...) => (VPABSW512 ...) +(AbsoluteInt16x8 ...) => (VPABSW128 ...) +(AbsoluteInt32x16 ...) => (VPABSD512 ...) +(AbsoluteInt32x4 ...) => (VPABSD128 ...) +(AbsoluteInt32x8 ...) => (VPABSD256 ...) +(AbsoluteInt64x2 ...) => (VPABSQ128 ...) +(AbsoluteInt64x4 ...) => (VPABSQ256 ...) +(AbsoluteInt64x8 ...) => (VPABSQ512 ...) +(AbsoluteInt8x16 ...) => (VPABSB128 ...) +(AbsoluteInt8x32 ...) => (VPABSB256 ...) +(AbsoluteInt8x64 ...) => (VPABSB512 ...) +(AddFloat32x16 ...) => (VADDPS512 ...) +(AddFloat32x4 ...) => (VADDPS128 ...) +(AddFloat32x8 ...) => (VADDPS256 ...) +(AddFloat64x2 ...) => (VADDPD128 ...) +(AddFloat64x4 ...) => (VADDPD256 ...) +(AddFloat64x8 ...) => (VADDPD512 ...) +(AddInt16x16 ...) => (VPADDW256 ...) +(AddInt16x32 ...) => (VPADDW512 ...) +(AddInt16x8 ...) => (VPADDW128 ...) +(AddInt32x16 ...) => (VPADDD512 ...) +(AddInt32x4 ...) => (VPADDD128 ...) +(AddInt32x8 ...) => (VPADDD256 ...) +(AddInt64x2 ...) => (VPADDQ128 ...) +(AddInt64x4 ...) => (VPADDQ256 ...) +(AddInt64x8 ...) => (VPADDQ512 ...) +(AddInt8x16 ...) => (VPADDB128 ...) +(AddInt8x32 ...) => (VPADDB256 ...) +(AddInt8x64 ...) => (VPADDB512 ...) +(AddUint16x16 ...) => (VPADDW256 ...) +(AddUint16x32 ...) => (VPADDW512 ...) +(AddUint16x8 ...) => (VPADDW128 ...) +(AddUint32x16 ...) => (VPADDD512 ...) +(AddUint32x4 ...) => (VPADDD128 ...) +(AddUint32x8 ...) => (VPADDD256 ...) +(AddUint64x2 ...) => (VPADDQ128 ...) +(AddUint64x4 ...) => (VPADDQ256 ...) +(AddUint64x8 ...) => (VPADDQ512 ...) +(AddUint8x16 ...) => (VPADDB128 ...) +(AddUint8x32 ...) => (VPADDB256 ...) +(AddUint8x64 ...) => (VPADDB512 ...) +(AddSubFloat32x4 ...) => (VADDSUBPS128 ...) +(AddSubFloat32x8 ...) => (VADDSUBPS256 ...) +(AddSubFloat64x2 ...) => (VADDSUBPD128 ...) +(AddSubFloat64x4 ...) => (VADDSUBPD256 ...) +(AndFloat32x16 ...) => (VANDPS512 ...) +(AndFloat32x4 ...) => (VANDPS128 ...) +(AndFloat32x8 ...) => (VANDPS256 ...) +(AndFloat64x2 ...) => (VANDPD128 ...) +(AndFloat64x4 ...) => (VANDPD256 ...) +(AndFloat64x8 ...) => (VANDPD512 ...) +(AndInt16x16 ...) => (VPAND256 ...) +(AndInt16x8 ...) => (VPAND128 ...) +(AndInt32x16 ...) => (VPANDD512 ...) +(AndInt32x4 ...) => (VPAND128 ...) +(AndInt32x8 ...) => (VPAND256 ...) +(AndInt64x2 ...) => (VPAND128 ...) +(AndInt64x4 ...) => (VPAND256 ...) +(AndInt64x8 ...) => (VPANDQ512 ...) +(AndInt8x16 ...) => (VPAND128 ...) +(AndInt8x32 ...) => (VPAND256 ...) +(AndUint16x16 ...) => (VPAND256 ...) +(AndUint16x8 ...) => (VPAND128 ...) +(AndUint32x16 ...) => (VPANDD512 ...) +(AndUint32x4 ...) => (VPAND128 ...) +(AndUint32x8 ...) => (VPAND256 ...) +(AndUint64x2 ...) => (VPAND128 ...) +(AndUint64x4 ...) => (VPAND256 ...) +(AndUint64x8 ...) => (VPANDQ512 ...) +(AndUint8x16 ...) => (VPAND128 ...) +(AndUint8x32 ...) => (VPAND256 ...) +(AndNotFloat32x16 ...) => (VANDNPS512 ...) +(AndNotFloat32x4 ...) => (VANDNPS128 ...) +(AndNotFloat32x8 ...) => (VANDNPS256 ...) +(AndNotFloat64x2 ...) => (VANDNPD128 ...) +(AndNotFloat64x4 ...) => (VANDNPD256 ...) +(AndNotFloat64x8 ...) => (VANDNPD512 ...) +(AndNotInt16x16 ...) => (VPANDN256 ...) +(AndNotInt16x8 ...) => (VPANDN128 ...) +(AndNotInt32x16 ...) => (VPANDND512 ...) +(AndNotInt32x4 ...) => (VPANDN128 ...) +(AndNotInt32x8 ...) => (VPANDN256 ...) +(AndNotInt64x2 ...) => (VPANDN128 ...) +(AndNotInt64x4 ...) => (VPANDN256 ...) +(AndNotInt64x8 ...) => (VPANDNQ512 ...) +(AndNotInt8x16 ...) => (VPANDN128 ...) +(AndNotInt8x32 ...) => (VPANDN256 ...) +(AndNotUint16x16 ...) => (VPANDN256 ...) +(AndNotUint16x8 ...) => (VPANDN128 ...) +(AndNotUint32x16 ...) => (VPANDND512 ...) +(AndNotUint32x4 ...) => (VPANDN128 ...) +(AndNotUint32x8 ...) => (VPANDN256 ...) +(AndNotUint64x2 ...) => (VPANDN128 ...) +(AndNotUint64x4 ...) => (VPANDN256 ...) +(AndNotUint64x8 ...) => (VPANDNQ512 ...) +(AndNotUint8x16 ...) => (VPANDN128 ...) +(AndNotUint8x32 ...) => (VPANDN256 ...) +(ApproximateReciprocalFloat32x16 ...) => (VRCP14PS512 ...) +(ApproximateReciprocalFloat32x4 ...) => (VRCP14PS128 ...) +(ApproximateReciprocalFloat32x8 ...) => (VRCP14PS256 ...) +(ApproximateReciprocalFloat64x2 ...) => (VRCP14PD128 ...) +(ApproximateReciprocalFloat64x4 ...) => (VRCP14PD256 ...) +(ApproximateReciprocalFloat64x8 ...) => (VRCP14PD512 ...) +(ApproximateReciprocalOfSqrtFloat32x16 ...) => (VRSQRT14PS512 ...) +(ApproximateReciprocalOfSqrtFloat32x4 ...) => (VRSQRTPS128 ...) +(ApproximateReciprocalOfSqrtFloat32x8 ...) => (VRSQRTPS256 ...) +(ApproximateReciprocalOfSqrtFloat64x2 ...) => (VRSQRT14PD128 ...) +(ApproximateReciprocalOfSqrtFloat64x4 ...) => (VRSQRT14PD256 ...) +(ApproximateReciprocalOfSqrtFloat64x8 ...) => (VRSQRT14PD512 ...) +(AverageUint16x16 ...) => (VPAVGW256 ...) +(AverageUint16x32 ...) => (VPAVGW512 ...) +(AverageUint16x8 ...) => (VPAVGW128 ...) +(AverageUint8x16 ...) => (VPAVGB128 ...) +(AverageUint8x32 ...) => (VPAVGB256 ...) +(AverageUint8x64 ...) => (VPAVGB512 ...) +(CeilFloat32x4 x) => (VROUNDPS128 [2] x) +(CeilFloat32x8 x) => (VROUNDPS256 [2] x) +(CeilFloat64x2 x) => (VROUNDPD128 [2] x) +(CeilFloat64x4 x) => (VROUNDPD256 [2] x) +(CeilSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+10] x) +(CeilSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+10] x) +(CeilSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+10] x) +(CeilSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+10] x) +(CeilSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+10] x) +(CeilSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+10] x) +(CeilWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+2] x) +(CeilWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+2] x) +(CeilWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+2] x) +(CeilWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+2] x) +(CeilWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+2] x) +(CeilWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+2] x) +(DiffWithCeilSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+10] x) +(DiffWithCeilSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+10] x) +(DiffWithCeilSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+10] x) +(DiffWithCeilSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+10] x) +(DiffWithCeilSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+10] x) +(DiffWithCeilSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+10] x) +(DiffWithCeilWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+2] x) +(DiffWithCeilWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+2] x) +(DiffWithCeilWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+2] x) +(DiffWithCeilWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+2] x) +(DiffWithCeilWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+2] x) +(DiffWithCeilWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+2] x) +(DiffWithFloorSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+9] x) +(DiffWithFloorSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+9] x) +(DiffWithFloorSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+9] x) +(DiffWithFloorSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+9] x) +(DiffWithFloorSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+9] x) +(DiffWithFloorSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+9] x) +(DiffWithFloorWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+1] x) +(DiffWithFloorWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+1] x) +(DiffWithFloorWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+1] x) +(DiffWithFloorWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+1] x) +(DiffWithFloorWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+1] x) +(DiffWithFloorWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+1] x) +(DiffWithRoundSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+8] x) +(DiffWithRoundSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+8] x) +(DiffWithRoundSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+8] x) +(DiffWithRoundSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+8] x) +(DiffWithRoundSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+8] x) +(DiffWithRoundSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+8] x) +(DiffWithRoundWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+0] x) +(DiffWithRoundWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+0] x) +(DiffWithRoundWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+0] x) +(DiffWithRoundWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+0] x) +(DiffWithRoundWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+0] x) +(DiffWithRoundWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+0] x) +(DiffWithTruncSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+11] x) +(DiffWithTruncSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+11] x) +(DiffWithTruncSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+11] x) +(DiffWithTruncSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+11] x) +(DiffWithTruncSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+11] x) +(DiffWithTruncSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+11] x) +(DiffWithTruncWithPrecisionFloat32x16 [a] x) => (VREDUCEPS512 [a+3] x) +(DiffWithTruncWithPrecisionFloat32x4 [a] x) => (VREDUCEPS128 [a+3] x) +(DiffWithTruncWithPrecisionFloat32x8 [a] x) => (VREDUCEPS256 [a+3] x) +(DiffWithTruncWithPrecisionFloat64x2 [a] x) => (VREDUCEPD128 [a+3] x) +(DiffWithTruncWithPrecisionFloat64x4 [a] x) => (VREDUCEPD256 [a+3] x) +(DiffWithTruncWithPrecisionFloat64x8 [a] x) => (VREDUCEPD512 [a+3] x) +(DivFloat32x16 ...) => (VDIVPS512 ...) +(DivFloat32x4 ...) => (VDIVPS128 ...) +(DivFloat32x8 ...) => (VDIVPS256 ...) +(DivFloat64x2 ...) => (VDIVPD128 ...) +(DivFloat64x4 ...) => (VDIVPD256 ...) +(DivFloat64x8 ...) => (VDIVPD512 ...) +(DotProdBroadcastFloat64x2 x y) => (VDPPD128 [127] x y) +(EqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [0] x y)) +(EqualFloat32x4 x y) => (VCMPPS128 [0] x y) +(EqualFloat32x8 x y) => (VCMPPS256 [0] x y) +(EqualFloat64x2 x y) => (VCMPPD128 [0] x y) +(EqualFloat64x4 x y) => (VCMPPD256 [0] x y) +(EqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [0] x y)) +(EqualInt16x16 ...) => (VPCMPEQW256 ...) +(EqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPEQW512 x y)) +(EqualInt16x8 ...) => (VPCMPEQW128 ...) +(EqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPEQD512 x y)) +(EqualInt32x4 ...) => (VPCMPEQD128 ...) +(EqualInt32x8 ...) => (VPCMPEQD256 ...) +(EqualInt64x2 ...) => (VPCMPEQQ128 ...) +(EqualInt64x4 ...) => (VPCMPEQQ256 ...) +(EqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPEQQ512 x y)) +(EqualInt8x16 ...) => (VPCMPEQB128 ...) +(EqualInt8x32 ...) => (VPCMPEQB256 ...) +(EqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPEQB512 x y)) +(EqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [0] x y)) +(EqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [0] x y)) +(EqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [0] x y)) +(EqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [0] x y)) +(EqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [0] x y)) +(EqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [0] x y)) +(EqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [0] x y)) +(EqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [0] x y)) +(EqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [0] x y)) +(EqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [0] x y)) +(EqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [0] x y)) +(EqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [0] x y)) +(FloorFloat32x4 x) => (VROUNDPS128 [1] x) +(FloorFloat32x8 x) => (VROUNDPS256 [1] x) +(FloorFloat64x2 x) => (VROUNDPD128 [1] x) +(FloorFloat64x4 x) => (VROUNDPD256 [1] x) +(FloorSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+9] x) +(FloorSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+9] x) +(FloorSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+9] x) +(FloorSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+9] x) +(FloorSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+9] x) +(FloorSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+9] x) +(FloorWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+1] x) +(FloorWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+1] x) +(FloorWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+1] x) +(FloorWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+1] x) +(FloorWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+1] x) +(FloorWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+1] x) +(FusedMultiplyAdd132Float32x16 ...) => (VFMADD132PS512 ...) +(FusedMultiplyAdd132Float32x4 ...) => (VFMADD132PS128 ...) +(FusedMultiplyAdd132Float32x8 ...) => (VFMADD132PS256 ...) +(FusedMultiplyAdd132Float64x2 ...) => (VFMADD132PD128 ...) +(FusedMultiplyAdd132Float64x4 ...) => (VFMADD132PD256 ...) +(FusedMultiplyAdd132Float64x8 ...) => (VFMADD132PD512 ...) +(FusedMultiplyAdd213Float32x16 ...) => (VFMADD213PS512 ...) +(FusedMultiplyAdd213Float32x4 ...) => (VFMADD213PS128 ...) +(FusedMultiplyAdd213Float32x8 ...) => (VFMADD213PS256 ...) +(FusedMultiplyAdd213Float64x2 ...) => (VFMADD213PD128 ...) +(FusedMultiplyAdd213Float64x4 ...) => (VFMADD213PD256 ...) +(FusedMultiplyAdd213Float64x8 ...) => (VFMADD213PD512 ...) +(FusedMultiplyAdd231Float32x16 ...) => (VFMADD231PS512 ...) +(FusedMultiplyAdd231Float32x4 ...) => (VFMADD231PS128 ...) +(FusedMultiplyAdd231Float32x8 ...) => (VFMADD231PS256 ...) +(FusedMultiplyAdd231Float64x2 ...) => (VFMADD231PD128 ...) +(FusedMultiplyAdd231Float64x4 ...) => (VFMADD231PD256 ...) +(FusedMultiplyAdd231Float64x8 ...) => (VFMADD231PD512 ...) +(FusedMultiplyAddSub132Float32x16 ...) => (VFMADDSUB132PS512 ...) +(FusedMultiplyAddSub132Float32x4 ...) => (VFMADDSUB132PS128 ...) +(FusedMultiplyAddSub132Float32x8 ...) => (VFMADDSUB132PS256 ...) +(FusedMultiplyAddSub132Float64x2 ...) => (VFMADDSUB132PD128 ...) +(FusedMultiplyAddSub132Float64x4 ...) => (VFMADDSUB132PD256 ...) +(FusedMultiplyAddSub132Float64x8 ...) => (VFMADDSUB132PD512 ...) +(FusedMultiplyAddSub213Float32x16 ...) => (VFMADDSUB213PS512 ...) +(FusedMultiplyAddSub213Float32x4 ...) => (VFMADDSUB213PS128 ...) +(FusedMultiplyAddSub213Float32x8 ...) => (VFMADDSUB213PS256 ...) +(FusedMultiplyAddSub213Float64x2 ...) => (VFMADDSUB213PD128 ...) +(FusedMultiplyAddSub213Float64x4 ...) => (VFMADDSUB213PD256 ...) +(FusedMultiplyAddSub213Float64x8 ...) => (VFMADDSUB213PD512 ...) +(FusedMultiplyAddSub231Float32x16 ...) => (VFMADDSUB231PS512 ...) +(FusedMultiplyAddSub231Float32x4 ...) => (VFMADDSUB231PS128 ...) +(FusedMultiplyAddSub231Float32x8 ...) => (VFMADDSUB231PS256 ...) +(FusedMultiplyAddSub231Float64x2 ...) => (VFMADDSUB231PD128 ...) +(FusedMultiplyAddSub231Float64x4 ...) => (VFMADDSUB231PD256 ...) +(FusedMultiplyAddSub231Float64x8 ...) => (VFMADDSUB231PD512 ...) +(FusedMultiplySub132Float32x16 ...) => (VFMSUB132PS512 ...) +(FusedMultiplySub132Float32x4 ...) => (VFMSUB132PS128 ...) +(FusedMultiplySub132Float32x8 ...) => (VFMSUB132PS256 ...) +(FusedMultiplySub132Float64x2 ...) => (VFMSUB132PD128 ...) +(FusedMultiplySub132Float64x4 ...) => (VFMSUB132PD256 ...) +(FusedMultiplySub132Float64x8 ...) => (VFMSUB132PD512 ...) +(FusedMultiplySub213Float32x16 ...) => (VFMSUB213PS512 ...) +(FusedMultiplySub213Float32x4 ...) => (VFMSUB213PS128 ...) +(FusedMultiplySub213Float32x8 ...) => (VFMSUB213PS256 ...) +(FusedMultiplySub213Float64x2 ...) => (VFMSUB213PD128 ...) +(FusedMultiplySub213Float64x4 ...) => (VFMSUB213PD256 ...) +(FusedMultiplySub213Float64x8 ...) => (VFMSUB213PD512 ...) +(FusedMultiplySub231Float32x16 ...) => (VFMSUB231PS512 ...) +(FusedMultiplySub231Float32x4 ...) => (VFMSUB231PS128 ...) +(FusedMultiplySub231Float32x8 ...) => (VFMSUB231PS256 ...) +(FusedMultiplySub231Float64x2 ...) => (VFMSUB231PD128 ...) +(FusedMultiplySub231Float64x4 ...) => (VFMSUB231PD256 ...) +(FusedMultiplySub231Float64x8 ...) => (VFMSUB231PD512 ...) +(FusedMultiplySubAdd132Float32x16 ...) => (VFMSUBADD132PS512 ...) +(FusedMultiplySubAdd132Float32x4 ...) => (VFMSUBADD132PS128 ...) +(FusedMultiplySubAdd132Float32x8 ...) => (VFMSUBADD132PS256 ...) +(FusedMultiplySubAdd132Float64x2 ...) => (VFMSUBADD132PD128 ...) +(FusedMultiplySubAdd132Float64x4 ...) => (VFMSUBADD132PD256 ...) +(FusedMultiplySubAdd132Float64x8 ...) => (VFMSUBADD132PD512 ...) +(FusedMultiplySubAdd213Float32x16 ...) => (VFMSUBADD213PS512 ...) +(FusedMultiplySubAdd213Float32x4 ...) => (VFMSUBADD213PS128 ...) +(FusedMultiplySubAdd213Float32x8 ...) => (VFMSUBADD213PS256 ...) +(FusedMultiplySubAdd213Float64x2 ...) => (VFMSUBADD213PD128 ...) +(FusedMultiplySubAdd213Float64x4 ...) => (VFMSUBADD213PD256 ...) +(FusedMultiplySubAdd213Float64x8 ...) => (VFMSUBADD213PD512 ...) +(FusedMultiplySubAdd231Float32x16 ...) => (VFMSUBADD231PS512 ...) +(FusedMultiplySubAdd231Float32x4 ...) => (VFMSUBADD231PS128 ...) +(FusedMultiplySubAdd231Float32x8 ...) => (VFMSUBADD231PS256 ...) +(FusedMultiplySubAdd231Float64x2 ...) => (VFMSUBADD231PD128 ...) +(FusedMultiplySubAdd231Float64x4 ...) => (VFMSUBADD231PD256 ...) +(FusedMultiplySubAdd231Float64x8 ...) => (VFMSUBADD231PD512 ...) +(FusedNegativeMultiplyAdd132Float32x16 ...) => (VFNMADD132PS512 ...) +(FusedNegativeMultiplyAdd132Float32x4 ...) => (VFNMADD132PS128 ...) +(FusedNegativeMultiplyAdd132Float32x8 ...) => (VFNMADD132PS256 ...) +(FusedNegativeMultiplyAdd132Float64x2 ...) => (VFNMADD132PD128 ...) +(FusedNegativeMultiplyAdd132Float64x4 ...) => (VFNMADD132PD256 ...) +(FusedNegativeMultiplyAdd132Float64x8 ...) => (VFNMADD132PD512 ...) +(FusedNegativeMultiplyAdd213Float32x16 ...) => (VFNMADD213PS512 ...) +(FusedNegativeMultiplyAdd213Float32x4 ...) => (VFNMADD213PS128 ...) +(FusedNegativeMultiplyAdd213Float32x8 ...) => (VFNMADD213PS256 ...) +(FusedNegativeMultiplyAdd213Float64x2 ...) => (VFNMADD213PD128 ...) +(FusedNegativeMultiplyAdd213Float64x4 ...) => (VFNMADD213PD256 ...) +(FusedNegativeMultiplyAdd213Float64x8 ...) => (VFNMADD213PD512 ...) +(FusedNegativeMultiplyAdd231Float32x16 ...) => (VFNMADD231PS512 ...) +(FusedNegativeMultiplyAdd231Float32x4 ...) => (VFNMADD231PS128 ...) +(FusedNegativeMultiplyAdd231Float32x8 ...) => (VFNMADD231PS256 ...) +(FusedNegativeMultiplyAdd231Float64x2 ...) => (VFNMADD231PD128 ...) +(FusedNegativeMultiplyAdd231Float64x4 ...) => (VFNMADD231PD256 ...) +(FusedNegativeMultiplyAdd231Float64x8 ...) => (VFNMADD231PD512 ...) +(FusedNegativeMultiplySub132Float32x16 ...) => (VFNMSUB132PS512 ...) +(FusedNegativeMultiplySub132Float32x4 ...) => (VFNMSUB132PS128 ...) +(FusedNegativeMultiplySub132Float32x8 ...) => (VFNMSUB132PS256 ...) +(FusedNegativeMultiplySub132Float64x2 ...) => (VFNMSUB132PD128 ...) +(FusedNegativeMultiplySub132Float64x4 ...) => (VFNMSUB132PD256 ...) +(FusedNegativeMultiplySub132Float64x8 ...) => (VFNMSUB132PD512 ...) +(FusedNegativeMultiplySub213Float32x16 ...) => (VFNMSUB213PS512 ...) +(FusedNegativeMultiplySub213Float32x4 ...) => (VFNMSUB213PS128 ...) +(FusedNegativeMultiplySub213Float32x8 ...) => (VFNMSUB213PS256 ...) +(FusedNegativeMultiplySub213Float64x2 ...) => (VFNMSUB213PD128 ...) +(FusedNegativeMultiplySub213Float64x4 ...) => (VFNMSUB213PD256 ...) +(FusedNegativeMultiplySub213Float64x8 ...) => (VFNMSUB213PD512 ...) +(FusedNegativeMultiplySub231Float32x16 ...) => (VFNMSUB231PS512 ...) +(FusedNegativeMultiplySub231Float32x4 ...) => (VFNMSUB231PS128 ...) +(FusedNegativeMultiplySub231Float32x8 ...) => (VFNMSUB231PS256 ...) +(FusedNegativeMultiplySub231Float64x2 ...) => (VFNMSUB231PD128 ...) +(FusedNegativeMultiplySub231Float64x4 ...) => (VFNMSUB231PD256 ...) +(FusedNegativeMultiplySub231Float64x8 ...) => (VFNMSUB231PD512 ...) +(GreaterFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [6] x y)) +(GreaterFloat32x4 x y) => (VCMPPS128 [6] x y) +(GreaterFloat32x8 x y) => (VCMPPS256 [6] x y) +(GreaterFloat64x2 x y) => (VCMPPD128 [6] x y) +(GreaterFloat64x4 x y) => (VCMPPD256 [6] x y) +(GreaterFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [6] x y)) +(GreaterInt16x16 ...) => (VPCMPGTW256 ...) +(GreaterInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPGTW512 x y)) +(GreaterInt16x8 ...) => (VPCMPGTW128 ...) +(GreaterInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPGTD512 x y)) +(GreaterInt32x4 ...) => (VPCMPGTD128 ...) +(GreaterInt32x8 ...) => (VPCMPGTD256 ...) +(GreaterInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPGTQ128 x y)) +(GreaterInt64x4 ...) => (VPCMPGTQ256 ...) +(GreaterInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPGTQ512 x y)) +(GreaterInt8x16 ...) => (VPCMPGTB128 ...) +(GreaterInt8x32 ...) => (VPCMPGTB256 ...) +(GreaterInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPGTB512 x y)) +(GreaterUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [6] x y)) +(GreaterUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [6] x y)) +(GreaterUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [6] x y)) +(GreaterUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [6] x y)) +(GreaterUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [6] x y)) +(GreaterUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [6] x y)) +(GreaterUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [6] x y)) +(GreaterUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [6] x y)) +(GreaterUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [6] x y)) +(GreaterUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [6] x y)) +(GreaterUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [6] x y)) +(GreaterUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [6] x y)) +(GreaterEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [5] x y)) +(GreaterEqualFloat32x4 x y) => (VCMPPS128 [5] x y) +(GreaterEqualFloat32x8 x y) => (VCMPPS256 [5] x y) +(GreaterEqualFloat64x2 x y) => (VCMPPD128 [5] x y) +(GreaterEqualFloat64x4 x y) => (VCMPPD256 [5] x y) +(GreaterEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [5] x y)) +(GreaterEqualInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [5] x y)) +(GreaterEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [5] x y)) +(GreaterEqualInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [5] x y)) +(GreaterEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [5] x y)) +(GreaterEqualInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [5] x y)) +(GreaterEqualInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [5] x y)) +(GreaterEqualInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [5] x y)) +(GreaterEqualInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [5] x y)) +(GreaterEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [5] x y)) +(GreaterEqualInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [5] x y)) +(GreaterEqualInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [5] x y)) +(GreaterEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [5] x y)) +(GreaterEqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [5] x y)) +(GreaterEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [5] x y)) +(GreaterEqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [5] x y)) +(GreaterEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [5] x y)) +(GreaterEqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [5] x y)) +(GreaterEqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [5] x y)) +(GreaterEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [5] x y)) +(GreaterEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [5] x y)) +(GreaterEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [5] x y)) +(GreaterEqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [5] x y)) +(GreaterEqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [5] x y)) +(GreaterEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [5] x y)) +(IsNanFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [3] x y)) +(IsNanFloat32x4 x y) => (VCMPPS128 [3] x y) +(IsNanFloat32x8 x y) => (VCMPPS256 [3] x y) +(IsNanFloat64x2 x y) => (VCMPPD128 [3] x y) +(IsNanFloat64x4 x y) => (VCMPPD256 [3] x y) +(IsNanFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [3] x y)) +(LessFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [1] x y)) +(LessFloat32x4 x y) => (VCMPPS128 [1] x y) +(LessFloat32x8 x y) => (VCMPPS256 [1] x y) +(LessFloat64x2 x y) => (VCMPPD128 [1] x y) +(LessFloat64x4 x y) => (VCMPPD256 [1] x y) +(LessFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [1] x y)) +(LessInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [1] x y)) +(LessInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [1] x y)) +(LessInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [1] x y)) +(LessInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [1] x y)) +(LessInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [1] x y)) +(LessInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [1] x y)) +(LessInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [1] x y)) +(LessInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [1] x y)) +(LessInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [1] x y)) +(LessInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [1] x y)) +(LessInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [1] x y)) +(LessInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [1] x y)) +(LessUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [1] x y)) +(LessUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [1] x y)) +(LessUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [1] x y)) +(LessUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [1] x y)) +(LessUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [1] x y)) +(LessUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [1] x y)) +(LessUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [1] x y)) +(LessUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [1] x y)) +(LessUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y)) +(LessUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [1] x y)) +(LessUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [1] x y)) +(LessUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [1] x y)) +(LessEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [2] x y)) +(LessEqualFloat32x4 x y) => (VCMPPS128 [2] x y) +(LessEqualFloat32x8 x y) => (VCMPPS256 [2] x y) +(LessEqualFloat64x2 x y) => (VCMPPD128 [2] x y) +(LessEqualFloat64x4 x y) => (VCMPPD256 [2] x y) +(LessEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [2] x y)) +(LessEqualInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [2] x y)) +(LessEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [2] x y)) +(LessEqualInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [2] x y)) +(LessEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [2] x y)) +(LessEqualInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [2] x y)) +(LessEqualInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [2] x y)) +(LessEqualInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [2] x y)) +(LessEqualInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [2] x y)) +(LessEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [2] x y)) +(LessEqualInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [2] x y)) +(LessEqualInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [2] x y)) +(LessEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [2] x y)) +(LessEqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [2] x y)) +(LessEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [2] x y)) +(LessEqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [2] x y)) +(LessEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [2] x y)) +(LessEqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [2] x y)) +(LessEqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [2] x y)) +(LessEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [2] x y)) +(LessEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [2] x y)) +(LessEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y)) +(LessEqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [2] x y)) +(LessEqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [2] x y)) +(LessEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [2] x y)) +(MaskedAbsoluteInt16x16 x mask) => (VPABSWMasked256 x (VPMOVVec16x16ToM mask)) +(MaskedAbsoluteInt16x32 x mask) => (VPABSWMasked512 x (VPMOVVec16x32ToM mask)) +(MaskedAbsoluteInt16x8 x mask) => (VPABSWMasked128 x (VPMOVVec16x8ToM mask)) +(MaskedAbsoluteInt32x16 x mask) => (VPABSDMasked512 x (VPMOVVec32x16ToM mask)) +(MaskedAbsoluteInt32x4 x mask) => (VPABSDMasked128 x (VPMOVVec32x4ToM mask)) +(MaskedAbsoluteInt32x8 x mask) => (VPABSDMasked256 x (VPMOVVec32x8ToM mask)) +(MaskedAbsoluteInt64x2 x mask) => (VPABSQMasked128 x (VPMOVVec64x2ToM mask)) +(MaskedAbsoluteInt64x4 x mask) => (VPABSQMasked256 x (VPMOVVec64x4ToM mask)) +(MaskedAbsoluteInt64x8 x mask) => (VPABSQMasked512 x (VPMOVVec64x8ToM mask)) +(MaskedAbsoluteInt8x16 x mask) => (VPABSBMasked128 x (VPMOVVec8x16ToM mask)) +(MaskedAbsoluteInt8x32 x mask) => (VPABSBMasked256 x (VPMOVVec8x32ToM mask)) +(MaskedAbsoluteInt8x64 x mask) => (VPABSBMasked512 x (VPMOVVec8x64ToM mask)) +(MaskedAddFloat32x16 x y mask) => (VADDPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAddFloat32x4 x y mask) => (VADDPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAddFloat32x8 x y mask) => (VADDPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAddFloat64x2 x y mask) => (VADDPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAddFloat64x4 x y mask) => (VADDPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAddFloat64x8 x y mask) => (VADDPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAddInt16x16 x y mask) => (VPADDWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedAddInt16x32 x y mask) => (VPADDWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedAddInt16x8 x y mask) => (VPADDWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedAddInt32x16 x y mask) => (VPADDDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAddInt32x4 x y mask) => (VPADDDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAddInt32x8 x y mask) => (VPADDDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAddInt64x2 x y mask) => (VPADDQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAddInt64x4 x y mask) => (VPADDQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAddInt64x8 x y mask) => (VPADDQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAddInt8x16 x y mask) => (VPADDBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedAddInt8x32 x y mask) => (VPADDBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedAddInt8x64 x y mask) => (VPADDBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedAddUint16x16 x y mask) => (VPADDWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedAddUint16x32 x y mask) => (VPADDWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedAddUint16x8 x y mask) => (VPADDWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedAddUint32x16 x y mask) => (VPADDDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAddUint32x4 x y mask) => (VPADDDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAddUint32x8 x y mask) => (VPADDDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAddUint64x2 x y mask) => (VPADDQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAddUint64x4 x y mask) => (VPADDQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAddUint64x8 x y mask) => (VPADDQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAddUint8x16 x y mask) => (VPADDBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedAddUint8x32 x y mask) => (VPADDBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedAddUint8x64 x y mask) => (VPADDBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedAndFloat32x16 x y mask) => (VANDPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAndFloat32x4 x y mask) => (VANDPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAndFloat32x8 x y mask) => (VANDPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAndFloat64x2 x y mask) => (VANDPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAndFloat64x4 x y mask) => (VANDPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAndFloat64x8 x y mask) => (VANDPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAndInt32x16 x y mask) => (VPANDDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAndInt32x4 x y mask) => (VPANDDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAndInt32x8 x y mask) => (VPANDDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAndInt64x2 x y mask) => (VPANDQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAndInt64x4 x y mask) => (VPANDQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAndInt64x8 x y mask) => (VPANDQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAndUint32x16 x y mask) => (VPANDDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAndUint32x4 x y mask) => (VPANDDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAndUint32x8 x y mask) => (VPANDDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAndUint64x2 x y mask) => (VPANDQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAndUint64x4 x y mask) => (VPANDQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAndUint64x8 x y mask) => (VPANDQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAndNotFloat32x16 x y mask) => (VANDNPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAndNotFloat32x4 x y mask) => (VANDNPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAndNotFloat32x8 x y mask) => (VANDNPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAndNotFloat64x2 x y mask) => (VANDNPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAndNotFloat64x4 x y mask) => (VANDNPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAndNotFloat64x8 x y mask) => (VANDNPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAndNotInt32x16 x y mask) => (VPANDNDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAndNotInt32x4 x y mask) => (VPANDNDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAndNotInt32x8 x y mask) => (VPANDNDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAndNotInt64x2 x y mask) => (VPANDNQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAndNotInt64x4 x y mask) => (VPANDNQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAndNotInt64x8 x y mask) => (VPANDNQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedAndNotUint32x16 x y mask) => (VPANDNDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedAndNotUint32x4 x y mask) => (VPANDNDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedAndNotUint32x8 x y mask) => (VPANDNDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedAndNotUint64x2 x y mask) => (VPANDNQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedAndNotUint64x4 x y mask) => (VPANDNQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedAndNotUint64x8 x y mask) => (VPANDNQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedApproximateReciprocalFloat32x16 x mask) => (VRCP14PSMasked512 x (VPMOVVec32x16ToM mask)) +(MaskedApproximateReciprocalFloat32x4 x mask) => (VRCP14PSMasked128 x (VPMOVVec32x4ToM mask)) +(MaskedApproximateReciprocalFloat32x8 x mask) => (VRCP14PSMasked256 x (VPMOVVec32x8ToM mask)) +(MaskedApproximateReciprocalFloat64x2 x mask) => (VRCP14PDMasked128 x (VPMOVVec64x2ToM mask)) +(MaskedApproximateReciprocalFloat64x4 x mask) => (VRCP14PDMasked256 x (VPMOVVec64x4ToM mask)) +(MaskedApproximateReciprocalFloat64x8 x mask) => (VRCP14PDMasked512 x (VPMOVVec64x8ToM mask)) +(MaskedApproximateReciprocalOfSqrtFloat32x16 x mask) => (VRSQRT14PSMasked512 x (VPMOVVec32x16ToM mask)) +(MaskedApproximateReciprocalOfSqrtFloat32x4 x mask) => (VRSQRT14PSMasked128 x (VPMOVVec32x4ToM mask)) +(MaskedApproximateReciprocalOfSqrtFloat32x8 x mask) => (VRSQRT14PSMasked256 x (VPMOVVec32x8ToM mask)) +(MaskedApproximateReciprocalOfSqrtFloat64x2 x mask) => (VRSQRT14PDMasked128 x (VPMOVVec64x2ToM mask)) +(MaskedApproximateReciprocalOfSqrtFloat64x4 x mask) => (VRSQRT14PDMasked256 x (VPMOVVec64x4ToM mask)) +(MaskedApproximateReciprocalOfSqrtFloat64x8 x mask) => (VRSQRT14PDMasked512 x (VPMOVVec64x8ToM mask)) +(MaskedAverageUint16x16 x y mask) => (VPAVGWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedAverageUint16x32 x y mask) => (VPAVGWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedAverageUint16x8 x y mask) => (VPAVGWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedAverageUint8x16 x y mask) => (VPAVGBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedAverageUint8x32 x y mask) => (VPAVGBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedAverageUint8x64 x y mask) => (VPAVGBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedCeilSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+10] x (VPMOVVec32x16ToM mask)) +(MaskedCeilSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+10] x (VPMOVVec32x4ToM mask)) +(MaskedCeilSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+10] x (VPMOVVec32x8ToM mask)) +(MaskedCeilSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+10] x (VPMOVVec64x2ToM mask)) +(MaskedCeilSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+10] x (VPMOVVec64x4ToM mask)) +(MaskedCeilSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+10] x (VPMOVVec64x8ToM mask)) +(MaskedCeilWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+2] x (VPMOVVec32x16ToM mask)) +(MaskedCeilWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+2] x (VPMOVVec32x4ToM mask)) +(MaskedCeilWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+2] x (VPMOVVec32x8ToM mask)) +(MaskedCeilWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+2] x (VPMOVVec64x2ToM mask)) +(MaskedCeilWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+2] x (VPMOVVec64x4ToM mask)) +(MaskedCeilWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+2] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+10] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+10] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+10] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+10] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+10] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+10] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithCeilWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+2] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithCeilWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+2] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithCeilWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+2] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithCeilWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+2] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithCeilWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+2] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithCeilWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+2] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+9] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+9] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+9] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+9] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+9] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+9] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithFloorWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+1] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithFloorWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+1] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithFloorWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+1] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithFloorWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+1] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithFloorWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+1] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithFloorWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+1] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+8] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+8] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+8] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+8] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+8] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+8] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithRoundWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+0] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithRoundWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+0] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithRoundWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+0] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithRoundWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+0] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithRoundWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+0] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithRoundWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+0] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+11] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+11] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+11] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+11] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+11] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+11] x (VPMOVVec64x8ToM mask)) +(MaskedDiffWithTruncWithPrecisionFloat32x16 [a] x mask) => (VREDUCEPSMasked512 [a+3] x (VPMOVVec32x16ToM mask)) +(MaskedDiffWithTruncWithPrecisionFloat32x4 [a] x mask) => (VREDUCEPSMasked128 [a+3] x (VPMOVVec32x4ToM mask)) +(MaskedDiffWithTruncWithPrecisionFloat32x8 [a] x mask) => (VREDUCEPSMasked256 [a+3] x (VPMOVVec32x8ToM mask)) +(MaskedDiffWithTruncWithPrecisionFloat64x2 [a] x mask) => (VREDUCEPDMasked128 [a+3] x (VPMOVVec64x2ToM mask)) +(MaskedDiffWithTruncWithPrecisionFloat64x4 [a] x mask) => (VREDUCEPDMasked256 [a+3] x (VPMOVVec64x4ToM mask)) +(MaskedDiffWithTruncWithPrecisionFloat64x8 [a] x mask) => (VREDUCEPDMasked512 [a+3] x (VPMOVVec64x8ToM mask)) +(MaskedDivFloat32x16 x y mask) => (VDIVPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedDivFloat32x4 x y mask) => (VDIVPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedDivFloat32x8 x y mask) => (VDIVPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedDivFloat64x2 x y mask) => (VDIVPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedDivFloat64x4 x y mask) => (VDIVPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedDivFloat64x8 x y mask) => (VDIVPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedEqualFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [0] x y (VPMOVVec32x16ToM mask))) +(MaskedEqualFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [0] x y (VPMOVVec32x4ToM mask))) +(MaskedEqualFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [0] x y (VPMOVVec32x8ToM mask))) +(MaskedEqualFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [0] x y (VPMOVVec64x2ToM mask))) +(MaskedEqualFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [0] x y (VPMOVVec64x4ToM mask))) +(MaskedEqualFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [0] x y (VPMOVVec64x8ToM mask))) +(MaskedEqualInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPEQWMasked256 x y (VPMOVVec16x16ToM mask))) +(MaskedEqualInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPEQWMasked512 x y (VPMOVVec16x32ToM mask))) +(MaskedEqualInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPEQWMasked128 x y (VPMOVVec16x8ToM mask))) +(MaskedEqualInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPEQDMasked512 x y (VPMOVVec32x16ToM mask))) +(MaskedEqualInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPEQDMasked128 x y (VPMOVVec32x4ToM mask))) +(MaskedEqualInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPEQDMasked256 x y (VPMOVVec32x8ToM mask))) +(MaskedEqualInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPEQQMasked128 x y (VPMOVVec64x2ToM mask))) +(MaskedEqualInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPEQQMasked256 x y (VPMOVVec64x4ToM mask))) +(MaskedEqualInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPEQQMasked512 x y (VPMOVVec64x8ToM mask))) +(MaskedEqualInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPEQBMasked128 x y (VPMOVVec8x16ToM mask))) +(MaskedEqualInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPEQBMasked256 x y (VPMOVVec8x32ToM mask))) +(MaskedEqualInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPEQBMasked512 x y (VPMOVVec8x64ToM mask))) +(MaskedEqualUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [0] x y (VPMOVVec16x16ToM mask))) +(MaskedEqualUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [0] x y (VPMOVVec16x32ToM mask))) +(MaskedEqualUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [0] x y (VPMOVVec16x8ToM mask))) +(MaskedEqualUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [0] x y (VPMOVVec32x16ToM mask))) +(MaskedEqualUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [0] x y (VPMOVVec32x4ToM mask))) +(MaskedEqualUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [0] x y (VPMOVVec32x8ToM mask))) +(MaskedEqualUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [0] x y (VPMOVVec64x2ToM mask))) +(MaskedEqualUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [0] x y (VPMOVVec64x4ToM mask))) +(MaskedEqualUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [0] x y (VPMOVVec64x8ToM mask))) +(MaskedEqualUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [0] x y (VPMOVVec8x16ToM mask))) +(MaskedEqualUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [0] x y (VPMOVVec8x32ToM mask))) +(MaskedEqualUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [0] x y (VPMOVVec8x64ToM mask))) +(MaskedFloorSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+9] x (VPMOVVec32x16ToM mask)) +(MaskedFloorSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+9] x (VPMOVVec32x4ToM mask)) +(MaskedFloorSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+9] x (VPMOVVec32x8ToM mask)) +(MaskedFloorSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+9] x (VPMOVVec64x2ToM mask)) +(MaskedFloorSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+9] x (VPMOVVec64x4ToM mask)) +(MaskedFloorSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+9] x (VPMOVVec64x8ToM mask)) +(MaskedFloorWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+1] x (VPMOVVec32x16ToM mask)) +(MaskedFloorWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+1] x (VPMOVVec32x4ToM mask)) +(MaskedFloorWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+1] x (VPMOVVec32x8ToM mask)) +(MaskedFloorWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM mask)) +(MaskedFloorWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM mask)) +(MaskedFloorWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplyAdd132Float32x16 x y z mask) => (VFMADD132PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplyAdd132Float32x4 x y z mask) => (VFMADD132PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplyAdd132Float32x8 x y z mask) => (VFMADD132PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplyAdd132Float64x2 x y z mask) => (VFMADD132PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplyAdd132Float64x4 x y z mask) => (VFMADD132PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplyAdd132Float64x8 x y z mask) => (VFMADD132PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplyAdd213Float32x16 x y z mask) => (VFMADD213PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplyAdd213Float32x4 x y z mask) => (VFMADD213PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplyAdd213Float32x8 x y z mask) => (VFMADD213PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplyAdd213Float64x2 x y z mask) => (VFMADD213PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplyAdd213Float64x4 x y z mask) => (VFMADD213PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplyAdd213Float64x8 x y z mask) => (VFMADD213PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplyAdd231Float32x16 x y z mask) => (VFMADD231PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplyAdd231Float32x4 x y z mask) => (VFMADD231PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplyAdd231Float32x8 x y z mask) => (VFMADD231PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplyAdd231Float64x2 x y z mask) => (VFMADD231PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplyAdd231Float64x4 x y z mask) => (VFMADD231PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplyAdd231Float64x8 x y z mask) => (VFMADD231PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplyAddSub132Float32x16 x y z mask) => (VFMADDSUB132PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplyAddSub132Float32x4 x y z mask) => (VFMADDSUB132PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplyAddSub132Float32x8 x y z mask) => (VFMADDSUB132PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplyAddSub132Float64x2 x y z mask) => (VFMADDSUB132PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplyAddSub132Float64x4 x y z mask) => (VFMADDSUB132PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplyAddSub132Float64x8 x y z mask) => (VFMADDSUB132PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplyAddSub213Float32x16 x y z mask) => (VFMADDSUB213PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplyAddSub213Float32x4 x y z mask) => (VFMADDSUB213PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplyAddSub213Float32x8 x y z mask) => (VFMADDSUB213PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplyAddSub213Float64x2 x y z mask) => (VFMADDSUB213PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplyAddSub213Float64x4 x y z mask) => (VFMADDSUB213PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplyAddSub213Float64x8 x y z mask) => (VFMADDSUB213PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplyAddSub231Float32x16 x y z mask) => (VFMADDSUB231PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplyAddSub231Float32x4 x y z mask) => (VFMADDSUB231PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplyAddSub231Float32x8 x y z mask) => (VFMADDSUB231PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplyAddSub231Float64x2 x y z mask) => (VFMADDSUB231PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplyAddSub231Float64x4 x y z mask) => (VFMADDSUB231PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplyAddSub231Float64x8 x y z mask) => (VFMADDSUB231PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplySub132Float32x16 x y z mask) => (VFMSUB132PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplySub132Float32x4 x y z mask) => (VFMSUB132PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplySub132Float32x8 x y z mask) => (VFMSUB132PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplySub132Float64x2 x y z mask) => (VFMSUB132PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplySub132Float64x4 x y z mask) => (VFMSUB132PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplySub132Float64x8 x y z mask) => (VFMSUB132PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplySub213Float32x16 x y z mask) => (VFMSUB213PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplySub213Float32x4 x y z mask) => (VFMSUB213PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplySub213Float32x8 x y z mask) => (VFMSUB213PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplySub213Float64x2 x y z mask) => (VFMSUB213PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplySub213Float64x4 x y z mask) => (VFMSUB213PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplySub213Float64x8 x y z mask) => (VFMSUB213PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplySub231Float32x16 x y z mask) => (VFMSUB231PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplySub231Float32x4 x y z mask) => (VFMSUB231PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplySub231Float32x8 x y z mask) => (VFMSUB231PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplySub231Float64x2 x y z mask) => (VFMSUB231PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplySub231Float64x4 x y z mask) => (VFMSUB231PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplySub231Float64x8 x y z mask) => (VFMSUB231PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplySubAdd132Float32x16 x y z mask) => (VFMSUBADD132PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplySubAdd132Float32x4 x y z mask) => (VFMSUBADD132PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplySubAdd132Float32x8 x y z mask) => (VFMSUBADD132PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplySubAdd132Float64x2 x y z mask) => (VFMSUBADD132PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplySubAdd132Float64x4 x y z mask) => (VFMSUBADD132PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplySubAdd132Float64x8 x y z mask) => (VFMSUBADD132PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplySubAdd213Float32x16 x y z mask) => (VFMSUBADD213PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplySubAdd213Float32x4 x y z mask) => (VFMSUBADD213PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplySubAdd213Float32x8 x y z mask) => (VFMSUBADD213PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplySubAdd213Float64x2 x y z mask) => (VFMSUBADD213PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplySubAdd213Float64x4 x y z mask) => (VFMSUBADD213PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplySubAdd213Float64x8 x y z mask) => (VFMSUBADD213PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedMultiplySubAdd231Float32x16 x y z mask) => (VFMSUBADD231PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedMultiplySubAdd231Float32x4 x y z mask) => (VFMSUBADD231PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedMultiplySubAdd231Float32x8 x y z mask) => (VFMSUBADD231PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedMultiplySubAdd231Float64x2 x y z mask) => (VFMSUBADD231PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedMultiplySubAdd231Float64x4 x y z mask) => (VFMSUBADD231PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedMultiplySubAdd231Float64x8 x y z mask) => (VFMSUBADD231PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedNegativeMultiplyAdd132Float32x16 x y z mask) => (VFNMADD132PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedNegativeMultiplyAdd132Float32x4 x y z mask) => (VFNMADD132PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedNegativeMultiplyAdd132Float32x8 x y z mask) => (VFNMADD132PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedNegativeMultiplyAdd132Float64x2 x y z mask) => (VFNMADD132PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedNegativeMultiplyAdd132Float64x4 x y z mask) => (VFNMADD132PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedNegativeMultiplyAdd132Float64x8 x y z mask) => (VFNMADD132PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedNegativeMultiplyAdd213Float32x16 x y z mask) => (VFNMADD213PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedNegativeMultiplyAdd213Float32x4 x y z mask) => (VFNMADD213PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedNegativeMultiplyAdd213Float32x8 x y z mask) => (VFNMADD213PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedNegativeMultiplyAdd213Float64x2 x y z mask) => (VFNMADD213PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedNegativeMultiplyAdd213Float64x4 x y z mask) => (VFNMADD213PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedNegativeMultiplyAdd213Float64x8 x y z mask) => (VFNMADD213PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedNegativeMultiplyAdd231Float32x16 x y z mask) => (VFNMADD231PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedNegativeMultiplyAdd231Float32x4 x y z mask) => (VFNMADD231PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedNegativeMultiplyAdd231Float32x8 x y z mask) => (VFNMADD231PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedNegativeMultiplyAdd231Float64x2 x y z mask) => (VFNMADD231PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedNegativeMultiplyAdd231Float64x4 x y z mask) => (VFNMADD231PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedNegativeMultiplyAdd231Float64x8 x y z mask) => (VFNMADD231PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedNegativeMultiplySub132Float32x16 x y z mask) => (VFNMSUB132PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedNegativeMultiplySub132Float32x4 x y z mask) => (VFNMSUB132PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedNegativeMultiplySub132Float32x8 x y z mask) => (VFNMSUB132PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedNegativeMultiplySub132Float64x2 x y z mask) => (VFNMSUB132PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedNegativeMultiplySub132Float64x4 x y z mask) => (VFNMSUB132PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedNegativeMultiplySub132Float64x8 x y z mask) => (VFNMSUB132PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedNegativeMultiplySub213Float32x16 x y z mask) => (VFNMSUB213PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedNegativeMultiplySub213Float32x4 x y z mask) => (VFNMSUB213PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedNegativeMultiplySub213Float32x8 x y z mask) => (VFNMSUB213PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedNegativeMultiplySub213Float64x2 x y z mask) => (VFNMSUB213PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedNegativeMultiplySub213Float64x4 x y z mask) => (VFNMSUB213PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedNegativeMultiplySub213Float64x8 x y z mask) => (VFNMSUB213PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedFusedNegativeMultiplySub231Float32x16 x y z mask) => (VFNMSUB231PSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedFusedNegativeMultiplySub231Float32x4 x y z mask) => (VFNMSUB231PSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedFusedNegativeMultiplySub231Float32x8 x y z mask) => (VFNMSUB231PSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedFusedNegativeMultiplySub231Float64x2 x y z mask) => (VFNMSUB231PDMasked128 x y z (VPMOVVec64x2ToM mask)) +(MaskedFusedNegativeMultiplySub231Float64x4 x y z mask) => (VFNMSUB231PDMasked256 x y z (VPMOVVec64x4ToM mask)) +(MaskedFusedNegativeMultiplySub231Float64x8 x y z mask) => (VFNMSUB231PDMasked512 x y z (VPMOVVec64x8ToM mask)) +(MaskedGreaterFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [6] x y (VPMOVVec32x16ToM mask))) +(MaskedGreaterFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [6] x y (VPMOVVec32x4ToM mask))) +(MaskedGreaterFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [6] x y (VPMOVVec32x8ToM mask))) +(MaskedGreaterFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [6] x y (VPMOVVec64x2ToM mask))) +(MaskedGreaterFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [6] x y (VPMOVVec64x4ToM mask))) +(MaskedGreaterFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [6] x y (VPMOVVec64x8ToM mask))) +(MaskedGreaterInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPGTWMasked256 x y (VPMOVVec16x16ToM mask))) +(MaskedGreaterInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPGTWMasked512 x y (VPMOVVec16x32ToM mask))) +(MaskedGreaterInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPGTWMasked128 x y (VPMOVVec16x8ToM mask))) +(MaskedGreaterInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPGTDMasked512 x y (VPMOVVec32x16ToM mask))) +(MaskedGreaterInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPGTDMasked128 x y (VPMOVVec32x4ToM mask))) +(MaskedGreaterInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPGTDMasked256 x y (VPMOVVec32x8ToM mask))) +(MaskedGreaterInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPGTQMasked128 x y (VPMOVVec64x2ToM mask))) +(MaskedGreaterInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPGTQMasked256 x y (VPMOVVec64x4ToM mask))) +(MaskedGreaterInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPGTQMasked512 x y (VPMOVVec64x8ToM mask))) +(MaskedGreaterInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPGTBMasked128 x y (VPMOVVec8x16ToM mask))) +(MaskedGreaterInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPGTBMasked256 x y (VPMOVVec8x32ToM mask))) +(MaskedGreaterInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPGTBMasked512 x y (VPMOVVec8x64ToM mask))) +(MaskedGreaterUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [6] x y (VPMOVVec16x16ToM mask))) +(MaskedGreaterUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [6] x y (VPMOVVec16x32ToM mask))) +(MaskedGreaterUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [6] x y (VPMOVVec16x8ToM mask))) +(MaskedGreaterUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [6] x y (VPMOVVec32x16ToM mask))) +(MaskedGreaterUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [6] x y (VPMOVVec32x4ToM mask))) +(MaskedGreaterUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [6] x y (VPMOVVec32x8ToM mask))) +(MaskedGreaterUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [6] x y (VPMOVVec64x2ToM mask))) +(MaskedGreaterUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [6] x y (VPMOVVec64x4ToM mask))) +(MaskedGreaterUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [6] x y (VPMOVVec64x8ToM mask))) +(MaskedGreaterUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [6] x y (VPMOVVec8x16ToM mask))) +(MaskedGreaterUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [6] x y (VPMOVVec8x32ToM mask))) +(MaskedGreaterUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [6] x y (VPMOVVec8x64ToM mask))) +(MaskedGreaterEqualFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [5] x y (VPMOVVec32x16ToM mask))) +(MaskedGreaterEqualFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [5] x y (VPMOVVec32x4ToM mask))) +(MaskedGreaterEqualFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [5] x y (VPMOVVec32x8ToM mask))) +(MaskedGreaterEqualFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [5] x y (VPMOVVec64x2ToM mask))) +(MaskedGreaterEqualFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [5] x y (VPMOVVec64x4ToM mask))) +(MaskedGreaterEqualFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [5] x y (VPMOVVec64x8ToM mask))) +(MaskedGreaterEqualInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [5] x y (VPMOVVec16x16ToM mask))) +(MaskedGreaterEqualInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [5] x y (VPMOVVec16x32ToM mask))) +(MaskedGreaterEqualInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [5] x y (VPMOVVec16x8ToM mask))) +(MaskedGreaterEqualInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [5] x y (VPMOVVec32x16ToM mask))) +(MaskedGreaterEqualInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [5] x y (VPMOVVec32x4ToM mask))) +(MaskedGreaterEqualInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [5] x y (VPMOVVec32x8ToM mask))) +(MaskedGreaterEqualInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [5] x y (VPMOVVec64x2ToM mask))) +(MaskedGreaterEqualInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [5] x y (VPMOVVec64x4ToM mask))) +(MaskedGreaterEqualInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [5] x y (VPMOVVec64x8ToM mask))) +(MaskedGreaterEqualInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [5] x y (VPMOVVec8x16ToM mask))) +(MaskedGreaterEqualInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [5] x y (VPMOVVec8x32ToM mask))) +(MaskedGreaterEqualInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [5] x y (VPMOVVec8x64ToM mask))) +(MaskedGreaterEqualUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [5] x y (VPMOVVec16x16ToM mask))) +(MaskedGreaterEqualUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [5] x y (VPMOVVec16x32ToM mask))) +(MaskedGreaterEqualUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [5] x y (VPMOVVec16x8ToM mask))) +(MaskedGreaterEqualUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [5] x y (VPMOVVec32x16ToM mask))) +(MaskedGreaterEqualUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [5] x y (VPMOVVec32x4ToM mask))) +(MaskedGreaterEqualUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [5] x y (VPMOVVec32x8ToM mask))) +(MaskedGreaterEqualUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [5] x y (VPMOVVec64x2ToM mask))) +(MaskedGreaterEqualUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [5] x y (VPMOVVec64x4ToM mask))) +(MaskedGreaterEqualUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [5] x y (VPMOVVec64x8ToM mask))) +(MaskedGreaterEqualUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [5] x y (VPMOVVec8x16ToM mask))) +(MaskedGreaterEqualUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [5] x y (VPMOVVec8x32ToM mask))) +(MaskedGreaterEqualUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [5] x y (VPMOVVec8x64ToM mask))) +(MaskedIsNanFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [3] x y (VPMOVVec32x16ToM mask))) +(MaskedIsNanFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [3] x y (VPMOVVec32x4ToM mask))) +(MaskedIsNanFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [3] x y (VPMOVVec32x8ToM mask))) +(MaskedIsNanFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [3] x y (VPMOVVec64x2ToM mask))) +(MaskedIsNanFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [3] x y (VPMOVVec64x4ToM mask))) +(MaskedIsNanFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [3] x y (VPMOVVec64x8ToM mask))) +(MaskedLessFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [1] x y (VPMOVVec32x16ToM mask))) +(MaskedLessFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [1] x y (VPMOVVec32x4ToM mask))) +(MaskedLessFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [1] x y (VPMOVVec32x8ToM mask))) +(MaskedLessFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [1] x y (VPMOVVec64x2ToM mask))) +(MaskedLessFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [1] x y (VPMOVVec64x4ToM mask))) +(MaskedLessFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [1] x y (VPMOVVec64x8ToM mask))) +(MaskedLessInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [1] x y (VPMOVVec16x16ToM mask))) +(MaskedLessInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [1] x y (VPMOVVec16x32ToM mask))) +(MaskedLessInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [1] x y (VPMOVVec16x8ToM mask))) +(MaskedLessInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [1] x y (VPMOVVec32x16ToM mask))) +(MaskedLessInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [1] x y (VPMOVVec32x4ToM mask))) +(MaskedLessInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [1] x y (VPMOVVec32x8ToM mask))) +(MaskedLessInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [1] x y (VPMOVVec64x2ToM mask))) +(MaskedLessInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [1] x y (VPMOVVec64x4ToM mask))) +(MaskedLessInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [1] x y (VPMOVVec64x8ToM mask))) +(MaskedLessInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [1] x y (VPMOVVec8x16ToM mask))) +(MaskedLessInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [1] x y (VPMOVVec8x32ToM mask))) +(MaskedLessInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [1] x y (VPMOVVec8x64ToM mask))) +(MaskedLessUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [1] x y (VPMOVVec16x16ToM mask))) +(MaskedLessUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [1] x y (VPMOVVec16x32ToM mask))) +(MaskedLessUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [1] x y (VPMOVVec16x8ToM mask))) +(MaskedLessUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [1] x y (VPMOVVec32x16ToM mask))) +(MaskedLessUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [1] x y (VPMOVVec32x4ToM mask))) +(MaskedLessUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [1] x y (VPMOVVec32x8ToM mask))) +(MaskedLessUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [1] x y (VPMOVVec64x2ToM mask))) +(MaskedLessUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [1] x y (VPMOVVec64x4ToM mask))) +(MaskedLessUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [1] x y (VPMOVVec64x8ToM mask))) +(MaskedLessUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [1] x y (VPMOVVec8x16ToM mask))) +(MaskedLessUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [1] x y (VPMOVVec8x32ToM mask))) +(MaskedLessUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [1] x y (VPMOVVec8x64ToM mask))) +(MaskedLessEqualFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [2] x y (VPMOVVec32x16ToM mask))) +(MaskedLessEqualFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [2] x y (VPMOVVec32x4ToM mask))) +(MaskedLessEqualFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [2] x y (VPMOVVec32x8ToM mask))) +(MaskedLessEqualFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [2] x y (VPMOVVec64x2ToM mask))) +(MaskedLessEqualFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [2] x y (VPMOVVec64x4ToM mask))) +(MaskedLessEqualFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [2] x y (VPMOVVec64x8ToM mask))) +(MaskedLessEqualInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [2] x y (VPMOVVec16x16ToM mask))) +(MaskedLessEqualInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [2] x y (VPMOVVec16x32ToM mask))) +(MaskedLessEqualInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [2] x y (VPMOVVec16x8ToM mask))) +(MaskedLessEqualInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [2] x y (VPMOVVec32x16ToM mask))) +(MaskedLessEqualInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [2] x y (VPMOVVec32x4ToM mask))) +(MaskedLessEqualInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [2] x y (VPMOVVec32x8ToM mask))) +(MaskedLessEqualInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [2] x y (VPMOVVec64x2ToM mask))) +(MaskedLessEqualInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [2] x y (VPMOVVec64x4ToM mask))) +(MaskedLessEqualInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [2] x y (VPMOVVec64x8ToM mask))) +(MaskedLessEqualInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [2] x y (VPMOVVec8x16ToM mask))) +(MaskedLessEqualInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [2] x y (VPMOVVec8x32ToM mask))) +(MaskedLessEqualInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [2] x y (VPMOVVec8x64ToM mask))) +(MaskedLessEqualUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [2] x y (VPMOVVec16x16ToM mask))) +(MaskedLessEqualUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [2] x y (VPMOVVec16x32ToM mask))) +(MaskedLessEqualUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [2] x y (VPMOVVec16x8ToM mask))) +(MaskedLessEqualUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [2] x y (VPMOVVec32x16ToM mask))) +(MaskedLessEqualUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [2] x y (VPMOVVec32x4ToM mask))) +(MaskedLessEqualUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [2] x y (VPMOVVec32x8ToM mask))) +(MaskedLessEqualUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [2] x y (VPMOVVec64x2ToM mask))) +(MaskedLessEqualUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [2] x y (VPMOVVec64x4ToM mask))) +(MaskedLessEqualUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [2] x y (VPMOVVec64x8ToM mask))) +(MaskedLessEqualUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [2] x y (VPMOVVec8x16ToM mask))) +(MaskedLessEqualUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [2] x y (VPMOVVec8x32ToM mask))) +(MaskedLessEqualUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [2] x y (VPMOVVec8x64ToM mask))) +(MaskedMaxFloat32x16 x y mask) => (VMAXPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMaxFloat32x4 x y mask) => (VMAXPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMaxFloat32x8 x y mask) => (VMAXPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMaxFloat64x2 x y mask) => (VMAXPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMaxFloat64x4 x y mask) => (VMAXPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMaxFloat64x8 x y mask) => (VMAXPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMaxInt16x16 x y mask) => (VPMAXSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMaxInt16x32 x y mask) => (VPMAXSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMaxInt16x8 x y mask) => (VPMAXSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMaxInt32x16 x y mask) => (VPMAXSDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMaxInt32x4 x y mask) => (VPMAXSDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMaxInt32x8 x y mask) => (VPMAXSDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMaxInt64x2 x y mask) => (VPMAXSQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMaxInt64x4 x y mask) => (VPMAXSQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMaxInt64x8 x y mask) => (VPMAXSQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMaxInt8x16 x y mask) => (VPMAXSBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedMaxInt8x32 x y mask) => (VPMAXSBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedMaxInt8x64 x y mask) => (VPMAXSBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedMaxUint16x16 x y mask) => (VPMAXUWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMaxUint16x32 x y mask) => (VPMAXUWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMaxUint16x8 x y mask) => (VPMAXUWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMaxUint32x16 x y mask) => (VPMAXUDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMaxUint32x4 x y mask) => (VPMAXUDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMaxUint32x8 x y mask) => (VPMAXUDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMaxUint64x2 x y mask) => (VPMAXUQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMaxUint64x4 x y mask) => (VPMAXUQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMaxUint64x8 x y mask) => (VPMAXUQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMaxUint8x16 x y mask) => (VPMAXUBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedMaxUint8x32 x y mask) => (VPMAXUBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedMaxUint8x64 x y mask) => (VPMAXUBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedMinFloat32x16 x y mask) => (VMINPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMinFloat32x4 x y mask) => (VMINPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMinFloat32x8 x y mask) => (VMINPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMinFloat64x2 x y mask) => (VMINPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMinFloat64x4 x y mask) => (VMINPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMinFloat64x8 x y mask) => (VMINPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMinInt16x16 x y mask) => (VPMINSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMinInt16x32 x y mask) => (VPMINSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMinInt16x8 x y mask) => (VPMINSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMinInt32x16 x y mask) => (VPMINSDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMinInt32x4 x y mask) => (VPMINSDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMinInt32x8 x y mask) => (VPMINSDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMinInt64x2 x y mask) => (VPMINSQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMinInt64x4 x y mask) => (VPMINSQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMinInt64x8 x y mask) => (VPMINSQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMinInt8x16 x y mask) => (VPMINSBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedMinInt8x32 x y mask) => (VPMINSBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedMinInt8x64 x y mask) => (VPMINSBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedMinUint16x16 x y mask) => (VPMINUWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMinUint16x32 x y mask) => (VPMINUWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMinUint16x8 x y mask) => (VPMINUWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMinUint32x16 x y mask) => (VPMINUDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMinUint32x4 x y mask) => (VPMINUDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMinUint32x8 x y mask) => (VPMINUDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMinUint64x2 x y mask) => (VPMINUQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMinUint64x4 x y mask) => (VPMINUQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMinUint64x8 x y mask) => (VPMINUQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMinUint8x16 x y mask) => (VPMINUBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedMinUint8x32 x y mask) => (VPMINUBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedMinUint8x64 x y mask) => (VPMINUBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedMulFloat32x16 x y mask) => (VMULPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMulFloat32x4 x y mask) => (VMULPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMulFloat32x8 x y mask) => (VMULPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMulFloat64x2 x y mask) => (VMULPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMulFloat64x4 x y mask) => (VMULPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMulFloat64x8 x y mask) => (VMULPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMulByPowOf2Float32x16 x y mask) => (VSCALEFPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMulByPowOf2Float32x4 x y mask) => (VSCALEFPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMulByPowOf2Float32x8 x y mask) => (VSCALEFPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMulByPowOf2Float64x2 x y mask) => (VSCALEFPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMulByPowOf2Float64x4 x y mask) => (VSCALEFPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMulByPowOf2Float64x8 x y mask) => (VSCALEFPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMulEvenWidenInt64x2 x y mask) => (VPMULDQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMulEvenWidenInt64x4 x y mask) => (VPMULDQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMulEvenWidenInt64x8 x y mask) => (VPMULDQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMulEvenWidenUint64x2 x y mask) => (VPMULUDQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMulEvenWidenUint64x4 x y mask) => (VPMULUDQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMulEvenWidenUint64x8 x y mask) => (VPMULUDQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedMulHighInt16x16 x y mask) => (VPMULHWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMulHighInt16x32 x y mask) => (VPMULHWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMulHighInt16x8 x y mask) => (VPMULHWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMulHighUint16x16 x y mask) => (VPMULHUWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMulHighUint16x32 x y mask) => (VPMULHUWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMulHighUint16x8 x y mask) => (VPMULHUWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMulLowInt16x16 x y mask) => (VPMULLWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedMulLowInt16x32 x y mask) => (VPMULLWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedMulLowInt16x8 x y mask) => (VPMULLWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedMulLowInt32x16 x y mask) => (VPMULLDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedMulLowInt32x4 x y mask) => (VPMULLDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedMulLowInt32x8 x y mask) => (VPMULLDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedMulLowInt64x2 x y mask) => (VPMULLQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedMulLowInt64x4 x y mask) => (VPMULLQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedMulLowInt64x8 x y mask) => (VPMULLQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedNotEqualFloat32x16 x y mask) => (VPMOVMToVec32x16 (VCMPPSMasked512 [4] x y (VPMOVVec32x16ToM mask))) +(MaskedNotEqualFloat32x4 x y mask) => (VPMOVMToVec32x4 (VCMPPSMasked128 [4] x y (VPMOVVec32x4ToM mask))) +(MaskedNotEqualFloat32x8 x y mask) => (VPMOVMToVec32x8 (VCMPPSMasked256 [4] x y (VPMOVVec32x8ToM mask))) +(MaskedNotEqualFloat64x2 x y mask) => (VPMOVMToVec64x2 (VCMPPDMasked128 [4] x y (VPMOVVec64x2ToM mask))) +(MaskedNotEqualFloat64x4 x y mask) => (VPMOVMToVec64x4 (VCMPPDMasked256 [4] x y (VPMOVVec64x4ToM mask))) +(MaskedNotEqualFloat64x8 x y mask) => (VPMOVMToVec64x8 (VCMPPDMasked512 [4] x y (VPMOVVec64x8ToM mask))) +(MaskedNotEqualInt16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPWMasked256 [4] x y (VPMOVVec16x16ToM mask))) +(MaskedNotEqualInt16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPWMasked512 [4] x y (VPMOVVec16x32ToM mask))) +(MaskedNotEqualInt16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPWMasked128 [4] x y (VPMOVVec16x8ToM mask))) +(MaskedNotEqualInt32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPDMasked512 [4] x y (VPMOVVec32x16ToM mask))) +(MaskedNotEqualInt32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPDMasked128 [4] x y (VPMOVVec32x4ToM mask))) +(MaskedNotEqualInt32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPDMasked256 [4] x y (VPMOVVec32x8ToM mask))) +(MaskedNotEqualInt64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPQMasked128 [4] x y (VPMOVVec64x2ToM mask))) +(MaskedNotEqualInt64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPQMasked256 [4] x y (VPMOVVec64x4ToM mask))) +(MaskedNotEqualInt64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPQMasked512 [4] x y (VPMOVVec64x8ToM mask))) +(MaskedNotEqualInt8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPBMasked128 [4] x y (VPMOVVec8x16ToM mask))) +(MaskedNotEqualInt8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPBMasked256 [4] x y (VPMOVVec8x32ToM mask))) +(MaskedNotEqualInt8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPBMasked512 [4] x y (VPMOVVec8x64ToM mask))) +(MaskedNotEqualUint16x16 x y mask) => (VPMOVMToVec16x16 (VPCMPUWMasked256 [4] x y (VPMOVVec16x16ToM mask))) +(MaskedNotEqualUint16x32 x y mask) => (VPMOVMToVec16x32 (VPCMPUWMasked512 [4] x y (VPMOVVec16x32ToM mask))) +(MaskedNotEqualUint16x8 x y mask) => (VPMOVMToVec16x8 (VPCMPUWMasked128 [4] x y (VPMOVVec16x8ToM mask))) +(MaskedNotEqualUint32x16 x y mask) => (VPMOVMToVec32x16 (VPCMPUDMasked512 [4] x y (VPMOVVec32x16ToM mask))) +(MaskedNotEqualUint32x4 x y mask) => (VPMOVMToVec32x4 (VPCMPUDMasked128 [4] x y (VPMOVVec32x4ToM mask))) +(MaskedNotEqualUint32x8 x y mask) => (VPMOVMToVec32x8 (VPCMPUDMasked256 [4] x y (VPMOVVec32x8ToM mask))) +(MaskedNotEqualUint64x2 x y mask) => (VPMOVMToVec64x2 (VPCMPUQMasked128 [4] x y (VPMOVVec64x2ToM mask))) +(MaskedNotEqualUint64x4 x y mask) => (VPMOVMToVec64x4 (VPCMPUQMasked256 [4] x y (VPMOVVec64x4ToM mask))) +(MaskedNotEqualUint64x8 x y mask) => (VPMOVMToVec64x8 (VPCMPUQMasked512 [4] x y (VPMOVVec64x8ToM mask))) +(MaskedNotEqualUint8x16 x y mask) => (VPMOVMToVec8x16 (VPCMPUBMasked128 [4] x y (VPMOVVec8x16ToM mask))) +(MaskedNotEqualUint8x32 x y mask) => (VPMOVMToVec8x32 (VPCMPUBMasked256 [4] x y (VPMOVVec8x32ToM mask))) +(MaskedNotEqualUint8x64 x y mask) => (VPMOVMToVec8x64 (VPCMPUBMasked512 [4] x y (VPMOVVec8x64ToM mask))) +(MaskedOrFloat32x16 x y mask) => (VORPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedOrFloat32x4 x y mask) => (VORPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedOrFloat32x8 x y mask) => (VORPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedOrFloat64x2 x y mask) => (VORPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedOrFloat64x4 x y mask) => (VORPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedOrFloat64x8 x y mask) => (VORPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedOrInt32x16 x y mask) => (VPORDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedOrInt32x4 x y mask) => (VPORDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedOrInt32x8 x y mask) => (VPORDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedOrInt64x2 x y mask) => (VPORQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedOrInt64x4 x y mask) => (VPORQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedOrInt64x8 x y mask) => (VPORQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedOrUint32x16 x y mask) => (VPORDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedOrUint32x4 x y mask) => (VPORDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedOrUint32x8 x y mask) => (VPORDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedOrUint64x2 x y mask) => (VPORQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedOrUint64x4 x y mask) => (VPORQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedOrUint64x8 x y mask) => (VPORQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedPairDotProdInt16x16 x y mask) => (VPMADDWDMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedPairDotProdInt16x32 x y mask) => (VPMADDWDMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedPairDotProdInt16x8 x y mask) => (VPMADDWDMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedPairDotProdAccumulateInt32x16 x y z mask) => (VPDPWSSDMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedPairDotProdAccumulateInt32x4 x y z mask) => (VPDPWSSDMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedPairDotProdAccumulateInt32x8 x y z mask) => (VPDPWSSDMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedPopCountInt16x16 x mask) => (VPOPCNTWMasked256 x (VPMOVVec16x16ToM mask)) +(MaskedPopCountInt16x32 x mask) => (VPOPCNTWMasked512 x (VPMOVVec16x32ToM mask)) +(MaskedPopCountInt16x8 x mask) => (VPOPCNTWMasked128 x (VPMOVVec16x8ToM mask)) +(MaskedPopCountInt32x16 x mask) => (VPOPCNTDMasked512 x (VPMOVVec32x16ToM mask)) +(MaskedPopCountInt32x4 x mask) => (VPOPCNTDMasked128 x (VPMOVVec32x4ToM mask)) +(MaskedPopCountInt32x8 x mask) => (VPOPCNTDMasked256 x (VPMOVVec32x8ToM mask)) +(MaskedPopCountInt64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM mask)) +(MaskedPopCountInt64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM mask)) +(MaskedPopCountInt64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM mask)) +(MaskedPopCountInt8x16 x mask) => (VPOPCNTBMasked128 x (VPMOVVec8x16ToM mask)) +(MaskedPopCountInt8x32 x mask) => (VPOPCNTBMasked256 x (VPMOVVec8x32ToM mask)) +(MaskedPopCountInt8x64 x mask) => (VPOPCNTBMasked512 x (VPMOVVec8x64ToM mask)) +(MaskedPopCountUint16x16 x mask) => (VPOPCNTWMasked256 x (VPMOVVec16x16ToM mask)) +(MaskedPopCountUint16x32 x mask) => (VPOPCNTWMasked512 x (VPMOVVec16x32ToM mask)) +(MaskedPopCountUint16x8 x mask) => (VPOPCNTWMasked128 x (VPMOVVec16x8ToM mask)) +(MaskedPopCountUint32x16 x mask) => (VPOPCNTDMasked512 x (VPMOVVec32x16ToM mask)) +(MaskedPopCountUint32x4 x mask) => (VPOPCNTDMasked128 x (VPMOVVec32x4ToM mask)) +(MaskedPopCountUint32x8 x mask) => (VPOPCNTDMasked256 x (VPMOVVec32x8ToM mask)) +(MaskedPopCountUint64x2 x mask) => (VPOPCNTQMasked128 x (VPMOVVec64x2ToM mask)) +(MaskedPopCountUint64x4 x mask) => (VPOPCNTQMasked256 x (VPMOVVec64x4ToM mask)) +(MaskedPopCountUint64x8 x mask) => (VPOPCNTQMasked512 x (VPMOVVec64x8ToM mask)) +(MaskedPopCountUint8x16 x mask) => (VPOPCNTBMasked128 x (VPMOVVec8x16ToM mask)) +(MaskedPopCountUint8x32 x mask) => (VPOPCNTBMasked256 x (VPMOVVec8x32ToM mask)) +(MaskedPopCountUint8x64 x mask) => (VPOPCNTBMasked512 x (VPMOVVec8x64ToM mask)) +(MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM mask)) +(MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM mask)) +(MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM mask)) +(MaskedRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+8] x (VPMOVVec64x2ToM mask)) +(MaskedRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+8] x (VPMOVVec64x4ToM mask)) +(MaskedRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+8] x (VPMOVVec64x8ToM mask)) +(MaskedRoundWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM mask)) +(MaskedRoundWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM mask)) +(MaskedRoundWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM mask)) +(MaskedRoundWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM mask)) +(MaskedRoundWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM mask)) +(MaskedRoundWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM mask)) +(MaskedSaturatedAddInt16x16 x y mask) => (VPADDSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSaturatedAddInt16x32 x y mask) => (VPADDSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSaturatedAddInt16x8 x y mask) => (VPADDSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSaturatedAddInt8x16 x y mask) => (VPADDSBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedSaturatedAddInt8x32 x y mask) => (VPADDSBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedSaturatedAddInt8x64 x y mask) => (VPADDSBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedSaturatedAddUint16x16 x y mask) => (VPADDSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSaturatedAddUint16x32 x y mask) => (VPADDSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSaturatedAddUint16x8 x y mask) => (VPADDSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSaturatedAddUint8x16 x y mask) => (VPADDSBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedSaturatedAddUint8x32 x y mask) => (VPADDSBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedSaturatedAddUint8x64 x y mask) => (VPADDSBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedSaturatedPairDotProdAccumulateInt32x16 x y z mask) => (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedSaturatedPairDotProdAccumulateInt32x4 x y z mask) => (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedSaturatedPairDotProdAccumulateInt32x8 x y z mask) => (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedSaturatedSubInt16x16 x y mask) => (VPSUBSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSaturatedSubInt16x32 x y mask) => (VPSUBSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSaturatedSubInt16x8 x y mask) => (VPSUBSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSaturatedSubInt8x16 x y mask) => (VPSUBSBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedSaturatedSubInt8x32 x y mask) => (VPSUBSBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedSaturatedSubInt8x64 x y mask) => (VPSUBSBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedSaturatedSubUint16x16 x y mask) => (VPSUBSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSaturatedSubUint16x32 x y mask) => (VPSUBSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSaturatedSubUint16x8 x y mask) => (VPSUBSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSaturatedSubUint8x16 x y mask) => (VPSUBSBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedSaturatedSubUint8x32 x y mask) => (VPSUBSBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedSaturatedSubUint8x64 x y mask) => (VPSUBSBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedSaturatedUnsignedSignedPairDotProdUint16x16 x y mask) => (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSaturatedUnsignedSignedPairDotProdUint16x32 x y mask) => (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSaturatedUnsignedSignedPairDotProdUint16x8 x y mask) => (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 x y z mask) => (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 x y z mask) => (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 x y z mask) => (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) => (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) => (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) => (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedSqrtFloat32x16 x mask) => (VSQRTPSMasked512 x (VPMOVVec32x16ToM mask)) +(MaskedSqrtFloat32x4 x mask) => (VSQRTPSMasked128 x (VPMOVVec32x4ToM mask)) +(MaskedSqrtFloat32x8 x mask) => (VSQRTPSMasked256 x (VPMOVVec32x8ToM mask)) +(MaskedSqrtFloat64x2 x mask) => (VSQRTPDMasked128 x (VPMOVVec64x2ToM mask)) +(MaskedSqrtFloat64x4 x mask) => (VSQRTPDMasked256 x (VPMOVVec64x4ToM mask)) +(MaskedSqrtFloat64x8 x mask) => (VSQRTPDMasked512 x (VPMOVVec64x8ToM mask)) +(MaskedSubFloat32x16 x y mask) => (VADDPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedSubFloat32x4 x y mask) => (VADDPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedSubFloat32x8 x y mask) => (VADDPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedSubFloat64x2 x y mask) => (VADDPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedSubFloat64x4 x y mask) => (VADDPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedSubFloat64x8 x y mask) => (VADDPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedSubInt16x16 x y mask) => (VPSUBWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSubInt16x32 x y mask) => (VPSUBWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSubInt16x8 x y mask) => (VPSUBWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSubInt32x16 x y mask) => (VPSUBDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedSubInt32x4 x y mask) => (VPSUBDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedSubInt32x8 x y mask) => (VPSUBDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedSubInt64x2 x y mask) => (VPSUBQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedSubInt64x4 x y mask) => (VPSUBQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedSubInt64x8 x y mask) => (VPSUBQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedSubInt8x16 x y mask) => (VPSUBBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedSubInt8x32 x y mask) => (VPSUBBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedSubInt8x64 x y mask) => (VPSUBBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedSubUint16x16 x y mask) => (VPSUBWMasked256 x y (VPMOVVec16x16ToM mask)) +(MaskedSubUint16x32 x y mask) => (VPSUBWMasked512 x y (VPMOVVec16x32ToM mask)) +(MaskedSubUint16x8 x y mask) => (VPSUBWMasked128 x y (VPMOVVec16x8ToM mask)) +(MaskedSubUint32x16 x y mask) => (VPSUBDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedSubUint32x4 x y mask) => (VPSUBDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedSubUint32x8 x y mask) => (VPSUBDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedSubUint64x2 x y mask) => (VPSUBQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedSubUint64x4 x y mask) => (VPSUBQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedSubUint64x8 x y mask) => (VPSUBQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedSubUint8x16 x y mask) => (VPSUBBMasked128 x y (VPMOVVec8x16ToM mask)) +(MaskedSubUint8x32 x y mask) => (VPSUBBMasked256 x y (VPMOVVec8x32ToM mask)) +(MaskedSubUint8x64 x y mask) => (VPSUBBMasked512 x y (VPMOVVec8x64ToM mask)) +(MaskedTruncSuppressExceptionWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+11] x (VPMOVVec32x16ToM mask)) +(MaskedTruncSuppressExceptionWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+11] x (VPMOVVec32x4ToM mask)) +(MaskedTruncSuppressExceptionWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+11] x (VPMOVVec32x8ToM mask)) +(MaskedTruncSuppressExceptionWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+11] x (VPMOVVec64x2ToM mask)) +(MaskedTruncSuppressExceptionWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+11] x (VPMOVVec64x4ToM mask)) +(MaskedTruncSuppressExceptionWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+11] x (VPMOVVec64x8ToM mask)) +(MaskedTruncWithPrecisionFloat32x16 [a] x mask) => (VRNDSCALEPSMasked512 [a+3] x (VPMOVVec32x16ToM mask)) +(MaskedTruncWithPrecisionFloat32x4 [a] x mask) => (VRNDSCALEPSMasked128 [a+3] x (VPMOVVec32x4ToM mask)) +(MaskedTruncWithPrecisionFloat32x8 [a] x mask) => (VRNDSCALEPSMasked256 [a+3] x (VPMOVVec32x8ToM mask)) +(MaskedTruncWithPrecisionFloat64x2 [a] x mask) => (VRNDSCALEPDMasked128 [a+3] x (VPMOVVec64x2ToM mask)) +(MaskedTruncWithPrecisionFloat64x4 [a] x mask) => (VRNDSCALEPDMasked256 [a+3] x (VPMOVVec64x4ToM mask)) +(MaskedTruncWithPrecisionFloat64x8 [a] x mask) => (VRNDSCALEPDMasked512 [a+3] x (VPMOVVec64x8ToM mask)) +(MaskedUnsignedSignedQuadDotProdAccumulateInt32x16 x y z mask) => (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedUnsignedSignedQuadDotProdAccumulateInt32x4 x y z mask) => (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedUnsignedSignedQuadDotProdAccumulateInt32x8 x y z mask) => (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) => (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM mask)) +(MaskedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) => (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM mask)) +(MaskedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) => (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM mask)) +(MaskedXorFloat32x16 x y mask) => (VXORPSMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedXorFloat32x4 x y mask) => (VXORPSMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedXorFloat32x8 x y mask) => (VXORPSMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedXorFloat64x2 x y mask) => (VXORPDMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedXorFloat64x4 x y mask) => (VXORPDMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedXorFloat64x8 x y mask) => (VXORPDMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedXorInt32x16 x y mask) => (VPXORDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedXorInt32x4 x y mask) => (VPXORDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedXorInt32x8 x y mask) => (VPXORDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedXorInt64x2 x y mask) => (VPXORQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedXorInt64x4 x y mask) => (VPXORQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedXorInt64x8 x y mask) => (VPXORQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaskedXorUint32x16 x y mask) => (VPXORDMasked512 x y (VPMOVVec32x16ToM mask)) +(MaskedXorUint32x4 x y mask) => (VPXORDMasked128 x y (VPMOVVec32x4ToM mask)) +(MaskedXorUint32x8 x y mask) => (VPXORDMasked256 x y (VPMOVVec32x8ToM mask)) +(MaskedXorUint64x2 x y mask) => (VPXORQMasked128 x y (VPMOVVec64x2ToM mask)) +(MaskedXorUint64x4 x y mask) => (VPXORQMasked256 x y (VPMOVVec64x4ToM mask)) +(MaskedXorUint64x8 x y mask) => (VPXORQMasked512 x y (VPMOVVec64x8ToM mask)) +(MaxFloat32x16 ...) => (VMAXPS512 ...) +(MaxFloat32x4 ...) => (VMAXPS128 ...) +(MaxFloat32x8 ...) => (VMAXPS256 ...) +(MaxFloat64x2 ...) => (VMAXPD128 ...) +(MaxFloat64x4 ...) => (VMAXPD256 ...) +(MaxFloat64x8 ...) => (VMAXPD512 ...) +(MaxInt16x16 ...) => (VPMAXSW256 ...) +(MaxInt16x32 ...) => (VPMAXSW512 ...) +(MaxInt16x8 ...) => (VPMAXSW128 ...) +(MaxInt32x16 ...) => (VPMAXSD512 ...) +(MaxInt32x4 ...) => (VPMAXSD128 ...) +(MaxInt32x8 ...) => (VPMAXSD256 ...) +(MaxInt64x2 ...) => (VPMAXSQ128 ...) +(MaxInt64x4 ...) => (VPMAXSQ256 ...) +(MaxInt64x8 ...) => (VPMAXSQ512 ...) +(MaxInt8x16 ...) => (VPMAXSB128 ...) +(MaxInt8x32 ...) => (VPMAXSB256 ...) +(MaxInt8x64 ...) => (VPMAXSB512 ...) +(MaxUint16x16 ...) => (VPMAXUW256 ...) +(MaxUint16x32 ...) => (VPMAXUW512 ...) +(MaxUint16x8 ...) => (VPMAXUW128 ...) +(MaxUint32x16 ...) => (VPMAXUD512 ...) +(MaxUint32x4 ...) => (VPMAXUD128 ...) +(MaxUint32x8 ...) => (VPMAXUD256 ...) +(MaxUint64x2 ...) => (VPMAXUQ128 ...) +(MaxUint64x4 ...) => (VPMAXUQ256 ...) +(MaxUint64x8 ...) => (VPMAXUQ512 ...) +(MaxUint8x16 ...) => (VPMAXUB128 ...) +(MaxUint8x32 ...) => (VPMAXUB256 ...) +(MaxUint8x64 ...) => (VPMAXUB512 ...) +(MinFloat32x16 ...) => (VMINPS512 ...) +(MinFloat32x4 ...) => (VMINPS128 ...) +(MinFloat32x8 ...) => (VMINPS256 ...) +(MinFloat64x2 ...) => (VMINPD128 ...) +(MinFloat64x4 ...) => (VMINPD256 ...) +(MinFloat64x8 ...) => (VMINPD512 ...) +(MinInt16x16 ...) => (VPMINSW256 ...) +(MinInt16x32 ...) => (VPMINSW512 ...) +(MinInt16x8 ...) => (VPMINSW128 ...) +(MinInt32x16 ...) => (VPMINSD512 ...) +(MinInt32x4 ...) => (VPMINSD128 ...) +(MinInt32x8 ...) => (VPMINSD256 ...) +(MinInt64x2 ...) => (VPMINSQ128 ...) +(MinInt64x4 ...) => (VPMINSQ256 ...) +(MinInt64x8 ...) => (VPMINSQ512 ...) +(MinInt8x16 ...) => (VPMINSB128 ...) +(MinInt8x32 ...) => (VPMINSB256 ...) +(MinInt8x64 ...) => (VPMINSB512 ...) +(MinUint16x16 ...) => (VPMINUW256 ...) +(MinUint16x32 ...) => (VPMINUW512 ...) +(MinUint16x8 ...) => (VPMINUW128 ...) +(MinUint32x16 ...) => (VPMINUD512 ...) +(MinUint32x4 ...) => (VPMINUD128 ...) +(MinUint32x8 ...) => (VPMINUD256 ...) +(MinUint64x2 ...) => (VPMINUQ128 ...) +(MinUint64x4 ...) => (VPMINUQ256 ...) +(MinUint64x8 ...) => (VPMINUQ512 ...) +(MinUint8x16 ...) => (VPMINUB128 ...) +(MinUint8x32 ...) => (VPMINUB256 ...) +(MinUint8x64 ...) => (VPMINUB512 ...) +(MulFloat32x16 ...) => (VMULPS512 ...) +(MulFloat32x4 ...) => (VMULPS128 ...) +(MulFloat32x8 ...) => (VMULPS256 ...) +(MulFloat64x2 ...) => (VMULPD128 ...) +(MulFloat64x4 ...) => (VMULPD256 ...) +(MulFloat64x8 ...) => (VMULPD512 ...) +(MulByPowOf2Float32x16 ...) => (VSCALEFPS512 ...) +(MulByPowOf2Float32x4 ...) => (VSCALEFPS128 ...) +(MulByPowOf2Float32x8 ...) => (VSCALEFPS256 ...) +(MulByPowOf2Float64x2 ...) => (VSCALEFPD128 ...) +(MulByPowOf2Float64x4 ...) => (VSCALEFPD256 ...) +(MulByPowOf2Float64x8 ...) => (VSCALEFPD512 ...) +(MulEvenWidenInt32x4 ...) => (VPMULDQ128 ...) +(MulEvenWidenInt32x8 ...) => (VPMULDQ256 ...) +(MulEvenWidenInt64x2 ...) => (VPMULDQ128 ...) +(MulEvenWidenInt64x4 ...) => (VPMULDQ256 ...) +(MulEvenWidenInt64x8 ...) => (VPMULDQ512 ...) +(MulEvenWidenUint32x4 ...) => (VPMULUDQ128 ...) +(MulEvenWidenUint32x8 ...) => (VPMULUDQ256 ...) +(MulEvenWidenUint64x2 ...) => (VPMULUDQ128 ...) +(MulEvenWidenUint64x4 ...) => (VPMULUDQ256 ...) +(MulEvenWidenUint64x8 ...) => (VPMULUDQ512 ...) +(MulHighInt16x16 ...) => (VPMULHW256 ...) +(MulHighInt16x32 ...) => (VPMULHW512 ...) +(MulHighInt16x8 ...) => (VPMULHW128 ...) +(MulHighUint16x16 ...) => (VPMULHUW256 ...) +(MulHighUint16x32 ...) => (VPMULHUW512 ...) +(MulHighUint16x8 ...) => (VPMULHUW128 ...) +(MulLowInt16x16 ...) => (VPMULLW256 ...) +(MulLowInt16x32 ...) => (VPMULLW512 ...) +(MulLowInt16x8 ...) => (VPMULLW128 ...) +(MulLowInt32x16 ...) => (VPMULLD512 ...) +(MulLowInt32x4 ...) => (VPMULLD128 ...) +(MulLowInt32x8 ...) => (VPMULLD256 ...) +(MulLowInt64x2 ...) => (VPMULLQ128 ...) +(MulLowInt64x4 ...) => (VPMULLQ256 ...) +(MulLowInt64x8 ...) => (VPMULLQ512 ...) +(NotEqualFloat32x16 x y) => (VPMOVMToVec32x16 (VCMPPS512 [4] x y)) +(NotEqualFloat32x4 x y) => (VCMPPS128 [4] x y) +(NotEqualFloat32x8 x y) => (VCMPPS256 [4] x y) +(NotEqualFloat64x2 x y) => (VCMPPD128 [4] x y) +(NotEqualFloat64x4 x y) => (VCMPPD256 [4] x y) +(NotEqualFloat64x8 x y) => (VPMOVMToVec64x8 (VCMPPD512 [4] x y)) +(NotEqualInt16x16 x y) => (VPMOVMToVec16x16 (VPCMPW256 [4] x y)) +(NotEqualInt16x32 x y) => (VPMOVMToVec16x32 (VPCMPW512 [4] x y)) +(NotEqualInt16x8 x y) => (VPMOVMToVec16x8 (VPCMPW128 [4] x y)) +(NotEqualInt32x16 x y) => (VPMOVMToVec32x16 (VPCMPD512 [4] x y)) +(NotEqualInt32x4 x y) => (VPMOVMToVec32x4 (VPCMPD128 [4] x y)) +(NotEqualInt32x8 x y) => (VPMOVMToVec32x8 (VPCMPD256 [4] x y)) +(NotEqualInt64x2 x y) => (VPMOVMToVec64x2 (VPCMPQ128 [4] x y)) +(NotEqualInt64x4 x y) => (VPMOVMToVec64x4 (VPCMPQ256 [4] x y)) +(NotEqualInt64x8 x y) => (VPMOVMToVec64x8 (VPCMPQ512 [4] x y)) +(NotEqualInt8x16 x y) => (VPMOVMToVec8x16 (VPCMPB128 [4] x y)) +(NotEqualInt8x32 x y) => (VPMOVMToVec8x32 (VPCMPB256 [4] x y)) +(NotEqualInt8x64 x y) => (VPMOVMToVec8x64 (VPCMPB512 [4] x y)) +(NotEqualUint16x16 x y) => (VPMOVMToVec16x16 (VPCMPUW256 [4] x y)) +(NotEqualUint16x32 x y) => (VPMOVMToVec16x32 (VPCMPUW512 [4] x y)) +(NotEqualUint16x8 x y) => (VPMOVMToVec16x8 (VPCMPUW128 [4] x y)) +(NotEqualUint32x16 x y) => (VPMOVMToVec32x16 (VPCMPUD512 [4] x y)) +(NotEqualUint32x4 x y) => (VPMOVMToVec32x4 (VPCMPUD128 [4] x y)) +(NotEqualUint32x8 x y) => (VPMOVMToVec32x8 (VPCMPUD256 [4] x y)) +(NotEqualUint64x2 x y) => (VPMOVMToVec64x2 (VPCMPUQ128 [4] x y)) +(NotEqualUint64x4 x y) => (VPMOVMToVec64x4 (VPCMPUQ256 [4] x y)) +(NotEqualUint64x8 x y) => (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y)) +(NotEqualUint8x16 x y) => (VPMOVMToVec8x16 (VPCMPUB128 [4] x y)) +(NotEqualUint8x32 x y) => (VPMOVMToVec8x32 (VPCMPUB256 [4] x y)) +(NotEqualUint8x64 x y) => (VPMOVMToVec8x64 (VPCMPUB512 [4] x y)) +(OrFloat32x16 ...) => (VORPS512 ...) +(OrFloat32x4 ...) => (VORPS128 ...) +(OrFloat32x8 ...) => (VORPS256 ...) +(OrFloat64x2 ...) => (VORPD128 ...) +(OrFloat64x4 ...) => (VORPD256 ...) +(OrFloat64x8 ...) => (VORPD512 ...) +(OrInt16x16 ...) => (VPOR256 ...) +(OrInt16x8 ...) => (VPOR128 ...) +(OrInt32x16 ...) => (VPORD512 ...) +(OrInt32x4 ...) => (VPOR128 ...) +(OrInt32x8 ...) => (VPOR256 ...) +(OrInt64x2 ...) => (VPOR128 ...) +(OrInt64x4 ...) => (VPOR256 ...) +(OrInt64x8 ...) => (VPORQ512 ...) +(OrInt8x16 ...) => (VPOR128 ...) +(OrInt8x32 ...) => (VPOR256 ...) +(OrUint16x16 ...) => (VPOR256 ...) +(OrUint16x8 ...) => (VPOR128 ...) +(OrUint32x16 ...) => (VPORD512 ...) +(OrUint32x4 ...) => (VPOR128 ...) +(OrUint32x8 ...) => (VPOR256 ...) +(OrUint64x2 ...) => (VPOR128 ...) +(OrUint64x4 ...) => (VPOR256 ...) +(OrUint64x8 ...) => (VPORQ512 ...) +(OrUint8x16 ...) => (VPOR128 ...) +(OrUint8x32 ...) => (VPOR256 ...) +(PairDotProdInt16x16 ...) => (VPMADDWD256 ...) +(PairDotProdInt16x32 ...) => (VPMADDWD512 ...) +(PairDotProdInt16x8 ...) => (VPMADDWD128 ...) +(PairDotProdAccumulateInt32x16 ...) => (VPDPWSSD512 ...) +(PairDotProdAccumulateInt32x4 ...) => (VPDPWSSD128 ...) +(PairDotProdAccumulateInt32x8 ...) => (VPDPWSSD256 ...) +(PairwiseAddFloat32x4 ...) => (VHADDPS128 ...) +(PairwiseAddFloat32x8 ...) => (VHADDPS256 ...) +(PairwiseAddFloat64x2 ...) => (VHADDPD128 ...) +(PairwiseAddFloat64x4 ...) => (VHADDPD256 ...) +(PairwiseAddInt16x16 ...) => (VPHADDW256 ...) +(PairwiseAddInt16x8 ...) => (VPHADDW128 ...) +(PairwiseAddInt32x4 ...) => (VPHADDD128 ...) +(PairwiseAddInt32x8 ...) => (VPHADDD256 ...) +(PairwiseAddUint16x16 ...) => (VPHADDW256 ...) +(PairwiseAddUint16x8 ...) => (VPHADDW128 ...) +(PairwiseAddUint32x4 ...) => (VPHADDD128 ...) +(PairwiseAddUint32x8 ...) => (VPHADDD256 ...) +(PairwiseSubFloat32x4 ...) => (VHSUBPS128 ...) +(PairwiseSubFloat32x8 ...) => (VHSUBPS256 ...) +(PairwiseSubFloat64x2 ...) => (VHSUBPD128 ...) +(PairwiseSubFloat64x4 ...) => (VHSUBPD256 ...) +(PairwiseSubInt16x16 ...) => (VPHSUBW256 ...) +(PairwiseSubInt16x8 ...) => (VPHSUBW128 ...) +(PairwiseSubInt32x4 ...) => (VPHSUBD128 ...) +(PairwiseSubInt32x8 ...) => (VPHSUBD256 ...) +(PairwiseSubUint16x16 ...) => (VPHSUBW256 ...) +(PairwiseSubUint16x8 ...) => (VPHSUBW128 ...) +(PairwiseSubUint32x4 ...) => (VPHSUBD128 ...) +(PairwiseSubUint32x8 ...) => (VPHSUBD256 ...) +(PopCountInt16x16 ...) => (VPOPCNTW256 ...) +(PopCountInt16x32 ...) => (VPOPCNTW512 ...) +(PopCountInt16x8 ...) => (VPOPCNTW128 ...) +(PopCountInt32x16 ...) => (VPOPCNTD512 ...) +(PopCountInt32x4 ...) => (VPOPCNTD128 ...) +(PopCountInt32x8 ...) => (VPOPCNTD256 ...) +(PopCountInt64x2 ...) => (VPOPCNTQ128 ...) +(PopCountInt64x4 ...) => (VPOPCNTQ256 ...) +(PopCountInt64x8 ...) => (VPOPCNTQ512 ...) +(PopCountInt8x16 ...) => (VPOPCNTB128 ...) +(PopCountInt8x32 ...) => (VPOPCNTB256 ...) +(PopCountInt8x64 ...) => (VPOPCNTB512 ...) +(PopCountUint16x16 ...) => (VPOPCNTW256 ...) +(PopCountUint16x32 ...) => (VPOPCNTW512 ...) +(PopCountUint16x8 ...) => (VPOPCNTW128 ...) +(PopCountUint32x16 ...) => (VPOPCNTD512 ...) +(PopCountUint32x4 ...) => (VPOPCNTD128 ...) +(PopCountUint32x8 ...) => (VPOPCNTD256 ...) +(PopCountUint64x2 ...) => (VPOPCNTQ128 ...) +(PopCountUint64x4 ...) => (VPOPCNTQ256 ...) +(PopCountUint64x8 ...) => (VPOPCNTQ512 ...) +(PopCountUint8x16 ...) => (VPOPCNTB128 ...) +(PopCountUint8x32 ...) => (VPOPCNTB256 ...) +(PopCountUint8x64 ...) => (VPOPCNTB512 ...) +(RoundFloat32x4 x) => (VROUNDPS128 [0] x) +(RoundFloat32x8 x) => (VROUNDPS256 [0] x) +(RoundFloat64x2 x) => (VROUNDPD128 [0] x) +(RoundFloat64x4 x) => (VROUNDPD256 [0] x) +(RoundSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+8] x) +(RoundSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+8] x) +(RoundSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+8] x) +(RoundSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+8] x) +(RoundSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+8] x) +(RoundSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+8] x) +(RoundWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+0] x) +(RoundWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+0] x) +(RoundWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+0] x) +(RoundWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+0] x) +(RoundWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+0] x) +(RoundWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+0] x) +(SaturatedAddInt16x16 ...) => (VPADDSW256 ...) +(SaturatedAddInt16x32 ...) => (VPADDSW512 ...) +(SaturatedAddInt16x8 ...) => (VPADDSW128 ...) +(SaturatedAddInt8x16 ...) => (VPADDSB128 ...) +(SaturatedAddInt8x32 ...) => (VPADDSB256 ...) +(SaturatedAddInt8x64 ...) => (VPADDSB512 ...) +(SaturatedAddUint16x16 ...) => (VPADDSW256 ...) +(SaturatedAddUint16x32 ...) => (VPADDSW512 ...) +(SaturatedAddUint16x8 ...) => (VPADDSW128 ...) +(SaturatedAddUint8x16 ...) => (VPADDSB128 ...) +(SaturatedAddUint8x32 ...) => (VPADDSB256 ...) +(SaturatedAddUint8x64 ...) => (VPADDSB512 ...) +(SaturatedPairDotProdAccumulateInt32x16 ...) => (VPDPWSSDS512 ...) +(SaturatedPairDotProdAccumulateInt32x4 ...) => (VPDPWSSDS128 ...) +(SaturatedPairDotProdAccumulateInt32x8 ...) => (VPDPWSSDS256 ...) +(SaturatedPairwiseAddInt16x16 ...) => (VPHADDSW256 ...) +(SaturatedPairwiseAddInt16x8 ...) => (VPHADDSW128 ...) +(SaturatedPairwiseSubInt16x16 ...) => (VPHSUBSW256 ...) +(SaturatedPairwiseSubInt16x8 ...) => (VPHSUBSW128 ...) +(SaturatedSubInt16x16 ...) => (VPSUBSW256 ...) +(SaturatedSubInt16x32 ...) => (VPSUBSW512 ...) +(SaturatedSubInt16x8 ...) => (VPSUBSW128 ...) +(SaturatedSubInt8x16 ...) => (VPSUBSB128 ...) +(SaturatedSubInt8x32 ...) => (VPSUBSB256 ...) +(SaturatedSubInt8x64 ...) => (VPSUBSB512 ...) +(SaturatedSubUint16x16 ...) => (VPSUBSW256 ...) +(SaturatedSubUint16x32 ...) => (VPSUBSW512 ...) +(SaturatedSubUint16x8 ...) => (VPSUBSW128 ...) +(SaturatedSubUint8x16 ...) => (VPSUBSB128 ...) +(SaturatedSubUint8x32 ...) => (VPSUBSB256 ...) +(SaturatedSubUint8x64 ...) => (VPSUBSB512 ...) +(SaturatedUnsignedSignedPairDotProdUint16x16 ...) => (VPMADDUBSW256 ...) +(SaturatedUnsignedSignedPairDotProdUint16x32 ...) => (VPMADDUBSW512 ...) +(SaturatedUnsignedSignedPairDotProdUint16x8 ...) => (VPMADDUBSW128 ...) +(SaturatedUnsignedSignedPairDotProdUint8x16 ...) => (VPMADDUBSW128 ...) +(SaturatedUnsignedSignedPairDotProdUint8x32 ...) => (VPMADDUBSW256 ...) +(SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 ...) => (VPDPBUSDS512 ...) +(SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 ...) => (VPDPBUSDS128 ...) +(SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 ...) => (VPDPBUSDS256 ...) +(SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 ...) => (VPDPBUSDS512 ...) +(SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 ...) => (VPDPBUSDS128 ...) +(SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 ...) => (VPDPBUSDS256 ...) +(SignInt16x16 ...) => (VPSIGNW256 ...) +(SignInt16x8 ...) => (VPSIGNW128 ...) +(SignInt32x4 ...) => (VPSIGND128 ...) +(SignInt32x8 ...) => (VPSIGND256 ...) +(SignInt8x16 ...) => (VPSIGNB128 ...) +(SignInt8x32 ...) => (VPSIGNB256 ...) +(SqrtFloat32x16 ...) => (VSQRTPS512 ...) +(SqrtFloat32x4 ...) => (VSQRTPS128 ...) +(SqrtFloat32x8 ...) => (VSQRTPS256 ...) +(SqrtFloat64x2 ...) => (VSQRTPD128 ...) +(SqrtFloat64x4 ...) => (VSQRTPD256 ...) +(SqrtFloat64x8 ...) => (VSQRTPD512 ...) +(SubFloat32x16 ...) => (VADDPS512 ...) +(SubFloat32x4 ...) => (VADDPS128 ...) +(SubFloat32x8 ...) => (VADDPS256 ...) +(SubFloat64x2 ...) => (VADDPD128 ...) +(SubFloat64x4 ...) => (VADDPD256 ...) +(SubFloat64x8 ...) => (VADDPD512 ...) +(SubInt16x16 ...) => (VPSUBW256 ...) +(SubInt16x32 ...) => (VPSUBW512 ...) +(SubInt16x8 ...) => (VPSUBW128 ...) +(SubInt32x16 ...) => (VPSUBD512 ...) +(SubInt32x4 ...) => (VPSUBD128 ...) +(SubInt32x8 ...) => (VPSUBD256 ...) +(SubInt64x2 ...) => (VPSUBQ128 ...) +(SubInt64x4 ...) => (VPSUBQ256 ...) +(SubInt64x8 ...) => (VPSUBQ512 ...) +(SubInt8x16 ...) => (VPSUBB128 ...) +(SubInt8x32 ...) => (VPSUBB256 ...) +(SubInt8x64 ...) => (VPSUBB512 ...) +(SubUint16x16 ...) => (VPSUBW256 ...) +(SubUint16x32 ...) => (VPSUBW512 ...) +(SubUint16x8 ...) => (VPSUBW128 ...) +(SubUint32x16 ...) => (VPSUBD512 ...) +(SubUint32x4 ...) => (VPSUBD128 ...) +(SubUint32x8 ...) => (VPSUBD256 ...) +(SubUint64x2 ...) => (VPSUBQ128 ...) +(SubUint64x4 ...) => (VPSUBQ256 ...) +(SubUint64x8 ...) => (VPSUBQ512 ...) +(SubUint8x16 ...) => (VPSUBB128 ...) +(SubUint8x32 ...) => (VPSUBB256 ...) +(SubUint8x64 ...) => (VPSUBB512 ...) +(TruncFloat32x4 x) => (VROUNDPS128 [3] x) +(TruncFloat32x8 x) => (VROUNDPS256 [3] x) +(TruncFloat64x2 x) => (VROUNDPD128 [3] x) +(TruncFloat64x4 x) => (VROUNDPD256 [3] x) +(TruncSuppressExceptionWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+11] x) +(TruncSuppressExceptionWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+11] x) +(TruncSuppressExceptionWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+11] x) +(TruncSuppressExceptionWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+11] x) +(TruncSuppressExceptionWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+11] x) +(TruncSuppressExceptionWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+11] x) +(TruncWithPrecisionFloat32x16 [a] x) => (VRNDSCALEPS512 [a+3] x) +(TruncWithPrecisionFloat32x4 [a] x) => (VRNDSCALEPS128 [a+3] x) +(TruncWithPrecisionFloat32x8 [a] x) => (VRNDSCALEPS256 [a+3] x) +(TruncWithPrecisionFloat64x2 [a] x) => (VRNDSCALEPD128 [a+3] x) +(TruncWithPrecisionFloat64x4 [a] x) => (VRNDSCALEPD256 [a+3] x) +(TruncWithPrecisionFloat64x8 [a] x) => (VRNDSCALEPD512 [a+3] x) +(UnsignedSignedQuadDotProdAccumulateInt32x16 ...) => (VPDPBUSD512 ...) +(UnsignedSignedQuadDotProdAccumulateInt32x4 ...) => (VPDPBUSD128 ...) +(UnsignedSignedQuadDotProdAccumulateInt32x8 ...) => (VPDPBUSD256 ...) +(UnsignedSignedQuadDotProdAccumulateUint32x16 ...) => (VPDPBUSD512 ...) +(UnsignedSignedQuadDotProdAccumulateUint32x4 ...) => (VPDPBUSD128 ...) +(UnsignedSignedQuadDotProdAccumulateUint32x8 ...) => (VPDPBUSD256 ...) +(XorFloat32x16 ...) => (VXORPS512 ...) +(XorFloat32x4 ...) => (VXORPS128 ...) +(XorFloat32x8 ...) => (VXORPS256 ...) +(XorFloat64x2 ...) => (VXORPD128 ...) +(XorFloat64x4 ...) => (VXORPD256 ...) +(XorFloat64x8 ...) => (VXORPD512 ...) +(XorInt16x16 ...) => (VPXOR256 ...) +(XorInt16x8 ...) => (VPXOR128 ...) +(XorInt32x16 ...) => (VPXORD512 ...) +(XorInt32x4 ...) => (VPXOR128 ...) +(XorInt32x8 ...) => (VPXOR256 ...) +(XorInt64x2 ...) => (VPXOR128 ...) +(XorInt64x4 ...) => (VPXOR256 ...) +(XorInt64x8 ...) => (VPXORQ512 ...) +(XorInt8x16 ...) => (VPXOR128 ...) +(XorInt8x32 ...) => (VPXOR256 ...) +(XorUint16x16 ...) => (VPXOR256 ...) +(XorUint16x8 ...) => (VPXOR128 ...) +(XorUint32x16 ...) => (VPXORD512 ...) +(XorUint32x4 ...) => (VPXOR128 ...) +(XorUint32x8 ...) => (VPXOR256 ...) +(XorUint64x2 ...) => (VPXOR128 ...) +(XorUint64x4 ...) => (VPXOR256 ...) +(XorUint64x8 ...) => (VPXORQ512 ...) +(XorUint8x16 ...) => (VPXOR128 ...) +(XorUint8x32 ...) => (VPXOR256 ...) diff --git a/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go new file mode 100644 index 00000000000000..651a4365c7c09d --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdAMD64ops.go @@ -0,0 +1,892 @@ +// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT. +package main + +func simdAMD64Ops(fp11, fp21, fp2k1, fp1k1fp1, fp2k1fp1, fp2k1k1, fp31, fp3k1fp1 regInfo) []opData { + return []opData{ + {name: "VADDPS512", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDPS512", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDNPS512", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRCP14PS512", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRSQRT14PS512", argLength: 1, reg: fp11, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VDIVPS512", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VFMADD132PS512", argLength: 3, reg: fp31, asm: "VFMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PS512", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD231PS512", argLength: 3, reg: fp31, asm: "VFMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB132PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB231PS512", argLength: 3, reg: fp31, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB132PS512", argLength: 3, reg: fp31, asm: "VFMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB213PS512", argLength: 3, reg: fp31, asm: "VFMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB231PS512", argLength: 3, reg: fp31, asm: "VFMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD132PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD231PS512", argLength: 3, reg: fp31, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD132PS512", argLength: 3, reg: fp31, asm: "VFNMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD213PS512", argLength: 3, reg: fp31, asm: "VFNMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD231PS512", argLength: 3, reg: fp31, asm: "VFNMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB132PS512", argLength: 3, reg: fp31, asm: "VFNMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB213PS512", argLength: 3, reg: fp31, asm: "VFNMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB231PS512", argLength: 3, reg: fp31, asm: "VFNMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VADDPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDNPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRCP14PSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRSQRT14PSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VDIVPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VFMADD132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB132PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB213PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB231PSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VMAXPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMINPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMULPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSCALEFPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VORPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VORPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSQRTPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VXORPSMasked512", argLength: 3, reg: fp2k1fp1, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMAXPS512", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMINPS512", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMULPS512", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSCALEFPS512", argLength: 2, reg: fp21, asm: "VSCALEFPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VORPS512", argLength: 2, reg: fp21, asm: "VORPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSQRTPS512", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VXORPS512", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VADDPS128", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VADDSUBPS128", argLength: 2, reg: fp21, asm: "VADDSUBPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VANDPS128", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VANDNPS128", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRCP14PS128", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRSQRTPS128", argLength: 1, reg: fp11, asm: "VRSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VDIVPS128", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VFMADD132PS128", argLength: 3, reg: fp31, asm: "VFMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PS128", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD231PS128", argLength: 3, reg: fp31, asm: "VFMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB132PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB231PS128", argLength: 3, reg: fp31, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB132PS128", argLength: 3, reg: fp31, asm: "VFMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB213PS128", argLength: 3, reg: fp31, asm: "VFMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB231PS128", argLength: 3, reg: fp31, asm: "VFMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD132PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD231PS128", argLength: 3, reg: fp31, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD132PS128", argLength: 3, reg: fp31, asm: "VFNMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD213PS128", argLength: 3, reg: fp31, asm: "VFNMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD231PS128", argLength: 3, reg: fp31, asm: "VFNMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB132PS128", argLength: 3, reg: fp31, asm: "VFNMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB213PS128", argLength: 3, reg: fp31, asm: "VFNMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB231PS128", argLength: 3, reg: fp31, asm: "VFNMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VADDPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VANDPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VANDNPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRCP14PSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRSQRT14PSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VDIVPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VFMADD132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB132PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB213PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB231PSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VMAXPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMINPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMULPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VSCALEFPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VORPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VORPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VSQRTPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VXORPSMasked128", argLength: 3, reg: fp2k1fp1, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMAXPS128", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMINPS128", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMULPS128", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VSCALEFPS128", argLength: 2, reg: fp21, asm: "VSCALEFPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VORPS128", argLength: 2, reg: fp21, asm: "VORPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VHADDPS128", argLength: 2, reg: fp21, asm: "VHADDPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VHSUBPS128", argLength: 2, reg: fp21, asm: "VHSUBPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VSQRTPS128", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VXORPS128", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VADDPS256", argLength: 2, reg: fp21, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VADDSUBPS256", argLength: 2, reg: fp21, asm: "VADDSUBPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VANDPS256", argLength: 2, reg: fp21, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VANDNPS256", argLength: 2, reg: fp21, asm: "VANDNPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRCP14PS256", argLength: 1, reg: fp11, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRSQRTPS256", argLength: 1, reg: fp11, asm: "VRSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VDIVPS256", argLength: 2, reg: fp21, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VFMADD132PS256", argLength: 3, reg: fp31, asm: "VFMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PS256", argLength: 3, reg: fp31, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD231PS256", argLength: 3, reg: fp31, asm: "VFMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB132PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB231PS256", argLength: 3, reg: fp31, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB132PS256", argLength: 3, reg: fp31, asm: "VFMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB213PS256", argLength: 3, reg: fp31, asm: "VFMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB231PS256", argLength: 3, reg: fp31, asm: "VFMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD132PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD231PS256", argLength: 3, reg: fp31, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD132PS256", argLength: 3, reg: fp31, asm: "VFNMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD213PS256", argLength: 3, reg: fp31, asm: "VFNMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD231PS256", argLength: 3, reg: fp31, asm: "VFNMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB132PS256", argLength: 3, reg: fp31, asm: "VFNMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB213PS256", argLength: 3, reg: fp31, asm: "VFNMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB231PS256", argLength: 3, reg: fp31, asm: "VFNMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VADDPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VADDPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VANDPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VANDNPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDNPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRCP14PSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRSQRT14PSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VDIVPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VDIVPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VFMADD132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB132PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB213PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB231PSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VMAXPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMINPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMULPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VSCALEFPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VORPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VORPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VSQRTPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VXORPSMasked256", argLength: 3, reg: fp2k1fp1, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMAXPS256", argLength: 2, reg: fp21, asm: "VMAXPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMINPS256", argLength: 2, reg: fp21, asm: "VMINPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMULPS256", argLength: 2, reg: fp21, asm: "VMULPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VSCALEFPS256", argLength: 2, reg: fp21, asm: "VSCALEFPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VORPS256", argLength: 2, reg: fp21, asm: "VORPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VHADDPS256", argLength: 2, reg: fp21, asm: "VHADDPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VHSUBPS256", argLength: 2, reg: fp21, asm: "VHSUBPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VSQRTPS256", argLength: 1, reg: fp11, asm: "VSQRTPS", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VXORPS256", argLength: 2, reg: fp21, asm: "VXORPS", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VADDPD128", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VADDSUBPD128", argLength: 2, reg: fp21, asm: "VADDSUBPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VANDPD128", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VANDNPD128", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRCP14PD128", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRSQRT14PD128", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VDIVPD128", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VFMADD132PD128", argLength: 3, reg: fp31, asm: "VFMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PD128", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD231PD128", argLength: 3, reg: fp31, asm: "VFMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB132PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB231PD128", argLength: 3, reg: fp31, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB132PD128", argLength: 3, reg: fp31, asm: "VFMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB213PD128", argLength: 3, reg: fp31, asm: "VFMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB231PD128", argLength: 3, reg: fp31, asm: "VFMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD132PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD231PD128", argLength: 3, reg: fp31, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD132PD128", argLength: 3, reg: fp31, asm: "VFNMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD213PD128", argLength: 3, reg: fp31, asm: "VFNMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD231PD128", argLength: 3, reg: fp31, asm: "VFNMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB132PD128", argLength: 3, reg: fp31, asm: "VFNMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB213PD128", argLength: 3, reg: fp31, asm: "VFNMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB231PD128", argLength: 3, reg: fp31, asm: "VFNMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VADDPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VANDPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VANDNPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRCP14PDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRSQRT14PDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VDIVPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VFMADD132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADD231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMADDSUB231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUB231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFMSUBADD231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMADD231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB132PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB213PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VFNMSUB231PDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VMAXPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMINPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMULPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VSCALEFPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VORPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VORPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VSQRTPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VXORPDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMAXPD128", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMINPD128", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VMULPD128", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VSCALEFPD128", argLength: 2, reg: fp21, asm: "VSCALEFPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VORPD128", argLength: 2, reg: fp21, asm: "VORPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VHADDPD128", argLength: 2, reg: fp21, asm: "VHADDPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VHSUBPD128", argLength: 2, reg: fp21, asm: "VHSUBPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VSQRTPD128", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VXORPD128", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VADDPD256", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VADDSUBPD256", argLength: 2, reg: fp21, asm: "VADDSUBPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VANDPD256", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VANDNPD256", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRCP14PD256", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRSQRT14PD256", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VDIVPD256", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VFMADD132PD256", argLength: 3, reg: fp31, asm: "VFMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PD256", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD231PD256", argLength: 3, reg: fp31, asm: "VFMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB132PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB231PD256", argLength: 3, reg: fp31, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB132PD256", argLength: 3, reg: fp31, asm: "VFMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB213PD256", argLength: 3, reg: fp31, asm: "VFMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB231PD256", argLength: 3, reg: fp31, asm: "VFMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD132PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD231PD256", argLength: 3, reg: fp31, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD132PD256", argLength: 3, reg: fp31, asm: "VFNMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD213PD256", argLength: 3, reg: fp31, asm: "VFNMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD231PD256", argLength: 3, reg: fp31, asm: "VFNMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB132PD256", argLength: 3, reg: fp31, asm: "VFNMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB213PD256", argLength: 3, reg: fp31, asm: "VFNMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB231PD256", argLength: 3, reg: fp31, asm: "VFNMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VADDPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VANDPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VANDNPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRCP14PDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRSQRT14PDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VDIVPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VFMADD132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADD231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMADDSUB231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUB231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFMSUBADD231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMADD231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB132PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB213PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VFNMSUB231PDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VMAXPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMINPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMULPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VSCALEFPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VORPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VORPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VSQRTPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VXORPDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VXORPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMAXPD256", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMINPD256", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VMULPD256", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VSCALEFPD256", argLength: 2, reg: fp21, asm: "VSCALEFPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VORPD256", argLength: 2, reg: fp21, asm: "VORPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VHADDPD256", argLength: 2, reg: fp21, asm: "VHADDPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VHSUBPD256", argLength: 2, reg: fp21, asm: "VHSUBPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VSQRTPD256", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VXORPD256", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VADDPD512", argLength: 2, reg: fp21, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDPD512", argLength: 2, reg: fp21, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDNPD512", argLength: 2, reg: fp21, asm: "VANDNPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRCP14PD512", argLength: 1, reg: fp11, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRSQRT14PD512", argLength: 1, reg: fp11, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VDIVPD512", argLength: 2, reg: fp21, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VFMADD132PD512", argLength: 3, reg: fp31, asm: "VFMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PD512", argLength: 3, reg: fp31, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD231PD512", argLength: 3, reg: fp31, asm: "VFMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB132PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB231PD512", argLength: 3, reg: fp31, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB132PD512", argLength: 3, reg: fp31, asm: "VFMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB213PD512", argLength: 3, reg: fp31, asm: "VFMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB231PD512", argLength: 3, reg: fp31, asm: "VFMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD132PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD231PD512", argLength: 3, reg: fp31, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD132PD512", argLength: 3, reg: fp31, asm: "VFNMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD213PD512", argLength: 3, reg: fp31, asm: "VFNMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD231PD512", argLength: 3, reg: fp31, asm: "VFNMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB132PD512", argLength: 3, reg: fp31, asm: "VFNMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB213PD512", argLength: 3, reg: fp31, asm: "VFNMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB231PD512", argLength: 3, reg: fp31, asm: "VFNMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VADDPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VADDPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VANDNPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VANDNPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRCP14PDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRCP14PD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VRSQRT14PDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRSQRT14PD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VDIVPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VDIVPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VFMADD132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADD231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMADDSUB231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMADDSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUB231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFMSUBADD231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFMSUBADD231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMADD231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMADD231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB132PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB132PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB213PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB213PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VFNMSUB231PDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VFNMSUB231PD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VMAXPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMINPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMULPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSCALEFPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VORPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VORPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSQRTPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VXORPDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VXORPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMAXPD512", argLength: 2, reg: fp21, asm: "VMAXPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMINPD512", argLength: 2, reg: fp21, asm: "VMINPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VMULPD512", argLength: 2, reg: fp21, asm: "VMULPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSCALEFPD512", argLength: 2, reg: fp21, asm: "VSCALEFPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VORPD512", argLength: 2, reg: fp21, asm: "VORPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VSQRTPD512", argLength: 1, reg: fp11, asm: "VSQRTPD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VXORPD512", argLength: 2, reg: fp21, asm: "VXORPD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPABSW256", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDW256", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPAND256", argLength: 2, reg: fp21, asm: "VPAND", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPANDN256", argLength: 2, reg: fp21, asm: "VPANDN", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQW256", argLength: 2, reg: fp21, asm: "VPCMPEQW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPGTW256", argLength: 2, reg: fp21, asm: "VPCMPGTW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPABSWMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQW", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTW", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULHWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULLWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMADDWDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTWMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXSW256", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSW256", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULHW256", argLength: 2, reg: fp21, asm: "VPMULHW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULLW256", argLength: 2, reg: fp21, asm: "VPMULLW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPOR256", argLength: 2, reg: fp21, asm: "VPOR", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMADDWD256", argLength: 2, reg: fp21, asm: "VPMADDWD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPHADDW256", argLength: 2, reg: fp21, asm: "VPHADDW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPHSUBW256", argLength: 2, reg: fp21, asm: "VPHSUBW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTW256", argLength: 1, reg: fp11, asm: "VPOPCNTW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDSW256", argLength: 2, reg: fp21, asm: "VPADDSW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPHADDSW256", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPHSUBSW256", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBSW256", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSIGNW256", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBW256", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPXOR256", argLength: 2, reg: fp21, asm: "VPXOR", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPABSW512", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDW512", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQW512", argLength: 2, reg: fp2k1, asm: "VPCMPEQW", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTW512", argLength: 2, reg: fp2k1, asm: "VPCMPGTW", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPABSWMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQWMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQW", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTWMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTW", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULHWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULLWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMADDWDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPOPCNTWMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXSW512", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSW512", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULHW512", argLength: 2, reg: fp21, asm: "VPMULHW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULLW512", argLength: 2, reg: fp21, asm: "VPMULLW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMADDWD512", argLength: 2, reg: fp21, asm: "VPMADDWD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPOPCNTW512", argLength: 1, reg: fp11, asm: "VPOPCNTW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDSW512", argLength: 2, reg: fp21, asm: "VPADDSW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBSW512", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBW512", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPABSW128", argLength: 1, reg: fp11, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDW128", argLength: 2, reg: fp21, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPAND128", argLength: 2, reg: fp21, asm: "VPAND", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPANDN128", argLength: 2, reg: fp21, asm: "VPANDN", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQW128", argLength: 2, reg: fp21, asm: "VPCMPEQW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPGTW128", argLength: 2, reg: fp21, asm: "VPCMPGTW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPABSWMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQWMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQW", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTWMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTW", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULHWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULLWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMADDWDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTWMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXSW128", argLength: 2, reg: fp21, asm: "VPMAXSW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSW128", argLength: 2, reg: fp21, asm: "VPMINSW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULHW128", argLength: 2, reg: fp21, asm: "VPMULHW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULLW128", argLength: 2, reg: fp21, asm: "VPMULLW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPOR128", argLength: 2, reg: fp21, asm: "VPOR", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMADDWD128", argLength: 2, reg: fp21, asm: "VPMADDWD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPHADDW128", argLength: 2, reg: fp21, asm: "VPHADDW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPHSUBW128", argLength: 2, reg: fp21, asm: "VPHSUBW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTW128", argLength: 1, reg: fp11, asm: "VPOPCNTW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDSW128", argLength: 2, reg: fp21, asm: "VPADDSW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPHADDSW128", argLength: 2, reg: fp21, asm: "VPHADDSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPHSUBSW128", argLength: 2, reg: fp21, asm: "VPHSUBSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBSW128", argLength: 2, reg: fp21, asm: "VPSUBSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSIGNW128", argLength: 2, reg: fp21, asm: "VPSIGNW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBW128", argLength: 2, reg: fp21, asm: "VPSUBW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPXOR128", argLength: 2, reg: fp21, asm: "VPXOR", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPABSD512", argLength: 1, reg: fp11, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDD512", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDD512", argLength: 2, reg: fp21, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDND512", argLength: 2, reg: fp21, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQD512", argLength: 2, reg: fp2k1, asm: "VPCMPEQD", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTD512", argLength: 2, reg: fp2k1, asm: "VPCMPGTD", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPABSDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDNDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDND", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQDMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQD", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTDMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTD", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULLDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPORDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPDPWSSDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPOPCNTDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPDPWSSDSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPDPBUSDSMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPSUBDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPDPBUSDMasked512", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPXORDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXSD512", argLength: 2, reg: fp21, asm: "VPMAXSD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSD512", argLength: 2, reg: fp21, asm: "VPMINSD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULLD512", argLength: 2, reg: fp21, asm: "VPMULLD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPORD512", argLength: 2, reg: fp21, asm: "VPORD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPDPWSSD512", argLength: 3, reg: fp31, asm: "VPDPWSSD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPOPCNTD512", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPDPWSSDS512", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPDPBUSDS512", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPSUBD512", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPDPBUSD512", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec512", resultInArg0: true}, + {name: "VPXORD512", argLength: 2, reg: fp21, asm: "VPXORD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPABSD128", argLength: 1, reg: fp11, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDD128", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQD128", argLength: 2, reg: fp21, asm: "VPCMPEQD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPGTD128", argLength: 2, reg: fp21, asm: "VPCMPGTD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPABSDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPANDDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPANDNDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDND", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQDMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQD", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTDMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTD", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULLDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPORDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPORD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPDPWSSDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPOPCNTDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPDPWSSDSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPDPBUSDSMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPSUBDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPDPBUSDMasked128", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPXORDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPXORD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXSD128", argLength: 2, reg: fp21, asm: "VPMAXSD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSD128", argLength: 2, reg: fp21, asm: "VPMINSD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULDQ128", argLength: 2, reg: fp21, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULLD128", argLength: 2, reg: fp21, asm: "VPMULLD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPDPWSSD128", argLength: 3, reg: fp31, asm: "VPDPWSSD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPHADDD128", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPHSUBD128", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTD128", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPDPWSSDS128", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPDPBUSDS128", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPSIGND128", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBD128", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPDPBUSD128", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec128", resultInArg0: true}, + {name: "VPABSD256", argLength: 1, reg: fp11, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDD256", argLength: 2, reg: fp21, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQD256", argLength: 2, reg: fp21, asm: "VPCMPEQD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPGTD256", argLength: 2, reg: fp21, asm: "VPCMPGTD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPABSDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPANDDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPANDNDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDND", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQDMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQD", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTDMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTD", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULLDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPORDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPORD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPDPWSSDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPOPCNTDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPDPWSSDSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPDPBUSDSMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPSUBDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPDPBUSDMasked256", argLength: 4, reg: fp3k1fp1, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPXORDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPXORD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXSD256", argLength: 2, reg: fp21, asm: "VPMAXSD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSD256", argLength: 2, reg: fp21, asm: "VPMINSD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULDQ256", argLength: 2, reg: fp21, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULLD256", argLength: 2, reg: fp21, asm: "VPMULLD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPDPWSSD256", argLength: 3, reg: fp31, asm: "VPDPWSSD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPHADDD256", argLength: 2, reg: fp21, asm: "VPHADDD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPHSUBD256", argLength: 2, reg: fp21, asm: "VPHSUBD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTD256", argLength: 1, reg: fp11, asm: "VPOPCNTD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPDPWSSDS256", argLength: 3, reg: fp31, asm: "VPDPWSSDS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPDPBUSDS256", argLength: 3, reg: fp31, asm: "VPDPBUSDS", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPSIGND256", argLength: 2, reg: fp21, asm: "VPSIGND", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBD256", argLength: 2, reg: fp21, asm: "VPSUBD", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPDPBUSD256", argLength: 3, reg: fp31, asm: "VPDPBUSD", commutative: false, typ: "Vec256", resultInArg0: true}, + {name: "VPABSQ128", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDQ128", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQQ128", argLength: 2, reg: fp21, asm: "VPCMPEQQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPGTQ128", argLength: 2, reg: fp2k1, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPABSQMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPANDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPANDNQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPANDNQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQQMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQQ", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTQMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULLQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPORQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPORQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTQMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPXORQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPXORQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXSQ128", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSQ128", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULLQ128", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTQ128", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBQ128", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPABSQ256", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDQ256", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQQ256", argLength: 2, reg: fp21, asm: "VPCMPEQQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPGTQ256", argLength: 2, reg: fp21, asm: "VPCMPGTQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPABSQMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPANDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPANDNQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPANDNQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQQMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQQ", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTQMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULLQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPORQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPORQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTQMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPXORQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPXORQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXSQ256", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSQ256", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULLQ256", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTQ256", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBQ256", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPABSQ512", argLength: 1, reg: fp11, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDQ512", argLength: 2, reg: fp21, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDQ512", argLength: 2, reg: fp21, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDNQ512", argLength: 2, reg: fp21, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQQ512", argLength: 2, reg: fp2k1, asm: "VPCMPEQQ", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTQ512", argLength: 2, reg: fp2k1, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPABSQMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPANDNQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPANDNQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQQMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQQ", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTQMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTQ", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULLQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPORQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPOPCNTQMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPXORQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXSQ512", argLength: 2, reg: fp21, asm: "VPMAXSQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSQ512", argLength: 2, reg: fp21, asm: "VPMINSQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULDQ512", argLength: 2, reg: fp21, asm: "VPMULDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULLQ512", argLength: 2, reg: fp21, asm: "VPMULLQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPORQ512", argLength: 2, reg: fp21, asm: "VPORQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPOPCNTQ512", argLength: 1, reg: fp11, asm: "VPOPCNTQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBQ512", argLength: 2, reg: fp21, asm: "VPSUBQ", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPXORQ512", argLength: 2, reg: fp21, asm: "VPXORQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPABSB128", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDB128", argLength: 2, reg: fp21, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQB128", argLength: 2, reg: fp21, asm: "VPCMPEQB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPGTB128", argLength: 2, reg: fp21, asm: "VPCMPGTB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPABSBMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPABSB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPCMPEQBMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQB", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTBMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTB", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTBMasked128", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBSBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXSB128", argLength: 2, reg: fp21, asm: "VPMAXSB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINSB128", argLength: 2, reg: fp21, asm: "VPMINSB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPOPCNTB128", argLength: 1, reg: fp11, asm: "VPOPCNTB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPADDSB128", argLength: 2, reg: fp21, asm: "VPADDSB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBSB128", argLength: 2, reg: fp21, asm: "VPSUBSB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSIGNB128", argLength: 2, reg: fp21, asm: "VPSIGNB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPSUBB128", argLength: 2, reg: fp21, asm: "VPSUBB", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPABSB256", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDB256", argLength: 2, reg: fp21, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQB256", argLength: 2, reg: fp21, asm: "VPCMPEQB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPGTB256", argLength: 2, reg: fp21, asm: "VPCMPGTB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPABSBMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPABSB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPCMPEQBMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQB", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTBMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTB", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTBMasked256", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBSBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXSB256", argLength: 2, reg: fp21, asm: "VPMAXSB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINSB256", argLength: 2, reg: fp21, asm: "VPMINSB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPOPCNTB256", argLength: 1, reg: fp11, asm: "VPOPCNTB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPADDSB256", argLength: 2, reg: fp21, asm: "VPADDSB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBSB256", argLength: 2, reg: fp21, asm: "VPSUBSB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSIGNB256", argLength: 2, reg: fp21, asm: "VPSIGNB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPSUBB256", argLength: 2, reg: fp21, asm: "VPSUBB", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPABSB512", argLength: 1, reg: fp11, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDB512", argLength: 2, reg: fp21, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQB512", argLength: 2, reg: fp2k1, asm: "VPCMPEQB", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTB512", argLength: 2, reg: fp2k1, asm: "VPCMPGTB", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPABSBMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPABSB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPCMPEQBMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPEQB", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPGTBMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPGTB", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPMAXSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPOPCNTBMasked512", argLength: 2, reg: fp1k1fp1, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBSBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXSB512", argLength: 2, reg: fp21, asm: "VPMAXSB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINSB512", argLength: 2, reg: fp21, asm: "VPMINSB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPOPCNTB512", argLength: 1, reg: fp11, asm: "VPOPCNTB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPADDSB512", argLength: 2, reg: fp21, asm: "VPADDSB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBSB512", argLength: 2, reg: fp21, asm: "VPSUBSB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPSUBB512", argLength: 2, reg: fp21, asm: "VPSUBB", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPAVGW256", argLength: 2, reg: fp21, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPAVGWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPAVGW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULHUWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMADDUBSWMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUW256", argLength: 2, reg: fp21, asm: "VPMAXUW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUW256", argLength: 2, reg: fp21, asm: "VPMINUW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULHUW256", argLength: 2, reg: fp21, asm: "VPMULHUW", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPAVGW512", argLength: 2, reg: fp21, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPAVGWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPAVGW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULHUWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMADDUBSWMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUW512", argLength: 2, reg: fp21, asm: "VPMAXUW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUW512", argLength: 2, reg: fp21, asm: "VPMINUW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULHUW512", argLength: 2, reg: fp21, asm: "VPMULHUW", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMADDUBSW512", argLength: 2, reg: fp21, asm: "VPMADDUBSW", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VPAVGW128", argLength: 2, reg: fp21, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPAVGWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPAVGW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULHUWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMADDUBSWMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUW128", argLength: 2, reg: fp21, asm: "VPMAXUW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUW128", argLength: 2, reg: fp21, asm: "VPMINUW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULHUW128", argLength: 2, reg: fp21, asm: "VPMULHUW", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUDMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUD512", argLength: 2, reg: fp21, asm: "VPMAXUD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUD512", argLength: 2, reg: fp21, asm: "VPMINUD", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUDMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUD128", argLength: 2, reg: fp21, asm: "VPMAXUD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUD128", argLength: 2, reg: fp21, asm: "VPMINUD", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULUDQ128", argLength: 2, reg: fp21, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUDMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUD256", argLength: 2, reg: fp21, asm: "VPMAXUD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUD256", argLength: 2, reg: fp21, asm: "VPMINUD", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULUDQ256", argLength: 2, reg: fp21, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMULUDQMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMULUDQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUQ128", argLength: 2, reg: fp21, asm: "VPMAXUQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUQ128", argLength: 2, reg: fp21, asm: "VPMINUQ", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMULUDQMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMULUDQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUQ256", argLength: 2, reg: fp21, asm: "VPMAXUQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUQ256", argLength: 2, reg: fp21, asm: "VPMINUQ", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULUDQMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUQ512", argLength: 2, reg: fp21, asm: "VPMAXUQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUQ512", argLength: 2, reg: fp21, asm: "VPMINUQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMULUDQ512", argLength: 2, reg: fp21, asm: "VPMULUDQ", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPAVGB128", argLength: 2, reg: fp21, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPAVGBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPAVGB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUBMasked128", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMAXUB128", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMINUB128", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VPMADDUBSW128", argLength: 2, reg: fp21, asm: "VPMADDUBSW", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VPAVGB256", argLength: 2, reg: fp21, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPAVGBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPAVGB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUBMasked256", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMAXUB256", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMINUB256", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VPMADDUBSW256", argLength: 2, reg: fp21, asm: "VPMADDUBSW", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VPAVGB512", argLength: 2, reg: fp21, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPAVGBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPAVGB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUBMasked512", argLength: 3, reg: fp2k1fp1, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMAXUB512", argLength: 2, reg: fp21, asm: "VPMAXUB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VPMINUB512", argLength: 2, reg: fp21, asm: "VPMINUB", commutative: true, typ: "Vec512", resultInArg0: false}, + {name: "VRNDSCALEPS512", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VREDUCEPS512", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCMPPS512", argLength: 2, reg: fp2k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VRNDSCALEPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VREDUCEPSMasked512", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCMPPSMasked512", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VROUNDPS128", argLength: 1, reg: fp11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRNDSCALEPS128", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VREDUCEPS128", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCMPPS128", argLength: 2, reg: fp21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VRNDSCALEPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VREDUCEPSMasked128", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCMPPSMasked128", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VROUNDPS256", argLength: 1, reg: fp11, asm: "VROUNDPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRNDSCALEPS256", argLength: 1, reg: fp11, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VREDUCEPS256", argLength: 1, reg: fp11, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCMPPS256", argLength: 2, reg: fp21, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VRNDSCALEPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VREDUCEPSMasked256", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPS", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCMPPSMasked256", argLength: 3, reg: fp2k1k1, asm: "VCMPPS", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VROUNDPD128", argLength: 1, reg: fp11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VRNDSCALEPD128", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VREDUCEPD128", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VDPPD128", argLength: 2, reg: fp21, asm: "VDPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VCMPPD128", argLength: 2, reg: fp21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec128", resultInArg0: false}, + {name: "VRNDSCALEPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VREDUCEPDMasked128", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec128", resultInArg0: false}, + {name: "VCMPPDMasked128", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VROUNDPD256", argLength: 1, reg: fp11, asm: "VROUNDPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VRNDSCALEPD256", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VREDUCEPD256", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCMPPD256", argLength: 2, reg: fp21, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Vec256", resultInArg0: false}, + {name: "VRNDSCALEPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VREDUCEPDMasked256", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec256", resultInArg0: false}, + {name: "VCMPPDMasked256", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VRNDSCALEPD512", argLength: 1, reg: fp11, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VREDUCEPD512", argLength: 1, reg: fp11, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCMPPD512", argLength: 2, reg: fp2k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VRNDSCALEPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VRNDSCALEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VREDUCEPDMasked512", argLength: 2, reg: fp1k1fp1, asm: "VREDUCEPD", aux: "Int8", commutative: false, typ: "Vec512", resultInArg0: false}, + {name: "VCMPPDMasked512", argLength: 3, reg: fp2k1k1, asm: "VCMPPD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPW256", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPW512", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPWMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPW128", argLength: 2, reg: fp2k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPWMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPW", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPD512", argLength: 2, reg: fp2k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPDMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPD128", argLength: 2, reg: fp2k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPDMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPD256", argLength: 2, reg: fp2k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPDMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPD", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPQ128", argLength: 2, reg: fp2k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPQMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPQ256", argLength: 2, reg: fp2k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPQMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPQ512", argLength: 2, reg: fp2k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPQMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPQ", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPB128", argLength: 2, reg: fp2k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPBMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPB256", argLength: 2, reg: fp2k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPBMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPB512", argLength: 2, reg: fp2k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPBMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPB", aux: "Int8", commutative: false, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUW256", argLength: 2, reg: fp2k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUWMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUW512", argLength: 2, reg: fp2k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUWMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUW128", argLength: 2, reg: fp2k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUWMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUW", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUD512", argLength: 2, reg: fp2k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUDMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUD128", argLength: 2, reg: fp2k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUDMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUD256", argLength: 2, reg: fp2k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUDMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUD", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUQ128", argLength: 2, reg: fp2k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUQMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUQ256", argLength: 2, reg: fp2k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUQMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUQ512", argLength: 2, reg: fp2k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUQMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUQ", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUB128", argLength: 2, reg: fp2k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUBMasked128", argLength: 3, reg: fp2k1k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUB256", argLength: 2, reg: fp2k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUBMasked256", argLength: 3, reg: fp2k1k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUB512", argLength: 2, reg: fp2k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + {name: "VPCMPUBMasked512", argLength: 3, reg: fp2k1k1, asm: "VPCMPUB", aux: "Int8", commutative: true, typ: "Mask", resultInArg0: false}, + } +} diff --git a/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go new file mode 100644 index 00000000000000..a29decdf008110 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/simdgenericOps.go @@ -0,0 +1,1558 @@ +// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT. +package main + +func simdGenericOps() []opData { + return []opData{ + {name: "AddFloat32x16", argLength: 2, commutative: true}, + {name: "AndFloat32x16", argLength: 2, commutative: true}, + {name: "AndNotFloat32x16", argLength: 2, commutative: false}, + {name: "ApproximateReciprocalFloat32x16", argLength: 1, commutative: false}, + {name: "ApproximateReciprocalOfSqrtFloat32x16", argLength: 1, commutative: false}, + {name: "DivFloat32x16", argLength: 2, commutative: false}, + {name: "EqualFloat32x16", argLength: 2, commutative: true}, + {name: "FusedMultiplyAdd132Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd213Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd231Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub132Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub213Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub231Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplySub132Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplySub213Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplySub231Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd132Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd213Float32x16", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd231Float32x16", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd132Float32x16", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd213Float32x16", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd231Float32x16", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub132Float32x16", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub213Float32x16", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub231Float32x16", argLength: 3, commutative: false}, + {name: "GreaterFloat32x16", argLength: 2, commutative: false}, + {name: "GreaterEqualFloat32x16", argLength: 2, commutative: false}, + {name: "IsNanFloat32x16", argLength: 2, commutative: true}, + {name: "LessFloat32x16", argLength: 2, commutative: false}, + {name: "LessEqualFloat32x16", argLength: 2, commutative: false}, + {name: "MaskedAddFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedAndFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedAndNotFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedApproximateReciprocalFloat32x16", argLength: 2, commutative: false}, + {name: "MaskedApproximateReciprocalOfSqrtFloat32x16", argLength: 2, commutative: false}, + {name: "MaskedDivFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedEqualFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedFusedMultiplyAdd132Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd213Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd231Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub132Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub213Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub231Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub132Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub213Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub231Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd132Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd213Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd231Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd132Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd213Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd231Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub132Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub213Float32x16", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub231Float32x16", argLength: 4, commutative: false}, + {name: "MaskedGreaterFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedIsNanFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedLessFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedMaxFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedMinFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedMulFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedMulByPowOf2Float32x16", argLength: 3, commutative: false}, + {name: "MaskedNotEqualFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedOrFloat32x16", argLength: 3, commutative: true}, + {name: "MaskedSqrtFloat32x16", argLength: 2, commutative: false}, + {name: "MaskedSubFloat32x16", argLength: 3, commutative: false}, + {name: "MaskedXorFloat32x16", argLength: 3, commutative: true}, + {name: "MaxFloat32x16", argLength: 2, commutative: true}, + {name: "MinFloat32x16", argLength: 2, commutative: true}, + {name: "MulFloat32x16", argLength: 2, commutative: true}, + {name: "MulByPowOf2Float32x16", argLength: 2, commutative: false}, + {name: "NotEqualFloat32x16", argLength: 2, commutative: true}, + {name: "OrFloat32x16", argLength: 2, commutative: true}, + {name: "SqrtFloat32x16", argLength: 1, commutative: false}, + {name: "SubFloat32x16", argLength: 2, commutative: false}, + {name: "XorFloat32x16", argLength: 2, commutative: true}, + {name: "AddFloat32x4", argLength: 2, commutative: true}, + {name: "AddSubFloat32x4", argLength: 2, commutative: false}, + {name: "AndFloat32x4", argLength: 2, commutative: true}, + {name: "AndNotFloat32x4", argLength: 2, commutative: false}, + {name: "ApproximateReciprocalFloat32x4", argLength: 1, commutative: false}, + {name: "ApproximateReciprocalOfSqrtFloat32x4", argLength: 1, commutative: false}, + {name: "CeilFloat32x4", argLength: 1, commutative: false}, + {name: "DivFloat32x4", argLength: 2, commutative: false}, + {name: "EqualFloat32x4", argLength: 2, commutative: true}, + {name: "FloorFloat32x4", argLength: 1, commutative: false}, + {name: "FusedMultiplyAdd132Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd213Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd231Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub132Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub213Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub231Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySub132Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySub213Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySub231Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd132Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd213Float32x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd231Float32x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd132Float32x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd213Float32x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd231Float32x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub132Float32x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub213Float32x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub231Float32x4", argLength: 3, commutative: false}, + {name: "GreaterFloat32x4", argLength: 2, commutative: false}, + {name: "GreaterEqualFloat32x4", argLength: 2, commutative: false}, + {name: "IsNanFloat32x4", argLength: 2, commutative: true}, + {name: "LessFloat32x4", argLength: 2, commutative: false}, + {name: "LessEqualFloat32x4", argLength: 2, commutative: false}, + {name: "MaskedAddFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedAndFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedAndNotFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedApproximateReciprocalFloat32x4", argLength: 2, commutative: false}, + {name: "MaskedApproximateReciprocalOfSqrtFloat32x4", argLength: 2, commutative: false}, + {name: "MaskedDivFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedEqualFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedFusedMultiplyAdd132Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd213Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd231Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub132Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub213Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub231Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub132Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub213Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub231Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd132Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd213Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd231Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd132Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd213Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd231Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub132Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub213Float32x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub231Float32x4", argLength: 4, commutative: false}, + {name: "MaskedGreaterFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedIsNanFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedLessFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedLessEqualFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedMaxFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedMinFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedMulFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedMulByPowOf2Float32x4", argLength: 3, commutative: false}, + {name: "MaskedNotEqualFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedOrFloat32x4", argLength: 3, commutative: true}, + {name: "MaskedSqrtFloat32x4", argLength: 2, commutative: false}, + {name: "MaskedSubFloat32x4", argLength: 3, commutative: false}, + {name: "MaskedXorFloat32x4", argLength: 3, commutative: true}, + {name: "MaxFloat32x4", argLength: 2, commutative: true}, + {name: "MinFloat32x4", argLength: 2, commutative: true}, + {name: "MulFloat32x4", argLength: 2, commutative: true}, + {name: "MulByPowOf2Float32x4", argLength: 2, commutative: false}, + {name: "NotEqualFloat32x4", argLength: 2, commutative: true}, + {name: "OrFloat32x4", argLength: 2, commutative: true}, + {name: "PairwiseAddFloat32x4", argLength: 2, commutative: false}, + {name: "PairwiseSubFloat32x4", argLength: 2, commutative: false}, + {name: "RoundFloat32x4", argLength: 1, commutative: false}, + {name: "SqrtFloat32x4", argLength: 1, commutative: false}, + {name: "SubFloat32x4", argLength: 2, commutative: false}, + {name: "TruncFloat32x4", argLength: 1, commutative: false}, + {name: "XorFloat32x4", argLength: 2, commutative: true}, + {name: "AddFloat32x8", argLength: 2, commutative: true}, + {name: "AddSubFloat32x8", argLength: 2, commutative: false}, + {name: "AndFloat32x8", argLength: 2, commutative: true}, + {name: "AndNotFloat32x8", argLength: 2, commutative: false}, + {name: "ApproximateReciprocalFloat32x8", argLength: 1, commutative: false}, + {name: "ApproximateReciprocalOfSqrtFloat32x8", argLength: 1, commutative: false}, + {name: "CeilFloat32x8", argLength: 1, commutative: false}, + {name: "DivFloat32x8", argLength: 2, commutative: false}, + {name: "EqualFloat32x8", argLength: 2, commutative: true}, + {name: "FloorFloat32x8", argLength: 1, commutative: false}, + {name: "FusedMultiplyAdd132Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd213Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd231Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub132Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub213Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub231Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySub132Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySub213Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySub231Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd132Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd213Float32x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd231Float32x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd132Float32x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd213Float32x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd231Float32x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub132Float32x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub213Float32x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub231Float32x8", argLength: 3, commutative: false}, + {name: "GreaterFloat32x8", argLength: 2, commutative: false}, + {name: "GreaterEqualFloat32x8", argLength: 2, commutative: false}, + {name: "IsNanFloat32x8", argLength: 2, commutative: true}, + {name: "LessFloat32x8", argLength: 2, commutative: false}, + {name: "LessEqualFloat32x8", argLength: 2, commutative: false}, + {name: "MaskedAddFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedAndFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedAndNotFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedApproximateReciprocalFloat32x8", argLength: 2, commutative: false}, + {name: "MaskedApproximateReciprocalOfSqrtFloat32x8", argLength: 2, commutative: false}, + {name: "MaskedDivFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedEqualFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedFusedMultiplyAdd132Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd213Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd231Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub132Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub213Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub231Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub132Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub213Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub231Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd132Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd213Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd231Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd132Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd213Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd231Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub132Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub213Float32x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub231Float32x8", argLength: 4, commutative: false}, + {name: "MaskedGreaterFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedIsNanFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedLessFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedMaxFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedMinFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedMulFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedMulByPowOf2Float32x8", argLength: 3, commutative: false}, + {name: "MaskedNotEqualFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedOrFloat32x8", argLength: 3, commutative: true}, + {name: "MaskedSqrtFloat32x8", argLength: 2, commutative: false}, + {name: "MaskedSubFloat32x8", argLength: 3, commutative: false}, + {name: "MaskedXorFloat32x8", argLength: 3, commutative: true}, + {name: "MaxFloat32x8", argLength: 2, commutative: true}, + {name: "MinFloat32x8", argLength: 2, commutative: true}, + {name: "MulFloat32x8", argLength: 2, commutative: true}, + {name: "MulByPowOf2Float32x8", argLength: 2, commutative: false}, + {name: "NotEqualFloat32x8", argLength: 2, commutative: true}, + {name: "OrFloat32x8", argLength: 2, commutative: true}, + {name: "PairwiseAddFloat32x8", argLength: 2, commutative: false}, + {name: "PairwiseSubFloat32x8", argLength: 2, commutative: false}, + {name: "RoundFloat32x8", argLength: 1, commutative: false}, + {name: "SqrtFloat32x8", argLength: 1, commutative: false}, + {name: "SubFloat32x8", argLength: 2, commutative: false}, + {name: "TruncFloat32x8", argLength: 1, commutative: false}, + {name: "XorFloat32x8", argLength: 2, commutative: true}, + {name: "AddFloat64x2", argLength: 2, commutative: true}, + {name: "AddSubFloat64x2", argLength: 2, commutative: false}, + {name: "AndFloat64x2", argLength: 2, commutative: true}, + {name: "AndNotFloat64x2", argLength: 2, commutative: false}, + {name: "ApproximateReciprocalFloat64x2", argLength: 1, commutative: false}, + {name: "ApproximateReciprocalOfSqrtFloat64x2", argLength: 1, commutative: false}, + {name: "CeilFloat64x2", argLength: 1, commutative: false}, + {name: "DivFloat64x2", argLength: 2, commutative: false}, + {name: "DotProdBroadcastFloat64x2", argLength: 2, commutative: true}, + {name: "EqualFloat64x2", argLength: 2, commutative: true}, + {name: "FloorFloat64x2", argLength: 1, commutative: false}, + {name: "FusedMultiplyAdd132Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd213Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd231Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub132Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub213Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub231Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplySub132Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplySub213Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplySub231Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd132Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd213Float64x2", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd231Float64x2", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd132Float64x2", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd213Float64x2", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd231Float64x2", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub132Float64x2", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub213Float64x2", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub231Float64x2", argLength: 3, commutative: false}, + {name: "GreaterFloat64x2", argLength: 2, commutative: false}, + {name: "GreaterEqualFloat64x2", argLength: 2, commutative: false}, + {name: "IsNanFloat64x2", argLength: 2, commutative: true}, + {name: "LessFloat64x2", argLength: 2, commutative: false}, + {name: "LessEqualFloat64x2", argLength: 2, commutative: false}, + {name: "MaskedAddFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedAndFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedAndNotFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedApproximateReciprocalFloat64x2", argLength: 2, commutative: false}, + {name: "MaskedApproximateReciprocalOfSqrtFloat64x2", argLength: 2, commutative: false}, + {name: "MaskedDivFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedEqualFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedFusedMultiplyAdd132Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd213Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd231Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub132Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub213Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub231Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub132Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub213Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub231Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd132Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd213Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd231Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd132Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd213Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd231Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub132Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub213Float64x2", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub231Float64x2", argLength: 4, commutative: false}, + {name: "MaskedGreaterFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedIsNanFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedLessFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedLessEqualFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedMaxFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedMinFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedMulFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedMulByPowOf2Float64x2", argLength: 3, commutative: false}, + {name: "MaskedNotEqualFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedOrFloat64x2", argLength: 3, commutative: true}, + {name: "MaskedSqrtFloat64x2", argLength: 2, commutative: false}, + {name: "MaskedSubFloat64x2", argLength: 3, commutative: false}, + {name: "MaskedXorFloat64x2", argLength: 3, commutative: true}, + {name: "MaxFloat64x2", argLength: 2, commutative: true}, + {name: "MinFloat64x2", argLength: 2, commutative: true}, + {name: "MulFloat64x2", argLength: 2, commutative: true}, + {name: "MulByPowOf2Float64x2", argLength: 2, commutative: false}, + {name: "NotEqualFloat64x2", argLength: 2, commutative: true}, + {name: "OrFloat64x2", argLength: 2, commutative: true}, + {name: "PairwiseAddFloat64x2", argLength: 2, commutative: false}, + {name: "PairwiseSubFloat64x2", argLength: 2, commutative: false}, + {name: "RoundFloat64x2", argLength: 1, commutative: false}, + {name: "SqrtFloat64x2", argLength: 1, commutative: false}, + {name: "SubFloat64x2", argLength: 2, commutative: false}, + {name: "TruncFloat64x2", argLength: 1, commutative: false}, + {name: "XorFloat64x2", argLength: 2, commutative: true}, + {name: "AddFloat64x4", argLength: 2, commutative: true}, + {name: "AddSubFloat64x4", argLength: 2, commutative: false}, + {name: "AndFloat64x4", argLength: 2, commutative: true}, + {name: "AndNotFloat64x4", argLength: 2, commutative: false}, + {name: "ApproximateReciprocalFloat64x4", argLength: 1, commutative: false}, + {name: "ApproximateReciprocalOfSqrtFloat64x4", argLength: 1, commutative: false}, + {name: "CeilFloat64x4", argLength: 1, commutative: false}, + {name: "DivFloat64x4", argLength: 2, commutative: false}, + {name: "EqualFloat64x4", argLength: 2, commutative: true}, + {name: "FloorFloat64x4", argLength: 1, commutative: false}, + {name: "FusedMultiplyAdd132Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd213Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd231Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub132Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub213Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub231Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySub132Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySub213Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySub231Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd132Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd213Float64x4", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd231Float64x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd132Float64x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd213Float64x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd231Float64x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub132Float64x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub213Float64x4", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub231Float64x4", argLength: 3, commutative: false}, + {name: "GreaterFloat64x4", argLength: 2, commutative: false}, + {name: "GreaterEqualFloat64x4", argLength: 2, commutative: false}, + {name: "IsNanFloat64x4", argLength: 2, commutative: true}, + {name: "LessFloat64x4", argLength: 2, commutative: false}, + {name: "LessEqualFloat64x4", argLength: 2, commutative: false}, + {name: "MaskedAddFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedAndFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedAndNotFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedApproximateReciprocalFloat64x4", argLength: 2, commutative: false}, + {name: "MaskedApproximateReciprocalOfSqrtFloat64x4", argLength: 2, commutative: false}, + {name: "MaskedDivFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedEqualFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedFusedMultiplyAdd132Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd213Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd231Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub132Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub213Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub231Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub132Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub213Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub231Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd132Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd213Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd231Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd132Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd213Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd231Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub132Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub213Float64x4", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub231Float64x4", argLength: 4, commutative: false}, + {name: "MaskedGreaterFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedIsNanFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedLessFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedLessEqualFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedMaxFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedMinFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedMulFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedMulByPowOf2Float64x4", argLength: 3, commutative: false}, + {name: "MaskedNotEqualFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedOrFloat64x4", argLength: 3, commutative: true}, + {name: "MaskedSqrtFloat64x4", argLength: 2, commutative: false}, + {name: "MaskedSubFloat64x4", argLength: 3, commutative: false}, + {name: "MaskedXorFloat64x4", argLength: 3, commutative: true}, + {name: "MaxFloat64x4", argLength: 2, commutative: true}, + {name: "MinFloat64x4", argLength: 2, commutative: true}, + {name: "MulFloat64x4", argLength: 2, commutative: true}, + {name: "MulByPowOf2Float64x4", argLength: 2, commutative: false}, + {name: "NotEqualFloat64x4", argLength: 2, commutative: true}, + {name: "OrFloat64x4", argLength: 2, commutative: true}, + {name: "PairwiseAddFloat64x4", argLength: 2, commutative: false}, + {name: "PairwiseSubFloat64x4", argLength: 2, commutative: false}, + {name: "RoundFloat64x4", argLength: 1, commutative: false}, + {name: "SqrtFloat64x4", argLength: 1, commutative: false}, + {name: "SubFloat64x4", argLength: 2, commutative: false}, + {name: "TruncFloat64x4", argLength: 1, commutative: false}, + {name: "XorFloat64x4", argLength: 2, commutative: true}, + {name: "AddFloat64x8", argLength: 2, commutative: true}, + {name: "AndFloat64x8", argLength: 2, commutative: true}, + {name: "AndNotFloat64x8", argLength: 2, commutative: false}, + {name: "ApproximateReciprocalFloat64x8", argLength: 1, commutative: false}, + {name: "ApproximateReciprocalOfSqrtFloat64x8", argLength: 1, commutative: false}, + {name: "DivFloat64x8", argLength: 2, commutative: false}, + {name: "EqualFloat64x8", argLength: 2, commutative: true}, + {name: "FusedMultiplyAdd132Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd213Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAdd231Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub132Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub213Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplyAddSub231Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySub132Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySub213Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySub231Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd132Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd213Float64x8", argLength: 3, commutative: false}, + {name: "FusedMultiplySubAdd231Float64x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd132Float64x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd213Float64x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplyAdd231Float64x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub132Float64x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub213Float64x8", argLength: 3, commutative: false}, + {name: "FusedNegativeMultiplySub231Float64x8", argLength: 3, commutative: false}, + {name: "GreaterFloat64x8", argLength: 2, commutative: false}, + {name: "GreaterEqualFloat64x8", argLength: 2, commutative: false}, + {name: "IsNanFloat64x8", argLength: 2, commutative: true}, + {name: "LessFloat64x8", argLength: 2, commutative: false}, + {name: "LessEqualFloat64x8", argLength: 2, commutative: false}, + {name: "MaskedAddFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedAndFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedAndNotFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedApproximateReciprocalFloat64x8", argLength: 2, commutative: false}, + {name: "MaskedApproximateReciprocalOfSqrtFloat64x8", argLength: 2, commutative: false}, + {name: "MaskedDivFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedEqualFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedFusedMultiplyAdd132Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd213Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAdd231Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub132Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub213Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplyAddSub231Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub132Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub213Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySub231Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd132Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd213Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedMultiplySubAdd231Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd132Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd213Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplyAdd231Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub132Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub213Float64x8", argLength: 4, commutative: false}, + {name: "MaskedFusedNegativeMultiplySub231Float64x8", argLength: 4, commutative: false}, + {name: "MaskedGreaterFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedIsNanFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedLessFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedMaxFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedMinFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedMulFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedMulByPowOf2Float64x8", argLength: 3, commutative: false}, + {name: "MaskedNotEqualFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedOrFloat64x8", argLength: 3, commutative: true}, + {name: "MaskedSqrtFloat64x8", argLength: 2, commutative: false}, + {name: "MaskedSubFloat64x8", argLength: 3, commutative: false}, + {name: "MaskedXorFloat64x8", argLength: 3, commutative: true}, + {name: "MaxFloat64x8", argLength: 2, commutative: true}, + {name: "MinFloat64x8", argLength: 2, commutative: true}, + {name: "MulFloat64x8", argLength: 2, commutative: true}, + {name: "MulByPowOf2Float64x8", argLength: 2, commutative: false}, + {name: "NotEqualFloat64x8", argLength: 2, commutative: true}, + {name: "OrFloat64x8", argLength: 2, commutative: true}, + {name: "SqrtFloat64x8", argLength: 1, commutative: false}, + {name: "SubFloat64x8", argLength: 2, commutative: false}, + {name: "XorFloat64x8", argLength: 2, commutative: true}, + {name: "AbsoluteInt16x16", argLength: 1, commutative: false}, + {name: "AddInt16x16", argLength: 2, commutative: true}, + {name: "AndInt16x16", argLength: 2, commutative: true}, + {name: "AndNotInt16x16", argLength: 2, commutative: false}, + {name: "EqualInt16x16", argLength: 2, commutative: true}, + {name: "GreaterInt16x16", argLength: 2, commutative: false}, + {name: "GreaterEqualInt16x16", argLength: 2, commutative: false}, + {name: "LessInt16x16", argLength: 2, commutative: false}, + {name: "LessEqualInt16x16", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt16x16", argLength: 2, commutative: false}, + {name: "MaskedAddInt16x16", argLength: 3, commutative: true}, + {name: "MaskedEqualInt16x16", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt16x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt16x16", argLength: 3, commutative: false}, + {name: "MaskedLessInt16x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt16x16", argLength: 3, commutative: false}, + {name: "MaskedMaxInt16x16", argLength: 3, commutative: true}, + {name: "MaskedMinInt16x16", argLength: 3, commutative: true}, + {name: "MaskedMulHighInt16x16", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt16x16", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt16x16", argLength: 3, commutative: true}, + {name: "MaskedPairDotProdInt16x16", argLength: 3, commutative: false}, + {name: "MaskedPopCountInt16x16", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddInt16x16", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubInt16x16", argLength: 3, commutative: false}, + {name: "MaskedSubInt16x16", argLength: 3, commutative: false}, + {name: "MaxInt16x16", argLength: 2, commutative: true}, + {name: "MinInt16x16", argLength: 2, commutative: true}, + {name: "MulHighInt16x16", argLength: 2, commutative: true}, + {name: "MulLowInt16x16", argLength: 2, commutative: true}, + {name: "NotEqualInt16x16", argLength: 2, commutative: true}, + {name: "OrInt16x16", argLength: 2, commutative: true}, + {name: "PairDotProdInt16x16", argLength: 2, commutative: false}, + {name: "PairwiseAddInt16x16", argLength: 2, commutative: false}, + {name: "PairwiseSubInt16x16", argLength: 2, commutative: false}, + {name: "PopCountInt16x16", argLength: 1, commutative: false}, + {name: "SaturatedAddInt16x16", argLength: 2, commutative: true}, + {name: "SaturatedPairwiseAddInt16x16", argLength: 2, commutative: false}, + {name: "SaturatedPairwiseSubInt16x16", argLength: 2, commutative: false}, + {name: "SaturatedSubInt16x16", argLength: 2, commutative: false}, + {name: "SignInt16x16", argLength: 2, commutative: false}, + {name: "SubInt16x16", argLength: 2, commutative: false}, + {name: "XorInt16x16", argLength: 2, commutative: true}, + {name: "AbsoluteInt16x32", argLength: 1, commutative: false}, + {name: "AddInt16x32", argLength: 2, commutative: true}, + {name: "EqualInt16x32", argLength: 2, commutative: true}, + {name: "GreaterInt16x32", argLength: 2, commutative: false}, + {name: "GreaterEqualInt16x32", argLength: 2, commutative: false}, + {name: "LessInt16x32", argLength: 2, commutative: false}, + {name: "LessEqualInt16x32", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt16x32", argLength: 2, commutative: false}, + {name: "MaskedAddInt16x32", argLength: 3, commutative: true}, + {name: "MaskedEqualInt16x32", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt16x32", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt16x32", argLength: 3, commutative: false}, + {name: "MaskedLessInt16x32", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt16x32", argLength: 3, commutative: false}, + {name: "MaskedMaxInt16x32", argLength: 3, commutative: true}, + {name: "MaskedMinInt16x32", argLength: 3, commutative: true}, + {name: "MaskedMulHighInt16x32", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt16x32", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt16x32", argLength: 3, commutative: true}, + {name: "MaskedPairDotProdInt16x32", argLength: 3, commutative: false}, + {name: "MaskedPopCountInt16x32", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddInt16x32", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubInt16x32", argLength: 3, commutative: false}, + {name: "MaskedSubInt16x32", argLength: 3, commutative: false}, + {name: "MaxInt16x32", argLength: 2, commutative: true}, + {name: "MinInt16x32", argLength: 2, commutative: true}, + {name: "MulHighInt16x32", argLength: 2, commutative: true}, + {name: "MulLowInt16x32", argLength: 2, commutative: true}, + {name: "NotEqualInt16x32", argLength: 2, commutative: true}, + {name: "PairDotProdInt16x32", argLength: 2, commutative: false}, + {name: "PopCountInt16x32", argLength: 1, commutative: false}, + {name: "SaturatedAddInt16x32", argLength: 2, commutative: true}, + {name: "SaturatedSubInt16x32", argLength: 2, commutative: false}, + {name: "SubInt16x32", argLength: 2, commutative: false}, + {name: "AbsoluteInt16x8", argLength: 1, commutative: false}, + {name: "AddInt16x8", argLength: 2, commutative: true}, + {name: "AndInt16x8", argLength: 2, commutative: true}, + {name: "AndNotInt16x8", argLength: 2, commutative: false}, + {name: "EqualInt16x8", argLength: 2, commutative: true}, + {name: "GreaterInt16x8", argLength: 2, commutative: false}, + {name: "GreaterEqualInt16x8", argLength: 2, commutative: false}, + {name: "LessInt16x8", argLength: 2, commutative: false}, + {name: "LessEqualInt16x8", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt16x8", argLength: 2, commutative: false}, + {name: "MaskedAddInt16x8", argLength: 3, commutative: true}, + {name: "MaskedEqualInt16x8", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt16x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt16x8", argLength: 3, commutative: false}, + {name: "MaskedLessInt16x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt16x8", argLength: 3, commutative: false}, + {name: "MaskedMaxInt16x8", argLength: 3, commutative: true}, + {name: "MaskedMinInt16x8", argLength: 3, commutative: true}, + {name: "MaskedMulHighInt16x8", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt16x8", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt16x8", argLength: 3, commutative: true}, + {name: "MaskedPairDotProdInt16x8", argLength: 3, commutative: false}, + {name: "MaskedPopCountInt16x8", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddInt16x8", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubInt16x8", argLength: 3, commutative: false}, + {name: "MaskedSubInt16x8", argLength: 3, commutative: false}, + {name: "MaxInt16x8", argLength: 2, commutative: true}, + {name: "MinInt16x8", argLength: 2, commutative: true}, + {name: "MulHighInt16x8", argLength: 2, commutative: true}, + {name: "MulLowInt16x8", argLength: 2, commutative: true}, + {name: "NotEqualInt16x8", argLength: 2, commutative: true}, + {name: "OrInt16x8", argLength: 2, commutative: true}, + {name: "PairDotProdInt16x8", argLength: 2, commutative: false}, + {name: "PairwiseAddInt16x8", argLength: 2, commutative: false}, + {name: "PairwiseSubInt16x8", argLength: 2, commutative: false}, + {name: "PopCountInt16x8", argLength: 1, commutative: false}, + {name: "SaturatedAddInt16x8", argLength: 2, commutative: true}, + {name: "SaturatedPairwiseAddInt16x8", argLength: 2, commutative: false}, + {name: "SaturatedPairwiseSubInt16x8", argLength: 2, commutative: false}, + {name: "SaturatedSubInt16x8", argLength: 2, commutative: false}, + {name: "SignInt16x8", argLength: 2, commutative: false}, + {name: "SubInt16x8", argLength: 2, commutative: false}, + {name: "XorInt16x8", argLength: 2, commutative: true}, + {name: "AbsoluteInt32x16", argLength: 1, commutative: false}, + {name: "AddInt32x16", argLength: 2, commutative: true}, + {name: "AndInt32x16", argLength: 2, commutative: true}, + {name: "AndNotInt32x16", argLength: 2, commutative: false}, + {name: "EqualInt32x16", argLength: 2, commutative: true}, + {name: "GreaterInt32x16", argLength: 2, commutative: false}, + {name: "GreaterEqualInt32x16", argLength: 2, commutative: false}, + {name: "LessInt32x16", argLength: 2, commutative: false}, + {name: "LessEqualInt32x16", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt32x16", argLength: 2, commutative: false}, + {name: "MaskedAddInt32x16", argLength: 3, commutative: true}, + {name: "MaskedAndInt32x16", argLength: 3, commutative: true}, + {name: "MaskedAndNotInt32x16", argLength: 3, commutative: false}, + {name: "MaskedEqualInt32x16", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt32x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt32x16", argLength: 3, commutative: false}, + {name: "MaskedLessInt32x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt32x16", argLength: 3, commutative: false}, + {name: "MaskedMaxInt32x16", argLength: 3, commutative: true}, + {name: "MaskedMinInt32x16", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt32x16", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt32x16", argLength: 3, commutative: true}, + {name: "MaskedOrInt32x16", argLength: 3, commutative: true}, + {name: "MaskedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false}, + {name: "MaskedPopCountInt32x16", argLength: 2, commutative: false}, + {name: "MaskedSaturatedPairDotProdAccumulateInt32x16", argLength: 4, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false}, + {name: "MaskedSubInt32x16", argLength: 3, commutative: false}, + {name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 4, commutative: false}, + {name: "MaskedXorInt32x16", argLength: 3, commutative: true}, + {name: "MaxInt32x16", argLength: 2, commutative: true}, + {name: "MinInt32x16", argLength: 2, commutative: true}, + {name: "MulLowInt32x16", argLength: 2, commutative: true}, + {name: "NotEqualInt32x16", argLength: 2, commutative: true}, + {name: "OrInt32x16", argLength: 2, commutative: true}, + {name: "PairDotProdAccumulateInt32x16", argLength: 3, commutative: false}, + {name: "PopCountInt32x16", argLength: 1, commutative: false}, + {name: "SaturatedPairDotProdAccumulateInt32x16", argLength: 3, commutative: false}, + {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false}, + {name: "SubInt32x16", argLength: 2, commutative: false}, + {name: "UnsignedSignedQuadDotProdAccumulateInt32x16", argLength: 3, commutative: false}, + {name: "XorInt32x16", argLength: 2, commutative: true}, + {name: "AbsoluteInt32x4", argLength: 1, commutative: false}, + {name: "AddInt32x4", argLength: 2, commutative: true}, + {name: "AndInt32x4", argLength: 2, commutative: true}, + {name: "AndNotInt32x4", argLength: 2, commutative: false}, + {name: "EqualInt32x4", argLength: 2, commutative: true}, + {name: "GreaterInt32x4", argLength: 2, commutative: false}, + {name: "GreaterEqualInt32x4", argLength: 2, commutative: false}, + {name: "LessInt32x4", argLength: 2, commutative: false}, + {name: "LessEqualInt32x4", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt32x4", argLength: 2, commutative: false}, + {name: "MaskedAddInt32x4", argLength: 3, commutative: true}, + {name: "MaskedAndInt32x4", argLength: 3, commutative: true}, + {name: "MaskedAndNotInt32x4", argLength: 3, commutative: false}, + {name: "MaskedEqualInt32x4", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt32x4", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt32x4", argLength: 3, commutative: false}, + {name: "MaskedLessInt32x4", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt32x4", argLength: 3, commutative: false}, + {name: "MaskedMaxInt32x4", argLength: 3, commutative: true}, + {name: "MaskedMinInt32x4", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt32x4", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt32x4", argLength: 3, commutative: true}, + {name: "MaskedOrInt32x4", argLength: 3, commutative: true}, + {name: "MaskedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false}, + {name: "MaskedPopCountInt32x4", argLength: 2, commutative: false}, + {name: "MaskedSaturatedPairDotProdAccumulateInt32x4", argLength: 4, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false}, + {name: "MaskedSubInt32x4", argLength: 3, commutative: false}, + {name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 4, commutative: false}, + {name: "MaskedXorInt32x4", argLength: 3, commutative: true}, + {name: "MaxInt32x4", argLength: 2, commutative: true}, + {name: "MinInt32x4", argLength: 2, commutative: true}, + {name: "MulEvenWidenInt32x4", argLength: 2, commutative: true}, + {name: "MulLowInt32x4", argLength: 2, commutative: true}, + {name: "NotEqualInt32x4", argLength: 2, commutative: true}, + {name: "OrInt32x4", argLength: 2, commutative: true}, + {name: "PairDotProdAccumulateInt32x4", argLength: 3, commutative: false}, + {name: "PairwiseAddInt32x4", argLength: 2, commutative: false}, + {name: "PairwiseSubInt32x4", argLength: 2, commutative: false}, + {name: "PopCountInt32x4", argLength: 1, commutative: false}, + {name: "SaturatedPairDotProdAccumulateInt32x4", argLength: 3, commutative: false}, + {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false}, + {name: "SignInt32x4", argLength: 2, commutative: false}, + {name: "SubInt32x4", argLength: 2, commutative: false}, + {name: "UnsignedSignedQuadDotProdAccumulateInt32x4", argLength: 3, commutative: false}, + {name: "XorInt32x4", argLength: 2, commutative: true}, + {name: "AbsoluteInt32x8", argLength: 1, commutative: false}, + {name: "AddInt32x8", argLength: 2, commutative: true}, + {name: "AndInt32x8", argLength: 2, commutative: true}, + {name: "AndNotInt32x8", argLength: 2, commutative: false}, + {name: "EqualInt32x8", argLength: 2, commutative: true}, + {name: "GreaterInt32x8", argLength: 2, commutative: false}, + {name: "GreaterEqualInt32x8", argLength: 2, commutative: false}, + {name: "LessInt32x8", argLength: 2, commutative: false}, + {name: "LessEqualInt32x8", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt32x8", argLength: 2, commutative: false}, + {name: "MaskedAddInt32x8", argLength: 3, commutative: true}, + {name: "MaskedAndInt32x8", argLength: 3, commutative: true}, + {name: "MaskedAndNotInt32x8", argLength: 3, commutative: false}, + {name: "MaskedEqualInt32x8", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt32x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt32x8", argLength: 3, commutative: false}, + {name: "MaskedLessInt32x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt32x8", argLength: 3, commutative: false}, + {name: "MaskedMaxInt32x8", argLength: 3, commutative: true}, + {name: "MaskedMinInt32x8", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt32x8", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt32x8", argLength: 3, commutative: true}, + {name: "MaskedOrInt32x8", argLength: 3, commutative: true}, + {name: "MaskedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false}, + {name: "MaskedPopCountInt32x8", argLength: 2, commutative: false}, + {name: "MaskedSaturatedPairDotProdAccumulateInt32x8", argLength: 4, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false}, + {name: "MaskedSubInt32x8", argLength: 3, commutative: false}, + {name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 4, commutative: false}, + {name: "MaskedXorInt32x8", argLength: 3, commutative: true}, + {name: "MaxInt32x8", argLength: 2, commutative: true}, + {name: "MinInt32x8", argLength: 2, commutative: true}, + {name: "MulEvenWidenInt32x8", argLength: 2, commutative: true}, + {name: "MulLowInt32x8", argLength: 2, commutative: true}, + {name: "NotEqualInt32x8", argLength: 2, commutative: true}, + {name: "OrInt32x8", argLength: 2, commutative: true}, + {name: "PairDotProdAccumulateInt32x8", argLength: 3, commutative: false}, + {name: "PairwiseAddInt32x8", argLength: 2, commutative: false}, + {name: "PairwiseSubInt32x8", argLength: 2, commutative: false}, + {name: "PopCountInt32x8", argLength: 1, commutative: false}, + {name: "SaturatedPairDotProdAccumulateInt32x8", argLength: 3, commutative: false}, + {name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false}, + {name: "SignInt32x8", argLength: 2, commutative: false}, + {name: "SubInt32x8", argLength: 2, commutative: false}, + {name: "UnsignedSignedQuadDotProdAccumulateInt32x8", argLength: 3, commutative: false}, + {name: "XorInt32x8", argLength: 2, commutative: true}, + {name: "AbsoluteInt64x2", argLength: 1, commutative: false}, + {name: "AddInt64x2", argLength: 2, commutative: true}, + {name: "AndInt64x2", argLength: 2, commutative: true}, + {name: "AndNotInt64x2", argLength: 2, commutative: false}, + {name: "EqualInt64x2", argLength: 2, commutative: true}, + {name: "GreaterInt64x2", argLength: 2, commutative: false}, + {name: "GreaterEqualInt64x2", argLength: 2, commutative: false}, + {name: "LessInt64x2", argLength: 2, commutative: false}, + {name: "LessEqualInt64x2", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt64x2", argLength: 2, commutative: false}, + {name: "MaskedAddInt64x2", argLength: 3, commutative: true}, + {name: "MaskedAndInt64x2", argLength: 3, commutative: true}, + {name: "MaskedAndNotInt64x2", argLength: 3, commutative: false}, + {name: "MaskedEqualInt64x2", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt64x2", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt64x2", argLength: 3, commutative: false}, + {name: "MaskedLessInt64x2", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt64x2", argLength: 3, commutative: false}, + {name: "MaskedMaxInt64x2", argLength: 3, commutative: true}, + {name: "MaskedMinInt64x2", argLength: 3, commutative: true}, + {name: "MaskedMulEvenWidenInt64x2", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt64x2", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt64x2", argLength: 3, commutative: true}, + {name: "MaskedOrInt64x2", argLength: 3, commutative: true}, + {name: "MaskedPopCountInt64x2", argLength: 2, commutative: false}, + {name: "MaskedSubInt64x2", argLength: 3, commutative: false}, + {name: "MaskedXorInt64x2", argLength: 3, commutative: true}, + {name: "MaxInt64x2", argLength: 2, commutative: true}, + {name: "MinInt64x2", argLength: 2, commutative: true}, + {name: "MulEvenWidenInt64x2", argLength: 2, commutative: true}, + {name: "MulLowInt64x2", argLength: 2, commutative: true}, + {name: "NotEqualInt64x2", argLength: 2, commutative: true}, + {name: "OrInt64x2", argLength: 2, commutative: true}, + {name: "PopCountInt64x2", argLength: 1, commutative: false}, + {name: "SubInt64x2", argLength: 2, commutative: false}, + {name: "XorInt64x2", argLength: 2, commutative: true}, + {name: "AbsoluteInt64x4", argLength: 1, commutative: false}, + {name: "AddInt64x4", argLength: 2, commutative: true}, + {name: "AndInt64x4", argLength: 2, commutative: true}, + {name: "AndNotInt64x4", argLength: 2, commutative: false}, + {name: "EqualInt64x4", argLength: 2, commutative: true}, + {name: "GreaterInt64x4", argLength: 2, commutative: false}, + {name: "GreaterEqualInt64x4", argLength: 2, commutative: false}, + {name: "LessInt64x4", argLength: 2, commutative: false}, + {name: "LessEqualInt64x4", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt64x4", argLength: 2, commutative: false}, + {name: "MaskedAddInt64x4", argLength: 3, commutative: true}, + {name: "MaskedAndInt64x4", argLength: 3, commutative: true}, + {name: "MaskedAndNotInt64x4", argLength: 3, commutative: false}, + {name: "MaskedEqualInt64x4", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt64x4", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt64x4", argLength: 3, commutative: false}, + {name: "MaskedLessInt64x4", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt64x4", argLength: 3, commutative: false}, + {name: "MaskedMaxInt64x4", argLength: 3, commutative: true}, + {name: "MaskedMinInt64x4", argLength: 3, commutative: true}, + {name: "MaskedMulEvenWidenInt64x4", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt64x4", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt64x4", argLength: 3, commutative: true}, + {name: "MaskedOrInt64x4", argLength: 3, commutative: true}, + {name: "MaskedPopCountInt64x4", argLength: 2, commutative: false}, + {name: "MaskedSubInt64x4", argLength: 3, commutative: false}, + {name: "MaskedXorInt64x4", argLength: 3, commutative: true}, + {name: "MaxInt64x4", argLength: 2, commutative: true}, + {name: "MinInt64x4", argLength: 2, commutative: true}, + {name: "MulEvenWidenInt64x4", argLength: 2, commutative: true}, + {name: "MulLowInt64x4", argLength: 2, commutative: true}, + {name: "NotEqualInt64x4", argLength: 2, commutative: true}, + {name: "OrInt64x4", argLength: 2, commutative: true}, + {name: "PopCountInt64x4", argLength: 1, commutative: false}, + {name: "SubInt64x4", argLength: 2, commutative: false}, + {name: "XorInt64x4", argLength: 2, commutative: true}, + {name: "AbsoluteInt64x8", argLength: 1, commutative: false}, + {name: "AddInt64x8", argLength: 2, commutative: true}, + {name: "AndInt64x8", argLength: 2, commutative: true}, + {name: "AndNotInt64x8", argLength: 2, commutative: false}, + {name: "EqualInt64x8", argLength: 2, commutative: true}, + {name: "GreaterInt64x8", argLength: 2, commutative: false}, + {name: "GreaterEqualInt64x8", argLength: 2, commutative: false}, + {name: "LessInt64x8", argLength: 2, commutative: false}, + {name: "LessEqualInt64x8", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt64x8", argLength: 2, commutative: false}, + {name: "MaskedAddInt64x8", argLength: 3, commutative: true}, + {name: "MaskedAndInt64x8", argLength: 3, commutative: true}, + {name: "MaskedAndNotInt64x8", argLength: 3, commutative: false}, + {name: "MaskedEqualInt64x8", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt64x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt64x8", argLength: 3, commutative: false}, + {name: "MaskedLessInt64x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt64x8", argLength: 3, commutative: false}, + {name: "MaskedMaxInt64x8", argLength: 3, commutative: true}, + {name: "MaskedMinInt64x8", argLength: 3, commutative: true}, + {name: "MaskedMulEvenWidenInt64x8", argLength: 3, commutative: true}, + {name: "MaskedMulLowInt64x8", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt64x8", argLength: 3, commutative: true}, + {name: "MaskedOrInt64x8", argLength: 3, commutative: true}, + {name: "MaskedPopCountInt64x8", argLength: 2, commutative: false}, + {name: "MaskedSubInt64x8", argLength: 3, commutative: false}, + {name: "MaskedXorInt64x8", argLength: 3, commutative: true}, + {name: "MaxInt64x8", argLength: 2, commutative: true}, + {name: "MinInt64x8", argLength: 2, commutative: true}, + {name: "MulEvenWidenInt64x8", argLength: 2, commutative: true}, + {name: "MulLowInt64x8", argLength: 2, commutative: true}, + {name: "NotEqualInt64x8", argLength: 2, commutative: true}, + {name: "OrInt64x8", argLength: 2, commutative: true}, + {name: "PopCountInt64x8", argLength: 1, commutative: false}, + {name: "SubInt64x8", argLength: 2, commutative: false}, + {name: "XorInt64x8", argLength: 2, commutative: true}, + {name: "AbsoluteInt8x16", argLength: 1, commutative: false}, + {name: "AddInt8x16", argLength: 2, commutative: true}, + {name: "AndInt8x16", argLength: 2, commutative: true}, + {name: "AndNotInt8x16", argLength: 2, commutative: false}, + {name: "EqualInt8x16", argLength: 2, commutative: true}, + {name: "GreaterInt8x16", argLength: 2, commutative: false}, + {name: "GreaterEqualInt8x16", argLength: 2, commutative: false}, + {name: "LessInt8x16", argLength: 2, commutative: false}, + {name: "LessEqualInt8x16", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt8x16", argLength: 2, commutative: false}, + {name: "MaskedAddInt8x16", argLength: 3, commutative: true}, + {name: "MaskedEqualInt8x16", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt8x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt8x16", argLength: 3, commutative: false}, + {name: "MaskedLessInt8x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt8x16", argLength: 3, commutative: false}, + {name: "MaskedMaxInt8x16", argLength: 3, commutative: true}, + {name: "MaskedMinInt8x16", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt8x16", argLength: 3, commutative: true}, + {name: "MaskedPopCountInt8x16", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddInt8x16", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubInt8x16", argLength: 3, commutative: false}, + {name: "MaskedSubInt8x16", argLength: 3, commutative: false}, + {name: "MaxInt8x16", argLength: 2, commutative: true}, + {name: "MinInt8x16", argLength: 2, commutative: true}, + {name: "NotEqualInt8x16", argLength: 2, commutative: true}, + {name: "OrInt8x16", argLength: 2, commutative: true}, + {name: "PopCountInt8x16", argLength: 1, commutative: false}, + {name: "SaturatedAddInt8x16", argLength: 2, commutative: true}, + {name: "SaturatedSubInt8x16", argLength: 2, commutative: false}, + {name: "SignInt8x16", argLength: 2, commutative: false}, + {name: "SubInt8x16", argLength: 2, commutative: false}, + {name: "XorInt8x16", argLength: 2, commutative: true}, + {name: "AbsoluteInt8x32", argLength: 1, commutative: false}, + {name: "AddInt8x32", argLength: 2, commutative: true}, + {name: "AndInt8x32", argLength: 2, commutative: true}, + {name: "AndNotInt8x32", argLength: 2, commutative: false}, + {name: "EqualInt8x32", argLength: 2, commutative: true}, + {name: "GreaterInt8x32", argLength: 2, commutative: false}, + {name: "GreaterEqualInt8x32", argLength: 2, commutative: false}, + {name: "LessInt8x32", argLength: 2, commutative: false}, + {name: "LessEqualInt8x32", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt8x32", argLength: 2, commutative: false}, + {name: "MaskedAddInt8x32", argLength: 3, commutative: true}, + {name: "MaskedEqualInt8x32", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt8x32", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt8x32", argLength: 3, commutative: false}, + {name: "MaskedLessInt8x32", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt8x32", argLength: 3, commutative: false}, + {name: "MaskedMaxInt8x32", argLength: 3, commutative: true}, + {name: "MaskedMinInt8x32", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt8x32", argLength: 3, commutative: true}, + {name: "MaskedPopCountInt8x32", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddInt8x32", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubInt8x32", argLength: 3, commutative: false}, + {name: "MaskedSubInt8x32", argLength: 3, commutative: false}, + {name: "MaxInt8x32", argLength: 2, commutative: true}, + {name: "MinInt8x32", argLength: 2, commutative: true}, + {name: "NotEqualInt8x32", argLength: 2, commutative: true}, + {name: "OrInt8x32", argLength: 2, commutative: true}, + {name: "PopCountInt8x32", argLength: 1, commutative: false}, + {name: "SaturatedAddInt8x32", argLength: 2, commutative: true}, + {name: "SaturatedSubInt8x32", argLength: 2, commutative: false}, + {name: "SignInt8x32", argLength: 2, commutative: false}, + {name: "SubInt8x32", argLength: 2, commutative: false}, + {name: "XorInt8x32", argLength: 2, commutative: true}, + {name: "AbsoluteInt8x64", argLength: 1, commutative: false}, + {name: "AddInt8x64", argLength: 2, commutative: true}, + {name: "EqualInt8x64", argLength: 2, commutative: true}, + {name: "GreaterInt8x64", argLength: 2, commutative: false}, + {name: "GreaterEqualInt8x64", argLength: 2, commutative: false}, + {name: "LessInt8x64", argLength: 2, commutative: false}, + {name: "LessEqualInt8x64", argLength: 2, commutative: false}, + {name: "MaskedAbsoluteInt8x64", argLength: 2, commutative: false}, + {name: "MaskedAddInt8x64", argLength: 3, commutative: true}, + {name: "MaskedEqualInt8x64", argLength: 3, commutative: true}, + {name: "MaskedGreaterInt8x64", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualInt8x64", argLength: 3, commutative: false}, + {name: "MaskedLessInt8x64", argLength: 3, commutative: false}, + {name: "MaskedLessEqualInt8x64", argLength: 3, commutative: false}, + {name: "MaskedMaxInt8x64", argLength: 3, commutative: true}, + {name: "MaskedMinInt8x64", argLength: 3, commutative: true}, + {name: "MaskedNotEqualInt8x64", argLength: 3, commutative: true}, + {name: "MaskedPopCountInt8x64", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddInt8x64", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubInt8x64", argLength: 3, commutative: false}, + {name: "MaskedSubInt8x64", argLength: 3, commutative: false}, + {name: "MaxInt8x64", argLength: 2, commutative: true}, + {name: "MinInt8x64", argLength: 2, commutative: true}, + {name: "NotEqualInt8x64", argLength: 2, commutative: true}, + {name: "PopCountInt8x64", argLength: 1, commutative: false}, + {name: "SaturatedAddInt8x64", argLength: 2, commutative: true}, + {name: "SaturatedSubInt8x64", argLength: 2, commutative: false}, + {name: "SubInt8x64", argLength: 2, commutative: false}, + {name: "AddUint16x16", argLength: 2, commutative: true}, + {name: "AndUint16x16", argLength: 2, commutative: true}, + {name: "AndNotUint16x16", argLength: 2, commutative: false}, + {name: "AverageUint16x16", argLength: 2, commutative: true}, + {name: "EqualUint16x16", argLength: 2, commutative: true}, + {name: "GreaterUint16x16", argLength: 2, commutative: false}, + {name: "GreaterEqualUint16x16", argLength: 2, commutative: false}, + {name: "LessUint16x16", argLength: 2, commutative: false}, + {name: "LessEqualUint16x16", argLength: 2, commutative: false}, + {name: "MaskedAddUint16x16", argLength: 3, commutative: true}, + {name: "MaskedAverageUint16x16", argLength: 3, commutative: true}, + {name: "MaskedEqualUint16x16", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint16x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint16x16", argLength: 3, commutative: false}, + {name: "MaskedLessUint16x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint16x16", argLength: 3, commutative: false}, + {name: "MaskedMaxUint16x16", argLength: 3, commutative: true}, + {name: "MaskedMinUint16x16", argLength: 3, commutative: true}, + {name: "MaskedMulHighUint16x16", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint16x16", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint16x16", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddUint16x16", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubUint16x16", argLength: 3, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedPairDotProdUint16x16", argLength: 3, commutative: false}, + {name: "MaskedSubUint16x16", argLength: 3, commutative: false}, + {name: "MaxUint16x16", argLength: 2, commutative: true}, + {name: "MinUint16x16", argLength: 2, commutative: true}, + {name: "MulHighUint16x16", argLength: 2, commutative: true}, + {name: "NotEqualUint16x16", argLength: 2, commutative: true}, + {name: "OrUint16x16", argLength: 2, commutative: true}, + {name: "PairwiseAddUint16x16", argLength: 2, commutative: false}, + {name: "PairwiseSubUint16x16", argLength: 2, commutative: false}, + {name: "PopCountUint16x16", argLength: 1, commutative: false}, + {name: "SaturatedAddUint16x16", argLength: 2, commutative: true}, + {name: "SaturatedSubUint16x16", argLength: 2, commutative: false}, + {name: "SaturatedUnsignedSignedPairDotProdUint16x16", argLength: 2, commutative: false}, + {name: "SubUint16x16", argLength: 2, commutative: false}, + {name: "XorUint16x16", argLength: 2, commutative: true}, + {name: "AddUint16x32", argLength: 2, commutative: true}, + {name: "AverageUint16x32", argLength: 2, commutative: true}, + {name: "EqualUint16x32", argLength: 2, commutative: true}, + {name: "GreaterUint16x32", argLength: 2, commutative: false}, + {name: "GreaterEqualUint16x32", argLength: 2, commutative: false}, + {name: "LessUint16x32", argLength: 2, commutative: false}, + {name: "LessEqualUint16x32", argLength: 2, commutative: false}, + {name: "MaskedAddUint16x32", argLength: 3, commutative: true}, + {name: "MaskedAverageUint16x32", argLength: 3, commutative: true}, + {name: "MaskedEqualUint16x32", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint16x32", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint16x32", argLength: 3, commutative: false}, + {name: "MaskedLessUint16x32", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint16x32", argLength: 3, commutative: false}, + {name: "MaskedMaxUint16x32", argLength: 3, commutative: true}, + {name: "MaskedMinUint16x32", argLength: 3, commutative: true}, + {name: "MaskedMulHighUint16x32", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint16x32", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint16x32", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddUint16x32", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubUint16x32", argLength: 3, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedPairDotProdUint16x32", argLength: 3, commutative: false}, + {name: "MaskedSubUint16x32", argLength: 3, commutative: false}, + {name: "MaxUint16x32", argLength: 2, commutative: true}, + {name: "MinUint16x32", argLength: 2, commutative: true}, + {name: "MulHighUint16x32", argLength: 2, commutative: true}, + {name: "NotEqualUint16x32", argLength: 2, commutative: true}, + {name: "PopCountUint16x32", argLength: 1, commutative: false}, + {name: "SaturatedAddUint16x32", argLength: 2, commutative: true}, + {name: "SaturatedSubUint16x32", argLength: 2, commutative: false}, + {name: "SaturatedUnsignedSignedPairDotProdUint16x32", argLength: 2, commutative: false}, + {name: "SubUint16x32", argLength: 2, commutative: false}, + {name: "AddUint16x8", argLength: 2, commutative: true}, + {name: "AndUint16x8", argLength: 2, commutative: true}, + {name: "AndNotUint16x8", argLength: 2, commutative: false}, + {name: "AverageUint16x8", argLength: 2, commutative: true}, + {name: "EqualUint16x8", argLength: 2, commutative: true}, + {name: "GreaterUint16x8", argLength: 2, commutative: false}, + {name: "GreaterEqualUint16x8", argLength: 2, commutative: false}, + {name: "LessUint16x8", argLength: 2, commutative: false}, + {name: "LessEqualUint16x8", argLength: 2, commutative: false}, + {name: "MaskedAddUint16x8", argLength: 3, commutative: true}, + {name: "MaskedAverageUint16x8", argLength: 3, commutative: true}, + {name: "MaskedEqualUint16x8", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint16x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint16x8", argLength: 3, commutative: false}, + {name: "MaskedLessUint16x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint16x8", argLength: 3, commutative: false}, + {name: "MaskedMaxUint16x8", argLength: 3, commutative: true}, + {name: "MaskedMinUint16x8", argLength: 3, commutative: true}, + {name: "MaskedMulHighUint16x8", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint16x8", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint16x8", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddUint16x8", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubUint16x8", argLength: 3, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedPairDotProdUint16x8", argLength: 3, commutative: false}, + {name: "MaskedSubUint16x8", argLength: 3, commutative: false}, + {name: "MaxUint16x8", argLength: 2, commutative: true}, + {name: "MinUint16x8", argLength: 2, commutative: true}, + {name: "MulHighUint16x8", argLength: 2, commutative: true}, + {name: "NotEqualUint16x8", argLength: 2, commutative: true}, + {name: "OrUint16x8", argLength: 2, commutative: true}, + {name: "PairwiseAddUint16x8", argLength: 2, commutative: false}, + {name: "PairwiseSubUint16x8", argLength: 2, commutative: false}, + {name: "PopCountUint16x8", argLength: 1, commutative: false}, + {name: "SaturatedAddUint16x8", argLength: 2, commutative: true}, + {name: "SaturatedSubUint16x8", argLength: 2, commutative: false}, + {name: "SaturatedUnsignedSignedPairDotProdUint16x8", argLength: 2, commutative: false}, + {name: "SubUint16x8", argLength: 2, commutative: false}, + {name: "XorUint16x8", argLength: 2, commutative: true}, + {name: "AddUint32x16", argLength: 2, commutative: true}, + {name: "AndUint32x16", argLength: 2, commutative: true}, + {name: "AndNotUint32x16", argLength: 2, commutative: false}, + {name: "EqualUint32x16", argLength: 2, commutative: true}, + {name: "GreaterUint32x16", argLength: 2, commutative: false}, + {name: "GreaterEqualUint32x16", argLength: 2, commutative: false}, + {name: "LessUint32x16", argLength: 2, commutative: false}, + {name: "LessEqualUint32x16", argLength: 2, commutative: false}, + {name: "MaskedAddUint32x16", argLength: 3, commutative: true}, + {name: "MaskedAndUint32x16", argLength: 3, commutative: true}, + {name: "MaskedAndNotUint32x16", argLength: 3, commutative: false}, + {name: "MaskedEqualUint32x16", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint32x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint32x16", argLength: 3, commutative: false}, + {name: "MaskedLessUint32x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint32x16", argLength: 3, commutative: false}, + {name: "MaskedMaxUint32x16", argLength: 3, commutative: true}, + {name: "MaskedMinUint32x16", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint32x16", argLength: 3, commutative: true}, + {name: "MaskedOrUint32x16", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint32x16", argLength: 2, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false}, + {name: "MaskedSubUint32x16", argLength: 3, commutative: false}, + {name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 4, commutative: false}, + {name: "MaskedXorUint32x16", argLength: 3, commutative: true}, + {name: "MaxUint32x16", argLength: 2, commutative: true}, + {name: "MinUint32x16", argLength: 2, commutative: true}, + {name: "NotEqualUint32x16", argLength: 2, commutative: true}, + {name: "OrUint32x16", argLength: 2, commutative: true}, + {name: "PopCountUint32x16", argLength: 1, commutative: false}, + {name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false}, + {name: "SubUint32x16", argLength: 2, commutative: false}, + {name: "UnsignedSignedQuadDotProdAccumulateUint32x16", argLength: 3, commutative: false}, + {name: "XorUint32x16", argLength: 2, commutative: true}, + {name: "AddUint32x4", argLength: 2, commutative: true}, + {name: "AndUint32x4", argLength: 2, commutative: true}, + {name: "AndNotUint32x4", argLength: 2, commutative: false}, + {name: "EqualUint32x4", argLength: 2, commutative: true}, + {name: "GreaterUint32x4", argLength: 2, commutative: false}, + {name: "GreaterEqualUint32x4", argLength: 2, commutative: false}, + {name: "LessUint32x4", argLength: 2, commutative: false}, + {name: "LessEqualUint32x4", argLength: 2, commutative: false}, + {name: "MaskedAddUint32x4", argLength: 3, commutative: true}, + {name: "MaskedAndUint32x4", argLength: 3, commutative: true}, + {name: "MaskedAndNotUint32x4", argLength: 3, commutative: false}, + {name: "MaskedEqualUint32x4", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint32x4", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint32x4", argLength: 3, commutative: false}, + {name: "MaskedLessUint32x4", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint32x4", argLength: 3, commutative: false}, + {name: "MaskedMaxUint32x4", argLength: 3, commutative: true}, + {name: "MaskedMinUint32x4", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint32x4", argLength: 3, commutative: true}, + {name: "MaskedOrUint32x4", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint32x4", argLength: 2, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false}, + {name: "MaskedSubUint32x4", argLength: 3, commutative: false}, + {name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 4, commutative: false}, + {name: "MaskedXorUint32x4", argLength: 3, commutative: true}, + {name: "MaxUint32x4", argLength: 2, commutative: true}, + {name: "MinUint32x4", argLength: 2, commutative: true}, + {name: "MulEvenWidenUint32x4", argLength: 2, commutative: true}, + {name: "NotEqualUint32x4", argLength: 2, commutative: true}, + {name: "OrUint32x4", argLength: 2, commutative: true}, + {name: "PairwiseAddUint32x4", argLength: 2, commutative: false}, + {name: "PairwiseSubUint32x4", argLength: 2, commutative: false}, + {name: "PopCountUint32x4", argLength: 1, commutative: false}, + {name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false}, + {name: "SubUint32x4", argLength: 2, commutative: false}, + {name: "UnsignedSignedQuadDotProdAccumulateUint32x4", argLength: 3, commutative: false}, + {name: "XorUint32x4", argLength: 2, commutative: true}, + {name: "AddUint32x8", argLength: 2, commutative: true}, + {name: "AndUint32x8", argLength: 2, commutative: true}, + {name: "AndNotUint32x8", argLength: 2, commutative: false}, + {name: "EqualUint32x8", argLength: 2, commutative: true}, + {name: "GreaterUint32x8", argLength: 2, commutative: false}, + {name: "GreaterEqualUint32x8", argLength: 2, commutative: false}, + {name: "LessUint32x8", argLength: 2, commutative: false}, + {name: "LessEqualUint32x8", argLength: 2, commutative: false}, + {name: "MaskedAddUint32x8", argLength: 3, commutative: true}, + {name: "MaskedAndUint32x8", argLength: 3, commutative: true}, + {name: "MaskedAndNotUint32x8", argLength: 3, commutative: false}, + {name: "MaskedEqualUint32x8", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint32x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint32x8", argLength: 3, commutative: false}, + {name: "MaskedLessUint32x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint32x8", argLength: 3, commutative: false}, + {name: "MaskedMaxUint32x8", argLength: 3, commutative: true}, + {name: "MaskedMinUint32x8", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint32x8", argLength: 3, commutative: true}, + {name: "MaskedOrUint32x8", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint32x8", argLength: 2, commutative: false}, + {name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false}, + {name: "MaskedSubUint32x8", argLength: 3, commutative: false}, + {name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 4, commutative: false}, + {name: "MaskedXorUint32x8", argLength: 3, commutative: true}, + {name: "MaxUint32x8", argLength: 2, commutative: true}, + {name: "MinUint32x8", argLength: 2, commutative: true}, + {name: "MulEvenWidenUint32x8", argLength: 2, commutative: true}, + {name: "NotEqualUint32x8", argLength: 2, commutative: true}, + {name: "OrUint32x8", argLength: 2, commutative: true}, + {name: "PairwiseAddUint32x8", argLength: 2, commutative: false}, + {name: "PairwiseSubUint32x8", argLength: 2, commutative: false}, + {name: "PopCountUint32x8", argLength: 1, commutative: false}, + {name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false}, + {name: "SubUint32x8", argLength: 2, commutative: false}, + {name: "UnsignedSignedQuadDotProdAccumulateUint32x8", argLength: 3, commutative: false}, + {name: "XorUint32x8", argLength: 2, commutative: true}, + {name: "AddUint64x2", argLength: 2, commutative: true}, + {name: "AndUint64x2", argLength: 2, commutative: true}, + {name: "AndNotUint64x2", argLength: 2, commutative: false}, + {name: "EqualUint64x2", argLength: 2, commutative: true}, + {name: "GreaterUint64x2", argLength: 2, commutative: false}, + {name: "GreaterEqualUint64x2", argLength: 2, commutative: false}, + {name: "LessUint64x2", argLength: 2, commutative: false}, + {name: "LessEqualUint64x2", argLength: 2, commutative: false}, + {name: "MaskedAddUint64x2", argLength: 3, commutative: true}, + {name: "MaskedAndUint64x2", argLength: 3, commutative: true}, + {name: "MaskedAndNotUint64x2", argLength: 3, commutative: false}, + {name: "MaskedEqualUint64x2", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint64x2", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint64x2", argLength: 3, commutative: false}, + {name: "MaskedLessUint64x2", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint64x2", argLength: 3, commutative: false}, + {name: "MaskedMaxUint64x2", argLength: 3, commutative: true}, + {name: "MaskedMinUint64x2", argLength: 3, commutative: true}, + {name: "MaskedMulEvenWidenUint64x2", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint64x2", argLength: 3, commutative: true}, + {name: "MaskedOrUint64x2", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint64x2", argLength: 2, commutative: false}, + {name: "MaskedSubUint64x2", argLength: 3, commutative: false}, + {name: "MaskedXorUint64x2", argLength: 3, commutative: true}, + {name: "MaxUint64x2", argLength: 2, commutative: true}, + {name: "MinUint64x2", argLength: 2, commutative: true}, + {name: "MulEvenWidenUint64x2", argLength: 2, commutative: true}, + {name: "NotEqualUint64x2", argLength: 2, commutative: true}, + {name: "OrUint64x2", argLength: 2, commutative: true}, + {name: "PopCountUint64x2", argLength: 1, commutative: false}, + {name: "SubUint64x2", argLength: 2, commutative: false}, + {name: "XorUint64x2", argLength: 2, commutative: true}, + {name: "AddUint64x4", argLength: 2, commutative: true}, + {name: "AndUint64x4", argLength: 2, commutative: true}, + {name: "AndNotUint64x4", argLength: 2, commutative: false}, + {name: "EqualUint64x4", argLength: 2, commutative: true}, + {name: "GreaterUint64x4", argLength: 2, commutative: false}, + {name: "GreaterEqualUint64x4", argLength: 2, commutative: false}, + {name: "LessUint64x4", argLength: 2, commutative: false}, + {name: "LessEqualUint64x4", argLength: 2, commutative: false}, + {name: "MaskedAddUint64x4", argLength: 3, commutative: true}, + {name: "MaskedAndUint64x4", argLength: 3, commutative: true}, + {name: "MaskedAndNotUint64x4", argLength: 3, commutative: false}, + {name: "MaskedEqualUint64x4", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint64x4", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint64x4", argLength: 3, commutative: false}, + {name: "MaskedLessUint64x4", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint64x4", argLength: 3, commutative: false}, + {name: "MaskedMaxUint64x4", argLength: 3, commutative: true}, + {name: "MaskedMinUint64x4", argLength: 3, commutative: true}, + {name: "MaskedMulEvenWidenUint64x4", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint64x4", argLength: 3, commutative: true}, + {name: "MaskedOrUint64x4", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint64x4", argLength: 2, commutative: false}, + {name: "MaskedSubUint64x4", argLength: 3, commutative: false}, + {name: "MaskedXorUint64x4", argLength: 3, commutative: true}, + {name: "MaxUint64x4", argLength: 2, commutative: true}, + {name: "MinUint64x4", argLength: 2, commutative: true}, + {name: "MulEvenWidenUint64x4", argLength: 2, commutative: true}, + {name: "NotEqualUint64x4", argLength: 2, commutative: true}, + {name: "OrUint64x4", argLength: 2, commutative: true}, + {name: "PopCountUint64x4", argLength: 1, commutative: false}, + {name: "SubUint64x4", argLength: 2, commutative: false}, + {name: "XorUint64x4", argLength: 2, commutative: true}, + {name: "AddUint64x8", argLength: 2, commutative: true}, + {name: "AndUint64x8", argLength: 2, commutative: true}, + {name: "AndNotUint64x8", argLength: 2, commutative: false}, + {name: "EqualUint64x8", argLength: 2, commutative: true}, + {name: "GreaterUint64x8", argLength: 2, commutative: false}, + {name: "GreaterEqualUint64x8", argLength: 2, commutative: false}, + {name: "LessUint64x8", argLength: 2, commutative: false}, + {name: "LessEqualUint64x8", argLength: 2, commutative: false}, + {name: "MaskedAddUint64x8", argLength: 3, commutative: true}, + {name: "MaskedAndUint64x8", argLength: 3, commutative: true}, + {name: "MaskedAndNotUint64x8", argLength: 3, commutative: false}, + {name: "MaskedEqualUint64x8", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint64x8", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint64x8", argLength: 3, commutative: false}, + {name: "MaskedLessUint64x8", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint64x8", argLength: 3, commutative: false}, + {name: "MaskedMaxUint64x8", argLength: 3, commutative: true}, + {name: "MaskedMinUint64x8", argLength: 3, commutative: true}, + {name: "MaskedMulEvenWidenUint64x8", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint64x8", argLength: 3, commutative: true}, + {name: "MaskedOrUint64x8", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint64x8", argLength: 2, commutative: false}, + {name: "MaskedSubUint64x8", argLength: 3, commutative: false}, + {name: "MaskedXorUint64x8", argLength: 3, commutative: true}, + {name: "MaxUint64x8", argLength: 2, commutative: true}, + {name: "MinUint64x8", argLength: 2, commutative: true}, + {name: "MulEvenWidenUint64x8", argLength: 2, commutative: true}, + {name: "NotEqualUint64x8", argLength: 2, commutative: true}, + {name: "OrUint64x8", argLength: 2, commutative: true}, + {name: "PopCountUint64x8", argLength: 1, commutative: false}, + {name: "SubUint64x8", argLength: 2, commutative: false}, + {name: "XorUint64x8", argLength: 2, commutative: true}, + {name: "AddUint8x16", argLength: 2, commutative: true}, + {name: "AndUint8x16", argLength: 2, commutative: true}, + {name: "AndNotUint8x16", argLength: 2, commutative: false}, + {name: "AverageUint8x16", argLength: 2, commutative: true}, + {name: "EqualUint8x16", argLength: 2, commutative: true}, + {name: "GreaterUint8x16", argLength: 2, commutative: false}, + {name: "GreaterEqualUint8x16", argLength: 2, commutative: false}, + {name: "LessUint8x16", argLength: 2, commutative: false}, + {name: "LessEqualUint8x16", argLength: 2, commutative: false}, + {name: "MaskedAddUint8x16", argLength: 3, commutative: true}, + {name: "MaskedAverageUint8x16", argLength: 3, commutative: true}, + {name: "MaskedEqualUint8x16", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint8x16", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint8x16", argLength: 3, commutative: false}, + {name: "MaskedLessUint8x16", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint8x16", argLength: 3, commutative: false}, + {name: "MaskedMaxUint8x16", argLength: 3, commutative: true}, + {name: "MaskedMinUint8x16", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint8x16", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint8x16", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddUint8x16", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubUint8x16", argLength: 3, commutative: false}, + {name: "MaskedSubUint8x16", argLength: 3, commutative: false}, + {name: "MaxUint8x16", argLength: 2, commutative: true}, + {name: "MinUint8x16", argLength: 2, commutative: true}, + {name: "NotEqualUint8x16", argLength: 2, commutative: true}, + {name: "OrUint8x16", argLength: 2, commutative: true}, + {name: "PopCountUint8x16", argLength: 1, commutative: false}, + {name: "SaturatedAddUint8x16", argLength: 2, commutative: true}, + {name: "SaturatedSubUint8x16", argLength: 2, commutative: false}, + {name: "SaturatedUnsignedSignedPairDotProdUint8x16", argLength: 2, commutative: false}, + {name: "SubUint8x16", argLength: 2, commutative: false}, + {name: "XorUint8x16", argLength: 2, commutative: true}, + {name: "AddUint8x32", argLength: 2, commutative: true}, + {name: "AndUint8x32", argLength: 2, commutative: true}, + {name: "AndNotUint8x32", argLength: 2, commutative: false}, + {name: "AverageUint8x32", argLength: 2, commutative: true}, + {name: "EqualUint8x32", argLength: 2, commutative: true}, + {name: "GreaterUint8x32", argLength: 2, commutative: false}, + {name: "GreaterEqualUint8x32", argLength: 2, commutative: false}, + {name: "LessUint8x32", argLength: 2, commutative: false}, + {name: "LessEqualUint8x32", argLength: 2, commutative: false}, + {name: "MaskedAddUint8x32", argLength: 3, commutative: true}, + {name: "MaskedAverageUint8x32", argLength: 3, commutative: true}, + {name: "MaskedEqualUint8x32", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint8x32", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint8x32", argLength: 3, commutative: false}, + {name: "MaskedLessUint8x32", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint8x32", argLength: 3, commutative: false}, + {name: "MaskedMaxUint8x32", argLength: 3, commutative: true}, + {name: "MaskedMinUint8x32", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint8x32", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint8x32", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddUint8x32", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubUint8x32", argLength: 3, commutative: false}, + {name: "MaskedSubUint8x32", argLength: 3, commutative: false}, + {name: "MaxUint8x32", argLength: 2, commutative: true}, + {name: "MinUint8x32", argLength: 2, commutative: true}, + {name: "NotEqualUint8x32", argLength: 2, commutative: true}, + {name: "OrUint8x32", argLength: 2, commutative: true}, + {name: "PopCountUint8x32", argLength: 1, commutative: false}, + {name: "SaturatedAddUint8x32", argLength: 2, commutative: true}, + {name: "SaturatedSubUint8x32", argLength: 2, commutative: false}, + {name: "SaturatedUnsignedSignedPairDotProdUint8x32", argLength: 2, commutative: false}, + {name: "SubUint8x32", argLength: 2, commutative: false}, + {name: "XorUint8x32", argLength: 2, commutative: true}, + {name: "AddUint8x64", argLength: 2, commutative: true}, + {name: "AverageUint8x64", argLength: 2, commutative: true}, + {name: "EqualUint8x64", argLength: 2, commutative: true}, + {name: "GreaterUint8x64", argLength: 2, commutative: false}, + {name: "GreaterEqualUint8x64", argLength: 2, commutative: false}, + {name: "LessUint8x64", argLength: 2, commutative: false}, + {name: "LessEqualUint8x64", argLength: 2, commutative: false}, + {name: "MaskedAddUint8x64", argLength: 3, commutative: true}, + {name: "MaskedAverageUint8x64", argLength: 3, commutative: true}, + {name: "MaskedEqualUint8x64", argLength: 3, commutative: true}, + {name: "MaskedGreaterUint8x64", argLength: 3, commutative: false}, + {name: "MaskedGreaterEqualUint8x64", argLength: 3, commutative: false}, + {name: "MaskedLessUint8x64", argLength: 3, commutative: false}, + {name: "MaskedLessEqualUint8x64", argLength: 3, commutative: false}, + {name: "MaskedMaxUint8x64", argLength: 3, commutative: true}, + {name: "MaskedMinUint8x64", argLength: 3, commutative: true}, + {name: "MaskedNotEqualUint8x64", argLength: 3, commutative: true}, + {name: "MaskedPopCountUint8x64", argLength: 2, commutative: false}, + {name: "MaskedSaturatedAddUint8x64", argLength: 3, commutative: true}, + {name: "MaskedSaturatedSubUint8x64", argLength: 3, commutative: false}, + {name: "MaskedSubUint8x64", argLength: 3, commutative: false}, + {name: "MaxUint8x64", argLength: 2, commutative: true}, + {name: "MinUint8x64", argLength: 2, commutative: true}, + {name: "NotEqualUint8x64", argLength: 2, commutative: true}, + {name: "PopCountUint8x64", argLength: 1, commutative: false}, + {name: "SaturatedAddUint8x64", argLength: 2, commutative: true}, + {name: "SaturatedSubUint8x64", argLength: 2, commutative: false}, + {name: "SubUint8x64", argLength: 2, commutative: false}, + {name: "CeilSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedCeilWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncWithPrecisionFloat32x16", argLength: 2, commutative: false, aux: "Int8"}, + {name: "RoundSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "RoundWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncSuppressExceptionWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncWithPrecisionFloat32x16", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedCeilWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncWithPrecisionFloat32x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "RoundSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "RoundWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncSuppressExceptionWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncWithPrecisionFloat32x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedCeilWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncWithPrecisionFloat32x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "RoundSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "RoundWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncSuppressExceptionWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncWithPrecisionFloat32x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedCeilWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncWithPrecisionFloat64x2", argLength: 2, commutative: false, aux: "Int8"}, + {name: "RoundSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "RoundWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncSuppressExceptionWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncWithPrecisionFloat64x2", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedCeilWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncWithPrecisionFloat64x4", argLength: 2, commutative: false, aux: "Int8"}, + {name: "RoundSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "RoundWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncSuppressExceptionWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncWithPrecisionFloat64x4", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "CeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithCeilWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithFloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithRoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "DiffWithTruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "FloorWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedCeilWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithCeilWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithFloorWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithRoundWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedDiffWithTruncWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedFloorWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedRoundWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "MaskedTruncWithPrecisionFloat64x8", argLength: 2, commutative: false, aux: "Int8"}, + {name: "RoundSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "RoundWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncSuppressExceptionWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + {name: "TruncWithPrecisionFloat64x8", argLength: 1, commutative: false, aux: "Int8"}, + } +} diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/LICENSE b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/LICENSE new file mode 100644 index 00000000000000..2a7cf70da6e498 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/LICENSE @@ -0,0 +1,27 @@ +Copyright 2009 The Go Authors. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above +copyright notice, this list of conditions and the following disclaimer +in the documentation and/or other materials provided with the +distribution. + * Neither the name of Google LLC nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/PATENTS b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/PATENTS new file mode 100644 index 00000000000000..733099041f84fa --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/PATENTS @@ -0,0 +1,22 @@ +Additional IP Rights Grant (Patents) + +"This implementation" means the copyrightable works distributed by +Google as part of the Go project. + +Google hereby grants to You a perpetual, worldwide, non-exclusive, +no-charge, royalty-free, irrevocable (except as stated in this section) +patent license to make, have made, use, offer to sell, sell, import, +transfer and otherwise run, modify and propagate the contents of this +implementation of Go, where such license applies only to those patent +claims, both currently owned or controlled by Google and acquired in +the future, licensable by Google that are necessarily infringed by this +implementation of Go. This grant does not include claims that would be +infringed only as a consequence of further modification of this +implementation. If you or your agent or exclusive licensee institute or +order or agree to the institution of patent litigation against any +entity (including a cross-claim or counterclaim in a lawsuit) alleging +that this implementation of Go or any code incorporated within this +implementation of Go constitutes direct or contributory patent +infringement, or inducement of patent infringement, then any patent +rights granted to you under this License for this implementation of Go +shall terminate as of the date such litigation is filed. diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/enclosing.go b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/enclosing.go new file mode 100644 index 00000000000000..6e34df46130b75 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/enclosing.go @@ -0,0 +1,654 @@ +// Copyright 2013 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package astutil + +// This file defines utilities for working with source positions. + +import ( + "fmt" + "go/ast" + "go/token" + "sort" +) + +// PathEnclosingInterval returns the node that encloses the source +// interval [start, end), and all its ancestors up to the AST root. +// +// The definition of "enclosing" used by this function considers +// additional whitespace abutting a node to be enclosed by it. +// In this example: +// +// z := x + y // add them +// <-A-> +// <----B-----> +// +// the ast.BinaryExpr(+) node is considered to enclose interval B +// even though its [Pos()..End()) is actually only interval A. +// This behaviour makes user interfaces more tolerant of imperfect +// input. +// +// This function treats tokens as nodes, though they are not included +// in the result. e.g. PathEnclosingInterval("+") returns the +// enclosing ast.BinaryExpr("x + y"). +// +// If start==end, the 1-char interval following start is used instead. +// +// The 'exact' result is true if the interval contains only path[0] +// and perhaps some adjacent whitespace. It is false if the interval +// overlaps multiple children of path[0], or if it contains only +// interior whitespace of path[0]. +// In this example: +// +// z := x + y // add them +// <--C--> <---E--> +// ^ +// D +// +// intervals C, D and E are inexact. C is contained by the +// z-assignment statement, because it spans three of its children (:=, +// x, +). So too is the 1-char interval D, because it contains only +// interior whitespace of the assignment. E is considered interior +// whitespace of the BlockStmt containing the assignment. +// +// The resulting path is never empty; it always contains at least the +// 'root' *ast.File. Ideally PathEnclosingInterval would reject +// intervals that lie wholly or partially outside the range of the +// file, but unfortunately ast.File records only the token.Pos of +// the 'package' keyword, but not of the start of the file itself. +func PathEnclosingInterval(root *ast.File, start, end token.Pos) (path []ast.Node, exact bool) { + // fmt.Printf("EnclosingInterval %d %d\n", start, end) // debugging + + // Precondition: node.[Pos..End) and adjoining whitespace contain [start, end). + var visit func(node ast.Node) bool + visit = func(node ast.Node) bool { + path = append(path, node) + + nodePos := node.Pos() + nodeEnd := node.End() + + // fmt.Printf("visit(%T, %d, %d)\n", node, nodePos, nodeEnd) // debugging + + // Intersect [start, end) with interval of node. + if start < nodePos { + start = nodePos + } + if end > nodeEnd { + end = nodeEnd + } + + // Find sole child that contains [start, end). + children := childrenOf(node) + l := len(children) + for i, child := range children { + // [childPos, childEnd) is unaugmented interval of child. + childPos := child.Pos() + childEnd := child.End() + + // [augPos, augEnd) is whitespace-augmented interval of child. + augPos := childPos + augEnd := childEnd + if i > 0 { + augPos = children[i-1].End() // start of preceding whitespace + } + if i < l-1 { + nextChildPos := children[i+1].Pos() + // Does [start, end) lie between child and next child? + if start >= augEnd && end <= nextChildPos { + return false // inexact match + } + augEnd = nextChildPos // end of following whitespace + } + + // fmt.Printf("\tchild %d: [%d..%d)\tcontains interval [%d..%d)?\n", + // i, augPos, augEnd, start, end) // debugging + + // Does augmented child strictly contain [start, end)? + if augPos <= start && end <= augEnd { + if is[tokenNode](child) { + return true + } + + // childrenOf elides the FuncType node beneath FuncDecl. + // Add it back here for TypeParams, Params, Results, + // all FieldLists). But we don't add it back for the "func" token + // even though it is is the tree at FuncDecl.Type.Func. + if decl, ok := node.(*ast.FuncDecl); ok { + if fields, ok := child.(*ast.FieldList); ok && fields != decl.Recv { + path = append(path, decl.Type) + } + } + + return visit(child) + } + + // Does [start, end) overlap multiple children? + // i.e. left-augmented child contains start + // but LR-augmented child does not contain end. + if start < childEnd && end > augEnd { + break + } + } + + // No single child contained [start, end), + // so node is the result. Is it exact? + + // (It's tempting to put this condition before the + // child loop, but it gives the wrong result in the + // case where a node (e.g. ExprStmt) and its sole + // child have equal intervals.) + if start == nodePos && end == nodeEnd { + return true // exact match + } + + return false // inexact: overlaps multiple children + } + + // Ensure [start,end) is nondecreasing. + if start > end { + start, end = end, start + } + + if start < root.End() && end > root.Pos() { + if start == end { + end = start + 1 // empty interval => interval of size 1 + } + exact = visit(root) + + // Reverse the path: + for i, l := 0, len(path); i < l/2; i++ { + path[i], path[l-1-i] = path[l-1-i], path[i] + } + } else { + // Selection lies within whitespace preceding the + // first (or following the last) declaration in the file. + // The result nonetheless always includes the ast.File. + path = append(path, root) + } + + return +} + +// tokenNode is a dummy implementation of ast.Node for a single token. +// They are used transiently by PathEnclosingInterval but never escape +// this package. +type tokenNode struct { + pos token.Pos + end token.Pos +} + +func (n tokenNode) Pos() token.Pos { + return n.pos +} + +func (n tokenNode) End() token.Pos { + return n.end +} + +func tok(pos token.Pos, len int) ast.Node { + return tokenNode{pos, pos + token.Pos(len)} +} + +// childrenOf returns the direct non-nil children of ast.Node n. +// It may include fake ast.Node implementations for bare tokens. +// it is not safe to call (e.g.) ast.Walk on such nodes. +func childrenOf(n ast.Node) []ast.Node { + var children []ast.Node + + // First add nodes for all true subtrees. + ast.Inspect(n, func(node ast.Node) bool { + if node == n { // push n + return true // recur + } + if node != nil { // push child + children = append(children, node) + } + return false // no recursion + }) + + // Then add fake Nodes for bare tokens. + switch n := n.(type) { + case *ast.ArrayType: + children = append(children, + tok(n.Lbrack, len("[")), + tok(n.Elt.End(), len("]"))) + + case *ast.AssignStmt: + children = append(children, + tok(n.TokPos, len(n.Tok.String()))) + + case *ast.BasicLit: + children = append(children, + tok(n.ValuePos, len(n.Value))) + + case *ast.BinaryExpr: + children = append(children, tok(n.OpPos, len(n.Op.String()))) + + case *ast.BlockStmt: + children = append(children, + tok(n.Lbrace, len("{")), + tok(n.Rbrace, len("}"))) + + case *ast.BranchStmt: + children = append(children, + tok(n.TokPos, len(n.Tok.String()))) + + case *ast.CallExpr: + children = append(children, + tok(n.Lparen, len("(")), + tok(n.Rparen, len(")"))) + if n.Ellipsis != 0 { + children = append(children, tok(n.Ellipsis, len("..."))) + } + + case *ast.CaseClause: + if n.List == nil { + children = append(children, + tok(n.Case, len("default"))) + } else { + children = append(children, + tok(n.Case, len("case"))) + } + children = append(children, tok(n.Colon, len(":"))) + + case *ast.ChanType: + switch n.Dir { + case ast.RECV: + children = append(children, tok(n.Begin, len("<-chan"))) + case ast.SEND: + children = append(children, tok(n.Begin, len("chan<-"))) + case ast.RECV | ast.SEND: + children = append(children, tok(n.Begin, len("chan"))) + } + + case *ast.CommClause: + if n.Comm == nil { + children = append(children, + tok(n.Case, len("default"))) + } else { + children = append(children, + tok(n.Case, len("case"))) + } + children = append(children, tok(n.Colon, len(":"))) + + case *ast.Comment: + // nop + + case *ast.CommentGroup: + // nop + + case *ast.CompositeLit: + children = append(children, + tok(n.Lbrace, len("{")), + tok(n.Rbrace, len("{"))) + + case *ast.DeclStmt: + // nop + + case *ast.DeferStmt: + children = append(children, + tok(n.Defer, len("defer"))) + + case *ast.Ellipsis: + children = append(children, + tok(n.Ellipsis, len("..."))) + + case *ast.EmptyStmt: + // nop + + case *ast.ExprStmt: + // nop + + case *ast.Field: + // TODO(adonovan): Field.{Doc,Comment,Tag}? + + case *ast.FieldList: + children = append(children, + tok(n.Opening, len("(")), // or len("[") + tok(n.Closing, len(")"))) // or len("]") + + case *ast.File: + // TODO test: Doc + children = append(children, + tok(n.Package, len("package"))) + + case *ast.ForStmt: + children = append(children, + tok(n.For, len("for"))) + + case *ast.FuncDecl: + // TODO(adonovan): FuncDecl.Comment? + + // Uniquely, FuncDecl breaks the invariant that + // preorder traversal yields tokens in lexical order: + // in fact, FuncDecl.Recv precedes FuncDecl.Type.Func. + // + // As a workaround, we inline the case for FuncType + // here and order things correctly. + // We also need to insert the elided FuncType just + // before the 'visit' recursion. + // + children = nil // discard ast.Walk(FuncDecl) info subtrees + children = append(children, tok(n.Type.Func, len("func"))) + if n.Recv != nil { + children = append(children, n.Recv) + } + children = append(children, n.Name) + if tparams := n.Type.TypeParams; tparams != nil { + children = append(children, tparams) + } + if n.Type.Params != nil { + children = append(children, n.Type.Params) + } + if n.Type.Results != nil { + children = append(children, n.Type.Results) + } + if n.Body != nil { + children = append(children, n.Body) + } + + case *ast.FuncLit: + // nop + + case *ast.FuncType: + if n.Func != 0 { + children = append(children, + tok(n.Func, len("func"))) + } + + case *ast.GenDecl: + children = append(children, + tok(n.TokPos, len(n.Tok.String()))) + if n.Lparen != 0 { + children = append(children, + tok(n.Lparen, len("(")), + tok(n.Rparen, len(")"))) + } + + case *ast.GoStmt: + children = append(children, + tok(n.Go, len("go"))) + + case *ast.Ident: + children = append(children, + tok(n.NamePos, len(n.Name))) + + case *ast.IfStmt: + children = append(children, + tok(n.If, len("if"))) + + case *ast.ImportSpec: + // TODO(adonovan): ImportSpec.{Doc,EndPos}? + + case *ast.IncDecStmt: + children = append(children, + tok(n.TokPos, len(n.Tok.String()))) + + case *ast.IndexExpr: + children = append(children, + tok(n.Lbrack, len("[")), + tok(n.Rbrack, len("]"))) + + case *ast.IndexListExpr: + children = append(children, + tok(n.Lbrack, len("[")), + tok(n.Rbrack, len("]"))) + + case *ast.InterfaceType: + children = append(children, + tok(n.Interface, len("interface"))) + + case *ast.KeyValueExpr: + children = append(children, + tok(n.Colon, len(":"))) + + case *ast.LabeledStmt: + children = append(children, + tok(n.Colon, len(":"))) + + case *ast.MapType: + children = append(children, + tok(n.Map, len("map"))) + + case *ast.ParenExpr: + children = append(children, + tok(n.Lparen, len("(")), + tok(n.Rparen, len(")"))) + + case *ast.RangeStmt: + children = append(children, + tok(n.For, len("for")), + tok(n.TokPos, len(n.Tok.String()))) + + case *ast.ReturnStmt: + children = append(children, + tok(n.Return, len("return"))) + + case *ast.SelectStmt: + children = append(children, + tok(n.Select, len("select"))) + + case *ast.SelectorExpr: + // nop + + case *ast.SendStmt: + children = append(children, + tok(n.Arrow, len("<-"))) + + case *ast.SliceExpr: + children = append(children, + tok(n.Lbrack, len("[")), + tok(n.Rbrack, len("]"))) + + case *ast.StarExpr: + children = append(children, tok(n.Star, len("*"))) + + case *ast.StructType: + children = append(children, tok(n.Struct, len("struct"))) + + case *ast.SwitchStmt: + children = append(children, tok(n.Switch, len("switch"))) + + case *ast.TypeAssertExpr: + children = append(children, + tok(n.Lparen-1, len(".")), + tok(n.Lparen, len("(")), + tok(n.Rparen, len(")"))) + + case *ast.TypeSpec: + // TODO(adonovan): TypeSpec.{Doc,Comment}? + + case *ast.TypeSwitchStmt: + children = append(children, tok(n.Switch, len("switch"))) + + case *ast.UnaryExpr: + children = append(children, tok(n.OpPos, len(n.Op.String()))) + + case *ast.ValueSpec: + // TODO(adonovan): ValueSpec.{Doc,Comment}? + + case *ast.BadDecl, *ast.BadExpr, *ast.BadStmt: + // nop + } + + // TODO(adonovan): opt: merge the logic of ast.Inspect() into + // the switch above so we can make interleaved callbacks for + // both Nodes and Tokens in the right order and avoid the need + // to sort. + sort.Sort(byPos(children)) + + return children +} + +type byPos []ast.Node + +func (sl byPos) Len() int { + return len(sl) +} +func (sl byPos) Less(i, j int) bool { + return sl[i].Pos() < sl[j].Pos() +} +func (sl byPos) Swap(i, j int) { + sl[i], sl[j] = sl[j], sl[i] +} + +// NodeDescription returns a description of the concrete type of n suitable +// for a user interface. +// +// TODO(adonovan): in some cases (e.g. Field, FieldList, Ident, +// StarExpr) we could be much more specific given the path to the AST +// root. Perhaps we should do that. +func NodeDescription(n ast.Node) string { + switch n := n.(type) { + case *ast.ArrayType: + return "array type" + case *ast.AssignStmt: + return "assignment" + case *ast.BadDecl: + return "bad declaration" + case *ast.BadExpr: + return "bad expression" + case *ast.BadStmt: + return "bad statement" + case *ast.BasicLit: + return "basic literal" + case *ast.BinaryExpr: + return fmt.Sprintf("binary %s operation", n.Op) + case *ast.BlockStmt: + return "block" + case *ast.BranchStmt: + switch n.Tok { + case token.BREAK: + return "break statement" + case token.CONTINUE: + return "continue statement" + case token.GOTO: + return "goto statement" + case token.FALLTHROUGH: + return "fall-through statement" + } + case *ast.CallExpr: + if len(n.Args) == 1 && !n.Ellipsis.IsValid() { + return "function call (or conversion)" + } + return "function call" + case *ast.CaseClause: + return "case clause" + case *ast.ChanType: + return "channel type" + case *ast.CommClause: + return "communication clause" + case *ast.Comment: + return "comment" + case *ast.CommentGroup: + return "comment group" + case *ast.CompositeLit: + return "composite literal" + case *ast.DeclStmt: + return NodeDescription(n.Decl) + " statement" + case *ast.DeferStmt: + return "defer statement" + case *ast.Ellipsis: + return "ellipsis" + case *ast.EmptyStmt: + return "empty statement" + case *ast.ExprStmt: + return "expression statement" + case *ast.Field: + // Can be any of these: + // struct {x, y int} -- struct field(s) + // struct {T} -- anon struct field + // interface {I} -- interface embedding + // interface {f()} -- interface method + // func (A) func(B) C -- receiver, param(s), result(s) + return "field/method/parameter" + case *ast.FieldList: + return "field/method/parameter list" + case *ast.File: + return "source file" + case *ast.ForStmt: + return "for loop" + case *ast.FuncDecl: + return "function declaration" + case *ast.FuncLit: + return "function literal" + case *ast.FuncType: + return "function type" + case *ast.GenDecl: + switch n.Tok { + case token.IMPORT: + return "import declaration" + case token.CONST: + return "constant declaration" + case token.TYPE: + return "type declaration" + case token.VAR: + return "variable declaration" + } + case *ast.GoStmt: + return "go statement" + case *ast.Ident: + return "identifier" + case *ast.IfStmt: + return "if statement" + case *ast.ImportSpec: + return "import specification" + case *ast.IncDecStmt: + if n.Tok == token.INC { + return "increment statement" + } + return "decrement statement" + case *ast.IndexExpr: + return "index expression" + case *ast.IndexListExpr: + return "index list expression" + case *ast.InterfaceType: + return "interface type" + case *ast.KeyValueExpr: + return "key/value association" + case *ast.LabeledStmt: + return "statement label" + case *ast.MapType: + return "map type" + case *ast.Package: + return "package" + case *ast.ParenExpr: + return "parenthesized " + NodeDescription(n.X) + case *ast.RangeStmt: + return "range loop" + case *ast.ReturnStmt: + return "return statement" + case *ast.SelectStmt: + return "select statement" + case *ast.SelectorExpr: + return "selector" + case *ast.SendStmt: + return "channel send" + case *ast.SliceExpr: + return "slice expression" + case *ast.StarExpr: + return "*-operation" // load/store expr or pointer type + case *ast.StructType: + return "struct type" + case *ast.SwitchStmt: + return "switch statement" + case *ast.TypeAssertExpr: + return "type assertion" + case *ast.TypeSpec: + return "type specification" + case *ast.TypeSwitchStmt: + return "type switch" + case *ast.UnaryExpr: + return fmt.Sprintf("unary %s operation", n.Op) + case *ast.ValueSpec: + return "value specification" + + } + panic(fmt.Sprintf("unexpected node type: %T", n)) +} + +func is[T any](x any) bool { + _, ok := x.(T) + return ok +} diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/imports.go b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/imports.go new file mode 100644 index 00000000000000..a6b5ed0a8933eb --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/imports.go @@ -0,0 +1,490 @@ +// Copyright 2013 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Package astutil contains common utilities for working with the Go AST. +package astutil // import "golang.org/x/tools/go/ast/astutil" + +import ( + "fmt" + "go/ast" + "go/token" + "strconv" + "strings" +) + +// AddImport adds the import path to the file f, if absent. +func AddImport(fset *token.FileSet, f *ast.File, path string) (added bool) { + return AddNamedImport(fset, f, "", path) +} + +// AddNamedImport adds the import with the given name and path to the file f, if absent. +// If name is not empty, it is used to rename the import. +// +// For example, calling +// +// AddNamedImport(fset, f, "pathpkg", "path") +// +// adds +// +// import pathpkg "path" +func AddNamedImport(fset *token.FileSet, f *ast.File, name, path string) (added bool) { + if imports(f, name, path) { + return false + } + + newImport := &ast.ImportSpec{ + Path: &ast.BasicLit{ + Kind: token.STRING, + Value: strconv.Quote(path), + }, + } + if name != "" { + newImport.Name = &ast.Ident{Name: name} + } + + // Find an import decl to add to. + // The goal is to find an existing import + // whose import path has the longest shared + // prefix with path. + var ( + bestMatch = -1 // length of longest shared prefix + lastImport = -1 // index in f.Decls of the file's final import decl + impDecl *ast.GenDecl // import decl containing the best match + impIndex = -1 // spec index in impDecl containing the best match + + isThirdPartyPath = isThirdParty(path) + ) + for i, decl := range f.Decls { + gen, ok := decl.(*ast.GenDecl) + if ok && gen.Tok == token.IMPORT { + lastImport = i + // Do not add to import "C", to avoid disrupting the + // association with its doc comment, breaking cgo. + if declImports(gen, "C") { + continue + } + + // Match an empty import decl if that's all that is available. + if len(gen.Specs) == 0 && bestMatch == -1 { + impDecl = gen + } + + // Compute longest shared prefix with imports in this group and find best + // matched import spec. + // 1. Always prefer import spec with longest shared prefix. + // 2. While match length is 0, + // - for stdlib package: prefer first import spec. + // - for third party package: prefer first third party import spec. + // We cannot use last import spec as best match for third party package + // because grouped imports are usually placed last by goimports -local + // flag. + // See issue #19190. + seenAnyThirdParty := false + for j, spec := range gen.Specs { + impspec := spec.(*ast.ImportSpec) + p := importPath(impspec) + n := matchLen(p, path) + if n > bestMatch || (bestMatch == 0 && !seenAnyThirdParty && isThirdPartyPath) { + bestMatch = n + impDecl = gen + impIndex = j + } + seenAnyThirdParty = seenAnyThirdParty || isThirdParty(p) + } + } + } + + // If no import decl found, add one after the last import. + if impDecl == nil { + impDecl = &ast.GenDecl{ + Tok: token.IMPORT, + } + if lastImport >= 0 { + impDecl.TokPos = f.Decls[lastImport].End() + } else { + // There are no existing imports. + // Our new import, preceded by a blank line, goes after the package declaration + // and after the comment, if any, that starts on the same line as the + // package declaration. + impDecl.TokPos = f.Package + + file := fset.File(f.Package) + pkgLine := file.Line(f.Package) + for _, c := range f.Comments { + if file.Line(c.Pos()) > pkgLine { + break + } + // +2 for a blank line + impDecl.TokPos = c.End() + 2 + } + } + f.Decls = append(f.Decls, nil) + copy(f.Decls[lastImport+2:], f.Decls[lastImport+1:]) + f.Decls[lastImport+1] = impDecl + } + + // Insert new import at insertAt. + insertAt := 0 + if impIndex >= 0 { + // insert after the found import + insertAt = impIndex + 1 + } + impDecl.Specs = append(impDecl.Specs, nil) + copy(impDecl.Specs[insertAt+1:], impDecl.Specs[insertAt:]) + impDecl.Specs[insertAt] = newImport + pos := impDecl.Pos() + if insertAt > 0 { + // If there is a comment after an existing import, preserve the comment + // position by adding the new import after the comment. + if spec, ok := impDecl.Specs[insertAt-1].(*ast.ImportSpec); ok && spec.Comment != nil { + pos = spec.Comment.End() + } else { + // Assign same position as the previous import, + // so that the sorter sees it as being in the same block. + pos = impDecl.Specs[insertAt-1].Pos() + } + } + if newImport.Name != nil { + newImport.Name.NamePos = pos + } + newImport.Path.ValuePos = pos + newImport.EndPos = pos + + // Clean up parens. impDecl contains at least one spec. + if len(impDecl.Specs) == 1 { + // Remove unneeded parens. + impDecl.Lparen = token.NoPos + } else if !impDecl.Lparen.IsValid() { + // impDecl needs parens added. + impDecl.Lparen = impDecl.Specs[0].Pos() + } + + f.Imports = append(f.Imports, newImport) + + if len(f.Decls) <= 1 { + return true + } + + // Merge all the import declarations into the first one. + var first *ast.GenDecl + for i := 0; i < len(f.Decls); i++ { + decl := f.Decls[i] + gen, ok := decl.(*ast.GenDecl) + if !ok || gen.Tok != token.IMPORT || declImports(gen, "C") { + continue + } + if first == nil { + first = gen + continue // Don't touch the first one. + } + // We now know there is more than one package in this import + // declaration. Ensure that it ends up parenthesized. + first.Lparen = first.Pos() + // Move the imports of the other import declaration to the first one. + for _, spec := range gen.Specs { + spec.(*ast.ImportSpec).Path.ValuePos = first.Pos() + first.Specs = append(first.Specs, spec) + } + f.Decls = append(f.Decls[:i], f.Decls[i+1:]...) + i-- + } + + return true +} + +func isThirdParty(importPath string) bool { + // Third party package import path usually contains "." (".com", ".org", ...) + // This logic is taken from golang.org/x/tools/imports package. + return strings.Contains(importPath, ".") +} + +// DeleteImport deletes the import path from the file f, if present. +// If there are duplicate import declarations, all matching ones are deleted. +func DeleteImport(fset *token.FileSet, f *ast.File, path string) (deleted bool) { + return DeleteNamedImport(fset, f, "", path) +} + +// DeleteNamedImport deletes the import with the given name and path from the file f, if present. +// If there are duplicate import declarations, all matching ones are deleted. +func DeleteNamedImport(fset *token.FileSet, f *ast.File, name, path string) (deleted bool) { + var delspecs []*ast.ImportSpec + var delcomments []*ast.CommentGroup + + // Find the import nodes that import path, if any. + for i := 0; i < len(f.Decls); i++ { + decl := f.Decls[i] + gen, ok := decl.(*ast.GenDecl) + if !ok || gen.Tok != token.IMPORT { + continue + } + for j := 0; j < len(gen.Specs); j++ { + spec := gen.Specs[j] + impspec := spec.(*ast.ImportSpec) + if importName(impspec) != name || importPath(impspec) != path { + continue + } + + // We found an import spec that imports path. + // Delete it. + delspecs = append(delspecs, impspec) + deleted = true + copy(gen.Specs[j:], gen.Specs[j+1:]) + gen.Specs = gen.Specs[:len(gen.Specs)-1] + + // If this was the last import spec in this decl, + // delete the decl, too. + if len(gen.Specs) == 0 { + copy(f.Decls[i:], f.Decls[i+1:]) + f.Decls = f.Decls[:len(f.Decls)-1] + i-- + break + } else if len(gen.Specs) == 1 { + if impspec.Doc != nil { + delcomments = append(delcomments, impspec.Doc) + } + if impspec.Comment != nil { + delcomments = append(delcomments, impspec.Comment) + } + for _, cg := range f.Comments { + // Found comment on the same line as the import spec. + if cg.End() < impspec.Pos() && fset.Position(cg.End()).Line == fset.Position(impspec.Pos()).Line { + delcomments = append(delcomments, cg) + break + } + } + + spec := gen.Specs[0].(*ast.ImportSpec) + + // Move the documentation right after the import decl. + if spec.Doc != nil { + for fset.Position(gen.TokPos).Line+1 < fset.Position(spec.Doc.Pos()).Line { + fset.File(gen.TokPos).MergeLine(fset.Position(gen.TokPos).Line) + } + } + for _, cg := range f.Comments { + if cg.End() < spec.Pos() && fset.Position(cg.End()).Line == fset.Position(spec.Pos()).Line { + for fset.Position(gen.TokPos).Line+1 < fset.Position(spec.Pos()).Line { + fset.File(gen.TokPos).MergeLine(fset.Position(gen.TokPos).Line) + } + break + } + } + } + if j > 0 { + lastImpspec := gen.Specs[j-1].(*ast.ImportSpec) + lastLine := fset.PositionFor(lastImpspec.Path.ValuePos, false).Line + line := fset.PositionFor(impspec.Path.ValuePos, false).Line + + // We deleted an entry but now there may be + // a blank line-sized hole where the import was. + if line-lastLine > 1 || !gen.Rparen.IsValid() { + // There was a blank line immediately preceding the deleted import, + // so there's no need to close the hole. The right parenthesis is + // invalid after AddImport to an import statement without parenthesis. + // Do nothing. + } else if line != fset.File(gen.Rparen).LineCount() { + // There was no blank line. Close the hole. + fset.File(gen.Rparen).MergeLine(line) + } + } + j-- + } + } + + // Delete imports from f.Imports. + for i := 0; i < len(f.Imports); i++ { + imp := f.Imports[i] + for j, del := range delspecs { + if imp == del { + copy(f.Imports[i:], f.Imports[i+1:]) + f.Imports = f.Imports[:len(f.Imports)-1] + copy(delspecs[j:], delspecs[j+1:]) + delspecs = delspecs[:len(delspecs)-1] + i-- + break + } + } + } + + // Delete comments from f.Comments. + for i := 0; i < len(f.Comments); i++ { + cg := f.Comments[i] + for j, del := range delcomments { + if cg == del { + copy(f.Comments[i:], f.Comments[i+1:]) + f.Comments = f.Comments[:len(f.Comments)-1] + copy(delcomments[j:], delcomments[j+1:]) + delcomments = delcomments[:len(delcomments)-1] + i-- + break + } + } + } + + if len(delspecs) > 0 { + panic(fmt.Sprintf("deleted specs from Decls but not Imports: %v", delspecs)) + } + + return +} + +// RewriteImport rewrites any import of path oldPath to path newPath. +func RewriteImport(fset *token.FileSet, f *ast.File, oldPath, newPath string) (rewrote bool) { + for _, imp := range f.Imports { + if importPath(imp) == oldPath { + rewrote = true + // record old End, because the default is to compute + // it using the length of imp.Path.Value. + imp.EndPos = imp.End() + imp.Path.Value = strconv.Quote(newPath) + } + } + return +} + +// UsesImport reports whether a given import is used. +// The provided File must have been parsed with syntactic object resolution +// (not using go/parser.SkipObjectResolution). +func UsesImport(f *ast.File, path string) (used bool) { + if f.Scope == nil { + panic("file f was not parsed with syntactic object resolution") + } + spec := importSpec(f, path) + if spec == nil { + return + } + + name := spec.Name.String() + switch name { + case "": + // If the package name is not explicitly specified, + // make an educated guess. This is not guaranteed to be correct. + lastSlash := strings.LastIndex(path, "/") + if lastSlash == -1 { + name = path + } else { + name = path[lastSlash+1:] + } + case "_", ".": + // Not sure if this import is used - err on the side of caution. + return true + } + + ast.Walk(visitFn(func(n ast.Node) { + sel, ok := n.(*ast.SelectorExpr) + if ok && isTopName(sel.X, name) { + used = true + } + }), f) + + return +} + +type visitFn func(node ast.Node) + +func (fn visitFn) Visit(node ast.Node) ast.Visitor { + fn(node) + return fn +} + +// imports reports whether f has an import with the specified name and path. +func imports(f *ast.File, name, path string) bool { + for _, s := range f.Imports { + if importName(s) == name && importPath(s) == path { + return true + } + } + return false +} + +// importSpec returns the import spec if f imports path, +// or nil otherwise. +func importSpec(f *ast.File, path string) *ast.ImportSpec { + for _, s := range f.Imports { + if importPath(s) == path { + return s + } + } + return nil +} + +// importName returns the name of s, +// or "" if the import is not named. +func importName(s *ast.ImportSpec) string { + if s.Name == nil { + return "" + } + return s.Name.Name +} + +// importPath returns the unquoted import path of s, +// or "" if the path is not properly quoted. +func importPath(s *ast.ImportSpec) string { + t, err := strconv.Unquote(s.Path.Value) + if err != nil { + return "" + } + return t +} + +// declImports reports whether gen contains an import of path. +func declImports(gen *ast.GenDecl, path string) bool { + if gen.Tok != token.IMPORT { + return false + } + for _, spec := range gen.Specs { + impspec := spec.(*ast.ImportSpec) + if importPath(impspec) == path { + return true + } + } + return false +} + +// matchLen returns the length of the longest path segment prefix shared by x and y. +func matchLen(x, y string) int { + n := 0 + for i := 0; i < len(x) && i < len(y) && x[i] == y[i]; i++ { + if x[i] == '/' { + n++ + } + } + return n +} + +// isTopName returns true if n is a top-level unresolved identifier with the given name. +func isTopName(n ast.Expr, name string) bool { + id, ok := n.(*ast.Ident) + return ok && id.Name == name && id.Obj == nil +} + +// Imports returns the file imports grouped by paragraph. +func Imports(fset *token.FileSet, f *ast.File) [][]*ast.ImportSpec { + var groups [][]*ast.ImportSpec + + for _, decl := range f.Decls { + genDecl, ok := decl.(*ast.GenDecl) + if !ok || genDecl.Tok != token.IMPORT { + break + } + + group := []*ast.ImportSpec{} + + var lastLine int + for _, spec := range genDecl.Specs { + importSpec := spec.(*ast.ImportSpec) + pos := importSpec.Path.ValuePos + line := fset.Position(pos).Line + if lastLine > 0 && pos > 0 && line-lastLine > 1 { + groups = append(groups, group) + group = []*ast.ImportSpec{} + } + group = append(group, importSpec) + lastLine = line + } + groups = append(groups, group) + } + + return groups +} diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/rewrite.go b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/rewrite.go new file mode 100644 index 00000000000000..58934f76633d50 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/rewrite.go @@ -0,0 +1,486 @@ +// Copyright 2017 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package astutil + +import ( + "fmt" + "go/ast" + "reflect" + "sort" +) + +// An ApplyFunc is invoked by Apply for each node n, even if n is nil, +// before and/or after the node's children, using a Cursor describing +// the current node and providing operations on it. +// +// The return value of ApplyFunc controls the syntax tree traversal. +// See Apply for details. +type ApplyFunc func(*Cursor) bool + +// Apply traverses a syntax tree recursively, starting with root, +// and calling pre and post for each node as described below. +// Apply returns the syntax tree, possibly modified. +// +// If pre is not nil, it is called for each node before the node's +// children are traversed (pre-order). If pre returns false, no +// children are traversed, and post is not called for that node. +// +// If post is not nil, and a prior call of pre didn't return false, +// post is called for each node after its children are traversed +// (post-order). If post returns false, traversal is terminated and +// Apply returns immediately. +// +// Only fields that refer to AST nodes are considered children; +// i.e., token.Pos, Scopes, Objects, and fields of basic types +// (strings, etc.) are ignored. +// +// Children are traversed in the order in which they appear in the +// respective node's struct definition. A package's files are +// traversed in the filenames' alphabetical order. +func Apply(root ast.Node, pre, post ApplyFunc) (result ast.Node) { + parent := &struct{ ast.Node }{root} + defer func() { + if r := recover(); r != nil && r != abort { + panic(r) + } + result = parent.Node + }() + a := &application{pre: pre, post: post} + a.apply(parent, "Node", nil, root) + return +} + +var abort = new(int) // singleton, to signal termination of Apply + +// A Cursor describes a node encountered during Apply. +// Information about the node and its parent is available +// from the Node, Parent, Name, and Index methods. +// +// If p is a variable of type and value of the current parent node +// c.Parent(), and f is the field identifier with name c.Name(), +// the following invariants hold: +// +// p.f == c.Node() if c.Index() < 0 +// p.f[c.Index()] == c.Node() if c.Index() >= 0 +// +// The methods Replace, Delete, InsertBefore, and InsertAfter +// can be used to change the AST without disrupting Apply. +type Cursor struct { + parent ast.Node + name string + iter *iterator // valid if non-nil + node ast.Node +} + +// Node returns the current Node. +func (c *Cursor) Node() ast.Node { return c.node } + +// Parent returns the parent of the current Node. +func (c *Cursor) Parent() ast.Node { return c.parent } + +// Name returns the name of the parent Node field that contains the current Node. +// If the parent is a *ast.Package and the current Node is a *ast.File, Name returns +// the filename for the current Node. +func (c *Cursor) Name() string { return c.name } + +// Index reports the index >= 0 of the current Node in the slice of Nodes that +// contains it, or a value < 0 if the current Node is not part of a slice. +// The index of the current node changes if InsertBefore is called while +// processing the current node. +func (c *Cursor) Index() int { + if c.iter != nil { + return c.iter.index + } + return -1 +} + +// field returns the current node's parent field value. +func (c *Cursor) field() reflect.Value { + return reflect.Indirect(reflect.ValueOf(c.parent)).FieldByName(c.name) +} + +// Replace replaces the current Node with n. +// The replacement node is not walked by Apply. +func (c *Cursor) Replace(n ast.Node) { + if _, ok := c.node.(*ast.File); ok { + file, ok := n.(*ast.File) + if !ok { + panic("attempt to replace *ast.File with non-*ast.File") + } + c.parent.(*ast.Package).Files[c.name] = file + return + } + + v := c.field() + if i := c.Index(); i >= 0 { + v = v.Index(i) + } + v.Set(reflect.ValueOf(n)) +} + +// Delete deletes the current Node from its containing slice. +// If the current Node is not part of a slice, Delete panics. +// As a special case, if the current node is a package file, +// Delete removes it from the package's Files map. +func (c *Cursor) Delete() { + if _, ok := c.node.(*ast.File); ok { + delete(c.parent.(*ast.Package).Files, c.name) + return + } + + i := c.Index() + if i < 0 { + panic("Delete node not contained in slice") + } + v := c.field() + l := v.Len() + reflect.Copy(v.Slice(i, l), v.Slice(i+1, l)) + v.Index(l - 1).Set(reflect.Zero(v.Type().Elem())) + v.SetLen(l - 1) + c.iter.step-- +} + +// InsertAfter inserts n after the current Node in its containing slice. +// If the current Node is not part of a slice, InsertAfter panics. +// Apply does not walk n. +func (c *Cursor) InsertAfter(n ast.Node) { + i := c.Index() + if i < 0 { + panic("InsertAfter node not contained in slice") + } + v := c.field() + v.Set(reflect.Append(v, reflect.Zero(v.Type().Elem()))) + l := v.Len() + reflect.Copy(v.Slice(i+2, l), v.Slice(i+1, l)) + v.Index(i + 1).Set(reflect.ValueOf(n)) + c.iter.step++ +} + +// InsertBefore inserts n before the current Node in its containing slice. +// If the current Node is not part of a slice, InsertBefore panics. +// Apply will not walk n. +func (c *Cursor) InsertBefore(n ast.Node) { + i := c.Index() + if i < 0 { + panic("InsertBefore node not contained in slice") + } + v := c.field() + v.Set(reflect.Append(v, reflect.Zero(v.Type().Elem()))) + l := v.Len() + reflect.Copy(v.Slice(i+1, l), v.Slice(i, l)) + v.Index(i).Set(reflect.ValueOf(n)) + c.iter.index++ +} + +// application carries all the shared data so we can pass it around cheaply. +type application struct { + pre, post ApplyFunc + cursor Cursor + iter iterator +} + +func (a *application) apply(parent ast.Node, name string, iter *iterator, n ast.Node) { + // convert typed nil into untyped nil + if v := reflect.ValueOf(n); v.Kind() == reflect.Ptr && v.IsNil() { + n = nil + } + + // avoid heap-allocating a new cursor for each apply call; reuse a.cursor instead + saved := a.cursor + a.cursor.parent = parent + a.cursor.name = name + a.cursor.iter = iter + a.cursor.node = n + + if a.pre != nil && !a.pre(&a.cursor) { + a.cursor = saved + return + } + + // walk children + // (the order of the cases matches the order of the corresponding node types in go/ast) + switch n := n.(type) { + case nil: + // nothing to do + + // Comments and fields + case *ast.Comment: + // nothing to do + + case *ast.CommentGroup: + if n != nil { + a.applyList(n, "List") + } + + case *ast.Field: + a.apply(n, "Doc", nil, n.Doc) + a.applyList(n, "Names") + a.apply(n, "Type", nil, n.Type) + a.apply(n, "Tag", nil, n.Tag) + a.apply(n, "Comment", nil, n.Comment) + + case *ast.FieldList: + a.applyList(n, "List") + + // Expressions + case *ast.BadExpr, *ast.Ident, *ast.BasicLit: + // nothing to do + + case *ast.Ellipsis: + a.apply(n, "Elt", nil, n.Elt) + + case *ast.FuncLit: + a.apply(n, "Type", nil, n.Type) + a.apply(n, "Body", nil, n.Body) + + case *ast.CompositeLit: + a.apply(n, "Type", nil, n.Type) + a.applyList(n, "Elts") + + case *ast.ParenExpr: + a.apply(n, "X", nil, n.X) + + case *ast.SelectorExpr: + a.apply(n, "X", nil, n.X) + a.apply(n, "Sel", nil, n.Sel) + + case *ast.IndexExpr: + a.apply(n, "X", nil, n.X) + a.apply(n, "Index", nil, n.Index) + + case *ast.IndexListExpr: + a.apply(n, "X", nil, n.X) + a.applyList(n, "Indices") + + case *ast.SliceExpr: + a.apply(n, "X", nil, n.X) + a.apply(n, "Low", nil, n.Low) + a.apply(n, "High", nil, n.High) + a.apply(n, "Max", nil, n.Max) + + case *ast.TypeAssertExpr: + a.apply(n, "X", nil, n.X) + a.apply(n, "Type", nil, n.Type) + + case *ast.CallExpr: + a.apply(n, "Fun", nil, n.Fun) + a.applyList(n, "Args") + + case *ast.StarExpr: + a.apply(n, "X", nil, n.X) + + case *ast.UnaryExpr: + a.apply(n, "X", nil, n.X) + + case *ast.BinaryExpr: + a.apply(n, "X", nil, n.X) + a.apply(n, "Y", nil, n.Y) + + case *ast.KeyValueExpr: + a.apply(n, "Key", nil, n.Key) + a.apply(n, "Value", nil, n.Value) + + // Types + case *ast.ArrayType: + a.apply(n, "Len", nil, n.Len) + a.apply(n, "Elt", nil, n.Elt) + + case *ast.StructType: + a.apply(n, "Fields", nil, n.Fields) + + case *ast.FuncType: + if tparams := n.TypeParams; tparams != nil { + a.apply(n, "TypeParams", nil, tparams) + } + a.apply(n, "Params", nil, n.Params) + a.apply(n, "Results", nil, n.Results) + + case *ast.InterfaceType: + a.apply(n, "Methods", nil, n.Methods) + + case *ast.MapType: + a.apply(n, "Key", nil, n.Key) + a.apply(n, "Value", nil, n.Value) + + case *ast.ChanType: + a.apply(n, "Value", nil, n.Value) + + // Statements + case *ast.BadStmt: + // nothing to do + + case *ast.DeclStmt: + a.apply(n, "Decl", nil, n.Decl) + + case *ast.EmptyStmt: + // nothing to do + + case *ast.LabeledStmt: + a.apply(n, "Label", nil, n.Label) + a.apply(n, "Stmt", nil, n.Stmt) + + case *ast.ExprStmt: + a.apply(n, "X", nil, n.X) + + case *ast.SendStmt: + a.apply(n, "Chan", nil, n.Chan) + a.apply(n, "Value", nil, n.Value) + + case *ast.IncDecStmt: + a.apply(n, "X", nil, n.X) + + case *ast.AssignStmt: + a.applyList(n, "Lhs") + a.applyList(n, "Rhs") + + case *ast.GoStmt: + a.apply(n, "Call", nil, n.Call) + + case *ast.DeferStmt: + a.apply(n, "Call", nil, n.Call) + + case *ast.ReturnStmt: + a.applyList(n, "Results") + + case *ast.BranchStmt: + a.apply(n, "Label", nil, n.Label) + + case *ast.BlockStmt: + a.applyList(n, "List") + + case *ast.IfStmt: + a.apply(n, "Init", nil, n.Init) + a.apply(n, "Cond", nil, n.Cond) + a.apply(n, "Body", nil, n.Body) + a.apply(n, "Else", nil, n.Else) + + case *ast.CaseClause: + a.applyList(n, "List") + a.applyList(n, "Body") + + case *ast.SwitchStmt: + a.apply(n, "Init", nil, n.Init) + a.apply(n, "Tag", nil, n.Tag) + a.apply(n, "Body", nil, n.Body) + + case *ast.TypeSwitchStmt: + a.apply(n, "Init", nil, n.Init) + a.apply(n, "Assign", nil, n.Assign) + a.apply(n, "Body", nil, n.Body) + + case *ast.CommClause: + a.apply(n, "Comm", nil, n.Comm) + a.applyList(n, "Body") + + case *ast.SelectStmt: + a.apply(n, "Body", nil, n.Body) + + case *ast.ForStmt: + a.apply(n, "Init", nil, n.Init) + a.apply(n, "Cond", nil, n.Cond) + a.apply(n, "Post", nil, n.Post) + a.apply(n, "Body", nil, n.Body) + + case *ast.RangeStmt: + a.apply(n, "Key", nil, n.Key) + a.apply(n, "Value", nil, n.Value) + a.apply(n, "X", nil, n.X) + a.apply(n, "Body", nil, n.Body) + + // Declarations + case *ast.ImportSpec: + a.apply(n, "Doc", nil, n.Doc) + a.apply(n, "Name", nil, n.Name) + a.apply(n, "Path", nil, n.Path) + a.apply(n, "Comment", nil, n.Comment) + + case *ast.ValueSpec: + a.apply(n, "Doc", nil, n.Doc) + a.applyList(n, "Names") + a.apply(n, "Type", nil, n.Type) + a.applyList(n, "Values") + a.apply(n, "Comment", nil, n.Comment) + + case *ast.TypeSpec: + a.apply(n, "Doc", nil, n.Doc) + a.apply(n, "Name", nil, n.Name) + if tparams := n.TypeParams; tparams != nil { + a.apply(n, "TypeParams", nil, tparams) + } + a.apply(n, "Type", nil, n.Type) + a.apply(n, "Comment", nil, n.Comment) + + case *ast.BadDecl: + // nothing to do + + case *ast.GenDecl: + a.apply(n, "Doc", nil, n.Doc) + a.applyList(n, "Specs") + + case *ast.FuncDecl: + a.apply(n, "Doc", nil, n.Doc) + a.apply(n, "Recv", nil, n.Recv) + a.apply(n, "Name", nil, n.Name) + a.apply(n, "Type", nil, n.Type) + a.apply(n, "Body", nil, n.Body) + + // Files and packages + case *ast.File: + a.apply(n, "Doc", nil, n.Doc) + a.apply(n, "Name", nil, n.Name) + a.applyList(n, "Decls") + // Don't walk n.Comments; they have either been walked already if + // they are Doc comments, or they can be easily walked explicitly. + + case *ast.Package: + // collect and sort names for reproducible behavior + var names []string + for name := range n.Files { + names = append(names, name) + } + sort.Strings(names) + for _, name := range names { + a.apply(n, name, nil, n.Files[name]) + } + + default: + panic(fmt.Sprintf("Apply: unexpected node type %T", n)) + } + + if a.post != nil && !a.post(&a.cursor) { + panic(abort) + } + + a.cursor = saved +} + +// An iterator controls iteration over a slice of nodes. +type iterator struct { + index, step int +} + +func (a *application) applyList(parent ast.Node, name string) { + // avoid heap-allocating a new iterator for each applyList call; reuse a.iter instead + saved := a.iter + a.iter.index = 0 + for { + // must reload parent.name each time, since cursor modifications might change it + v := reflect.Indirect(reflect.ValueOf(parent)).FieldByName(name) + if a.iter.index >= v.Len() { + break + } + + // element x may be nil in a bad AST - be cautious + var x ast.Node + if e := v.Index(a.iter.index); e.IsValid() { + x = e.Interface().(ast.Node) + } + + a.iter.step = 1 + a.apply(parent, name, &a.iter, x) + a.iter.index += a.iter.step + } + a.iter = saved +} diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/util.go b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/util.go new file mode 100644 index 00000000000000..ca71e3e1055387 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/golang.org/x/tools/go/ast/astutil/util.go @@ -0,0 +1,11 @@ +// Copyright 2015 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package astutil + +import "go/ast" + +// Unparen returns e with any enclosing parentheses stripped. +// Deprecated: use [ast.Unparen]. +func Unparen(e ast.Expr) ast.Expr { return ast.Unparen(e) } diff --git a/src/cmd/compile/internal/ssa/_gen/vendor/modules.txt b/src/cmd/compile/internal/ssa/_gen/vendor/modules.txt new file mode 100644 index 00000000000000..2efa97223356a2 --- /dev/null +++ b/src/cmd/compile/internal/ssa/_gen/vendor/modules.txt @@ -0,0 +1,3 @@ +# golang.org/x/tools v0.27.0 +## explicit; go 1.22.0 +golang.org/x/tools/go/ast/astutil diff --git a/src/cmd/compile/internal/ssa/config.go b/src/cmd/compile/internal/ssa/config.go index d4cd32a0d7b5b6..0299e808c6d365 100644 --- a/src/cmd/compile/internal/ssa/config.go +++ b/src/cmd/compile/internal/ssa/config.go @@ -89,6 +89,10 @@ type Types struct { Float32Ptr *types.Type Float64Ptr *types.Type BytePtrPtr *types.Type + Vec128 *types.Type + Vec256 *types.Type + Vec512 *types.Type + Mask *types.Type } // NewTypes creates and populates a Types. @@ -123,6 +127,10 @@ func (t *Types) SetTypPtrs() { t.Float32Ptr = types.NewPtr(types.Types[types.TFLOAT32]) t.Float64Ptr = types.NewPtr(types.Types[types.TFLOAT64]) t.BytePtrPtr = types.NewPtr(types.NewPtr(types.Types[types.TUINT8])) + t.Vec128 = types.TypeVec128 + t.Vec256 = types.TypeVec256 + t.Vec512 = types.TypeVec512 + t.Mask = types.TypeMask } type Logger interface { diff --git a/src/cmd/compile/internal/ssa/decompose.go b/src/cmd/compile/internal/ssa/decompose.go index cf9285741ed085..c3d9997793ef05 100644 --- a/src/cmd/compile/internal/ssa/decompose.go +++ b/src/cmd/compile/internal/ssa/decompose.go @@ -100,7 +100,7 @@ func decomposeBuiltIn(f *Func) { } case t.IsFloat(): // floats are never decomposed, even ones bigger than RegSize - case t.Size() > f.Config.RegSize: + case t.Size() > f.Config.RegSize && !t.IsSIMD(): f.Fatalf("undecomposed named type %s %v", name, t) } } @@ -135,7 +135,7 @@ func decomposeBuiltInPhi(v *Value) { decomposeInterfacePhi(v) case v.Type.IsFloat(): // floats are never decomposed, even ones bigger than RegSize - case v.Type.Size() > v.Block.Func.Config.RegSize: + case v.Type.Size() > v.Block.Func.Config.RegSize && !v.Type.IsSIMD(): v.Fatalf("%v undecomposed type %v", v, v.Type) } } @@ -248,7 +248,7 @@ func decomposeUser(f *Func) { for _, name := range f.Names { t := name.Type switch { - case t.IsStruct(): + case isStructNotSIMD(t): newNames = decomposeUserStructInto(f, name, newNames) case t.IsArray(): newNames = decomposeUserArrayInto(f, name, newNames) @@ -293,7 +293,7 @@ func decomposeUserArrayInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Loc if t.Elem().IsArray() { return decomposeUserArrayInto(f, elemName, slots) - } else if t.Elem().IsStruct() { + } else if isStructNotSIMD(t.Elem()) { return decomposeUserStructInto(f, elemName, slots) } @@ -313,7 +313,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo fnames = append(fnames, fs) // arrays and structs will be decomposed further, so // there's no need to record a name - if !fs.Type.IsArray() && !fs.Type.IsStruct() { + if !fs.Type.IsArray() && !isStructNotSIMD(fs.Type) { slots = maybeAppend(f, slots, fs) } } @@ -339,7 +339,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo // now that this f.NamedValues contains values for the struct // fields, recurse into nested structs for i := 0; i < n; i++ { - if name.Type.FieldType(i).IsStruct() { + if isStructNotSIMD(name.Type.FieldType(i)) { slots = decomposeUserStructInto(f, fnames[i], slots) delete(f.NamedValues, *fnames[i]) } else if name.Type.FieldType(i).IsArray() { @@ -351,7 +351,7 @@ func decomposeUserStructInto(f *Func, name *LocalSlot, slots []*LocalSlot) []*Lo } func decomposeUserPhi(v *Value) { switch { - case v.Type.IsStruct(): + case isStructNotSIMD(v.Type): decomposeStructPhi(v) case v.Type.IsArray(): decomposeArrayPhi(v) @@ -458,3 +458,7 @@ func deleteNamedVals(f *Func, toDelete []namedVal) { } f.Names = f.Names[:end] } + +func isStructNotSIMD(t *types.Type) bool { + return t.IsStruct() && !t.IsSIMD() +} diff --git a/src/cmd/compile/internal/ssa/expand_calls.go b/src/cmd/compile/internal/ssa/expand_calls.go index fb281f2f8452cb..9e46182a4cd9ae 100644 --- a/src/cmd/compile/internal/ssa/expand_calls.go +++ b/src/cmd/compile/internal/ssa/expand_calls.go @@ -399,6 +399,9 @@ func (x *expandState) decomposeAsNecessary(pos src.XPos, b *Block, a, m0 *Value, return mem case types.TSTRUCT: + if at.IsSIMD() { + break // XXX + } for i := 0; i < at.NumFields(); i++ { et := at.Field(i).Type // might need to read offsets from the fields e := b.NewValue1I(pos, OpStructSelect, et, int64(i), a) @@ -547,6 +550,9 @@ func (x *expandState) rewriteSelectOrArg(pos src.XPos, b *Block, container, a, m case types.TSTRUCT: // Assume ssagen/ssa.go (in buildssa) spills large aggregates so they won't appear here. + if at.IsSIMD() { + break // XXX + } for i := 0; i < at.NumFields(); i++ { et := at.Field(i).Type e := x.rewriteSelectOrArg(pos, b, container, nil, m0, et, rc.next(et)) @@ -713,6 +719,9 @@ func (x *expandState) rewriteWideSelectToStores(pos src.XPos, b *Block, containe case types.TSTRUCT: // Assume ssagen/ssa.go (in buildssa) spills large aggregates so they won't appear here. + if at.IsSIMD() { + break // XXX + } for i := 0; i < at.NumFields(); i++ { et := at.Field(i).Type m0 = x.rewriteWideSelectToStores(pos, b, container, m0, et, rc.next(et)) @@ -859,7 +868,7 @@ func (c *registerCursor) at(t *types.Type, i int) registerCursor { rc.nextSlice += Abi1RO(i * w) return rc } - if t.IsStruct() { + if isStructNotSIMD(t) { for j := 0; j < i; j++ { rc.next(t.FieldType(j)) } @@ -973,7 +982,7 @@ func (x *expandState) regOffset(t *types.Type, i int) Abi1RO { if t.IsArray() { return Abi1RO(i) * x.regWidth(t.Elem()) } - if t.IsStruct() { + if isStructNotSIMD(t) { k := Abi1RO(0) for j := 0; j < i; j++ { k += x.regWidth(t.FieldType(j)) diff --git a/src/cmd/compile/internal/ssa/generate_test.go b/src/cmd/compile/internal/ssa/generate_test.go new file mode 100644 index 00000000000000..d65288c399996f --- /dev/null +++ b/src/cmd/compile/internal/ssa/generate_test.go @@ -0,0 +1,135 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package ssa + +import ( + "bytes" + "fmt" + "internal/testenv" + "os" + "path/filepath" + "testing" +) + +const expectedHeader = "// Code generated from _gen/" // this is the common part + +// TestGeneratedFilesUpToDate regenerates all the rewrite and rewrite-related +// files defined in _gen into a temporary directory, +// checks that they match what appears in the source tree, +// verifies that they start with the prefix of a generated header, +// and checks that the only source files with that header were actually generated. +func TestGeneratedFilesUpToDate(t *testing.T) { + testenv.MustHaveGoRun(t) + wd, err := os.Getwd() + if err != nil { + t.Fatalf("Failed to get current working directory: %v", err) + } + genDir := filepath.Join(wd, "_gen") + if _, err := os.Stat(genDir); os.IsNotExist(err) { + t.Fatalf("_gen directory not found") + } + + tmpdir := t.TempDir() + + // Accumulate a list of all existing files that look generated. + // It's an error if this set does not match the set that are + // generated into tmpdir. + genFiles := make(map[string]bool) + genPrefix := []byte(expectedHeader) + ssaFiles, err := filepath.Glob(filepath.Join(wd, "*.go")) + if err != nil { + t.Fatalf("could not glob for .go files in ssa directory: %v", err) + } + for _, f := range ssaFiles { + contents, err := os.ReadFile(f) + if err != nil { + t.Fatalf("could not read source file from ssa directory: %v", err) + } + // verify that the generated file has the expected header + // (this should cause other failures later, but if this is + // the problem, diagnose it here to shorten the treasure hunt.) + if bytes.HasPrefix(contents, genPrefix) { + genFiles[filepath.Base(f)] = true + } + } + + goFiles, err := filepath.Glob(filepath.Join(genDir, "*.go")) + if err != nil { + t.Fatalf("could not glob for .go files in _gen: %v", err) + } + if len(goFiles) == 0 { + t.Fatal("no .go files found in _gen") + } + + // Construct the command line for "go run". + // Explicitly list the files, just to make it + // clear what is included (if the test is logging). + args := []string{"run", "-C", genDir} + for _, f := range goFiles { + args = append(args, filepath.Base(f)) + } + args = append(args, "-outdir", tmpdir) + + logArgs := fmt.Sprintf("%v", args) + logArgs = logArgs[1 : len(logArgs)-2] // strip '[' and ']' + t.Logf("%s %v", testenv.GoToolPath(t), logArgs) + output, err := testenv.Command(t, testenv.GoToolPath(t), args...).CombinedOutput() + + if err != nil { + t.Fatalf("go run in _gen failed: %v\n%s", err, output) + } + + // Compare generated files with existing files in the parent directory. + files, err := os.ReadDir(tmpdir) + if err != nil { + t.Fatalf("could not read tmpdir %s: %v", tmpdir, err) + } + + for _, file := range files { + if file.IsDir() { + continue + } + filename := file.Name() + + // filename must be in the generated set, + if !genFiles[filename] { + t.Errorf("%s does not start with the expected header '%s' (if the header was changed the test needs to be updated)", + filename, expectedHeader) + } + genFiles[filename] = false // remove from set + + generatedPath := filepath.Join(tmpdir, filename) + originalPath := filepath.Join(wd, filename) + + generatedData, err := os.ReadFile(generatedPath) + if err != nil { + t.Errorf("could not read generated file %s: %v", generatedPath, err) + continue + } + + // there should be a corresponding file in the ssa directory, + originalData, err := os.ReadFile(originalPath) + if err != nil { + if os.IsNotExist(err) { + t.Errorf("generated file %s was created, but does not exist in the ssa directory. It may need to be added to the repository.", filename) + } else { + t.Errorf("could not read original file %s: %v", originalPath, err) + } + continue + } + + // and the contents of that file should match. + if !bytes.Equal(originalData, generatedData) { + t.Errorf("%s is out of date. Please run 'go generate'.", filename) + } + } + + // the generated set should be empty now. + for file, notGenerated := range genFiles { + if notGenerated { + t.Errorf("%s has the header of a generated file but was not generated", file) + } + } +} diff --git a/src/cmd/compile/internal/ssa/opGen.go b/src/cmd/compile/internal/ssa/opGen.go index 5d13f81841482d..d2e86702d838f0 100644 --- a/src/cmd/compile/internal/ssa/opGen.go +++ b/src/cmd/compile/internal/ssa/opGen.go @@ -1162,6 +1162,925 @@ const ( OpAMD64PSIGNB OpAMD64PCMPEQB OpAMD64PMOVMSKB + OpAMD64VPADDD4 + OpAMD64VMOVDQUload128 + OpAMD64VMOVDQUstore128 + OpAMD64VMOVDQUload256 + OpAMD64VMOVDQUstore256 + OpAMD64VMOVDQUload512 + OpAMD64VMOVDQUstore512 + OpAMD64VPMOVMToVec8x16 + OpAMD64VPMOVMToVec8x32 + OpAMD64VPMOVMToVec8x64 + OpAMD64VPMOVMToVec16x8 + OpAMD64VPMOVMToVec16x16 + OpAMD64VPMOVMToVec16x32 + OpAMD64VPMOVMToVec32x4 + OpAMD64VPMOVMToVec32x8 + OpAMD64VPMOVMToVec32x16 + OpAMD64VPMOVMToVec64x2 + OpAMD64VPMOVMToVec64x4 + OpAMD64VPMOVMToVec64x8 + OpAMD64VPMOVVec8x16ToM + OpAMD64VPMOVVec8x32ToM + OpAMD64VPMOVVec8x64ToM + OpAMD64VPMOVVec16x8ToM + OpAMD64VPMOVVec16x16ToM + OpAMD64VPMOVVec16x32ToM + OpAMD64VPMOVVec32x4ToM + OpAMD64VPMOVVec32x8ToM + OpAMD64VPMOVVec32x16ToM + OpAMD64VPMOVVec64x2ToM + OpAMD64VPMOVVec64x4ToM + OpAMD64VPMOVVec64x8ToM + OpAMD64Zero128 + OpAMD64Zero256 + OpAMD64Zero512 + OpAMD64VADDPS512 + OpAMD64VANDPS512 + OpAMD64VANDNPS512 + OpAMD64VRCP14PS512 + OpAMD64VRSQRT14PS512 + OpAMD64VDIVPS512 + OpAMD64VFMADD132PS512 + OpAMD64VFMADD213PS512 + OpAMD64VFMADD231PS512 + OpAMD64VFMADDSUB132PS512 + OpAMD64VFMADDSUB213PS512 + OpAMD64VFMADDSUB231PS512 + OpAMD64VFMSUB132PS512 + OpAMD64VFMSUB213PS512 + OpAMD64VFMSUB231PS512 + OpAMD64VFMSUBADD132PS512 + OpAMD64VFMSUBADD213PS512 + OpAMD64VFMSUBADD231PS512 + OpAMD64VFNMADD132PS512 + OpAMD64VFNMADD213PS512 + OpAMD64VFNMADD231PS512 + OpAMD64VFNMSUB132PS512 + OpAMD64VFNMSUB213PS512 + OpAMD64VFNMSUB231PS512 + OpAMD64VADDPSMasked512 + OpAMD64VANDPSMasked512 + OpAMD64VANDNPSMasked512 + OpAMD64VRCP14PSMasked512 + OpAMD64VRSQRT14PSMasked512 + OpAMD64VDIVPSMasked512 + OpAMD64VFMADD132PSMasked512 + OpAMD64VFMADD213PSMasked512 + OpAMD64VFMADD231PSMasked512 + OpAMD64VFMADDSUB132PSMasked512 + OpAMD64VFMADDSUB213PSMasked512 + OpAMD64VFMADDSUB231PSMasked512 + OpAMD64VFMSUB132PSMasked512 + OpAMD64VFMSUB213PSMasked512 + OpAMD64VFMSUB231PSMasked512 + OpAMD64VFMSUBADD132PSMasked512 + OpAMD64VFMSUBADD213PSMasked512 + OpAMD64VFMSUBADD231PSMasked512 + OpAMD64VFNMADD132PSMasked512 + OpAMD64VFNMADD213PSMasked512 + OpAMD64VFNMADD231PSMasked512 + OpAMD64VFNMSUB132PSMasked512 + OpAMD64VFNMSUB213PSMasked512 + OpAMD64VFNMSUB231PSMasked512 + OpAMD64VMAXPSMasked512 + OpAMD64VMINPSMasked512 + OpAMD64VMULPSMasked512 + OpAMD64VSCALEFPSMasked512 + OpAMD64VORPSMasked512 + OpAMD64VSQRTPSMasked512 + OpAMD64VXORPSMasked512 + OpAMD64VMAXPS512 + OpAMD64VMINPS512 + OpAMD64VMULPS512 + OpAMD64VSCALEFPS512 + OpAMD64VORPS512 + OpAMD64VSQRTPS512 + OpAMD64VXORPS512 + OpAMD64VADDPS128 + OpAMD64VADDSUBPS128 + OpAMD64VANDPS128 + OpAMD64VANDNPS128 + OpAMD64VRCP14PS128 + OpAMD64VRSQRTPS128 + OpAMD64VDIVPS128 + OpAMD64VFMADD132PS128 + OpAMD64VFMADD213PS128 + OpAMD64VFMADD231PS128 + OpAMD64VFMADDSUB132PS128 + OpAMD64VFMADDSUB213PS128 + OpAMD64VFMADDSUB231PS128 + OpAMD64VFMSUB132PS128 + OpAMD64VFMSUB213PS128 + OpAMD64VFMSUB231PS128 + OpAMD64VFMSUBADD132PS128 + OpAMD64VFMSUBADD213PS128 + OpAMD64VFMSUBADD231PS128 + OpAMD64VFNMADD132PS128 + OpAMD64VFNMADD213PS128 + OpAMD64VFNMADD231PS128 + OpAMD64VFNMSUB132PS128 + OpAMD64VFNMSUB213PS128 + OpAMD64VFNMSUB231PS128 + OpAMD64VADDPSMasked128 + OpAMD64VANDPSMasked128 + OpAMD64VANDNPSMasked128 + OpAMD64VRCP14PSMasked128 + OpAMD64VRSQRT14PSMasked128 + OpAMD64VDIVPSMasked128 + OpAMD64VFMADD132PSMasked128 + OpAMD64VFMADD213PSMasked128 + OpAMD64VFMADD231PSMasked128 + OpAMD64VFMADDSUB132PSMasked128 + OpAMD64VFMADDSUB213PSMasked128 + OpAMD64VFMADDSUB231PSMasked128 + OpAMD64VFMSUB132PSMasked128 + OpAMD64VFMSUB213PSMasked128 + OpAMD64VFMSUB231PSMasked128 + OpAMD64VFMSUBADD132PSMasked128 + OpAMD64VFMSUBADD213PSMasked128 + OpAMD64VFMSUBADD231PSMasked128 + OpAMD64VFNMADD132PSMasked128 + OpAMD64VFNMADD213PSMasked128 + OpAMD64VFNMADD231PSMasked128 + OpAMD64VFNMSUB132PSMasked128 + OpAMD64VFNMSUB213PSMasked128 + OpAMD64VFNMSUB231PSMasked128 + OpAMD64VMAXPSMasked128 + OpAMD64VMINPSMasked128 + OpAMD64VMULPSMasked128 + OpAMD64VSCALEFPSMasked128 + OpAMD64VORPSMasked128 + OpAMD64VSQRTPSMasked128 + OpAMD64VXORPSMasked128 + OpAMD64VMAXPS128 + OpAMD64VMINPS128 + OpAMD64VMULPS128 + OpAMD64VSCALEFPS128 + OpAMD64VORPS128 + OpAMD64VHADDPS128 + OpAMD64VHSUBPS128 + OpAMD64VSQRTPS128 + OpAMD64VXORPS128 + OpAMD64VADDPS256 + OpAMD64VADDSUBPS256 + OpAMD64VANDPS256 + OpAMD64VANDNPS256 + OpAMD64VRCP14PS256 + OpAMD64VRSQRTPS256 + OpAMD64VDIVPS256 + OpAMD64VFMADD132PS256 + OpAMD64VFMADD213PS256 + OpAMD64VFMADD231PS256 + OpAMD64VFMADDSUB132PS256 + OpAMD64VFMADDSUB213PS256 + OpAMD64VFMADDSUB231PS256 + OpAMD64VFMSUB132PS256 + OpAMD64VFMSUB213PS256 + OpAMD64VFMSUB231PS256 + OpAMD64VFMSUBADD132PS256 + OpAMD64VFMSUBADD213PS256 + OpAMD64VFMSUBADD231PS256 + OpAMD64VFNMADD132PS256 + OpAMD64VFNMADD213PS256 + OpAMD64VFNMADD231PS256 + OpAMD64VFNMSUB132PS256 + OpAMD64VFNMSUB213PS256 + OpAMD64VFNMSUB231PS256 + OpAMD64VADDPSMasked256 + OpAMD64VANDPSMasked256 + OpAMD64VANDNPSMasked256 + OpAMD64VRCP14PSMasked256 + OpAMD64VRSQRT14PSMasked256 + OpAMD64VDIVPSMasked256 + OpAMD64VFMADD132PSMasked256 + OpAMD64VFMADD213PSMasked256 + OpAMD64VFMADD231PSMasked256 + OpAMD64VFMADDSUB132PSMasked256 + OpAMD64VFMADDSUB213PSMasked256 + OpAMD64VFMADDSUB231PSMasked256 + OpAMD64VFMSUB132PSMasked256 + OpAMD64VFMSUB213PSMasked256 + OpAMD64VFMSUB231PSMasked256 + OpAMD64VFMSUBADD132PSMasked256 + OpAMD64VFMSUBADD213PSMasked256 + OpAMD64VFMSUBADD231PSMasked256 + OpAMD64VFNMADD132PSMasked256 + OpAMD64VFNMADD213PSMasked256 + OpAMD64VFNMADD231PSMasked256 + OpAMD64VFNMSUB132PSMasked256 + OpAMD64VFNMSUB213PSMasked256 + OpAMD64VFNMSUB231PSMasked256 + OpAMD64VMAXPSMasked256 + OpAMD64VMINPSMasked256 + OpAMD64VMULPSMasked256 + OpAMD64VSCALEFPSMasked256 + OpAMD64VORPSMasked256 + OpAMD64VSQRTPSMasked256 + OpAMD64VXORPSMasked256 + OpAMD64VMAXPS256 + OpAMD64VMINPS256 + OpAMD64VMULPS256 + OpAMD64VSCALEFPS256 + OpAMD64VORPS256 + OpAMD64VHADDPS256 + OpAMD64VHSUBPS256 + OpAMD64VSQRTPS256 + OpAMD64VXORPS256 + OpAMD64VADDPD128 + OpAMD64VADDSUBPD128 + OpAMD64VANDPD128 + OpAMD64VANDNPD128 + OpAMD64VRCP14PD128 + OpAMD64VRSQRT14PD128 + OpAMD64VDIVPD128 + OpAMD64VFMADD132PD128 + OpAMD64VFMADD213PD128 + OpAMD64VFMADD231PD128 + OpAMD64VFMADDSUB132PD128 + OpAMD64VFMADDSUB213PD128 + OpAMD64VFMADDSUB231PD128 + OpAMD64VFMSUB132PD128 + OpAMD64VFMSUB213PD128 + OpAMD64VFMSUB231PD128 + OpAMD64VFMSUBADD132PD128 + OpAMD64VFMSUBADD213PD128 + OpAMD64VFMSUBADD231PD128 + OpAMD64VFNMADD132PD128 + OpAMD64VFNMADD213PD128 + OpAMD64VFNMADD231PD128 + OpAMD64VFNMSUB132PD128 + OpAMD64VFNMSUB213PD128 + OpAMD64VFNMSUB231PD128 + OpAMD64VADDPDMasked128 + OpAMD64VANDPDMasked128 + OpAMD64VANDNPDMasked128 + OpAMD64VRCP14PDMasked128 + OpAMD64VRSQRT14PDMasked128 + OpAMD64VDIVPDMasked128 + OpAMD64VFMADD132PDMasked128 + OpAMD64VFMADD213PDMasked128 + OpAMD64VFMADD231PDMasked128 + OpAMD64VFMADDSUB132PDMasked128 + OpAMD64VFMADDSUB213PDMasked128 + OpAMD64VFMADDSUB231PDMasked128 + OpAMD64VFMSUB132PDMasked128 + OpAMD64VFMSUB213PDMasked128 + OpAMD64VFMSUB231PDMasked128 + OpAMD64VFMSUBADD132PDMasked128 + OpAMD64VFMSUBADD213PDMasked128 + OpAMD64VFMSUBADD231PDMasked128 + OpAMD64VFNMADD132PDMasked128 + OpAMD64VFNMADD213PDMasked128 + OpAMD64VFNMADD231PDMasked128 + OpAMD64VFNMSUB132PDMasked128 + OpAMD64VFNMSUB213PDMasked128 + OpAMD64VFNMSUB231PDMasked128 + OpAMD64VMAXPDMasked128 + OpAMD64VMINPDMasked128 + OpAMD64VMULPDMasked128 + OpAMD64VSCALEFPDMasked128 + OpAMD64VORPDMasked128 + OpAMD64VSQRTPDMasked128 + OpAMD64VXORPDMasked128 + OpAMD64VMAXPD128 + OpAMD64VMINPD128 + OpAMD64VMULPD128 + OpAMD64VSCALEFPD128 + OpAMD64VORPD128 + OpAMD64VHADDPD128 + OpAMD64VHSUBPD128 + OpAMD64VSQRTPD128 + OpAMD64VXORPD128 + OpAMD64VADDPD256 + OpAMD64VADDSUBPD256 + OpAMD64VANDPD256 + OpAMD64VANDNPD256 + OpAMD64VRCP14PD256 + OpAMD64VRSQRT14PD256 + OpAMD64VDIVPD256 + OpAMD64VFMADD132PD256 + OpAMD64VFMADD213PD256 + OpAMD64VFMADD231PD256 + OpAMD64VFMADDSUB132PD256 + OpAMD64VFMADDSUB213PD256 + OpAMD64VFMADDSUB231PD256 + OpAMD64VFMSUB132PD256 + OpAMD64VFMSUB213PD256 + OpAMD64VFMSUB231PD256 + OpAMD64VFMSUBADD132PD256 + OpAMD64VFMSUBADD213PD256 + OpAMD64VFMSUBADD231PD256 + OpAMD64VFNMADD132PD256 + OpAMD64VFNMADD213PD256 + OpAMD64VFNMADD231PD256 + OpAMD64VFNMSUB132PD256 + OpAMD64VFNMSUB213PD256 + OpAMD64VFNMSUB231PD256 + OpAMD64VADDPDMasked256 + OpAMD64VANDPDMasked256 + OpAMD64VANDNPDMasked256 + OpAMD64VRCP14PDMasked256 + OpAMD64VRSQRT14PDMasked256 + OpAMD64VDIVPDMasked256 + OpAMD64VFMADD132PDMasked256 + OpAMD64VFMADD213PDMasked256 + OpAMD64VFMADD231PDMasked256 + OpAMD64VFMADDSUB132PDMasked256 + OpAMD64VFMADDSUB213PDMasked256 + OpAMD64VFMADDSUB231PDMasked256 + OpAMD64VFMSUB132PDMasked256 + OpAMD64VFMSUB213PDMasked256 + OpAMD64VFMSUB231PDMasked256 + OpAMD64VFMSUBADD132PDMasked256 + OpAMD64VFMSUBADD213PDMasked256 + OpAMD64VFMSUBADD231PDMasked256 + OpAMD64VFNMADD132PDMasked256 + OpAMD64VFNMADD213PDMasked256 + OpAMD64VFNMADD231PDMasked256 + OpAMD64VFNMSUB132PDMasked256 + OpAMD64VFNMSUB213PDMasked256 + OpAMD64VFNMSUB231PDMasked256 + OpAMD64VMAXPDMasked256 + OpAMD64VMINPDMasked256 + OpAMD64VMULPDMasked256 + OpAMD64VSCALEFPDMasked256 + OpAMD64VORPDMasked256 + OpAMD64VSQRTPDMasked256 + OpAMD64VXORPDMasked256 + OpAMD64VMAXPD256 + OpAMD64VMINPD256 + OpAMD64VMULPD256 + OpAMD64VSCALEFPD256 + OpAMD64VORPD256 + OpAMD64VHADDPD256 + OpAMD64VHSUBPD256 + OpAMD64VSQRTPD256 + OpAMD64VXORPD256 + OpAMD64VADDPD512 + OpAMD64VANDPD512 + OpAMD64VANDNPD512 + OpAMD64VRCP14PD512 + OpAMD64VRSQRT14PD512 + OpAMD64VDIVPD512 + OpAMD64VFMADD132PD512 + OpAMD64VFMADD213PD512 + OpAMD64VFMADD231PD512 + OpAMD64VFMADDSUB132PD512 + OpAMD64VFMADDSUB213PD512 + OpAMD64VFMADDSUB231PD512 + OpAMD64VFMSUB132PD512 + OpAMD64VFMSUB213PD512 + OpAMD64VFMSUB231PD512 + OpAMD64VFMSUBADD132PD512 + OpAMD64VFMSUBADD213PD512 + OpAMD64VFMSUBADD231PD512 + OpAMD64VFNMADD132PD512 + OpAMD64VFNMADD213PD512 + OpAMD64VFNMADD231PD512 + OpAMD64VFNMSUB132PD512 + OpAMD64VFNMSUB213PD512 + OpAMD64VFNMSUB231PD512 + OpAMD64VADDPDMasked512 + OpAMD64VANDPDMasked512 + OpAMD64VANDNPDMasked512 + OpAMD64VRCP14PDMasked512 + OpAMD64VRSQRT14PDMasked512 + OpAMD64VDIVPDMasked512 + OpAMD64VFMADD132PDMasked512 + OpAMD64VFMADD213PDMasked512 + OpAMD64VFMADD231PDMasked512 + OpAMD64VFMADDSUB132PDMasked512 + OpAMD64VFMADDSUB213PDMasked512 + OpAMD64VFMADDSUB231PDMasked512 + OpAMD64VFMSUB132PDMasked512 + OpAMD64VFMSUB213PDMasked512 + OpAMD64VFMSUB231PDMasked512 + OpAMD64VFMSUBADD132PDMasked512 + OpAMD64VFMSUBADD213PDMasked512 + OpAMD64VFMSUBADD231PDMasked512 + OpAMD64VFNMADD132PDMasked512 + OpAMD64VFNMADD213PDMasked512 + OpAMD64VFNMADD231PDMasked512 + OpAMD64VFNMSUB132PDMasked512 + OpAMD64VFNMSUB213PDMasked512 + OpAMD64VFNMSUB231PDMasked512 + OpAMD64VMAXPDMasked512 + OpAMD64VMINPDMasked512 + OpAMD64VMULPDMasked512 + OpAMD64VSCALEFPDMasked512 + OpAMD64VORPDMasked512 + OpAMD64VSQRTPDMasked512 + OpAMD64VXORPDMasked512 + OpAMD64VMAXPD512 + OpAMD64VMINPD512 + OpAMD64VMULPD512 + OpAMD64VSCALEFPD512 + OpAMD64VORPD512 + OpAMD64VSQRTPD512 + OpAMD64VXORPD512 + OpAMD64VPABSW256 + OpAMD64VPADDW256 + OpAMD64VPAND256 + OpAMD64VPANDN256 + OpAMD64VPCMPEQW256 + OpAMD64VPCMPGTW256 + OpAMD64VPABSWMasked256 + OpAMD64VPADDWMasked256 + OpAMD64VPCMPEQWMasked256 + OpAMD64VPCMPGTWMasked256 + OpAMD64VPMAXSWMasked256 + OpAMD64VPMINSWMasked256 + OpAMD64VPMULHWMasked256 + OpAMD64VPMULLWMasked256 + OpAMD64VPMADDWDMasked256 + OpAMD64VPOPCNTWMasked256 + OpAMD64VPADDSWMasked256 + OpAMD64VPSUBSWMasked256 + OpAMD64VPSUBWMasked256 + OpAMD64VPMAXSW256 + OpAMD64VPMINSW256 + OpAMD64VPMULHW256 + OpAMD64VPMULLW256 + OpAMD64VPOR256 + OpAMD64VPMADDWD256 + OpAMD64VPHADDW256 + OpAMD64VPHSUBW256 + OpAMD64VPOPCNTW256 + OpAMD64VPADDSW256 + OpAMD64VPHADDSW256 + OpAMD64VPHSUBSW256 + OpAMD64VPSUBSW256 + OpAMD64VPSIGNW256 + OpAMD64VPSUBW256 + OpAMD64VPXOR256 + OpAMD64VPABSW512 + OpAMD64VPADDW512 + OpAMD64VPCMPEQW512 + OpAMD64VPCMPGTW512 + OpAMD64VPABSWMasked512 + OpAMD64VPADDWMasked512 + OpAMD64VPCMPEQWMasked512 + OpAMD64VPCMPGTWMasked512 + OpAMD64VPMAXSWMasked512 + OpAMD64VPMINSWMasked512 + OpAMD64VPMULHWMasked512 + OpAMD64VPMULLWMasked512 + OpAMD64VPMADDWDMasked512 + OpAMD64VPOPCNTWMasked512 + OpAMD64VPADDSWMasked512 + OpAMD64VPSUBSWMasked512 + OpAMD64VPSUBWMasked512 + OpAMD64VPMAXSW512 + OpAMD64VPMINSW512 + OpAMD64VPMULHW512 + OpAMD64VPMULLW512 + OpAMD64VPMADDWD512 + OpAMD64VPOPCNTW512 + OpAMD64VPADDSW512 + OpAMD64VPSUBSW512 + OpAMD64VPSUBW512 + OpAMD64VPABSW128 + OpAMD64VPADDW128 + OpAMD64VPAND128 + OpAMD64VPANDN128 + OpAMD64VPCMPEQW128 + OpAMD64VPCMPGTW128 + OpAMD64VPABSWMasked128 + OpAMD64VPADDWMasked128 + OpAMD64VPCMPEQWMasked128 + OpAMD64VPCMPGTWMasked128 + OpAMD64VPMAXSWMasked128 + OpAMD64VPMINSWMasked128 + OpAMD64VPMULHWMasked128 + OpAMD64VPMULLWMasked128 + OpAMD64VPMADDWDMasked128 + OpAMD64VPOPCNTWMasked128 + OpAMD64VPADDSWMasked128 + OpAMD64VPSUBSWMasked128 + OpAMD64VPSUBWMasked128 + OpAMD64VPMAXSW128 + OpAMD64VPMINSW128 + OpAMD64VPMULHW128 + OpAMD64VPMULLW128 + OpAMD64VPOR128 + OpAMD64VPMADDWD128 + OpAMD64VPHADDW128 + OpAMD64VPHSUBW128 + OpAMD64VPOPCNTW128 + OpAMD64VPADDSW128 + OpAMD64VPHADDSW128 + OpAMD64VPHSUBSW128 + OpAMD64VPSUBSW128 + OpAMD64VPSIGNW128 + OpAMD64VPSUBW128 + OpAMD64VPXOR128 + OpAMD64VPABSD512 + OpAMD64VPADDD512 + OpAMD64VPANDD512 + OpAMD64VPANDND512 + OpAMD64VPCMPEQD512 + OpAMD64VPCMPGTD512 + OpAMD64VPABSDMasked512 + OpAMD64VPADDDMasked512 + OpAMD64VPANDDMasked512 + OpAMD64VPANDNDMasked512 + OpAMD64VPCMPEQDMasked512 + OpAMD64VPCMPGTDMasked512 + OpAMD64VPMAXSDMasked512 + OpAMD64VPMINSDMasked512 + OpAMD64VPMULLDMasked512 + OpAMD64VPORDMasked512 + OpAMD64VPDPWSSDMasked512 + OpAMD64VPOPCNTDMasked512 + OpAMD64VPDPWSSDSMasked512 + OpAMD64VPDPBUSDSMasked512 + OpAMD64VPSUBDMasked512 + OpAMD64VPDPBUSDMasked512 + OpAMD64VPXORDMasked512 + OpAMD64VPMAXSD512 + OpAMD64VPMINSD512 + OpAMD64VPMULLD512 + OpAMD64VPORD512 + OpAMD64VPDPWSSD512 + OpAMD64VPOPCNTD512 + OpAMD64VPDPWSSDS512 + OpAMD64VPDPBUSDS512 + OpAMD64VPSUBD512 + OpAMD64VPDPBUSD512 + OpAMD64VPXORD512 + OpAMD64VPABSD128 + OpAMD64VPADDD128 + OpAMD64VPCMPEQD128 + OpAMD64VPCMPGTD128 + OpAMD64VPABSDMasked128 + OpAMD64VPADDDMasked128 + OpAMD64VPANDDMasked128 + OpAMD64VPANDNDMasked128 + OpAMD64VPCMPEQDMasked128 + OpAMD64VPCMPGTDMasked128 + OpAMD64VPMAXSDMasked128 + OpAMD64VPMINSDMasked128 + OpAMD64VPMULLDMasked128 + OpAMD64VPORDMasked128 + OpAMD64VPDPWSSDMasked128 + OpAMD64VPOPCNTDMasked128 + OpAMD64VPDPWSSDSMasked128 + OpAMD64VPDPBUSDSMasked128 + OpAMD64VPSUBDMasked128 + OpAMD64VPDPBUSDMasked128 + OpAMD64VPXORDMasked128 + OpAMD64VPMAXSD128 + OpAMD64VPMINSD128 + OpAMD64VPMULDQ128 + OpAMD64VPMULLD128 + OpAMD64VPDPWSSD128 + OpAMD64VPHADDD128 + OpAMD64VPHSUBD128 + OpAMD64VPOPCNTD128 + OpAMD64VPDPWSSDS128 + OpAMD64VPDPBUSDS128 + OpAMD64VPSIGND128 + OpAMD64VPSUBD128 + OpAMD64VPDPBUSD128 + OpAMD64VPABSD256 + OpAMD64VPADDD256 + OpAMD64VPCMPEQD256 + OpAMD64VPCMPGTD256 + OpAMD64VPABSDMasked256 + OpAMD64VPADDDMasked256 + OpAMD64VPANDDMasked256 + OpAMD64VPANDNDMasked256 + OpAMD64VPCMPEQDMasked256 + OpAMD64VPCMPGTDMasked256 + OpAMD64VPMAXSDMasked256 + OpAMD64VPMINSDMasked256 + OpAMD64VPMULLDMasked256 + OpAMD64VPORDMasked256 + OpAMD64VPDPWSSDMasked256 + OpAMD64VPOPCNTDMasked256 + OpAMD64VPDPWSSDSMasked256 + OpAMD64VPDPBUSDSMasked256 + OpAMD64VPSUBDMasked256 + OpAMD64VPDPBUSDMasked256 + OpAMD64VPXORDMasked256 + OpAMD64VPMAXSD256 + OpAMD64VPMINSD256 + OpAMD64VPMULDQ256 + OpAMD64VPMULLD256 + OpAMD64VPDPWSSD256 + OpAMD64VPHADDD256 + OpAMD64VPHSUBD256 + OpAMD64VPOPCNTD256 + OpAMD64VPDPWSSDS256 + OpAMD64VPDPBUSDS256 + OpAMD64VPSIGND256 + OpAMD64VPSUBD256 + OpAMD64VPDPBUSD256 + OpAMD64VPABSQ128 + OpAMD64VPADDQ128 + OpAMD64VPCMPEQQ128 + OpAMD64VPCMPGTQ128 + OpAMD64VPABSQMasked128 + OpAMD64VPADDQMasked128 + OpAMD64VPANDQMasked128 + OpAMD64VPANDNQMasked128 + OpAMD64VPCMPEQQMasked128 + OpAMD64VPCMPGTQMasked128 + OpAMD64VPMAXSQMasked128 + OpAMD64VPMINSQMasked128 + OpAMD64VPMULDQMasked128 + OpAMD64VPMULLQMasked128 + OpAMD64VPORQMasked128 + OpAMD64VPOPCNTQMasked128 + OpAMD64VPSUBQMasked128 + OpAMD64VPXORQMasked128 + OpAMD64VPMAXSQ128 + OpAMD64VPMINSQ128 + OpAMD64VPMULLQ128 + OpAMD64VPOPCNTQ128 + OpAMD64VPSUBQ128 + OpAMD64VPABSQ256 + OpAMD64VPADDQ256 + OpAMD64VPCMPEQQ256 + OpAMD64VPCMPGTQ256 + OpAMD64VPABSQMasked256 + OpAMD64VPADDQMasked256 + OpAMD64VPANDQMasked256 + OpAMD64VPANDNQMasked256 + OpAMD64VPCMPEQQMasked256 + OpAMD64VPCMPGTQMasked256 + OpAMD64VPMAXSQMasked256 + OpAMD64VPMINSQMasked256 + OpAMD64VPMULDQMasked256 + OpAMD64VPMULLQMasked256 + OpAMD64VPORQMasked256 + OpAMD64VPOPCNTQMasked256 + OpAMD64VPSUBQMasked256 + OpAMD64VPXORQMasked256 + OpAMD64VPMAXSQ256 + OpAMD64VPMINSQ256 + OpAMD64VPMULLQ256 + OpAMD64VPOPCNTQ256 + OpAMD64VPSUBQ256 + OpAMD64VPABSQ512 + OpAMD64VPADDQ512 + OpAMD64VPANDQ512 + OpAMD64VPANDNQ512 + OpAMD64VPCMPEQQ512 + OpAMD64VPCMPGTQ512 + OpAMD64VPABSQMasked512 + OpAMD64VPADDQMasked512 + OpAMD64VPANDQMasked512 + OpAMD64VPANDNQMasked512 + OpAMD64VPCMPEQQMasked512 + OpAMD64VPCMPGTQMasked512 + OpAMD64VPMAXSQMasked512 + OpAMD64VPMINSQMasked512 + OpAMD64VPMULDQMasked512 + OpAMD64VPMULLQMasked512 + OpAMD64VPORQMasked512 + OpAMD64VPOPCNTQMasked512 + OpAMD64VPSUBQMasked512 + OpAMD64VPXORQMasked512 + OpAMD64VPMAXSQ512 + OpAMD64VPMINSQ512 + OpAMD64VPMULDQ512 + OpAMD64VPMULLQ512 + OpAMD64VPORQ512 + OpAMD64VPOPCNTQ512 + OpAMD64VPSUBQ512 + OpAMD64VPXORQ512 + OpAMD64VPABSB128 + OpAMD64VPADDB128 + OpAMD64VPCMPEQB128 + OpAMD64VPCMPGTB128 + OpAMD64VPABSBMasked128 + OpAMD64VPADDBMasked128 + OpAMD64VPCMPEQBMasked128 + OpAMD64VPCMPGTBMasked128 + OpAMD64VPMAXSBMasked128 + OpAMD64VPMINSBMasked128 + OpAMD64VPOPCNTBMasked128 + OpAMD64VPADDSBMasked128 + OpAMD64VPSUBSBMasked128 + OpAMD64VPSUBBMasked128 + OpAMD64VPMAXSB128 + OpAMD64VPMINSB128 + OpAMD64VPOPCNTB128 + OpAMD64VPADDSB128 + OpAMD64VPSUBSB128 + OpAMD64VPSIGNB128 + OpAMD64VPSUBB128 + OpAMD64VPABSB256 + OpAMD64VPADDB256 + OpAMD64VPCMPEQB256 + OpAMD64VPCMPGTB256 + OpAMD64VPABSBMasked256 + OpAMD64VPADDBMasked256 + OpAMD64VPCMPEQBMasked256 + OpAMD64VPCMPGTBMasked256 + OpAMD64VPMAXSBMasked256 + OpAMD64VPMINSBMasked256 + OpAMD64VPOPCNTBMasked256 + OpAMD64VPADDSBMasked256 + OpAMD64VPSUBSBMasked256 + OpAMD64VPSUBBMasked256 + OpAMD64VPMAXSB256 + OpAMD64VPMINSB256 + OpAMD64VPOPCNTB256 + OpAMD64VPADDSB256 + OpAMD64VPSUBSB256 + OpAMD64VPSIGNB256 + OpAMD64VPSUBB256 + OpAMD64VPABSB512 + OpAMD64VPADDB512 + OpAMD64VPCMPEQB512 + OpAMD64VPCMPGTB512 + OpAMD64VPABSBMasked512 + OpAMD64VPADDBMasked512 + OpAMD64VPCMPEQBMasked512 + OpAMD64VPCMPGTBMasked512 + OpAMD64VPMAXSBMasked512 + OpAMD64VPMINSBMasked512 + OpAMD64VPOPCNTBMasked512 + OpAMD64VPADDSBMasked512 + OpAMD64VPSUBSBMasked512 + OpAMD64VPSUBBMasked512 + OpAMD64VPMAXSB512 + OpAMD64VPMINSB512 + OpAMD64VPOPCNTB512 + OpAMD64VPADDSB512 + OpAMD64VPSUBSB512 + OpAMD64VPSUBB512 + OpAMD64VPAVGW256 + OpAMD64VPAVGWMasked256 + OpAMD64VPMAXUWMasked256 + OpAMD64VPMINUWMasked256 + OpAMD64VPMULHUWMasked256 + OpAMD64VPMADDUBSWMasked256 + OpAMD64VPMAXUW256 + OpAMD64VPMINUW256 + OpAMD64VPMULHUW256 + OpAMD64VPAVGW512 + OpAMD64VPAVGWMasked512 + OpAMD64VPMAXUWMasked512 + OpAMD64VPMINUWMasked512 + OpAMD64VPMULHUWMasked512 + OpAMD64VPMADDUBSWMasked512 + OpAMD64VPMAXUW512 + OpAMD64VPMINUW512 + OpAMD64VPMULHUW512 + OpAMD64VPMADDUBSW512 + OpAMD64VPAVGW128 + OpAMD64VPAVGWMasked128 + OpAMD64VPMAXUWMasked128 + OpAMD64VPMINUWMasked128 + OpAMD64VPMULHUWMasked128 + OpAMD64VPMADDUBSWMasked128 + OpAMD64VPMAXUW128 + OpAMD64VPMINUW128 + OpAMD64VPMULHUW128 + OpAMD64VPMAXUDMasked512 + OpAMD64VPMINUDMasked512 + OpAMD64VPMAXUD512 + OpAMD64VPMINUD512 + OpAMD64VPMAXUDMasked128 + OpAMD64VPMINUDMasked128 + OpAMD64VPMAXUD128 + OpAMD64VPMINUD128 + OpAMD64VPMULUDQ128 + OpAMD64VPMAXUDMasked256 + OpAMD64VPMINUDMasked256 + OpAMD64VPMAXUD256 + OpAMD64VPMINUD256 + OpAMD64VPMULUDQ256 + OpAMD64VPMAXUQMasked128 + OpAMD64VPMINUQMasked128 + OpAMD64VPMULUDQMasked128 + OpAMD64VPMAXUQ128 + OpAMD64VPMINUQ128 + OpAMD64VPMAXUQMasked256 + OpAMD64VPMINUQMasked256 + OpAMD64VPMULUDQMasked256 + OpAMD64VPMAXUQ256 + OpAMD64VPMINUQ256 + OpAMD64VPMAXUQMasked512 + OpAMD64VPMINUQMasked512 + OpAMD64VPMULUDQMasked512 + OpAMD64VPMAXUQ512 + OpAMD64VPMINUQ512 + OpAMD64VPMULUDQ512 + OpAMD64VPAVGB128 + OpAMD64VPAVGBMasked128 + OpAMD64VPMAXUBMasked128 + OpAMD64VPMINUBMasked128 + OpAMD64VPMAXUB128 + OpAMD64VPMINUB128 + OpAMD64VPMADDUBSW128 + OpAMD64VPAVGB256 + OpAMD64VPAVGBMasked256 + OpAMD64VPMAXUBMasked256 + OpAMD64VPMINUBMasked256 + OpAMD64VPMAXUB256 + OpAMD64VPMINUB256 + OpAMD64VPMADDUBSW256 + OpAMD64VPAVGB512 + OpAMD64VPAVGBMasked512 + OpAMD64VPMAXUBMasked512 + OpAMD64VPMINUBMasked512 + OpAMD64VPMAXUB512 + OpAMD64VPMINUB512 + OpAMD64VRNDSCALEPS512 + OpAMD64VREDUCEPS512 + OpAMD64VCMPPS512 + OpAMD64VRNDSCALEPSMasked512 + OpAMD64VREDUCEPSMasked512 + OpAMD64VCMPPSMasked512 + OpAMD64VROUNDPS128 + OpAMD64VRNDSCALEPS128 + OpAMD64VREDUCEPS128 + OpAMD64VCMPPS128 + OpAMD64VRNDSCALEPSMasked128 + OpAMD64VREDUCEPSMasked128 + OpAMD64VCMPPSMasked128 + OpAMD64VROUNDPS256 + OpAMD64VRNDSCALEPS256 + OpAMD64VREDUCEPS256 + OpAMD64VCMPPS256 + OpAMD64VRNDSCALEPSMasked256 + OpAMD64VREDUCEPSMasked256 + OpAMD64VCMPPSMasked256 + OpAMD64VROUNDPD128 + OpAMD64VRNDSCALEPD128 + OpAMD64VREDUCEPD128 + OpAMD64VDPPD128 + OpAMD64VCMPPD128 + OpAMD64VRNDSCALEPDMasked128 + OpAMD64VREDUCEPDMasked128 + OpAMD64VCMPPDMasked128 + OpAMD64VROUNDPD256 + OpAMD64VRNDSCALEPD256 + OpAMD64VREDUCEPD256 + OpAMD64VCMPPD256 + OpAMD64VRNDSCALEPDMasked256 + OpAMD64VREDUCEPDMasked256 + OpAMD64VCMPPDMasked256 + OpAMD64VRNDSCALEPD512 + OpAMD64VREDUCEPD512 + OpAMD64VCMPPD512 + OpAMD64VRNDSCALEPDMasked512 + OpAMD64VREDUCEPDMasked512 + OpAMD64VCMPPDMasked512 + OpAMD64VPCMPW256 + OpAMD64VPCMPWMasked256 + OpAMD64VPCMPW512 + OpAMD64VPCMPWMasked512 + OpAMD64VPCMPW128 + OpAMD64VPCMPWMasked128 + OpAMD64VPCMPD512 + OpAMD64VPCMPDMasked512 + OpAMD64VPCMPD128 + OpAMD64VPCMPDMasked128 + OpAMD64VPCMPD256 + OpAMD64VPCMPDMasked256 + OpAMD64VPCMPQ128 + OpAMD64VPCMPQMasked128 + OpAMD64VPCMPQ256 + OpAMD64VPCMPQMasked256 + OpAMD64VPCMPQ512 + OpAMD64VPCMPQMasked512 + OpAMD64VPCMPB128 + OpAMD64VPCMPBMasked128 + OpAMD64VPCMPB256 + OpAMD64VPCMPBMasked256 + OpAMD64VPCMPB512 + OpAMD64VPCMPBMasked512 + OpAMD64VPCMPUW256 + OpAMD64VPCMPUWMasked256 + OpAMD64VPCMPUW512 + OpAMD64VPCMPUWMasked512 + OpAMD64VPCMPUW128 + OpAMD64VPCMPUWMasked128 + OpAMD64VPCMPUD512 + OpAMD64VPCMPUDMasked512 + OpAMD64VPCMPUD128 + OpAMD64VPCMPUDMasked128 + OpAMD64VPCMPUD256 + OpAMD64VPCMPUDMasked256 + OpAMD64VPCMPUQ128 + OpAMD64VPCMPUQMasked128 + OpAMD64VPCMPUQ256 + OpAMD64VPCMPUQMasked256 + OpAMD64VPCMPUQ512 + OpAMD64VPCMPUQMasked512 + OpAMD64VPCMPUB128 + OpAMD64VPCMPUBMasked128 + OpAMD64VPCMPUB256 + OpAMD64VPCMPUBMasked256 + OpAMD64VPCMPUB512 + OpAMD64VPCMPUBMasked512 OpARMADD OpARMADDconst @@ -3386,6 +4305,1559 @@ const ( OpClobberReg OpPrefetchCache OpPrefetchCacheStreamed + OpAdd32x4 + OpZeroSIMD + OpAddFloat32x16 + OpAndFloat32x16 + OpAndNotFloat32x16 + OpApproximateReciprocalFloat32x16 + OpApproximateReciprocalOfSqrtFloat32x16 + OpDivFloat32x16 + OpEqualFloat32x16 + OpFusedMultiplyAdd132Float32x16 + OpFusedMultiplyAdd213Float32x16 + OpFusedMultiplyAdd231Float32x16 + OpFusedMultiplyAddSub132Float32x16 + OpFusedMultiplyAddSub213Float32x16 + OpFusedMultiplyAddSub231Float32x16 + OpFusedMultiplySub132Float32x16 + OpFusedMultiplySub213Float32x16 + OpFusedMultiplySub231Float32x16 + OpFusedMultiplySubAdd132Float32x16 + OpFusedMultiplySubAdd213Float32x16 + OpFusedMultiplySubAdd231Float32x16 + OpFusedNegativeMultiplyAdd132Float32x16 + OpFusedNegativeMultiplyAdd213Float32x16 + OpFusedNegativeMultiplyAdd231Float32x16 + OpFusedNegativeMultiplySub132Float32x16 + OpFusedNegativeMultiplySub213Float32x16 + OpFusedNegativeMultiplySub231Float32x16 + OpGreaterFloat32x16 + OpGreaterEqualFloat32x16 + OpIsNanFloat32x16 + OpLessFloat32x16 + OpLessEqualFloat32x16 + OpMaskedAddFloat32x16 + OpMaskedAndFloat32x16 + OpMaskedAndNotFloat32x16 + OpMaskedApproximateReciprocalFloat32x16 + OpMaskedApproximateReciprocalOfSqrtFloat32x16 + OpMaskedDivFloat32x16 + OpMaskedEqualFloat32x16 + OpMaskedFusedMultiplyAdd132Float32x16 + OpMaskedFusedMultiplyAdd213Float32x16 + OpMaskedFusedMultiplyAdd231Float32x16 + OpMaskedFusedMultiplyAddSub132Float32x16 + OpMaskedFusedMultiplyAddSub213Float32x16 + OpMaskedFusedMultiplyAddSub231Float32x16 + OpMaskedFusedMultiplySub132Float32x16 + OpMaskedFusedMultiplySub213Float32x16 + OpMaskedFusedMultiplySub231Float32x16 + OpMaskedFusedMultiplySubAdd132Float32x16 + OpMaskedFusedMultiplySubAdd213Float32x16 + OpMaskedFusedMultiplySubAdd231Float32x16 + OpMaskedFusedNegativeMultiplyAdd132Float32x16 + OpMaskedFusedNegativeMultiplyAdd213Float32x16 + OpMaskedFusedNegativeMultiplyAdd231Float32x16 + OpMaskedFusedNegativeMultiplySub132Float32x16 + OpMaskedFusedNegativeMultiplySub213Float32x16 + OpMaskedFusedNegativeMultiplySub231Float32x16 + OpMaskedGreaterFloat32x16 + OpMaskedGreaterEqualFloat32x16 + OpMaskedIsNanFloat32x16 + OpMaskedLessFloat32x16 + OpMaskedLessEqualFloat32x16 + OpMaskedMaxFloat32x16 + OpMaskedMinFloat32x16 + OpMaskedMulFloat32x16 + OpMaskedMulByPowOf2Float32x16 + OpMaskedNotEqualFloat32x16 + OpMaskedOrFloat32x16 + OpMaskedSqrtFloat32x16 + OpMaskedSubFloat32x16 + OpMaskedXorFloat32x16 + OpMaxFloat32x16 + OpMinFloat32x16 + OpMulFloat32x16 + OpMulByPowOf2Float32x16 + OpNotEqualFloat32x16 + OpOrFloat32x16 + OpSqrtFloat32x16 + OpSubFloat32x16 + OpXorFloat32x16 + OpAddFloat32x4 + OpAddSubFloat32x4 + OpAndFloat32x4 + OpAndNotFloat32x4 + OpApproximateReciprocalFloat32x4 + OpApproximateReciprocalOfSqrtFloat32x4 + OpCeilFloat32x4 + OpDivFloat32x4 + OpEqualFloat32x4 + OpFloorFloat32x4 + OpFusedMultiplyAdd132Float32x4 + OpFusedMultiplyAdd213Float32x4 + OpFusedMultiplyAdd231Float32x4 + OpFusedMultiplyAddSub132Float32x4 + OpFusedMultiplyAddSub213Float32x4 + OpFusedMultiplyAddSub231Float32x4 + OpFusedMultiplySub132Float32x4 + OpFusedMultiplySub213Float32x4 + OpFusedMultiplySub231Float32x4 + OpFusedMultiplySubAdd132Float32x4 + OpFusedMultiplySubAdd213Float32x4 + OpFusedMultiplySubAdd231Float32x4 + OpFusedNegativeMultiplyAdd132Float32x4 + OpFusedNegativeMultiplyAdd213Float32x4 + OpFusedNegativeMultiplyAdd231Float32x4 + OpFusedNegativeMultiplySub132Float32x4 + OpFusedNegativeMultiplySub213Float32x4 + OpFusedNegativeMultiplySub231Float32x4 + OpGreaterFloat32x4 + OpGreaterEqualFloat32x4 + OpIsNanFloat32x4 + OpLessFloat32x4 + OpLessEqualFloat32x4 + OpMaskedAddFloat32x4 + OpMaskedAndFloat32x4 + OpMaskedAndNotFloat32x4 + OpMaskedApproximateReciprocalFloat32x4 + OpMaskedApproximateReciprocalOfSqrtFloat32x4 + OpMaskedDivFloat32x4 + OpMaskedEqualFloat32x4 + OpMaskedFusedMultiplyAdd132Float32x4 + OpMaskedFusedMultiplyAdd213Float32x4 + OpMaskedFusedMultiplyAdd231Float32x4 + OpMaskedFusedMultiplyAddSub132Float32x4 + OpMaskedFusedMultiplyAddSub213Float32x4 + OpMaskedFusedMultiplyAddSub231Float32x4 + OpMaskedFusedMultiplySub132Float32x4 + OpMaskedFusedMultiplySub213Float32x4 + OpMaskedFusedMultiplySub231Float32x4 + OpMaskedFusedMultiplySubAdd132Float32x4 + OpMaskedFusedMultiplySubAdd213Float32x4 + OpMaskedFusedMultiplySubAdd231Float32x4 + OpMaskedFusedNegativeMultiplyAdd132Float32x4 + OpMaskedFusedNegativeMultiplyAdd213Float32x4 + OpMaskedFusedNegativeMultiplyAdd231Float32x4 + OpMaskedFusedNegativeMultiplySub132Float32x4 + OpMaskedFusedNegativeMultiplySub213Float32x4 + OpMaskedFusedNegativeMultiplySub231Float32x4 + OpMaskedGreaterFloat32x4 + OpMaskedGreaterEqualFloat32x4 + OpMaskedIsNanFloat32x4 + OpMaskedLessFloat32x4 + OpMaskedLessEqualFloat32x4 + OpMaskedMaxFloat32x4 + OpMaskedMinFloat32x4 + OpMaskedMulFloat32x4 + OpMaskedMulByPowOf2Float32x4 + OpMaskedNotEqualFloat32x4 + OpMaskedOrFloat32x4 + OpMaskedSqrtFloat32x4 + OpMaskedSubFloat32x4 + OpMaskedXorFloat32x4 + OpMaxFloat32x4 + OpMinFloat32x4 + OpMulFloat32x4 + OpMulByPowOf2Float32x4 + OpNotEqualFloat32x4 + OpOrFloat32x4 + OpPairwiseAddFloat32x4 + OpPairwiseSubFloat32x4 + OpRoundFloat32x4 + OpSqrtFloat32x4 + OpSubFloat32x4 + OpTruncFloat32x4 + OpXorFloat32x4 + OpAddFloat32x8 + OpAddSubFloat32x8 + OpAndFloat32x8 + OpAndNotFloat32x8 + OpApproximateReciprocalFloat32x8 + OpApproximateReciprocalOfSqrtFloat32x8 + OpCeilFloat32x8 + OpDivFloat32x8 + OpEqualFloat32x8 + OpFloorFloat32x8 + OpFusedMultiplyAdd132Float32x8 + OpFusedMultiplyAdd213Float32x8 + OpFusedMultiplyAdd231Float32x8 + OpFusedMultiplyAddSub132Float32x8 + OpFusedMultiplyAddSub213Float32x8 + OpFusedMultiplyAddSub231Float32x8 + OpFusedMultiplySub132Float32x8 + OpFusedMultiplySub213Float32x8 + OpFusedMultiplySub231Float32x8 + OpFusedMultiplySubAdd132Float32x8 + OpFusedMultiplySubAdd213Float32x8 + OpFusedMultiplySubAdd231Float32x8 + OpFusedNegativeMultiplyAdd132Float32x8 + OpFusedNegativeMultiplyAdd213Float32x8 + OpFusedNegativeMultiplyAdd231Float32x8 + OpFusedNegativeMultiplySub132Float32x8 + OpFusedNegativeMultiplySub213Float32x8 + OpFusedNegativeMultiplySub231Float32x8 + OpGreaterFloat32x8 + OpGreaterEqualFloat32x8 + OpIsNanFloat32x8 + OpLessFloat32x8 + OpLessEqualFloat32x8 + OpMaskedAddFloat32x8 + OpMaskedAndFloat32x8 + OpMaskedAndNotFloat32x8 + OpMaskedApproximateReciprocalFloat32x8 + OpMaskedApproximateReciprocalOfSqrtFloat32x8 + OpMaskedDivFloat32x8 + OpMaskedEqualFloat32x8 + OpMaskedFusedMultiplyAdd132Float32x8 + OpMaskedFusedMultiplyAdd213Float32x8 + OpMaskedFusedMultiplyAdd231Float32x8 + OpMaskedFusedMultiplyAddSub132Float32x8 + OpMaskedFusedMultiplyAddSub213Float32x8 + OpMaskedFusedMultiplyAddSub231Float32x8 + OpMaskedFusedMultiplySub132Float32x8 + OpMaskedFusedMultiplySub213Float32x8 + OpMaskedFusedMultiplySub231Float32x8 + OpMaskedFusedMultiplySubAdd132Float32x8 + OpMaskedFusedMultiplySubAdd213Float32x8 + OpMaskedFusedMultiplySubAdd231Float32x8 + OpMaskedFusedNegativeMultiplyAdd132Float32x8 + OpMaskedFusedNegativeMultiplyAdd213Float32x8 + OpMaskedFusedNegativeMultiplyAdd231Float32x8 + OpMaskedFusedNegativeMultiplySub132Float32x8 + OpMaskedFusedNegativeMultiplySub213Float32x8 + OpMaskedFusedNegativeMultiplySub231Float32x8 + OpMaskedGreaterFloat32x8 + OpMaskedGreaterEqualFloat32x8 + OpMaskedIsNanFloat32x8 + OpMaskedLessFloat32x8 + OpMaskedLessEqualFloat32x8 + OpMaskedMaxFloat32x8 + OpMaskedMinFloat32x8 + OpMaskedMulFloat32x8 + OpMaskedMulByPowOf2Float32x8 + OpMaskedNotEqualFloat32x8 + OpMaskedOrFloat32x8 + OpMaskedSqrtFloat32x8 + OpMaskedSubFloat32x8 + OpMaskedXorFloat32x8 + OpMaxFloat32x8 + OpMinFloat32x8 + OpMulFloat32x8 + OpMulByPowOf2Float32x8 + OpNotEqualFloat32x8 + OpOrFloat32x8 + OpPairwiseAddFloat32x8 + OpPairwiseSubFloat32x8 + OpRoundFloat32x8 + OpSqrtFloat32x8 + OpSubFloat32x8 + OpTruncFloat32x8 + OpXorFloat32x8 + OpAddFloat64x2 + OpAddSubFloat64x2 + OpAndFloat64x2 + OpAndNotFloat64x2 + OpApproximateReciprocalFloat64x2 + OpApproximateReciprocalOfSqrtFloat64x2 + OpCeilFloat64x2 + OpDivFloat64x2 + OpDotProdBroadcastFloat64x2 + OpEqualFloat64x2 + OpFloorFloat64x2 + OpFusedMultiplyAdd132Float64x2 + OpFusedMultiplyAdd213Float64x2 + OpFusedMultiplyAdd231Float64x2 + OpFusedMultiplyAddSub132Float64x2 + OpFusedMultiplyAddSub213Float64x2 + OpFusedMultiplyAddSub231Float64x2 + OpFusedMultiplySub132Float64x2 + OpFusedMultiplySub213Float64x2 + OpFusedMultiplySub231Float64x2 + OpFusedMultiplySubAdd132Float64x2 + OpFusedMultiplySubAdd213Float64x2 + OpFusedMultiplySubAdd231Float64x2 + OpFusedNegativeMultiplyAdd132Float64x2 + OpFusedNegativeMultiplyAdd213Float64x2 + OpFusedNegativeMultiplyAdd231Float64x2 + OpFusedNegativeMultiplySub132Float64x2 + OpFusedNegativeMultiplySub213Float64x2 + OpFusedNegativeMultiplySub231Float64x2 + OpGreaterFloat64x2 + OpGreaterEqualFloat64x2 + OpIsNanFloat64x2 + OpLessFloat64x2 + OpLessEqualFloat64x2 + OpMaskedAddFloat64x2 + OpMaskedAndFloat64x2 + OpMaskedAndNotFloat64x2 + OpMaskedApproximateReciprocalFloat64x2 + OpMaskedApproximateReciprocalOfSqrtFloat64x2 + OpMaskedDivFloat64x2 + OpMaskedEqualFloat64x2 + OpMaskedFusedMultiplyAdd132Float64x2 + OpMaskedFusedMultiplyAdd213Float64x2 + OpMaskedFusedMultiplyAdd231Float64x2 + OpMaskedFusedMultiplyAddSub132Float64x2 + OpMaskedFusedMultiplyAddSub213Float64x2 + OpMaskedFusedMultiplyAddSub231Float64x2 + OpMaskedFusedMultiplySub132Float64x2 + OpMaskedFusedMultiplySub213Float64x2 + OpMaskedFusedMultiplySub231Float64x2 + OpMaskedFusedMultiplySubAdd132Float64x2 + OpMaskedFusedMultiplySubAdd213Float64x2 + OpMaskedFusedMultiplySubAdd231Float64x2 + OpMaskedFusedNegativeMultiplyAdd132Float64x2 + OpMaskedFusedNegativeMultiplyAdd213Float64x2 + OpMaskedFusedNegativeMultiplyAdd231Float64x2 + OpMaskedFusedNegativeMultiplySub132Float64x2 + OpMaskedFusedNegativeMultiplySub213Float64x2 + OpMaskedFusedNegativeMultiplySub231Float64x2 + OpMaskedGreaterFloat64x2 + OpMaskedGreaterEqualFloat64x2 + OpMaskedIsNanFloat64x2 + OpMaskedLessFloat64x2 + OpMaskedLessEqualFloat64x2 + OpMaskedMaxFloat64x2 + OpMaskedMinFloat64x2 + OpMaskedMulFloat64x2 + OpMaskedMulByPowOf2Float64x2 + OpMaskedNotEqualFloat64x2 + OpMaskedOrFloat64x2 + OpMaskedSqrtFloat64x2 + OpMaskedSubFloat64x2 + OpMaskedXorFloat64x2 + OpMaxFloat64x2 + OpMinFloat64x2 + OpMulFloat64x2 + OpMulByPowOf2Float64x2 + OpNotEqualFloat64x2 + OpOrFloat64x2 + OpPairwiseAddFloat64x2 + OpPairwiseSubFloat64x2 + OpRoundFloat64x2 + OpSqrtFloat64x2 + OpSubFloat64x2 + OpTruncFloat64x2 + OpXorFloat64x2 + OpAddFloat64x4 + OpAddSubFloat64x4 + OpAndFloat64x4 + OpAndNotFloat64x4 + OpApproximateReciprocalFloat64x4 + OpApproximateReciprocalOfSqrtFloat64x4 + OpCeilFloat64x4 + OpDivFloat64x4 + OpEqualFloat64x4 + OpFloorFloat64x4 + OpFusedMultiplyAdd132Float64x4 + OpFusedMultiplyAdd213Float64x4 + OpFusedMultiplyAdd231Float64x4 + OpFusedMultiplyAddSub132Float64x4 + OpFusedMultiplyAddSub213Float64x4 + OpFusedMultiplyAddSub231Float64x4 + OpFusedMultiplySub132Float64x4 + OpFusedMultiplySub213Float64x4 + OpFusedMultiplySub231Float64x4 + OpFusedMultiplySubAdd132Float64x4 + OpFusedMultiplySubAdd213Float64x4 + OpFusedMultiplySubAdd231Float64x4 + OpFusedNegativeMultiplyAdd132Float64x4 + OpFusedNegativeMultiplyAdd213Float64x4 + OpFusedNegativeMultiplyAdd231Float64x4 + OpFusedNegativeMultiplySub132Float64x4 + OpFusedNegativeMultiplySub213Float64x4 + OpFusedNegativeMultiplySub231Float64x4 + OpGreaterFloat64x4 + OpGreaterEqualFloat64x4 + OpIsNanFloat64x4 + OpLessFloat64x4 + OpLessEqualFloat64x4 + OpMaskedAddFloat64x4 + OpMaskedAndFloat64x4 + OpMaskedAndNotFloat64x4 + OpMaskedApproximateReciprocalFloat64x4 + OpMaskedApproximateReciprocalOfSqrtFloat64x4 + OpMaskedDivFloat64x4 + OpMaskedEqualFloat64x4 + OpMaskedFusedMultiplyAdd132Float64x4 + OpMaskedFusedMultiplyAdd213Float64x4 + OpMaskedFusedMultiplyAdd231Float64x4 + OpMaskedFusedMultiplyAddSub132Float64x4 + OpMaskedFusedMultiplyAddSub213Float64x4 + OpMaskedFusedMultiplyAddSub231Float64x4 + OpMaskedFusedMultiplySub132Float64x4 + OpMaskedFusedMultiplySub213Float64x4 + OpMaskedFusedMultiplySub231Float64x4 + OpMaskedFusedMultiplySubAdd132Float64x4 + OpMaskedFusedMultiplySubAdd213Float64x4 + OpMaskedFusedMultiplySubAdd231Float64x4 + OpMaskedFusedNegativeMultiplyAdd132Float64x4 + OpMaskedFusedNegativeMultiplyAdd213Float64x4 + OpMaskedFusedNegativeMultiplyAdd231Float64x4 + OpMaskedFusedNegativeMultiplySub132Float64x4 + OpMaskedFusedNegativeMultiplySub213Float64x4 + OpMaskedFusedNegativeMultiplySub231Float64x4 + OpMaskedGreaterFloat64x4 + OpMaskedGreaterEqualFloat64x4 + OpMaskedIsNanFloat64x4 + OpMaskedLessFloat64x4 + OpMaskedLessEqualFloat64x4 + OpMaskedMaxFloat64x4 + OpMaskedMinFloat64x4 + OpMaskedMulFloat64x4 + OpMaskedMulByPowOf2Float64x4 + OpMaskedNotEqualFloat64x4 + OpMaskedOrFloat64x4 + OpMaskedSqrtFloat64x4 + OpMaskedSubFloat64x4 + OpMaskedXorFloat64x4 + OpMaxFloat64x4 + OpMinFloat64x4 + OpMulFloat64x4 + OpMulByPowOf2Float64x4 + OpNotEqualFloat64x4 + OpOrFloat64x4 + OpPairwiseAddFloat64x4 + OpPairwiseSubFloat64x4 + OpRoundFloat64x4 + OpSqrtFloat64x4 + OpSubFloat64x4 + OpTruncFloat64x4 + OpXorFloat64x4 + OpAddFloat64x8 + OpAndFloat64x8 + OpAndNotFloat64x8 + OpApproximateReciprocalFloat64x8 + OpApproximateReciprocalOfSqrtFloat64x8 + OpDivFloat64x8 + OpEqualFloat64x8 + OpFusedMultiplyAdd132Float64x8 + OpFusedMultiplyAdd213Float64x8 + OpFusedMultiplyAdd231Float64x8 + OpFusedMultiplyAddSub132Float64x8 + OpFusedMultiplyAddSub213Float64x8 + OpFusedMultiplyAddSub231Float64x8 + OpFusedMultiplySub132Float64x8 + OpFusedMultiplySub213Float64x8 + OpFusedMultiplySub231Float64x8 + OpFusedMultiplySubAdd132Float64x8 + OpFusedMultiplySubAdd213Float64x8 + OpFusedMultiplySubAdd231Float64x8 + OpFusedNegativeMultiplyAdd132Float64x8 + OpFusedNegativeMultiplyAdd213Float64x8 + OpFusedNegativeMultiplyAdd231Float64x8 + OpFusedNegativeMultiplySub132Float64x8 + OpFusedNegativeMultiplySub213Float64x8 + OpFusedNegativeMultiplySub231Float64x8 + OpGreaterFloat64x8 + OpGreaterEqualFloat64x8 + OpIsNanFloat64x8 + OpLessFloat64x8 + OpLessEqualFloat64x8 + OpMaskedAddFloat64x8 + OpMaskedAndFloat64x8 + OpMaskedAndNotFloat64x8 + OpMaskedApproximateReciprocalFloat64x8 + OpMaskedApproximateReciprocalOfSqrtFloat64x8 + OpMaskedDivFloat64x8 + OpMaskedEqualFloat64x8 + OpMaskedFusedMultiplyAdd132Float64x8 + OpMaskedFusedMultiplyAdd213Float64x8 + OpMaskedFusedMultiplyAdd231Float64x8 + OpMaskedFusedMultiplyAddSub132Float64x8 + OpMaskedFusedMultiplyAddSub213Float64x8 + OpMaskedFusedMultiplyAddSub231Float64x8 + OpMaskedFusedMultiplySub132Float64x8 + OpMaskedFusedMultiplySub213Float64x8 + OpMaskedFusedMultiplySub231Float64x8 + OpMaskedFusedMultiplySubAdd132Float64x8 + OpMaskedFusedMultiplySubAdd213Float64x8 + OpMaskedFusedMultiplySubAdd231Float64x8 + OpMaskedFusedNegativeMultiplyAdd132Float64x8 + OpMaskedFusedNegativeMultiplyAdd213Float64x8 + OpMaskedFusedNegativeMultiplyAdd231Float64x8 + OpMaskedFusedNegativeMultiplySub132Float64x8 + OpMaskedFusedNegativeMultiplySub213Float64x8 + OpMaskedFusedNegativeMultiplySub231Float64x8 + OpMaskedGreaterFloat64x8 + OpMaskedGreaterEqualFloat64x8 + OpMaskedIsNanFloat64x8 + OpMaskedLessFloat64x8 + OpMaskedLessEqualFloat64x8 + OpMaskedMaxFloat64x8 + OpMaskedMinFloat64x8 + OpMaskedMulFloat64x8 + OpMaskedMulByPowOf2Float64x8 + OpMaskedNotEqualFloat64x8 + OpMaskedOrFloat64x8 + OpMaskedSqrtFloat64x8 + OpMaskedSubFloat64x8 + OpMaskedXorFloat64x8 + OpMaxFloat64x8 + OpMinFloat64x8 + OpMulFloat64x8 + OpMulByPowOf2Float64x8 + OpNotEqualFloat64x8 + OpOrFloat64x8 + OpSqrtFloat64x8 + OpSubFloat64x8 + OpXorFloat64x8 + OpAbsoluteInt16x16 + OpAddInt16x16 + OpAndInt16x16 + OpAndNotInt16x16 + OpEqualInt16x16 + OpGreaterInt16x16 + OpGreaterEqualInt16x16 + OpLessInt16x16 + OpLessEqualInt16x16 + OpMaskedAbsoluteInt16x16 + OpMaskedAddInt16x16 + OpMaskedEqualInt16x16 + OpMaskedGreaterInt16x16 + OpMaskedGreaterEqualInt16x16 + OpMaskedLessInt16x16 + OpMaskedLessEqualInt16x16 + OpMaskedMaxInt16x16 + OpMaskedMinInt16x16 + OpMaskedMulHighInt16x16 + OpMaskedMulLowInt16x16 + OpMaskedNotEqualInt16x16 + OpMaskedPairDotProdInt16x16 + OpMaskedPopCountInt16x16 + OpMaskedSaturatedAddInt16x16 + OpMaskedSaturatedSubInt16x16 + OpMaskedSubInt16x16 + OpMaxInt16x16 + OpMinInt16x16 + OpMulHighInt16x16 + OpMulLowInt16x16 + OpNotEqualInt16x16 + OpOrInt16x16 + OpPairDotProdInt16x16 + OpPairwiseAddInt16x16 + OpPairwiseSubInt16x16 + OpPopCountInt16x16 + OpSaturatedAddInt16x16 + OpSaturatedPairwiseAddInt16x16 + OpSaturatedPairwiseSubInt16x16 + OpSaturatedSubInt16x16 + OpSignInt16x16 + OpSubInt16x16 + OpXorInt16x16 + OpAbsoluteInt16x32 + OpAddInt16x32 + OpEqualInt16x32 + OpGreaterInt16x32 + OpGreaterEqualInt16x32 + OpLessInt16x32 + OpLessEqualInt16x32 + OpMaskedAbsoluteInt16x32 + OpMaskedAddInt16x32 + OpMaskedEqualInt16x32 + OpMaskedGreaterInt16x32 + OpMaskedGreaterEqualInt16x32 + OpMaskedLessInt16x32 + OpMaskedLessEqualInt16x32 + OpMaskedMaxInt16x32 + OpMaskedMinInt16x32 + OpMaskedMulHighInt16x32 + OpMaskedMulLowInt16x32 + OpMaskedNotEqualInt16x32 + OpMaskedPairDotProdInt16x32 + OpMaskedPopCountInt16x32 + OpMaskedSaturatedAddInt16x32 + OpMaskedSaturatedSubInt16x32 + OpMaskedSubInt16x32 + OpMaxInt16x32 + OpMinInt16x32 + OpMulHighInt16x32 + OpMulLowInt16x32 + OpNotEqualInt16x32 + OpPairDotProdInt16x32 + OpPopCountInt16x32 + OpSaturatedAddInt16x32 + OpSaturatedSubInt16x32 + OpSubInt16x32 + OpAbsoluteInt16x8 + OpAddInt16x8 + OpAndInt16x8 + OpAndNotInt16x8 + OpEqualInt16x8 + OpGreaterInt16x8 + OpGreaterEqualInt16x8 + OpLessInt16x8 + OpLessEqualInt16x8 + OpMaskedAbsoluteInt16x8 + OpMaskedAddInt16x8 + OpMaskedEqualInt16x8 + OpMaskedGreaterInt16x8 + OpMaskedGreaterEqualInt16x8 + OpMaskedLessInt16x8 + OpMaskedLessEqualInt16x8 + OpMaskedMaxInt16x8 + OpMaskedMinInt16x8 + OpMaskedMulHighInt16x8 + OpMaskedMulLowInt16x8 + OpMaskedNotEqualInt16x8 + OpMaskedPairDotProdInt16x8 + OpMaskedPopCountInt16x8 + OpMaskedSaturatedAddInt16x8 + OpMaskedSaturatedSubInt16x8 + OpMaskedSubInt16x8 + OpMaxInt16x8 + OpMinInt16x8 + OpMulHighInt16x8 + OpMulLowInt16x8 + OpNotEqualInt16x8 + OpOrInt16x8 + OpPairDotProdInt16x8 + OpPairwiseAddInt16x8 + OpPairwiseSubInt16x8 + OpPopCountInt16x8 + OpSaturatedAddInt16x8 + OpSaturatedPairwiseAddInt16x8 + OpSaturatedPairwiseSubInt16x8 + OpSaturatedSubInt16x8 + OpSignInt16x8 + OpSubInt16x8 + OpXorInt16x8 + OpAbsoluteInt32x16 + OpAddInt32x16 + OpAndInt32x16 + OpAndNotInt32x16 + OpEqualInt32x16 + OpGreaterInt32x16 + OpGreaterEqualInt32x16 + OpLessInt32x16 + OpLessEqualInt32x16 + OpMaskedAbsoluteInt32x16 + OpMaskedAddInt32x16 + OpMaskedAndInt32x16 + OpMaskedAndNotInt32x16 + OpMaskedEqualInt32x16 + OpMaskedGreaterInt32x16 + OpMaskedGreaterEqualInt32x16 + OpMaskedLessInt32x16 + OpMaskedLessEqualInt32x16 + OpMaskedMaxInt32x16 + OpMaskedMinInt32x16 + OpMaskedMulLowInt32x16 + OpMaskedNotEqualInt32x16 + OpMaskedOrInt32x16 + OpMaskedPairDotProdAccumulateInt32x16 + OpMaskedPopCountInt32x16 + OpMaskedSaturatedPairDotProdAccumulateInt32x16 + OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 + OpMaskedSubInt32x16 + OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x16 + OpMaskedXorInt32x16 + OpMaxInt32x16 + OpMinInt32x16 + OpMulLowInt32x16 + OpNotEqualInt32x16 + OpOrInt32x16 + OpPairDotProdAccumulateInt32x16 + OpPopCountInt32x16 + OpSaturatedPairDotProdAccumulateInt32x16 + OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 + OpSubInt32x16 + OpUnsignedSignedQuadDotProdAccumulateInt32x16 + OpXorInt32x16 + OpAbsoluteInt32x4 + OpAddInt32x4 + OpAndInt32x4 + OpAndNotInt32x4 + OpEqualInt32x4 + OpGreaterInt32x4 + OpGreaterEqualInt32x4 + OpLessInt32x4 + OpLessEqualInt32x4 + OpMaskedAbsoluteInt32x4 + OpMaskedAddInt32x4 + OpMaskedAndInt32x4 + OpMaskedAndNotInt32x4 + OpMaskedEqualInt32x4 + OpMaskedGreaterInt32x4 + OpMaskedGreaterEqualInt32x4 + OpMaskedLessInt32x4 + OpMaskedLessEqualInt32x4 + OpMaskedMaxInt32x4 + OpMaskedMinInt32x4 + OpMaskedMulLowInt32x4 + OpMaskedNotEqualInt32x4 + OpMaskedOrInt32x4 + OpMaskedPairDotProdAccumulateInt32x4 + OpMaskedPopCountInt32x4 + OpMaskedSaturatedPairDotProdAccumulateInt32x4 + OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 + OpMaskedSubInt32x4 + OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x4 + OpMaskedXorInt32x4 + OpMaxInt32x4 + OpMinInt32x4 + OpMulEvenWidenInt32x4 + OpMulLowInt32x4 + OpNotEqualInt32x4 + OpOrInt32x4 + OpPairDotProdAccumulateInt32x4 + OpPairwiseAddInt32x4 + OpPairwiseSubInt32x4 + OpPopCountInt32x4 + OpSaturatedPairDotProdAccumulateInt32x4 + OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 + OpSignInt32x4 + OpSubInt32x4 + OpUnsignedSignedQuadDotProdAccumulateInt32x4 + OpXorInt32x4 + OpAbsoluteInt32x8 + OpAddInt32x8 + OpAndInt32x8 + OpAndNotInt32x8 + OpEqualInt32x8 + OpGreaterInt32x8 + OpGreaterEqualInt32x8 + OpLessInt32x8 + OpLessEqualInt32x8 + OpMaskedAbsoluteInt32x8 + OpMaskedAddInt32x8 + OpMaskedAndInt32x8 + OpMaskedAndNotInt32x8 + OpMaskedEqualInt32x8 + OpMaskedGreaterInt32x8 + OpMaskedGreaterEqualInt32x8 + OpMaskedLessInt32x8 + OpMaskedLessEqualInt32x8 + OpMaskedMaxInt32x8 + OpMaskedMinInt32x8 + OpMaskedMulLowInt32x8 + OpMaskedNotEqualInt32x8 + OpMaskedOrInt32x8 + OpMaskedPairDotProdAccumulateInt32x8 + OpMaskedPopCountInt32x8 + OpMaskedSaturatedPairDotProdAccumulateInt32x8 + OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 + OpMaskedSubInt32x8 + OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x8 + OpMaskedXorInt32x8 + OpMaxInt32x8 + OpMinInt32x8 + OpMulEvenWidenInt32x8 + OpMulLowInt32x8 + OpNotEqualInt32x8 + OpOrInt32x8 + OpPairDotProdAccumulateInt32x8 + OpPairwiseAddInt32x8 + OpPairwiseSubInt32x8 + OpPopCountInt32x8 + OpSaturatedPairDotProdAccumulateInt32x8 + OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 + OpSignInt32x8 + OpSubInt32x8 + OpUnsignedSignedQuadDotProdAccumulateInt32x8 + OpXorInt32x8 + OpAbsoluteInt64x2 + OpAddInt64x2 + OpAndInt64x2 + OpAndNotInt64x2 + OpEqualInt64x2 + OpGreaterInt64x2 + OpGreaterEqualInt64x2 + OpLessInt64x2 + OpLessEqualInt64x2 + OpMaskedAbsoluteInt64x2 + OpMaskedAddInt64x2 + OpMaskedAndInt64x2 + OpMaskedAndNotInt64x2 + OpMaskedEqualInt64x2 + OpMaskedGreaterInt64x2 + OpMaskedGreaterEqualInt64x2 + OpMaskedLessInt64x2 + OpMaskedLessEqualInt64x2 + OpMaskedMaxInt64x2 + OpMaskedMinInt64x2 + OpMaskedMulEvenWidenInt64x2 + OpMaskedMulLowInt64x2 + OpMaskedNotEqualInt64x2 + OpMaskedOrInt64x2 + OpMaskedPopCountInt64x2 + OpMaskedSubInt64x2 + OpMaskedXorInt64x2 + OpMaxInt64x2 + OpMinInt64x2 + OpMulEvenWidenInt64x2 + OpMulLowInt64x2 + OpNotEqualInt64x2 + OpOrInt64x2 + OpPopCountInt64x2 + OpSubInt64x2 + OpXorInt64x2 + OpAbsoluteInt64x4 + OpAddInt64x4 + OpAndInt64x4 + OpAndNotInt64x4 + OpEqualInt64x4 + OpGreaterInt64x4 + OpGreaterEqualInt64x4 + OpLessInt64x4 + OpLessEqualInt64x4 + OpMaskedAbsoluteInt64x4 + OpMaskedAddInt64x4 + OpMaskedAndInt64x4 + OpMaskedAndNotInt64x4 + OpMaskedEqualInt64x4 + OpMaskedGreaterInt64x4 + OpMaskedGreaterEqualInt64x4 + OpMaskedLessInt64x4 + OpMaskedLessEqualInt64x4 + OpMaskedMaxInt64x4 + OpMaskedMinInt64x4 + OpMaskedMulEvenWidenInt64x4 + OpMaskedMulLowInt64x4 + OpMaskedNotEqualInt64x4 + OpMaskedOrInt64x4 + OpMaskedPopCountInt64x4 + OpMaskedSubInt64x4 + OpMaskedXorInt64x4 + OpMaxInt64x4 + OpMinInt64x4 + OpMulEvenWidenInt64x4 + OpMulLowInt64x4 + OpNotEqualInt64x4 + OpOrInt64x4 + OpPopCountInt64x4 + OpSubInt64x4 + OpXorInt64x4 + OpAbsoluteInt64x8 + OpAddInt64x8 + OpAndInt64x8 + OpAndNotInt64x8 + OpEqualInt64x8 + OpGreaterInt64x8 + OpGreaterEqualInt64x8 + OpLessInt64x8 + OpLessEqualInt64x8 + OpMaskedAbsoluteInt64x8 + OpMaskedAddInt64x8 + OpMaskedAndInt64x8 + OpMaskedAndNotInt64x8 + OpMaskedEqualInt64x8 + OpMaskedGreaterInt64x8 + OpMaskedGreaterEqualInt64x8 + OpMaskedLessInt64x8 + OpMaskedLessEqualInt64x8 + OpMaskedMaxInt64x8 + OpMaskedMinInt64x8 + OpMaskedMulEvenWidenInt64x8 + OpMaskedMulLowInt64x8 + OpMaskedNotEqualInt64x8 + OpMaskedOrInt64x8 + OpMaskedPopCountInt64x8 + OpMaskedSubInt64x8 + OpMaskedXorInt64x8 + OpMaxInt64x8 + OpMinInt64x8 + OpMulEvenWidenInt64x8 + OpMulLowInt64x8 + OpNotEqualInt64x8 + OpOrInt64x8 + OpPopCountInt64x8 + OpSubInt64x8 + OpXorInt64x8 + OpAbsoluteInt8x16 + OpAddInt8x16 + OpAndInt8x16 + OpAndNotInt8x16 + OpEqualInt8x16 + OpGreaterInt8x16 + OpGreaterEqualInt8x16 + OpLessInt8x16 + OpLessEqualInt8x16 + OpMaskedAbsoluteInt8x16 + OpMaskedAddInt8x16 + OpMaskedEqualInt8x16 + OpMaskedGreaterInt8x16 + OpMaskedGreaterEqualInt8x16 + OpMaskedLessInt8x16 + OpMaskedLessEqualInt8x16 + OpMaskedMaxInt8x16 + OpMaskedMinInt8x16 + OpMaskedNotEqualInt8x16 + OpMaskedPopCountInt8x16 + OpMaskedSaturatedAddInt8x16 + OpMaskedSaturatedSubInt8x16 + OpMaskedSubInt8x16 + OpMaxInt8x16 + OpMinInt8x16 + OpNotEqualInt8x16 + OpOrInt8x16 + OpPopCountInt8x16 + OpSaturatedAddInt8x16 + OpSaturatedSubInt8x16 + OpSignInt8x16 + OpSubInt8x16 + OpXorInt8x16 + OpAbsoluteInt8x32 + OpAddInt8x32 + OpAndInt8x32 + OpAndNotInt8x32 + OpEqualInt8x32 + OpGreaterInt8x32 + OpGreaterEqualInt8x32 + OpLessInt8x32 + OpLessEqualInt8x32 + OpMaskedAbsoluteInt8x32 + OpMaskedAddInt8x32 + OpMaskedEqualInt8x32 + OpMaskedGreaterInt8x32 + OpMaskedGreaterEqualInt8x32 + OpMaskedLessInt8x32 + OpMaskedLessEqualInt8x32 + OpMaskedMaxInt8x32 + OpMaskedMinInt8x32 + OpMaskedNotEqualInt8x32 + OpMaskedPopCountInt8x32 + OpMaskedSaturatedAddInt8x32 + OpMaskedSaturatedSubInt8x32 + OpMaskedSubInt8x32 + OpMaxInt8x32 + OpMinInt8x32 + OpNotEqualInt8x32 + OpOrInt8x32 + OpPopCountInt8x32 + OpSaturatedAddInt8x32 + OpSaturatedSubInt8x32 + OpSignInt8x32 + OpSubInt8x32 + OpXorInt8x32 + OpAbsoluteInt8x64 + OpAddInt8x64 + OpEqualInt8x64 + OpGreaterInt8x64 + OpGreaterEqualInt8x64 + OpLessInt8x64 + OpLessEqualInt8x64 + OpMaskedAbsoluteInt8x64 + OpMaskedAddInt8x64 + OpMaskedEqualInt8x64 + OpMaskedGreaterInt8x64 + OpMaskedGreaterEqualInt8x64 + OpMaskedLessInt8x64 + OpMaskedLessEqualInt8x64 + OpMaskedMaxInt8x64 + OpMaskedMinInt8x64 + OpMaskedNotEqualInt8x64 + OpMaskedPopCountInt8x64 + OpMaskedSaturatedAddInt8x64 + OpMaskedSaturatedSubInt8x64 + OpMaskedSubInt8x64 + OpMaxInt8x64 + OpMinInt8x64 + OpNotEqualInt8x64 + OpPopCountInt8x64 + OpSaturatedAddInt8x64 + OpSaturatedSubInt8x64 + OpSubInt8x64 + OpAddUint16x16 + OpAndUint16x16 + OpAndNotUint16x16 + OpAverageUint16x16 + OpEqualUint16x16 + OpGreaterUint16x16 + OpGreaterEqualUint16x16 + OpLessUint16x16 + OpLessEqualUint16x16 + OpMaskedAddUint16x16 + OpMaskedAverageUint16x16 + OpMaskedEqualUint16x16 + OpMaskedGreaterUint16x16 + OpMaskedGreaterEqualUint16x16 + OpMaskedLessUint16x16 + OpMaskedLessEqualUint16x16 + OpMaskedMaxUint16x16 + OpMaskedMinUint16x16 + OpMaskedMulHighUint16x16 + OpMaskedNotEqualUint16x16 + OpMaskedPopCountUint16x16 + OpMaskedSaturatedAddUint16x16 + OpMaskedSaturatedSubUint16x16 + OpMaskedSaturatedUnsignedSignedPairDotProdUint16x16 + OpMaskedSubUint16x16 + OpMaxUint16x16 + OpMinUint16x16 + OpMulHighUint16x16 + OpNotEqualUint16x16 + OpOrUint16x16 + OpPairwiseAddUint16x16 + OpPairwiseSubUint16x16 + OpPopCountUint16x16 + OpSaturatedAddUint16x16 + OpSaturatedSubUint16x16 + OpSaturatedUnsignedSignedPairDotProdUint16x16 + OpSubUint16x16 + OpXorUint16x16 + OpAddUint16x32 + OpAverageUint16x32 + OpEqualUint16x32 + OpGreaterUint16x32 + OpGreaterEqualUint16x32 + OpLessUint16x32 + OpLessEqualUint16x32 + OpMaskedAddUint16x32 + OpMaskedAverageUint16x32 + OpMaskedEqualUint16x32 + OpMaskedGreaterUint16x32 + OpMaskedGreaterEqualUint16x32 + OpMaskedLessUint16x32 + OpMaskedLessEqualUint16x32 + OpMaskedMaxUint16x32 + OpMaskedMinUint16x32 + OpMaskedMulHighUint16x32 + OpMaskedNotEqualUint16x32 + OpMaskedPopCountUint16x32 + OpMaskedSaturatedAddUint16x32 + OpMaskedSaturatedSubUint16x32 + OpMaskedSaturatedUnsignedSignedPairDotProdUint16x32 + OpMaskedSubUint16x32 + OpMaxUint16x32 + OpMinUint16x32 + OpMulHighUint16x32 + OpNotEqualUint16x32 + OpPopCountUint16x32 + OpSaturatedAddUint16x32 + OpSaturatedSubUint16x32 + OpSaturatedUnsignedSignedPairDotProdUint16x32 + OpSubUint16x32 + OpAddUint16x8 + OpAndUint16x8 + OpAndNotUint16x8 + OpAverageUint16x8 + OpEqualUint16x8 + OpGreaterUint16x8 + OpGreaterEqualUint16x8 + OpLessUint16x8 + OpLessEqualUint16x8 + OpMaskedAddUint16x8 + OpMaskedAverageUint16x8 + OpMaskedEqualUint16x8 + OpMaskedGreaterUint16x8 + OpMaskedGreaterEqualUint16x8 + OpMaskedLessUint16x8 + OpMaskedLessEqualUint16x8 + OpMaskedMaxUint16x8 + OpMaskedMinUint16x8 + OpMaskedMulHighUint16x8 + OpMaskedNotEqualUint16x8 + OpMaskedPopCountUint16x8 + OpMaskedSaturatedAddUint16x8 + OpMaskedSaturatedSubUint16x8 + OpMaskedSaturatedUnsignedSignedPairDotProdUint16x8 + OpMaskedSubUint16x8 + OpMaxUint16x8 + OpMinUint16x8 + OpMulHighUint16x8 + OpNotEqualUint16x8 + OpOrUint16x8 + OpPairwiseAddUint16x8 + OpPairwiseSubUint16x8 + OpPopCountUint16x8 + OpSaturatedAddUint16x8 + OpSaturatedSubUint16x8 + OpSaturatedUnsignedSignedPairDotProdUint16x8 + OpSubUint16x8 + OpXorUint16x8 + OpAddUint32x16 + OpAndUint32x16 + OpAndNotUint32x16 + OpEqualUint32x16 + OpGreaterUint32x16 + OpGreaterEqualUint32x16 + OpLessUint32x16 + OpLessEqualUint32x16 + OpMaskedAddUint32x16 + OpMaskedAndUint32x16 + OpMaskedAndNotUint32x16 + OpMaskedEqualUint32x16 + OpMaskedGreaterUint32x16 + OpMaskedGreaterEqualUint32x16 + OpMaskedLessUint32x16 + OpMaskedLessEqualUint32x16 + OpMaskedMaxUint32x16 + OpMaskedMinUint32x16 + OpMaskedNotEqualUint32x16 + OpMaskedOrUint32x16 + OpMaskedPopCountUint32x16 + OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 + OpMaskedSubUint32x16 + OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x16 + OpMaskedXorUint32x16 + OpMaxUint32x16 + OpMinUint32x16 + OpNotEqualUint32x16 + OpOrUint32x16 + OpPopCountUint32x16 + OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 + OpSubUint32x16 + OpUnsignedSignedQuadDotProdAccumulateUint32x16 + OpXorUint32x16 + OpAddUint32x4 + OpAndUint32x4 + OpAndNotUint32x4 + OpEqualUint32x4 + OpGreaterUint32x4 + OpGreaterEqualUint32x4 + OpLessUint32x4 + OpLessEqualUint32x4 + OpMaskedAddUint32x4 + OpMaskedAndUint32x4 + OpMaskedAndNotUint32x4 + OpMaskedEqualUint32x4 + OpMaskedGreaterUint32x4 + OpMaskedGreaterEqualUint32x4 + OpMaskedLessUint32x4 + OpMaskedLessEqualUint32x4 + OpMaskedMaxUint32x4 + OpMaskedMinUint32x4 + OpMaskedNotEqualUint32x4 + OpMaskedOrUint32x4 + OpMaskedPopCountUint32x4 + OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 + OpMaskedSubUint32x4 + OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4 + OpMaskedXorUint32x4 + OpMaxUint32x4 + OpMinUint32x4 + OpMulEvenWidenUint32x4 + OpNotEqualUint32x4 + OpOrUint32x4 + OpPairwiseAddUint32x4 + OpPairwiseSubUint32x4 + OpPopCountUint32x4 + OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 + OpSubUint32x4 + OpUnsignedSignedQuadDotProdAccumulateUint32x4 + OpXorUint32x4 + OpAddUint32x8 + OpAndUint32x8 + OpAndNotUint32x8 + OpEqualUint32x8 + OpGreaterUint32x8 + OpGreaterEqualUint32x8 + OpLessUint32x8 + OpLessEqualUint32x8 + OpMaskedAddUint32x8 + OpMaskedAndUint32x8 + OpMaskedAndNotUint32x8 + OpMaskedEqualUint32x8 + OpMaskedGreaterUint32x8 + OpMaskedGreaterEqualUint32x8 + OpMaskedLessUint32x8 + OpMaskedLessEqualUint32x8 + OpMaskedMaxUint32x8 + OpMaskedMinUint32x8 + OpMaskedNotEqualUint32x8 + OpMaskedOrUint32x8 + OpMaskedPopCountUint32x8 + OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 + OpMaskedSubUint32x8 + OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8 + OpMaskedXorUint32x8 + OpMaxUint32x8 + OpMinUint32x8 + OpMulEvenWidenUint32x8 + OpNotEqualUint32x8 + OpOrUint32x8 + OpPairwiseAddUint32x8 + OpPairwiseSubUint32x8 + OpPopCountUint32x8 + OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 + OpSubUint32x8 + OpUnsignedSignedQuadDotProdAccumulateUint32x8 + OpXorUint32x8 + OpAddUint64x2 + OpAndUint64x2 + OpAndNotUint64x2 + OpEqualUint64x2 + OpGreaterUint64x2 + OpGreaterEqualUint64x2 + OpLessUint64x2 + OpLessEqualUint64x2 + OpMaskedAddUint64x2 + OpMaskedAndUint64x2 + OpMaskedAndNotUint64x2 + OpMaskedEqualUint64x2 + OpMaskedGreaterUint64x2 + OpMaskedGreaterEqualUint64x2 + OpMaskedLessUint64x2 + OpMaskedLessEqualUint64x2 + OpMaskedMaxUint64x2 + OpMaskedMinUint64x2 + OpMaskedMulEvenWidenUint64x2 + OpMaskedNotEqualUint64x2 + OpMaskedOrUint64x2 + OpMaskedPopCountUint64x2 + OpMaskedSubUint64x2 + OpMaskedXorUint64x2 + OpMaxUint64x2 + OpMinUint64x2 + OpMulEvenWidenUint64x2 + OpNotEqualUint64x2 + OpOrUint64x2 + OpPopCountUint64x2 + OpSubUint64x2 + OpXorUint64x2 + OpAddUint64x4 + OpAndUint64x4 + OpAndNotUint64x4 + OpEqualUint64x4 + OpGreaterUint64x4 + OpGreaterEqualUint64x4 + OpLessUint64x4 + OpLessEqualUint64x4 + OpMaskedAddUint64x4 + OpMaskedAndUint64x4 + OpMaskedAndNotUint64x4 + OpMaskedEqualUint64x4 + OpMaskedGreaterUint64x4 + OpMaskedGreaterEqualUint64x4 + OpMaskedLessUint64x4 + OpMaskedLessEqualUint64x4 + OpMaskedMaxUint64x4 + OpMaskedMinUint64x4 + OpMaskedMulEvenWidenUint64x4 + OpMaskedNotEqualUint64x4 + OpMaskedOrUint64x4 + OpMaskedPopCountUint64x4 + OpMaskedSubUint64x4 + OpMaskedXorUint64x4 + OpMaxUint64x4 + OpMinUint64x4 + OpMulEvenWidenUint64x4 + OpNotEqualUint64x4 + OpOrUint64x4 + OpPopCountUint64x4 + OpSubUint64x4 + OpXorUint64x4 + OpAddUint64x8 + OpAndUint64x8 + OpAndNotUint64x8 + OpEqualUint64x8 + OpGreaterUint64x8 + OpGreaterEqualUint64x8 + OpLessUint64x8 + OpLessEqualUint64x8 + OpMaskedAddUint64x8 + OpMaskedAndUint64x8 + OpMaskedAndNotUint64x8 + OpMaskedEqualUint64x8 + OpMaskedGreaterUint64x8 + OpMaskedGreaterEqualUint64x8 + OpMaskedLessUint64x8 + OpMaskedLessEqualUint64x8 + OpMaskedMaxUint64x8 + OpMaskedMinUint64x8 + OpMaskedMulEvenWidenUint64x8 + OpMaskedNotEqualUint64x8 + OpMaskedOrUint64x8 + OpMaskedPopCountUint64x8 + OpMaskedSubUint64x8 + OpMaskedXorUint64x8 + OpMaxUint64x8 + OpMinUint64x8 + OpMulEvenWidenUint64x8 + OpNotEqualUint64x8 + OpOrUint64x8 + OpPopCountUint64x8 + OpSubUint64x8 + OpXorUint64x8 + OpAddUint8x16 + OpAndUint8x16 + OpAndNotUint8x16 + OpAverageUint8x16 + OpEqualUint8x16 + OpGreaterUint8x16 + OpGreaterEqualUint8x16 + OpLessUint8x16 + OpLessEqualUint8x16 + OpMaskedAddUint8x16 + OpMaskedAverageUint8x16 + OpMaskedEqualUint8x16 + OpMaskedGreaterUint8x16 + OpMaskedGreaterEqualUint8x16 + OpMaskedLessUint8x16 + OpMaskedLessEqualUint8x16 + OpMaskedMaxUint8x16 + OpMaskedMinUint8x16 + OpMaskedNotEqualUint8x16 + OpMaskedPopCountUint8x16 + OpMaskedSaturatedAddUint8x16 + OpMaskedSaturatedSubUint8x16 + OpMaskedSubUint8x16 + OpMaxUint8x16 + OpMinUint8x16 + OpNotEqualUint8x16 + OpOrUint8x16 + OpPopCountUint8x16 + OpSaturatedAddUint8x16 + OpSaturatedSubUint8x16 + OpSaturatedUnsignedSignedPairDotProdUint8x16 + OpSubUint8x16 + OpXorUint8x16 + OpAddUint8x32 + OpAndUint8x32 + OpAndNotUint8x32 + OpAverageUint8x32 + OpEqualUint8x32 + OpGreaterUint8x32 + OpGreaterEqualUint8x32 + OpLessUint8x32 + OpLessEqualUint8x32 + OpMaskedAddUint8x32 + OpMaskedAverageUint8x32 + OpMaskedEqualUint8x32 + OpMaskedGreaterUint8x32 + OpMaskedGreaterEqualUint8x32 + OpMaskedLessUint8x32 + OpMaskedLessEqualUint8x32 + OpMaskedMaxUint8x32 + OpMaskedMinUint8x32 + OpMaskedNotEqualUint8x32 + OpMaskedPopCountUint8x32 + OpMaskedSaturatedAddUint8x32 + OpMaskedSaturatedSubUint8x32 + OpMaskedSubUint8x32 + OpMaxUint8x32 + OpMinUint8x32 + OpNotEqualUint8x32 + OpOrUint8x32 + OpPopCountUint8x32 + OpSaturatedAddUint8x32 + OpSaturatedSubUint8x32 + OpSaturatedUnsignedSignedPairDotProdUint8x32 + OpSubUint8x32 + OpXorUint8x32 + OpAddUint8x64 + OpAverageUint8x64 + OpEqualUint8x64 + OpGreaterUint8x64 + OpGreaterEqualUint8x64 + OpLessUint8x64 + OpLessEqualUint8x64 + OpMaskedAddUint8x64 + OpMaskedAverageUint8x64 + OpMaskedEqualUint8x64 + OpMaskedGreaterUint8x64 + OpMaskedGreaterEqualUint8x64 + OpMaskedLessUint8x64 + OpMaskedLessEqualUint8x64 + OpMaskedMaxUint8x64 + OpMaskedMinUint8x64 + OpMaskedNotEqualUint8x64 + OpMaskedPopCountUint8x64 + OpMaskedSaturatedAddUint8x64 + OpMaskedSaturatedSubUint8x64 + OpMaskedSubUint8x64 + OpMaxUint8x64 + OpMinUint8x64 + OpNotEqualUint8x64 + OpPopCountUint8x64 + OpSaturatedAddUint8x64 + OpSaturatedSubUint8x64 + OpSubUint8x64 + OpCeilSuppressExceptionWithPrecisionFloat32x16 + OpCeilWithPrecisionFloat32x16 + OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x16 + OpDiffWithCeilWithPrecisionFloat32x16 + OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x16 + OpDiffWithFloorWithPrecisionFloat32x16 + OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x16 + OpDiffWithRoundWithPrecisionFloat32x16 + OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x16 + OpDiffWithTruncWithPrecisionFloat32x16 + OpFloorSuppressExceptionWithPrecisionFloat32x16 + OpFloorWithPrecisionFloat32x16 + OpMaskedCeilSuppressExceptionWithPrecisionFloat32x16 + OpMaskedCeilWithPrecisionFloat32x16 + OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16 + OpMaskedDiffWithCeilWithPrecisionFloat32x16 + OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16 + OpMaskedDiffWithFloorWithPrecisionFloat32x16 + OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16 + OpMaskedDiffWithRoundWithPrecisionFloat32x16 + OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16 + OpMaskedDiffWithTruncWithPrecisionFloat32x16 + OpMaskedFloorSuppressExceptionWithPrecisionFloat32x16 + OpMaskedFloorWithPrecisionFloat32x16 + OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16 + OpMaskedRoundWithPrecisionFloat32x16 + OpMaskedTruncSuppressExceptionWithPrecisionFloat32x16 + OpMaskedTruncWithPrecisionFloat32x16 + OpRoundSuppressExceptionWithPrecisionFloat32x16 + OpRoundWithPrecisionFloat32x16 + OpTruncSuppressExceptionWithPrecisionFloat32x16 + OpTruncWithPrecisionFloat32x16 + OpCeilSuppressExceptionWithPrecisionFloat32x4 + OpCeilWithPrecisionFloat32x4 + OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x4 + OpDiffWithCeilWithPrecisionFloat32x4 + OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x4 + OpDiffWithFloorWithPrecisionFloat32x4 + OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x4 + OpDiffWithRoundWithPrecisionFloat32x4 + OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x4 + OpDiffWithTruncWithPrecisionFloat32x4 + OpFloorSuppressExceptionWithPrecisionFloat32x4 + OpFloorWithPrecisionFloat32x4 + OpMaskedCeilSuppressExceptionWithPrecisionFloat32x4 + OpMaskedCeilWithPrecisionFloat32x4 + OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4 + OpMaskedDiffWithCeilWithPrecisionFloat32x4 + OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4 + OpMaskedDiffWithFloorWithPrecisionFloat32x4 + OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4 + OpMaskedDiffWithRoundWithPrecisionFloat32x4 + OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4 + OpMaskedDiffWithTruncWithPrecisionFloat32x4 + OpMaskedFloorSuppressExceptionWithPrecisionFloat32x4 + OpMaskedFloorWithPrecisionFloat32x4 + OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4 + OpMaskedRoundWithPrecisionFloat32x4 + OpMaskedTruncSuppressExceptionWithPrecisionFloat32x4 + OpMaskedTruncWithPrecisionFloat32x4 + OpRoundSuppressExceptionWithPrecisionFloat32x4 + OpRoundWithPrecisionFloat32x4 + OpTruncSuppressExceptionWithPrecisionFloat32x4 + OpTruncWithPrecisionFloat32x4 + OpCeilSuppressExceptionWithPrecisionFloat32x8 + OpCeilWithPrecisionFloat32x8 + OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x8 + OpDiffWithCeilWithPrecisionFloat32x8 + OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x8 + OpDiffWithFloorWithPrecisionFloat32x8 + OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x8 + OpDiffWithRoundWithPrecisionFloat32x8 + OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x8 + OpDiffWithTruncWithPrecisionFloat32x8 + OpFloorSuppressExceptionWithPrecisionFloat32x8 + OpFloorWithPrecisionFloat32x8 + OpMaskedCeilSuppressExceptionWithPrecisionFloat32x8 + OpMaskedCeilWithPrecisionFloat32x8 + OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8 + OpMaskedDiffWithCeilWithPrecisionFloat32x8 + OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8 + OpMaskedDiffWithFloorWithPrecisionFloat32x8 + OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8 + OpMaskedDiffWithRoundWithPrecisionFloat32x8 + OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8 + OpMaskedDiffWithTruncWithPrecisionFloat32x8 + OpMaskedFloorSuppressExceptionWithPrecisionFloat32x8 + OpMaskedFloorWithPrecisionFloat32x8 + OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8 + OpMaskedRoundWithPrecisionFloat32x8 + OpMaskedTruncSuppressExceptionWithPrecisionFloat32x8 + OpMaskedTruncWithPrecisionFloat32x8 + OpRoundSuppressExceptionWithPrecisionFloat32x8 + OpRoundWithPrecisionFloat32x8 + OpTruncSuppressExceptionWithPrecisionFloat32x8 + OpTruncWithPrecisionFloat32x8 + OpCeilSuppressExceptionWithPrecisionFloat64x2 + OpCeilWithPrecisionFloat64x2 + OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x2 + OpDiffWithCeilWithPrecisionFloat64x2 + OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x2 + OpDiffWithFloorWithPrecisionFloat64x2 + OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x2 + OpDiffWithRoundWithPrecisionFloat64x2 + OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x2 + OpDiffWithTruncWithPrecisionFloat64x2 + OpFloorSuppressExceptionWithPrecisionFloat64x2 + OpFloorWithPrecisionFloat64x2 + OpMaskedCeilSuppressExceptionWithPrecisionFloat64x2 + OpMaskedCeilWithPrecisionFloat64x2 + OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2 + OpMaskedDiffWithCeilWithPrecisionFloat64x2 + OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2 + OpMaskedDiffWithFloorWithPrecisionFloat64x2 + OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2 + OpMaskedDiffWithRoundWithPrecisionFloat64x2 + OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2 + OpMaskedDiffWithTruncWithPrecisionFloat64x2 + OpMaskedFloorSuppressExceptionWithPrecisionFloat64x2 + OpMaskedFloorWithPrecisionFloat64x2 + OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2 + OpMaskedRoundWithPrecisionFloat64x2 + OpMaskedTruncSuppressExceptionWithPrecisionFloat64x2 + OpMaskedTruncWithPrecisionFloat64x2 + OpRoundSuppressExceptionWithPrecisionFloat64x2 + OpRoundWithPrecisionFloat64x2 + OpTruncSuppressExceptionWithPrecisionFloat64x2 + OpTruncWithPrecisionFloat64x2 + OpCeilSuppressExceptionWithPrecisionFloat64x4 + OpCeilWithPrecisionFloat64x4 + OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x4 + OpDiffWithCeilWithPrecisionFloat64x4 + OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x4 + OpDiffWithFloorWithPrecisionFloat64x4 + OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x4 + OpDiffWithRoundWithPrecisionFloat64x4 + OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x4 + OpDiffWithTruncWithPrecisionFloat64x4 + OpFloorSuppressExceptionWithPrecisionFloat64x4 + OpFloorWithPrecisionFloat64x4 + OpMaskedCeilSuppressExceptionWithPrecisionFloat64x4 + OpMaskedCeilWithPrecisionFloat64x4 + OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4 + OpMaskedDiffWithCeilWithPrecisionFloat64x4 + OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4 + OpMaskedDiffWithFloorWithPrecisionFloat64x4 + OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4 + OpMaskedDiffWithRoundWithPrecisionFloat64x4 + OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4 + OpMaskedDiffWithTruncWithPrecisionFloat64x4 + OpMaskedFloorSuppressExceptionWithPrecisionFloat64x4 + OpMaskedFloorWithPrecisionFloat64x4 + OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4 + OpMaskedRoundWithPrecisionFloat64x4 + OpMaskedTruncSuppressExceptionWithPrecisionFloat64x4 + OpMaskedTruncWithPrecisionFloat64x4 + OpRoundSuppressExceptionWithPrecisionFloat64x4 + OpRoundWithPrecisionFloat64x4 + OpTruncSuppressExceptionWithPrecisionFloat64x4 + OpTruncWithPrecisionFloat64x4 + OpCeilSuppressExceptionWithPrecisionFloat64x8 + OpCeilWithPrecisionFloat64x8 + OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x8 + OpDiffWithCeilWithPrecisionFloat64x8 + OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x8 + OpDiffWithFloorWithPrecisionFloat64x8 + OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x8 + OpDiffWithRoundWithPrecisionFloat64x8 + OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x8 + OpDiffWithTruncWithPrecisionFloat64x8 + OpFloorSuppressExceptionWithPrecisionFloat64x8 + OpFloorWithPrecisionFloat64x8 + OpMaskedCeilSuppressExceptionWithPrecisionFloat64x8 + OpMaskedCeilWithPrecisionFloat64x8 + OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8 + OpMaskedDiffWithCeilWithPrecisionFloat64x8 + OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8 + OpMaskedDiffWithFloorWithPrecisionFloat64x8 + OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8 + OpMaskedDiffWithRoundWithPrecisionFloat64x8 + OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8 + OpMaskedDiffWithTruncWithPrecisionFloat64x8 + OpMaskedFloorSuppressExceptionWithPrecisionFloat64x8 + OpMaskedFloorWithPrecisionFloat64x8 + OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8 + OpMaskedRoundWithPrecisionFloat64x8 + OpMaskedTruncSuppressExceptionWithPrecisionFloat64x8 + OpMaskedTruncWithPrecisionFloat64x8 + OpRoundSuppressExceptionWithPrecisionFloat64x8 + OpRoundWithPrecisionFloat64x8 + OpTruncSuppressExceptionWithPrecisionFloat64x8 + OpTruncWithPrecisionFloat64x8 ) var opcodeTable = [...]opInfo{ @@ -6856,7 +9328,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -6872,7 +9344,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -6912,8 +9384,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -6929,8 +9401,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -6946,8 +9418,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -6963,8 +9435,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -6980,8 +9452,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVSS, reg: regInfo{ inputs: []inputInfo{ - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -6994,8 +9466,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVSD, reg: regInfo{ inputs: []inputInfo{ - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7008,9 +9480,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7023,9 +9495,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7038,9 +9510,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7053,9 +9525,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -7069,8 +9541,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7087,8 +9559,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7105,8 +9577,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7123,8 +9595,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7141,8 +9613,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMULSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7159,8 +9631,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMULSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7177,8 +9649,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVSS, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7195,8 +9667,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ADIVSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7213,9 +9685,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7232,9 +9704,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7251,9 +9723,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7270,9 +9742,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7289,9 +9761,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7308,9 +9780,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7327,9 +9799,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7346,9 +9818,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7365,9 +9837,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7384,9 +9856,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7403,9 +9875,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7422,9 +9894,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7441,9 +9913,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7460,9 +9932,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7479,9 +9951,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7498,9 +9970,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -7579,7 +10051,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -7593,7 +10065,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8227,7 +10699,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8241,7 +10713,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8321,7 +10793,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8335,7 +10807,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8415,7 +10887,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8429,7 +10901,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8530,8 +11002,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8544,8 +11016,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8558,8 +11030,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8572,8 +11044,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8586,7 +11058,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8599,7 +11071,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8612,7 +11084,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8625,7 +11097,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ACMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8638,9 +11110,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8654,9 +11126,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8669,9 +11141,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8685,9 +11157,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8700,9 +11172,9 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8716,9 +11188,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8732,9 +11204,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8747,8 +11219,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8762,8 +11234,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8776,8 +11248,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8791,8 +11263,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8805,8 +11277,8 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8820,8 +11292,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -8835,8 +11307,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9060,7 +11532,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ABTSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9074,7 +11546,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ABTRQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9088,7 +11560,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ABTCQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -9741,8 +12213,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9760,8 +12232,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9779,8 +12251,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9798,8 +12270,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9817,8 +12289,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9836,8 +12308,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9855,8 +12327,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9874,8 +12346,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9893,8 +12365,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9912,8 +12384,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9931,9 +12403,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9951,9 +12423,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9971,9 +12443,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -9991,9 +12463,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10011,9 +12483,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10031,9 +12503,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10051,9 +12523,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10071,9 +12543,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10091,9 +12563,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10111,9 +12583,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10131,9 +12603,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10151,9 +12623,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10171,9 +12643,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10191,9 +12663,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10211,9 +12683,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10231,9 +12703,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10251,9 +12723,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10271,9 +12743,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10291,9 +12763,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10311,9 +12783,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10331,9 +12803,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10351,9 +12823,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10371,9 +12843,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10391,9 +12863,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10411,9 +12883,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -10430,8 +12902,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10445,8 +12917,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10460,8 +12932,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10475,8 +12947,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10490,8 +12962,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10505,8 +12977,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AADDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10520,8 +12992,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASUBL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10535,8 +13007,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10550,8 +13022,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10565,8 +13037,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXORL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10580,9 +13052,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10596,9 +13068,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10612,9 +13084,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10628,9 +13100,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10644,9 +13116,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10660,9 +13132,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10676,9 +13148,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10692,9 +13164,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10708,9 +13180,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10724,9 +13196,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10740,9 +13212,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10756,9 +13228,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10772,9 +13244,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10788,9 +13260,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10804,9 +13276,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10820,9 +13292,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10836,9 +13308,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10852,9 +13324,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10868,9 +13340,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10884,9 +13356,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10900,9 +13372,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10916,9 +13388,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10932,9 +13404,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10948,9 +13420,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10964,9 +13436,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10980,8 +13452,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -10995,8 +13467,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11010,8 +13482,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11025,8 +13497,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11040,8 +13512,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11055,8 +13527,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11070,8 +13542,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11085,8 +13557,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11100,8 +13572,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11115,8 +13587,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11130,8 +13602,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11145,8 +13617,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11160,8 +13632,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11175,8 +13647,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11190,8 +13662,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11205,8 +13677,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11220,8 +13692,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11235,8 +13707,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11250,8 +13722,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -11265,8 +13737,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12342,7 +14814,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12355,7 +14827,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETNE, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12368,7 +14840,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETLT, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12381,7 +14853,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETLE, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12394,7 +14866,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETGT, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12407,7 +14879,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETGE, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12420,7 +14892,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETCS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12433,7 +14905,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETLS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12446,7 +14918,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETHI, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12459,7 +14931,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ASETCC, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12473,8 +14945,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12488,8 +14960,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12503,8 +14975,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12518,8 +14990,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12533,8 +15005,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12548,8 +15020,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12563,8 +15035,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12578,8 +15050,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12593,8 +15065,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12608,8 +15080,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -12998,7 +15470,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ALEAQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13014,7 +15486,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ALEAL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13030,7 +15502,7 @@ var opcodeTable = [...]opInfo{ asm: x86.ALEAW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13047,8 +15519,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13065,8 +15537,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13083,8 +15555,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13100,8 +15572,8 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13117,8 +15589,8 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13134,8 +15606,8 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13151,8 +15623,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13168,8 +15640,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13185,8 +15657,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13202,8 +15674,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13219,8 +15691,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13236,8 +15708,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13253,7 +15725,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13269,7 +15741,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13285,7 +15757,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVWLZX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13301,7 +15773,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVWQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13317,7 +15789,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13333,7 +15805,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVLQSX, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13349,7 +15821,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13365,8 +15837,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13379,8 +15851,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13393,8 +15865,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13407,8 +15879,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13421,7 +15893,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 @@ -13437,8 +15909,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ - {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 - {0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, }, }, @@ -13452,8 +15924,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13470,8 +15942,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13487,8 +15959,8 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13505,8 +15977,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13522,8 +15994,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13539,8 +16011,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13557,8 +16029,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13574,8 +16046,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -13592,9 +16064,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13608,9 +16080,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13623,9 +16095,9 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13639,9 +16111,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13654,9 +16126,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13669,9 +16141,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13685,9 +16157,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13700,9 +16172,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13715,7 +16187,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13728,7 +16200,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13741,7 +16213,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13754,7 +16226,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13767,7 +16239,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVUPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13781,8 +16253,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13796,8 +16268,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13810,8 +16282,8 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13825,8 +16297,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13839,8 +16311,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13854,8 +16326,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -13868,8 +16340,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14124,7 +16596,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14140,7 +16612,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14156,7 +16628,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14174,8 +16646,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXCHGB, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14193,8 +16665,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXCHGL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14212,8 +16684,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXCHGQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14232,8 +16704,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXADDL, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14252,8 +16724,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AXADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14325,8 +16797,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14341,8 +16813,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14357,8 +16829,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AANDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14373,8 +16845,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORB, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14389,8 +16861,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14405,8 +16877,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AORQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14509,7 +16981,7 @@ var opcodeTable = [...]opInfo{ asm: x86.APREFETCHT0, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14520,7 +16992,7 @@ var opcodeTable = [...]opInfo{ asm: x86.APREFETCHNTA, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14703,8 +17175,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBEW, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14717,7 +17189,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14733,8 +17205,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBEL, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14747,7 +17219,7 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14763,8 +17235,8 @@ var opcodeTable = [...]opInfo{ asm: x86.AMOVBEQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14778,8 +17250,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14795,8 +17267,8 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14812,8 +17284,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14830,8 +17302,8 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14847,8 +17319,8 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -14865,9 +17337,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14880,9 +17352,9 @@ var opcodeTable = [...]opInfo{ scale: 2, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14896,9 +17368,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14911,9 +17383,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14926,9 +17398,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14942,9 +17414,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -14957,9 +17429,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, }, }, @@ -15056,8 +17528,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASARXL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15073,8 +17545,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASARXQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15090,8 +17562,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHLXL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15107,8 +17579,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHLXQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15124,8 +17596,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHRXL, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15141,8 +17613,8 @@ var opcodeTable = [...]opInfo{ asm: x86.ASHRXQ, reg: regInfo{ inputs: []inputInfo{ - {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15159,9 +17631,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15178,9 +17650,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15197,9 +17669,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15216,9 +17688,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15235,9 +17707,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15254,9 +17726,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15273,9 +17745,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15292,9 +17764,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15311,9 +17783,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15330,9 +17802,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15349,9 +17821,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15368,9 +17840,9 @@ var opcodeTable = [...]opInfo{ scale: 4, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15387,9 +17859,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15406,9 +17878,9 @@ var opcodeTable = [...]opInfo{ scale: 1, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15425,9 +17897,9 @@ var opcodeTable = [...]opInfo{ scale: 8, reg: regInfo{ inputs: []inputInfo{ - {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 - {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 - {0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB + {2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 + {1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 + {0, 1099511693311}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB }, outputs: []outputInfo{ {0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15 @@ -15534,18859 +18006,20418 @@ var opcodeTable = [...]opInfo{ }, }, }, - { - name: "ADD", + name: "VPADDD4", argLen: 2, commutative: true, - asm: arm.AADD, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AADD, + name: "VMOVDQUload128", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUB", - argLen: 2, - asm: arm.ASUB, + name: "VMOVDQUstore128", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + }, + }, + { + name: "VMOVDQUload256", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASUB, + name: "VMOVDQUstore256", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + }, + }, + { + name: "VMOVDQUload512", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: x86.AVMOVDQU64, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSB", - argLen: 2, - asm: arm.ARSB, + name: "VMOVDQUstore512", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: x86.AVMOVDQU64, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {0, 1099511676927}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB + }, + }, + }, + { + name: "VPMOVMToVec8x16", + argLen: 1, + asm: x86.AVPMOVM2B, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ARSB, + name: "VPMOVMToVec8x32", + argLen: 1, + asm: x86.AVPMOVM2B, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: arm.AMUL, + name: "VPMOVMToVec8x64", + argLen: 1, + asm: x86.AVPMOVM2B, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "HMUL", - argLen: 2, - commutative: true, - asm: arm.AMULL, + name: "VPMOVMToVec16x8", + argLen: 1, + asm: x86.AVPMOVM2W, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "HMULU", - argLen: 2, - commutative: true, - asm: arm.AMULLU, + name: "VPMOVMToVec16x16", + argLen: 1, + asm: x86.AVPMOVM2W, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLudiv", - argLen: 2, - clobberFlags: true, + name: "VPMOVMToVec16x32", + argLen: 1, + asm: x86.AVPMOVM2W, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 1}, // R0 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, - clobbers: 20492, // R2 R3 R12 R14 outputs: []outputInfo{ - {0, 1}, // R0 - {1, 2}, // R1 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDS", - argLen: 2, - commutative: true, - asm: arm.AADD, + name: "VPMOVMToVec32x4", + argLen: 1, + asm: x86.AVPMOVM2D, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AADD, + name: "VPMOVMToVec32x8", + argLen: 1, + asm: x86.AVPMOVM2D, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADC", - argLen: 3, - commutative: true, - asm: arm.AADC, + name: "VPMOVMToVec32x16", + argLen: 1, + asm: x86.AVPMOVM2D, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCconst", - auxType: auxInt32, - argLen: 2, - asm: arm.AADC, + name: "VPMOVMToVec64x2", + argLen: 1, + asm: x86.AVPMOVM2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBS", - argLen: 2, - asm: arm.ASUB, + name: "VPMOVMToVec64x4", + argLen: 1, + asm: x86.AVPMOVM2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASUB, + name: "VPMOVMToVec64x8", + argLen: 1, + asm: x86.AVPMOVM2Q, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ARSB, + name: "VPMOVVec8x16ToM", + argLen: 1, + asm: x86.AVPMOVB2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBC", - argLen: 3, - asm: arm.ASBC, + name: "VPMOVVec8x32ToM", + argLen: 1, + asm: x86.AVPMOVB2M, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBCconst", - auxType: auxInt32, - argLen: 2, - asm: arm.ASBC, + name: "VPMOVVec8x64ToM", + argLen: 1, + asm: x86.AVPMOVB2M, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "RSCconst", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSC, + name: "VPMOVVec16x8ToM", + argLen: 1, + asm: x86.AVPMOVW2M, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULLU", - argLen: 2, - commutative: true, - asm: arm.AMULLU, + name: "VPMOVVec16x16ToM", + argLen: 1, + asm: x86.AVPMOVW2M, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULA", - argLen: 3, - asm: arm.AMULA, + name: "VPMOVVec16x32ToM", + argLen: 1, + asm: x86.AVPMOVW2M, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULS", - argLen: 3, - asm: arm.AMULS, + name: "VPMOVVec32x4ToM", + argLen: 1, + asm: x86.AVPMOVD2M, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDF", - argLen: 2, - commutative: true, - asm: arm.AADDF, + name: "VPMOVVec32x8ToM", + argLen: 1, + asm: x86.AVPMOVD2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDD", - argLen: 2, - commutative: true, - asm: arm.AADDD, + name: "VPMOVVec32x16ToM", + argLen: 1, + asm: x86.AVPMOVD2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBF", - argLen: 2, - asm: arm.ASUBF, + name: "VPMOVVec64x2ToM", + argLen: 1, + asm: x86.AVPMOVQ2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBD", - argLen: 2, - asm: arm.ASUBD, + name: "VPMOVVec64x4ToM", + argLen: 1, + asm: x86.AVPMOVQ2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULF", - argLen: 2, - commutative: true, - asm: arm.AMULF, + name: "VPMOVVec64x8ToM", + argLen: 1, + asm: x86.AVPMOVQ2M, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULD", - argLen: 2, - commutative: true, - asm: arm.AMULD, + name: "Zero128", + argLen: 0, + asm: x86.AVPXOR, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, + }, + }, + { + name: "Zero256", + argLen: 0, + asm: x86.AVPXOR, + reg: regInfo{ outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NMULF", + name: "Zero512", + argLen: 0, + asm: x86.AVPXORQ, + reg: regInfo{ + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, + }, + { + name: "VADDPS512", argLen: 2, commutative: true, - asm: arm.ANMULF, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NMULD", + name: "VANDPS512", argLen: 2, commutative: true, - asm: arm.ANMULD, + asm: x86.AVANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVF", + name: "VANDNPS512", argLen: 2, - asm: arm.ADIVF, + asm: x86.AVANDNPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: arm.ADIVD, + name: "VRCP14PS512", + argLen: 1, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULAF", - argLen: 3, - resultInArg0: true, - asm: arm.AMULAF, + name: "VRSQRT14PS512", + argLen: 1, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULAD", - argLen: 3, - resultInArg0: true, - asm: arm.AMULAD, + name: "VDIVPS512", + argLen: 2, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULSF", + name: "VFMADD132PS512", argLen: 3, resultInArg0: true, - asm: arm.AMULSF, + asm: x86.AVFMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULSD", + name: "VFMADD213PS512", argLen: 3, resultInArg0: true, - asm: arm.AMULSD, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMULAD", + name: "VFMADD231PS512", argLen: 3, resultInArg0: true, - asm: arm.AFMULAD, + asm: x86.AVFMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: arm.AAND, + name: "VFMADDSUB132PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AAND, + name: "VFMADDSUB213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: arm.AORR, + name: "VFMADDSUB231PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AORR, + name: "VFMSUB132PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: arm.AEOR, + name: "VFMSUB213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORconst", - auxType: auxInt32, - argLen: 1, - asm: arm.AEOR, + name: "VFMSUB231PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BIC", - argLen: 2, - asm: arm.ABIC, + name: "VFMSUBADD132PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ABIC, + name: "VFMSUBADD213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BFX", - auxType: auxInt32, - argLen: 1, - asm: arm.ABFX, + name: "VFMSUBADD231PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BFXU", - auxType: auxInt32, - argLen: 1, - asm: arm.ABFXU, + name: "VFNMADD132PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVN", - argLen: 1, - asm: arm.AMVN, + name: "VFNMADD213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGF", - argLen: 1, - asm: arm.ANEGF, + name: "VFNMADD231PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGD", - argLen: 1, - asm: arm.ANEGD, + name: "VFNMSUB132PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTD", - argLen: 1, - asm: arm.ASQRTD, + name: "VFNMSUB213PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: arm.ASQRTF, + name: "VFNMSUB231PS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ABSD", - argLen: 1, - asm: arm.AABSD, + name: "VADDPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZ", - argLen: 1, - asm: arm.ACLZ, + name: "VANDPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV", - argLen: 1, - asm: arm.AREV, + name: "VANDNPSMasked512", + argLen: 3, + asm: x86.AVANDNPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV16", - argLen: 1, - asm: arm.AREV16, + name: "VRCP14PSMasked512", + argLen: 2, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RBIT", - argLen: 1, - asm: arm.ARBIT, + name: "VRSQRT14PSMasked512", + argLen: 2, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", - argLen: 2, - asm: arm.ASLL, + name: "VDIVPSMasked512", + argLen: 3, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASLL, + name: "VFMADD132PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRL", - argLen: 2, - asm: arm.ASRL, + name: "VFMADD213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASRL, + name: "VFMADD231PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRA", - argLen: 2, - asm: arm.ASRA, + name: "VFMADDSUB132PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ASRA, + name: "VFMADDSUB213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRR", - argLen: 2, + name: "VFMADDSUB231PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRRconst", - auxType: auxInt32, - argLen: 1, + name: "VFMSUB132PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "VFMSUB213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "VFMSUB231PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "VFMSUBADD132PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VFMSUBADD213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VFMSUBADD231PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VFNMADD132PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VFNMADD213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VFNMADD231PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VFNMSUB132PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AAND, + name: "VFNMSUB213PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AAND, + name: "VFNMSUB231PSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AAND, + name: "VMAXPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AORR, + name: "VMINPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AORR, + name: "VMULPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AORR, + name: "VSCALEFPSMasked512", + argLen: 3, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "VORPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "VSQRTPSMasked512", + argLen: 2, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "VXORPSMasked512", + argLen: 3, + commutative: true, + asm: x86.AVXORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRR", - auxType: auxInt32, - argLen: 2, - asm: arm.AEOR, + name: "VMAXPS512", + argLen: 2, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ABIC, + name: "VMINPS512", + argLen: 2, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ABIC, + name: "VMULPS512", + argLen: 2, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ABIC, + name: "VSCALEFPS512", + argLen: 2, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftLL", - auxType: auxInt32, - argLen: 1, - asm: arm.AMVN, + name: "VORPS512", + argLen: 2, + commutative: true, + asm: x86.AVORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRL", - auxType: auxInt32, - argLen: 1, - asm: arm.AMVN, + name: "VSQRTPS512", + argLen: 1, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRA", - auxType: auxInt32, - argLen: 1, - asm: arm.AMVN, + name: "VXORPS512", + argLen: 2, + commutative: true, + asm: x86.AVXORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.AADC, + name: "VADDPS128", + argLen: 2, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.AADC, + name: "VADDSUBPS128", + argLen: 2, + asm: x86.AVADDSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.AADC, + name: "VANDPS128", + argLen: 2, + commutative: true, + asm: x86.AVANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.ASBC, + name: "VANDNPS128", + argLen: 2, + asm: x86.AVANDNPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.ASBC, + name: "VRCP14PS128", + argLen: 1, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.ASBC, + name: "VRSQRTPS128", + argLen: 1, + asm: x86.AVRSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.ARSC, + name: "VDIVPS128", + argLen: 2, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.ARSC, + name: "VFMADD132PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.ARSC, + name: "VFMADD213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "VFMADD231PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "VFMADDSUB132PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.AADD, + name: "VFMADDSUB213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VFMADDSUB231PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VFMSUB132PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ASUB, + name: "VFMSUB213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VFMSUB231PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VFMSUBADD132PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ARSB, + name: "VFMSUBADD213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftLLreg", - argLen: 3, - asm: arm.AADD, + name: "VFMSUBADD231PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRLreg", - argLen: 3, - asm: arm.AADD, + name: "VFNMADD132PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRAreg", - argLen: 3, - asm: arm.AADD, + name: "VFNMADD213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftLLreg", - argLen: 3, - asm: arm.ASUB, + name: "VFNMADD231PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftRLreg", - argLen: 3, - asm: arm.ASUB, + name: "VFNMSUB132PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftRAreg", - argLen: 3, - asm: arm.ASUB, + name: "VFNMSUB213PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftLLreg", - argLen: 3, - asm: arm.ARSB, + name: "VFNMSUB231PS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftRLreg", - argLen: 3, - asm: arm.ARSB, + name: "VADDPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBshiftRAreg", - argLen: 3, - asm: arm.ARSB, + name: "VANDPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftLLreg", + name: "VANDNPSMasked128", argLen: 3, - asm: arm.AAND, + asm: x86.AVANDNPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRLreg", - argLen: 3, - asm: arm.AAND, + name: "VRCP14PSMasked128", + argLen: 2, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRAreg", - argLen: 3, - asm: arm.AAND, + name: "VRSQRT14PSMasked128", + argLen: 2, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftLLreg", + name: "VDIVPSMasked128", argLen: 3, - asm: arm.AORR, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRLreg", - argLen: 3, - asm: arm.AORR, + name: "VFMADD132PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRAreg", - argLen: 3, - asm: arm.AORR, + name: "VFMADD213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftLLreg", - argLen: 3, - asm: arm.AEOR, + name: "VFMADD231PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRLreg", - argLen: 3, - asm: arm.AEOR, + name: "VFMADDSUB132PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRAreg", - argLen: 3, - asm: arm.AEOR, + name: "VFMADDSUB213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftLLreg", - argLen: 3, - asm: arm.ABIC, + name: "VFMADDSUB231PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRLreg", - argLen: 3, - asm: arm.ABIC, + name: "VFMSUB132PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRAreg", - argLen: 3, - asm: arm.ABIC, + name: "VFMSUB213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftLLreg", - argLen: 2, - asm: arm.AMVN, + name: "VFMSUB231PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRLreg", - argLen: 2, - asm: arm.AMVN, + name: "VFMSUBADD132PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRAreg", - argLen: 2, - asm: arm.AMVN, + name: "VFMSUBADD213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftLLreg", - argLen: 4, - asm: arm.AADC, + name: "VFMSUBADD231PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftRLreg", - argLen: 4, - asm: arm.AADC, + name: "VFNMADD132PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCshiftRAreg", - argLen: 4, - asm: arm.AADC, + name: "VFNMADD213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftLLreg", - argLen: 4, - asm: arm.ASBC, + name: "VFNMADD231PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftRLreg", - argLen: 4, - asm: arm.ASBC, + name: "VFNMSUB132PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCshiftRAreg", - argLen: 4, - asm: arm.ASBC, + name: "VFNMSUB213PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftLLreg", - argLen: 4, - asm: arm.ARSC, + name: "VFNMSUB231PSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftRLreg", - argLen: 4, - asm: arm.ARSC, + name: "VMAXPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSCshiftRAreg", - argLen: 4, - asm: arm.ARSC, + name: "VMINPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftLLreg", - argLen: 3, - asm: arm.AADD, + name: "VMULPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftRLreg", + name: "VSCALEFPSMasked128", argLen: 3, - asm: arm.AADD, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSshiftRAreg", - argLen: 3, - asm: arm.AADD, + name: "VORPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftLLreg", - argLen: 3, - asm: arm.ASUB, + name: "VSQRTPSMasked128", + argLen: 2, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftRLreg", - argLen: 3, - asm: arm.ASUB, + name: "VXORPSMasked128", + argLen: 3, + commutative: true, + asm: x86.AVXORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSshiftRAreg", - argLen: 3, - asm: arm.ASUB, + name: "VMAXPS128", + argLen: 2, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftLLreg", - argLen: 3, - asm: arm.ARSB, + name: "VMINPS128", + argLen: 2, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftRLreg", - argLen: 3, - asm: arm.ARSB, + name: "VMULPS128", + argLen: 2, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RSBSshiftRAreg", - argLen: 3, - asm: arm.ARSB, + name: "VSCALEFPS128", + argLen: 2, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMP", - argLen: 2, - asm: arm.ACMP, + name: "VORPS128", + argLen: 2, + commutative: true, + asm: x86.AVORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ACMP, + name: "VHADDPS128", + argLen: 2, + asm: x86.AVHADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMN", - argLen: 2, - commutative: true, - asm: arm.ACMN, + name: "VHSUBPS128", + argLen: 2, + asm: x86.AVHSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ACMN, + name: "VSQRTPS128", + argLen: 1, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TST", + name: "VXORPS128", argLen: 2, commutative: true, - asm: arm.ATST, + asm: x86.AVXORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ATST, + name: "VADDPS256", + argLen: 2, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQ", - argLen: 2, - commutative: true, - asm: arm.ATEQ, + name: "VADDSUBPS256", + argLen: 2, + asm: x86.AVADDSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQconst", - auxType: auxInt32, - argLen: 1, - asm: arm.ATEQ, + name: "VANDPS256", + argLen: 2, + commutative: true, + asm: x86.AVANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPF", + name: "VANDNPS256", argLen: 2, - asm: arm.ACMPF, + asm: x86.AVANDNPS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPD", - argLen: 2, - asm: arm.ACMPD, + name: "VRCP14PS256", + argLen: 1, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMP, + name: "VRSQRTPS256", + argLen: 1, + asm: x86.AVRSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMP, + name: "VDIVPS256", + argLen: 2, + asm: x86.AVDIVPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMP, + name: "VFMADD132PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMN, + name: "VFMADD213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMN, + name: "VFMADD231PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ACMN, + name: "VFMADDSUB132PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATST, + name: "VFMADDSUB213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATST, + name: "VFMADDSUB231PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ATST, + name: "VFMSUB132PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQshiftLL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATEQ, + name: "VFMSUB213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQshiftRL", - auxType: auxInt32, - argLen: 2, - asm: arm.ATEQ, + name: "VFMSUB231PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQshiftRA", - auxType: auxInt32, - argLen: 2, - asm: arm.ATEQ, + name: "VFMSUBADD132PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftLLreg", - argLen: 3, - asm: arm.ACMP, + name: "VFMSUBADD213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRLreg", - argLen: 3, - asm: arm.ACMP, + name: "VFMSUBADD231PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRAreg", - argLen: 3, - asm: arm.ACMP, + name: "VFNMADD132PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftLLreg", - argLen: 3, - asm: arm.ACMN, + name: "VFNMADD213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRLreg", - argLen: 3, - asm: arm.ACMN, + name: "VFNMADD231PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRAreg", - argLen: 3, - asm: arm.ACMN, + name: "VFNMSUB132PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftLLreg", - argLen: 3, - asm: arm.ATST, + name: "VFNMSUB213PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRLreg", - argLen: 3, - asm: arm.ATST, + name: "VFNMSUB231PS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRAreg", - argLen: 3, - asm: arm.ATST, + name: "VADDPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQshiftLLreg", - argLen: 3, - asm: arm.ATEQ, + name: "VANDPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVANDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TEQshiftRLreg", + name: "VANDNPSMasked256", argLen: 3, - asm: arm.ATEQ, + asm: x86.AVANDNPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - }, - }, - { - name: "TEQshiftRAreg", - argLen: 3, - asm: arm.ATEQ, - reg: regInfo{ - inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPF0", - argLen: 1, - asm: arm.ACMPF, + name: "VRCP14PSMasked256", + argLen: 2, + asm: x86.AVRCP14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPD0", - argLen: 1, - asm: arm.ACMPD, + name: "VRSQRT14PSMasked256", + argLen: 2, + asm: x86.AVRSQRT14PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - }, - }, - { - name: "MOVWconst", - auxType: auxInt32, - argLen: 0, - rematerializeable: true, - asm: arm.AMOVW, - reg: regInfo{ outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm.AMOVF, + name: "VDIVPSMasked256", + argLen: 3, + asm: x86.AVDIVPS, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm.AMOVD, + name: "VFMADD132PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD132PS, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: arm.AMOVW, + name: "VFMADD213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294975488}, // SP SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVB, + name: "VFMADD231PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVBU, + name: "VFMADDSUB132PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVH, + name: "VFMADDSUB213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVHU, + name: "VFMADDSUB231PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVW, + name: "VFMSUB132PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVF, + name: "VFMSUB213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm.AMOVD, + name: "VFMSUB231PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVB, + name: "VFMSUBADD132PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD132PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVH, + name: "VFMSUBADD213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVW, + name: "VFMSUBADD231PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD231PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVF, + name: "VFNMADD132PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD132PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm.AMOVD, + name: "VFNMADD213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD213PS, reg: regInfo{ inputs: []inputInfo{ - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: arm.AMOVW, + name: "VFNMADD231PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD231PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadshiftLL", - auxType: auxInt32, - argLen: 3, - asm: arm.AMOVW, + name: "VFNMSUB132PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB132PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadshiftRL", - auxType: auxInt32, - argLen: 3, - asm: arm.AMOVW, + name: "VFNMSUB213PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB213PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadshiftRA", - auxType: auxInt32, - argLen: 3, - asm: arm.AMOVW, + name: "VFNMSUB231PSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB231PS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUloadidx", - argLen: 3, - asm: arm.AMOVBU, + name: "VMAXPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBloadidx", - argLen: 3, - asm: arm.AMOVB, + name: "VMINPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUloadidx", - argLen: 3, - asm: arm.AMOVHU, + name: "VMULPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHloadidx", + name: "VSCALEFPSMasked256", argLen: 3, - asm: arm.AMOVH, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: arm.AMOVW, + name: "VORPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVORPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstoreshiftLL", - auxType: auxInt32, - argLen: 4, - asm: arm.AMOVW, + name: "VSQRTPSMasked256", + argLen: 2, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstoreshiftRL", - auxType: auxInt32, - argLen: 4, - asm: arm.AMOVW, + name: "VXORPSMasked256", + argLen: 3, + commutative: true, + asm: x86.AVXORPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstoreshiftRA", - auxType: auxInt32, - argLen: 4, - asm: arm.AMOVW, + name: "VMAXPS256", + argLen: 2, + commutative: true, + asm: x86.AVMAXPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: arm.AMOVB, + name: "VMINPS256", + argLen: 2, + commutative: true, + asm: x86.AVMINPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: arm.AMOVH, + name: "VMULPS256", + argLen: 2, + commutative: true, + asm: x86.AVMULPS, reg: regInfo{ inputs: []inputInfo{ - {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 - {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: arm.AMOVBS, + name: "VSCALEFPS256", + argLen: 2, + asm: x86.AVSCALEFPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: arm.AMOVBU, + name: "VORPS256", + argLen: 2, + commutative: true, + asm: x86.AVORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: arm.AMOVHS, + name: "VHADDPS256", + argLen: 2, + asm: x86.AVHADDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: arm.AMOVHU, + name: "VHSUBPS256", + argLen: 2, + asm: x86.AVHSUBPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWreg", + name: "VSQRTPS256", argLen: 1, - asm: arm.AMOVW, + asm: x86.AVSQRTPS, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWnop", - argLen: 1, - resultInArg0: true, + name: "VXORPS256", + argLen: 2, + commutative: true, + asm: x86.AVXORPS, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWF", - argLen: 1, - asm: arm.AMOVWF, + name: "VADDPD128", + argLen: 2, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWD", - argLen: 1, - asm: arm.AMOVWD, + name: "VADDSUBPD128", + argLen: 2, + asm: x86.AVADDSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUF", - argLen: 1, - asm: arm.AMOVWF, + name: "VANDPD128", + argLen: 2, + commutative: true, + asm: x86.AVANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUD", - argLen: 1, - asm: arm.AMOVWD, + name: "VANDNPD128", + argLen: 2, + asm: x86.AVANDNPD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFW", + name: "VRCP14PD128", argLen: 1, - asm: arm.AMOVFW, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDW", + name: "VRSQRT14PD128", argLen: 1, - asm: arm.AMOVDW, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFWU", - argLen: 1, - asm: arm.AMOVFW, + name: "VDIVPD128", + argLen: 2, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDWU", - argLen: 1, - asm: arm.AMOVDW, + name: "VFMADD132PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFD", - argLen: 1, - asm: arm.AMOVFD, + name: "VFMADD213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDF", - argLen: 1, - asm: arm.AMOVDF, + name: "VFMADD231PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMOVWHSconst", - auxType: auxInt32, - argLen: 2, + name: "VFMADDSUB132PD128", + argLen: 3, resultInArg0: true, - asm: arm.AMOVW, + asm: x86.AVFMADDSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMOVWLSconst", - auxType: auxInt32, - argLen: 2, + name: "VFMADDSUB213PD128", + argLen: 3, resultInArg0: true, - asm: arm.AMOVW, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAcond", - argLen: 3, - asm: arm.ASRA, + name: "VFMADDSUB231PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, + name: "VFMSUB132PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB132PD, reg: regInfo{ - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VFMSUB213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB213PD, reg: regInfo{ - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, + name: "VFMSUB231PD128", argLen: 3, - clobberFlags: true, - call: true, + resultInArg0: true, + asm: x86.AVFMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {1, 128}, // R7 - {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, + name: "VFMSUBADD132PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VFMSUBADD213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "Equal", - argLen: 1, + name: "VFMSUBADD231PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD231PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotEqual", - argLen: 1, + name: "VFNMADD132PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD132PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThan", - argLen: 1, + name: "VFNMADD213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD213PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqual", - argLen: 1, + name: "VFNMADD231PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD231PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterThan", - argLen: 1, + name: "VFNMSUB132PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB132PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqual", - argLen: 1, + name: "VFNMSUB213PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB213PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThanU", - argLen: 1, + name: "VFNMSUB231PD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB231PD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqualU", - argLen: 1, + name: "VADDPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterThanU", - argLen: 1, + name: "VANDPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVANDPD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqualU", - argLen: 1, + name: "VANDNPDMasked128", + argLen: 3, + asm: x86.AVANDNPD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, + name: "VRCP14PDMasked128", + argLen: 2, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 1}, // R0 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 20482, // R1 R12 R14 }, }, { - name: "DUFFCOPY", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VRSQRT14PDMasked128", + argLen: 2, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, + name: "VDIVPDMasked128", + argLen: 3, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 2, // R1 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VFMADD132PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 - {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VFMADD213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 128}, // R7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VFMADD231PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD231PD, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VFMADDSUB132PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB132PD, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VFMADDSUB213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VFMADDSUB231PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VFMSUB132PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // R0 - {1, 2}, // R1 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicExtendA", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VFMSUB213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // R4 - {1, 4}, // R2 - {2, 8}, // R3 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicExtendB", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VFMSUB231PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // R4 - {1, 2}, // R1 - {2, 4}, // R2 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicExtendC", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VFMSUBADD132PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // R4 - {1, 1}, // R0 - {2, 2}, // R1 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FlagConstant", - auxType: auxFlagConstant, - argLen: 0, - reg: regInfo{}, - }, - { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VFMSUBADD213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ - clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 256}, // R8 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, - { - name: "ADCSflags", - argLen: 3, - commutative: true, - asm: arm64.AADCS, + name: "VFMSUBADD231PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADCzerocarry", - argLen: 1, - asm: arm64.AADC, + name: "VFNMADD132PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD132PD, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADD", - argLen: 2, - commutative: true, - asm: arm64.AADD, + name: "VFNMADD213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AADD, + name: "VFNMADD231PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSconstflags", - auxType: auxInt64, - argLen: 1, - asm: arm64.AADDS, + name: "VFNMSUB132PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDSflags", - argLen: 2, - commutative: true, - asm: arm64.AADDS, + name: "VFNMSUB213PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUB", - argLen: 2, - asm: arm64.ASUB, + name: "VFNMSUB231PDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ASUB, + name: "VMAXPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SBCSflags", - argLen: 3, - asm: arm64.ASBCS, + name: "VMINPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBSflags", - argLen: 2, - asm: arm64.ASUBS, + name: "VMULPDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: arm64.AMUL, + name: "VSCALEFPDMasked128", + argLen: 3, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULW", - argLen: 2, + name: "VORPDMasked128", + argLen: 3, commutative: true, - asm: arm64.AMULW, + asm: x86.AVORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MNEG", - argLen: 2, - commutative: true, - asm: arm64.AMNEG, + name: "VSQRTPDMasked128", + argLen: 2, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MNEGW", - argLen: 2, + name: "VXORPDMasked128", + argLen: 3, commutative: true, - asm: arm64.AMNEGW, + asm: x86.AVXORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULH", + name: "VMAXPD128", argLen: 2, commutative: true, - asm: arm64.ASMULH, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UMULH", + name: "VMINPD128", argLen: 2, commutative: true, - asm: arm64.AUMULH, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULL", + name: "VMULPD128", argLen: 2, commutative: true, - asm: arm64.ASMULL, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UMULL", - argLen: 2, - commutative: true, - asm: arm64.AUMULL, + name: "VSCALEFPD128", + argLen: 2, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIV", - argLen: 2, - asm: arm64.ASDIV, + name: "VORPD128", + argLen: 2, + commutative: true, + asm: x86.AVORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UDIV", + name: "VHADDPD128", argLen: 2, - asm: arm64.AUDIV, + asm: x86.AVHADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVW", + name: "VHSUBPD128", argLen: 2, - asm: arm64.ASDIVW, + asm: x86.AVHSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UDIVW", - argLen: 2, - asm: arm64.AUDIVW, + name: "VSQRTPD128", + argLen: 1, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOD", - argLen: 2, - asm: arm64.AREM, + name: "VXORPD128", + argLen: 2, + commutative: true, + asm: x86.AVXORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UMOD", - argLen: 2, - asm: arm64.AUREM, + name: "VADDPD256", + argLen: 2, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MODW", + name: "VADDSUBPD256", argLen: 2, - asm: arm64.AREMW, + asm: x86.AVADDSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UMODW", - argLen: 2, - asm: arm64.AUREMW, + name: "VANDPD256", + argLen: 2, + commutative: true, + asm: x86.AVANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FADDS", - argLen: 2, - commutative: true, - asm: arm64.AFADDS, + name: "VANDNPD256", + argLen: 2, + asm: x86.AVANDNPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FADDD", - argLen: 2, - commutative: true, - asm: arm64.AFADDD, + name: "VRCP14PD256", + argLen: 1, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSUBS", - argLen: 2, - asm: arm64.AFSUBS, + name: "VRSQRT14PD256", + argLen: 1, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSUBD", + name: "VDIVPD256", argLen: 2, - asm: arm64.AFSUBD, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - asm: arm64.AFMULS, + name: "VFMADD132PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMULD", - argLen: 2, - commutative: true, - asm: arm64.AFMULD, + name: "VFMADD213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMULS", - argLen: 2, - commutative: true, - asm: arm64.AFNMULS, + name: "VFMADD231PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMULD", - argLen: 2, - commutative: true, - asm: arm64.AFNMULD, + name: "VFMADDSUB132PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FDIVS", - argLen: 2, - asm: arm64.AFDIVS, + name: "VFMADDSUB213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FDIVD", - argLen: 2, - asm: arm64.AFDIVD, + name: "VFMADDSUB231PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: arm64.AAND, + name: "VFMSUB132PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AAND, + name: "VFMSUB213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: arm64.AORR, + name: "VFMSUB231PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AORR, + name: "VFMSUBADD132PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: arm64.AEOR, + name: "VFMSUBADD213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AEOR, + name: "VFMSUBADD231PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BIC", - argLen: 2, - asm: arm64.ABIC, + name: "VFNMADD132PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EON", - argLen: 2, - asm: arm64.AEON, + name: "VFNMADD213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORN", - argLen: 2, - asm: arm64.AORN, + name: "VFNMADD231PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVN", - argLen: 1, - asm: arm64.AMVN, + name: "VFNMSUB132PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEG", - argLen: 1, - asm: arm64.ANEG, + name: "VFNMSUB213PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGSflags", - argLen: 1, - asm: arm64.ANEGS, + name: "VFNMSUB231PD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {1, 0}, - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NGCzerocarry", - argLen: 1, - asm: arm64.ANGC, + name: "VADDPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FABSD", - argLen: 1, - asm: arm64.AFABSD, + name: "VANDPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNEGS", - argLen: 1, - asm: arm64.AFNEGS, + name: "VANDNPDMasked256", + argLen: 3, + asm: x86.AVANDNPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNEGD", - argLen: 1, - asm: arm64.AFNEGD, + name: "VRCP14PDMasked256", + argLen: 2, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSQRTD", - argLen: 1, - asm: arm64.AFSQRTD, + name: "VRSQRT14PDMasked256", + argLen: 2, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: arm64.AFSQRTS, + name: "VDIVPDMasked256", + argLen: 3, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMIND", - argLen: 2, - asm: arm64.AFMIND, + name: "VFMADD132PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMINS", - argLen: 2, - asm: arm64.AFMINS, + name: "VFMADD213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMAXD", - argLen: 2, - asm: arm64.AFMAXD, + name: "VFMADD231PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMAXS", - argLen: 2, - asm: arm64.AFMAXS, + name: "VFMADDSUB132PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV", - argLen: 1, - asm: arm64.AREV, + name: "VFMADDSUB213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REVW", - argLen: 1, - asm: arm64.AREVW, + name: "VFMADDSUB231PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV16", - argLen: 1, - asm: arm64.AREV16, + name: "VFMSUB132PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REV16W", - argLen: 1, - asm: arm64.AREV16W, + name: "VFMSUB213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RBIT", - argLen: 1, - asm: arm64.ARBIT, + name: "VFMSUB231PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RBITW", - argLen: 1, - asm: arm64.ARBITW, + name: "VFMSUBADD132PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZ", - argLen: 1, - asm: arm64.ACLZ, + name: "VFMSUBADD213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZW", - argLen: 1, - asm: arm64.ACLZW, + name: "VFMSUBADD231PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "VCNT", - argLen: 1, - asm: arm64.AVCNT, + name: "VFNMADD132PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "VUADDLV", - argLen: 1, - asm: arm64.AVUADDLV, + name: "VFNMADD213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredRound32F", - argLen: 1, + name: "VFNMADD231PDMasked256", + argLen: 4, resultInArg0: true, - zeroWidth: true, + asm: x86.AVFNMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredRound64F", - argLen: 1, + name: "VFNMSUB132PDMasked256", + argLen: 4, resultInArg0: true, - zeroWidth: true, + asm: x86.AVFNMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMADDS", - argLen: 3, - asm: arm64.AFMADDS, + name: "VFNMSUB213PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMADDD", - argLen: 3, - asm: arm64.AFMADDD, + name: "VFNMSUB231PDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMADDS", - argLen: 3, - asm: arm64.AFNMADDS, + name: "VMAXPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMADDD", - argLen: 3, - asm: arm64.AFNMADDD, + name: "VMINPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMSUBS", - argLen: 3, - asm: arm64.AFMSUBS, + name: "VMULPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMSUBD", + name: "VSCALEFPDMasked256", argLen: 3, - asm: arm64.AFMSUBD, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMSUBS", - argLen: 3, - asm: arm64.AFNMSUBS, + name: "VORPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMSUBD", - argLen: 3, - asm: arm64.AFNMSUBD, + name: "VSQRTPDMasked256", + argLen: 2, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MADD", - argLen: 3, - asm: arm64.AMADD, + name: "VXORPDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVXORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MADDW", - argLen: 3, - asm: arm64.AMADDW, + name: "VMAXPD256", + argLen: 2, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MSUB", - argLen: 3, - asm: arm64.AMSUB, + name: "VMINPD256", + argLen: 2, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MSUBW", - argLen: 3, - asm: arm64.AMSUBW, + name: "VMULPD256", + argLen: 2, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", + name: "VSCALEFPD256", argLen: 2, - asm: arm64.ALSL, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ALSL, + name: "VORPD256", + argLen: 2, + commutative: true, + asm: x86.AVORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRL", + name: "VHADDPD256", argLen: 2, - asm: arm64.ALSR, + asm: x86.AVHADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ALSR, + name: "VHSUBPD256", + argLen: 2, + asm: x86.AVHSUBPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRA", - argLen: 2, - asm: arm64.AASR, + name: "VSQRTPD256", + argLen: 1, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AASR, + name: "VXORPD256", + argLen: 2, + commutative: true, + asm: x86.AVXORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ROR", - argLen: 2, - asm: arm64.AROR, + name: "VADDPD512", + argLen: 2, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RORW", - argLen: 2, - asm: arm64.ARORW, + name: "VANDPD512", + argLen: 2, + commutative: true, + asm: x86.AVANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RORconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.AROR, + name: "VANDNPD512", + argLen: 2, + asm: x86.AVANDNPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "RORWconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ARORW, + name: "VRCP14PD512", + argLen: 1, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EXTRconst", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEXTR, + name: "VRSQRT14PD512", + argLen: 1, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EXTRWconst", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEXTRW, + name: "VDIVPD512", + argLen: 2, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMP", - argLen: 2, - asm: arm64.ACMP, + name: "VFMADD132PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ACMP, + name: "VFMADD213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPW", - argLen: 2, - asm: arm64.ACMPW, + name: "VFMADD231PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPWconst", - auxType: auxInt32, - argLen: 1, - asm: arm64.ACMPW, + name: "VFMADDSUB132PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMN", - argLen: 2, - commutative: true, - asm: arm64.ACMN, + name: "VFMADDSUB213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ACMN, + name: "VFMADDSUB231PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMADDSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNW", - argLen: 2, - commutative: true, - asm: arm64.ACMNW, + name: "VFMSUB132PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNWconst", - auxType: auxInt32, - argLen: 1, - asm: arm64.ACMNW, + name: "VFMSUB213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TST", - argLen: 2, - commutative: true, - asm: arm64.ATST, + name: "VFMSUB231PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTconst", - auxType: auxInt64, - argLen: 1, - asm: arm64.ATST, + name: "VFMSUBADD132PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTW", - argLen: 2, - commutative: true, - asm: arm64.ATSTW, + name: "VFMSUBADD213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTWconst", - auxType: auxInt32, - argLen: 1, - asm: arm64.ATSTW, + name: "VFMSUBADD231PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFMSUBADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPS", - argLen: 2, - asm: arm64.AFCMPS, + name: "VFNMADD132PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPD", - argLen: 2, - asm: arm64.AFCMPD, + name: "VFNMADD213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPS0", - argLen: 1, - asm: arm64.AFCMPS, + name: "VFNMADD231PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCMPD0", - argLen: 1, - asm: arm64.AFCMPD, + name: "VFNMSUB132PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftLL", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VFNMSUB213PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRL", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VFNMSUB231PD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVFNMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRA", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VADDPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVADDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MVNshiftRO", - auxType: auxInt64, - argLen: 1, - asm: arm64.AMVN, + name: "VANDPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVANDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGshiftLL", - auxType: auxInt64, - argLen: 1, - asm: arm64.ANEG, + name: "VANDNPDMasked512", + argLen: 3, + asm: x86.AVANDNPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGshiftRL", - auxType: auxInt64, - argLen: 1, - asm: arm64.ANEG, + name: "VRCP14PDMasked512", + argLen: 2, + asm: x86.AVRCP14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGshiftRA", - auxType: auxInt64, - argLen: 1, - asm: arm64.ANEG, + name: "VRSQRT14PDMasked512", + argLen: 2, + asm: x86.AVRSQRT14PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AADD, + name: "VDIVPDMasked512", + argLen: 3, + asm: x86.AVDIVPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AADD, + name: "VFMADD132PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AADD, + name: "VFMADD213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ASUB, + name: "VFMADD231PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ASUB, + name: "VFMADDSUB132PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ASUB, + name: "VFMADDSUB213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VFMADDSUB231PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMADDSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VFMSUB132PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VFMSUB213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AAND, + name: "VFMSUB231PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VFMSUBADD132PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VFMSUBADD213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VFMSUBADD231PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFMSUBADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORR, + name: "VFNMADD132PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VFNMADD213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VFNMADD231PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMADD231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VFNMSUB132PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB132PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEOR, + name: "VFNMSUB213PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB213PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VFNMSUB231PDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVFNMSUB231PD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VMAXPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VMINPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BICshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.ABIC, + name: "VMULPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EONshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VSCALEFPDMasked512", + argLen: 3, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EONshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VORPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EONshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VSQRTPDMasked512", + argLen: 2, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "EONshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AEON, + name: "VXORPDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVXORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORNshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VMAXPD512", + argLen: 2, + commutative: true, + asm: x86.AVMAXPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORNshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VMINPD512", + argLen: 2, + commutative: true, + asm: x86.AVMINPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORNshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VMULPD512", + argLen: 2, + commutative: true, + asm: x86.AVMULPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORNshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.AORN, + name: "VSCALEFPD512", + argLen: 2, + asm: x86.AVSCALEFPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMP, + name: "VORPD512", + argLen: 2, + commutative: true, + asm: x86.AVORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMP, + name: "VSQRTPD512", + argLen: 1, + asm: x86.AVSQRTPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMP, + name: "VXORPD512", + argLen: 2, + commutative: true, + asm: x86.AVXORPD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMN, + name: "VPABSW256", + argLen: 1, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMN, + name: "VPADDW256", + argLen: 2, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMNshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ACMN, + name: "VPAND256", + argLen: 2, + commutative: true, + asm: x86.AVPAND, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftLL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPANDN256", + argLen: 2, + asm: x86.AVPANDN, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRL", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPCMPEQW256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRA", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPCMPGTW256", + argLen: 2, + asm: x86.AVPCMPGTW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TSTshiftRO", - auxType: auxInt64, - argLen: 2, - asm: arm64.ATST, + name: "VPABSWMasked256", + argLen: 2, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BFI", - auxType: auxARM64BitField, - argLen: 2, - resultInArg0: true, - asm: arm64.ABFI, + name: "VPADDWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BFXIL", - auxType: auxARM64BitField, - argLen: 2, - resultInArg0: true, - asm: arm64.ABFXIL, + name: "VPCMPEQWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBFIZ", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.ASBFIZ, + name: "VPCMPGTWMasked256", + argLen: 3, + asm: x86.AVPCMPGTW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SBFX", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.ASBFX, + name: "VPMAXSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UBFIZ", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.AUBFIZ, + name: "VPMINSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UBFX", - auxType: auxARM64BitField, - argLen: 1, - asm: arm64.AUBFX, + name: "VPMULHWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: arm64.AMOVD, + name: "VPMULLWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm64.AFMOVS, + name: "VPMADDWDMasked256", + argLen: 3, + asm: x86.AVPMADDWD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: arm64.AFMOVD, + name: "VPOPCNTWMasked256", + argLen: 2, + asm: x86.AVPOPCNTW, reg: regInfo{ + inputs: []inputInfo{ + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: arm64.AMOVD, + name: "VPADDSWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037928517632}, // SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVB, + name: "VPSUBSWMasked256", + argLen: 3, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVBU, + name: "VPSUBWMasked256", + argLen: 3, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVH, + name: "VPMAXSW256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVHU, + name: "VPMINSW256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVW, + name: "VPMULHW256", + argLen: 2, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVWU, + name: "VPMULLW256", + argLen: 2, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AMOVD, + name: "VPOR256", + argLen: 2, + commutative: true, + asm: x86.AVPOR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFMOVS, + name: "VPMADDWD256", + argLen: 2, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFMOVD, + name: "VPHADDW256", + argLen: 2, + asm: x86.AVPHADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LDP", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.ALDP, + name: "VPHSUBW256", + argLen: 2, + asm: x86.AVPHSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LDPW", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.ALDPW, + name: "VPOPCNTW256", + argLen: 1, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LDPSW", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.ALDPSW, + name: "VPADDSW256", + argLen: 2, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FLDPD", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFLDPD, + name: "VPHADDSW256", + argLen: 2, + asm: x86.AVPHADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FLDPS", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: arm64.AFLDPS, + name: "VPHSUBSW256", + argLen: 2, + asm: x86.AVPHSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDloadidx", - argLen: 3, - asm: arm64.AMOVD, + name: "VPSUBSW256", + argLen: 2, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: arm64.AMOVW, + name: "VPSIGNW256", + argLen: 2, + asm: x86.AVPSIGNW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUloadidx", - argLen: 3, - asm: arm64.AMOVWU, + name: "VPSUBW256", + argLen: 2, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHloadidx", - argLen: 3, - asm: arm64.AMOVH, + name: "VPXOR256", + argLen: 2, + commutative: true, + asm: x86.AVPXOR, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUloadidx", - argLen: 3, - asm: arm64.AMOVHU, + name: "VPABSW512", + argLen: 1, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBloadidx", - argLen: 3, - asm: arm64.AMOVB, + name: "VPADDW512", + argLen: 2, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUloadidx", - argLen: 3, - asm: arm64.AMOVBU, + name: "VPCMPEQW512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMOVSloadidx", - argLen: 3, - asm: arm64.AFMOVS, + name: "VPCMPGTW512", + argLen: 2, + asm: x86.AVPCMPGTW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMOVDloadidx", - argLen: 3, - asm: arm64.AFMOVD, + name: "VPABSWMasked512", + argLen: 2, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHloadidx2", - argLen: 3, - asm: arm64.AMOVH, + name: "VPADDWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUloadidx2", - argLen: 3, - asm: arm64.AMOVHU, + name: "VPCMPEQWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWloadidx4", + name: "VPCMPGTWMasked512", argLen: 3, - asm: arm64.AMOVW, + asm: x86.AVPCMPGTW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWUloadidx4", - argLen: 3, - asm: arm64.AMOVWU, + name: "VPMAXSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDloadidx8", - argLen: 3, - asm: arm64.AMOVD, + name: "VPMINSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSloadidx4", - argLen: 3, - asm: arm64.AFMOVS, + name: "VPMULHWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDloadidx8", - argLen: 3, - asm: arm64.AFMOVD, + name: "VPMULLWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVB, + name: "VPMADDWDMasked512", + argLen: 3, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVH, + name: "VPOPCNTWMasked512", + argLen: 2, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVW, + name: "VPADDSWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AMOVD, + name: "VPSUBSWMasked512", + argLen: 3, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFMOVS, + name: "VPSUBWMasked512", + argLen: 3, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFMOVD, + name: "VPMAXSW512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "STP", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.ASTP, + name: "VPMINSW512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "STPW", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.ASTPW, + name: "VPMULHW512", + argLen: 2, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSTPD", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFSTPD, + name: "VPMULLW512", + argLen: 2, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FSTPS", - auxType: auxSymOff, - argLen: 4, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: arm64.AFSTPS, + name: "VPMADDWD512", + argLen: 2, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: arm64.AMOVB, + name: "VPOPCNTW512", + argLen: 1, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: arm64.AMOVH, + name: "VPADDSW512", + argLen: 2, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: arm64.AMOVW, + name: "VPSUBSW512", + argLen: 2, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstoreidx", - argLen: 4, - asm: arm64.AMOVD, + name: "VPSUBW512", + argLen: 2, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSstoreidx", - argLen: 4, - asm: arm64.AFMOVS, + name: "VPABSW128", + argLen: 1, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstoreidx", - argLen: 4, - asm: arm64.AFMOVD, + name: "VPADDW128", + argLen: 2, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstoreidx2", - argLen: 4, - asm: arm64.AMOVH, + name: "VPAND128", + argLen: 2, + commutative: true, + asm: x86.AVPAND, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstoreidx4", - argLen: 4, - asm: arm64.AMOVW, + name: "VPANDN128", + argLen: 2, + asm: x86.AVPANDN, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstoreidx8", - argLen: 4, - asm: arm64.AMOVD, + name: "VPCMPEQW128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVSstoreidx4", - argLen: 4, - asm: arm64.AFMOVS, + name: "VPCMPGTW128", + argLen: 2, + asm: x86.AVPCMPGTW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDstoreidx8", - argLen: 4, - asm: arm64.AFMOVD, + name: "VPABSWMasked128", + argLen: 2, + asm: x86.AVPABSW, reg: regInfo{ inputs: []inputInfo{ - {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDgpfp", - argLen: 1, - asm: arm64.AFMOVD, + name: "VPADDWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMOVDfpgp", - argLen: 1, - asm: arm64.AFMOVD, + name: "VPCMPEQWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMOVSgpfp", - argLen: 1, - asm: arm64.AFMOVS, + name: "VPCMPGTWMasked128", + argLen: 3, + asm: x86.AVPCMPGTW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMOVSfpgp", - argLen: 1, - asm: arm64.AFMOVS, + name: "VPMAXSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: arm64.AMOVB, + name: "VPMINSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: arm64.AMOVBU, + name: "VPMULHWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: arm64.AMOVH, + name: "VPMULLWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: arm64.AMOVHU, + name: "VPMADDWDMasked128", + argLen: 3, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: arm64.AMOVW, + name: "VPOPCNTWMasked128", + argLen: 2, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: arm64.AMOVWU, + name: "VPADDSWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDreg", - argLen: 1, - asm: arm64.AMOVD, + name: "VPSUBSWMasked128", + argLen: 3, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDnop", - argLen: 1, - resultInArg0: true, + name: "VPSUBWMasked128", + argLen: 3, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SCVTFWS", - argLen: 1, - asm: arm64.ASCVTFWS, + name: "VPMAXSW128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SCVTFWD", - argLen: 1, - asm: arm64.ASCVTFWD, + name: "VPMINSW128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UCVTFWS", - argLen: 1, - asm: arm64.AUCVTFWS, + name: "VPMULHW128", + argLen: 2, + commutative: true, + asm: x86.AVPMULHW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UCVTFWD", - argLen: 1, - asm: arm64.AUCVTFWD, + name: "VPMULLW128", + argLen: 2, + commutative: true, + asm: x86.AVPMULLW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SCVTFS", - argLen: 1, - asm: arm64.ASCVTFS, + name: "VPOR128", + argLen: 2, + commutative: true, + asm: x86.AVPOR, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SCVTFD", - argLen: 1, - asm: arm64.ASCVTFD, + name: "VPMADDWD128", + argLen: 2, + asm: x86.AVPMADDWD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UCVTFS", - argLen: 1, - asm: arm64.AUCVTFS, + name: "VPHADDW128", + argLen: 2, + asm: x86.AVPHADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "UCVTFD", - argLen: 1, - asm: arm64.AUCVTFD, + name: "VPHSUBW128", + argLen: 2, + asm: x86.AVPHSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZSSW", + name: "VPOPCNTW128", argLen: 1, - asm: arm64.AFCVTZSSW, + asm: x86.AVPOPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZSDW", - argLen: 1, - asm: arm64.AFCVTZSDW, + name: "VPADDSW128", + argLen: 2, + commutative: true, + asm: x86.AVPADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZUSW", - argLen: 1, - asm: arm64.AFCVTZUSW, + name: "VPHADDSW128", + argLen: 2, + asm: x86.AVPHADDSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZUDW", - argLen: 1, - asm: arm64.AFCVTZUDW, + name: "VPHSUBSW128", + argLen: 2, + asm: x86.AVPHSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZSS", - argLen: 1, - asm: arm64.AFCVTZSS, + name: "VPSUBSW128", + argLen: 2, + asm: x86.AVPSUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZSD", - argLen: 1, - asm: arm64.AFCVTZSD, + name: "VPSIGNW128", + argLen: 2, + asm: x86.AVPSIGNW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZUS", - argLen: 1, - asm: arm64.AFCVTZUS, + name: "VPSUBW128", + argLen: 2, + asm: x86.AVPSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTZUD", - argLen: 1, - asm: arm64.AFCVTZUD, + name: "VPXOR128", + argLen: 2, + commutative: true, + asm: x86.AVPXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTSD", + name: "VPABSD512", argLen: 1, - asm: arm64.AFCVTSD, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCVTDS", - argLen: 1, - asm: arm64.AFCVTDS, + name: "VPADDD512", + argLen: 2, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FRINTAD", - argLen: 1, - asm: arm64.AFRINTAD, + name: "VPANDD512", + argLen: 2, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FRINTMD", - argLen: 1, - asm: arm64.AFRINTMD, + name: "VPANDND512", + argLen: 2, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FRINTND", - argLen: 1, - asm: arm64.AFRINTND, + name: "VPCMPEQD512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FRINTPD", - argLen: 1, - asm: arm64.AFRINTPD, + name: "VPCMPGTD512", + argLen: 2, + asm: x86.AVPCMPGTD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FRINTZD", - argLen: 1, - asm: arm64.AFRINTZD, + name: "VPABSDMasked512", + argLen: 2, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSEL", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSEL, + name: "VPADDDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSEL0", - auxType: auxCCop, - argLen: 2, - asm: arm64.ACSEL, + name: "VPANDDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSINC", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSINC, + name: "VPANDNDMasked512", + argLen: 3, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CSINV", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSINV, + name: "VPCMPEQDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CSNEG", - auxType: auxCCop, - argLen: 3, - asm: arm64.ACSNEG, + name: "VPCMPGTDMasked512", + argLen: 3, + asm: x86.AVPCMPGTD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CSETM", - auxType: auxCCop, - argLen: 1, - asm: arm64.ACSETM, + name: "VPMAXSDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPMINSDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - tailCall: true, + name: "VPMULLDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPORDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {1, 33554432}, // R26 - {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPDPWSSDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPOPCNTDMasked512", + argLen: 2, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "Equal", - argLen: 1, + name: "VPDPWSSDSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSDS, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotEqual", - argLen: 1, + name: "VPDPBUSDSMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPBUSDS, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThan", - argLen: 1, + name: "VPSUBDMasked512", + argLen: 3, + asm: x86.AVPSUBD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqual", - argLen: 1, + name: "VPDPBUSDMasked512", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPBUSD, reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterThan", - argLen: 1, + name: "VPXORDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqual", - argLen: 1, + name: "VPMAXSD512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThanU", - argLen: 1, + name: "VPMINSD512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqualU", - argLen: 1, + name: "VPMULLD512", + argLen: 2, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterThanU", - argLen: 1, + name: "VPORD512", + argLen: 2, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqualU", - argLen: 1, + name: "VPDPWSSD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThanF", + name: "VPOPCNTD512", argLen: 1, + asm: x86.AVPOPCNTD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessEqualF", - argLen: 1, + name: "VPDPWSSDS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSDS, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterThanF", - argLen: 1, + name: "VPDPBUSDS512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPBUSDS, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqualF", - argLen: 1, + name: "VPSUBD512", + argLen: 2, + asm: x86.AVPSUBD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotLessThanF", - argLen: 1, + name: "VPDPBUSD512", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPBUSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotLessEqualF", - argLen: 1, + name: "VPXORD512", + argLen: 2, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotGreaterThanF", + name: "VPABSD128", argLen: 1, + asm: x86.AVPABSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NotGreaterEqualF", - argLen: 1, + name: "VPADDD128", + argLen: 2, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LessThanNoov", - argLen: 1, + name: "VPCMPEQD128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "GreaterEqualNoov", - argLen: 1, + name: "VPCMPGTD128", + argLen: 2, + asm: x86.AVPCMPGTD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 2, - unsafePoint: true, + name: "VPABSDMasked128", + argLen: 2, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 524288}, // R20 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 269156352, // R16 R17 R20 R30 }, }, { - name: "LoweredZero", - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, + name: "VPADDDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 65536}, // R16 - {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 65536, // R16 }, }, { - name: "DUFFCOPY", - auxType: auxInt64, + name: "VPANDDMasked128", argLen: 3, - unsafePoint: true, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R21 - {1, 524288}, // R20 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 303759360, // R16 R17 R20 R21 R26 R30 }, }, { - name: "LoweredMove", - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPANDNDMasked128", + argLen: 3, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {0, 131072}, // R17 - {1, 65536}, // R16 - {2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 16973824, // R16 R17 R25 }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPCMPEQDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 33554432}, // R26 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPCMPGTDMasked128", + argLen: 3, + asm: x86.AVPCMPGTD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPMAXSDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FlagConstant", - auxType: auxFlagConstant, - argLen: 0, - reg: regInfo{}, - }, - { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "LDAR", - argLen: 2, - faultOnNilArg0: true, - asm: arm64.ALDAR, + name: "VPMINSDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LDARB", - argLen: 2, - faultOnNilArg0: true, - asm: arm64.ALDARB, + name: "VPMULLDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LDARW", - argLen: 2, - faultOnNilArg0: true, - asm: arm64.ALDARW, + name: "VPORDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "STLRB", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: arm64.ASTLRB, + name: "VPDPWSSDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "STLR", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: arm64.ASTLR, + name: "VPOPCNTDMasked128", + argLen: 2, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "STLRW", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: arm64.ASTLRW, + name: "VPDPWSSDSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSDS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPDPBUSDSMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPBUSDS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPSUBDMasked128", + argLen: 3, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange8", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPDPBUSDMasked128", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPBUSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPXORDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMAXSD128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMINSD128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMULDQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMULLD128", + argLen: 2, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPDPWSSD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPHADDD128", + argLen: 2, + asm: x86.AVPHADDD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPHSUBD128", + argLen: 2, + asm: x86.AVPHSUBD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPOPCNTD128", + argLen: 1, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas64Variant", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPDPWSSDS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSDS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas32Variant", - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPDPBUSDS128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPBUSDS, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd8", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AAND, + name: "VPSIGND128", + argLen: 2, + asm: x86.AVPSIGND, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr8", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AORR, + name: "VPSUBD128", + argLen: 2, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd64", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AAND, + name: "VPDPBUSD128", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPBUSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr64", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AORR, + name: "VPABSD256", + argLen: 1, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AAND, + name: "VPADDD256", + argLen: 2, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - resultNotInArgs: true, - needIntTemp: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: arm64.AORR, + name: "VPCMPEQD256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPGTD256", + argLen: 2, + asm: x86.AVPCMPGTD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPABSDMasked256", + argLen: 2, + asm: x86.AVPABSD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPADDDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr64Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPANDDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPANDD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPANDNDMasked256", + argLen: 3, + asm: x86.AVPANDND, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr32Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPEQDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQD, reg: regInfo{ inputs: []inputInfo{ - {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPCMPGTDMasked256", + argLen: 3, + asm: x86.AVPCMPGTD, reg: regInfo{ - clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 16777216}, // R25 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMAXSDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMINSDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMULLDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // R0 - {1, 2}, // R1 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "PRFM", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: arm64.APRFM, + name: "VPORDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPORD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DMB", - auxType: auxInt64, - argLen: 1, - hasSideEffects: true, - asm: arm64.ADMB, - reg: regInfo{}, + name: "VPDPWSSDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSD, + reg: regInfo{ + inputs: []inputInfo{ + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, { - name: "ZERO", - argLen: 0, - zeroWidth: true, - fixedReg: true, - reg: regInfo{}, + name: "VPOPCNTDMasked256", + argLen: 2, + asm: x86.AVPOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + }, }, - { - name: "NEGV", - argLen: 1, + name: "VPDPWSSDSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPWSSDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGF", - argLen: 1, - asm: loong64.ANEGF, + name: "VPDPBUSDSMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPBUSDS, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGD", - argLen: 1, - asm: loong64.ANEGD, + name: "VPSUBDMasked256", + argLen: 3, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTD", - argLen: 1, - asm: loong64.ASQRTD, + name: "VPDPBUSDMasked256", + argLen: 4, + resultInArg0: true, + asm: x86.AVPDPBUSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {3, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: loong64.ASQRTF, + name: "VPXORDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPXORD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ABSD", - argLen: 1, - asm: loong64.AABSD, + name: "VPMAXSD256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZW", - argLen: 1, - asm: loong64.ACLZW, + name: "VPMINSD256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZV", - argLen: 1, - asm: loong64.ACLZV, + name: "VPMULDQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CTZW", - argLen: 1, - asm: loong64.ACTZW, + name: "VPMULLD256", + argLen: 2, + commutative: true, + asm: x86.AVPMULLD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CTZV", - argLen: 1, - asm: loong64.ACTZV, + name: "VPDPWSSD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REVB2H", - argLen: 1, - asm: loong64.AREVB2H, + name: "VPHADDD256", + argLen: 2, + asm: x86.AVPHADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REVB2W", - argLen: 1, - asm: loong64.AREVB2W, + name: "VPHSUBD256", + argLen: 2, + asm: x86.AVPHSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REVBV", + name: "VPOPCNTD256", argLen: 1, - asm: loong64.AREVBV, + asm: x86.AVPOPCNTD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BITREV4B", - argLen: 1, - asm: loong64.ABITREV4B, + name: "VPDPWSSDS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPWSSDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BITREVW", - argLen: 1, - asm: loong64.ABITREVW, + name: "VPDPBUSDS256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPBUSDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BITREVV", - argLen: 1, - asm: loong64.ABITREVV, + name: "VPSIGND256", + argLen: 2, + asm: x86.AVPSIGND, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "VPCNT64", - argLen: 1, - asm: loong64.AVPCNTV, + name: "VPSUBD256", + argLen: 2, + asm: x86.AVPSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "VPCNT32", - argLen: 1, - asm: loong64.AVPCNTW, + name: "VPDPBUSD256", + argLen: 3, + resultInArg0: true, + asm: x86.AVPDPBUSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "VPCNT16", + name: "VPABSQ128", argLen: 1, - asm: loong64.AVPCNTH, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDV", + name: "VPADDQ128", argLen: 2, commutative: true, - asm: loong64.AADDVU, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AADDVU, + name: "VPCMPEQQ128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBV", + name: "VPCMPGTQ128", argLen: 2, - asm: loong64.ASUBVU, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASUBVU, + name: "VPABSQMasked128", + argLen: 2, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULV", - argLen: 2, + name: "VPADDQMasked128", + argLen: 3, commutative: true, - asm: loong64.AMULV, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULHV", - argLen: 2, + name: "VPANDQMasked128", + argLen: 3, commutative: true, - asm: loong64.AMULHV, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULHVU", - argLen: 2, - commutative: true, - asm: loong64.AMULHVU, + name: "VPANDNQMasked128", + argLen: 3, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVV", - argLen: 2, - asm: loong64.ADIVV, + name: "VPCMPEQQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "DIVVU", - argLen: 2, - asm: loong64.ADIVVU, + name: "VPCMPGTQMasked128", + argLen: 3, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "REMV", - argLen: 2, - asm: loong64.AREMV, + name: "VPMAXSQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "REMVU", - argLen: 2, - asm: loong64.AREMVU, + name: "VPMINSQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDF", - argLen: 2, + name: "VPMULDQMasked128", + argLen: 3, commutative: true, - asm: loong64.AADDF, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDD", - argLen: 2, + name: "VPMULLQMasked128", + argLen: 3, commutative: true, - asm: loong64.AADDD, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBF", - argLen: 2, - asm: loong64.ASUBF, + name: "VPORQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBD", + name: "VPOPCNTQMasked128", argLen: 2, - asm: loong64.ASUBD, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULF", - argLen: 2, - commutative: true, - asm: loong64.AMULF, + name: "VPSUBQMasked128", + argLen: 3, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULD", - argLen: 2, + name: "VPXORQMasked128", + argLen: 3, commutative: true, - asm: loong64.AMULD, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVF", - argLen: 2, - asm: loong64.ADIVF, + name: "VPMAXSQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: loong64.ADIVD, + name: "VPMINSQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "AND", + name: "VPMULLQ128", argLen: 2, commutative: true, - asm: loong64.AAND, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AAND, + name: "VPOPCNTQ128", + argLen: 1, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: loong64.AOR, + name: "VPSUBQ128", + argLen: 2, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AOR, + name: "VPABSQ256", + argLen: 1, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", + name: "VPADDQ256", argLen: 2, commutative: true, - asm: loong64.AXOR, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AXOR, + name: "VPCMPEQQ256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NOR", - argLen: 2, - commutative: true, - asm: loong64.ANOR, + name: "VPCMPGTQ256", + argLen: 2, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NORconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ANOR, + name: "VPABSQMasked256", + argLen: 2, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDN", - argLen: 2, - asm: loong64.AANDN, + name: "VPADDQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORN", - argLen: 2, - asm: loong64.AORN, + name: "VPANDQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMADDF", - argLen: 3, - commutative: true, - asm: loong64.AFMADDF, + name: "VPANDNQMasked256", + argLen: 3, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMADDD", + name: "VPCMPEQQMasked256", argLen: 3, commutative: true, - asm: loong64.AFMADDD, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMSUBF", - argLen: 3, - commutative: true, - asm: loong64.AFMSUBF, + name: "VPCMPGTQMasked256", + argLen: 3, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FMSUBD", + name: "VPMAXSQMasked256", argLen: 3, commutative: true, - asm: loong64.AFMSUBD, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMADDF", + name: "VPMINSQMasked256", argLen: 3, commutative: true, - asm: loong64.AFNMADDF, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMADDD", + name: "VPMULDQMasked256", argLen: 3, commutative: true, - asm: loong64.AFNMADDD, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMSUBF", + name: "VPMULLQMasked256", argLen: 3, commutative: true, - asm: loong64.AFNMSUBF, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FNMSUBD", + name: "VPORQMasked256", argLen: 3, commutative: true, - asm: loong64.AFNMSUBD, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMINF", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMINF, + name: "VPOPCNTQMasked256", + argLen: 2, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMIND", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMIND, + name: "VPSUBQMasked256", + argLen: 3, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMAXF", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMAXF, + name: "VPXORQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FMAXD", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: loong64.AFMAXD, + name: "VPMAXSQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MASKEQZ", - argLen: 2, - asm: loong64.AMASKEQZ, + name: "VPMINSQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MASKNEZ", - argLen: 2, - asm: loong64.AMASKNEZ, + name: "VPMULLQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FCOPYSGD", - argLen: 2, - asm: loong64.AFCOPYSGD, + name: "VPOPCNTQ256", + argLen: 1, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", + name: "VPSUBQ256", argLen: 2, - asm: loong64.ASLL, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLV", - argLen: 2, - asm: loong64.ASLLV, + name: "VPABSQ512", + argLen: 1, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASLL, + name: "VPADDQ512", + argLen: 2, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASLLV, + name: "VPANDQ512", + argLen: 2, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRL", + name: "VPANDNQ512", argLen: 2, - asm: loong64.ASRL, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLV", - argLen: 2, - asm: loong64.ASRLV, + name: "VPCMPEQQ512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SRLconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRL, + name: "VPCMPGTQ512", + argLen: 2, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SRLVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRLV, + name: "VPABSQMasked512", + argLen: 2, + asm: x86.AVPABSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRA", - argLen: 2, - asm: loong64.ASRA, + name: "VPADDQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAV", - argLen: 2, - asm: loong64.ASRAV, + name: "VPANDQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPANDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRA, + name: "VPANDNQMasked512", + argLen: 3, + asm: x86.AVPANDNQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASRAV, + name: "VPCMPEQQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ROTR", - argLen: 2, - asm: loong64.AROTR, + name: "VPCMPGTQMasked512", + argLen: 3, + asm: x86.AVPCMPGTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ROTRV", - argLen: 2, - asm: loong64.AROTRV, + name: "VPMAXSQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ROTRconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AROTR, + name: "VPMINSQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ROTRVconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.AROTRV, + name: "VPMULDQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGT", - argLen: 2, - asm: loong64.ASGT, + name: "VPMULLQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASGT, + name: "VPORQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTU", + name: "VPOPCNTQMasked512", argLen: 2, - asm: loong64.ASGTU, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTUconst", - auxType: auxInt64, - argLen: 1, - asm: loong64.ASGTU, + name: "VPSUBQMasked512", + argLen: 3, + asm: x86.AVPSUBQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPEQF", - argLen: 2, - asm: loong64.ACMPEQF, + name: "VPXORQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPXORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPEQD", - argLen: 2, - asm: loong64.ACMPEQD, + name: "VPMAXSQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - }, - }, - { - name: "CMPGEF", - argLen: 2, - asm: loong64.ACMPGEF, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGED", - argLen: 2, - asm: loong64.ACMPGED, + name: "VPMINSQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGTF", - argLen: 2, - asm: loong64.ACMPGTF, + name: "VPMULDQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMULDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGTD", - argLen: 2, - asm: loong64.ACMPGTD, + name: "VPMULLQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMULLQ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BSTRPICKW", - auxType: auxInt64, - argLen: 1, - asm: loong64.ABSTRPICKW, + name: "VPORQ512", + argLen: 2, + commutative: true, + asm: x86.AVPORQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "BSTRPICKV", - auxType: auxInt64, - argLen: 1, - asm: loong64.ABSTRPICKV, + name: "VPOPCNTQ512", + argLen: 1, + asm: x86.AVPOPCNTQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: loong64.AMOVV, + name: "VPSUBQ512", + argLen: 2, + asm: x86.AVPSUBQ, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: loong64.AMOVF, + name: "VPXORQ512", + argLen: 2, + commutative: true, + asm: x86.AVPXORQ, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: loong64.AMOVD, + name: "VPABSB128", + argLen: 1, + asm: x86.AVPABSB, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: loong64.AMOVV, + name: "VPADDB128", + argLen: 2, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018427387908}, // SP SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVB, + name: "VPCMPEQB128", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVBU, + name: "VPCMPGTB128", + argLen: 2, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVH, + name: "VPABSBMasked128", + argLen: 2, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVHU, + name: "VPADDBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVW, + name: "VPCMPEQBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVWU, + name: "VPCMPGTBMasked128", + argLen: 3, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVVload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVV, + name: "VPMAXSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVF, + name: "VPMINSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: loong64.AMOVD, + name: "VPOPCNTBMasked128", + argLen: 2, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVloadidx", - argLen: 3, - asm: loong64.AMOVV, + name: "VPADDSBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWloadidx", + name: "VPSUBSBMasked128", argLen: 3, - asm: loong64.AMOVW, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWUloadidx", + name: "VPSUBBMasked128", argLen: 3, - asm: loong64.AMOVWU, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHloadidx", - argLen: 3, - asm: loong64.AMOVH, + name: "VPMAXSB128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUloadidx", - argLen: 3, - asm: loong64.AMOVHU, + name: "VPMINSB128", + argLen: 2, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBloadidx", - argLen: 3, - asm: loong64.AMOVB, + name: "VPOPCNTB128", + argLen: 1, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUloadidx", - argLen: 3, - asm: loong64.AMOVBU, + name: "VPADDSB128", + argLen: 2, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFloadidx", - argLen: 3, - asm: loong64.AMOVF, + name: "VPSUBSB128", + argLen: 2, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDloadidx", - argLen: 3, - asm: loong64.AMOVD, + name: "VPSIGNB128", + argLen: 2, + asm: x86.AVPSIGNB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVB, + name: "VPSUBB128", + argLen: 2, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVH, + name: "VPABSB256", + argLen: 1, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVW, + name: "VPADDB256", + argLen: 2, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVV, + name: "VPCMPEQB256", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVF, + name: "VPCMPGTB256", + argLen: 2, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVD, + name: "VPABSBMasked256", + argLen: 2, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: loong64.AMOVB, + name: "VPADDBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: loong64.AMOVH, + name: "VPCMPEQBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: loong64.AMOVW, + name: "VPCMPGTBMasked256", + argLen: 3, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVVstoreidx", - argLen: 4, - asm: loong64.AMOVV, + name: "VPMAXSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFstoreidx", - argLen: 4, - asm: loong64.AMOVF, + name: "VPMINSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstoreidx", - argLen: 4, - asm: loong64.AMOVD, + name: "VPOPCNTBMasked256", + argLen: 2, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB - {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVB, + name: "VPADDSBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVH, + name: "VPSUBSBMasked256", + argLen: 3, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVW, + name: "VPSUBBMasked256", + argLen: 3, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: loong64.AMOVV, + name: "VPMAXSB256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstorezeroidx", - argLen: 3, - asm: loong64.AMOVB, + name: "VPMINSB256", + argLen: 2, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstorezeroidx", - argLen: 3, - asm: loong64.AMOVH, + name: "VPOPCNTB256", + argLen: 1, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstorezeroidx", - argLen: 3, - asm: loong64.AMOVW, + name: "VPADDSB256", + argLen: 2, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVstorezeroidx", - argLen: 3, - asm: loong64.AMOVV, + name: "VPSUBSB256", + argLen: 2, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWfpgp", - argLen: 1, - asm: loong64.AMOVW, + name: "VPSIGNB256", + argLen: 2, + asm: x86.AVPSIGNB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWgpfp", - argLen: 1, - asm: loong64.AMOVW, + name: "VPSUBB256", + argLen: 2, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVfpgp", + name: "VPABSB512", argLen: 1, - asm: loong64.AMOVV, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVgpfp", - argLen: 1, - asm: loong64.AMOVV, + name: "VPADDB512", + argLen: 2, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: loong64.AMOVB, + name: "VPCMPEQB512", + argLen: 2, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: loong64.AMOVBU, + name: "VPCMPGTB512", + argLen: 2, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: loong64.AMOVH, + name: "VPABSBMasked512", + argLen: 2, + asm: x86.AVPABSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: loong64.AMOVHU, + name: "VPADDBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: loong64.AMOVW, + name: "VPCMPEQBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPCMPEQB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: loong64.AMOVWU, + name: "VPCMPGTBMasked512", + argLen: 3, + asm: x86.AVPCMPGTB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVVreg", - argLen: 1, - asm: loong64.AMOVV, + name: "VPMAXSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVnop", - argLen: 1, - resultInArg0: true, + name: "VPMINSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWF", - argLen: 1, - asm: loong64.AMOVWF, + name: "VPOPCNTBMasked512", + argLen: 2, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWD", - argLen: 1, - asm: loong64.AMOVWD, + name: "VPADDSBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVF", - argLen: 1, - asm: loong64.AMOVVF, + name: "VPSUBSBMasked512", + argLen: 3, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVVD", - argLen: 1, - asm: loong64.AMOVVD, + name: "VPSUBBMasked512", + argLen: 3, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TRUNCFW", - argLen: 1, - asm: loong64.ATRUNCFW, + name: "VPMAXSB512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TRUNCDW", - argLen: 1, - asm: loong64.ATRUNCDW, + name: "VPMINSB512", + argLen: 2, + commutative: true, + asm: x86.AVPMINSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TRUNCFV", + name: "VPOPCNTB512", argLen: 1, - asm: loong64.ATRUNCFV, + asm: x86.AVPOPCNTB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "TRUNCDV", - argLen: 1, - asm: loong64.ATRUNCDV, + name: "VPADDSB512", + argLen: 2, + commutative: true, + asm: x86.AVPADDSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFD", - argLen: 1, - asm: loong64.AMOVFD, + name: "VPSUBSB512", + argLen: 2, + asm: x86.AVPSUBSB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDF", - argLen: 1, - asm: loong64.AMOVDF, + name: "VPSUBB512", + argLen: 2, + asm: x86.AVPSUBB, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, + name: "VPAVGW256", + argLen: 2, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, + name: "VPAVGWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, - { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPMAXUWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 268435456}, // R29 - {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "VPMINUWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, + name: "VPMULHUWMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 524288}, // R20 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 524290, // R1 R20 }, }, { - name: "DUFFCOPY", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPMADDUBSWMasked256", + argLen: 3, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R21 - {1, 524288}, // R20 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 1572866, // R1 R20 R21 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, + name: "VPMAXUW256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {0, 524288}, // R20 - {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 524288, // R20 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPMINUW256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R21 - {1, 524288}, // R20 - {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 1572864, // R20 R21 }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "VPMULHUW256", + argLen: 2, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "VPAVGW512", + argLen: 2, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicLoad64", - argLen: 2, - faultOnNilArg0: true, + name: "VPAVGWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMAXUWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMINUWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore64", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMULHUWMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore8Variant", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMADDUBSWMasked512", + argLen: 3, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore32Variant", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMAXUW512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicStore64Variant", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMINUW512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMULHUW512", + argLen: 2, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMADDUBSW512", + argLen: 2, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicExchange8Variant", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPAVGW128", + argLen: 2, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPAVGWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPAVGW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPMAXUWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMINUWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMULHUWMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas64Variant", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMADDUBSWMasked128", + argLen: 3, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicCas32Variant", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPMAXUW128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMANDDBW, + name: "VPMINUW128", + argLen: 2, + commutative: true, + asm: x86.AVPMINUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMORDBW, + name: "VPMULHUW128", + argLen: 2, + commutative: true, + asm: x86.AVPMULHUW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd32value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMANDDBW, + name: "VPMAXUDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicAnd64value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMANDDBV, + name: "VPMINUDMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr32value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMORDBW, + name: "VPMAXUD512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredAtomicOr64value", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - asm: loong64.AAMORDBV, + name: "VPMINUD512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 - {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPMAXUDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - }, - }, - { - name: "FPFlagTrue", - argLen: 1, - reg: regInfo{ outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "FPFlagFalse", - argLen: 1, + name: "VPMINUDMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ - outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - }, - }, - { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, - reg: regInfo{ outputs: []outputInfo{ - {0, 268435456}, // R29 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPMAXUD128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPMINUD128", + argLen: 2, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPMULUDQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ - clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 268435456}, // R29 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: loong64.ADBAR, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMAXUDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4194304}, // R23 - {1, 8388608}, // R24 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMINUDMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R21 - {1, 4194304}, // R23 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPMAXUD256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUD, reg: regInfo{ inputs: []inputInfo{ - {0, 524288}, // R20 - {1, 1048576}, // R21 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "PRELD", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: loong64.APRELD, + name: "VPMINUD256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "PRELDX", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: loong64.APRELDX, + name: "VPMULUDQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, - { - name: "ADD", - argLen: 2, + name: "VPMAXUQMasked128", + argLen: 3, commutative: true, - asm: mips.AADDU, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AADDU, + name: "VPMINUQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUB", - argLen: 2, - asm: mips.ASUBU, + name: "VPMULUDQMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASUBU, + name: "VPMAXUQ128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MUL", + name: "VPMINUQ128", argLen: 2, commutative: true, - asm: mips.AMUL, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, - clobbers: 105553116266496, // HI LO outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULT", - argLen: 2, + name: "VPMAXUQMasked256", + argLen: 3, commutative: true, - asm: mips.AMUL, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULTU", - argLen: 2, + name: "VPMINUQMasked256", + argLen: 3, commutative: true, - asm: mips.AMULU, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIV", - argLen: 2, - asm: mips.ADIV, + name: "VPMULUDQMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVU", - argLen: 2, - asm: mips.ADIVU, + name: "VPMAXUQ256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35184372088832}, // HI - {1, 70368744177664}, // LO + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDF", + name: "VPMINUQ256", argLen: 2, commutative: true, - asm: mips.AADDF, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ADDD", - argLen: 2, + name: "VPMAXUQMasked512", + argLen: 3, commutative: true, - asm: mips.AADDD, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBF", - argLen: 2, - asm: mips.ASUBF, + name: "VPMINUQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SUBD", - argLen: 2, - asm: mips.ASUBD, + name: "VPMULUDQMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULF", + name: "VPMAXUQ512", argLen: 2, commutative: true, - asm: mips.AMULF, + asm: x86.AVPMAXUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MULD", + name: "VPMINUQ512", argLen: 2, commutative: true, - asm: mips.AMULD, + asm: x86.AVPMINUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVF", - argLen: 2, - asm: mips.ADIVF, + name: "VPMULUDQ512", + argLen: 2, + commutative: true, + asm: x86.AVPMULUDQ, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: mips.ADIVD, + name: "VPAVGB128", + argLen: 2, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "AND", - argLen: 2, + name: "VPAVGBMasked128", + argLen: 3, commutative: true, - asm: mips.AAND, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ANDconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AAND, + name: "VPMAXUBMasked128", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "OR", - argLen: 2, + name: "VPMINUBMasked128", + argLen: 3, commutative: true, - asm: mips.AOR, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ORconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AOR, + name: "VPMAXUB128", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XOR", + name: "VPMINUB128", argLen: 2, commutative: true, - asm: mips.AXOR, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "XORconst", - auxType: auxInt32, - argLen: 1, - asm: mips.AXOR, + name: "VPMADDUBSW128", + argLen: 2, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NOR", + name: "VPAVGB256", argLen: 2, commutative: true, - asm: mips.ANOR, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NORconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ANOR, + name: "VPAVGBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEG", - argLen: 1, + name: "VPMAXUBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGF", - argLen: 1, - asm: mips.ANEGF, + name: "VPMINUBMasked256", + argLen: 3, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "NEGD", - argLen: 1, - asm: mips.ANEGD, + name: "VPMAXUB256", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "ABSD", - argLen: 1, - asm: mips.AABSD, + name: "VPMINUB256", + argLen: 2, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTD", - argLen: 1, - asm: mips.ASQRTD, + name: "VPMADDUBSW256", + argLen: 2, + asm: x86.AVPMADDUBSW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: mips.ASQRTF, + name: "VPAVGB512", + argLen: 2, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLL", - argLen: 2, - asm: mips.ASLL, + name: "VPAVGBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPAVGB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SLLconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASLL, + name: "VPMAXUBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRL", - argLen: 2, - asm: mips.ASRL, + name: "VPMINUBMasked512", + argLen: 3, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRLconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASRL, + name: "VPMAXUB512", + argLen: 2, + commutative: true, + asm: x86.AVPMAXUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRA", - argLen: 2, - asm: mips.ASRA, + name: "VPMINUB512", + argLen: 2, + commutative: true, + asm: x86.AVPMINUB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SRAconst", - auxType: auxInt32, + name: "VRNDSCALEPS512", + auxType: auxInt8, argLen: 1, - asm: mips.ASRA, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CLZ", - argLen: 1, - asm: mips.ACLZ, + name: "VREDUCEPS512", + auxType: auxInt8, + argLen: 1, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGT", - argLen: 2, - asm: mips.ASGT, + name: "VCMPPS512", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SGTconst", - auxType: auxInt32, - argLen: 1, - asm: mips.ASGT, + name: "VRNDSCALEPSMasked512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTzero", - argLen: 1, - asm: mips.ASGT, + name: "VREDUCEPSMasked512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTU", - argLen: 2, - asm: mips.ASGTU, + name: "VCMPPSMasked512", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SGTUconst", - auxType: auxInt32, + name: "VROUNDPS128", + auxType: auxInt8, argLen: 1, - asm: mips.ASGTU, + asm: x86.AVROUNDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "SGTUzero", - argLen: 1, - asm: mips.ASGTU, + name: "VRNDSCALEPS128", + auxType: auxInt8, + argLen: 1, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPEQF", - argLen: 2, - asm: mips.ACMPEQF, + name: "VREDUCEPS128", + auxType: auxInt8, + argLen: 1, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPEQD", - argLen: 2, - asm: mips.ACMPEQD, + name: "VCMPPS128", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGEF", - argLen: 2, - asm: mips.ACMPGEF, + name: "VRNDSCALEPSMasked128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGED", - argLen: 2, - asm: mips.ACMPGED, + name: "VREDUCEPSMasked128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "CMPGTF", - argLen: 2, - asm: mips.ACMPGTF, + name: "VCMPPSMasked128", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CMPGTD", - argLen: 2, - asm: mips.ACMPGTD, + name: "VROUNDPS256", + auxType: auxInt8, + argLen: 1, + asm: x86.AVROUNDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWconst", - auxType: auxInt32, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVW, + name: "VRNDSCALEPS256", + auxType: auxInt8, + argLen: 1, + asm: x86.AVRNDSCALEPS, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFconst", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVF, + name: "VREDUCEPS256", + auxType: auxInt8, + argLen: 1, + asm: x86.AVREDUCEPS, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVD, + name: "VCMPPS256", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVCMPPS, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: mips.AMOVW, + name: "VRNDSCALEPSMasked256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVRNDSCALEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 140737555464192}, // SP SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVB, + name: "VREDUCEPSMasked256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVREDUCEPS, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVBU, + name: "VCMPPSMasked256", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVCMPPS, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVH, + name: "VROUNDPD128", + auxType: auxInt8, + argLen: 1, + asm: x86.AVROUNDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVHU, + name: "VRNDSCALEPD128", + auxType: auxInt8, + argLen: 1, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVW, + name: "VREDUCEPD128", + auxType: auxInt8, + argLen: 1, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVF, + name: "VDPPD128", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVDPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVD, + name: "VCMPPD128", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "VRNDSCALEPDMasked128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "VREDUCEPDMasked128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "VCMPPDMasked128", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVF, + name: "VROUNDPD256", + auxType: auxInt8, + argLen: 1, + asm: x86.AVROUNDPD, reg: regInfo{ inputs: []inputInfo{ - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVD, + name: "VRNDSCALEPD256", + auxType: auxInt8, + argLen: 1, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "VREDUCEPD256", + auxType: auxInt8, + argLen: 1, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "VCMPPD256", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "VRNDSCALEPDMasked256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWfpgp", - argLen: 1, - asm: mips.AMOVW, + name: "VREDUCEPDMasked256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWgpfp", - argLen: 1, - asm: mips.AMOVW, + name: "VCMPPDMasked256", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: mips.AMOVB, + name: "VRNDSCALEPD512", + auxType: auxInt8, + argLen: 1, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: mips.AMOVBU, + name: "VREDUCEPD512", + auxType: auxInt8, + argLen: 1, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: mips.AMOVH, + name: "VCMPPD512", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: mips.AMOVHU, + name: "VRNDSCALEPDMasked512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVRNDSCALEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: mips.AMOVW, + name: "VREDUCEPDMasked512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVREDUCEPD, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, }, }, { - name: "MOVWnop", - argLen: 1, - resultInArg0: true, + name: "VCMPPDMasked512", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVCMPPD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CMOVZ", - argLen: 3, - resultInArg0: true, - asm: mips.ACMOVZ, + name: "VPCMPW256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 - {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 - {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CMOVZzero", - argLen: 2, - resultInArg0: true, - asm: mips.ACMOVZ, + name: "VPCMPWMasked256", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWF", - argLen: 1, - asm: mips.AMOVWF, + name: "VPCMPW512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVWD", - argLen: 1, - asm: mips.AMOVWD, + name: "VPCMPWMasked512", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "TRUNCFW", - argLen: 1, - asm: mips.ATRUNCFW, + name: "VPCMPW128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "TRUNCDW", - argLen: 1, - asm: mips.ATRUNCDW, + name: "VPCMPWMasked128", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVFD", - argLen: 1, - asm: mips.AMOVFD, + name: "VPCMPD512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MOVDF", - argLen: 1, - asm: mips.AMOVDF, + name: "VPCMPDMasked512", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO - }, - }, - { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "VPCMPD128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {1, 4194304}, // R22 - {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, + name: "VPCMPDMasked128", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, - clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "VPCMPD256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "VPCMPDMasked256", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPQ128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPQMasked128", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicStorezero", - argLen: 2, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VPCMPQ256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicExchange", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPQMasked256", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicAdd", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPQ512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicAddconst", - auxType: auxInt32, - argLen: 2, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPQMasked512", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPQ, reg: regInfo{ inputs: []inputInfo{ - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicCas", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "VPCMPB128", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicAnd", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AAND, + name: "VPCMPBMasked128", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredAtomicOr", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AOR, + name: "VPCMPB256", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 - {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredZero", - auxType: auxInt32, - argLen: 3, - faultOnNilArg0: true, + name: "VPCMPBMasked256", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, - clobbers: 2, // R1 }, }, { - name: "LoweredMove", - auxType: auxInt32, - argLen: 4, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "VPCMPB512", + auxType: auxInt8, + argLen: 2, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 - {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "VPCMPBMasked512", + auxType: auxInt8, + argLen: 3, + asm: x86.AVPCMPB, reg: regInfo{ inputs: []inputInfo{ - {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FPFlagTrue", - argLen: 1, + name: "VPCMPUW256", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUW, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "FPFlagFalse", - argLen: 1, + name: "VPCMPUWMasked256", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUW, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "VPCMPUW512", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUW, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 4194304}, // R22 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "VPCMPUWMasked512", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUW, reg: regInfo{ + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "VPCMPUW128", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUW, reg: regInfo{ + inputs: []inputInfo{ + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "VPCMPUWMasked128", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUW, reg: regInfo{ - clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + inputs: []inputInfo{ + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, outputs: []outputInfo{ - {0, 16777216}, // R25 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: mips.ASYNC, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPCMPUD512", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 8}, // R3 - {1, 16}, // R4 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPCMPUDMasked512", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "VPCMPUD128", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicExtendA", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VPCMPUDMasked128", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 32}, // R5 - {1, 8}, // R3 - {2, 16}, // R4 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicExtendB", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VPCMPUD256", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 32}, // R5 - {1, 4}, // R2 - {2, 8}, // R3 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "LoweredPanicExtendC", - auxType: auxInt64, - argLen: 4, - call: true, + name: "VPCMPUDMasked256", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUD, reg: regInfo{ inputs: []inputInfo{ - {0, 32}, // R5 - {1, 2}, // R1 - {2, 4}, // R2 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + }, + outputs: []outputInfo{ + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, - { - name: "ADDV", + name: "VPCMPUQ128", + auxType: auxInt8, argLen: 2, commutative: true, - asm: mips.AADDVU, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AADDVU, + name: "VPCMPUQMasked128", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBV", - argLen: 2, - asm: mips.ASUBVU, + name: "VPCMPUQ256", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASUBVU, + name: "VPCMPUQMasked256", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULV", + name: "VPCMPUQ512", + auxType: auxInt8, argLen: 2, commutative: true, - asm: mips.AMULV, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "MULVU", - argLen: 2, + name: "VPCMPUQMasked512", + auxType: auxInt8, + argLen: 3, commutative: true, - asm: mips.AMULVU, + asm: x86.AVPCMPUQ, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "DIVV", - argLen: 2, - asm: mips.ADIVV, + name: "VPCMPUB128", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "DIVVU", - argLen: 2, - asm: mips.ADIVVU, + name: "VPCMPUBMasked128", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504606846976}, // HI - {1, 2305843009213693952}, // LO + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDF", + name: "VPCMPUB256", + auxType: auxInt8, argLen: 2, commutative: true, - asm: mips.AADDF, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "ADDD", - argLen: 2, + name: "VPCMPUBMasked256", + auxType: auxInt8, + argLen: 3, commutative: true, - asm: mips.AADDD, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBF", - argLen: 2, - asm: mips.ASUBF, + name: "VPCMPUB512", + auxType: auxInt8, + argLen: 2, + commutative: true, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, { - name: "SUBD", - argLen: 2, - asm: mips.ASUBD, + name: "VPCMPUBMasked512", + auxType: auxInt8, + argLen: 3, + commutative: true, + asm: x86.AVPCMPUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 + {0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 + {1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1090921693184}, // K1 K2 K3 K4 K5 K6 K7 }, }, }, + { - name: "MULF", + name: "ADD", argLen: 2, commutative: true, - asm: mips.AMULF, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULD", - argLen: 2, - commutative: true, - asm: mips.AMULD, + name: "ADDconst", + auxType: auxInt32, + argLen: 1, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "DIVF", + name: "SUB", argLen: 2, - asm: mips.ADIVF, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: mips.ADIVD, + name: "SUBconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: mips.AAND, + name: "RSB", + argLen: 2, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ANDconst", - auxType: auxInt64, + name: "RSBconst", + auxType: auxInt32, argLen: 1, - asm: mips.AAND, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "OR", + name: "MUL", argLen: 2, commutative: true, - asm: mips.AOR, + asm: arm.AMUL, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AOR, + name: "HMUL", + argLen: 2, + commutative: true, + asm: arm.AMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "XOR", + name: "HMULU", argLen: 2, commutative: true, - asm: mips.AXOR, + asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: mips.AXOR, + name: "CALLudiv", + argLen: 2, + clobberFlags: true, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 2}, // R1 + {1, 1}, // R0 }, + clobbers: 20492, // R2 R3 R12 R14 outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 1}, // R0 + {1, 2}, // R1 }, }, }, { - name: "NOR", + name: "ADDS", argLen: 2, commutative: true, - asm: mips.ANOR, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "NORconst", - auxType: auxInt64, + name: "ADDSconst", + auxType: auxInt32, argLen: 1, - asm: mips.ANOR, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "NEGV", - argLen: 1, + name: "ADC", + argLen: 3, + commutative: true, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "NEGF", - argLen: 1, - asm: mips.ANEGF, + name: "ADCconst", + auxType: auxInt32, + argLen: 2, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "NEGD", - argLen: 1, - asm: mips.ANEGD, + name: "SUBS", + argLen: 2, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ABSD", - argLen: 1, - asm: mips.AABSD, + name: "SUBSconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SQRTD", - argLen: 1, - asm: mips.ASQRTD, + name: "RSBSconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SQRTF", - argLen: 1, - asm: mips.ASQRTF, + name: "SBC", + argLen: 3, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SLLV", - argLen: 2, - asm: mips.ASLLV, + name: "SBCconst", + auxType: auxInt32, + argLen: 2, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SLLVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASLLV, + name: "RSCconst", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRLV", - argLen: 2, - asm: mips.ASRLV, + name: "MULLU", + argLen: 2, + commutative: true, + asm: arm.AMULLU, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRLVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASRLV, + name: "MULA", + argLen: 3, + asm: arm.AMULA, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRAV", - argLen: 2, - asm: mips.ASRAV, + name: "MULS", + argLen: 3, + asm: arm.AMULS, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRAVconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASRAV, + name: "ADDF", + argLen: 2, + commutative: true, + asm: arm.AADDF, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "SGT", - argLen: 2, - asm: mips.ASGT, + name: "ADDD", + argLen: 2, + commutative: true, + asm: arm.AADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "SGTconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASGT, + name: "SUBF", + argLen: 2, + asm: arm.ASUBF, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "SGTU", + name: "SUBD", argLen: 2, - asm: mips.ASGTU, + asm: arm.ASUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "SGTUconst", - auxType: auxInt64, - argLen: 1, - asm: mips.ASGTU, + name: "MULF", + argLen: 2, + commutative: true, + asm: arm.AMULF, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "CMPEQF", - argLen: 2, - asm: mips.ACMPEQF, + name: "MULD", + argLen: 2, + commutative: true, + asm: arm.AMULD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "CMPEQD", - argLen: 2, - asm: mips.ACMPEQD, + name: "NMULF", + argLen: 2, + commutative: true, + asm: arm.ANMULF, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "CMPGEF", - argLen: 2, - asm: mips.ACMPGEF, + name: "NMULD", + argLen: 2, + commutative: true, + asm: arm.ANMULD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "CMPGED", + name: "DIVF", argLen: 2, - asm: mips.ACMPGED, + asm: arm.ADIVF, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "CMPGTF", + name: "DIVD", argLen: 2, - asm: mips.ACMPGTF, + asm: arm.ADIVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "CMPGTD", - argLen: 2, - asm: mips.ACMPGTD, + name: "MULAF", + argLen: 3, + resultInArg0: true, + asm: arm.AMULAF, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVVconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVV, + name: "MULAD", + argLen: 3, + resultInArg0: true, + asm: arm.AMULAD, reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVFconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVF, + name: "MULSF", + argLen: 3, + resultInArg0: true, + asm: arm.AMULSF, reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: mips.AMOVD, + name: "MULSD", + argLen: 3, + resultInArg0: true, + asm: arm.AMULSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVVaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: mips.AMOVV, + name: "FMULAD", + argLen: 3, + resultInArg0: true, + asm: arm.AFMULAD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018460942336}, // SP SB + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVB, + name: "AND", + argLen: 2, + commutative: true, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVBU, + name: "ANDconst", + auxType: auxInt32, + argLen: 1, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVH, + name: "OR", + argLen: 2, + commutative: true, + asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVHU, + name: "ORconst", + auxType: auxInt32, + argLen: 1, + asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVW, + name: "XOR", + argLen: 2, + commutative: true, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVWU, + name: "XORconst", + auxType: auxInt32, + argLen: 1, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVV, + name: "BIC", + argLen: 2, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVFload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVF, + name: "BICconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: mips.AMOVD, + name: "BFX", + auxType: auxInt32, + argLen: 1, + asm: arm.ABFX, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "BFXU", + auxType: auxInt32, + argLen: 1, + asm: arm.ABFXU, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "MVN", + argLen: 1, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "NEGF", + argLen: 1, + asm: arm.ANEGF, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVVstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVV, + name: "NEGD", + argLen: 1, + asm: arm.ANEGD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVFstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVF, + name: "SQRTD", + argLen: 1, + asm: arm.ASQRTD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVD, + name: "SQRTF", + argLen: 1, + asm: arm.ASQRTF, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB - {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVB, + name: "ABSD", + argLen: 1, + asm: arm.AABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVH, + name: "CLZ", + argLen: 1, + asm: arm.ACLZ, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVW, + name: "REV", + argLen: 1, + asm: arm.AREV, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: mips.AMOVV, + name: "REV16", + argLen: 1, + asm: arm.AREV16, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWfpgp", + name: "RBIT", argLen: 1, - asm: mips.AMOVW, + asm: arm.ARBIT, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWgpfp", - argLen: 1, - asm: mips.AMOVW, + name: "SLL", + argLen: 2, + asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVfpgp", - argLen: 1, - asm: mips.AMOVV, + name: "SLLconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ASLL, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVgpfp", - argLen: 1, - asm: mips.AMOVV, + name: "SRL", + argLen: 2, + asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: mips.AMOVB, + name: "SRLconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ASRL, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: mips.AMOVBU, + name: "SRA", + argLen: 2, + asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: mips.AMOVH, + name: "SRAconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: mips.AMOVHU, + name: "SRR", + argLen: 2, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: mips.AMOVW, + name: "SRRconst", + auxType: auxInt32, + argLen: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: mips.AMOVWU, + name: "ADDshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVreg", - argLen: 1, - asm: mips.AMOVV, + name: "ADDshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVnop", - argLen: 1, - resultInArg0: true, + name: "ADDshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWF", - argLen: 1, - asm: mips.AMOVWF, + name: "SUBshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWD", - argLen: 1, - asm: mips.AMOVWD, + name: "SUBshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVF", - argLen: 1, - asm: mips.AMOVVF, + name: "SUBshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVVD", - argLen: 1, - asm: mips.AMOVVD, + name: "RSBshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "TRUNCFW", - argLen: 1, - asm: mips.ATRUNCFW, + name: "RSBshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "TRUNCDW", - argLen: 1, - asm: mips.ATRUNCDW, + name: "RSBshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "TRUNCFV", - argLen: 1, - asm: mips.ATRUNCFV, + name: "ANDshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "TRUNCDV", - argLen: 1, - asm: mips.ATRUNCDV, + name: "ANDshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVFD", - argLen: 1, - asm: mips.AMOVFD, + name: "ANDshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVDF", - argLen: 1, - asm: mips.AMOVDF, + name: "ORshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, + name: "ORshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.AORR, reg: regInfo{ - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + inputs: []inputInfo{ + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, + name: "ORshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.AORR, reg: regInfo{ - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + inputs: []inputInfo{ + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "XORshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {1, 4194304}, // R22 - {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, - reg: regInfo{ - inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 - }, - clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO - }, - }, - { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, + name: "XORshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 134217730, // R1 R31 }, }, { - name: "DUFFCOPY", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "XORshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 134217734, // R1 R2 R31 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, + name: "XORshiftRR", + auxType: auxInt32, + argLen: 2, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 2, // R1 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "BICshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 2}, // R1 - {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AAND, + name: "BICshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, - asm: mips.AOR, + name: "BICshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "MVNshiftLL", + auxType: auxInt32, + argLen: 1, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, - faultOnNilArg0: true, + name: "MVNshiftRL", + auxType: auxInt32, + argLen: 1, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicLoad64", - argLen: 2, - faultOnNilArg0: true, + name: "MVNshiftRA", + auxType: auxInt32, + argLen: 1, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicStore8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "ADCshiftLL", + auxType: auxInt32, + argLen: 3, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicStore32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "ADCshiftRL", + auxType: auxInt32, + argLen: 3, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicStore64", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "ADCshiftRA", + auxType: auxInt32, + argLen: 3, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicStorezero32", - argLen: 2, - faultOnNilArg0: true, - hasSideEffects: true, + name: "SBCshiftLL", + auxType: auxInt32, + argLen: 3, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicStorezero64", - argLen: 2, - faultOnNilArg0: true, - hasSideEffects: true, + name: "SBCshiftRL", + auxType: auxInt32, + argLen: 3, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "SBCshiftRA", + auxType: auxInt32, + argLen: 3, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "RSCshiftLL", + auxType: auxInt32, + argLen: 3, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "RSCshiftRL", + auxType: auxInt32, + argLen: 3, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "RSCshiftRA", + auxType: auxInt32, + argLen: 3, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicAddconst32", - auxType: auxInt32, - argLen: 2, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "ADDSshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicAddconst64", - auxType: auxInt64, - argLen: 2, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "ADDSshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "ADDSshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "SUBSshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 - {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "SUBSshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, + outputs: []outputInfo{ + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FPFlagTrue", - argLen: 1, + name: "SUBSshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ASUB, reg: regInfo{ + inputs: []inputInfo{ + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FPFlagFalse", - argLen: 1, + name: "RSBSshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, reg: regInfo{ + inputs: []inputInfo{ + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "RSBSshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, reg: regInfo{ + inputs: []inputInfo{ + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, outputs: []outputInfo{ - {0, 4194304}, // R22 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "RSBSshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ARSB, reg: regInfo{ + inputs: []inputInfo{ + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "ADDshiftLLreg", + argLen: 3, + asm: arm.AADD, reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, outputs: []outputInfo{ - {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "ADDshiftRLreg", + argLen: 3, + asm: arm.AADD, reg: regInfo{ - clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, outputs: []outputInfo{ - {0, 16777216}, // R25 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: mips.ASYNC, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "ADDshiftRAreg", + argLen: 3, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 8}, // R3 - {1, 16}, // R4 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "SUBshiftLLreg", + argLen: 3, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "SUBshiftRLreg", + argLen: 3, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, - { - name: "ADD", - argLen: 2, - commutative: true, - asm: ppc64.AADD, + name: "SUBshiftRAreg", + argLen: 3, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ADDCC", - argLen: 2, - commutative: true, - asm: ppc64.AADDCC, + name: "RSBshiftLLreg", + argLen: 3, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ADDconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AADD, + name: "RSBshiftRLreg", + argLen: 3, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ADDCCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AADDCCC, + name: "RSBshiftRAreg", + argLen: 3, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FADD", - argLen: 2, - commutative: true, - asm: ppc64.AFADD, + name: "ANDshiftLLreg", + argLen: 3, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FADDS", - argLen: 2, - commutative: true, - asm: ppc64.AFADDS, + name: "ANDshiftRLreg", + argLen: 3, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SUB", - argLen: 2, - asm: ppc64.ASUB, + name: "ANDshiftRAreg", + argLen: 3, + asm: arm.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SUBCC", - argLen: 2, - asm: ppc64.ASUBCC, + name: "ORshiftLLreg", + argLen: 3, + asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SUBFCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASUBC, + name: "ORshiftRLreg", + argLen: 3, + asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FSUB", - argLen: 2, - asm: ppc64.AFSUB, + name: "ORshiftRAreg", + argLen: 3, + asm: arm.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FSUBS", - argLen: 2, - asm: ppc64.AFSUBS, + name: "XORshiftLLreg", + argLen: 3, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "XSMINJDP", - argLen: 2, - asm: ppc64.AXSMINJDP, + name: "XORshiftRLreg", + argLen: 3, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "XSMAXJDP", - argLen: 2, - asm: ppc64.AXSMAXJDP, + name: "XORshiftRAreg", + argLen: 3, + asm: arm.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULLD", - argLen: 2, - commutative: true, - asm: ppc64.AMULLD, + name: "BICshiftLLreg", + argLen: 3, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULLW", - argLen: 2, - commutative: true, - asm: ppc64.AMULLW, + name: "BICshiftRLreg", + argLen: 3, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULLDconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.AMULLD, + name: "BICshiftRAreg", + argLen: 3, + asm: arm.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULLWconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.AMULLW, + name: "MVNshiftLLreg", + argLen: 2, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MADDLD", - argLen: 3, - asm: ppc64.AMADDLD, + name: "MVNshiftRLreg", + argLen: 2, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULHD", - argLen: 2, - commutative: true, - asm: ppc64.AMULHD, + name: "MVNshiftRAreg", + argLen: 2, + asm: arm.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULHW", - argLen: 2, - commutative: true, - asm: ppc64.AMULHW, + name: "ADCshiftLLreg", + argLen: 4, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULHDU", - argLen: 2, - commutative: true, - asm: ppc64.AMULHDU, + name: "ADCshiftRLreg", + argLen: 4, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULHDUCC", - argLen: 2, - commutative: true, - asm: ppc64.AMULHDUCC, + name: "ADCshiftRAreg", + argLen: 4, + asm: arm.AADC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MULHWU", - argLen: 2, - commutative: true, - asm: ppc64.AMULHWU, + name: "SBCshiftLLreg", + argLen: 4, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMUL", - argLen: 2, - commutative: true, - asm: ppc64.AFMUL, + name: "SBCshiftRLreg", + argLen: 4, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - asm: ppc64.AFMULS, + name: "SBCshiftRAreg", + argLen: 4, + asm: arm.ASBC, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMADD", - argLen: 3, - asm: ppc64.AFMADD, + name: "RSCshiftLLreg", + argLen: 4, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMADDS", - argLen: 3, - asm: ppc64.AFMADDS, + name: "RSCshiftRLreg", + argLen: 4, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMSUB", - argLen: 3, - asm: ppc64.AFMSUB, + name: "RSCshiftRAreg", + argLen: 4, + asm: arm.ARSC, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMSUBS", + name: "ADDSshiftLLreg", argLen: 3, - asm: ppc64.AFMSUBS, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRAD", - argLen: 2, - asm: ppc64.ASRAD, + name: "ADDSshiftRLreg", + argLen: 3, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRAW", - argLen: 2, - asm: ppc64.ASRAW, + name: "ADDSshiftRAreg", + argLen: 3, + asm: arm.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, - clobbers: 9223372036854775808, // XER outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRD", - argLen: 2, - asm: ppc64.ASRD, + name: "SUBSshiftLLreg", + argLen: 3, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SRW", - argLen: 2, - asm: ppc64.ASRW, + name: "SUBSshiftRLreg", + argLen: 3, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SLD", - argLen: 2, - asm: ppc64.ASLD, + name: "SUBSshiftRAreg", + argLen: 3, + asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "SLW", - argLen: 2, - asm: ppc64.ASLW, + name: "RSBSshiftLLreg", + argLen: 3, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ROTL", - argLen: 2, - asm: ppc64.AROTL, + name: "RSBSshiftRLreg", + argLen: 3, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ROTLW", - argLen: 2, - asm: ppc64.AROTLW, + name: "RSBSshiftRAreg", + argLen: 3, + asm: arm.ARSB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 0}, + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CLRLSLWI", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACLRLSLWI, + name: "CMP", + argLen: 2, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "CLRLSLDI", + name: "CMPconst", auxType: auxInt32, argLen: 1, - asm: ppc64.ACLRLSLDI, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "ADDC", + name: "CMN", argLen: 2, commutative: true, - asm: ppc64.AADDC, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SUBC", - argLen: 2, - asm: ppc64.ASUBC, + name: "CMNconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "ADDCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AADDC, + name: "TST", + argLen: 2, + commutative: true, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SUBCconst", - auxType: auxInt64, + name: "TSTconst", + auxType: auxInt32, argLen: 1, - asm: ppc64.ASUBC, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "ADDE", - argLen: 3, + name: "TEQ", + argLen: 2, commutative: true, - asm: ppc64.AADDE, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {2, 9223372036854775808}, // XER - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "ADDZE", - argLen: 2, - asm: ppc64.AADDZE, + name: "TEQconst", + auxType: auxInt32, + argLen: 1, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SUBE", - argLen: 3, - asm: ppc64.ASUBE, + name: "CMPF", + argLen: 2, + asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ - {2, 9223372036854775808}, // XER - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {1, 9223372036854775808}, // XER - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "ADDZEzero", - argLen: 1, - asm: ppc64.AADDZE, + name: "CMPD", + argLen: 2, + asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372036854775808}, // XER - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "SUBZEzero", - argLen: 1, - asm: ppc64.ASUBZE, + name: "CMPshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372036854775808}, // XER - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SRADconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRAD, + name: "CMPshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SRAWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRAW, + name: "CMPshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - clobbers: 9223372036854775808, // XER - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SRDconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRD, + name: "CMNshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SRWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASRW, + name: "CMNshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SLDconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASLD, + name: "CMNshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "SLWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ASLW, + name: "TSTshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "ROTLconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AROTL, + name: "TSTshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "ROTLWconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AROTLW, + name: "TSTshiftRA", + auxType: auxInt32, + argLen: 2, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "EXTSWSLconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AEXTSWSLI, + name: "TEQshiftLL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "RLWINM", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLWNM, + name: "TEQshiftRL", + auxType: auxInt32, + argLen: 2, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "RLWNM", - auxType: auxInt64, + name: "TEQshiftRA", + auxType: auxInt32, argLen: 2, - asm: ppc64.ARLWNM, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "RLWMI", - auxType: auxInt64, - argLen: 2, - resultInArg0: true, - asm: ppc64.ARLWMI, + name: "CMPshiftLLreg", + argLen: 3, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "RLDICL", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLDICL, + name: "CMPshiftRLreg", + argLen: 3, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "RLDICLCC", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLDICLCC, + name: "CMPshiftRAreg", + argLen: 3, + asm: arm.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "RLDICR", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ARLDICR, + name: "CMNshiftLLreg", + argLen: 3, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CNTLZD", - argLen: 1, - asm: ppc64.ACNTLZD, + name: "CMNshiftRLreg", + argLen: 3, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CNTLZDCC", - argLen: 1, - asm: ppc64.ACNTLZDCC, + name: "CMNshiftRAreg", + argLen: 3, + asm: arm.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CNTLZW", - argLen: 1, - asm: ppc64.ACNTLZW, + name: "TSTshiftLLreg", + argLen: 3, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CNTTZD", - argLen: 1, - asm: ppc64.ACNTTZD, + name: "TSTshiftRLreg", + argLen: 3, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "CNTTZW", - argLen: 1, - asm: ppc64.ACNTTZW, + name: "TSTshiftRAreg", + argLen: 3, + asm: arm.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "POPCNTD", - argLen: 1, - asm: ppc64.APOPCNTD, + name: "TEQshiftLLreg", + argLen: 3, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "POPCNTW", - argLen: 1, - asm: ppc64.APOPCNTW, + name: "TEQshiftRLreg", + argLen: 3, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "POPCNTB", - argLen: 1, - asm: ppc64.APOPCNTB, + name: "TEQshiftRAreg", + argLen: 3, + asm: arm.ATEQ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FDIV", - argLen: 2, - asm: ppc64.AFDIV, + name: "CMPF0", + argLen: 1, + asm: arm.ACMPF, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FDIVS", - argLen: 2, - asm: ppc64.AFDIVS, + name: "CMPD0", + argLen: 1, + asm: arm.ACMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, + }, + }, + { + name: "MOVWconst", + auxType: auxInt32, + argLen: 0, + rematerializeable: true, + asm: arm.AMOVW, + reg: regInfo{ outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "DIVD", - argLen: 2, - asm: ppc64.ADIVD, + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: arm.AMOVF, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "DIVW", - argLen: 2, - asm: ppc64.ADIVW, + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: arm.AMOVD, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "DIVDU", - argLen: 2, - asm: ppc64.ADIVDU, + name: "MOVWaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294975488}, // SP SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "DIVWU", - argLen: 2, - asm: ppc64.ADIVWU, + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MODUD", - argLen: 2, - asm: ppc64.AMODUD, + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MODSD", - argLen: 2, - asm: ppc64.AMODSD, + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MODUW", - argLen: 2, - asm: ppc64.AMODUW, + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MODSW", - argLen: 2, - asm: ppc64.AMODSW, + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FCTIDZ", - argLen: 1, - asm: ppc64.AFCTIDZ, + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FCTIWZ", - argLen: 1, - asm: ppc64.AFCTIWZ, + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FCFID", - argLen: 1, - asm: ppc64.AFCFID, + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "FCFIDS", - argLen: 1, - asm: ppc64.AFCFIDS, + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "FRSP", - argLen: 1, - asm: ppc64.AFRSP, + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "MFVSRD", - argLen: 1, - asm: ppc64.AMFVSRD, + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "MTVSRD", - argLen: 1, - asm: ppc64.AMTVSRD, + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: ppc64.AAND, + name: "MOVWloadidx", + argLen: 3, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ANDN", - argLen: 2, - asm: ppc64.AANDN, + name: "MOVWloadshiftLL", + auxType: auxInt32, + argLen: 3, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ANDNCC", - argLen: 2, - asm: ppc64.AANDNCC, + name: "MOVWloadshiftRL", + auxType: auxInt32, + argLen: 3, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ANDCC", - argLen: 2, - commutative: true, - asm: ppc64.AANDCC, + name: "MOVWloadshiftRA", + auxType: auxInt32, + argLen: 3, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: ppc64.AOR, + name: "MOVBUloadidx", + argLen: 3, + asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ORN", - argLen: 2, - asm: ppc64.AORN, + name: "MOVBloadidx", + argLen: 3, + asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ORCC", - argLen: 2, - commutative: true, - asm: ppc64.AORCC, + name: "MOVHUloadidx", + argLen: 3, + asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "NOR", - argLen: 2, - commutative: true, - asm: ppc64.ANOR, + name: "MOVHloadidx", + argLen: 3, + asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "NORCC", - argLen: 2, - commutative: true, - asm: ppc64.ANORCC, + name: "MOVWstoreidx", + argLen: 4, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: ppc64.AXOR, + name: "MOVWstoreshiftLL", + auxType: auxInt32, + argLen: 4, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "XORCC", - argLen: 2, - commutative: true, - asm: ppc64.AXORCC, + name: "MOVWstoreshiftRL", + auxType: auxInt32, + argLen: 4, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "EQV", - argLen: 2, - commutative: true, - asm: ppc64.AEQV, + name: "MOVWstoreshiftRA", + auxType: auxInt32, + argLen: 4, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "NEG", - argLen: 1, - asm: ppc64.ANEG, + name: "MOVBstoreidx", + argLen: 4, + asm: arm.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "NEGCC", - argLen: 1, - asm: ppc64.ANEGCC, + name: "MOVHstoreidx", + argLen: 4, + asm: arm.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {2, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 + {0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB }, }, }, { - name: "BRD", + name: "MOVBreg", argLen: 1, - asm: ppc64.ABRD, + asm: arm.AMOVBS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "BRW", + name: "MOVBUreg", argLen: 1, - asm: ppc64.ABRW, + asm: arm.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "BRH", + name: "MOVHreg", argLen: 1, - asm: ppc64.ABRH, + asm: arm.AMOVHS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FNEG", + name: "MOVHUreg", argLen: 1, - asm: ppc64.AFNEG, + asm: arm.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FSQRT", + name: "MOVWreg", argLen: 1, - asm: ppc64.AFSQRT, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: ppc64.AFSQRTS, + name: "MOVWnop", + argLen: 1, + resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FFLOOR", + name: "MOVWF", argLen: 1, - asm: ppc64.AFRIM, + asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FCEIL", + name: "MOVWD", argLen: 1, - asm: ppc64.AFRIP, + asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FTRUNC", + name: "MOVWUF", argLen: 1, - asm: ppc64.AFRIZ, + asm: arm.AMOVWF, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FROUND", + name: "MOVWUD", argLen: 1, - asm: ppc64.AFRIN, + asm: arm.AMOVWD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "FABS", + name: "MOVFW", argLen: 1, - asm: ppc64.AFABS, + asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FNABS", + name: "MOVDW", argLen: 1, - asm: ppc64.AFNABS, + asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FCPSGN", - argLen: 2, - asm: ppc64.AFCPSGN, + name: "MOVFWU", + argLen: 1, + asm: arm.AMOVFW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AOR, + name: "MOVDWU", + argLen: 1, + asm: arm.AMOVDW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, + clobbers: 2147483648, // F15 outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AXOR, + name: "MOVFD", + argLen: 1, + asm: arm.AMOVFD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "ANDCCconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.AANDCC, + name: "MOVDF", + argLen: 1, + asm: arm.AMOVDF, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, - asm: ppc64.AANDCC, + name: "CMOVWHSconst", + auxType: auxInt32, + argLen: 2, + resultInArg0: true, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: ppc64.AMOVB, + name: "CMOVWLSconst", + auxType: auxInt32, + argLen: 2, + resultInArg0: true, + asm: arm.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBZreg", - argLen: 1, - asm: ppc64.AMOVBZ, + name: "SRAcond", + argLen: 3, + asm: arm.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: ppc64.AMOVH, + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, + clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "MOVHZreg", - argLen: 1, - asm: ppc64.AMOVHZ, + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, + clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "MOVWreg", - argLen: 1, - asm: ppc64.AMOVW, + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 128}, // R7 + {0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14 }, + clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "MOVWZreg", - argLen: 1, - asm: ppc64.AMOVWZ, + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "MOVBZload", - auxType: auxSymOff, + name: "LoweredNilCheck", argLen: 2, + nilCheck: true, faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVBZ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVH, + name: "Equal", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVHZ, + name: "NotEqual", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVW, + name: "LessThan", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVWZ, + name: "LessEqual", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AMOVD, + name: "GreaterThan", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVDBRload", - argLen: 2, - faultOnNilArg0: true, - asm: ppc64.AMOVDBR, + name: "GreaterEqual", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVWBRload", - argLen: 2, - faultOnNilArg0: true, - asm: ppc64.AMOVWBR, + name: "LessThanU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHBRload", - argLen: 2, - faultOnNilArg0: true, - asm: ppc64.AMOVHBR, + name: "LessEqualU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVBZloadidx", - argLen: 3, - asm: ppc64.AMOVBZ, + name: "GreaterThanU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHloadidx", - argLen: 3, - asm: ppc64.AMOVH, + name: "GreaterEqualU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVHZloadidx", - argLen: 3, - asm: ppc64.AMOVHZ, + name: "DUFFZERO", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 2}, // R1 + {1, 1}, // R0 }, + clobbers: 20482, // R1 R12 R14 }, }, { - name: "MOVWloadidx", - argLen: 3, - asm: ppc64.AMOVW, + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4}, // R2 + {1, 2}, // R1 }, + clobbers: 20487, // R0 R1 R2 R12 R14 }, }, { - name: "MOVWZloadidx", - argLen: 3, - asm: ppc64.AMOVWZ, + name: "LoweredZero", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 2}, // R1 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 2, // R1 }, }, { - name: "MOVDloadidx", - argLen: 3, - asm: ppc64.AMOVD, + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 4}, // R2 + {1, 2}, // R1 + {2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, + clobbers: 6, // R1 R2 }, }, { - name: "MOVHBRloadidx", - argLen: 3, - asm: ppc64.AMOVHBR, + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, reg: regInfo{ - inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 128}, // R7 }, }, }, { - name: "MOVWBRloadidx", - argLen: 3, - asm: ppc64.AMOVWBR, + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, reg: regInfo{ - inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "MOVDBRloadidx", - argLen: 3, - asm: ppc64.AMOVDBR, + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, reg: regInfo{ - inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { - name: "FMOVDloadidx", - argLen: 3, - asm: ppc64.AFMOVD, + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 4}, // R2 + {1, 8}, // R3 }, }, }, { - name: "FMOVSloadidx", - argLen: 3, - asm: ppc64.AFMOVS, + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, - outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 2}, // R1 + {1, 4}, // R2 }, }, }, { - name: "DCBT", - auxType: auxInt64, - argLen: 2, - hasSideEffects: true, - asm: ppc64.ADCBT, + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1}, // R0 + {1, 2}, // R1 }, }, }, { - name: "MOVDBRstore", - argLen: 3, - faultOnNilArg0: true, - asm: ppc64.AMOVDBR, + name: "LoweredPanicExtendA", + auxType: auxInt64, + argLen: 4, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 16}, // R4 + {1, 4}, // R2 + {2, 8}, // R3 }, }, }, { - name: "MOVWBRstore", - argLen: 3, - faultOnNilArg0: true, - asm: ppc64.AMOVWBR, + name: "LoweredPanicExtendB", + auxType: auxInt64, + argLen: 4, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 16}, // R4 + {1, 2}, // R1 + {2, 4}, // R2 }, }, }, { - name: "MOVHBRstore", - argLen: 3, - faultOnNilArg0: true, - asm: ppc64.AMOVHBR, + name: "LoweredPanicExtendC", + auxType: auxInt64, + argLen: 4, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 16}, // R4 + {1, 1}, // R0 + {2, 2}, // R1 }, }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AFMOVD, + name: "FlagConstant", + auxType: auxFlagConstant, + argLen: 0, + reg: regInfo{}, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - }, + clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 256}, // R8 }, }, }, + { - name: "FMOVSload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: ppc64.AFMOVS, + name: "ADCSflags", + argLen: 3, + commutative: true, + asm: arm64.AADCS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 0}, + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVB, + name: "ADCzerocarry", + argLen: 1, + asm: arm64.AADC, reg: regInfo{ - inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVH, + name: "ADD", + argLen: 2, + commutative: true, + asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVW, + name: "ADDconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1476395007}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP }, - }, - }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, + }, { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVD, + name: "ADDSconstflags", + auxType: auxInt64, + argLen: 1, + asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {1, 0}, + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AFMOVD, + name: "ADDSflags", + argLen: 2, + commutative: true, + asm: arm64.AADDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, 0}, + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVSstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AFMOVS, + name: "SUB", + argLen: 2, + asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBstoreidx", - argLen: 4, - asm: ppc64.AMOVB, + name: "SUBconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHstoreidx", - argLen: 4, - asm: ppc64.AMOVH, + name: "SBCSflags", + argLen: 3, + asm: arm64.ASBCS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, 0}, + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWstoreidx", - argLen: 4, - asm: ppc64.AMOVW, + name: "SUBSflags", + argLen: 2, + asm: arm64.ASUBS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {1, 0}, + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDstoreidx", - argLen: 4, - asm: ppc64.AMOVD, + name: "MUL", + argLen: 2, + commutative: true, + asm: arm64.AMUL, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVDstoreidx", - argLen: 4, - asm: ppc64.AFMOVD, + name: "MULW", + argLen: 2, + commutative: true, + asm: arm64.AMULW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVSstoreidx", - argLen: 4, - asm: ppc64.AFMOVS, + name: "MNEG", + argLen: 2, + commutative: true, + asm: arm64.AMNEG, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHBRstoreidx", - argLen: 4, - asm: ppc64.AMOVHBR, + name: "MNEGW", + argLen: 2, + commutative: true, + asm: arm64.AMNEGW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWBRstoreidx", - argLen: 4, - asm: ppc64.AMOVWBR, + name: "MULH", + argLen: 2, + commutative: true, + asm: arm64.ASMULH, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDBRstoreidx", - argLen: 4, - asm: ppc64.AMOVDBR, + name: "UMULH", + argLen: 2, + commutative: true, + asm: arm64.AUMULH, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVB, + name: "MULL", + argLen: 2, + commutative: true, + asm: arm64.ASMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVH, + name: "UMULL", + argLen: 2, + commutative: true, + asm: arm64.AUMULL, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVW, + name: "DIV", + argLen: 2, + asm: arm64.ASDIV, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: ppc64.AMOVD, + name: "UDIV", + argLen: 2, + asm: arm64.AUDIV, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: ppc64.AMOVD, + name: "DIVW", + argLen: 2, + asm: arm64.ASDIVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: ppc64.AMOVD, + name: "UDIVW", + argLen: 2, + asm: arm64.AUDIVW, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVDconst", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, - asm: ppc64.AFMOVD, + name: "MOD", + argLen: 2, + asm: arm64.AREM, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVSconst", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, - asm: ppc64.AFMOVS, + name: "UMOD", + argLen: 2, + asm: arm64.AUREM, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCMPU", + name: "MODW", argLen: 2, - asm: ppc64.AFCMPU, + asm: arm64.AREMW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 - {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CMP", + name: "UMODW", argLen: 2, - asm: ppc64.ACMP, + asm: arm64.AUREMW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CMPU", - argLen: 2, - asm: ppc64.ACMPU, + name: "FADDS", + argLen: 2, + commutative: true, + asm: arm64.AFADDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CMPW", - argLen: 2, - asm: ppc64.ACMPW, + name: "FADDD", + argLen: 2, + commutative: true, + asm: arm64.AFADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CMPWU", + name: "FSUBS", argLen: 2, - asm: ppc64.ACMPWU, + asm: arm64.AFSUBS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CMPconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ACMP, + name: "FSUBD", + argLen: 2, + asm: arm64.AFSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CMPUconst", - auxType: auxInt64, - argLen: 1, - asm: ppc64.ACMPU, + name: "FMULS", + argLen: 2, + commutative: true, + asm: arm64.AFMULS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CMPWconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACMPW, + name: "FMULD", + argLen: 2, + commutative: true, + asm: arm64.AFMULD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CMPWUconst", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ACMPWU, + name: "FNMULS", + argLen: 2, + commutative: true, + asm: arm64.AFNMULS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ISEL", - auxType: auxInt32, - argLen: 3, - asm: ppc64.AISEL, + name: "FNMULD", + argLen: 2, + commutative: true, + asm: arm64.AFNMULD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ISELZ", - auxType: auxInt32, - argLen: 2, - asm: ppc64.AISEL, + name: "FDIVS", + argLen: 2, + asm: arm64.AFDIVS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SETBC", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ASETBC, + name: "FDIVD", + argLen: 2, + asm: arm64.AFDIVD, reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SETBCR", - auxType: auxInt32, - argLen: 1, - asm: ppc64.ASETBCR, + name: "AND", + argLen: 2, + commutative: true, + asm: arm64.AAND, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "Equal", - argLen: 1, + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AAND, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "NotEqual", - argLen: 1, + name: "OR", + argLen: 2, + commutative: true, + asm: arm64.AORR, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LessThan", - argLen: 1, + name: "ORconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AORR, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FLessThan", - argLen: 1, + name: "XOR", + argLen: 2, + commutative: true, + asm: arm64.AEOR, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LessEqual", - argLen: 1, + name: "XORconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AEOR, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FLessEqual", - argLen: 1, + name: "BIC", + argLen: 2, + asm: arm64.ABIC, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "GreaterThan", - argLen: 1, + name: "EON", + argLen: 2, + asm: arm64.AEON, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FGreaterThan", - argLen: 1, + name: "ORN", + argLen: 2, + asm: arm64.AORN, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "GreaterEqual", + name: "MVN", argLen: 1, + asm: arm64.AMVN, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FGreaterEqual", + name: "NEG", argLen: 1, + asm: arm64.ANEG, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "NEGSflags", + argLen: 1, + asm: arm64.ANEGS, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 2048}, // R11 + {1, 0}, + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "NGCzerocarry", + argLen: 1, + asm: arm64.ANGC, reg: regInfo{ outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "FABSD", + argLen: 1, + asm: arm64.AFABSD, reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - clobberFlags: true, - nilCheck: true, - faultOnNilArg0: true, + name: "FNEGS", + argLen: 1, + asm: arm64.AFNEGS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, - clobbers: 2147483648, // R31 }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "FNEGD", + argLen: 1, + asm: arm64.AFNEGD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "FSQRTD", + argLen: 1, + asm: arm64.AFSQRTD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - reg: regInfo{ - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER - }, - }, - { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, - tailCall: true, + name: "FSQRTS", + argLen: 1, + asm: arm64.AFSQRTS, reg: regInfo{ - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "FMIND", + argLen: 2, + asm: arm64.AFMIND, reg: regInfo{ inputs: []inputInfo{ - {0, 4096}, // R12 - {1, 2048}, // R11 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - clobberFlags: true, - call: true, + name: "FMINS", + argLen: 2, + asm: arm64.AFMINS, reg: regInfo{ inputs: []inputInfo{ - {0, 4096}, // R12 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, - clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, - unsafePoint: true, + name: "FMAXD", + argLen: 2, + asm: arm64.AFMAXD, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, - clobbers: 1048576, // R20 }, }, { - name: "LoweredZeroShort", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, - unsafePoint: true, + name: "FMAXS", + argLen: 2, + asm: arm64.AFMAXS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredQuadZeroShort", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, - unsafePoint: true, + name: "REV", + argLen: 1, + asm: arm64.AREV, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredQuadZero", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, - unsafePoint: true, + name: "REVW", + argLen: 1, + asm: arm64.AREVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, - clobbers: 1048576, // R20 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "REV16", + argLen: 1, + asm: arm64.AREV16, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 - {1, 2097152}, // R21 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, - clobbers: 3145728, // R20 R21 }, }, { - name: "LoweredMoveShort", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "REV16W", + argLen: 1, + asm: arm64.AREV16W, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredQuadMove", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "RBIT", + argLen: 1, + asm: arm64.ARBIT, reg: regInfo{ inputs: []inputInfo{ - {0, 1048576}, // R20 - {1, 2097152}, // R21 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, - clobbers: 3145728, // R20 R21 }, }, { - name: "LoweredQuadMoveShort", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - unsafePoint: true, + name: "RBITW", + argLen: 1, + asm: arm64.ARBITW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredAtomicStore8", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "CLZ", + argLen: 1, + asm: arm64.ACLZ, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredAtomicStore32", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "CLZW", + argLen: 1, + asm: arm64.ACLZW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredAtomicStore64", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, + name: "VCNT", + argLen: 1, + asm: arm64.AVCNT, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicLoad8", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "VUADDLV", + argLen: 1, + asm: arm64.AVUADDLV, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicLoad32", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicLoad64", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicLoadPtr", - auxType: auxInt64, - argLen: 2, - clobberFlags: true, - faultOnNilArg0: true, + name: "FMADDS", + argLen: 3, + asm: arm64.AFMADDS, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FMADDD", + argLen: 3, + asm: arm64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FNMADDS", + argLen: 3, + asm: arm64.AFNMADDS, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicExchange8", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FNMADDD", + argLen: 3, + asm: arm64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FMSUBS", + argLen: 3, + asm: arm64.AFMSUBS, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FMSUBD", + argLen: 3, + asm: arm64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicCas64", - auxType: auxInt64, - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FNMSUBS", + argLen: 3, + asm: arm64.AFNMSUBS, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicCas32", - auxType: auxInt64, - argLen: 4, - resultNotInArgs: true, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FNMSUBD", + argLen: 3, + asm: arm64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicAnd8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AAND, + name: "MADD", + argLen: 3, + asm: arm64.AMADD, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AAND, + name: "MADDW", + argLen: 3, + asm: arm64.AMADDW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredAtomicOr8", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AOR, + name: "MSUB", + argLen: 3, + asm: arm64.AMSUB, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: ppc64.AOR, + name: "MSUBW", + argLen: 3, + asm: arm64.AMSUBW, reg: regInfo{ inputs: []inputInfo{ - {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 - {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {2, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "SLL", + argLen: 2, + asm: arm64.ALSL, reg: regInfo{ - clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 536870912}, // R29 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: ppc64.ALWSYNC, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsA", + name: "SLLconst", auxType: auxInt64, - argLen: 3, - call: true, + argLen: 1, + asm: arm64.ALSL, reg: regInfo{ inputs: []inputInfo{ - {0, 32}, // R5 - {1, 64}, // R6 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "SRL", + argLen: 2, + asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // R4 - {1, 32}, // R5 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredPanicBoundsC", + name: "SRLconst", auxType: auxInt64, - argLen: 3, - call: true, + argLen: 1, + asm: arm64.ALSR, reg: regInfo{ inputs: []inputInfo{ - {0, 8}, // R3 - {1, 16}, // R4 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "InvertFlags", - argLen: 1, - reg: regInfo{}, - }, - { - name: "FlagEQ", - argLen: 0, - reg: regInfo{}, + name: "SRA", + argLen: 2, + asm: arm64.AASR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, }, { - name: "FlagLT", - argLen: 0, - reg: regInfo{}, + name: "SRAconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.AASR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, }, { - name: "FlagGT", - argLen: 0, - reg: regInfo{}, + name: "ROR", + argLen: 2, + asm: arm64.AROR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + }, }, - { - name: "ADD", - argLen: 2, - commutative: true, - asm: riscv.AADD, + name: "RORW", + argLen: 2, + asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDI", + name: "RORconst", auxType: auxInt64, argLen: 1, - asm: riscv.AADDI, + asm: arm64.AROR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDIW", + name: "RORWconst", auxType: auxInt64, argLen: 1, - asm: riscv.AADDIW, + asm: arm64.ARORW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "NEG", - argLen: 1, - asm: riscv.ANEG, + name: "EXTRconst", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEXTR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "NEGW", - argLen: 1, - asm: riscv.ANEGW, + name: "EXTRWconst", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEXTRW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUB", + name: "CMP", argLen: 2, - asm: riscv.ASUB, + asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + { + name: "CMPconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "SUBW", + name: "CMPW", argLen: 2, - asm: riscv.ASUBW, + asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "MUL", - argLen: 2, - commutative: true, - asm: riscv.AMUL, + name: "CMPWconst", + auxType: auxInt32, + argLen: 1, + asm: arm64.ACMPW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "MULW", + name: "CMN", argLen: 2, commutative: true, - asm: riscv.AMULW, + asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + { + name: "CMNconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ACMN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "MULH", + name: "CMNW", argLen: 2, commutative: true, - asm: riscv.AMULH, + asm: arm64.ACMNW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + { + name: "CMNWconst", + auxType: auxInt32, + argLen: 1, + asm: arm64.ACMNW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "MULHU", + name: "TST", argLen: 2, commutative: true, - asm: riscv.AMULHU, + asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "LoweredMuluhilo", - argLen: 2, - resultNotInArgs: true, + name: "TSTconst", + auxType: auxInt64, + argLen: 1, + asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "LoweredMuluover", - argLen: 2, - resultNotInArgs: true, + name: "TSTW", + argLen: 2, + commutative: true, + asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "DIV", - argLen: 2, - asm: riscv.ADIV, + name: "TSTWconst", + auxType: auxInt32, + argLen: 1, + asm: arm64.ATSTW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "DIVU", + name: "FCMPS", argLen: 2, - asm: riscv.ADIVU, + asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "DIVW", + name: "FCMPD", argLen: 2, - asm: riscv.ADIVW, + asm: arm64.AFCMPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "DIVUW", - argLen: 2, - asm: riscv.ADIVUW, + name: "FCMPS0", + argLen: 1, + asm: arm64.AFCMPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + { + name: "FCMPD0", + argLen: 1, + asm: arm64.AFCMPD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "REM", - argLen: 2, - asm: riscv.AREM, + name: "MVNshiftLL", + auxType: auxInt64, + argLen: 1, + asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "REMU", - argLen: 2, - asm: riscv.AREMU, + name: "MVNshiftRL", + auxType: auxInt64, + argLen: 1, + asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "REMW", - argLen: 2, - asm: riscv.AREMW, + name: "MVNshiftRA", + auxType: auxInt64, + argLen: 1, + asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "REMUW", - argLen: 2, - asm: riscv.AREMUW, + name: "MVNshiftRO", + auxType: auxInt64, + argLen: 1, + asm: arm64.AMVN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, - asm: riscv.AMOV, + name: "NEGshiftLL", + auxType: auxInt64, + argLen: 1, + asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: riscv.AMOV, + name: "NEGshiftRL", + auxType: auxInt64, + argLen: 1, + asm: arm64.ANEG, reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVB, + name: "NEGshiftRA", + auxType: auxInt64, + argLen: 1, + asm: arm64.ANEG, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVH, + name: "ADDshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVW, + name: "ADDshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOV, + name: "ADDshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.AADD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVBU, + name: "SUBshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVHU, + name: "SUBshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWUload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVWU, + name: "SUBshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ASUB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVB, + name: "ANDshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - }, - }, - { - name: "MOVHstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVH, - reg: regInfo{ - inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVW, + name: "ANDshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - }, - }, - { - name: "MOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOV, - reg: regInfo{ - inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVB, + name: "ANDshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVH, + name: "ANDshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVW, + name: "ORshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDstorezero", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOV, + name: "ORshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: riscv.AMOVB, + name: "ORshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: riscv.AMOVH, + name: "ORshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: riscv.AMOVW, + name: "XORshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDreg", - argLen: 1, - asm: riscv.AMOV, + name: "XORshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVBUreg", - argLen: 1, - asm: riscv.AMOVBU, + name: "XORshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVHUreg", - argLen: 1, - asm: riscv.AMOVHU, + name: "XORshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEOR, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVWUreg", - argLen: 1, - asm: riscv.AMOVWU, + name: "BICshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MOVDnop", - argLen: 1, - resultInArg0: true, + name: "BICshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLL", - argLen: 2, - asm: riscv.ASLL, + name: "BICshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLLW", - argLen: 2, - asm: riscv.ASLLW, + name: "BICshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.ABIC, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRA", - argLen: 2, - asm: riscv.ASRA, + name: "EONshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRAW", - argLen: 2, - asm: riscv.ASRAW, + name: "EONshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRL", - argLen: 2, - asm: riscv.ASRL, + name: "EONshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRLW", - argLen: 2, - asm: riscv.ASRLW, + name: "EONshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.AEON, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLLI", + name: "ORNshiftLL", auxType: auxInt64, - argLen: 1, - asm: riscv.ASLLI, + argLen: 2, + asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLLIW", + name: "ORNshiftRL", auxType: auxInt64, - argLen: 1, - asm: riscv.ASLLIW, + argLen: 2, + asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRAI", + name: "ORNshiftRA", auxType: auxInt64, - argLen: 1, - asm: riscv.ASRAI, + argLen: 2, + asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRAIW", + name: "ORNshiftRO", auxType: auxInt64, - argLen: 1, - asm: riscv.ASRAIW, + argLen: 2, + asm: arm64.AORN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SRLI", + name: "CMPshiftLL", auxType: auxInt64, - argLen: 1, - asm: riscv.ASRLI, + argLen: 2, + asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "SRLIW", + name: "CMPshiftRL", auxType: auxInt64, - argLen: 1, - asm: riscv.ASRLIW, + argLen: 2, + asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "SH1ADD", - argLen: 2, - asm: riscv.ASH1ADD, + name: "CMPshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMP, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "SH2ADD", - argLen: 2, - asm: riscv.ASH2ADD, + name: "CMNshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "SH3ADD", - argLen: 2, - asm: riscv.ASH3ADD, + name: "CMNshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - asm: riscv.AAND, + name: "CMNshiftRA", + auxType: auxInt64, + argLen: 2, + asm: arm64.ACMN, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "ANDN", - argLen: 2, - asm: riscv.AANDN, + name: "TSTshiftLL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + { + name: "TSTshiftRL", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "ANDI", + name: "TSTshiftRA", auxType: auxInt64, - argLen: 1, - asm: riscv.AANDI, + argLen: 2, + asm: arm64.ATST, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + { + name: "TSTshiftRO", + auxType: auxInt64, + argLen: 2, + asm: arm64.ATST, + reg: regInfo{ + inputs: []inputInfo{ + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "CLZ", - argLen: 1, - asm: riscv.ACLZ, + name: "BFI", + auxType: auxARM64BitField, + argLen: 2, + resultInArg0: true, + asm: arm64.ABFI, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CLZW", - argLen: 1, - asm: riscv.ACLZW, + name: "BFXIL", + auxType: auxARM64BitField, + argLen: 2, + resultInArg0: true, + asm: arm64.ABFXIL, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CPOP", - argLen: 1, - asm: riscv.ACPOP, + name: "SBFIZ", + auxType: auxARM64BitField, + argLen: 1, + asm: arm64.ASBFIZ, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CPOPW", - argLen: 1, - asm: riscv.ACPOPW, + name: "SBFX", + auxType: auxARM64BitField, + argLen: 1, + asm: arm64.ASBFX, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CTZ", - argLen: 1, - asm: riscv.ACTZ, + name: "UBFIZ", + auxType: auxARM64BitField, + argLen: 1, + asm: arm64.AUBFIZ, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CTZW", - argLen: 1, - asm: riscv.ACTZW, + name: "UBFX", + auxType: auxARM64BitField, + argLen: 1, + asm: arm64.AUBFX, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "NOT", - argLen: 1, - asm: riscv.ANOT, + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: arm64.AMOVD, reg: regInfo{ - inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - asm: riscv.AOR, + name: "FMOVSconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: arm64.AFMOVS, reg: regInfo{ - inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: arm64.AFMOVD, + reg: regInfo{ outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ORN", - argLen: 2, - asm: riscv.AORN, + name: "MOVDaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037928517632}, // SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ORI", - auxType: auxInt64, - argLen: 1, - asm: riscv.AORI, + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "REV8", - argLen: 1, - asm: riscv.AREV8, + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ROL", - argLen: 2, - asm: riscv.AROL, + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ROLW", - argLen: 2, - asm: riscv.AROLW, + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ROR", - argLen: 2, - asm: riscv.AROR, + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "RORI", - auxType: auxInt64, - argLen: 1, - asm: riscv.ARORI, + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "RORIW", - auxType: auxInt64, - argLen: 1, - asm: riscv.ARORIW, + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "RORW", - argLen: 2, - asm: riscv.ARORW, + name: "FMOVSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "XNOR", - argLen: 2, - commutative: true, - asm: riscv.AXNOR, + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - asm: riscv.AXOR, + name: "LDP", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.ALDP, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "XORI", - auxType: auxInt64, - argLen: 1, - asm: riscv.AXORI, + name: "LDPW", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.ALDPW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "MIN", - argLen: 2, - commutative: true, - asm: riscv.AMIN, + name: "LDPSW", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.ALDPSW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "MAX", - argLen: 2, - commutative: true, - asm: riscv.AMAX, + name: "FLDPD", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AFLDPD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MINU", - argLen: 2, - commutative: true, - asm: riscv.AMINU, + name: "FLDPS", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: arm64.AFLDPS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MAXU", - argLen: 2, - commutative: true, - asm: riscv.AMAXU, + name: "MOVDloadidx", + argLen: 3, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SEQZ", - argLen: 1, - asm: riscv.ASEQZ, + name: "MOVWloadidx", + argLen: 3, + asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SNEZ", - argLen: 1, - asm: riscv.ASNEZ, + name: "MOVWUloadidx", + argLen: 3, + asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLT", - argLen: 2, - asm: riscv.ASLT, + name: "MOVHloadidx", + argLen: 3, + asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLTI", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASLTI, + name: "MOVHUloadidx", + argLen: 3, + asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLTU", - argLen: 2, - asm: riscv.ASLTU, + name: "MOVBloadidx", + argLen: 3, + asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SLTIU", - auxType: auxInt64, - argLen: 1, - asm: riscv.ASLTIU, + name: "MOVBUloadidx", + argLen: 3, + asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, + name: "FMOVSloadidx", + argLen: 3, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -34394,12 +38425,13 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, + name: "FMOVDloadidx", + argLen: 3, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -34407,410 +38439,386 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "MOVHloadidx2", + argLen: 3, + asm: arm64.AMOVH, reg: regInfo{ - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: -1, - call: true, - tailCall: true, + name: "MOVHUloadidx2", + argLen: 3, + asm: arm64.AMOVHU, reg: regInfo{ - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + inputs: []inputInfo{ + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "MOVWloadidx4", + argLen: 3, + asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 33554432}, // X26 - {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, - { - name: "CALLinter", - auxType: auxCallOff, - argLen: -1, - call: true, - reg: regInfo{ - inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, - clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "DUFFZERO", - auxType: auxInt64, - argLen: 2, - faultOnNilArg0: true, + name: "MOVWUloadidx4", + argLen: 3, + asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 16777216}, // X25 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 16777216, // X25 - }, - }, - { - name: "DUFFCOPY", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, - faultOnNilArg1: true, - reg: regInfo{ - inputs: []inputInfo{ - {0, 16777216}, // X25 - {1, 8388608}, // X24 + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, - clobbers: 25165824, // X24 X25 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 3, - faultOnNilArg0: true, + name: "MOVDloadidx8", + argLen: 3, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // X5 - {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, - clobbers: 16, // X5 }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "FMOVSloadidx4", + argLen: 3, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // X5 - {1, 32}, // X6 - {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, - clobbers: 112, // X5 X6 X7 }, }, { - name: "LoweredAtomicLoad8", - argLen: 2, - faultOnNilArg0: true, + name: "FMOVDloadidx8", + argLen: 3, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicLoad32", - argLen: 2, + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicLoad64", - argLen: 2, + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicStore8", + name: "MOVWstore", + auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, - hasSideEffects: true, + symEffect: SymWrite, + asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicStore32", + name: "MOVDstore", + auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, - hasSideEffects: true, + symEffect: SymWrite, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicStore64", + name: "FMOVSstore", + auxType: auxSymOff, argLen: 3, faultOnNilArg0: true, - hasSideEffects: true, + symEffect: SymWrite, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicExchange32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicExchange64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, + name: "STP", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.ASTP, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicAdd32", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "STPW", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.ASTPW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicAdd64", - argLen: 3, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "FSTPD", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.AFSTPD, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicCas32", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "FSTPS", + auxType: auxSymOff, + argLen: 4, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: arm64.AFSTPS, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredAtomicCas64", - argLen: 4, - resultNotInArgs: true, - faultOnNilArg0: true, - hasSideEffects: true, - unsafePoint: true, + name: "MOVBstoreidx", + argLen: 4, + asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicAnd32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: riscv.AAMOANDW, + name: "MOVHstoreidx", + argLen: 4, + asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredAtomicOr32", - argLen: 3, - faultOnNilArg0: true, - hasSideEffects: true, - asm: riscv.AAMOORW, + name: "MOVWstoreidx", + argLen: 4, + asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 - {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "MOVDstoreidx", + argLen: 4, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, + name: "FMOVSstoreidx", + argLen: 4, + asm: arm64.AFMOVS, reg: regInfo{ - outputs: []outputInfo{ - {0, 33554432}, // X26 + inputs: []inputInfo{ + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "FMOVDstoreidx", + argLen: 4, + asm: arm64.AFMOVD, reg: regInfo{ - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + inputs: []inputInfo{ + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "MOVHstoreidx2", + argLen: 4, + asm: arm64.AMOVH, reg: regInfo{ - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + inputs: []inputInfo{ + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "MOVWstoreidx4", + argLen: 4, + asm: arm64.AMOVW, reg: regInfo{ - clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - outputs: []outputInfo{ - {0, 8388608}, // X24 + inputs: []inputInfo{ + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredPubBarrier", - argLen: 1, - hasSideEffects: true, - asm: riscv.AFENCE, - reg: regInfo{}, - }, - { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "MOVDstoreidx8", + argLen: 4, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 64}, // X7 - {1, 134217728}, // X28 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "FMOVSstoreidx4", + argLen: 4, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {0, 32}, // X6 - {1, 64}, // X7 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "FMOVDstoreidx8", + argLen: 4, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 16}, // X5 - {1, 32}, // X6 + {1, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FADDS", - argLen: 2, - commutative: true, - asm: riscv.AFADDS, + name: "FMOVDgpfp", + argLen: 1, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -34818,28 +38826,25 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FSUBS", - argLen: 2, - asm: riscv.AFSUBS, + name: "FMOVDfpgp", + argLen: 1, + asm: arm64.AFMOVD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - asm: riscv.AFMULS, + name: "FMOVSgpfp", + argLen: 1, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -34847,142 +38852,129 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FDIVS", - argLen: 2, - asm: riscv.AFDIVS, + name: "FMOVSfpgp", + argLen: 1, + asm: arm64.AFMOVS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMADDS", - argLen: 3, - commutative: true, - asm: riscv.AFMADDS, + name: "MOVBreg", + argLen: 1, + asm: arm64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMSUBS", - argLen: 3, - commutative: true, - asm: riscv.AFMSUBS, + name: "MOVBUreg", + argLen: 1, + asm: arm64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FNMADDS", - argLen: 3, - commutative: true, - asm: riscv.AFNMADDS, + name: "MOVHreg", + argLen: 1, + asm: arm64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FNMSUBS", - argLen: 3, - commutative: true, - asm: riscv.AFNMSUBS, + name: "MOVHUreg", + argLen: 1, + asm: arm64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FSQRTS", + name: "MOVWreg", argLen: 1, - asm: riscv.AFSQRTS, + asm: arm64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FNEGS", + name: "MOVWUreg", argLen: 1, - asm: riscv.AFNEGS, + asm: arm64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMVSX", + name: "MOVDreg", argLen: 1, - asm: riscv.AFMVSX, + asm: arm64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTSW", - argLen: 1, - asm: riscv.AFCVTSW, + name: "MOVDnop", + argLen: 1, + resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTSL", + name: "SCVTFWS", argLen: 1, - asm: riscv.AFCVTSL, + asm: arm64.ASCVTFWS, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -34990,41 +38982,38 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FCVTWS", + name: "SCVTFWD", argLen: 1, - asm: riscv.AFCVTWS, + asm: arm64.ASCVTFWD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FCVTLS", + name: "UCVTFWS", argLen: 1, - asm: riscv.AFCVTLS, + asm: arm64.AUCVTFWS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FMOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVF, + name: "UCVTFWD", + argLen: 1, + asm: arm64.AUCVTFWD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35032,193 +39021,168 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FMOVWstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVF, + name: "SCVTFS", + argLen: 1, + asm: arm64.ASCVTFS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FEQS", - argLen: 2, - commutative: true, - asm: riscv.AFEQS, + name: "SCVTFD", + argLen: 1, + asm: arm64.ASCVTFD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FNES", - argLen: 2, - commutative: true, - asm: riscv.AFNES, + name: "UCVTFS", + argLen: 1, + asm: arm64.AUCVTFS, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FLTS", - argLen: 2, - asm: riscv.AFLTS, + name: "UCVTFD", + argLen: 1, + asm: arm64.AUCVTFD, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FLES", - argLen: 2, - asm: riscv.AFLES, + name: "FCVTZSSW", + argLen: 1, + asm: arm64.AFCVTZSSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredFMAXS", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMAXS, + name: "FCVTZSDW", + argLen: 1, + asm: arm64.AFCVTZSDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredFMINS", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMINS, + name: "FCVTZUSW", + argLen: 1, + asm: arm64.AFCVTZUSW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FADDD", - argLen: 2, - commutative: true, - asm: riscv.AFADDD, + name: "FCVTZUDW", + argLen: 1, + asm: arm64.AFCVTZUDW, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FSUBD", - argLen: 2, - asm: riscv.AFSUBD, + name: "FCVTZSS", + argLen: 1, + asm: arm64.AFCVTZSS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMULD", - argLen: 2, - commutative: true, - asm: riscv.AFMULD, + name: "FCVTZSD", + argLen: 1, + asm: arm64.AFCVTZSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FDIVD", - argLen: 2, - asm: riscv.AFDIVD, + name: "FCVTZUS", + argLen: 1, + asm: arm64.AFCVTZUS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMADDD", - argLen: 3, - commutative: true, - asm: riscv.AFMADDD, + name: "FCVTZUD", + argLen: 1, + asm: arm64.AFCVTZUD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMSUBD", - argLen: 3, - commutative: true, - asm: riscv.AFMSUBD, + name: "FCVTSD", + argLen: 1, + asm: arm64.AFCVTSD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35226,15 +39190,12 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FNMADDD", - argLen: 3, - commutative: true, - asm: riscv.AFNMADDD, + name: "FCVTDS", + argLen: 1, + asm: arm64.AFCVTDS, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35242,15 +39203,12 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FNMSUBD", - argLen: 3, - commutative: true, - asm: riscv.AFNMSUBD, + name: "FRINTAD", + argLen: 1, + asm: arm64.AFRINTAD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35258,9 +39216,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FSQRTD", + name: "FRINTMD", argLen: 1, - asm: riscv.AFSQRTD, + asm: arm64.AFRINTMD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35271,9 +39229,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FNEGD", + name: "FRINTND", argLen: 1, - asm: riscv.AFNEGD, + asm: arm64.AFRINTND, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35284,9 +39242,9 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FABSD", + name: "FRINTPD", argLen: 1, - asm: riscv.AFABSD, + asm: arm64.AFRINTPD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35297,13 +39255,12 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FSGNJD", - argLen: 2, - asm: riscv.AFSGNJD, + name: "FRINTZD", + argLen: 1, + asm: arm64.AFRINTZD, reg: regInfo{ inputs: []inputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 @@ -35311,7370 +39268,28465 @@ var opcodeTable = [...]opInfo{ }, }, { - name: "FMVDX", - argLen: 1, - asm: riscv.AFMVDX, + name: "CSEL", + auxType: auxCCop, + argLen: 3, + asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTDW", - argLen: 1, - asm: riscv.AFCVTDW, + name: "CSEL0", + auxType: auxCCop, + argLen: 2, + asm: arm64.ACSEL, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTDL", - argLen: 1, - asm: riscv.AFCVTDL, + name: "CSINC", + auxType: auxCCop, + argLen: 3, + asm: arm64.ACSINC, reg: regInfo{ inputs: []inputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTWD", - argLen: 1, - asm: riscv.AFCVTWD, + name: "CSINV", + auxType: auxCCop, + argLen: 3, + asm: arm64.ACSINV, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTLD", - argLen: 1, - asm: riscv.AFCVTLD, + name: "CSNEG", + auxType: auxCCop, + argLen: 3, + asm: arm64.ACSNEG, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTDS", - argLen: 1, - asm: riscv.AFCVTDS, + name: "CSETM", + auxType: auxCCop, + argLen: 1, + asm: arm64.ACSETM, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FCVTSD", - argLen: 1, - asm: riscv.AFCVTSD, + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, + clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: riscv.AMOVD, + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - }, - outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, + clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "FMOVDstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: riscv.AMOVD, + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 33554432}, // R26 + {0, 1409286143}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP }, + clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "FEQD", - argLen: 2, - commutative: true, - asm: riscv.AFEQD, + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, + clobbers: 9223372035109945343, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "FNED", - argLen: 2, - commutative: true, - asm: riscv.AFNED, + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 402653183}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 }, }, }, { - name: "FLTD", - argLen: 2, - asm: riscv.AFLTD, + name: "Equal", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FLED", - argLen: 2, - asm: riscv.AFLED, + name: "NotEqual", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, outputs: []outputInfo{ - {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredFMIND", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMIND, + name: "LessThan", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LoweredFMAXD", - argLen: 2, - commutative: true, - resultNotInArgs: true, - asm: riscv.AFMAXD, + name: "LessEqual", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, outputs: []outputInfo{ - {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, - { - name: "FADDS", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFADDS, + name: "GreaterThan", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FADD", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFADD, + name: "GreaterEqual", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FSUBS", - argLen: 2, - resultInArg0: true, - asm: s390x.AFSUBS, + name: "LessThanU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FSUB", - argLen: 2, - resultInArg0: true, - asm: s390x.AFSUB, + name: "LessEqualU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMULS", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFMULS, + name: "GreaterThanU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMUL", - argLen: 2, - commutative: true, - resultInArg0: true, - asm: s390x.AFMUL, + name: "GreaterEqualU", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FDIVS", - argLen: 2, - resultInArg0: true, - asm: s390x.AFDIVS, + name: "LessThanF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FDIV", - argLen: 2, - resultInArg0: true, - asm: s390x.AFDIV, + name: "LessEqualF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FNEGS", - argLen: 1, - clobberFlags: true, - asm: s390x.AFNEGS, + name: "GreaterThanF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FNEG", - argLen: 1, - clobberFlags: true, - asm: s390x.AFNEG, + name: "GreaterEqualF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMADDS", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMADDS, + name: "NotLessThanF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMADD", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMADD, + name: "NotLessEqualF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMSUBS", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMSUBS, + name: "NotGreaterThanF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMSUB", - argLen: 3, - resultInArg0: true, - asm: s390x.AFMSUB, + name: "NotGreaterEqualF", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LPDFR", + name: "LessThanNoov", argLen: 1, - asm: s390x.ALPDFR, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "LNDFR", + name: "GreaterEqualNoov", argLen: 1, - asm: s390x.ALNDFR, reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "CPSDR", - argLen: 2, - asm: s390x.ACPSDR, + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 524288}, // R20 }, + clobbers: 269156352, // R16 R17 R20 R30 }, }, { - name: "FIDBR", - auxType: auxInt8, - argLen: 1, - asm: s390x.AFIDBR, + name: "LoweredZero", + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 65536}, // R16 + {1, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, + clobbers: 65536, // R16 }, }, { - name: "FMOVSload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AFMOVS, + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1048576}, // R21 + {1, 524288}, // R20 }, + clobbers: 303759360, // R16 R17 R20 R21 R26 R30 }, }, { - name: "FMOVDload", - auxType: auxSymOff, - argLen: 2, + name: "LoweredMove", + argLen: 4, + clobberFlags: true, faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AFMOVD, + faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 131072}, // R17 + {1, 65536}, // R16 + {2, 318767103}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R26 R30 }, + clobbers: 16973824, // R16 R17 R25 + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 33554432}, // R26 }, }, }, { - name: "FMOVSconst", - auxType: auxFloat32, - argLen: 0, + name: "LoweredGetCallerSP", + argLen: 1, rematerializeable: true, - asm: s390x.AFMOVS, reg: regInfo{ outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVDconst", - auxType: auxFloat64, + name: "LoweredGetCallerPC", argLen: 0, rematerializeable: true, - asm: s390x.AFMOVD, reg: regInfo{ outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVSloadidx", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: s390x.AFMOVS, + name: "FlagConstant", + auxType: auxFlagConstant, + argLen: 0, + reg: regInfo{}, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LDAR", + argLen: 2, + faultOnNilArg0: true, + asm: arm64.ALDAR, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVDloadidx", - auxType: auxSymOff, - argLen: 3, - symEffect: SymRead, - asm: s390x.AFMOVD, + name: "LDARB", + argLen: 2, + faultOnNilArg0: true, + asm: arm64.ALDARB, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVSstore", - auxType: auxSymOff, - argLen: 3, + name: "LDARW", + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AFMOVS, + asm: arm64.ALDARW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "FMOVDstore", - auxType: auxSymOff, + name: "STLRB", argLen: 3, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AFMOVD, + hasSideEffects: true, + asm: arm64.ASTLRB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "FMOVSstoreidx", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: s390x.AFMOVS, + name: "STLR", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: arm64.ASTLR, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "FMOVDstoreidx", - auxType: auxSymOff, - argLen: 4, - symEffect: SymWrite, - asm: s390x.AFMOVD, + name: "STLRW", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: arm64.ASTLRW, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "ADD", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AADD, + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AADDW, + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDconst", - auxType: auxInt32, - argLen: 1, - clobberFlags: true, - asm: s390x.AADD, + name: "LoweredAtomicExchange8", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDWconst", - auxType: auxInt32, - argLen: 1, - clobberFlags: true, - asm: s390x.AADDW, + name: "LoweredAtomicExchange64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AADD, + name: "LoweredAtomicExchange32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "ADDWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AADDW, + name: "LoweredAtomicExchange8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUB", - argLen: 2, - clobberFlags: true, - asm: s390x.ASUB, + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUBW", - argLen: 2, - clobberFlags: true, - asm: s390x.ASUBW, + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUBconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ASUB, + name: "LoweredAtomicAdd64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUBWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ASUBW, + name: "LoweredAtomicAdd32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUBload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.ASUB, + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "SUBWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.ASUBW, + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULLD", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLD, + name: "LoweredAtomicCas64Variant", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULLW", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLW, + name: "LoweredAtomicCas32Variant", + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {2, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB + }, + outputs: []outputInfo{ + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULLDconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLD, + name: "LoweredAtomicAnd8", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULLWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULLW, + name: "LoweredAtomicOr8", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULLDload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AMULLD, + name: "LoweredAtomicAnd64", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULLWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AMULLW, + name: "LoweredAtomicOr64", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULHD", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULHD, + name: "LoweredAtomicAnd32", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MULHDU", - argLen: 2, - commutative: true, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMULHDU, + name: "LoweredAtomicOr32", + argLen: 3, + resultNotInArgs: true, + needIntTemp: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: arm64.AORR, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "DIVD", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVD, + name: "LoweredAtomicAnd8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "DIVW", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVW, + name: "LoweredAtomicOr8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "DIVDU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVDU, + name: "LoweredAtomicAnd64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "DIVWU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ADIVWU, + name: "LoweredAtomicOr64Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MODD", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODD, + name: "LoweredAtomicAnd32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MODW", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODW, + name: "LoweredAtomicOr32Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 939524095}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 ZERO + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, - clobbers: 2048, // R11 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 335544319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { - name: "MODDU", - argLen: 2, - resultInArg0: true, + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, clobberFlags: true, - asm: s390x.AMODDU, reg: regInfo{ - inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - clobbers: 2048, // R11 + clobbers: 9223372034975924224, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 16777216}, // R25 }, }, }, { - name: "MODWU", - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AMODWU, + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 - }, - clobbers: 2048, // R11 - outputs: []outputInfo{ - {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {0, 4}, // R2 + {1, 8}, // R3 }, }, }, { - name: "AND", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AAND, + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 2}, // R1 + {1, 4}, // R2 }, }, }, { - name: "ANDW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AANDW, + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1}, // R0 + {1, 2}, // R1 }, }, }, { - name: "ANDconst", - auxType: auxInt64, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AAND, + name: "PRFM", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: arm64.APRFM, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 9223372038331170815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB }, }, }, { - name: "ANDWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AANDW, + name: "DMB", + auxType: auxInt64, + argLen: 1, + hasSideEffects: true, + asm: arm64.ADMB, + reg: regInfo{}, + }, + { + name: "ZERO", + argLen: 0, + zeroWidth: true, + fixedReg: true, + reg: regInfo{}, + }, + + { + name: "NEGV", + argLen: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "ANDload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AAND, + name: "NEGF", + argLen: 1, + asm: loong64.ANEGF, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ANDWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AANDW, + name: "NEGD", + argLen: 1, + asm: loong64.ANEGD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "OR", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AOR, + name: "SQRTD", + argLen: 1, + asm: loong64.ASQRTD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ORW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AORW, + name: "SQRTF", + argLen: 1, + asm: loong64.ASQRTF, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ORconst", - auxType: auxInt64, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AOR, + name: "ABSD", + argLen: 1, + asm: loong64.AABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ORWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AORW, + name: "CLZW", + argLen: 1, + asm: loong64.ACLZW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "ORload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AOR, + name: "CLZV", + argLen: 1, + asm: loong64.ACLZV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "ORWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AORW, + name: "CTZW", + argLen: 1, + asm: loong64.ACTZW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "XOR", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AXOR, + name: "CTZV", + argLen: 1, + asm: loong64.ACTZV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "XORW", - argLen: 2, - commutative: true, - clobberFlags: true, - asm: s390x.AXORW, + name: "REVB2H", + argLen: 1, + asm: loong64.AREVB2H, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "XORconst", - auxType: auxInt64, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AXOR, + name: "REVB2W", + argLen: 1, + asm: loong64.AREVB2W, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "XORWconst", - auxType: auxInt32, - argLen: 1, - resultInArg0: true, - clobberFlags: true, - asm: s390x.AXORW, + name: "REVBV", + argLen: 1, + asm: loong64.AREVBV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "XORload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AXOR, + name: "BITREV4B", + argLen: 1, + asm: loong64.ABITREV4B, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "XORWload", - auxType: auxSymOff, - argLen: 3, - resultInArg0: true, - clobberFlags: true, - faultOnNilArg1: true, - symEffect: SymRead, - asm: s390x.AXORW, + name: "BITREVW", + argLen: 1, + asm: loong64.ABITREVW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "ADDC", - argLen: 2, - commutative: true, - asm: s390x.AADDC, + name: "BITREVV", + argLen: 1, + asm: loong64.ABITREVV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "ADDCconst", - auxType: auxInt16, - argLen: 1, - asm: s390x.AADDC, + name: "VPCNT64", + argLen: 1, + asm: loong64.AVPCNTV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "ADDE", - argLen: 3, - commutative: true, - resultInArg0: true, - asm: s390x.AADDE, + name: "VPCNT32", + argLen: 1, + asm: loong64.AVPCNTW, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SUBC", - argLen: 2, - asm: s390x.ASUBC, + name: "VPCNT16", + argLen: 1, + asm: loong64.AVPCNTH, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SUBE", - argLen: 3, - resultInArg0: true, - asm: s390x.ASUBE, + name: "ADDV", + argLen: 2, + commutative: true, + asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMP", - argLen: 2, - asm: s390x.ACMP, + name: "ADDVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AADDVU, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPW", + name: "SUBV", argLen: 2, - asm: s390x.ACMPW, + asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPU", - argLen: 2, - asm: s390x.ACMPU, + name: "SUBVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASUBVU, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPWU", - argLen: 2, - asm: s390x.ACMPWU, + name: "MULV", + argLen: 2, + commutative: true, + asm: loong64.AMULV, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMP, + name: "MULHV", + argLen: 2, + commutative: true, + asm: loong64.AMULHV, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPWconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMPW, + name: "MULHVU", + argLen: 2, + commutative: true, + asm: loong64.AMULHVU, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPUconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMPU, + name: "DIVV", + argLen: 2, + asm: loong64.ADIVV, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CMPWUconst", - auxType: auxInt32, - argLen: 1, - asm: s390x.ACMPWU, + name: "DIVVU", + argLen: 2, + asm: loong64.ADIVVU, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "FCMPS", + name: "REMV", argLen: 2, - asm: s390x.ACEBR, + asm: loong64.AREMV, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "FCMP", + name: "REMVU", argLen: 2, - asm: s390x.AFCMPU, + asm: loong64.AREMVU, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LTDBR", - argLen: 1, - asm: s390x.ALTDBR, + name: "ADDF", + argLen: 2, + commutative: true, + asm: loong64.AADDF, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LTEBR", - argLen: 1, - asm: s390x.ALTEBR, + name: "ADDD", + argLen: 2, + commutative: true, + asm: loong64.AADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SLD", + name: "SUBF", argLen: 2, - asm: s390x.ASLD, + asm: loong64.ASUBF, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SLW", + name: "SUBD", argLen: 2, - asm: s390x.ASLW, + asm: loong64.ASUBD, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SLDconst", - auxType: auxUInt8, - argLen: 1, - asm: s390x.ASLD, + name: "MULF", + argLen: 2, + commutative: true, + asm: loong64.AMULF, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SLWconst", - auxType: auxUInt8, - argLen: 1, - asm: s390x.ASLW, + name: "MULD", + argLen: 2, + commutative: true, + asm: loong64.AMULD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SRD", + name: "DIVF", argLen: 2, - asm: s390x.ASRD, + asm: loong64.ADIVF, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SRW", + name: "DIVD", argLen: 2, - asm: s390x.ASRW, + asm: loong64.ADIVD, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "SRDconst", - auxType: auxUInt8, - argLen: 1, - asm: s390x.ASRD, + name: "AND", + argLen: 2, + commutative: true, + asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "SRWconst", - auxType: auxUInt8, + name: "ANDconst", + auxType: auxInt64, argLen: 1, - asm: s390x.ASRW, + asm: loong64.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "SRAD", - argLen: 2, - clobberFlags: true, - asm: s390x.ASRAD, + name: "OR", + argLen: 2, + commutative: true, + asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "SRAW", - argLen: 2, - clobberFlags: true, - asm: s390x.ASRAW, + name: "ORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AOR, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "SRADconst", - auxType: auxUInt8, - argLen: 1, - clobberFlags: true, - asm: s390x.ASRAD, + name: "XOR", + argLen: 2, + commutative: true, + asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "SRAWconst", - auxType: auxUInt8, - argLen: 1, - clobberFlags: true, - asm: s390x.ASRAW, + name: "XORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "RLLG", - argLen: 2, - asm: s390x.ARLLG, + name: "NOR", + argLen: 2, + commutative: true, + asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "RLL", - argLen: 2, - asm: s390x.ARLL, + name: "NORconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ANOR, reg: regInfo{ inputs: []inputInfo{ - {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "RLLconst", - auxType: auxUInt8, - argLen: 1, - asm: s390x.ARLL, + name: "ANDN", + argLen: 2, + asm: loong64.AANDN, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "RXSBG", - auxType: auxS390XRotateParams, - argLen: 2, - resultInArg0: true, - clobberFlags: true, - asm: s390x.ARXSBG, + name: "ORN", + argLen: 2, + asm: loong64.AORN, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "RISBGZ", - auxType: auxS390XRotateParams, - argLen: 1, - clobberFlags: true, - asm: s390x.ARISBGZ, + name: "FMADDF", + argLen: 3, + commutative: true, + asm: loong64.AFMADDF, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "NEG", - argLen: 1, - clobberFlags: true, - asm: s390x.ANEG, + name: "FMADDD", + argLen: 3, + commutative: true, + asm: loong64.AFMADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "NEGW", - argLen: 1, - clobberFlags: true, - asm: s390x.ANEGW, + name: "FMSUBF", + argLen: 3, + commutative: true, + asm: loong64.AFMSUBF, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "NOT", - argLen: 1, - resultInArg0: true, - clobberFlags: true, + name: "FMSUBD", + argLen: 3, + commutative: true, + asm: loong64.AFMSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "NOTW", - argLen: 1, - resultInArg0: true, - clobberFlags: true, + name: "FNMADDF", + argLen: 3, + commutative: true, + asm: loong64.AFNMADDF, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FSQRT", - argLen: 1, - asm: s390x.AFSQRT, + name: "FNMADDD", + argLen: 3, + commutative: true, + asm: loong64.AFNMADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "FSQRTS", - argLen: 1, - asm: s390x.AFSQRTS, + name: "FNMSUBF", + argLen: 3, + commutative: true, + asm: loong64.AFNMSUBF, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LOCGR", - auxType: auxS390XCCMask, - argLen: 3, - resultInArg0: true, - asm: s390x.ALOCGR, + name: "FNMSUBD", + argLen: 3, + commutative: true, + asm: loong64.AFNMSUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVBreg", - argLen: 1, - asm: s390x.AMOVB, + name: "FMINF", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: loong64.AFMINF, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVBZreg", - argLen: 1, - asm: s390x.AMOVBZ, + name: "FMIND", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: loong64.AFMIND, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHreg", - argLen: 1, - asm: s390x.AMOVH, + name: "FMAXF", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: loong64.AFMAXF, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHZreg", - argLen: 1, - asm: s390x.AMOVHZ, + name: "FMAXD", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: loong64.AFMAXD, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVWreg", - argLen: 1, - asm: s390x.AMOVW, + name: "MASKEQZ", + argLen: 2, + asm: loong64.AMASKEQZ, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWZreg", - argLen: 1, - asm: s390x.AMOVWZ, + name: "MASKNEZ", + argLen: 2, + asm: loong64.AMASKNEZ, reg: regInfo{ inputs: []inputInfo{ - {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVDconst", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, - asm: s390x.AMOVD, + name: "FCOPYSGD", + argLen: 2, + asm: loong64.AFCOPYSGD, reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LDGR", - argLen: 1, - asm: s390x.ALDGR, + name: "SLL", + argLen: 2, + asm: loong64.ASLL, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LGDR", - argLen: 1, - asm: s390x.ALGDR, + name: "SLLV", + argLen: 2, + asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CFDBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACFDBRA, + name: "SLLconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASLL, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CGDBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACGDBRA, + name: "SLLVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASLLV, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CFEBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACFEBRA, + name: "SRL", + argLen: 2, + asm: loong64.ASRL, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CGEBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACGEBRA, + name: "SRLV", + argLen: 2, + asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CEFBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACEFBRA, + name: "SRLconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRL, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CDFBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDFBRA, + name: "SRLVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRLV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CEGBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACEGBRA, + name: "SRA", + argLen: 2, + asm: loong64.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CDGBRA", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDGBRA, + name: "SRAV", + argLen: 2, + asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CLFEBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLFEBR, + name: "SRAconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CLFDBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLFDBR, + name: "SRAVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASRAV, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CLGEBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLGEBR, + name: "ROTR", + argLen: 2, + asm: loong64.AROTR, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CLGDBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACLGDBR, + name: "ROTRV", + argLen: 2, + asm: loong64.AROTRV, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CELFBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACELFBR, + name: "ROTRconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AROTR, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CDLFBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDLFBR, + name: "ROTRVconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.AROTRV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CELGBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACELGBR, + name: "SGT", + argLen: 2, + asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "CDLGBR", - argLen: 1, - clobberFlags: true, - asm: s390x.ACDLGBR, + name: "SGTconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASGT, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LEDBR", - argLen: 1, - asm: s390x.ALEDBR, + name: "SGTU", + argLen: 2, + asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LDEBR", - argLen: 1, - asm: s390x.ALDEBR, + name: "SGTUconst", + auxType: auxInt64, + argLen: 1, + asm: loong64.ASGTU, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVDaddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, + name: "CMPEQF", + argLen: 2, + asm: loong64.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ - {0, 4295000064}, // SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVDaddridx", - auxType: auxSymOff, - argLen: 2, - symEffect: SymAddr, + name: "CMPEQD", + argLen: 2, + asm: loong64.ACMPEQD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295000064}, // SP SB - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVBZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVBZ, + name: "CMPGEF", + argLen: 2, + asm: loong64.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVBload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVB, + name: "CMPGED", + argLen: 2, + asm: loong64.ACMPGED, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVHZ, + name: "CMPGTF", + argLen: 2, + asm: loong64.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVH, + name: "CMPGTD", + argLen: 2, + asm: loong64.ACMPGTD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVWZload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVWZ, + name: "BSTRPICKW", + auxType: auxInt64, + argLen: 1, + asm: loong64.ABSTRPICKW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVW, + name: "BSTRPICKV", + auxType: auxInt64, + argLen: 1, + asm: loong64.ABSTRPICKV, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVDload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVD, + name: "MOVVconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVV, reg: regInfo{ - inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWBR", - argLen: 1, - asm: s390x.AMOVWBR, + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVF, reg: regInfo{ - inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVDBR", - argLen: 1, - asm: s390x.AMOVDBR, + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: loong64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686018427387908}, // SP SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVHBRload", + name: "MOVBload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, - asm: s390x.AMOVHBR, + asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWBRload", + name: "MOVBUload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, - asm: s390x.AMOVWBR, + asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVDBRload", + name: "MOVHload", auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymRead, - asm: s390x.AMOVDBR, + asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVBstore", + name: "MOVHUload", auxType: auxSymOff, - argLen: 3, + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + symEffect: SymRead, + asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVHstore", + name: "MOVWload", auxType: auxSymOff, - argLen: 3, + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVH, + symEffect: SymRead, + asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWstore", + name: "MOVWUload", auxType: auxSymOff, - argLen: 3, + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + symEffect: SymRead, + asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVDstore", + name: "MOVVload", auxType: auxSymOff, - argLen: 3, + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + symEffect: SymRead, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVHBRstore", + name: "MOVFload", auxType: auxSymOff, - argLen: 3, + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVHBR, + symEffect: SymRead, + asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVWBRstore", + name: "MOVDload", auxType: auxSymOff, - argLen: 3, + argLen: 2, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVWBR, + symEffect: SymRead, + asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVDBRstore", - auxType: auxSymOff, - argLen: 3, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVDBR, + name: "MOVVloadidx", + argLen: 3, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MVC", - auxType: auxSymValAndOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, - symEffect: SymNone, - asm: s390x.AMVC, + name: "MOVWloadidx", + argLen: 3, + asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVBZloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVBZ, + name: "MOVWUloadidx", + argLen: 3, + asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVBloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVB, + name: "MOVHloadidx", + argLen: 3, + asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVHZloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVHZ, + name: "MOVHUloadidx", + argLen: 3, + asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVHloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVH, + name: "MOVBloadidx", + argLen: 3, + asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWZloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVWZ, + name: "MOVBUloadidx", + argLen: 3, + asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "MOVWloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVW, + name: "MOVFloadidx", + argLen: 3, + asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVDloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVD, + name: "MOVDloadidx", + argLen: 3, + asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHBRloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVHBR, + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVWBRloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVWBR, + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVDBRloadidx", - auxType: auxSymOff, - argLen: 3, - commutative: true, - symEffect: SymRead, - asm: s390x.AMOVDBR, + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + { + name: "MOVVstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVBstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVH, + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {1, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVWstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + name: "MOVBstoreidx", + argLen: 4, + asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVDstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + name: "MOVHstoreidx", + argLen: 4, + asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVHBRstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVHBR, + name: "MOVWstoreidx", + argLen: 4, + asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVWBRstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVWBR, + name: "MOVVstoreidx", + argLen: 4, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVDBRstoreidx", - auxType: auxSymOff, - argLen: 4, - commutative: true, - symEffect: SymWrite, - asm: s390x.AMOVDBR, + name: "MOVFstoreidx", + argLen: 4, + asm: loong64.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVBstoreconst", - auxType: auxSymValAndOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "MOVDstoreidx", + argLen: 4, + asm: loong64.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + {2, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVHstoreconst", - auxType: auxSymValAndOff, + name: "MOVBstorezero", + auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, - asm: s390x.AMOVH, + asm: loong64.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVWstoreconst", - auxType: auxSymValAndOff, + name: "MOVHstorezero", + auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, - asm: s390x.AMOVW, + asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MOVDstoreconst", - auxType: auxSymValAndOff, + name: "MOVWstorezero", + auxType: auxSymOff, argLen: 2, faultOnNilArg0: true, symEffect: SymWrite, - asm: s390x.AMOVD, + asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "CLEAR", - auxType: auxSymValAndOff, + name: "MOVVstorezero", + auxType: auxSymOff, argLen: 2, - clobberFlags: true, faultOnNilArg0: true, symEffect: SymWrite, - asm: s390x.ACLEAR, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "CALLstatic", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, + name: "MOVBstorezeroidx", + argLen: 3, + asm: loong64.AMOVB, reg: regInfo{ - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, }, }, { - name: "CALLtail", - auxType: auxCallOff, - argLen: 1, - clobberFlags: true, - call: true, - tailCall: true, + name: "MOVHstorezeroidx", + argLen: 3, + asm: loong64.AMOVH, reg: regInfo{ - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, }, }, { - name: "CALLclosure", - auxType: auxCallOff, - argLen: 3, - clobberFlags: true, - call: true, + name: "MOVWstorezeroidx", + argLen: 3, + asm: loong64.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {1, 4096}, // R12 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "CALLinter", - auxType: auxCallOff, - argLen: 2, - clobberFlags: true, - call: true, + name: "MOVVstorezeroidx", + argLen: 3, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, - clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, { - name: "InvertFlags", + name: "MOVWfpgp", argLen: 1, - reg: regInfo{}, + asm: loong64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + }, }, { - name: "LoweredGetG", + name: "MOVWgpfp", argLen: 1, + asm: loong64.AMOVW, reg: regInfo{ + inputs: []inputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredGetClosurePtr", - argLen: 0, - zeroWidth: true, + name: "MOVVfpgp", + argLen: 1, + asm: loong64.AMOVV, reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, outputs: []outputInfo{ - {0, 4096}, // R12 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "MOVVgpfp", + argLen: 1, + asm: loong64.AMOVV, reg: regInfo{ + inputs: []inputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "MOVBreg", + argLen: 1, + asm: loong64.AMOVB, reg: regInfo{ + inputs: []inputInfo{ + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - clobberFlags: true, - nilCheck: true, - faultOnNilArg0: true, + name: "MOVBUreg", + argLen: 1, + asm: loong64.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredRound32F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "MOVHreg", + argLen: 1, + asm: loong64.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredRound64F", - argLen: 1, - resultInArg0: true, - zeroWidth: true, + name: "MOVHUreg", + argLen: 1, + asm: loong64.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - clobberFlags: true, + name: "MOVWreg", + argLen: 1, + asm: loong64.AMOVW, reg: regInfo{ - clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + inputs: []inputInfo{ + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, outputs: []outputInfo{ - {0, 512}, // R9 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredPanicBoundsA", - auxType: auxInt64, - argLen: 3, - call: true, + name: "MOVWUreg", + argLen: 1, + asm: loong64.AMOVWU, reg: regInfo{ inputs: []inputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredPanicBoundsB", - auxType: auxInt64, - argLen: 3, - call: true, + name: "MOVVreg", + argLen: 1, + asm: loong64.AMOVV, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredPanicBoundsC", - auxType: auxInt64, - argLen: 3, - call: true, + name: "MOVVnop", + argLen: 1, + resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1}, // R0 - {1, 2}, // R1 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "FlagEQ", - argLen: 0, - reg: regInfo{}, - }, - { - name: "FlagLT", - argLen: 0, - reg: regInfo{}, + name: "MOVWF", + argLen: 1, + asm: loong64.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, }, { - name: "FlagGT", - argLen: 0, - reg: regInfo{}, + name: "MOVWD", + argLen: 1, + asm: loong64.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, }, { - name: "FlagOV", - argLen: 0, - reg: regInfo{}, + name: "MOVVF", + argLen: 1, + asm: loong64.AMOVVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, }, { - name: "SYNC", + name: "MOVVD", argLen: 1, - asm: s390x.ASYNC, - reg: regInfo{}, + asm: loong64.AMOVVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, }, { - name: "MOVBZatomicload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVBZ, + name: "TRUNCFW", + argLen: 1, + asm: loong64.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVWZatomicload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVWZ, + name: "TRUNCDW", + argLen: 1, + asm: loong64.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVDatomicload", - auxType: auxSymOff, - argLen: 2, - faultOnNilArg0: true, - symEffect: SymRead, - asm: s390x.AMOVD, + name: "TRUNCFV", + argLen: 1, + asm: loong64.ATRUNCFV, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVBatomicstore", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymWrite, - asm: s390x.AMOVB, + name: "TRUNCDV", + argLen: 1, + asm: loong64.ATRUNCDV, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVWatomicstore", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymWrite, - asm: s390x.AMOVW, + name: "MOVFD", + argLen: 1, + asm: loong64.AMOVFD, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "MOVDatomicstore", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymWrite, - asm: s390x.AMOVD, + name: "MOVDF", + argLen: 1, + asm: loong64.AMOVDF, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LAA", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ALAA, + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "LAAG", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ALAAG, + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686017353646080}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, }, { - name: "AddTupleFirst32", - argLen: 2, - reg: regInfo{}, + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, }, { - name: "AddTupleFirst64", - argLen: 2, - reg: regInfo{}, + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, }, { - name: "LAN", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAN, + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 268435456}, // R29 + {0, 1071644668}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, + clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "LANfloor", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAN, + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, - clobbers: 2, // R1 + clobbers: 4611686018427387896, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 }, }, { - name: "LAO", - argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAO, + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 524288}, // R20 }, + clobbers: 524290, // R1 R20 }, }, { - name: "LAOfloor", + name: "DUFFCOPY", + auxType: auxInt64, argLen: 3, - clobberFlags: true, - hasSideEffects: true, - asm: s390x.ALAO, + faultOnNilArg0: true, + faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 1048576}, // R21 + {1, 524288}, // R20 }, - clobbers: 2, // R1 + clobbers: 1572866, // R1 R20 R21 }, }, { - name: "LoweredAtomicCas32", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ - {1, 1}, // R0 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - }, - clobbers: 1, // R0 - outputs: []outputInfo{ - {1, 0}, - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 524288}, // R20 + {1, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, + clobbers: 524288, // R20 }, }, { - name: "LoweredAtomicCas64", - auxType: auxSymOff, + name: "LoweredMove", + auxType: auxInt64, argLen: 4, - clobberFlags: true, faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACSG, + faultOnNilArg1: true, reg: regInfo{ inputs: []inputInfo{ - {1, 1}, // R0 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - }, - clobbers: 1, // R0 - outputs: []outputInfo{ - {1, 0}, - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 1048576}, // R21 + {1, 524288}, // R20 + {2, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, + clobbers: 1572864, // R20 R21 }, }, { - name: "LoweredAtomicExchange32", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, + name: "LoweredAtomicLoad8", + argLen: 2, faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACS, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // R0 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredAtomicExchange64", - auxType: auxSymOff, - argLen: 3, - clobberFlags: true, + name: "LoweredAtomicLoad32", + argLen: 2, faultOnNilArg0: true, - hasSideEffects: true, - symEffect: SymRdWr, - asm: s390x.ACSG, reg: regInfo{ inputs: []inputInfo{ - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP - {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {1, 0}, - {0, 1}, // R0 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "FLOGR", - argLen: 1, - clobberFlags: true, - asm: s390x.AFLOGR, + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, - clobbers: 2, // R1 outputs: []outputInfo{ - {0, 1}, // R0 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "POPCNT", - argLen: 1, - clobberFlags: true, - asm: s390x.APOPCNT, + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, - outputs: []outputInfo{ - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "MLGR", - argLen: 2, - asm: s390x.AMLGR, + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 8}, // R3 - {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 - }, - outputs: []outputInfo{ - {0, 4}, // R2 - {1, 8}, // R3 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "SumBytes2", - argLen: 1, - reg: regInfo{}, - }, - { - name: "SumBytes4", - argLen: 1, - reg: regInfo{}, - }, - { - name: "SumBytes8", - argLen: 1, - reg: regInfo{}, - }, - { - name: "STMG2", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, + name: "LoweredAtomicStore64", + argLen: 3, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMG, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "STMG3", - auxType: auxSymOff, - argLen: 5, - clobberFlags: true, + name: "LoweredAtomicStore8Variant", + argLen: 3, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMG, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "STMG4", - auxType: auxSymOff, - argLen: 6, - clobberFlags: true, + name: "LoweredAtomicStore32Variant", + argLen: 3, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMG, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {4, 16}, // R4 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "STM2", - auxType: auxSymOff, - argLen: 4, - clobberFlags: true, + name: "LoweredAtomicStore64Variant", + argLen: 3, faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMY, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, }, }, { - name: "STM3", - auxType: auxSymOff, - argLen: 5, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMY, + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "STM4", - auxType: auxSymOff, - argLen: 6, - clobberFlags: true, - faultOnNilArg0: true, - symEffect: SymWrite, - asm: s390x.ASTMY, + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {1, 2}, // R1 - {2, 4}, // R2 - {3, 8}, // R3 - {4, 16}, // R4 - {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 4, - clobberFlags: true, - faultOnNilArg0: true, - faultOnNilArg1: true, + name: "LoweredAtomicExchange8Variant", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 4}, // R2 - {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, - clobbers: 6, // R1 R2 }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 3, - clobberFlags: true, - faultOnNilArg0: true, + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 2}, // R1 - {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, - clobbers: 2, // R1 - }, - }, - - { - name: "LoweredStaticCall", - auxType: auxCallOff, - argLen: 1, - call: true, - reg: regInfo{ - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g - }, - }, - { - name: "LoweredTailCall", - auxType: auxCallOff, - argLen: 1, - call: true, - tailCall: true, - reg: regInfo{ - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { - name: "LoweredClosureCall", - auxType: auxCallOff, - argLen: 3, - call: true, + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { - name: "LoweredInterCall", - auxType: auxCallOff, - argLen: 2, - call: true, + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g }, }, { - name: "LoweredAddr", - auxType: auxSymOff, - argLen: 1, - rematerializeable: true, - symEffect: SymAddr, + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredMove", - auxType: auxInt64, - argLen: 3, + name: "LoweredAtomicCas64Variant", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, + outputs: []outputInfo{ + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredZero", - auxType: auxInt64, - argLen: 2, + name: "LoweredAtomicCas32Variant", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {2, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, - }, - }, - { - name: "LoweredGetClosurePtr", - argLen: 0, - reg: regInfo{ outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredGetCallerPC", - argLen: 0, - rematerializeable: true, + name: "LoweredAtomicAnd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMANDDBW, reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredGetCallerSP", - argLen: 1, - rematerializeable: true, + name: "LoweredAtomicOr32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMORDBW, reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB + }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredNilCheck", - argLen: 2, - nilCheck: true, - faultOnNilArg0: true, + name: "LoweredAtomicAnd32value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMANDDBW, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, - }, - }, - { - name: "LoweredWB", - auxType: auxInt64, - argLen: 1, - reg: regInfo{ - clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "LoweredConvert", - argLen: 2, + name: "LoweredAtomicAnd64value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMANDDBV, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "Select", - argLen: 3, - asm: wasm.ASelect, + name: "LoweredAtomicOr32value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMORDBW, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "I64Load8U", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load8U, + name: "LoweredAtomicOr64value", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + asm: loong64.AAMORDBV, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {1, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 + {0, 4611686019501129724}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "I64Load8S", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load8S, + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + reg: regInfo{ outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "I64Load16U", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load16U, + name: "FPFlagFalse", + argLen: 1, reg: regInfo{ - inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB - }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "I64Load16S", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load16S, + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB - }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 268435456}, // R29 }, }, }, { - name: "I64Load32U", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load32U, + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB - }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "I64Load32S", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load32S, + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB - }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "I64Load", - auxType: auxInt64, - argLen: 2, - asm: wasm.AI64Load, + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, reg: regInfo{ - inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB - }, + clobbers: 4611686017353646082, // R1 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 268435456}, // R29 }, }, }, { - name: "I64Store8", + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: loong64.ADBAR, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsA", auxType: auxInt64, argLen: 3, - asm: wasm.AI64Store8, + call: true, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 4194304}, // R23 + {1, 8388608}, // R24 }, }, }, { - name: "I64Store16", + name: "LoweredPanicBoundsB", auxType: auxInt64, argLen: 3, - asm: wasm.AI64Store16, + call: true, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 1048576}, // R21 + {1, 4194304}, // R23 }, }, }, { - name: "I64Store32", + name: "LoweredPanicBoundsC", auxType: auxInt64, argLen: 3, - asm: wasm.AI64Store32, + call: true, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 524288}, // R20 + {1, 1048576}, // R21 }, }, }, { - name: "I64Store", - auxType: auxInt64, - argLen: 3, - asm: wasm.AI64Store, + name: "PRELD", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: loong64.APRELD, reg: regInfo{ inputs: []inputInfo{ - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, { - name: "F32Load", - auxType: auxInt64, - argLen: 2, - asm: wasm.AF32Load, + name: "PRELDX", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: loong64.APRELDX, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1073741820}, // SP R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31 }, }, }, + { - name: "F64Load", - auxType: auxInt64, - argLen: 2, - asm: wasm.AF64Load, + name: "ADD", + argLen: 2, + commutative: true, + asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Store", - auxType: auxInt64, - argLen: 3, - asm: wasm.AF32Store, + name: "ADDconst", + auxType: auxInt32, + argLen: 1, + asm: mips.AADDU, reg: regInfo{ inputs: []inputInfo{ - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Store", - auxType: auxInt64, - argLen: 3, - asm: wasm.AF64Store, + name: "SUB", + argLen: 2, + asm: mips.ASUBU, reg: regInfo{ inputs: []inputInfo{ - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Const", - auxType: auxInt64, - argLen: 0, - rematerializeable: true, + name: "SUBconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ASUBU, reg: regInfo{ + inputs: []inputInfo{ + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Const", - auxType: auxFloat32, - argLen: 0, - rematerializeable: true, + name: "MUL", + argLen: 2, + commutative: true, + asm: mips.AMUL, reg: regInfo{ + inputs: []inputInfo{ + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + clobbers: 105553116266496, // HI LO outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Const", - auxType: auxFloat64, - argLen: 0, - rematerializeable: true, + name: "MULT", + argLen: 2, + commutative: true, + asm: mips.AMUL, reg: regInfo{ + inputs: []inputInfo{ + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 35184372088832}, // HI + {1, 70368744177664}, // LO }, }, }, { - name: "I64Eqz", - argLen: 1, - asm: wasm.AI64Eqz, + name: "MULTU", + argLen: 2, + commutative: true, + asm: mips.AMULU, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35184372088832}, // HI + {1, 70368744177664}, // LO }, }, }, { - name: "I64Eq", + name: "DIV", argLen: 2, - asm: wasm.AI64Eq, + asm: mips.ADIV, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35184372088832}, // HI + {1, 70368744177664}, // LO }, }, }, { - name: "I64Ne", + name: "DIVU", argLen: 2, - asm: wasm.AI64Ne, + asm: mips.ADIVU, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35184372088832}, // HI + {1, 70368744177664}, // LO }, }, }, { - name: "I64LtS", - argLen: 2, - asm: wasm.AI64LtS, + name: "ADDF", + argLen: 2, + commutative: true, + asm: mips.AADDF, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64LtU", - argLen: 2, - asm: wasm.AI64LtU, + name: "ADDD", + argLen: 2, + commutative: true, + asm: mips.AADDD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64GtS", + name: "SUBF", argLen: 2, - asm: wasm.AI64GtS, + asm: mips.ASUBF, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64GtU", + name: "SUBD", argLen: 2, - asm: wasm.AI64GtU, + asm: mips.ASUBD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64LeS", - argLen: 2, - asm: wasm.AI64LeS, + name: "MULF", + argLen: 2, + commutative: true, + asm: mips.AMULF, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64LeU", - argLen: 2, - asm: wasm.AI64LeU, + name: "MULD", + argLen: 2, + commutative: true, + asm: mips.AMULD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64GeS", + name: "DIVF", argLen: 2, - asm: wasm.AI64GeS, + asm: mips.ADIVF, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64GeU", + name: "DIVD", argLen: 2, - asm: wasm.AI64GeU, + asm: mips.ADIVD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Eq", - argLen: 2, - asm: wasm.AF32Eq, + name: "AND", + argLen: 2, + commutative: true, + asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Ne", - argLen: 2, - asm: wasm.AF32Ne, + name: "ANDconst", + auxType: auxInt32, + argLen: 1, + asm: mips.AAND, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Lt", - argLen: 2, - asm: wasm.AF32Lt, + name: "OR", + argLen: 2, + commutative: true, + asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Gt", - argLen: 2, - asm: wasm.AF32Gt, + name: "ORconst", + auxType: auxInt32, + argLen: 1, + asm: mips.AOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Le", - argLen: 2, - asm: wasm.AF32Le, + name: "XOR", + argLen: 2, + commutative: true, + asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Ge", - argLen: 2, - asm: wasm.AF32Ge, + name: "XORconst", + auxType: auxInt32, + argLen: 1, + asm: mips.AXOR, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Eq", - argLen: 2, - asm: wasm.AF64Eq, + name: "NOR", + argLen: 2, + commutative: true, + asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Ne", - argLen: 2, - asm: wasm.AF64Ne, + name: "NORconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ANOR, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Lt", - argLen: 2, - asm: wasm.AF64Lt, + name: "NEG", + argLen: 1, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Gt", - argLen: 2, - asm: wasm.AF64Gt, + name: "NEGF", + argLen: 1, + asm: mips.ANEGF, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F64Le", - argLen: 2, - asm: wasm.AF64Le, + name: "NEGD", + argLen: 1, + asm: mips.ANEGD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F64Ge", - argLen: 2, - asm: wasm.AF64Ge, + name: "ABSD", + argLen: 1, + asm: mips.AABSD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64Add", - argLen: 2, - asm: wasm.AI64Add, + name: "SQRTD", + argLen: 1, + asm: mips.ASQRTD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64AddConst", - auxType: auxInt64, - argLen: 1, - asm: wasm.AI64Add, + name: "SQRTF", + argLen: 1, + asm: mips.ASQRTF, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64Sub", + name: "SLL", argLen: 2, - asm: wasm.AI64Sub, + asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Mul", - argLen: 2, - asm: wasm.AI64Mul, + name: "SLLconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ASLL, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64DivS", + name: "SRL", argLen: 2, - asm: wasm.AI64DivS, + asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64DivU", - argLen: 2, - asm: wasm.AI64DivU, + name: "SRLconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ASRL, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64RemS", + name: "SRA", argLen: 2, - asm: wasm.AI64RemS, + asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64RemU", - argLen: 2, - asm: wasm.AI64RemU, + name: "SRAconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ASRA, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64And", - argLen: 2, - asm: wasm.AI64And, + name: "CLZ", + argLen: 1, + asm: mips.ACLZ, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Or", + name: "SGT", argLen: 2, - asm: wasm.AI64Or, + asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Xor", - argLen: 2, - asm: wasm.AI64Xor, + name: "SGTconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Shl", - argLen: 2, - asm: wasm.AI64Shl, + name: "SGTzero", + argLen: 1, + asm: mips.ASGT, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64ShrS", + name: "SGTU", argLen: 2, - asm: wasm.AI64ShrS, + asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64ShrU", - argLen: 2, - asm: wasm.AI64ShrU, + name: "SGTUconst", + auxType: auxInt32, + argLen: 1, + asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Neg", + name: "SGTUzero", argLen: 1, - asm: wasm.AF32Neg, + asm: mips.ASGTU, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32Add", + name: "CMPEQF", argLen: 2, - asm: wasm.AF32Add, + asm: mips.ACMPEQF, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: mips.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Sub", + name: "CMPGEF", argLen: 2, - asm: wasm.AF32Sub, + asm: mips.ACMPGEF, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: mips.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Mul", + name: "CMPGTF", argLen: 2, - asm: wasm.AF32Mul, + asm: mips.ACMPGTF, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: mips.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVWconst", + auxType: auxInt32, + argLen: 0, + rematerializeable: true, + asm: mips.AMOVW, + reg: regInfo{ + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + asm: mips.AMOVF, + reg: regInfo{ outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Div", - argLen: 2, - asm: wasm.AF32Div, + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: mips.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + }, + }, + }, + { + name: "MOVWaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 140737555464192}, // SP SB }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Neg", - argLen: 1, - asm: wasm.AF64Neg, + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Add", - argLen: 2, - asm: wasm.AF64Add, + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Sub", - argLen: 2, - asm: wasm.AF64Sub, + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Mul", - argLen: 2, - asm: wasm.AF64Mul, + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64Div", - argLen: 2, - asm: wasm.AF64Div, + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64TruncSatF64S", - argLen: 1, - asm: wasm.AI64TruncSatF64S, + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVF, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64TruncSatF64U", - argLen: 1, - asm: wasm.AI64TruncSatF64U, + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVD, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64TruncSatF32S", + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "MOVWfpgp", argLen: 1, - asm: wasm.AI64TruncSatF32S, + asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64TruncSatF32U", + name: "MOVWgpfp", argLen: 1, - asm: wasm.AI64TruncSatF32U, + asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32ConvertI64S", + name: "MOVBreg", argLen: 1, - asm: wasm.AF32ConvertI64S, + asm: mips.AMOVB, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32ConvertI64U", + name: "MOVBUreg", argLen: 1, - asm: wasm.AF32ConvertI64U, + asm: mips.AMOVBU, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64ConvertI64S", + name: "MOVHreg", argLen: 1, - asm: wasm.AF64ConvertI64S, + asm: mips.AMOVH, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64ConvertI64U", + name: "MOVHUreg", argLen: 1, - asm: wasm.AF64ConvertI64U, + asm: mips.AMOVHU, reg: regInfo{ inputs: []inputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F32DemoteF64", + name: "MOVWreg", argLen: 1, - asm: wasm.AF32DemoteF64, + asm: mips.AMOVW, reg: regInfo{ inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "F64PromoteF32", - argLen: 1, - asm: wasm.AF64PromoteF32, + name: "MOVWnop", + argLen: 1, + resultInArg0: true, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Extend8S", - argLen: 1, - asm: wasm.AI64Extend8S, + name: "CMOVZ", + argLen: 3, + resultInArg0: true, + asm: mips.ACMOVZ, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 }, }, }, { - name: "I64Extend16S", + name: "CMOVZzero", + argLen: 2, + resultInArg0: true, + asm: mips.ACMOVZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "MOVWF", argLen: 1, - asm: wasm.AI64Extend16S, + asm: mips.AMOVWF, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "I64Extend32S", + name: "MOVWD", argLen: 1, - asm: wasm.AI64Extend32S, + asm: mips.AMOVWD, reg: regInfo{ inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Sqrt", + name: "TRUNCFW", argLen: 1, - asm: wasm.AF32Sqrt, + asm: mips.ATRUNCFW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Trunc", + name: "TRUNCDW", argLen: 1, - asm: wasm.AF32Trunc, + asm: mips.ATRUNCDW, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Ceil", + name: "MOVFD", argLen: 1, - asm: wasm.AF32Ceil, + asm: mips.AMOVFD, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Floor", + name: "MOVDF", argLen: 1, - asm: wasm.AF32Floor, + asm: mips.AMOVDF, reg: regInfo{ inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 }, }, }, { - name: "F32Nearest", - argLen: 1, - asm: wasm.AF32Nearest, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4194304}, // R22 + {0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31 + }, + clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst", + auxType: auxInt32, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicCas", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {2, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredAtomicAnd", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicOr", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + {0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB + }, + }, + }, + { + name: "LoweredZero", + auxType: auxInt32, + argLen: 3, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: 2, // R1 + }, + }, + { + name: "LoweredMove", + auxType: auxInt32, + argLen: 4, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4}, // R2 + {1, 2}, // R1 + {2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + clobbers: 6, // R1 R2 + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4194304}, // R22 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO + outputs: []outputInfo{ + {0, 16777216}, // R25 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: mips.ASYNC, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8}, // R3 + {1, 16}, // R4 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4}, // R2 + {1, 8}, // R3 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 4}, // R2 + }, + }, + }, + { + name: "LoweredPanicExtendA", + auxType: auxInt64, + argLen: 4, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 32}, // R5 + {1, 8}, // R3 + {2, 16}, // R4 + }, + }, + }, + { + name: "LoweredPanicExtendB", + auxType: auxInt64, + argLen: 4, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 32}, // R5 + {1, 4}, // R2 + {2, 8}, // R3 + }, + }, + }, + { + name: "LoweredPanicExtendC", + auxType: auxInt64, + argLen: 4, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 32}, // R5 + {1, 2}, // R1 + {2, 4}, // R2 + }, + }, + }, + + { + name: "ADDV", + argLen: 2, + commutative: true, + asm: mips.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ADDVconst", + auxType: auxInt64, + argLen: 1, + asm: mips.AADDVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SUBV", + argLen: 2, + asm: mips.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SUBVconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ASUBVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MULV", + argLen: 2, + commutative: true, + asm: mips.AMULV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 1152921504606846976}, // HI + {1, 2305843009213693952}, // LO + }, + }, + }, + { + name: "MULVU", + argLen: 2, + commutative: true, + asm: mips.AMULVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 1152921504606846976}, // HI + {1, 2305843009213693952}, // LO + }, + }, + }, + { + name: "DIVV", + argLen: 2, + asm: mips.ADIVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 1152921504606846976}, // HI + {1, 2305843009213693952}, // LO + }, + }, + }, + { + name: "DIVVU", + argLen: 2, + asm: mips.ADIVVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 1152921504606846976}, // HI + {1, 2305843009213693952}, // LO + }, + }, + }, + { + name: "ADDF", + argLen: 2, + commutative: true, + asm: mips.AADDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ADDD", + argLen: 2, + commutative: true, + asm: mips.AADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBF", + argLen: 2, + asm: mips.ASUBF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SUBD", + argLen: 2, + asm: mips.ASUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULF", + argLen: 2, + commutative: true, + asm: mips.AMULF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MULD", + argLen: 2, + commutative: true, + asm: mips.AMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVF", + argLen: 2, + asm: mips.ADIVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + asm: mips.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + asm: mips.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + asm: mips.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + asm: mips.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NORconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NEGV", + argLen: 1, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "NEGF", + argLen: 1, + asm: mips.ANEGF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "NEGD", + argLen: 1, + asm: mips.ANEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "ABSD", + argLen: 1, + asm: mips.AABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTD", + argLen: 1, + asm: mips.ASQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SQRTF", + argLen: 1, + asm: mips.ASQRTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "SLLV", + argLen: 2, + asm: mips.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SLLVconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ASLLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRLV", + argLen: 2, + asm: mips.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRLVconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ASRLV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRAV", + argLen: 2, + asm: mips.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SRAVconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ASRAV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGT", + argLen: 2, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGTconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ASGT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGTU", + argLen: 2, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "SGTUconst", + auxType: auxInt64, + argLen: 1, + asm: mips.ASGTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "CMPEQF", + argLen: 2, + asm: mips.ACMPEQF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPEQD", + argLen: 2, + asm: mips.ACMPEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGEF", + argLen: 2, + asm: mips.ACMPGEF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGED", + argLen: 2, + asm: mips.ACMPGED, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTF", + argLen: 2, + asm: mips.ACMPGTF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CMPGTD", + argLen: 2, + asm: mips.ACMPGTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: mips.AMOVV, + reg: regInfo{ + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVFconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: mips.AMOVF, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: mips.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018460942336}, // SP SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVFload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVVstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVFstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + {1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVVstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "MOVWfpgp", + argLen: 1, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWgpfp", + argLen: 1, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVfpgp", + argLen: 1, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVgpfp", + argLen: 1, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + asm: mips.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + asm: mips.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + asm: mips.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + asm: mips.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + asm: mips.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + asm: mips.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVreg", + argLen: 1, + asm: mips.AMOVV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVVnop", + argLen: 1, + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "MOVWF", + argLen: 1, + asm: mips.AMOVWF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVWD", + argLen: 1, + asm: mips.AMOVWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVF", + argLen: 1, + asm: mips.AMOVVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVVD", + argLen: 1, + asm: mips.AMOVVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFW", + argLen: 1, + asm: mips.ATRUNCFW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDW", + argLen: 1, + asm: mips.ATRUNCDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCFV", + argLen: 1, + asm: mips.ATRUNCFV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "TRUNCDV", + argLen: 1, + asm: mips.ATRUNCDV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVFD", + argLen: 1, + asm: mips.AMOVFD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "MOVDF", + argLen: 1, + asm: mips.AMOVDF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4194304}, // R22 + {0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31 + }, + clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: 134217730, // R1 R31 + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4}, // R2 + {1, 2}, // R1 + }, + clobbers: 134217734, // R1 R2 R31 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: 2, // R1 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4}, // R2 + {1, 2}, // R1 + {2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + clobbers: 6, // R1 R2 + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + asm: mips.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero32", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicStorezero64", + argLen: 2, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst32", + auxType: auxInt32, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicAddconst64", + auxType: auxInt64, + argLen: 2, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {2, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + {0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB + }, + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 + }, + }, + }, + { + name: "FPFlagTrue", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "FPFlagFalse", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4194304}, // R22 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO + outputs: []outputInfo{ + {0, 16777216}, // R25 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: mips.ASYNC, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8}, // R3 + {1, 16}, // R4 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4}, // R2 + {1, 8}, // R3 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 4}, // R2 + }, + }, + }, + + { + name: "ADD", + argLen: 2, + commutative: true, + asm: ppc64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDCC", + argLen: 2, + commutative: true, + asm: ppc64.AADDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDCCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AADDCCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FADD", + argLen: 2, + commutative: true, + asm: ppc64.AFADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FADDS", + argLen: 2, + commutative: true, + asm: ppc64.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "SUB", + argLen: 2, + asm: ppc64.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBCC", + argLen: 2, + asm: ppc64.ASUBCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBFCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FSUB", + argLen: 2, + asm: ppc64.AFSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + asm: ppc64.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "XSMINJDP", + argLen: 2, + asm: ppc64.AXSMINJDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "XSMAXJDP", + argLen: 2, + asm: ppc64.AXSMAXJDP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MULLD", + argLen: 2, + commutative: true, + asm: ppc64.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULLW", + argLen: 2, + commutative: true, + asm: ppc64.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULLDconst", + auxType: auxInt32, + argLen: 1, + asm: ppc64.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULLWconst", + auxType: auxInt32, + argLen: 1, + asm: ppc64.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MADDLD", + argLen: 3, + asm: ppc64.AMADDLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHD", + argLen: 2, + commutative: true, + asm: ppc64.AMULHD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHW", + argLen: 2, + commutative: true, + asm: ppc64.AMULHW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHDU", + argLen: 2, + commutative: true, + asm: ppc64.AMULHDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHDUCC", + argLen: 2, + commutative: true, + asm: ppc64.AMULHDUCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MULHWU", + argLen: 2, + commutative: true, + asm: ppc64.AMULHWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMUL", + argLen: 2, + commutative: true, + asm: ppc64.AFMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + asm: ppc64.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMADD", + argLen: 3, + asm: ppc64.AFMADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + asm: ppc64.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMSUB", + argLen: 3, + asm: ppc64.AFMSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + asm: ppc64.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "SRAD", + argLen: 2, + asm: ppc64.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRAW", + argLen: 2, + asm: ppc64.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRD", + argLen: 2, + asm: ppc64.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRW", + argLen: 2, + asm: ppc64.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLD", + argLen: 2, + asm: ppc64.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLW", + argLen: 2, + asm: ppc64.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTL", + argLen: 2, + asm: ppc64.AROTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTLW", + argLen: 2, + asm: ppc64.AROTLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CLRLSLWI", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ACLRLSLWI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CLRLSLDI", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ACLRLSLDI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDC", + argLen: 2, + commutative: true, + asm: ppc64.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBC", + argLen: 2, + asm: ppc64.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDE", + argLen: 3, + commutative: true, + asm: ppc64.AADDE, + reg: regInfo{ + inputs: []inputInfo{ + {2, 9223372036854775808}, // XER + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDZE", + argLen: 2, + asm: ppc64.AADDZE, + reg: regInfo{ + inputs: []inputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBE", + argLen: 3, + asm: ppc64.ASUBE, + reg: regInfo{ + inputs: []inputInfo{ + {2, 9223372036854775808}, // XER + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {1, 9223372036854775808}, // XER + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ADDZEzero", + argLen: 1, + asm: ppc64.AADDZE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372036854775808}, // XER + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SUBZEzero", + argLen: 1, + asm: ppc64.ASUBZE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372036854775808}, // XER + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRADconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRAWconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 9223372036854775808, // XER + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRDconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SRWconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLDconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SLWconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTLconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AROTL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ROTLWconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AROTLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "EXTSWSLconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AEXTSWSLI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLWINM", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ARLWNM, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLWNM", + auxType: auxInt64, + argLen: 2, + asm: ppc64.ARLWNM, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLWMI", + auxType: auxInt64, + argLen: 2, + resultInArg0: true, + asm: ppc64.ARLWMI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLDICL", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ARLDICL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLDICLCC", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ARLDICLCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "RLDICR", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ARLDICR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTLZD", + argLen: 1, + asm: ppc64.ACNTLZD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTLZDCC", + argLen: 1, + asm: ppc64.ACNTLZDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTLZW", + argLen: 1, + asm: ppc64.ACNTLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTTZD", + argLen: 1, + asm: ppc64.ACNTTZD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CNTTZW", + argLen: 1, + asm: ppc64.ACNTTZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "POPCNTD", + argLen: 1, + asm: ppc64.APOPCNTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "POPCNTW", + argLen: 1, + asm: ppc64.APOPCNTW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "POPCNTB", + argLen: 1, + asm: ppc64.APOPCNTB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FDIV", + argLen: 2, + asm: ppc64.AFDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + asm: ppc64.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + asm: ppc64.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + asm: ppc64.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "DIVDU", + argLen: 2, + asm: ppc64.ADIVDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "DIVWU", + argLen: 2, + asm: ppc64.ADIVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODUD", + argLen: 2, + asm: ppc64.AMODUD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODSD", + argLen: 2, + asm: ppc64.AMODSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODUW", + argLen: 2, + asm: ppc64.AMODUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MODSW", + argLen: 2, + asm: ppc64.AMODSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FCTIDZ", + argLen: 1, + asm: ppc64.AFCTIDZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCTIWZ", + argLen: 1, + asm: ppc64.AFCTIWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCFID", + argLen: 1, + asm: ppc64.AFCFID, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCFIDS", + argLen: 1, + asm: ppc64.AFCFIDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FRSP", + argLen: 1, + asm: ppc64.AFRSP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MFVSRD", + argLen: 1, + asm: ppc64.AMFVSRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MTVSRD", + argLen: 1, + asm: ppc64.AMTVSRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + asm: ppc64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDN", + argLen: 2, + asm: ppc64.AANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDNCC", + argLen: 2, + asm: ppc64.AANDNCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDCC", + argLen: 2, + commutative: true, + asm: ppc64.AANDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ORN", + argLen: 2, + asm: ppc64.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ORCC", + argLen: 2, + commutative: true, + asm: ppc64.AORCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NOR", + argLen: 2, + commutative: true, + asm: ppc64.ANOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NORCC", + argLen: 2, + commutative: true, + asm: ppc64.ANORCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + asm: ppc64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "XORCC", + argLen: 2, + commutative: true, + asm: ppc64.AXORCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "EQV", + argLen: 2, + commutative: true, + asm: ppc64.AEQV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NEG", + argLen: 1, + asm: ppc64.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NEGCC", + argLen: 1, + asm: ppc64.ANEGCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "BRD", + argLen: 1, + asm: ppc64.ABRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "BRW", + argLen: 1, + asm: ppc64.ABRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "BRH", + argLen: 1, + asm: ppc64.ABRH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FNEG", + argLen: 1, + asm: ppc64.AFNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FSQRT", + argLen: 1, + asm: ppc64.AFSQRT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + asm: ppc64.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FFLOOR", + argLen: 1, + asm: ppc64.AFRIM, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCEIL", + argLen: 1, + asm: ppc64.AFRIP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FTRUNC", + argLen: 1, + asm: ppc64.AFRIZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FROUND", + argLen: 1, + asm: ppc64.AFRIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FABS", + argLen: 1, + asm: ppc64.AFABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FNABS", + argLen: 1, + asm: ppc64.AFNABS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCPSGN", + argLen: 2, + asm: ppc64.AFCPSGN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDCCconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.AANDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + asm: ppc64.AANDCC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBZreg", + argLen: 1, + asm: ppc64.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHZreg", + argLen: 1, + asm: ppc64.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWZreg", + argLen: 1, + asm: ppc64.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRload", + argLen: 2, + faultOnNilArg0: true, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRload", + argLen: 2, + faultOnNilArg0: true, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHBRload", + argLen: 2, + faultOnNilArg0: true, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBZloadidx", + argLen: 3, + asm: ppc64.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHloadidx", + argLen: 3, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHZloadidx", + argLen: 3, + asm: ppc64.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWloadidx", + argLen: 3, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWZloadidx", + argLen: 3, + asm: ppc64.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDloadidx", + argLen: 3, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHBRloadidx", + argLen: 3, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRloadidx", + argLen: 3, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRloadidx", + argLen: 3, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDloadidx", + argLen: 3, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSloadidx", + argLen: 3, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "DCBT", + auxType: auxInt64, + argLen: 2, + hasSideEffects: true, + asm: ppc64.ADCBT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRstore", + argLen: 3, + faultOnNilArg0: true, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRstore", + argLen: 3, + faultOnNilArg0: true, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHBRstore", + argLen: 3, + faultOnNilArg0: true, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MOVBstoreidx", + argLen: 4, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHstoreidx", + argLen: 4, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWstoreidx", + argLen: 4, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDstoreidx", + argLen: 4, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDstoreidx", + argLen: 4, + asm: ppc64.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSstoreidx", + argLen: 4, + asm: ppc64.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "MOVHBRstoreidx", + argLen: 4, + asm: ppc64.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWBRstoreidx", + argLen: 4, + asm: ppc64.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDBRstoreidx", + argLen: 4, + asm: ppc64.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: ppc64.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: ppc64.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: ppc64.AFMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FMOVSconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + asm: ppc64.AFMOVS, + reg: regInfo{ + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "FCMPU", + argLen: 2, + asm: ppc64.AFCMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + {1, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "CMP", + argLen: 2, + asm: ppc64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPU", + argLen: 2, + asm: ppc64.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPW", + argLen: 2, + asm: ppc64.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPWU", + argLen: 2, + asm: ppc64.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPUconst", + auxType: auxInt64, + argLen: 1, + asm: ppc64.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPWconst", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "CMPWUconst", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ISEL", + auxType: auxInt32, + argLen: 3, + asm: ppc64.AISEL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "ISELZ", + auxType: auxInt32, + argLen: 2, + asm: ppc64.AISEL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SETBC", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ASETBC, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "SETBCR", + auxType: auxInt32, + argLen: 1, + asm: ppc64.ASETBCR, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "Equal", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "NotEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LessThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FLessThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LessEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FLessEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "GreaterThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FGreaterThan", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "GreaterEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "FGreaterEqual", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 2048}, // R11 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + clobberFlags: true, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + clobbers: 2147483648, // R31 + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + outputs: []outputInfo{ + {0, 9223372032559808512}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4096}, // R12 + {1, 2048}, // R11 + }, + clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4096}, // R12 + }, + clobbers: 18446744071562059768, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1048576}, // R20 + }, + clobbers: 1048576, // R20 + }, + }, + { + name: "LoweredZeroShort", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredQuadZeroShort", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredQuadZero", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1048576}, // R20 + }, + clobbers: 1048576, // R20 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1048576}, // R20 + {1, 2097152}, // R21 + }, + clobbers: 3145728, // R20 R21 + }, + }, + { + name: "LoweredMoveShort", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredQuadMove", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1048576}, // R20 + {1, 2097152}, // R21 + }, + clobbers: 3145728, // R20 R21 + }, + }, + { + name: "LoweredQuadMoveShort", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicStore8", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicStore32", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicStore64", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoad8", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicLoadPtr", + auxType: auxInt64, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicExchange8", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicCas64", + auxType: auxInt64, + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicCas32", + auxType: auxInt64, + argLen: 4, + resultNotInArgs: true, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + outputs: []outputInfo{ + {0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAnd8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicOr8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: ppc64.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + {1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: 18446744072632408064, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 XER + outputs: []outputInfo{ + {0, 536870912}, // R29 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: ppc64.ALWSYNC, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 32}, // R5 + {1, 64}, // R6 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 16}, // R4 + {1, 32}, // R5 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 8}, // R3 + {1, 16}, // R4 + }, + }, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "FlagEQ", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagLT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagGT", + argLen: 0, + reg: regInfo{}, + }, + + { + name: "ADD", + argLen: 2, + commutative: true, + asm: riscv.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ADDI", + auxType: auxInt64, + argLen: 1, + asm: riscv.AADDI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ADDIW", + auxType: auxInt64, + argLen: 1, + asm: riscv.AADDIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "NEG", + argLen: 1, + asm: riscv.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "NEGW", + argLen: 1, + asm: riscv.ANEGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SUB", + argLen: 2, + asm: riscv.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SUBW", + argLen: 2, + asm: riscv.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MUL", + argLen: 2, + commutative: true, + asm: riscv.AMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MULW", + argLen: 2, + commutative: true, + asm: riscv.AMULW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MULH", + argLen: 2, + commutative: true, + asm: riscv.AMULH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MULHU", + argLen: 2, + commutative: true, + asm: riscv.AMULHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredMuluhilo", + argLen: 2, + resultNotInArgs: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredMuluover", + argLen: 2, + resultNotInArgs: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIV", + argLen: 2, + asm: riscv.ADIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIVU", + argLen: 2, + asm: riscv.ADIVU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + asm: riscv.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "DIVUW", + argLen: 2, + asm: riscv.ADIVUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REM", + argLen: 2, + asm: riscv.AREM, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REMU", + argLen: 2, + asm: riscv.AREMU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REMW", + argLen: 2, + asm: riscv.AREMW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REMUW", + argLen: 2, + asm: riscv.AREMUW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: riscv.AMOV, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWUload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVBstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVHstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVWstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVDstorezero", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + asm: riscv.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + asm: riscv.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + asm: riscv.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDreg", + argLen: 1, + asm: riscv.AMOV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVBUreg", + argLen: 1, + asm: riscv.AMOVBU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVHUreg", + argLen: 1, + asm: riscv.AMOVHU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVWUreg", + argLen: 1, + asm: riscv.AMOVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MOVDnop", + argLen: 1, + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLL", + argLen: 2, + asm: riscv.ASLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLLW", + argLen: 2, + asm: riscv.ASLLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRA", + argLen: 2, + asm: riscv.ASRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRAW", + argLen: 2, + asm: riscv.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRL", + argLen: 2, + asm: riscv.ASRL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRLW", + argLen: 2, + asm: riscv.ASRLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLLI", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASLLI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLLIW", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASLLIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRAI", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASRAI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRAIW", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASRAIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRLI", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASRLI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SRLIW", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASRLIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SH1ADD", + argLen: 2, + asm: riscv.ASH1ADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SH2ADD", + argLen: 2, + asm: riscv.ASH2ADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SH3ADD", + argLen: 2, + asm: riscv.ASH3ADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + asm: riscv.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ANDN", + argLen: 2, + asm: riscv.AANDN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ANDI", + auxType: auxInt64, + argLen: 1, + asm: riscv.AANDI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CLZ", + argLen: 1, + asm: riscv.ACLZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CLZW", + argLen: 1, + asm: riscv.ACLZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOP", + argLen: 1, + asm: riscv.ACPOP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CPOPW", + argLen: 1, + asm: riscv.ACPOPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CTZ", + argLen: 1, + asm: riscv.ACTZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "CTZW", + argLen: 1, + asm: riscv.ACTZW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "NOT", + argLen: 1, + asm: riscv.ANOT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + asm: riscv.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ORN", + argLen: 2, + asm: riscv.AORN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ORI", + auxType: auxInt64, + argLen: 1, + asm: riscv.AORI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "REV8", + argLen: 1, + asm: riscv.AREV8, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ROL", + argLen: 2, + asm: riscv.AROL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ROLW", + argLen: 2, + asm: riscv.AROLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "ROR", + argLen: 2, + asm: riscv.AROR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "RORI", + auxType: auxInt64, + argLen: 1, + asm: riscv.ARORI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "RORIW", + auxType: auxInt64, + argLen: 1, + asm: riscv.ARORIW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "RORW", + argLen: 2, + asm: riscv.ARORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "XNOR", + argLen: 2, + commutative: true, + asm: riscv.AXNOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + asm: riscv.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "XORI", + auxType: auxInt64, + argLen: 1, + asm: riscv.AXORI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MIN", + argLen: 2, + commutative: true, + asm: riscv.AMIN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MAX", + argLen: 2, + commutative: true, + asm: riscv.AMAX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MINU", + argLen: 2, + commutative: true, + asm: riscv.AMINU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "MAXU", + argLen: 2, + commutative: true, + asm: riscv.AMAXU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SEQZ", + argLen: 1, + asm: riscv.ASEQZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SNEZ", + argLen: 1, + asm: riscv.ASNEZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLT", + argLen: 2, + asm: riscv.ASLT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLTI", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASLTI, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLTU", + argLen: 2, + asm: riscv.ASLTU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "SLTIU", + auxType: auxInt64, + argLen: 1, + asm: riscv.ASLTIU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: -1, + call: true, + reg: regInfo{ + clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: -1, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: -1, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 33554432}, // X26 + {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: -1, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + { + name: "DUFFZERO", + auxType: auxInt64, + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 16777216}, // X25 + }, + clobbers: 16777216, // X25 + }, + }, + { + name: "DUFFCOPY", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 16777216}, // X25 + {1, 8388608}, // X24 + }, + clobbers: 25165824, // X24 X25 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 16}, // X5 + {1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: 16, // X5 + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 16}, // X5 + {1, 32}, // X6 + {2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + clobbers: 112, // X5 X6 X7 + }, + }, + { + name: "LoweredAtomicLoad8", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicLoad32", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicLoad64", + argLen: 2, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicStore8", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicStore32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicStore64", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicExchange32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicAdd32", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicAdd64", + argLen: 3, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicCas32", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicCas64", + argLen: 4, + resultNotInArgs: true, + faultOnNilArg0: true, + hasSideEffects: true, + unsafePoint: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {2, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredAtomicAnd32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: riscv.AAMOANDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredAtomicOr32", + argLen: 3, + faultOnNilArg0: true, + hasSideEffects: true, + asm: riscv.AAMOORW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1073741808}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 + {0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + reg: regInfo{ + outputs: []outputInfo{ + {0, 33554432}, // X26 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + outputs: []outputInfo{ + {0, 8388608}, // X24 + }, + }, + }, + { + name: "LoweredPubBarrier", + argLen: 1, + hasSideEffects: true, + asm: riscv.AFENCE, + reg: regInfo{}, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 64}, // X7 + {1, 134217728}, // X28 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 32}, // X6 + {1, 64}, // X7 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 16}, // X5 + {1, 32}, // X6 + }, + }, + }, + { + name: "FADDS", + argLen: 2, + commutative: true, + asm: riscv.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + asm: riscv.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + asm: riscv.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + asm: riscv.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + commutative: true, + asm: riscv.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + commutative: true, + asm: riscv.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDS", + argLen: 3, + commutative: true, + asm: riscv.AFNMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBS", + argLen: 3, + commutative: true, + asm: riscv.AFNMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + asm: riscv.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNEGS", + argLen: 1, + asm: riscv.AFNEGS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMVSX", + argLen: 1, + asm: riscv.AFMVSX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTSW", + argLen: 1, + asm: riscv.AFCVTSW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTSL", + argLen: 1, + asm: riscv.AFCVTSL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTWS", + argLen: 1, + asm: riscv.AFCVTWS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTLS", + argLen: 1, + asm: riscv.AFCVTLS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FMOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVF, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FEQS", + argLen: 2, + commutative: true, + asm: riscv.AFEQS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FNES", + argLen: 2, + commutative: true, + asm: riscv.AFNES, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLTS", + argLen: 2, + asm: riscv.AFLTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLES", + argLen: 2, + asm: riscv.AFLES, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredFMAXS", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: riscv.AFMAXS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredFMINS", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: riscv.AFMINS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FADDD", + argLen: 2, + commutative: true, + asm: riscv.AFADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSUBD", + argLen: 2, + asm: riscv.AFSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMULD", + argLen: 2, + commutative: true, + asm: riscv.AFMULD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FDIVD", + argLen: 2, + asm: riscv.AFDIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMADDD", + argLen: 3, + commutative: true, + asm: riscv.AFMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMSUBD", + argLen: 3, + commutative: true, + asm: riscv.AFMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMADDD", + argLen: 3, + commutative: true, + asm: riscv.AFNMADDD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNMSUBD", + argLen: 3, + commutative: true, + asm: riscv.AFNMSUBD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSQRTD", + argLen: 1, + asm: riscv.AFSQRTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FNEGD", + argLen: 1, + asm: riscv.AFNEGD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FABSD", + argLen: 1, + asm: riscv.AFABSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FSGNJD", + argLen: 2, + asm: riscv.AFSGNJD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMVDX", + argLen: 1, + asm: riscv.AFMVDX, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTDW", + argLen: 1, + asm: riscv.AFCVTDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTDL", + argLen: 1, + asm: riscv.AFCVTDL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTWD", + argLen: 1, + asm: riscv.AFCVTWD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTLD", + argLen: 1, + asm: riscv.AFCVTLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FCVTDS", + argLen: 1, + asm: riscv.AFCVTDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FCVTSD", + argLen: 1, + asm: riscv.AFCVTSD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: riscv.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: riscv.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "FEQD", + argLen: 2, + commutative: true, + asm: riscv.AFEQD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FNED", + argLen: 2, + commutative: true, + asm: riscv.AFNED, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLTD", + argLen: 2, + asm: riscv.AFLTD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "FLED", + argLen: 2, + asm: riscv.AFLED, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 + }, + }, + }, + { + name: "LoweredFMIND", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: riscv.AFMIND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "LoweredFMAXD", + argLen: 2, + commutative: true, + resultNotInArgs: true, + asm: riscv.AFMAXD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + + { + name: "FADDS", + argLen: 2, + commutative: true, + resultInArg0: true, + asm: s390x.AFADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FADD", + argLen: 2, + commutative: true, + resultInArg0: true, + asm: s390x.AFADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FSUBS", + argLen: 2, + resultInArg0: true, + asm: s390x.AFSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FSUB", + argLen: 2, + resultInArg0: true, + asm: s390x.AFSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMULS", + argLen: 2, + commutative: true, + resultInArg0: true, + asm: s390x.AFMULS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMUL", + argLen: 2, + commutative: true, + resultInArg0: true, + asm: s390x.AFMUL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FDIVS", + argLen: 2, + resultInArg0: true, + asm: s390x.AFDIVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FDIV", + argLen: 2, + resultInArg0: true, + asm: s390x.AFDIV, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FNEGS", + argLen: 1, + clobberFlags: true, + asm: s390x.AFNEGS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FNEG", + argLen: 1, + clobberFlags: true, + asm: s390x.AFNEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMADDS", + argLen: 3, + resultInArg0: true, + asm: s390x.AFMADDS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMADD", + argLen: 3, + resultInArg0: true, + asm: s390x.AFMADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMSUBS", + argLen: 3, + resultInArg0: true, + asm: s390x.AFMSUBS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMSUB", + argLen: 3, + resultInArg0: true, + asm: s390x.AFMSUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LPDFR", + argLen: 1, + asm: s390x.ALPDFR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LNDFR", + argLen: 1, + asm: s390x.ALNDFR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CPSDR", + argLen: 2, + asm: s390x.ACPSDR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FIDBR", + auxType: auxInt8, + argLen: 1, + asm: s390x.AFIDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSconst", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + asm: s390x.AFMOVS, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDconst", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + asm: s390x.AFMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSloadidx", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDloadidx", + auxType: auxSymOff, + argLen: 3, + symEffect: SymRead, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVSstoreidx", + auxType: auxSymOff, + argLen: 4, + symEffect: SymWrite, + asm: s390x.AFMOVS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FMOVDstoreidx", + auxType: auxSymOff, + argLen: 4, + symEffect: SymWrite, + asm: s390x.AFMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "ADD", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDW", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AADDW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDconst", + auxType: auxInt32, + argLen: 1, + clobberFlags: true, + asm: s390x.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDWconst", + auxType: auxInt32, + argLen: 1, + clobberFlags: true, + asm: s390x.AADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AADD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AADDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUB", + argLen: 2, + clobberFlags: true, + asm: s390x.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBW", + argLen: 2, + clobberFlags: true, + asm: s390x.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.ASUB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.ASUBW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLD", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLW", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLDconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLDload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AMULLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULLWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AMULLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MULHD", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMULHD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MULHDU", + argLen: 2, + commutative: true, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMULHDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVD", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVW", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVDU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "DIVWU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ADIVWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODD", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODW", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODDU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODDU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "MODWU", + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AMODWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + clobbers: 2048, // R11 + outputs: []outputInfo{ + {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 + }, + }, + }, + { + name: "AND", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDW", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AANDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDconst", + auxType: auxInt64, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AANDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AAND, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ANDWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AANDW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "OR", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORW", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORconst", + auxType: auxInt64, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ORWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XOR", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORW", + argLen: 2, + commutative: true, + clobberFlags: true, + asm: s390x.AXORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORconst", + auxType: auxInt64, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORWconst", + auxType: auxInt32, + argLen: 1, + resultInArg0: true, + clobberFlags: true, + asm: s390x.AXORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AXOR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "XORWload", + auxType: auxSymOff, + argLen: 3, + resultInArg0: true, + clobberFlags: true, + faultOnNilArg1: true, + symEffect: SymRead, + asm: s390x.AXORW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDC", + argLen: 2, + commutative: true, + asm: s390x.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDCconst", + auxType: auxInt16, + argLen: 1, + asm: s390x.AADDC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "ADDE", + argLen: 3, + commutative: true, + resultInArg0: true, + asm: s390x.AADDE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBC", + argLen: 2, + asm: s390x.ASUBC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SUBE", + argLen: 3, + resultInArg0: true, + asm: s390x.ASUBE, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CMP", + argLen: 2, + asm: s390x.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPW", + argLen: 2, + asm: s390x.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPU", + argLen: 2, + asm: s390x.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPWU", + argLen: 2, + asm: s390x.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMP, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPWconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMPW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPUconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "CMPWUconst", + auxType: auxInt32, + argLen: 1, + asm: s390x.ACMPWU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "FCMPS", + argLen: 2, + asm: s390x.ACEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FCMP", + argLen: 2, + asm: s390x.AFCMPU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LTDBR", + argLen: 1, + asm: s390x.ALTDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LTEBR", + argLen: 1, + asm: s390x.ALTEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "SLD", + argLen: 2, + asm: s390x.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SLW", + argLen: 2, + asm: s390x.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SLDconst", + auxType: auxUInt8, + argLen: 1, + asm: s390x.ASLD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SLWconst", + auxType: auxUInt8, + argLen: 1, + asm: s390x.ASLW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRD", + argLen: 2, + asm: s390x.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRW", + argLen: 2, + asm: s390x.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRDconst", + auxType: auxUInt8, + argLen: 1, + asm: s390x.ASRD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRWconst", + auxType: auxUInt8, + argLen: 1, + asm: s390x.ASRW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRAD", + argLen: 2, + clobberFlags: true, + asm: s390x.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRAW", + argLen: 2, + clobberFlags: true, + asm: s390x.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRADconst", + auxType: auxUInt8, + argLen: 1, + clobberFlags: true, + asm: s390x.ASRAD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "SRAWconst", + auxType: auxUInt8, + argLen: 1, + clobberFlags: true, + asm: s390x.ASRAW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RLLG", + argLen: 2, + asm: s390x.ARLLG, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RLL", + argLen: 2, + asm: s390x.ARLL, + reg: regInfo{ + inputs: []inputInfo{ + {1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RLLconst", + auxType: auxUInt8, + argLen: 1, + asm: s390x.ARLL, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RXSBG", + auxType: auxS390XRotateParams, + argLen: 2, + resultInArg0: true, + clobberFlags: true, + asm: s390x.ARXSBG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "RISBGZ", + auxType: auxS390XRotateParams, + argLen: 1, + clobberFlags: true, + asm: s390x.ARISBGZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NEG", + argLen: 1, + clobberFlags: true, + asm: s390x.ANEG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NEGW", + argLen: 1, + clobberFlags: true, + asm: s390x.ANEGW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NOT", + argLen: 1, + resultInArg0: true, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "NOTW", + argLen: 1, + resultInArg0: true, + clobberFlags: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "FSQRT", + argLen: 1, + asm: s390x.AFSQRT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "FSQRTS", + argLen: 1, + asm: s390x.AFSQRTS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LOCGR", + auxType: auxS390XCCMask, + argLen: 3, + resultInArg0: true, + asm: s390x.ALOCGR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + {1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBreg", + argLen: 1, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBZreg", + argLen: 1, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHreg", + argLen: 1, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHZreg", + argLen: 1, + asm: s390x.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWreg", + argLen: 1, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZreg", + argLen: 1, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDconst", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + asm: s390x.AMOVD, + reg: regInfo{ + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LDGR", + argLen: 1, + asm: s390x.ALDGR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LGDR", + argLen: 1, + asm: s390x.ALGDR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CFDBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACFDBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CGDBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACGDBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CFEBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACFEBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CGEBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACGEBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CEFBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACEFBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDFBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACDFBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CEGBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACEGBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDGBRA", + argLen: 1, + clobberFlags: true, + asm: s390x.ACDGBRA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CLFEBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACLFEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CLFDBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACLFDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CLGEBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACLGEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CLGDBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACLGDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CELFBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACELFBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDLFBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACDLFBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CELGBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACELGBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "CDLGBR", + argLen: 1, + clobberFlags: true, + asm: s390x.ACDLGBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LEDBR", + argLen: 1, + asm: s390x.ALEDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LDEBR", + argLen: 1, + asm: s390x.ALDEBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "MOVDaddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295000064}, // SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDaddridx", + auxType: auxSymOff, + argLen: 2, + symEffect: SymAddr, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295000064}, // SP SB + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWBR", + argLen: 1, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDBR", + argLen: 1, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHBRload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWBRload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDBRload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHBRstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWBRstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDBRstore", + auxType: auxSymOff, + argLen: 3, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MVC", + auxType: auxSymValAndOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + symEffect: SymNone, + asm: s390x.AMVC, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVBZloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHZloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVHZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVHBRloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWBRloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDBRloadidx", + auxType: auxSymOff, + argLen: 3, + commutative: true, + symEffect: SymRead, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVHBRstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVHBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWBRstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVWBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDBRstoreidx", + auxType: auxSymOff, + argLen: 4, + commutative: true, + symEffect: SymWrite, + asm: s390x.AMOVDBR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVBstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "MOVHstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVH, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "MOVWstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "MOVDstoreconst", + auxType: auxSymValAndOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + }, + }, + { + name: "CLEAR", + auxType: auxSymValAndOff, + argLen: 2, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ACLEAR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "CALLstatic", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + reg: regInfo{ + clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLtail", + auxType: auxCallOff, + argLen: 1, + clobberFlags: true, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLclosure", + auxType: auxCallOff, + argLen: 3, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4096}, // R12 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "CALLinter", + auxType: auxCallOff, + argLen: 2, + clobberFlags: true, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + { + name: "InvertFlags", + argLen: 1, + reg: regInfo{}, + }, + { + name: "LoweredGetG", + argLen: 1, + reg: regInfo{ + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + zeroWidth: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4096}, // R12 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + clobberFlags: true, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LoweredRound32F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LoweredRound64F", + argLen: 1, + resultInArg0: true, + zeroWidth: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + clobberFlags: true, + reg: regInfo{ + clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + outputs: []outputInfo{ + {0, 512}, // R9 + }, + }, + }, + { + name: "LoweredPanicBoundsA", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4}, // R2 + {1, 8}, // R3 + }, + }, + }, + { + name: "LoweredPanicBoundsB", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 4}, // R2 + }, + }, + }, + { + name: "LoweredPanicBoundsC", + auxType: auxInt64, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1}, // R0 + {1, 2}, // R1 + }, + }, + }, + { + name: "FlagEQ", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagLT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagGT", + argLen: 0, + reg: regInfo{}, + }, + { + name: "FlagOV", + argLen: 0, + reg: regInfo{}, + }, + { + name: "SYNC", + argLen: 1, + asm: s390x.ASYNC, + reg: regInfo{}, + }, + { + name: "MOVBZatomicload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVBZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVWZatomicload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVWZ, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVDatomicload", + auxType: auxSymOff, + argLen: 2, + faultOnNilArg0: true, + symEffect: SymRead, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MOVBatomicstore", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymWrite, + asm: s390x.AMOVB, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVWatomicstore", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymWrite, + asm: s390x.AMOVW, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "MOVDatomicstore", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymWrite, + asm: s390x.AMOVD, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LAA", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ALAA, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LAAG", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ALAAG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "AddTupleFirst32", + argLen: 2, + reg: regInfo{}, + }, + { + name: "AddTupleFirst64", + argLen: 2, + reg: regInfo{}, + }, + { + name: "LAN", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LANfloor", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAN, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 2, // R1 + }, + }, + { + name: "LAO", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAO, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LAOfloor", + argLen: 3, + clobberFlags: true, + hasSideEffects: true, + asm: s390x.ALAO, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 2, // R1 + }, + }, + { + name: "LoweredAtomicCas32", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACS, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1}, // R0 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 1, // R0 + outputs: []outputInfo{ + {1, 0}, + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredAtomicCas64", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACSG, + reg: regInfo{ + inputs: []inputInfo{ + {1, 1}, // R0 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 1, // R0 + outputs: []outputInfo{ + {1, 0}, + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "LoweredAtomicExchange32", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {1, 0}, + {0, 1}, // R0 + }, + }, + }, + { + name: "LoweredAtomicExchange64", + auxType: auxSymOff, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + hasSideEffects: true, + symEffect: SymRdWr, + asm: s390x.ACSG, + reg: regInfo{ + inputs: []inputInfo{ + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + {1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + outputs: []outputInfo{ + {1, 0}, + {0, 1}, // R0 + }, + }, + }, + { + name: "FLOGR", + argLen: 1, + clobberFlags: true, + asm: s390x.AFLOGR, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + clobbers: 2, // R1 + outputs: []outputInfo{ + {0, 1}, // R0 + }, + }, + }, + { + name: "POPCNT", + argLen: 1, + clobberFlags: true, + asm: s390x.APOPCNT, + reg: regInfo{ + inputs: []inputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + }, + }, + { + name: "MLGR", + argLen: 2, + asm: s390x.AMLGR, + reg: regInfo{ + inputs: []inputInfo{ + {1, 8}, // R3 + {0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 + }, + outputs: []outputInfo{ + {0, 4}, // R2 + {1, 8}, // R3 + }, + }, + }, + { + name: "SumBytes2", + argLen: 1, + reg: regInfo{}, + }, + { + name: "SumBytes4", + argLen: 1, + reg: regInfo{}, + }, + { + name: "SumBytes8", + argLen: 1, + reg: regInfo{}, + }, + { + name: "STMG2", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMG, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // R1 + {2, 4}, // R2 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STMG3", + auxType: auxSymOff, + argLen: 5, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMG, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // R1 + {2, 4}, // R2 + {3, 8}, // R3 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STMG4", + auxType: auxSymOff, + argLen: 6, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMG, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // R1 + {2, 4}, // R2 + {3, 8}, // R3 + {4, 16}, // R4 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STM2", + auxType: auxSymOff, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // R1 + {2, 4}, // R2 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STM3", + auxType: auxSymOff, + argLen: 5, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // R1 + {2, 4}, // R2 + {3, 8}, // R3 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "STM4", + auxType: auxSymOff, + argLen: 6, + clobberFlags: true, + faultOnNilArg0: true, + symEffect: SymWrite, + asm: s390x.ASTMY, + reg: regInfo{ + inputs: []inputInfo{ + {1, 2}, // R1 + {2, 4}, // R2 + {3, 8}, // R3 + {4, 16}, // R4 + {0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 4, + clobberFlags: true, + faultOnNilArg0: true, + faultOnNilArg1: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 4}, // R2 + {2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 6, // R1 R2 + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 3, + clobberFlags: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 2}, // R1 + {1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP + }, + clobbers: 2, // R1 + }, + }, + + { + name: "LoweredStaticCall", + auxType: auxCallOff, + argLen: 1, + call: true, + reg: regInfo{ + clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g + }, + }, + { + name: "LoweredTailCall", + auxType: auxCallOff, + argLen: 1, + call: true, + tailCall: true, + reg: regInfo{ + clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g + }, + }, + { + name: "LoweredClosureCall", + auxType: auxCallOff, + argLen: 3, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g + }, + }, + { + name: "LoweredInterCall", + auxType: auxCallOff, + argLen: 2, + call: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g + }, + }, + { + name: "LoweredAddr", + auxType: auxSymOff, + argLen: 1, + rematerializeable: true, + symEffect: SymAddr, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredMove", + auxType: auxInt64, + argLen: 3, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + {1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredZero", + auxType: auxInt64, + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredGetClosurePtr", + argLen: 0, + reg: regInfo{ + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredGetCallerPC", + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredGetCallerSP", + argLen: 1, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredNilCheck", + argLen: 2, + nilCheck: true, + faultOnNilArg0: true, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredWB", + auxType: auxInt64, + argLen: 1, + reg: regInfo{ + clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "LoweredConvert", + argLen: 2, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "Select", + argLen: 3, + asm: wasm.ASelect, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load8U", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load8U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load8S", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load16U", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load16U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load16S", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load32U", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load32U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load32S", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load32S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Load", + auxType: auxInt64, + argLen: 2, + asm: wasm.AI64Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Store8", + auxType: auxInt64, + argLen: 3, + asm: wasm.AI64Store8, + reg: regInfo{ + inputs: []inputInfo{ + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Store16", + auxType: auxInt64, + argLen: 3, + asm: wasm.AI64Store16, + reg: regInfo{ + inputs: []inputInfo{ + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Store32", + auxType: auxInt64, + argLen: 3, + asm: wasm.AI64Store32, + reg: regInfo{ + inputs: []inputInfo{ + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Store", + auxType: auxInt64, + argLen: 3, + asm: wasm.AI64Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "F32Load", + auxType: auxInt64, + argLen: 2, + asm: wasm.AF32Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Load", + auxType: auxInt64, + argLen: 2, + asm: wasm.AF64Load, + reg: regInfo{ + inputs: []inputInfo{ + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F32Store", + auxType: auxInt64, + argLen: 3, + asm: wasm.AF32Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "F64Store", + auxType: auxInt64, + argLen: 3, + asm: wasm.AF64Store, + reg: regInfo{ + inputs: []inputInfo{ + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB + }, + }, + }, + { + name: "I64Const", + auxType: auxInt64, + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Const", + auxType: auxFloat32, + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Const", + auxType: auxFloat64, + argLen: 0, + rematerializeable: true, + reg: regInfo{ + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64Eqz", + argLen: 1, + asm: wasm.AI64Eqz, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Eq", + argLen: 2, + asm: wasm.AI64Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Ne", + argLen: 2, + asm: wasm.AI64Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LtS", + argLen: 2, + asm: wasm.AI64LtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LtU", + argLen: 2, + asm: wasm.AI64LtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GtS", + argLen: 2, + asm: wasm.AI64GtS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GtU", + argLen: 2, + asm: wasm.AI64GtU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LeS", + argLen: 2, + asm: wasm.AI64LeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64LeU", + argLen: 2, + asm: wasm.AI64LeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GeS", + argLen: 2, + asm: wasm.AI64GeS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64GeU", + argLen: 2, + asm: wasm.AI64GeU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Eq", + argLen: 2, + asm: wasm.AF32Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Ne", + argLen: 2, + asm: wasm.AF32Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Lt", + argLen: 2, + asm: wasm.AF32Lt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Gt", + argLen: 2, + asm: wasm.AF32Gt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Le", + argLen: 2, + asm: wasm.AF32Le, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Ge", + argLen: 2, + asm: wasm.AF32Ge, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Eq", + argLen: 2, + asm: wasm.AF64Eq, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Ne", + argLen: 2, + asm: wasm.AF64Ne, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Lt", + argLen: 2, + asm: wasm.AF64Lt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Gt", + argLen: 2, + asm: wasm.AF64Gt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Le", + argLen: 2, + asm: wasm.AF64Le, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F64Ge", + argLen: 2, + asm: wasm.AF64Ge, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Add", + argLen: 2, + asm: wasm.AI64Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64AddConst", + auxType: auxInt64, + argLen: 1, + asm: wasm.AI64Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Sub", + argLen: 2, + asm: wasm.AI64Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Mul", + argLen: 2, + asm: wasm.AI64Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64DivS", + argLen: 2, + asm: wasm.AI64DivS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64DivU", + argLen: 2, + asm: wasm.AI64DivU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64RemS", + argLen: 2, + asm: wasm.AI64RemS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64RemU", + argLen: 2, + asm: wasm.AI64RemU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64And", + argLen: 2, + asm: wasm.AI64And, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Or", + argLen: 2, + asm: wasm.AI64Or, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Xor", + argLen: 2, + asm: wasm.AI64Xor, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Shl", + argLen: 2, + asm: wasm.AI64Shl, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64ShrS", + argLen: 2, + asm: wasm.AI64ShrS, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64ShrU", + argLen: 2, + asm: wasm.AI64ShrU, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Neg", + argLen: 1, + asm: wasm.AF32Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Add", + argLen: 2, + asm: wasm.AF32Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Sub", + argLen: 2, + asm: wasm.AF32Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Mul", + argLen: 2, + asm: wasm.AF32Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Div", + argLen: 2, + asm: wasm.AF32Div, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Neg", + argLen: 1, + asm: wasm.AF64Neg, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Add", + argLen: 2, + asm: wasm.AF64Add, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Sub", + argLen: 2, + asm: wasm.AF64Sub, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Mul", + argLen: 2, + asm: wasm.AF64Mul, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Div", + argLen: 2, + asm: wasm.AF64Div, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64TruncSatF64S", + argLen: 1, + asm: wasm.AI64TruncSatF64S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64TruncSatF64U", + argLen: 1, + asm: wasm.AI64TruncSatF64U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64TruncSatF32S", + argLen: 1, + asm: wasm.AI64TruncSatF32S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64TruncSatF32U", + argLen: 1, + asm: wasm.AI64TruncSatF32U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32ConvertI64S", + argLen: 1, + asm: wasm.AF32ConvertI64S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32ConvertI64U", + argLen: 1, + asm: wasm.AF32ConvertI64U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64ConvertI64S", + argLen: 1, + asm: wasm.AF64ConvertI64S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64ConvertI64U", + argLen: 1, + asm: wasm.AF64ConvertI64U, + reg: regInfo{ + inputs: []inputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F32DemoteF64", + argLen: 1, + asm: wasm.AF32DemoteF64, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64PromoteF32", + argLen: 1, + asm: wasm.AF64PromoteF32, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64Extend8S", + argLen: 1, + asm: wasm.AI64Extend8S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Extend16S", + argLen: 1, + asm: wasm.AI64Extend16S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Extend32S", + argLen: 1, + asm: wasm.AI64Extend32S, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "F32Sqrt", + argLen: 1, + asm: wasm.AF32Sqrt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Trunc", + argLen: 1, + asm: wasm.AF32Trunc, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Ceil", + argLen: 1, + asm: wasm.AF32Ceil, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Floor", + argLen: 1, + asm: wasm.AF32Floor, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Nearest", + argLen: 1, + asm: wasm.AF32Nearest, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Abs", + argLen: 1, + asm: wasm.AF32Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F32Copysign", + argLen: 2, + asm: wasm.AF32Copysign, + reg: regInfo{ + inputs: []inputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + outputs: []outputInfo{ + {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 + }, + }, + }, + { + name: "F64Sqrt", + argLen: 1, + asm: wasm.AF64Sqrt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Trunc", + argLen: 1, + asm: wasm.AF64Trunc, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Ceil", + argLen: 1, + asm: wasm.AF64Ceil, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Floor", + argLen: 1, + asm: wasm.AF64Floor, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Nearest", + argLen: 1, + asm: wasm.AF64Nearest, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Abs", + argLen: 1, + asm: wasm.AF64Abs, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "F64Copysign", + argLen: 2, + asm: wasm.AF64Copysign, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + outputs: []outputInfo{ + {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 + }, + }, + }, + { + name: "I64Ctz", + argLen: 1, + asm: wasm.AI64Ctz, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Clz", + argLen: 1, + asm: wasm.AI64Clz, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I32Rotl", + argLen: 2, + asm: wasm.AI32Rotl, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Rotl", + argLen: 2, + asm: wasm.AI64Rotl, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + { + name: "I64Popcnt", + argLen: 1, + asm: wasm.AI64Popcnt, + reg: regInfo{ + inputs: []inputInfo{ + {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP + }, + outputs: []outputInfo{ + {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + }, + }, + }, + + { + name: "Add8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddPtr", + argLen: 2, + generic: true, + }, + { + name: "Add32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Sub8", + argLen: 2, + generic: true, + }, + { + name: "Sub16", + argLen: 2, + generic: true, + }, + { + name: "Sub32", + argLen: 2, + generic: true, + }, + { + name: "Sub64", + argLen: 2, + generic: true, + }, + { + name: "SubPtr", + argLen: 2, + generic: true, + }, + { + name: "Sub32F", + argLen: 2, + generic: true, + }, + { + name: "Sub64F", + argLen: 2, + generic: true, + }, + { + name: "Mul8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Div32F", + argLen: 2, + generic: true, + }, + { + name: "Div64F", + argLen: 2, + generic: true, + }, + { + name: "Hmul32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Hmul32u", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Hmul64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Hmul64u", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32uhilo", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64uhilo", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul32uover", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Mul64uover", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Avg32u", + argLen: 2, + generic: true, + }, + { + name: "Avg64u", + argLen: 2, + generic: true, + }, + { + name: "Div8", + argLen: 2, + generic: true, + }, + { + name: "Div8u", + argLen: 2, + generic: true, + }, + { + name: "Div16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Div16u", + argLen: 2, + generic: true, + }, + { + name: "Div32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Div32u", + argLen: 2, + generic: true, + }, + { + name: "Div64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Div64u", + argLen: 2, + generic: true, + }, + { + name: "Div128u", + argLen: 3, + generic: true, + }, + { + name: "Mod8", + argLen: 2, + generic: true, + }, + { + name: "Mod8u", + argLen: 2, + generic: true, + }, + { + name: "Mod16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Mod16u", + argLen: 2, + generic: true, + }, + { + name: "Mod32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Mod32u", + argLen: 2, + generic: true, + }, + { + name: "Mod64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Mod64u", + argLen: 2, + generic: true, + }, + { + name: "And8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "And64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Or64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Xor64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Lsh8x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh8x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh8x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh8x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh16x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh32x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Lsh64x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64x64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh8Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh16Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh32Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux8", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux16", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux32", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Rsh64Ux64", + auxType: auxBool, + argLen: 2, + generic: true, + }, + { + name: "Eq8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqPtr", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqInter", + argLen: 2, + generic: true, + }, + { + name: "EqSlice", + argLen: 2, + generic: true, + }, + { + name: "Eq32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Eq64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqPtr", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqInter", + argLen: 2, + generic: true, + }, + { + name: "NeqSlice", + argLen: 2, + generic: true, + }, + { + name: "Neq32F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Neq64F", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Less8", + argLen: 2, + generic: true, + }, + { + name: "Less8U", + argLen: 2, + generic: true, + }, + { + name: "Less16", + argLen: 2, + generic: true, + }, + { + name: "Less16U", + argLen: 2, + generic: true, + }, + { + name: "Less32", + argLen: 2, + generic: true, + }, + { + name: "Less32U", + argLen: 2, + generic: true, + }, + { + name: "Less64", + argLen: 2, + generic: true, + }, + { + name: "Less64U", + argLen: 2, + generic: true, + }, + { + name: "Less32F", + argLen: 2, + generic: true, + }, + { + name: "Less64F", + argLen: 2, + generic: true, + }, + { + name: "Leq8", + argLen: 2, + generic: true, + }, + { + name: "Leq8U", + argLen: 2, + generic: true, + }, + { + name: "Leq16", + argLen: 2, + generic: true, + }, + { + name: "Leq16U", + argLen: 2, + generic: true, + }, + { + name: "Leq32", + argLen: 2, + generic: true, + }, + { + name: "Leq32U", + argLen: 2, + generic: true, + }, + { + name: "Leq64", + argLen: 2, + generic: true, + }, + { + name: "Leq64U", + argLen: 2, + generic: true, + }, + { + name: "Leq32F", + argLen: 2, + generic: true, + }, + { + name: "Leq64F", + argLen: 2, + generic: true, + }, + { + name: "CondSelect", + argLen: 3, + generic: true, + }, + { + name: "AndB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NeqB", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Not", + argLen: 1, + generic: true, + }, + { + name: "Neg8", + argLen: 1, + generic: true, + }, + { + name: "Neg16", + argLen: 1, + generic: true, + }, + { + name: "Neg32", + argLen: 1, + generic: true, + }, + { + name: "Neg64", + argLen: 1, + generic: true, + }, + { + name: "Neg32F", + argLen: 1, + generic: true, + }, + { + name: "Neg64F", + argLen: 1, + generic: true, + }, + { + name: "Com8", + argLen: 1, + generic: true, + }, + { + name: "Com16", + argLen: 1, + generic: true, + }, + { + name: "Com32", + argLen: 1, + generic: true, + }, + { + name: "Com64", + argLen: 1, + generic: true, + }, + { + name: "Ctz8", + argLen: 1, + generic: true, + }, + { + name: "Ctz16", + argLen: 1, + generic: true, + }, + { + name: "Ctz32", + argLen: 1, + generic: true, + }, + { + name: "Ctz64", + argLen: 1, + generic: true, + }, + { + name: "Ctz64On32", + argLen: 2, + generic: true, + }, + { + name: "Ctz8NonZero", + argLen: 1, + generic: true, + }, + { + name: "Ctz16NonZero", + argLen: 1, + generic: true, + }, + { + name: "Ctz32NonZero", + argLen: 1, + generic: true, + }, + { + name: "Ctz64NonZero", + argLen: 1, + generic: true, + }, + { + name: "BitLen8", + argLen: 1, + generic: true, + }, + { + name: "BitLen16", + argLen: 1, + generic: true, + }, + { + name: "BitLen32", + argLen: 1, + generic: true, + }, + { + name: "BitLen64", + argLen: 1, + generic: true, + }, + { + name: "Bswap16", + argLen: 1, + generic: true, + }, + { + name: "Bswap32", + argLen: 1, + generic: true, + }, + { + name: "Bswap64", + argLen: 1, + generic: true, + }, + { + name: "BitRev8", + argLen: 1, + generic: true, + }, + { + name: "BitRev16", + argLen: 1, + generic: true, + }, + { + name: "BitRev32", + argLen: 1, + generic: true, + }, + { + name: "BitRev64", + argLen: 1, + generic: true, + }, + { + name: "PopCount8", + argLen: 1, + generic: true, + }, + { + name: "PopCount16", + argLen: 1, + generic: true, + }, + { + name: "PopCount32", + argLen: 1, + generic: true, + }, + { + name: "PopCount64", + argLen: 1, + generic: true, + }, + { + name: "RotateLeft64", + argLen: 2, + generic: true, + }, + { + name: "RotateLeft32", + argLen: 2, + generic: true, + }, + { + name: "RotateLeft16", + argLen: 2, + generic: true, + }, + { + name: "RotateLeft8", + argLen: 2, + generic: true, + }, + { + name: "Sqrt", + argLen: 1, + generic: true, + }, + { + name: "Sqrt32", + argLen: 1, + generic: true, + }, + { + name: "Floor", + argLen: 1, + generic: true, + }, + { + name: "Ceil", + argLen: 1, + generic: true, + }, + { + name: "Trunc", + argLen: 1, + generic: true, + }, + { + name: "Round", + argLen: 1, + generic: true, + }, + { + name: "RoundToEven", + argLen: 1, + generic: true, + }, + { + name: "Abs", + argLen: 1, + generic: true, + }, + { + name: "Copysign", + argLen: 2, + generic: true, + }, + { + name: "Min64", + argLen: 2, + generic: true, + }, + { + name: "Max64", + argLen: 2, + generic: true, + }, + { + name: "Min64u", + argLen: 2, + generic: true, + }, + { + name: "Max64u", + argLen: 2, + generic: true, + }, + { + name: "Min64F", + argLen: 2, + generic: true, + }, + { + name: "Min32F", + argLen: 2, + generic: true, + }, + { + name: "Max64F", + argLen: 2, + generic: true, + }, + { + name: "Max32F", + argLen: 2, + generic: true, + }, + { + name: "FMA", + argLen: 3, + generic: true, + }, + { + name: "Phi", + argLen: -1, + zeroWidth: true, + generic: true, + }, + { + name: "Copy", + argLen: 1, + generic: true, + }, + { + name: "Convert", + argLen: 2, + resultInArg0: true, + zeroWidth: true, + generic: true, + }, + { + name: "ConstBool", + auxType: auxBool, + argLen: 0, + generic: true, + }, + { + name: "ConstString", + auxType: auxString, + argLen: 0, + generic: true, + }, + { + name: "ConstNil", + argLen: 0, + generic: true, + }, + { + name: "Const8", + auxType: auxInt8, + argLen: 0, + generic: true, + }, + { + name: "Const16", + auxType: auxInt16, + argLen: 0, + generic: true, + }, + { + name: "Const32", + auxType: auxInt32, + argLen: 0, + generic: true, + }, + { + name: "Const64", + auxType: auxInt64, + argLen: 0, + generic: true, + }, + { + name: "Const32F", + auxType: auxFloat32, + argLen: 0, + generic: true, + }, + { + name: "Const64F", + auxType: auxFloat64, + argLen: 0, + generic: true, + }, + { + name: "ConstInterface", + argLen: 0, + generic: true, + }, + { + name: "ConstSlice", + argLen: 0, + generic: true, + }, + { + name: "InitMem", + argLen: 0, + zeroWidth: true, + generic: true, + }, + { + name: "Arg", + auxType: auxSymOff, + argLen: 0, + zeroWidth: true, + symEffect: SymRead, + generic: true, + }, + { + name: "ArgIntReg", + auxType: auxNameOffsetInt8, + argLen: 0, + zeroWidth: true, + generic: true, + }, + { + name: "ArgFloatReg", + auxType: auxNameOffsetInt8, + argLen: 0, + zeroWidth: true, + generic: true, + }, + { + name: "Addr", + auxType: auxSym, + argLen: 1, + symEffect: SymAddr, + generic: true, + }, + { + name: "LocalAddr", + auxType: auxSym, + argLen: 2, + symEffect: SymAddr, + generic: true, + }, + { + name: "SP", + argLen: 0, + zeroWidth: true, + fixedReg: true, + generic: true, + }, + { + name: "SB", + argLen: 0, + zeroWidth: true, + fixedReg: true, + generic: true, + }, + { + name: "SPanchored", + argLen: 2, + zeroWidth: true, + generic: true, + }, + { + name: "Load", + argLen: 2, + generic: true, + }, + { + name: "Dereference", + argLen: 2, + generic: true, + }, + { + name: "Store", + auxType: auxTyp, + argLen: 3, + generic: true, + }, + { + name: "Move", + auxType: auxTypSize, + argLen: 3, + generic: true, + }, + { + name: "Zero", + auxType: auxTypSize, + argLen: 2, + generic: true, + }, + { + name: "StoreWB", + auxType: auxTyp, + argLen: 3, + generic: true, + }, + { + name: "MoveWB", + auxType: auxTypSize, + argLen: 3, + generic: true, + }, + { + name: "ZeroWB", + auxType: auxTypSize, + argLen: 2, + generic: true, + }, + { + name: "WBend", + argLen: 1, + generic: true, + }, + { + name: "WB", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "HasCPUFeature", + auxType: auxSym, + argLen: 0, + symEffect: SymNone, + generic: true, + }, + { + name: "PanicBounds", + auxType: auxInt64, + argLen: 3, + call: true, + generic: true, + }, + { + name: "PanicExtend", + auxType: auxInt64, + argLen: 4, + call: true, + generic: true, + }, + { + name: "ClosureCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "StaticCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "InterCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "TailCall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "ClosureLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "StaticLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "InterLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "TailLECall", + auxType: auxCallOff, + argLen: -1, + call: true, + generic: true, + }, + { + name: "SignExt8to16", + argLen: 1, + generic: true, + }, + { + name: "SignExt8to32", + argLen: 1, + generic: true, + }, + { + name: "SignExt8to64", + argLen: 1, + generic: true, + }, + { + name: "SignExt16to32", + argLen: 1, + generic: true, + }, + { + name: "SignExt16to64", + argLen: 1, + generic: true, + }, + { + name: "SignExt32to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to16", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to32", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt8to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt16to32", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt16to64", + argLen: 1, + generic: true, + }, + { + name: "ZeroExt32to64", + argLen: 1, + generic: true, + }, + { + name: "Trunc16to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc32to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc32to16", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to8", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to16", + argLen: 1, + generic: true, + }, + { + name: "Trunc64to32", + argLen: 1, + generic: true, + }, + { + name: "Cvt32to32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32to64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64to32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64to64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto32", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto64", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32F", + argLen: 1, + generic: true, + }, + { + name: "CvtBoolToUint8", + argLen: 1, + generic: true, + }, + { + name: "Round32F", + argLen: 1, + generic: true, + }, + { + name: "Round64F", + argLen: 1, + generic: true, + }, + { + name: "IsNonNil", + argLen: 1, + generic: true, + }, + { + name: "IsInBounds", + argLen: 2, + generic: true, + }, + { + name: "IsSliceInBounds", + argLen: 2, + generic: true, + }, + { + name: "NilCheck", + argLen: 2, + nilCheck: true, + generic: true, + }, + { + name: "GetG", + argLen: 1, + zeroWidth: true, + generic: true, + }, + { + name: "GetClosurePtr", + argLen: 0, + generic: true, + }, + { + name: "GetCallerPC", + argLen: 0, + generic: true, + }, + { + name: "GetCallerSP", + argLen: 1, + generic: true, + }, + { + name: "PtrIndex", + argLen: 2, + generic: true, + }, + { + name: "OffPtr", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "SliceMake", + argLen: 3, + generic: true, + }, + { + name: "SlicePtr", + argLen: 1, + generic: true, + }, + { + name: "SliceLen", + argLen: 1, + generic: true, + }, + { + name: "SliceCap", + argLen: 1, + generic: true, + }, + { + name: "SlicePtrUnchecked", + argLen: 1, + generic: true, + }, + { + name: "ComplexMake", + argLen: 2, + generic: true, + }, + { + name: "ComplexReal", + argLen: 1, + generic: true, + }, + { + name: "ComplexImag", + argLen: 1, + generic: true, + }, + { + name: "StringMake", + argLen: 2, + generic: true, + }, + { + name: "StringPtr", + argLen: 1, + generic: true, + }, + { + name: "StringLen", + argLen: 1, + generic: true, + }, + { + name: "IMake", + argLen: 2, + generic: true, + }, + { + name: "ITab", + argLen: 1, + generic: true, + }, + { + name: "IData", + argLen: 1, + generic: true, + }, + { + name: "StructMake", + argLen: -1, + generic: true, + }, + { + name: "StructSelect", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "ArrayMake0", + argLen: 0, + generic: true, + }, + { + name: "ArrayMake1", + argLen: 1, + generic: true, + }, + { + name: "ArraySelect", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "StoreReg", + argLen: 1, + generic: true, + }, + { + name: "LoadReg", + argLen: 1, + generic: true, + }, + { + name: "FwdRef", + auxType: auxSym, + argLen: 0, + symEffect: SymNone, + generic: true, + }, + { + name: "Unknown", + argLen: 0, + generic: true, + }, + { + name: "VarDef", + auxType: auxSym, + argLen: 1, + zeroWidth: true, + symEffect: SymNone, + generic: true, + }, + { + name: "VarLive", + auxType: auxSym, + argLen: 1, + zeroWidth: true, + symEffect: SymRead, + generic: true, + }, + { + name: "KeepAlive", + argLen: 2, + zeroWidth: true, + generic: true, + }, + { + name: "InlMark", + auxType: auxInt32, + argLen: 1, + generic: true, + }, + { + name: "Int64Make", + argLen: 2, + generic: true, + }, + { + name: "Int64Hi", + argLen: 1, + generic: true, + }, + { + name: "Int64Lo", + argLen: 1, + generic: true, + }, + { + name: "Add32carry", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "Add32withcarry", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "Sub32carry", + argLen: 2, + generic: true, + }, + { + name: "Sub32withcarry", + argLen: 3, + generic: true, + }, + { + name: "Add64carry", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "Sub64borrow", + argLen: 3, + generic: true, + }, + { + name: "Signmask", + argLen: 1, + generic: true, + }, + { + name: "Zeromask", + argLen: 1, + generic: true, + }, + { + name: "Slicemask", + argLen: 1, + generic: true, + }, + { + name: "SpectreIndex", + argLen: 2, + generic: true, + }, + { + name: "SpectreSliceIndex", + argLen: 2, + generic: true, + }, + { + name: "Cvt32Uto32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Uto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto32U", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto32U", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Uto32F", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Uto64F", + argLen: 1, + generic: true, + }, + { + name: "Cvt32Fto64U", + argLen: 1, + generic: true, + }, + { + name: "Cvt64Fto64U", + argLen: 1, + generic: true, + }, + { + name: "Select0", + argLen: 1, + zeroWidth: true, + generic: true, + }, + { + name: "Select1", + argLen: 1, + zeroWidth: true, + generic: true, + }, + { + name: "MakeTuple", + argLen: 2, + generic: true, + }, + { + name: "SelectN", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "SelectNAddr", + auxType: auxInt64, + argLen: 1, + generic: true, + }, + { + name: "MakeResult", + argLen: -1, + generic: true, + }, + { + name: "AtomicLoad8", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoad32", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoad64", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoadPtr", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoadAcq32", + argLen: 2, + generic: true, + }, + { + name: "AtomicLoadAcq64", + argLen: 2, + generic: true, + }, + { + name: "AtomicStore8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStorePtrNoWB", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStoreRel32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStoreRel64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd64", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap32", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap64", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwapRel32", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr8", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr32", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd64value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd32value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd8value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr64value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr32value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr8value", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore8Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore32Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicStore64Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd32Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAdd64Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange8Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange32Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicExchange64Variant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap32Variant", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicCompareAndSwap64Variant", + argLen: 4, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd64valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr64valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd32valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr32valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicAnd8valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "AtomicOr8valueVariant", + argLen: 3, + hasSideEffects: true, + generic: true, + }, + { + name: "PubBarrier", + argLen: 1, + hasSideEffects: true, + generic: true, + }, + { + name: "Clobber", + auxType: auxSymOff, + argLen: 0, + symEffect: SymNone, + generic: true, + }, + { + name: "ClobberReg", + argLen: 0, + generic: true, + }, + { + name: "PrefetchCache", + argLen: 2, + hasSideEffects: true, + generic: true, + }, + { + name: "PrefetchCacheStreamed", + argLen: 2, + hasSideEffects: true, + generic: true, + }, + { + name: "Add32x4", + argLen: 2, + generic: true, + }, + { + name: "ZeroSIMD", + argLen: 0, + generic: true, + }, + { + name: "AddFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "ApproximateReciprocalFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "ApproximateReciprocalOfSqrtFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "DivFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "EqualFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "FusedMultiplyAdd132Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd213Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd231Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub132Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub213Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub231Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub132Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub213Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub231Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd132Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd213Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd231Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd132Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd213Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd231Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub132Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub213Float32x16", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub231Float32x16", + argLen: 3, + generic: true, + }, + { + name: "GreaterFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "IsNanFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "LessFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedApproximateReciprocalFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedApproximateReciprocalOfSqrtFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedDivFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd132Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd213Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd231Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub132Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub213Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub231Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub132Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub213Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub231Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd132Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd213Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd231Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd132Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd213Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd231Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub132Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub213Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub231Float32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedGreaterFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedIsNanFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedLessFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulByPowOf2Float32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedNotEqualFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSqrtFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubFloat32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorFloat32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulByPowOf2Float32x16", + argLen: 2, + generic: true, + }, + { + name: "NotEqualFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SqrtFloat32x16", + argLen: 1, + generic: true, + }, + { + name: "SubFloat32x16", + argLen: 2, + generic: true, + }, + { + name: "XorFloat32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSubFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "AndFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "ApproximateReciprocalFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "ApproximateReciprocalOfSqrtFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "DivFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "EqualFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "FloorFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "FusedMultiplyAdd132Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd213Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd231Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub132Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub213Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub231Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub132Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub213Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub231Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd132Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd213Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd231Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd132Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd213Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd231Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub132Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub213Float32x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub231Float32x4", + argLen: 3, + generic: true, + }, + { + name: "GreaterFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "IsNanFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "LessFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedApproximateReciprocalFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedApproximateReciprocalOfSqrtFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedDivFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd132Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd213Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd231Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub132Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub213Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub231Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub132Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub213Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub231Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd132Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd213Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd231Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd132Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd213Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd231Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub132Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub213Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub231Float32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedGreaterFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedIsNanFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedLessFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulByPowOf2Float32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedNotEqualFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSqrtFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubFloat32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorFloat32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulByPowOf2Float32x4", + argLen: 2, + generic: true, + }, + { + name: "NotEqualFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "RoundFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "SqrtFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "SubFloat32x4", + argLen: 2, + generic: true, + }, + { + name: "TruncFloat32x4", + argLen: 1, + generic: true, + }, + { + name: "XorFloat32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSubFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "AndFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "ApproximateReciprocalFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "ApproximateReciprocalOfSqrtFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "DivFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "EqualFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "FloorFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "FusedMultiplyAdd132Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd213Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd231Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub132Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub213Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub231Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub132Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub213Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub231Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd132Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd213Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd231Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd132Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd213Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd231Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub132Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub213Float32x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub231Float32x8", + argLen: 3, + generic: true, + }, + { + name: "GreaterFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "IsNanFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "LessFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedApproximateReciprocalFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedApproximateReciprocalOfSqrtFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedDivFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd132Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd213Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd231Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub132Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub213Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub231Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub132Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub213Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub231Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd132Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd213Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd231Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd132Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd213Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd231Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub132Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub213Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub231Float32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedGreaterFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedIsNanFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedLessFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulByPowOf2Float32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedNotEqualFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSqrtFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubFloat32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorFloat32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulByPowOf2Float32x8", + argLen: 2, + generic: true, + }, + { + name: "NotEqualFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "RoundFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "SqrtFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "SubFloat32x8", + argLen: 2, + generic: true, + }, + { + name: "TruncFloat32x8", + argLen: 1, + generic: true, + }, + { + name: "XorFloat32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSubFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "AndFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "ApproximateReciprocalFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "ApproximateReciprocalOfSqrtFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "DivFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "DotProdBroadcastFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "FloorFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "FusedMultiplyAdd132Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd213Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd231Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub132Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub213Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub231Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub132Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub213Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub231Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd132Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd213Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd231Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd132Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd213Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd231Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub132Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub213Float64x2", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub231Float64x2", + argLen: 3, + generic: true, + }, + { + name: "GreaterFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "IsNanFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "LessFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedApproximateReciprocalFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedApproximateReciprocalOfSqrtFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedDivFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd132Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd213Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd231Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub132Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub213Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub231Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub132Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub213Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub231Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd132Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd213Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd231Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd132Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd213Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd231Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub132Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub213Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub231Float64x2", + argLen: 4, + generic: true, + }, + { + name: "MaskedGreaterFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedIsNanFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedLessFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulByPowOf2Float64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedNotEqualFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSqrtFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubFloat64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorFloat64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulByPowOf2Float64x2", + argLen: 2, + generic: true, + }, + { + name: "NotEqualFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "RoundFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "SqrtFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "SubFloat64x2", + argLen: 2, + generic: true, + }, + { + name: "TruncFloat64x2", + argLen: 1, + generic: true, + }, + { + name: "XorFloat64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddSubFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "AndFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "ApproximateReciprocalFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "ApproximateReciprocalOfSqrtFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "CeilFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "DivFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "EqualFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "FloorFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "FusedMultiplyAdd132Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd213Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd231Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub132Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub213Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub231Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub132Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub213Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub231Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd132Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd213Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd231Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd132Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd213Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd231Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub132Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub213Float64x4", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub231Float64x4", + argLen: 3, + generic: true, + }, + { + name: "GreaterFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "IsNanFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "LessFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedApproximateReciprocalFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedApproximateReciprocalOfSqrtFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedDivFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd132Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd213Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd231Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub132Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub213Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub231Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub132Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub213Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub231Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd132Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd213Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd231Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd132Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd213Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd231Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub132Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub213Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub231Float64x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedGreaterFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedIsNanFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedLessFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulByPowOf2Float64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedNotEqualFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSqrtFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubFloat64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorFloat64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulByPowOf2Float64x4", + argLen: 2, + generic: true, + }, + { + name: "NotEqualFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "RoundFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "SqrtFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "SubFloat64x4", + argLen: 2, + generic: true, + }, + { + name: "TruncFloat64x4", + argLen: 1, + generic: true, + }, + { + name: "XorFloat64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "ApproximateReciprocalFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "ApproximateReciprocalOfSqrtFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "DivFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "EqualFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "FusedMultiplyAdd132Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd213Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAdd231Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub132Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub213Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplyAddSub231Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub132Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub213Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySub231Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd132Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd213Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedMultiplySubAdd231Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd132Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd213Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplyAdd231Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub132Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub213Float64x8", + argLen: 3, + generic: true, + }, + { + name: "FusedNegativeMultiplySub231Float64x8", + argLen: 3, + generic: true, + }, + { + name: "GreaterFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "IsNanFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "LessFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedApproximateReciprocalFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedApproximateReciprocalOfSqrtFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedDivFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd132Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd213Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAdd231Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub132Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub213Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplyAddSub231Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub132Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub213Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySub231Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd132Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd213Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedMultiplySubAdd231Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd132Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd213Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplyAdd231Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub132Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub213Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedFusedNegativeMultiplySub231Float64x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedGreaterFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedIsNanFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedLessFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulByPowOf2Float64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedNotEqualFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSqrtFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubFloat64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorFloat64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulByPowOf2Float64x8", + argLen: 2, + generic: true, + }, + { + name: "NotEqualFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SqrtFloat64x8", + argLen: 1, + generic: true, + }, + { + name: "SubFloat64x8", + argLen: 2, + generic: true, + }, + { + name: "XorFloat64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt16x16", + argLen: 1, + generic: true, + }, + { + name: "AddInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt16x16", + argLen: 2, + generic: true, + }, + { + name: "EqualInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt16x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt16x16", + argLen: 2, + generic: true, + }, + { + name: "LessInt16x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt16x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt16x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulHighInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPairDotProdInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedPopCountInt16x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddInt16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubInt16x16", + argLen: 3, + generic: true, + }, + { + name: "MaxInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairDotProdInt16x16", + argLen: 2, + generic: true, + }, + { + name: "PairwiseAddInt16x16", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubInt16x16", + argLen: 2, + generic: true, + }, + { + name: "PopCountInt16x16", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedPairwiseAddInt16x16", + argLen: 2, + generic: true, + }, + { + name: "SaturatedPairwiseSubInt16x16", + argLen: 2, + generic: true, + }, + { + name: "SaturatedSubInt16x16", + argLen: 2, + generic: true, + }, + { + name: "SignInt16x16", + argLen: 2, + generic: true, + }, + { + name: "SubInt16x16", + argLen: 2, + generic: true, + }, + { + name: "XorInt16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt16x32", + argLen: 1, + generic: true, + }, + { + name: "AddInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt16x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt16x32", + argLen: 2, + generic: true, + }, + { + name: "LessInt16x32", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt16x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt16x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulHighInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPairDotProdInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedPopCountInt16x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddInt16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubInt16x32", + argLen: 3, + generic: true, + }, + { + name: "MaxInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairDotProdInt16x32", + argLen: 2, + generic: true, + }, + { + name: "PopCountInt16x32", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddInt16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubInt16x32", + argLen: 2, + generic: true, + }, + { + name: "SubInt16x32", + argLen: 2, + generic: true, + }, + { + name: "AbsoluteInt16x8", + argLen: 1, + generic: true, + }, + { + name: "AddInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt16x8", + argLen: 2, + generic: true, + }, + { + name: "EqualInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt16x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt16x8", + argLen: 2, + generic: true, + }, + { + name: "LessInt16x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt16x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt16x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulHighInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPairDotProdInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedPopCountInt16x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddInt16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubInt16x8", + argLen: 3, + generic: true, + }, + { + name: "MaxInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairDotProdInt16x8", + argLen: 2, + generic: true, + }, + { + name: "PairwiseAddInt16x8", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubInt16x8", + argLen: 2, + generic: true, + }, + { + name: "PopCountInt16x8", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedPairwiseAddInt16x8", + argLen: 2, + generic: true, + }, + { + name: "SaturatedPairwiseSubInt16x8", + argLen: 2, + generic: true, + }, + { + name: "SaturatedSubInt16x8", + argLen: 2, + generic: true, + }, + { + name: "SignInt16x8", + argLen: 2, + generic: true, + }, + { + name: "SubInt16x8", + argLen: 2, + generic: true, + }, + { + name: "XorInt16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt32x16", + argLen: 1, + generic: true, + }, + { + name: "AddInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt32x16", + argLen: 2, + generic: true, + }, + { + name: "EqualInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt32x16", + argLen: 2, + generic: true, + }, + { + name: "LessInt32x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotInt32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPairDotProdAccumulateInt32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedPopCountInt32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedPairDotProdAccumulateInt32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedSubInt32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedXorInt32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairDotProdAccumulateInt32x16", + argLen: 3, + generic: true, + }, + { + name: "PopCountInt32x16", + argLen: 1, + generic: true, + }, + { + name: "SaturatedPairDotProdAccumulateInt32x16", + argLen: 3, + generic: true, + }, + { + name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x16", + argLen: 3, + generic: true, + }, + { + name: "SubInt32x16", + argLen: 2, + generic: true, + }, + { + name: "UnsignedSignedQuadDotProdAccumulateInt32x16", + argLen: 3, + generic: true, + }, + { + name: "XorInt32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt32x4", + argLen: 1, + generic: true, + }, + { + name: "AddInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt32x4", + argLen: 2, + generic: true, + }, + { + name: "EqualInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt32x4", + argLen: 2, + generic: true, + }, + { + name: "LessInt32x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPairDotProdAccumulateInt32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedPopCountInt32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedPairDotProdAccumulateInt32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedSubInt32x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x4", + argLen: 4, + generic: true, + }, + { + name: "MaskedXorInt32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulEvenWidenInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairDotProdAccumulateInt32x4", + argLen: 3, + generic: true, + }, + { + name: "PairwiseAddInt32x4", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubInt32x4", + argLen: 2, + generic: true, + }, + { + name: "PopCountInt32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturatedPairDotProdAccumulateInt32x4", + argLen: 3, + generic: true, + }, + { + name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x4", + argLen: 3, + generic: true, + }, + { + name: "SignInt32x4", + argLen: 2, + generic: true, + }, + { + name: "SubInt32x4", + argLen: 2, + generic: true, + }, + { + name: "UnsignedSignedQuadDotProdAccumulateInt32x4", + argLen: 3, + generic: true, + }, + { + name: "XorInt32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt32x8", + argLen: 1, + generic: true, + }, + { + name: "AddInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt32x8", + argLen: 2, + generic: true, + }, + { + name: "EqualInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt32x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt32x8", + argLen: 2, + generic: true, + }, + { + name: "LessInt32x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotInt32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPairDotProdAccumulateInt32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedPopCountInt32x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedPairDotProdAccumulateInt32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedSubInt32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedUnsignedSignedQuadDotProdAccumulateInt32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedXorInt32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulEvenWidenInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairDotProdAccumulateInt32x8", + argLen: 3, + generic: true, + }, + { + name: "PairwiseAddInt32x8", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubInt32x8", + argLen: 2, + generic: true, + }, + { + name: "PopCountInt32x8", + argLen: 1, + generic: true, + }, + { + name: "SaturatedPairDotProdAccumulateInt32x8", + argLen: 3, + generic: true, + }, + { + name: "SaturatedUnsignedSignedQuadDotProdAccumulateInt32x8", + argLen: 3, + generic: true, + }, + { + name: "SignInt32x8", + argLen: 2, + generic: true, + }, + { + name: "SubInt32x8", + argLen: 2, + generic: true, + }, + { + name: "UnsignedSignedQuadDotProdAccumulateInt32x8", + argLen: 3, + generic: true, + }, + { + name: "XorInt32x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt64x2", + argLen: 1, + generic: true, + }, + { + name: "AddInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt64x2", + argLen: 2, + generic: true, + }, + { + name: "EqualInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt64x2", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt64x2", + argLen: 2, + generic: true, + }, + { + name: "LessInt64x2", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotInt64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulEvenWidenInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountInt64x2", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubInt64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorInt64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulEvenWidenInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountInt64x2", + argLen: 1, + generic: true, + }, + { + name: "SubInt64x2", + argLen: 2, + generic: true, + }, + { + name: "XorInt64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt64x4", + argLen: 1, + generic: true, + }, + { + name: "AddInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt64x4", + argLen: 2, + generic: true, + }, + { + name: "EqualInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt64x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt64x4", + argLen: 2, + generic: true, + }, + { + name: "LessInt64x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotInt64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulEvenWidenInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountInt64x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubInt64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorInt64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulEvenWidenInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountInt64x4", + argLen: 1, + generic: true, + }, + { + name: "SubInt64x4", + argLen: 2, + generic: true, + }, + { + name: "XorInt64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt64x8", + argLen: 1, + generic: true, + }, + { + name: "AddInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt64x8", + argLen: 2, + generic: true, + }, + { + name: "EqualInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt64x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt64x8", + argLen: 2, + generic: true, + }, + { + name: "LessInt64x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotInt64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulEvenWidenInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulLowInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountInt64x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedSubInt64x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorInt64x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulEvenWidenInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulLowInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountInt64x8", + argLen: 1, + generic: true, + }, + { + name: "SubInt64x8", + argLen: 2, + generic: true, + }, + { + name: "XorInt64x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt8x16", + argLen: 1, + generic: true, + }, + { + name: "AddInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt8x16", + argLen: 2, + generic: true, + }, + { + name: "EqualInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt8x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt8x16", + argLen: 2, + generic: true, + }, + { + name: "LessInt8x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt8x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt8x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualInt8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountInt8x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddInt8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubInt8x16", + argLen: 3, + generic: true, + }, + { + name: "MaxInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountInt8x16", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubInt8x16", + argLen: 2, + generic: true, + }, + { + name: "SignInt8x16", + argLen: 2, + generic: true, + }, + { + name: "SubInt8x16", + argLen: 2, + generic: true, + }, + { + name: "XorInt8x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt8x32", + argLen: 1, + generic: true, + }, + { + name: "AddInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotInt8x32", + argLen: 2, + generic: true, + }, + { + name: "EqualInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt8x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt8x32", + argLen: 2, + generic: true, + }, + { + name: "LessInt8x32", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt8x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt8x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualInt8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt8x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt8x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt8x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt8x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountInt8x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddInt8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubInt8x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubInt8x32", + argLen: 3, + generic: true, + }, + { + name: "MaxInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountInt8x32", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubInt8x32", + argLen: 2, + generic: true, + }, + { + name: "SignInt8x32", + argLen: 2, + generic: true, + }, + { + name: "SubInt8x32", + argLen: 2, + generic: true, + }, + { + name: "XorInt8x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AbsoluteInt8x64", + argLen: 1, + generic: true, + }, + { + name: "AddInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterInt8x64", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualInt8x64", + argLen: 2, + generic: true, + }, + { + name: "LessInt8x64", + argLen: 2, + generic: true, + }, + { + name: "LessEqualInt8x64", + argLen: 2, + generic: true, + }, + { + name: "MaskedAbsoluteInt8x64", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddInt8x64", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualInt8x64", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterInt8x64", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualInt8x64", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessInt8x64", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualInt8x64", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxInt8x64", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinInt8x64", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualInt8x64", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountInt8x64", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddInt8x64", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubInt8x64", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubInt8x64", + argLen: 3, + generic: true, + }, + { + name: "MaxInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountInt8x64", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddInt8x64", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubInt8x64", + argLen: 2, + generic: true, + }, + { + name: "SubInt8x64", + argLen: 2, + generic: true, + }, + { + name: "AddUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotUint16x16", + argLen: 2, + generic: true, + }, + { + name: "AverageUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint16x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint16x16", + argLen: 2, + generic: true, + }, + { + name: "LessUint16x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint16x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAverageUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulHighUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountUint16x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddUint16x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedPairDotProdUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubUint16x16", + argLen: 3, + generic: true, + }, + { + name: "MaxUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddUint16x16", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubUint16x16", + argLen: 2, + generic: true, + }, + { + name: "PopCountUint16x16", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubUint16x16", + argLen: 2, + generic: true, + }, + { + name: "SaturatedUnsignedSignedPairDotProdUint16x16", + argLen: 2, + generic: true, + }, + { + name: "SubUint16x16", + argLen: 2, + generic: true, + }, + { + name: "XorUint16x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AverageUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint16x32", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint16x32", + argLen: 2, + generic: true, + }, + { + name: "LessUint16x32", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint16x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAverageUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulHighUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountUint16x32", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddUint16x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedPairDotProdUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubUint16x32", + argLen: 3, + generic: true, + }, + { + name: "MaxUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountUint16x32", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddUint16x32", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubUint16x32", + argLen: 2, + generic: true, + }, + { + name: "SaturatedUnsignedSignedPairDotProdUint16x32", + argLen: 2, + generic: true, + }, + { + name: "SubUint16x32", + argLen: 2, + generic: true, + }, + { + name: "AddUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotUint16x8", + argLen: 2, + generic: true, + }, + { + name: "AverageUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "EqualUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint16x8", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint16x8", + argLen: 2, + generic: true, + }, + { + name: "LessUint16x8", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint16x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAverageUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulHighUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountUint16x8", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedAddUint16x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedPairDotProdUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedSubUint16x8", + argLen: 3, + generic: true, + }, + { + name: "MaxUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulHighUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddUint16x8", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubUint16x8", + argLen: 2, + generic: true, + }, + { + name: "PopCountUint16x8", + argLen: 1, + generic: true, + }, + { + name: "SaturatedAddUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "SaturatedSubUint16x8", + argLen: 2, + generic: true, + }, + { + name: "SaturatedUnsignedSignedPairDotProdUint16x8", + argLen: 2, + generic: true, + }, + { + name: "SubUint16x8", + argLen: 2, + generic: true, + }, + { + name: "XorUint16x8", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotUint32x16", + argLen: 2, + generic: true, + }, + { + name: "EqualUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint32x16", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint32x16", + argLen: 2, + generic: true, + }, + { + name: "LessUint32x16", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotUint32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualUint32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessUint32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualUint32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountUint32x16", + argLen: 2, + generic: true, + }, + { + name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedSubUint32x16", + argLen: 3, + generic: true, + }, + { + name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x16", + argLen: 4, + generic: true, + }, + { + name: "MaskedXorUint32x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountUint32x16", + argLen: 1, + generic: true, + }, + { + name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x16", + argLen: 3, + generic: true, + }, + { + name: "SubUint32x16", + argLen: 2, + generic: true, + }, + { + name: "UnsignedSignedQuadDotProdAccumulateUint32x16", + argLen: 3, + generic: true, + }, + { + name: "XorUint32x16", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotUint32x4", + argLen: 2, + generic: true, + }, + { + name: "EqualUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint32x4", + argLen: 2, + generic: true, + }, + { + name: "GreaterEqualUint32x4", + argLen: 2, + generic: true, + }, + { + name: "LessUint32x4", + argLen: 2, + generic: true, + }, + { + name: "LessEqualUint32x4", + argLen: 2, + generic: true, + }, + { + name: "MaskedAddUint32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndUint32x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotUint32x4", + argLen: 3, + generic: true, }, { - name: "F32Abs", - argLen: 1, - asm: wasm.AF32Abs, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, + name: "MaskedEqualUint32x4", + argLen: 3, + commutative: true, + generic: true, }, { - name: "F32Copysign", - argLen: 2, - asm: wasm.AF32Copysign, - reg: regInfo{ - inputs: []inputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - {1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - outputs: []outputInfo{ - {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 - }, - }, + name: "MaskedGreaterUint32x4", + argLen: 3, + generic: true, }, { - name: "F64Sqrt", - argLen: 1, - asm: wasm.AF64Sqrt, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedGreaterEqualUint32x4", + argLen: 3, + generic: true, }, { - name: "F64Trunc", - argLen: 1, - asm: wasm.AF64Trunc, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedLessUint32x4", + argLen: 3, + generic: true, }, { - name: "F64Ceil", - argLen: 1, - asm: wasm.AF64Ceil, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedLessEqualUint32x4", + argLen: 3, + generic: true, }, { - name: "F64Floor", - argLen: 1, - asm: wasm.AF64Floor, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedMaxUint32x4", + argLen: 3, + commutative: true, + generic: true, }, { - name: "F64Nearest", - argLen: 1, - asm: wasm.AF64Nearest, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedMinUint32x4", + argLen: 3, + commutative: true, + generic: true, }, { - name: "F64Abs", - argLen: 1, - asm: wasm.AF64Abs, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedNotEqualUint32x4", + argLen: 3, + commutative: true, + generic: true, }, { - name: "F64Copysign", - argLen: 2, - asm: wasm.AF64Copysign, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - {1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - outputs: []outputInfo{ - {0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 - }, - }, + name: "MaskedOrUint32x4", + argLen: 3, + commutative: true, + generic: true, }, { - name: "I64Ctz", - argLen: 1, - asm: wasm.AI64Ctz, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - }, - outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - }, - }, + name: "MaskedPopCountUint32x4", + argLen: 2, + generic: true, }, { - name: "I64Clz", - argLen: 1, - asm: wasm.AI64Clz, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - }, - outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - }, - }, + name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", + argLen: 4, + generic: true, }, { - name: "I32Rotl", - argLen: 2, - asm: wasm.AI32Rotl, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - }, - outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - }, - }, + name: "MaskedSubUint32x4", + argLen: 3, + generic: true, }, { - name: "I64Rotl", - argLen: 2, - asm: wasm.AI64Rotl, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - {1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - }, - outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - }, - }, + name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x4", + argLen: 4, + generic: true, }, { - name: "I64Popcnt", - argLen: 1, - asm: wasm.AI64Popcnt, - reg: regInfo{ - inputs: []inputInfo{ - {0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP - }, - outputs: []outputInfo{ - {0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 - }, - }, + name: "MaskedXorUint32x4", + argLen: 3, + commutative: true, + generic: true, }, - { - name: "Add8", + name: "MaxUint32x4", argLen: 2, commutative: true, generic: true, }, { - name: "Add16", + name: "MinUint32x4", argLen: 2, commutative: true, generic: true, }, { - name: "Add32", + name: "MulEvenWidenUint32x4", argLen: 2, commutative: true, generic: true, }, { - name: "Add64", + name: "NotEqualUint32x4", argLen: 2, commutative: true, generic: true, }, { - name: "AddPtr", + name: "OrUint32x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PairwiseAddUint32x4", argLen: 2, generic: true, }, { - name: "Add32F", + name: "PairwiseSubUint32x4", + argLen: 2, + generic: true, + }, + { + name: "PopCountUint32x4", + argLen: 1, + generic: true, + }, + { + name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x4", + argLen: 3, + generic: true, + }, + { + name: "SubUint32x4", + argLen: 2, + generic: true, + }, + { + name: "UnsignedSignedQuadDotProdAccumulateUint32x4", + argLen: 3, + generic: true, + }, + { + name: "XorUint32x4", argLen: 2, commutative: true, generic: true, }, { - name: "Add64F", + name: "AddUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Sub8", - argLen: 2, - generic: true, + name: "AndUint32x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Sub16", + name: "AndNotUint32x8", argLen: 2, generic: true, }, { - name: "Sub32", - argLen: 2, - generic: true, + name: "EqualUint32x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Sub64", + name: "GreaterUint32x8", argLen: 2, generic: true, }, { - name: "SubPtr", + name: "GreaterEqualUint32x8", argLen: 2, generic: true, }, { - name: "Sub32F", + name: "LessUint32x8", argLen: 2, generic: true, }, { - name: "Sub64F", + name: "LessEqualUint32x8", argLen: 2, generic: true, }, { - name: "Mul8", - argLen: 2, + name: "MaskedAddUint32x8", + argLen: 3, commutative: true, generic: true, }, { - name: "Mul16", - argLen: 2, + name: "MaskedAndUint32x8", + argLen: 3, commutative: true, generic: true, }, { - name: "Mul32", - argLen: 2, + name: "MaskedAndNotUint32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualUint32x8", + argLen: 3, commutative: true, generic: true, }, { - name: "Mul64", - argLen: 2, + name: "MaskedGreaterUint32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualUint32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessUint32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualUint32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxUint32x8", + argLen: 3, commutative: true, generic: true, }, { - name: "Mul32F", - argLen: 2, + name: "MaskedMinUint32x8", + argLen: 3, commutative: true, generic: true, }, { - name: "Mul64F", - argLen: 2, + name: "MaskedNotEqualUint32x8", + argLen: 3, commutative: true, generic: true, }, { - name: "Div32F", + name: "MaskedOrUint32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountUint32x8", argLen: 2, generic: true, }, { - name: "Div64F", - argLen: 2, + name: "MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", + argLen: 4, generic: true, }, { - name: "Hmul32", + name: "MaskedSubUint32x8", + argLen: 3, + generic: true, + }, + { + name: "MaskedUnsignedSignedQuadDotProdAccumulateUint32x8", + argLen: 4, + generic: true, + }, + { + name: "MaskedXorUint32x8", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Hmul32u", + name: "MinUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Hmul64", + name: "MulEvenWidenUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Hmul64u", + name: "NotEqualUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Mul32uhilo", + name: "OrUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Mul64uhilo", + name: "PairwiseAddUint32x8", + argLen: 2, + generic: true, + }, + { + name: "PairwiseSubUint32x8", + argLen: 2, + generic: true, + }, + { + name: "PopCountUint32x8", + argLen: 1, + generic: true, + }, + { + name: "SaturatedUnsignedSignedQuadDotProdAccumulateUint32x8", + argLen: 3, + generic: true, + }, + { + name: "SubUint32x8", + argLen: 2, + generic: true, + }, + { + name: "UnsignedSignedQuadDotProdAccumulateUint32x8", + argLen: 3, + generic: true, + }, + { + name: "XorUint32x8", argLen: 2, commutative: true, generic: true, }, { - name: "Mul32uover", + name: "AddUint64x2", argLen: 2, commutative: true, generic: true, }, { - name: "Mul64uover", + name: "AndUint64x2", argLen: 2, commutative: true, generic: true, }, { - name: "Avg32u", + name: "AndNotUint64x2", argLen: 2, generic: true, }, { - name: "Avg64u", + name: "EqualUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint64x2", argLen: 2, generic: true, }, { - name: "Div8", + name: "GreaterEqualUint64x2", argLen: 2, generic: true, }, { - name: "Div8u", + name: "LessUint64x2", argLen: 2, generic: true, }, { - name: "Div16", - auxType: auxBool, + name: "LessEqualUint64x2", argLen: 2, generic: true, }, { - name: "Div16u", - argLen: 2, + name: "MaskedAddUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotUint64x2", + argLen: 3, generic: true, }, { - name: "Div32", - auxType: auxBool, - argLen: 2, + name: "MaskedEqualUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint64x2", + argLen: 3, generic: true, }, { - name: "Div32u", - argLen: 2, + name: "MaskedGreaterEqualUint64x2", + argLen: 3, generic: true, }, { - name: "Div64", - auxType: auxBool, - argLen: 2, + name: "MaskedLessUint64x2", + argLen: 3, generic: true, }, { - name: "Div64u", + name: "MaskedLessEqualUint64x2", + argLen: 3, + generic: true, + }, + { + name: "MaskedMaxUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMinUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedMulEvenWidenUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedNotEqualUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedOrUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedPopCountUint64x2", argLen: 2, generic: true, }, { - name: "Div128u", + name: "MaskedSubUint64x2", argLen: 3, generic: true, }, { - name: "Mod8", - argLen: 2, + name: "MaskedXorUint64x2", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaxUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MinUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "MulEvenWidenUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "NotEqualUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "OrUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "PopCountUint64x2", + argLen: 1, generic: true, }, { - name: "Mod8u", + name: "SubUint64x2", argLen: 2, generic: true, }, { - name: "Mod16", - auxType: auxBool, + name: "XorUint64x2", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AddUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "AndNotUint64x4", argLen: 2, generic: true, }, { - name: "Mod16u", + name: "EqualUint64x4", + argLen: 2, + commutative: true, + generic: true, + }, + { + name: "GreaterUint64x4", argLen: 2, generic: true, }, { - name: "Mod32", - auxType: auxBool, + name: "GreaterEqualUint64x4", argLen: 2, generic: true, }, { - name: "Mod32u", + name: "LessUint64x4", argLen: 2, generic: true, }, { - name: "Mod64", - auxType: auxBool, + name: "LessEqualUint64x4", argLen: 2, generic: true, }, { - name: "Mod64u", - argLen: 2, + name: "MaskedAddUint64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndUint64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAndNotUint64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedEqualUint64x4", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedGreaterEqualUint64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessUint64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedLessEqualUint64x4", + argLen: 3, generic: true, }, { - name: "And8", - argLen: 2, + name: "MaskedMaxUint64x4", + argLen: 3, commutative: true, generic: true, }, { - name: "And16", - argLen: 2, + name: "MaskedMinUint64x4", + argLen: 3, commutative: true, generic: true, }, { - name: "And32", - argLen: 2, + name: "MaskedMulEvenWidenUint64x4", + argLen: 3, commutative: true, generic: true, }, { - name: "And64", - argLen: 2, + name: "MaskedNotEqualUint64x4", + argLen: 3, commutative: true, generic: true, }, { - name: "Or8", - argLen: 2, + name: "MaskedOrUint64x4", + argLen: 3, commutative: true, generic: true, }, { - name: "Or16", - argLen: 2, - commutative: true, - generic: true, + name: "MaskedPopCountUint64x4", + argLen: 2, + generic: true, }, { - name: "Or32", - argLen: 2, + name: "MaskedSubUint64x4", + argLen: 3, + generic: true, + }, + { + name: "MaskedXorUint64x4", + argLen: 3, commutative: true, generic: true, }, { - name: "Or64", + name: "MaxUint64x4", argLen: 2, commutative: true, generic: true, }, { - name: "Xor8", + name: "MinUint64x4", argLen: 2, commutative: true, generic: true, }, { - name: "Xor16", + name: "MulEvenWidenUint64x4", argLen: 2, commutative: true, generic: true, }, { - name: "Xor32", + name: "NotEqualUint64x4", argLen: 2, commutative: true, generic: true, }, { - name: "Xor64", + name: "OrUint64x4", argLen: 2, commutative: true, generic: true, }, { - name: "Lsh8x8", - auxType: auxBool, - argLen: 2, + name: "PopCountUint64x4", + argLen: 1, generic: true, }, { - name: "Lsh8x16", - auxType: auxBool, + name: "SubUint64x4", argLen: 2, generic: true, }, { - name: "Lsh8x32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "XorUint64x4", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Lsh8x64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "AddUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Lsh16x8", - auxType: auxBool, - argLen: 2, - generic: true, + name: "AndUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Lsh16x16", - auxType: auxBool, + name: "AndNotUint64x8", argLen: 2, generic: true, }, { - name: "Lsh16x32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "EqualUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Lsh16x64", - auxType: auxBool, + name: "GreaterUint64x8", argLen: 2, generic: true, }, { - name: "Lsh32x8", - auxType: auxBool, + name: "GreaterEqualUint64x8", argLen: 2, generic: true, }, { - name: "Lsh32x16", - auxType: auxBool, + name: "LessUint64x8", argLen: 2, generic: true, }, { - name: "Lsh32x32", - auxType: auxBool, + name: "LessEqualUint64x8", argLen: 2, generic: true, }, { - name: "Lsh32x64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedAddUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Lsh64x8", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedAndUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Lsh64x16", - auxType: auxBool, - argLen: 2, + name: "MaskedAndNotUint64x8", + argLen: 3, generic: true, }, { - name: "Lsh64x32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedEqualUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Lsh64x64", - auxType: auxBool, - argLen: 2, + name: "MaskedGreaterUint64x8", + argLen: 3, generic: true, }, { - name: "Rsh8x8", - auxType: auxBool, - argLen: 2, + name: "MaskedGreaterEqualUint64x8", + argLen: 3, generic: true, }, { - name: "Rsh8x16", - auxType: auxBool, - argLen: 2, + name: "MaskedLessUint64x8", + argLen: 3, generic: true, }, { - name: "Rsh8x32", - auxType: auxBool, - argLen: 2, + name: "MaskedLessEqualUint64x8", + argLen: 3, generic: true, }, { - name: "Rsh8x64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedMaxUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Rsh16x8", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedMinUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Rsh16x16", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedMulEvenWidenUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Rsh16x32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedNotEqualUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Rsh16x64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedOrUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Rsh32x8", - auxType: auxBool, + name: "MaskedPopCountUint64x8", argLen: 2, generic: true, }, { - name: "Rsh32x16", - auxType: auxBool, - argLen: 2, + name: "MaskedSubUint64x8", + argLen: 3, generic: true, }, { - name: "Rsh32x32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaskedXorUint64x8", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Rsh32x64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MaxUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh64x8", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MinUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh64x16", - auxType: auxBool, - argLen: 2, - generic: true, + name: "MulEvenWidenUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh64x32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "NotEqualUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh64x64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "OrUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh8Ux8", - auxType: auxBool, - argLen: 2, + name: "PopCountUint64x8", + argLen: 1, generic: true, }, { - name: "Rsh8Ux16", - auxType: auxBool, + name: "SubUint64x8", argLen: 2, generic: true, }, { - name: "Rsh8Ux32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "XorUint64x8", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh8Ux64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "AddUint8x16", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh16Ux8", - auxType: auxBool, - argLen: 2, - generic: true, + name: "AndUint8x16", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh16Ux16", - auxType: auxBool, + name: "AndNotUint8x16", argLen: 2, generic: true, }, { - name: "Rsh16Ux32", - auxType: auxBool, - argLen: 2, - generic: true, + name: "AverageUint8x16", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh16Ux64", - auxType: auxBool, - argLen: 2, - generic: true, + name: "EqualUint8x16", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Rsh32Ux8", - auxType: auxBool, + name: "GreaterUint8x16", argLen: 2, generic: true, }, { - name: "Rsh32Ux16", - auxType: auxBool, + name: "GreaterEqualUint8x16", argLen: 2, generic: true, }, { - name: "Rsh32Ux32", - auxType: auxBool, + name: "LessUint8x16", argLen: 2, generic: true, }, { - name: "Rsh32Ux64", - auxType: auxBool, + name: "LessEqualUint8x16", argLen: 2, generic: true, }, { - name: "Rsh64Ux8", - auxType: auxBool, - argLen: 2, + name: "MaskedAddUint8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedAverageUint8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedEqualUint8x16", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedGreaterUint8x16", + argLen: 3, generic: true, }, { - name: "Rsh64Ux16", - auxType: auxBool, - argLen: 2, + name: "MaskedGreaterEqualUint8x16", + argLen: 3, generic: true, }, { - name: "Rsh64Ux32", - auxType: auxBool, - argLen: 2, + name: "MaskedLessUint8x16", + argLen: 3, generic: true, }, { - name: "Rsh64Ux64", - auxType: auxBool, - argLen: 2, + name: "MaskedLessEqualUint8x16", + argLen: 3, generic: true, }, { - name: "Eq8", - argLen: 2, + name: "MaskedMaxUint8x16", + argLen: 3, commutative: true, generic: true, }, { - name: "Eq16", - argLen: 2, + name: "MaskedMinUint8x16", + argLen: 3, commutative: true, generic: true, }, { - name: "Eq32", - argLen: 2, + name: "MaskedNotEqualUint8x16", + argLen: 3, commutative: true, generic: true, }, { - name: "Eq64", - argLen: 2, - commutative: true, - generic: true, + name: "MaskedPopCountUint8x16", + argLen: 2, + generic: true, }, { - name: "EqPtr", - argLen: 2, + name: "MaskedSaturatedAddUint8x16", + argLen: 3, commutative: true, generic: true, }, { - name: "EqInter", - argLen: 2, + name: "MaskedSaturatedSubUint8x16", + argLen: 3, generic: true, }, { - name: "EqSlice", - argLen: 2, + name: "MaskedSubUint8x16", + argLen: 3, generic: true, }, { - name: "Eq32F", + name: "MaxUint8x16", argLen: 2, commutative: true, generic: true, }, { - name: "Eq64F", + name: "MinUint8x16", argLen: 2, commutative: true, generic: true, }, { - name: "Neq8", + name: "NotEqualUint8x16", argLen: 2, commutative: true, generic: true, }, { - name: "Neq16", + name: "OrUint8x16", argLen: 2, commutative: true, generic: true, }, { - name: "Neq32", - argLen: 2, - commutative: true, - generic: true, + name: "PopCountUint8x16", + argLen: 1, + generic: true, }, { - name: "Neq64", + name: "SaturatedAddUint8x16", argLen: 2, commutative: true, generic: true, }, { - name: "NeqPtr", - argLen: 2, - commutative: true, - generic: true, + name: "SaturatedSubUint8x16", + argLen: 2, + generic: true, }, { - name: "NeqInter", + name: "SaturatedUnsignedSignedPairDotProdUint8x16", argLen: 2, generic: true, }, { - name: "NeqSlice", + name: "SubUint8x16", argLen: 2, generic: true, }, { - name: "Neq32F", + name: "XorUint8x16", argLen: 2, commutative: true, generic: true, }, { - name: "Neq64F", + name: "AddUint8x32", argLen: 2, commutative: true, generic: true, }, { - name: "Less8", - argLen: 2, - generic: true, + name: "AndUint8x32", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Less8U", + name: "AndNotUint8x32", argLen: 2, generic: true, }, { - name: "Less16", - argLen: 2, - generic: true, + name: "AverageUint8x32", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Less16U", - argLen: 2, - generic: true, + name: "EqualUint8x32", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Less32", + name: "GreaterUint8x32", argLen: 2, generic: true, }, { - name: "Less32U", + name: "GreaterEqualUint8x32", argLen: 2, generic: true, }, { - name: "Less64", + name: "LessUint8x32", argLen: 2, generic: true, }, { - name: "Less64U", + name: "LessEqualUint8x32", argLen: 2, generic: true, }, { - name: "Less32F", - argLen: 2, - generic: true, + name: "MaskedAddUint8x32", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Less64F", - argLen: 2, - generic: true, + name: "MaskedAverageUint8x32", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Leq8", - argLen: 2, - generic: true, + name: "MaskedEqualUint8x32", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Leq8U", - argLen: 2, + name: "MaskedGreaterUint8x32", + argLen: 3, generic: true, }, { - name: "Leq16", - argLen: 2, + name: "MaskedGreaterEqualUint8x32", + argLen: 3, generic: true, }, { - name: "Leq16U", - argLen: 2, + name: "MaskedLessUint8x32", + argLen: 3, generic: true, }, { - name: "Leq32", - argLen: 2, + name: "MaskedLessEqualUint8x32", + argLen: 3, generic: true, }, { - name: "Leq32U", - argLen: 2, - generic: true, + name: "MaskedMaxUint8x32", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Leq64", - argLen: 2, - generic: true, + name: "MaskedMinUint8x32", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Leq64U", - argLen: 2, - generic: true, + name: "MaskedNotEqualUint8x32", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Leq32F", + name: "MaskedPopCountUint8x32", argLen: 2, generic: true, }, { - name: "Leq64F", - argLen: 2, + name: "MaskedSaturatedAddUint8x32", + argLen: 3, + commutative: true, + generic: true, + }, + { + name: "MaskedSaturatedSubUint8x32", + argLen: 3, generic: true, }, { - name: "CondSelect", + name: "MaskedSubUint8x32", argLen: 3, generic: true, }, { - name: "AndB", + name: "MaxUint8x32", argLen: 2, commutative: true, generic: true, }, { - name: "OrB", + name: "MinUint8x32", argLen: 2, commutative: true, generic: true, }, { - name: "EqB", + name: "NotEqualUint8x32", argLen: 2, commutative: true, generic: true, }, { - name: "NeqB", + name: "OrUint8x32", argLen: 2, commutative: true, generic: true, }, { - name: "Not", - argLen: 1, - generic: true, - }, - { - name: "Neg8", - argLen: 1, - generic: true, - }, - { - name: "Neg16", - argLen: 1, - generic: true, - }, - { - name: "Neg32", - argLen: 1, - generic: true, - }, - { - name: "Neg64", - argLen: 1, - generic: true, - }, - { - name: "Neg32F", + name: "PopCountUint8x32", argLen: 1, generic: true, }, { - name: "Neg64F", - argLen: 1, - generic: true, + name: "SaturatedAddUint8x32", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Com8", - argLen: 1, + name: "SaturatedSubUint8x32", + argLen: 2, generic: true, }, { - name: "Com16", - argLen: 1, + name: "SaturatedUnsignedSignedPairDotProdUint8x32", + argLen: 2, generic: true, }, { - name: "Com32", - argLen: 1, + name: "SubUint8x32", + argLen: 2, generic: true, }, { - name: "Com64", - argLen: 1, - generic: true, + name: "XorUint8x32", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Ctz8", - argLen: 1, - generic: true, + name: "AddUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Ctz16", - argLen: 1, - generic: true, + name: "AverageUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Ctz32", - argLen: 1, - generic: true, + name: "EqualUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "Ctz64", - argLen: 1, + name: "GreaterUint8x64", + argLen: 2, generic: true, }, { - name: "Ctz64On32", + name: "GreaterEqualUint8x64", argLen: 2, generic: true, }, { - name: "Ctz8NonZero", - argLen: 1, + name: "LessUint8x64", + argLen: 2, generic: true, }, { - name: "Ctz16NonZero", - argLen: 1, + name: "LessEqualUint8x64", + argLen: 2, generic: true, }, { - name: "Ctz32NonZero", - argLen: 1, - generic: true, + name: "MaskedAddUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Ctz64NonZero", - argLen: 1, - generic: true, + name: "MaskedAverageUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "BitLen8", - argLen: 1, - generic: true, + name: "MaskedEqualUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "BitLen16", - argLen: 1, + name: "MaskedGreaterUint8x64", + argLen: 3, generic: true, }, { - name: "BitLen32", - argLen: 1, + name: "MaskedGreaterEqualUint8x64", + argLen: 3, generic: true, }, { - name: "BitLen64", - argLen: 1, + name: "MaskedLessUint8x64", + argLen: 3, generic: true, }, { - name: "Bswap16", - argLen: 1, + name: "MaskedLessEqualUint8x64", + argLen: 3, generic: true, }, { - name: "Bswap32", - argLen: 1, - generic: true, + name: "MaskedMaxUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "Bswap64", - argLen: 1, - generic: true, + name: "MaskedMinUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "BitRev8", - argLen: 1, - generic: true, + name: "MaskedNotEqualUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "BitRev16", - argLen: 1, + name: "MaskedPopCountUint8x64", + argLen: 2, generic: true, }, { - name: "BitRev32", - argLen: 1, - generic: true, + name: "MaskedSaturatedAddUint8x64", + argLen: 3, + commutative: true, + generic: true, }, { - name: "BitRev64", - argLen: 1, + name: "MaskedSaturatedSubUint8x64", + argLen: 3, generic: true, }, { - name: "PopCount8", - argLen: 1, + name: "MaskedSubUint8x64", + argLen: 3, generic: true, }, { - name: "PopCount16", - argLen: 1, - generic: true, + name: "MaxUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "PopCount32", - argLen: 1, - generic: true, + name: "MinUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "PopCount64", - argLen: 1, - generic: true, + name: "NotEqualUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "RotateLeft64", - argLen: 2, + name: "PopCountUint8x64", + argLen: 1, generic: true, }, { - name: "RotateLeft32", - argLen: 2, - generic: true, + name: "SaturatedAddUint8x64", + argLen: 2, + commutative: true, + generic: true, }, { - name: "RotateLeft16", + name: "SaturatedSubUint8x64", argLen: 2, generic: true, }, { - name: "RotateLeft8", + name: "SubUint8x64", argLen: 2, generic: true, }, { - name: "Sqrt", + name: "CeilSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Sqrt32", + name: "CeilWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Floor", + name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Ceil", + name: "DiffWithCeilWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Trunc", + name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Round", + name: "DiffWithFloorWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "RoundToEven", + name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Abs", + name: "DiffWithRoundWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Copysign", - argLen: 2, + name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Min64", - argLen: 2, + name: "DiffWithTruncWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Max64", - argLen: 2, + name: "FloorSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Min64u", - argLen: 2, + name: "FloorWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Max64u", + name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Min64F", + name: "MaskedCeilWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Min32F", + name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Max64F", + name: "MaskedDiffWithCeilWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Max32F", + name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "FMA", - argLen: 3, - generic: true, - }, - { - name: "Phi", - argLen: -1, - zeroWidth: true, - generic: true, - }, - { - name: "Copy", - argLen: 1, - generic: true, - }, - { - name: "Convert", - argLen: 2, - resultInArg0: true, - zeroWidth: true, - generic: true, - }, - { - name: "ConstBool", - auxType: auxBool, - argLen: 0, - generic: true, - }, - { - name: "ConstString", - auxType: auxString, - argLen: 0, - generic: true, - }, - { - name: "ConstNil", - argLen: 0, + name: "MaskedDiffWithFloorWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Const8", + name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16", auxType: auxInt8, - argLen: 0, + argLen: 2, generic: true, }, { - name: "Const16", - auxType: auxInt16, - argLen: 0, + name: "MaskedDiffWithRoundWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Const32", - auxType: auxInt32, - argLen: 0, + name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Const64", - auxType: auxInt64, - argLen: 0, + name: "MaskedDiffWithTruncWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Const32F", - auxType: auxFloat32, - argLen: 0, + name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Const64F", - auxType: auxFloat64, - argLen: 0, + name: "MaskedFloorWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ConstInterface", - argLen: 0, + name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ConstSlice", - argLen: 0, + name: "MaskedRoundWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "InitMem", - argLen: 0, - zeroWidth: true, - generic: true, - }, - { - name: "Arg", - auxType: auxSymOff, - argLen: 0, - zeroWidth: true, - symEffect: SymRead, - generic: true, - }, - { - name: "ArgIntReg", - auxType: auxNameOffsetInt8, - argLen: 0, - zeroWidth: true, - generic: true, - }, - { - name: "ArgFloatReg", - auxType: auxNameOffsetInt8, - argLen: 0, - zeroWidth: true, - generic: true, - }, - { - name: "Addr", - auxType: auxSym, - argLen: 1, - symEffect: SymAddr, - generic: true, - }, - { - name: "LocalAddr", - auxType: auxSym, - argLen: 2, - symEffect: SymAddr, - generic: true, - }, - { - name: "SP", - argLen: 0, - zeroWidth: true, - fixedReg: true, - generic: true, - }, - { - name: "SB", - argLen: 0, - zeroWidth: true, - fixedReg: true, - generic: true, - }, - { - name: "SPanchored", - argLen: 2, - zeroWidth: true, - generic: true, - }, - { - name: "Load", + name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Dereference", + name: "MaskedTruncWithPrecisionFloat32x16", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Store", - auxType: auxTyp, - argLen: 3, + name: "RoundSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Move", - auxType: auxTypSize, - argLen: 3, + name: "RoundWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Zero", - auxType: auxTypSize, - argLen: 2, + name: "TruncSuppressExceptionWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "StoreWB", - auxType: auxTyp, - argLen: 3, + name: "TruncWithPrecisionFloat32x16", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "MoveWB", - auxType: auxTypSize, - argLen: 3, + name: "CeilSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "ZeroWB", - auxType: auxTypSize, - argLen: 2, + name: "CeilWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "WBend", + name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "WB", - auxType: auxInt64, + name: "DiffWithCeilWithPrecisionFloat32x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "HasCPUFeature", - auxType: auxSym, - argLen: 0, - symEffect: SymNone, - generic: true, - }, - { - name: "PanicBounds", - auxType: auxInt64, - argLen: 3, - call: true, + name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "PanicExtend", - auxType: auxInt64, - argLen: 4, - call: true, + name: "DiffWithFloorWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "ClosureCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "StaticCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "DiffWithRoundWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "InterCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "TailCall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "DiffWithTruncWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "ClosureLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "FloorSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "StaticLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "FloorWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "InterLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "TailLECall", - auxType: auxCallOff, - argLen: -1, - call: true, + name: "MaskedCeilWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SignExt8to16", - argLen: 1, + name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SignExt8to32", - argLen: 1, + name: "MaskedDiffWithCeilWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SignExt8to64", - argLen: 1, + name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SignExt16to32", - argLen: 1, + name: "MaskedDiffWithFloorWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SignExt16to64", - argLen: 1, + name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SignExt32to64", - argLen: 1, + name: "MaskedDiffWithRoundWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ZeroExt8to16", - argLen: 1, + name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ZeroExt8to32", - argLen: 1, + name: "MaskedDiffWithTruncWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ZeroExt8to64", - argLen: 1, + name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ZeroExt16to32", - argLen: 1, + name: "MaskedFloorWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ZeroExt16to64", - argLen: 1, + name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ZeroExt32to64", - argLen: 1, + name: "MaskedRoundWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Trunc16to8", - argLen: 1, + name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Trunc32to8", - argLen: 1, + name: "MaskedTruncWithPrecisionFloat32x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Trunc32to16", + name: "RoundSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Trunc64to8", + name: "RoundWithPrecisionFloat32x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Trunc64to16", + name: "TruncSuppressExceptionWithPrecisionFloat32x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Trunc64to32", + name: "TruncWithPrecisionFloat32x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32to32F", + name: "CeilSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32to64F", + name: "CeilWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64to32F", + name: "DiffWithCeilSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64to64F", + name: "DiffWithCeilWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto32", + name: "DiffWithFloorSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto64", + name: "DiffWithFloorWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto32", + name: "DiffWithRoundSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto64", + name: "DiffWithRoundWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto64F", + name: "DiffWithTruncSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto32F", + name: "DiffWithTruncWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "CvtBoolToUint8", + name: "FloorSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Round32F", + name: "FloorWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Round64F", - argLen: 1, + name: "MaskedCeilSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "IsNonNil", - argLen: 1, + name: "MaskedCeilWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "IsInBounds", + name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "IsSliceInBounds", + name: "MaskedDiffWithCeilWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "NilCheck", - argLen: 2, - nilCheck: true, - generic: true, + name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "GetG", - argLen: 1, - zeroWidth: true, - generic: true, + name: "MaskedDiffWithFloorWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "GetClosurePtr", - argLen: 0, + name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "GetCallerPC", - argLen: 0, + name: "MaskedDiffWithRoundWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "GetCallerSP", - argLen: 1, + name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "PtrIndex", + name: "MaskedDiffWithTruncWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "OffPtr", - auxType: auxInt64, - argLen: 1, + name: "MaskedFloorSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SliceMake", - argLen: 3, + name: "MaskedFloorWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SlicePtr", - argLen: 1, + name: "MaskedRoundSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SliceLen", - argLen: 1, + name: "MaskedRoundWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SliceCap", - argLen: 1, + name: "MaskedTruncSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "SlicePtrUnchecked", - argLen: 1, + name: "MaskedTruncWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "ComplexMake", - argLen: 2, + name: "RoundSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "ComplexReal", + name: "RoundWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "ComplexImag", + name: "TruncSuppressExceptionWithPrecisionFloat32x8", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "StringMake", - argLen: 2, + name: "TruncWithPrecisionFloat32x8", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "StringPtr", + name: "CeilSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "StringLen", + name: "CeilWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "IMake", - argLen: 2, + name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "ITab", + name: "DiffWithCeilWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "IData", + name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "StructMake", - argLen: -1, + name: "DiffWithFloorWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "StructSelect", - auxType: auxInt64, + name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "ArrayMake0", - argLen: 0, + name: "DiffWithRoundWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "ArrayMake1", + name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "ArraySelect", - auxType: auxInt64, + name: "DiffWithTruncWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "StoreReg", + name: "FloorSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "LoadReg", + name: "FloorWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "FwdRef", - auxType: auxSym, - argLen: 0, - symEffect: SymNone, - generic: true, + name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "Unknown", - argLen: 0, + name: "MaskedCeilWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "VarDef", - auxType: auxSym, - argLen: 1, - zeroWidth: true, - symEffect: SymNone, - generic: true, + name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "VarLive", - auxType: auxSym, - argLen: 1, - zeroWidth: true, - symEffect: SymRead, - generic: true, + name: "MaskedDiffWithCeilWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "KeepAlive", - argLen: 2, - zeroWidth: true, - generic: true, + name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "InlMark", - auxType: auxInt32, - argLen: 1, + name: "MaskedDiffWithFloorWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Int64Make", + name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Int64Hi", - argLen: 1, + name: "MaskedDiffWithRoundWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Int64Lo", - argLen: 1, + name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Add32carry", - argLen: 2, - commutative: true, - generic: true, + name: "MaskedDiffWithTruncWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "Add32withcarry", - argLen: 3, - commutative: true, - generic: true, + name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "Sub32carry", + name: "MaskedFloorWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "Sub32withcarry", - argLen: 3, + name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Add64carry", - argLen: 3, - commutative: true, - generic: true, + name: "MaskedRoundWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "Sub64borrow", - argLen: 3, + name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Signmask", - argLen: 1, + name: "MaskedTruncWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "Zeromask", + name: "RoundSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Slicemask", + name: "RoundWithPrecisionFloat64x2", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "SpectreIndex", - argLen: 2, + name: "TruncSuppressExceptionWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "SpectreSliceIndex", - argLen: 2, + name: "TruncWithPrecisionFloat64x2", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "Cvt32Uto32F", + name: "CeilSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32Uto64F", + name: "CeilWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto32U", + name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto32U", + name: "DiffWithCeilWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Uto32F", + name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Uto64F", + name: "DiffWithFloorWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt32Fto64U", + name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Cvt64Fto64U", + name: "DiffWithRoundWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "Select0", - argLen: 1, - zeroWidth: true, - generic: true, - }, - { - name: "Select1", - argLen: 1, - zeroWidth: true, - generic: true, + name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "MakeTuple", - argLen: 2, + name: "DiffWithTruncWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "SelectN", - auxType: auxInt64, + name: "FloorSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "SelectNAddr", - auxType: auxInt64, + name: "FloorWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 1, generic: true, }, { - name: "MakeResult", - argLen: -1, + name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, generic: true, }, { - name: "AtomicLoad8", + name: "MaskedCeilWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "AtomicLoad32", + name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "AtomicLoad64", + name: "MaskedDiffWithCeilWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "AtomicLoadPtr", + name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "AtomicLoadAcq32", + name: "MaskedDiffWithFloorWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "AtomicLoadAcq64", + name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, argLen: 2, generic: true, }, { - name: "AtomicStore8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithRoundWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStore32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStore64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithTruncWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStorePtrNoWB", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStoreRel32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedFloorWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStoreRel64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedRoundWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedTruncWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAdd32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "RoundSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAdd64", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "RoundWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicCompareAndSwap32", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "TruncSuppressExceptionWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicCompareAndSwap64", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "TruncWithPrecisionFloat64x4", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicCompareAndSwapRel32", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "CeilSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "CeilWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr8", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithCeilSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithCeilWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr32", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithFloorSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd64value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithFloorWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd32value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithRoundSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicAnd8value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithRoundWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr64value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithTruncSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr32value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "DiffWithTruncWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicOr8value", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "FloorSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicStore8Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "FloorWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "AtomicStore32Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedCeilSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicStore64Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedCeilWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAdd32Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAdd64Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithCeilWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange8Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange32Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithFloorWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicExchange64Variant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicCompareAndSwap32Variant", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithRoundWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicCompareAndSwap64Variant", - argLen: 4, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAnd64valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedDiffWithTruncWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicOr64valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedFloorSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAnd32valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedFloorWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicOr32valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedRoundSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicAnd8valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedRoundWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "AtomicOr8valueVariant", - argLen: 3, - hasSideEffects: true, - generic: true, + name: "MaskedTruncSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "PubBarrier", - argLen: 1, - hasSideEffects: true, - generic: true, + name: "MaskedTruncWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 2, + generic: true, }, { - name: "Clobber", - auxType: auxSymOff, - argLen: 0, - symEffect: SymNone, - generic: true, + name: "RoundSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "ClobberReg", - argLen: 0, + name: "RoundWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, generic: true, }, { - name: "PrefetchCache", - argLen: 2, - hasSideEffects: true, - generic: true, + name: "TruncSuppressExceptionWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, { - name: "PrefetchCacheStreamed", - argLen: 2, - hasSideEffects: true, - generic: true, + name: "TruncWithPrecisionFloat64x8", + auxType: auxInt8, + argLen: 1, + generic: true, }, } @@ -42747,13 +67799,21 @@ var registersAMD64 = [...]Register{ {29, x86.REG_X13, "X13"}, {30, x86.REG_X14, "X14"}, {31, x86.REG_X15, "X15"}, - {32, 0, "SB"}, + {32, x86.REG_K0, "K0"}, + {33, x86.REG_K1, "K1"}, + {34, x86.REG_K2, "K2"}, + {35, x86.REG_K3, "K3"}, + {36, x86.REG_K4, "K4"}, + {37, x86.REG_K5, "K5"}, + {38, x86.REG_K6, "K6"}, + {39, x86.REG_K7, "K7"}, + {40, 0, "SB"}, } var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11} var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30} var gpRegMaskAMD64 = regMask(49135) var fpRegMaskAMD64 = regMask(2147418112) -var specialRegMaskAMD64 = regMask(2147483648) +var specialRegMaskAMD64 = regMask(1093069176832) var framepointerRegAMD64 = int8(5) var linkRegAMD64 = int8(-1) var registersARM = [...]Register{ diff --git a/src/cmd/compile/internal/ssa/rewriteAMD64.go b/src/cmd/compile/internal/ssa/rewriteAMD64.go index 3d7af5f365a116..e9bafe2a1b400f 100644 --- a/src/cmd/compile/internal/ssa/rewriteAMD64.go +++ b/src/cmd/compile/internal/ssa/rewriteAMD64.go @@ -501,6 +501,30 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64TESTW(v) case OpAMD64TESTWconst: return rewriteValueAMD64_OpAMD64TESTWconst(v) + case OpAMD64VPMOVVec16x16ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec16x16ToM(v) + case OpAMD64VPMOVVec16x32ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec16x32ToM(v) + case OpAMD64VPMOVVec16x8ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec16x8ToM(v) + case OpAMD64VPMOVVec32x16ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec32x16ToM(v) + case OpAMD64VPMOVVec32x4ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec32x4ToM(v) + case OpAMD64VPMOVVec32x8ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec32x8ToM(v) + case OpAMD64VPMOVVec64x2ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec64x2ToM(v) + case OpAMD64VPMOVVec64x4ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec64x4ToM(v) + case OpAMD64VPMOVVec64x8ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec64x8ToM(v) + case OpAMD64VPMOVVec8x16ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec8x16ToM(v) + case OpAMD64VPMOVVec8x32ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v) + case OpAMD64VPMOVVec8x64ToM: + return rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v) case OpAMD64XADDLlock: return rewriteValueAMD64_OpAMD64XADDLlock(v) case OpAMD64XADDQlock: @@ -529,6 +553,42 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAMD64XORQload(v) case OpAMD64XORQmodify: return rewriteValueAMD64_OpAMD64XORQmodify(v) + case OpAbsoluteInt16x16: + v.Op = OpAMD64VPABSW256 + return true + case OpAbsoluteInt16x32: + v.Op = OpAMD64VPABSW512 + return true + case OpAbsoluteInt16x8: + v.Op = OpAMD64VPABSW128 + return true + case OpAbsoluteInt32x16: + v.Op = OpAMD64VPABSD512 + return true + case OpAbsoluteInt32x4: + v.Op = OpAMD64VPABSD128 + return true + case OpAbsoluteInt32x8: + v.Op = OpAMD64VPABSD256 + return true + case OpAbsoluteInt64x2: + v.Op = OpAMD64VPABSQ128 + return true + case OpAbsoluteInt64x4: + v.Op = OpAMD64VPABSQ256 + return true + case OpAbsoluteInt64x8: + v.Op = OpAMD64VPABSQ512 + return true + case OpAbsoluteInt8x16: + v.Op = OpAMD64VPABSB128 + return true + case OpAbsoluteInt8x32: + v.Op = OpAMD64VPABSB256 + return true + case OpAbsoluteInt8x64: + v.Op = OpAMD64VPABSB512 + return true case OpAdd16: v.Op = OpAMD64ADDL return true @@ -547,9 +607,111 @@ func rewriteValueAMD64(v *Value) bool { case OpAdd8: v.Op = OpAMD64ADDL return true + case OpAddFloat32x16: + v.Op = OpAMD64VADDPS512 + return true + case OpAddFloat32x4: + v.Op = OpAMD64VADDPS128 + return true + case OpAddFloat32x8: + v.Op = OpAMD64VADDPS256 + return true + case OpAddFloat64x2: + v.Op = OpAMD64VADDPD128 + return true + case OpAddFloat64x4: + v.Op = OpAMD64VADDPD256 + return true + case OpAddFloat64x8: + v.Op = OpAMD64VADDPD512 + return true + case OpAddInt16x16: + v.Op = OpAMD64VPADDW256 + return true + case OpAddInt16x32: + v.Op = OpAMD64VPADDW512 + return true + case OpAddInt16x8: + v.Op = OpAMD64VPADDW128 + return true + case OpAddInt32x16: + v.Op = OpAMD64VPADDD512 + return true + case OpAddInt32x4: + v.Op = OpAMD64VPADDD128 + return true + case OpAddInt32x8: + v.Op = OpAMD64VPADDD256 + return true + case OpAddInt64x2: + v.Op = OpAMD64VPADDQ128 + return true + case OpAddInt64x4: + v.Op = OpAMD64VPADDQ256 + return true + case OpAddInt64x8: + v.Op = OpAMD64VPADDQ512 + return true + case OpAddInt8x16: + v.Op = OpAMD64VPADDB128 + return true + case OpAddInt8x32: + v.Op = OpAMD64VPADDB256 + return true + case OpAddInt8x64: + v.Op = OpAMD64VPADDB512 + return true case OpAddPtr: v.Op = OpAMD64ADDQ return true + case OpAddSubFloat32x4: + v.Op = OpAMD64VADDSUBPS128 + return true + case OpAddSubFloat32x8: + v.Op = OpAMD64VADDSUBPS256 + return true + case OpAddSubFloat64x2: + v.Op = OpAMD64VADDSUBPD128 + return true + case OpAddSubFloat64x4: + v.Op = OpAMD64VADDSUBPD256 + return true + case OpAddUint16x16: + v.Op = OpAMD64VPADDW256 + return true + case OpAddUint16x32: + v.Op = OpAMD64VPADDW512 + return true + case OpAddUint16x8: + v.Op = OpAMD64VPADDW128 + return true + case OpAddUint32x16: + v.Op = OpAMD64VPADDD512 + return true + case OpAddUint32x4: + v.Op = OpAMD64VPADDD128 + return true + case OpAddUint32x8: + v.Op = OpAMD64VPADDD256 + return true + case OpAddUint64x2: + v.Op = OpAMD64VPADDQ128 + return true + case OpAddUint64x4: + v.Op = OpAMD64VPADDQ256 + return true + case OpAddUint64x8: + v.Op = OpAMD64VPADDQ512 + return true + case OpAddUint8x16: + v.Op = OpAMD64VPADDB128 + return true + case OpAddUint8x32: + v.Op = OpAMD64VPADDB256 + return true + case OpAddUint8x64: + v.Op = OpAMD64VPADDB512 + return true case OpAddr: return rewriteValueAMD64_OpAddr(v) case OpAnd16: @@ -567,6 +729,198 @@ func rewriteValueAMD64(v *Value) bool { case OpAndB: v.Op = OpAMD64ANDL return true + case OpAndFloat32x16: + v.Op = OpAMD64VANDPS512 + return true + case OpAndFloat32x4: + v.Op = OpAMD64VANDPS128 + return true + case OpAndFloat32x8: + v.Op = OpAMD64VANDPS256 + return true + case OpAndFloat64x2: + v.Op = OpAMD64VANDPD128 + return true + case OpAndFloat64x4: + v.Op = OpAMD64VANDPD256 + return true + case OpAndFloat64x8: + v.Op = OpAMD64VANDPD512 + return true + case OpAndInt16x16: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt16x8: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt32x16: + v.Op = OpAMD64VPANDD512 + return true + case OpAndInt32x4: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt32x8: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt64x2: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt64x4: + v.Op = OpAMD64VPAND256 + return true + case OpAndInt64x8: + v.Op = OpAMD64VPANDQ512 + return true + case OpAndInt8x16: + v.Op = OpAMD64VPAND128 + return true + case OpAndInt8x32: + v.Op = OpAMD64VPAND256 + return true + case OpAndNotFloat32x16: + v.Op = OpAMD64VANDNPS512 + return true + case OpAndNotFloat32x4: + v.Op = OpAMD64VANDNPS128 + return true + case OpAndNotFloat32x8: + v.Op = OpAMD64VANDNPS256 + return true + case OpAndNotFloat64x2: + v.Op = OpAMD64VANDNPD128 + return true + case OpAndNotFloat64x4: + v.Op = OpAMD64VANDNPD256 + return true + case OpAndNotFloat64x8: + v.Op = OpAMD64VANDNPD512 + return true + case OpAndNotInt16x16: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt16x8: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt32x16: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotInt32x4: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt32x8: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt64x2: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt64x4: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotInt64x8: + v.Op = OpAMD64VPANDNQ512 + return true + case OpAndNotInt8x16: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotInt8x32: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint16x16: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint16x8: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint32x16: + v.Op = OpAMD64VPANDND512 + return true + case OpAndNotUint32x4: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint32x8: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint64x2: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint64x4: + v.Op = OpAMD64VPANDN256 + return true + case OpAndNotUint64x8: + v.Op = OpAMD64VPANDNQ512 + return true + case OpAndNotUint8x16: + v.Op = OpAMD64VPANDN128 + return true + case OpAndNotUint8x32: + v.Op = OpAMD64VPANDN256 + return true + case OpAndUint16x16: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint16x8: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint32x16: + v.Op = OpAMD64VPANDD512 + return true + case OpAndUint32x4: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint32x8: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint64x2: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint64x4: + v.Op = OpAMD64VPAND256 + return true + case OpAndUint64x8: + v.Op = OpAMD64VPANDQ512 + return true + case OpAndUint8x16: + v.Op = OpAMD64VPAND128 + return true + case OpAndUint8x32: + v.Op = OpAMD64VPAND256 + return true + case OpApproximateReciprocalFloat32x16: + v.Op = OpAMD64VRCP14PS512 + return true + case OpApproximateReciprocalFloat32x4: + v.Op = OpAMD64VRCP14PS128 + return true + case OpApproximateReciprocalFloat32x8: + v.Op = OpAMD64VRCP14PS256 + return true + case OpApproximateReciprocalFloat64x2: + v.Op = OpAMD64VRCP14PD128 + return true + case OpApproximateReciprocalFloat64x4: + v.Op = OpAMD64VRCP14PD256 + return true + case OpApproximateReciprocalFloat64x8: + v.Op = OpAMD64VRCP14PD512 + return true + case OpApproximateReciprocalOfSqrtFloat32x16: + v.Op = OpAMD64VRSQRT14PS512 + return true + case OpApproximateReciprocalOfSqrtFloat32x4: + v.Op = OpAMD64VRSQRTPS128 + return true + case OpApproximateReciprocalOfSqrtFloat32x8: + v.Op = OpAMD64VRSQRTPS256 + return true + case OpApproximateReciprocalOfSqrtFloat64x2: + v.Op = OpAMD64VRSQRT14PD128 + return true + case OpApproximateReciprocalOfSqrtFloat64x4: + v.Op = OpAMD64VRSQRT14PD256 + return true + case OpApproximateReciprocalOfSqrtFloat64x8: + v.Op = OpAMD64VRSQRT14PD512 + return true case OpAtomicAdd32: return rewriteValueAMD64_OpAtomicAdd32(v) case OpAtomicAdd64: @@ -613,6 +967,24 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpAtomicStore8(v) case OpAtomicStorePtrNoWB: return rewriteValueAMD64_OpAtomicStorePtrNoWB(v) + case OpAverageUint16x16: + v.Op = OpAMD64VPAVGW256 + return true + case OpAverageUint16x32: + v.Op = OpAMD64VPAVGW512 + return true + case OpAverageUint16x8: + v.Op = OpAMD64VPAVGW128 + return true + case OpAverageUint8x16: + v.Op = OpAMD64VPAVGB128 + return true + case OpAverageUint8x32: + v.Op = OpAMD64VPAVGB256 + return true + case OpAverageUint8x64: + v.Op = OpAMD64VPAVGB512 + return true case OpAvg64u: v.Op = OpAMD64AVGQU return true @@ -634,6 +1006,38 @@ func rewriteValueAMD64(v *Value) bool { return true case OpCeil: return rewriteValueAMD64_OpCeil(v) + case OpCeilFloat32x4: + return rewriteValueAMD64_OpCeilFloat32x4(v) + case OpCeilFloat32x8: + return rewriteValueAMD64_OpCeilFloat32x8(v) + case OpCeilFloat64x2: + return rewriteValueAMD64_OpCeilFloat64x2(v) + case OpCeilFloat64x4: + return rewriteValueAMD64_OpCeilFloat64x4(v) + case OpCeilSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat32x16(v) + case OpCeilSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat32x4(v) + case OpCeilSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat32x8(v) + case OpCeilSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat64x2(v) + case OpCeilSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat64x4(v) + case OpCeilSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat64x8(v) + case OpCeilWithPrecisionFloat32x16: + return rewriteValueAMD64_OpCeilWithPrecisionFloat32x16(v) + case OpCeilWithPrecisionFloat32x4: + return rewriteValueAMD64_OpCeilWithPrecisionFloat32x4(v) + case OpCeilWithPrecisionFloat32x8: + return rewriteValueAMD64_OpCeilWithPrecisionFloat32x8(v) + case OpCeilWithPrecisionFloat64x2: + return rewriteValueAMD64_OpCeilWithPrecisionFloat64x2(v) + case OpCeilWithPrecisionFloat64x4: + return rewriteValueAMD64_OpCeilWithPrecisionFloat64x4(v) + case OpCeilWithPrecisionFloat64x8: + return rewriteValueAMD64_OpCeilWithPrecisionFloat64x8(v) case OpClosureCall: v.Op = OpAMD64CALLclosure return true @@ -720,6 +1124,102 @@ func rewriteValueAMD64(v *Value) bool { case OpCvtBoolToUint8: v.Op = OpCopy return true + case OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x16(v) + case OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x4(v) + case OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x8(v) + case OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x2(v) + case OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x4(v) + case OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x8(v) + case OpDiffWithCeilWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x16(v) + case OpDiffWithCeilWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x4(v) + case OpDiffWithCeilWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x8(v) + case OpDiffWithCeilWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x2(v) + case OpDiffWithCeilWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x4(v) + case OpDiffWithCeilWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x8(v) + case OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x16(v) + case OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x4(v) + case OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x8(v) + case OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x2(v) + case OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x4(v) + case OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x8(v) + case OpDiffWithFloorWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x16(v) + case OpDiffWithFloorWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x4(v) + case OpDiffWithFloorWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x8(v) + case OpDiffWithFloorWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x2(v) + case OpDiffWithFloorWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x4(v) + case OpDiffWithFloorWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x8(v) + case OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x16(v) + case OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x4(v) + case OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x8(v) + case OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x2(v) + case OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x4(v) + case OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x8(v) + case OpDiffWithRoundWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x16(v) + case OpDiffWithRoundWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x4(v) + case OpDiffWithRoundWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x8(v) + case OpDiffWithRoundWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x2(v) + case OpDiffWithRoundWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x4(v) + case OpDiffWithRoundWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x8(v) + case OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x16(v) + case OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x4(v) + case OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x8(v) + case OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x2(v) + case OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x4(v) + case OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x8(v) + case OpDiffWithTruncWithPrecisionFloat32x16: + return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x16(v) + case OpDiffWithTruncWithPrecisionFloat32x4: + return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x4(v) + case OpDiffWithTruncWithPrecisionFloat32x8: + return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x8(v) + case OpDiffWithTruncWithPrecisionFloat64x2: + return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x2(v) + case OpDiffWithTruncWithPrecisionFloat64x4: + return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x4(v) + case OpDiffWithTruncWithPrecisionFloat64x8: + return rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x8(v) case OpDiv128u: v.Op = OpAMD64DIVQU2 return true @@ -745,6 +1245,26 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpDiv8(v) case OpDiv8u: return rewriteValueAMD64_OpDiv8u(v) + case OpDivFloat32x16: + v.Op = OpAMD64VDIVPS512 + return true + case OpDivFloat32x4: + v.Op = OpAMD64VDIVPS128 + return true + case OpDivFloat32x8: + v.Op = OpAMD64VDIVPS256 + return true + case OpDivFloat64x2: + v.Op = OpAMD64VDIVPD128 + return true + case OpDivFloat64x4: + v.Op = OpAMD64VDIVPD256 + return true + case OpDivFloat64x8: + v.Op = OpAMD64VDIVPD512 + return true + case OpDotProdBroadcastFloat64x2: + return rewriteValueAMD64_OpDotProdBroadcastFloat64x2(v) case OpEq16: return rewriteValueAMD64_OpEq16(v) case OpEq32: @@ -761,10 +1281,434 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpEqB(v) case OpEqPtr: return rewriteValueAMD64_OpEqPtr(v) + case OpEqualFloat32x16: + return rewriteValueAMD64_OpEqualFloat32x16(v) + case OpEqualFloat32x4: + return rewriteValueAMD64_OpEqualFloat32x4(v) + case OpEqualFloat32x8: + return rewriteValueAMD64_OpEqualFloat32x8(v) + case OpEqualFloat64x2: + return rewriteValueAMD64_OpEqualFloat64x2(v) + case OpEqualFloat64x4: + return rewriteValueAMD64_OpEqualFloat64x4(v) + case OpEqualFloat64x8: + return rewriteValueAMD64_OpEqualFloat64x8(v) + case OpEqualInt16x16: + v.Op = OpAMD64VPCMPEQW256 + return true + case OpEqualInt16x32: + return rewriteValueAMD64_OpEqualInt16x32(v) + case OpEqualInt16x8: + v.Op = OpAMD64VPCMPEQW128 + return true + case OpEqualInt32x16: + return rewriteValueAMD64_OpEqualInt32x16(v) + case OpEqualInt32x4: + v.Op = OpAMD64VPCMPEQD128 + return true + case OpEqualInt32x8: + v.Op = OpAMD64VPCMPEQD256 + return true + case OpEqualInt64x2: + v.Op = OpAMD64VPCMPEQQ128 + return true + case OpEqualInt64x4: + v.Op = OpAMD64VPCMPEQQ256 + return true + case OpEqualInt64x8: + return rewriteValueAMD64_OpEqualInt64x8(v) + case OpEqualInt8x16: + v.Op = OpAMD64VPCMPEQB128 + return true + case OpEqualInt8x32: + v.Op = OpAMD64VPCMPEQB256 + return true + case OpEqualInt8x64: + return rewriteValueAMD64_OpEqualInt8x64(v) + case OpEqualUint16x16: + return rewriteValueAMD64_OpEqualUint16x16(v) + case OpEqualUint16x32: + return rewriteValueAMD64_OpEqualUint16x32(v) + case OpEqualUint16x8: + return rewriteValueAMD64_OpEqualUint16x8(v) + case OpEqualUint32x16: + return rewriteValueAMD64_OpEqualUint32x16(v) + case OpEqualUint32x4: + return rewriteValueAMD64_OpEqualUint32x4(v) + case OpEqualUint32x8: + return rewriteValueAMD64_OpEqualUint32x8(v) + case OpEqualUint64x2: + return rewriteValueAMD64_OpEqualUint64x2(v) + case OpEqualUint64x4: + return rewriteValueAMD64_OpEqualUint64x4(v) + case OpEqualUint64x8: + return rewriteValueAMD64_OpEqualUint64x8(v) + case OpEqualUint8x16: + return rewriteValueAMD64_OpEqualUint8x16(v) + case OpEqualUint8x32: + return rewriteValueAMD64_OpEqualUint8x32(v) + case OpEqualUint8x64: + return rewriteValueAMD64_OpEqualUint8x64(v) case OpFMA: return rewriteValueAMD64_OpFMA(v) case OpFloor: return rewriteValueAMD64_OpFloor(v) + case OpFloorFloat32x4: + return rewriteValueAMD64_OpFloorFloat32x4(v) + case OpFloorFloat32x8: + return rewriteValueAMD64_OpFloorFloat32x8(v) + case OpFloorFloat64x2: + return rewriteValueAMD64_OpFloorFloat64x2(v) + case OpFloorFloat64x4: + return rewriteValueAMD64_OpFloorFloat64x4(v) + case OpFloorSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat32x16(v) + case OpFloorSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat32x4(v) + case OpFloorSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat32x8(v) + case OpFloorSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat64x2(v) + case OpFloorSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat64x4(v) + case OpFloorSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat64x8(v) + case OpFloorWithPrecisionFloat32x16: + return rewriteValueAMD64_OpFloorWithPrecisionFloat32x16(v) + case OpFloorWithPrecisionFloat32x4: + return rewriteValueAMD64_OpFloorWithPrecisionFloat32x4(v) + case OpFloorWithPrecisionFloat32x8: + return rewriteValueAMD64_OpFloorWithPrecisionFloat32x8(v) + case OpFloorWithPrecisionFloat64x2: + return rewriteValueAMD64_OpFloorWithPrecisionFloat64x2(v) + case OpFloorWithPrecisionFloat64x4: + return rewriteValueAMD64_OpFloorWithPrecisionFloat64x4(v) + case OpFloorWithPrecisionFloat64x8: + return rewriteValueAMD64_OpFloorWithPrecisionFloat64x8(v) + case OpFusedMultiplyAdd132Float32x16: + v.Op = OpAMD64VFMADD132PS512 + return true + case OpFusedMultiplyAdd132Float32x4: + v.Op = OpAMD64VFMADD132PS128 + return true + case OpFusedMultiplyAdd132Float32x8: + v.Op = OpAMD64VFMADD132PS256 + return true + case OpFusedMultiplyAdd132Float64x2: + v.Op = OpAMD64VFMADD132PD128 + return true + case OpFusedMultiplyAdd132Float64x4: + v.Op = OpAMD64VFMADD132PD256 + return true + case OpFusedMultiplyAdd132Float64x8: + v.Op = OpAMD64VFMADD132PD512 + return true + case OpFusedMultiplyAdd213Float32x16: + v.Op = OpAMD64VFMADD213PS512 + return true + case OpFusedMultiplyAdd213Float32x4: + v.Op = OpAMD64VFMADD213PS128 + return true + case OpFusedMultiplyAdd213Float32x8: + v.Op = OpAMD64VFMADD213PS256 + return true + case OpFusedMultiplyAdd213Float64x2: + v.Op = OpAMD64VFMADD213PD128 + return true + case OpFusedMultiplyAdd213Float64x4: + v.Op = OpAMD64VFMADD213PD256 + return true + case OpFusedMultiplyAdd213Float64x8: + v.Op = OpAMD64VFMADD213PD512 + return true + case OpFusedMultiplyAdd231Float32x16: + v.Op = OpAMD64VFMADD231PS512 + return true + case OpFusedMultiplyAdd231Float32x4: + v.Op = OpAMD64VFMADD231PS128 + return true + case OpFusedMultiplyAdd231Float32x8: + v.Op = OpAMD64VFMADD231PS256 + return true + case OpFusedMultiplyAdd231Float64x2: + v.Op = OpAMD64VFMADD231PD128 + return true + case OpFusedMultiplyAdd231Float64x4: + v.Op = OpAMD64VFMADD231PD256 + return true + case OpFusedMultiplyAdd231Float64x8: + v.Op = OpAMD64VFMADD231PD512 + return true + case OpFusedMultiplyAddSub132Float32x16: + v.Op = OpAMD64VFMADDSUB132PS512 + return true + case OpFusedMultiplyAddSub132Float32x4: + v.Op = OpAMD64VFMADDSUB132PS128 + return true + case OpFusedMultiplyAddSub132Float32x8: + v.Op = OpAMD64VFMADDSUB132PS256 + return true + case OpFusedMultiplyAddSub132Float64x2: + v.Op = OpAMD64VFMADDSUB132PD128 + return true + case OpFusedMultiplyAddSub132Float64x4: + v.Op = OpAMD64VFMADDSUB132PD256 + return true + case OpFusedMultiplyAddSub132Float64x8: + v.Op = OpAMD64VFMADDSUB132PD512 + return true + case OpFusedMultiplyAddSub213Float32x16: + v.Op = OpAMD64VFMADDSUB213PS512 + return true + case OpFusedMultiplyAddSub213Float32x4: + v.Op = OpAMD64VFMADDSUB213PS128 + return true + case OpFusedMultiplyAddSub213Float32x8: + v.Op = OpAMD64VFMADDSUB213PS256 + return true + case OpFusedMultiplyAddSub213Float64x2: + v.Op = OpAMD64VFMADDSUB213PD128 + return true + case OpFusedMultiplyAddSub213Float64x4: + v.Op = OpAMD64VFMADDSUB213PD256 + return true + case OpFusedMultiplyAddSub213Float64x8: + v.Op = OpAMD64VFMADDSUB213PD512 + return true + case OpFusedMultiplyAddSub231Float32x16: + v.Op = OpAMD64VFMADDSUB231PS512 + return true + case OpFusedMultiplyAddSub231Float32x4: + v.Op = OpAMD64VFMADDSUB231PS128 + return true + case OpFusedMultiplyAddSub231Float32x8: + v.Op = OpAMD64VFMADDSUB231PS256 + return true + case OpFusedMultiplyAddSub231Float64x2: + v.Op = OpAMD64VFMADDSUB231PD128 + return true + case OpFusedMultiplyAddSub231Float64x4: + v.Op = OpAMD64VFMADDSUB231PD256 + return true + case OpFusedMultiplyAddSub231Float64x8: + v.Op = OpAMD64VFMADDSUB231PD512 + return true + case OpFusedMultiplySub132Float32x16: + v.Op = OpAMD64VFMSUB132PS512 + return true + case OpFusedMultiplySub132Float32x4: + v.Op = OpAMD64VFMSUB132PS128 + return true + case OpFusedMultiplySub132Float32x8: + v.Op = OpAMD64VFMSUB132PS256 + return true + case OpFusedMultiplySub132Float64x2: + v.Op = OpAMD64VFMSUB132PD128 + return true + case OpFusedMultiplySub132Float64x4: + v.Op = OpAMD64VFMSUB132PD256 + return true + case OpFusedMultiplySub132Float64x8: + v.Op = OpAMD64VFMSUB132PD512 + return true + case OpFusedMultiplySub213Float32x16: + v.Op = OpAMD64VFMSUB213PS512 + return true + case OpFusedMultiplySub213Float32x4: + v.Op = OpAMD64VFMSUB213PS128 + return true + case OpFusedMultiplySub213Float32x8: + v.Op = OpAMD64VFMSUB213PS256 + return true + case OpFusedMultiplySub213Float64x2: + v.Op = OpAMD64VFMSUB213PD128 + return true + case OpFusedMultiplySub213Float64x4: + v.Op = OpAMD64VFMSUB213PD256 + return true + case OpFusedMultiplySub213Float64x8: + v.Op = OpAMD64VFMSUB213PD512 + return true + case OpFusedMultiplySub231Float32x16: + v.Op = OpAMD64VFMSUB231PS512 + return true + case OpFusedMultiplySub231Float32x4: + v.Op = OpAMD64VFMSUB231PS128 + return true + case OpFusedMultiplySub231Float32x8: + v.Op = OpAMD64VFMSUB231PS256 + return true + case OpFusedMultiplySub231Float64x2: + v.Op = OpAMD64VFMSUB231PD128 + return true + case OpFusedMultiplySub231Float64x4: + v.Op = OpAMD64VFMSUB231PD256 + return true + case OpFusedMultiplySub231Float64x8: + v.Op = OpAMD64VFMSUB231PD512 + return true + case OpFusedMultiplySubAdd132Float32x16: + v.Op = OpAMD64VFMSUBADD132PS512 + return true + case OpFusedMultiplySubAdd132Float32x4: + v.Op = OpAMD64VFMSUBADD132PS128 + return true + case OpFusedMultiplySubAdd132Float32x8: + v.Op = OpAMD64VFMSUBADD132PS256 + return true + case OpFusedMultiplySubAdd132Float64x2: + v.Op = OpAMD64VFMSUBADD132PD128 + return true + case OpFusedMultiplySubAdd132Float64x4: + v.Op = OpAMD64VFMSUBADD132PD256 + return true + case OpFusedMultiplySubAdd132Float64x8: + v.Op = OpAMD64VFMSUBADD132PD512 + return true + case OpFusedMultiplySubAdd213Float32x16: + v.Op = OpAMD64VFMSUBADD213PS512 + return true + case OpFusedMultiplySubAdd213Float32x4: + v.Op = OpAMD64VFMSUBADD213PS128 + return true + case OpFusedMultiplySubAdd213Float32x8: + v.Op = OpAMD64VFMSUBADD213PS256 + return true + case OpFusedMultiplySubAdd213Float64x2: + v.Op = OpAMD64VFMSUBADD213PD128 + return true + case OpFusedMultiplySubAdd213Float64x4: + v.Op = OpAMD64VFMSUBADD213PD256 + return true + case OpFusedMultiplySubAdd213Float64x8: + v.Op = OpAMD64VFMSUBADD213PD512 + return true + case OpFusedMultiplySubAdd231Float32x16: + v.Op = OpAMD64VFMSUBADD231PS512 + return true + case OpFusedMultiplySubAdd231Float32x4: + v.Op = OpAMD64VFMSUBADD231PS128 + return true + case OpFusedMultiplySubAdd231Float32x8: + v.Op = OpAMD64VFMSUBADD231PS256 + return true + case OpFusedMultiplySubAdd231Float64x2: + v.Op = OpAMD64VFMSUBADD231PD128 + return true + case OpFusedMultiplySubAdd231Float64x4: + v.Op = OpAMD64VFMSUBADD231PD256 + return true + case OpFusedMultiplySubAdd231Float64x8: + v.Op = OpAMD64VFMSUBADD231PD512 + return true + case OpFusedNegativeMultiplyAdd132Float32x16: + v.Op = OpAMD64VFNMADD132PS512 + return true + case OpFusedNegativeMultiplyAdd132Float32x4: + v.Op = OpAMD64VFNMADD132PS128 + return true + case OpFusedNegativeMultiplyAdd132Float32x8: + v.Op = OpAMD64VFNMADD132PS256 + return true + case OpFusedNegativeMultiplyAdd132Float64x2: + v.Op = OpAMD64VFNMADD132PD128 + return true + case OpFusedNegativeMultiplyAdd132Float64x4: + v.Op = OpAMD64VFNMADD132PD256 + return true + case OpFusedNegativeMultiplyAdd132Float64x8: + v.Op = OpAMD64VFNMADD132PD512 + return true + case OpFusedNegativeMultiplyAdd213Float32x16: + v.Op = OpAMD64VFNMADD213PS512 + return true + case OpFusedNegativeMultiplyAdd213Float32x4: + v.Op = OpAMD64VFNMADD213PS128 + return true + case OpFusedNegativeMultiplyAdd213Float32x8: + v.Op = OpAMD64VFNMADD213PS256 + return true + case OpFusedNegativeMultiplyAdd213Float64x2: + v.Op = OpAMD64VFNMADD213PD128 + return true + case OpFusedNegativeMultiplyAdd213Float64x4: + v.Op = OpAMD64VFNMADD213PD256 + return true + case OpFusedNegativeMultiplyAdd213Float64x8: + v.Op = OpAMD64VFNMADD213PD512 + return true + case OpFusedNegativeMultiplyAdd231Float32x16: + v.Op = OpAMD64VFNMADD231PS512 + return true + case OpFusedNegativeMultiplyAdd231Float32x4: + v.Op = OpAMD64VFNMADD231PS128 + return true + case OpFusedNegativeMultiplyAdd231Float32x8: + v.Op = OpAMD64VFNMADD231PS256 + return true + case OpFusedNegativeMultiplyAdd231Float64x2: + v.Op = OpAMD64VFNMADD231PD128 + return true + case OpFusedNegativeMultiplyAdd231Float64x4: + v.Op = OpAMD64VFNMADD231PD256 + return true + case OpFusedNegativeMultiplyAdd231Float64x8: + v.Op = OpAMD64VFNMADD231PD512 + return true + case OpFusedNegativeMultiplySub132Float32x16: + v.Op = OpAMD64VFNMSUB132PS512 + return true + case OpFusedNegativeMultiplySub132Float32x4: + v.Op = OpAMD64VFNMSUB132PS128 + return true + case OpFusedNegativeMultiplySub132Float32x8: + v.Op = OpAMD64VFNMSUB132PS256 + return true + case OpFusedNegativeMultiplySub132Float64x2: + v.Op = OpAMD64VFNMSUB132PD128 + return true + case OpFusedNegativeMultiplySub132Float64x4: + v.Op = OpAMD64VFNMSUB132PD256 + return true + case OpFusedNegativeMultiplySub132Float64x8: + v.Op = OpAMD64VFNMSUB132PD512 + return true + case OpFusedNegativeMultiplySub213Float32x16: + v.Op = OpAMD64VFNMSUB213PS512 + return true + case OpFusedNegativeMultiplySub213Float32x4: + v.Op = OpAMD64VFNMSUB213PS128 + return true + case OpFusedNegativeMultiplySub213Float32x8: + v.Op = OpAMD64VFNMSUB213PS256 + return true + case OpFusedNegativeMultiplySub213Float64x2: + v.Op = OpAMD64VFNMSUB213PD128 + return true + case OpFusedNegativeMultiplySub213Float64x4: + v.Op = OpAMD64VFNMSUB213PD256 + return true + case OpFusedNegativeMultiplySub213Float64x8: + v.Op = OpAMD64VFNMSUB213PD512 + return true + case OpFusedNegativeMultiplySub231Float32x16: + v.Op = OpAMD64VFNMSUB231PS512 + return true + case OpFusedNegativeMultiplySub231Float32x4: + v.Op = OpAMD64VFNMSUB231PS128 + return true + case OpFusedNegativeMultiplySub231Float32x8: + v.Op = OpAMD64VFNMSUB231PS256 + return true + case OpFusedNegativeMultiplySub231Float64x2: + v.Op = OpAMD64VFNMSUB231PD128 + return true + case OpFusedNegativeMultiplySub231Float64x4: + v.Op = OpAMD64VFNMSUB231PD256 + return true + case OpFusedNegativeMultiplySub231Float64x8: + v.Op = OpAMD64VFNMSUB231PD512 + return true case OpGetCallerPC: v.Op = OpAMD64LoweredGetCallerPC return true @@ -776,6 +1720,133 @@ func rewriteValueAMD64(v *Value) bool { return true case OpGetG: return rewriteValueAMD64_OpGetG(v) + case OpGreaterEqualFloat32x16: + return rewriteValueAMD64_OpGreaterEqualFloat32x16(v) + case OpGreaterEqualFloat32x4: + return rewriteValueAMD64_OpGreaterEqualFloat32x4(v) + case OpGreaterEqualFloat32x8: + return rewriteValueAMD64_OpGreaterEqualFloat32x8(v) + case OpGreaterEqualFloat64x2: + return rewriteValueAMD64_OpGreaterEqualFloat64x2(v) + case OpGreaterEqualFloat64x4: + return rewriteValueAMD64_OpGreaterEqualFloat64x4(v) + case OpGreaterEqualFloat64x8: + return rewriteValueAMD64_OpGreaterEqualFloat64x8(v) + case OpGreaterEqualInt16x16: + return rewriteValueAMD64_OpGreaterEqualInt16x16(v) + case OpGreaterEqualInt16x32: + return rewriteValueAMD64_OpGreaterEqualInt16x32(v) + case OpGreaterEqualInt16x8: + return rewriteValueAMD64_OpGreaterEqualInt16x8(v) + case OpGreaterEqualInt32x16: + return rewriteValueAMD64_OpGreaterEqualInt32x16(v) + case OpGreaterEqualInt32x4: + return rewriteValueAMD64_OpGreaterEqualInt32x4(v) + case OpGreaterEqualInt32x8: + return rewriteValueAMD64_OpGreaterEqualInt32x8(v) + case OpGreaterEqualInt64x2: + return rewriteValueAMD64_OpGreaterEqualInt64x2(v) + case OpGreaterEqualInt64x4: + return rewriteValueAMD64_OpGreaterEqualInt64x4(v) + case OpGreaterEqualInt64x8: + return rewriteValueAMD64_OpGreaterEqualInt64x8(v) + case OpGreaterEqualInt8x16: + return rewriteValueAMD64_OpGreaterEqualInt8x16(v) + case OpGreaterEqualInt8x32: + return rewriteValueAMD64_OpGreaterEqualInt8x32(v) + case OpGreaterEqualInt8x64: + return rewriteValueAMD64_OpGreaterEqualInt8x64(v) + case OpGreaterEqualUint16x16: + return rewriteValueAMD64_OpGreaterEqualUint16x16(v) + case OpGreaterEqualUint16x32: + return rewriteValueAMD64_OpGreaterEqualUint16x32(v) + case OpGreaterEqualUint16x8: + return rewriteValueAMD64_OpGreaterEqualUint16x8(v) + case OpGreaterEqualUint32x16: + return rewriteValueAMD64_OpGreaterEqualUint32x16(v) + case OpGreaterEqualUint32x4: + return rewriteValueAMD64_OpGreaterEqualUint32x4(v) + case OpGreaterEqualUint32x8: + return rewriteValueAMD64_OpGreaterEqualUint32x8(v) + case OpGreaterEqualUint64x2: + return rewriteValueAMD64_OpGreaterEqualUint64x2(v) + case OpGreaterEqualUint64x4: + return rewriteValueAMD64_OpGreaterEqualUint64x4(v) + case OpGreaterEqualUint64x8: + return rewriteValueAMD64_OpGreaterEqualUint64x8(v) + case OpGreaterEqualUint8x16: + return rewriteValueAMD64_OpGreaterEqualUint8x16(v) + case OpGreaterEqualUint8x32: + return rewriteValueAMD64_OpGreaterEqualUint8x32(v) + case OpGreaterEqualUint8x64: + return rewriteValueAMD64_OpGreaterEqualUint8x64(v) + case OpGreaterFloat32x16: + return rewriteValueAMD64_OpGreaterFloat32x16(v) + case OpGreaterFloat32x4: + return rewriteValueAMD64_OpGreaterFloat32x4(v) + case OpGreaterFloat32x8: + return rewriteValueAMD64_OpGreaterFloat32x8(v) + case OpGreaterFloat64x2: + return rewriteValueAMD64_OpGreaterFloat64x2(v) + case OpGreaterFloat64x4: + return rewriteValueAMD64_OpGreaterFloat64x4(v) + case OpGreaterFloat64x8: + return rewriteValueAMD64_OpGreaterFloat64x8(v) + case OpGreaterInt16x16: + v.Op = OpAMD64VPCMPGTW256 + return true + case OpGreaterInt16x32: + return rewriteValueAMD64_OpGreaterInt16x32(v) + case OpGreaterInt16x8: + v.Op = OpAMD64VPCMPGTW128 + return true + case OpGreaterInt32x16: + return rewriteValueAMD64_OpGreaterInt32x16(v) + case OpGreaterInt32x4: + v.Op = OpAMD64VPCMPGTD128 + return true + case OpGreaterInt32x8: + v.Op = OpAMD64VPCMPGTD256 + return true + case OpGreaterInt64x2: + return rewriteValueAMD64_OpGreaterInt64x2(v) + case OpGreaterInt64x4: + v.Op = OpAMD64VPCMPGTQ256 + return true + case OpGreaterInt64x8: + return rewriteValueAMD64_OpGreaterInt64x8(v) + case OpGreaterInt8x16: + v.Op = OpAMD64VPCMPGTB128 + return true + case OpGreaterInt8x32: + v.Op = OpAMD64VPCMPGTB256 + return true + case OpGreaterInt8x64: + return rewriteValueAMD64_OpGreaterInt8x64(v) + case OpGreaterUint16x16: + return rewriteValueAMD64_OpGreaterUint16x16(v) + case OpGreaterUint16x32: + return rewriteValueAMD64_OpGreaterUint16x32(v) + case OpGreaterUint16x8: + return rewriteValueAMD64_OpGreaterUint16x8(v) + case OpGreaterUint32x16: + return rewriteValueAMD64_OpGreaterUint32x16(v) + case OpGreaterUint32x4: + return rewriteValueAMD64_OpGreaterUint32x4(v) + case OpGreaterUint32x8: + return rewriteValueAMD64_OpGreaterUint32x8(v) + case OpGreaterUint64x2: + return rewriteValueAMD64_OpGreaterUint64x2(v) + case OpGreaterUint64x4: + return rewriteValueAMD64_OpGreaterUint64x4(v) + case OpGreaterUint64x8: + return rewriteValueAMD64_OpGreaterUint64x8(v) + case OpGreaterUint8x16: + return rewriteValueAMD64_OpGreaterUint8x16(v) + case OpGreaterUint8x32: + return rewriteValueAMD64_OpGreaterUint8x32(v) + case OpGreaterUint8x64: + return rewriteValueAMD64_OpGreaterUint8x64(v) case OpHasCPUFeature: return rewriteValueAMD64_OpHasCPUFeature(v) case OpHmul32: @@ -795,6 +1866,18 @@ func rewriteValueAMD64(v *Value) bool { return true case OpIsInBounds: return rewriteValueAMD64_OpIsInBounds(v) + case OpIsNanFloat32x16: + return rewriteValueAMD64_OpIsNanFloat32x16(v) + case OpIsNanFloat32x4: + return rewriteValueAMD64_OpIsNanFloat32x4(v) + case OpIsNanFloat32x8: + return rewriteValueAMD64_OpIsNanFloat32x8(v) + case OpIsNanFloat64x2: + return rewriteValueAMD64_OpIsNanFloat64x2(v) + case OpIsNanFloat64x4: + return rewriteValueAMD64_OpIsNanFloat64x4(v) + case OpIsNanFloat64x8: + return rewriteValueAMD64_OpIsNanFloat64x8(v) case OpIsNonNil: return rewriteValueAMD64_OpIsNonNil(v) case OpIsSliceInBounds: @@ -839,6 +1922,126 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpLess8(v) case OpLess8U: return rewriteValueAMD64_OpLess8U(v) + case OpLessEqualFloat32x16: + return rewriteValueAMD64_OpLessEqualFloat32x16(v) + case OpLessEqualFloat32x4: + return rewriteValueAMD64_OpLessEqualFloat32x4(v) + case OpLessEqualFloat32x8: + return rewriteValueAMD64_OpLessEqualFloat32x8(v) + case OpLessEqualFloat64x2: + return rewriteValueAMD64_OpLessEqualFloat64x2(v) + case OpLessEqualFloat64x4: + return rewriteValueAMD64_OpLessEqualFloat64x4(v) + case OpLessEqualFloat64x8: + return rewriteValueAMD64_OpLessEqualFloat64x8(v) + case OpLessEqualInt16x16: + return rewriteValueAMD64_OpLessEqualInt16x16(v) + case OpLessEqualInt16x32: + return rewriteValueAMD64_OpLessEqualInt16x32(v) + case OpLessEqualInt16x8: + return rewriteValueAMD64_OpLessEqualInt16x8(v) + case OpLessEqualInt32x16: + return rewriteValueAMD64_OpLessEqualInt32x16(v) + case OpLessEqualInt32x4: + return rewriteValueAMD64_OpLessEqualInt32x4(v) + case OpLessEqualInt32x8: + return rewriteValueAMD64_OpLessEqualInt32x8(v) + case OpLessEqualInt64x2: + return rewriteValueAMD64_OpLessEqualInt64x2(v) + case OpLessEqualInt64x4: + return rewriteValueAMD64_OpLessEqualInt64x4(v) + case OpLessEqualInt64x8: + return rewriteValueAMD64_OpLessEqualInt64x8(v) + case OpLessEqualInt8x16: + return rewriteValueAMD64_OpLessEqualInt8x16(v) + case OpLessEqualInt8x32: + return rewriteValueAMD64_OpLessEqualInt8x32(v) + case OpLessEqualInt8x64: + return rewriteValueAMD64_OpLessEqualInt8x64(v) + case OpLessEqualUint16x16: + return rewriteValueAMD64_OpLessEqualUint16x16(v) + case OpLessEqualUint16x32: + return rewriteValueAMD64_OpLessEqualUint16x32(v) + case OpLessEqualUint16x8: + return rewriteValueAMD64_OpLessEqualUint16x8(v) + case OpLessEqualUint32x16: + return rewriteValueAMD64_OpLessEqualUint32x16(v) + case OpLessEqualUint32x4: + return rewriteValueAMD64_OpLessEqualUint32x4(v) + case OpLessEqualUint32x8: + return rewriteValueAMD64_OpLessEqualUint32x8(v) + case OpLessEqualUint64x2: + return rewriteValueAMD64_OpLessEqualUint64x2(v) + case OpLessEqualUint64x4: + return rewriteValueAMD64_OpLessEqualUint64x4(v) + case OpLessEqualUint64x8: + return rewriteValueAMD64_OpLessEqualUint64x8(v) + case OpLessEqualUint8x16: + return rewriteValueAMD64_OpLessEqualUint8x16(v) + case OpLessEqualUint8x32: + return rewriteValueAMD64_OpLessEqualUint8x32(v) + case OpLessEqualUint8x64: + return rewriteValueAMD64_OpLessEqualUint8x64(v) + case OpLessFloat32x16: + return rewriteValueAMD64_OpLessFloat32x16(v) + case OpLessFloat32x4: + return rewriteValueAMD64_OpLessFloat32x4(v) + case OpLessFloat32x8: + return rewriteValueAMD64_OpLessFloat32x8(v) + case OpLessFloat64x2: + return rewriteValueAMD64_OpLessFloat64x2(v) + case OpLessFloat64x4: + return rewriteValueAMD64_OpLessFloat64x4(v) + case OpLessFloat64x8: + return rewriteValueAMD64_OpLessFloat64x8(v) + case OpLessInt16x16: + return rewriteValueAMD64_OpLessInt16x16(v) + case OpLessInt16x32: + return rewriteValueAMD64_OpLessInt16x32(v) + case OpLessInt16x8: + return rewriteValueAMD64_OpLessInt16x8(v) + case OpLessInt32x16: + return rewriteValueAMD64_OpLessInt32x16(v) + case OpLessInt32x4: + return rewriteValueAMD64_OpLessInt32x4(v) + case OpLessInt32x8: + return rewriteValueAMD64_OpLessInt32x8(v) + case OpLessInt64x2: + return rewriteValueAMD64_OpLessInt64x2(v) + case OpLessInt64x4: + return rewriteValueAMD64_OpLessInt64x4(v) + case OpLessInt64x8: + return rewriteValueAMD64_OpLessInt64x8(v) + case OpLessInt8x16: + return rewriteValueAMD64_OpLessInt8x16(v) + case OpLessInt8x32: + return rewriteValueAMD64_OpLessInt8x32(v) + case OpLessInt8x64: + return rewriteValueAMD64_OpLessInt8x64(v) + case OpLessUint16x16: + return rewriteValueAMD64_OpLessUint16x16(v) + case OpLessUint16x32: + return rewriteValueAMD64_OpLessUint16x32(v) + case OpLessUint16x8: + return rewriteValueAMD64_OpLessUint16x8(v) + case OpLessUint32x16: + return rewriteValueAMD64_OpLessUint32x16(v) + case OpLessUint32x4: + return rewriteValueAMD64_OpLessUint32x4(v) + case OpLessUint32x8: + return rewriteValueAMD64_OpLessUint32x8(v) + case OpLessUint64x2: + return rewriteValueAMD64_OpLessUint64x2(v) + case OpLessUint64x4: + return rewriteValueAMD64_OpLessUint64x4(v) + case OpLessUint64x8: + return rewriteValueAMD64_OpLessUint64x8(v) + case OpLessUint8x16: + return rewriteValueAMD64_OpLessUint8x16(v) + case OpLessUint8x32: + return rewriteValueAMD64_OpLessUint8x32(v) + case OpLessUint8x64: + return rewriteValueAMD64_OpLessUint8x64(v) case OpLoad: return rewriteValueAMD64_OpLoad(v) case OpLocalAddr: @@ -875,14 +2078,1652 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpLsh8x64(v) case OpLsh8x8: return rewriteValueAMD64_OpLsh8x8(v) + case OpMaskedAbsoluteInt16x16: + return rewriteValueAMD64_OpMaskedAbsoluteInt16x16(v) + case OpMaskedAbsoluteInt16x32: + return rewriteValueAMD64_OpMaskedAbsoluteInt16x32(v) + case OpMaskedAbsoluteInt16x8: + return rewriteValueAMD64_OpMaskedAbsoluteInt16x8(v) + case OpMaskedAbsoluteInt32x16: + return rewriteValueAMD64_OpMaskedAbsoluteInt32x16(v) + case OpMaskedAbsoluteInt32x4: + return rewriteValueAMD64_OpMaskedAbsoluteInt32x4(v) + case OpMaskedAbsoluteInt32x8: + return rewriteValueAMD64_OpMaskedAbsoluteInt32x8(v) + case OpMaskedAbsoluteInt64x2: + return rewriteValueAMD64_OpMaskedAbsoluteInt64x2(v) + case OpMaskedAbsoluteInt64x4: + return rewriteValueAMD64_OpMaskedAbsoluteInt64x4(v) + case OpMaskedAbsoluteInt64x8: + return rewriteValueAMD64_OpMaskedAbsoluteInt64x8(v) + case OpMaskedAbsoluteInt8x16: + return rewriteValueAMD64_OpMaskedAbsoluteInt8x16(v) + case OpMaskedAbsoluteInt8x32: + return rewriteValueAMD64_OpMaskedAbsoluteInt8x32(v) + case OpMaskedAbsoluteInt8x64: + return rewriteValueAMD64_OpMaskedAbsoluteInt8x64(v) + case OpMaskedAddFloat32x16: + return rewriteValueAMD64_OpMaskedAddFloat32x16(v) + case OpMaskedAddFloat32x4: + return rewriteValueAMD64_OpMaskedAddFloat32x4(v) + case OpMaskedAddFloat32x8: + return rewriteValueAMD64_OpMaskedAddFloat32x8(v) + case OpMaskedAddFloat64x2: + return rewriteValueAMD64_OpMaskedAddFloat64x2(v) + case OpMaskedAddFloat64x4: + return rewriteValueAMD64_OpMaskedAddFloat64x4(v) + case OpMaskedAddFloat64x8: + return rewriteValueAMD64_OpMaskedAddFloat64x8(v) + case OpMaskedAddInt16x16: + return rewriteValueAMD64_OpMaskedAddInt16x16(v) + case OpMaskedAddInt16x32: + return rewriteValueAMD64_OpMaskedAddInt16x32(v) + case OpMaskedAddInt16x8: + return rewriteValueAMD64_OpMaskedAddInt16x8(v) + case OpMaskedAddInt32x16: + return rewriteValueAMD64_OpMaskedAddInt32x16(v) + case OpMaskedAddInt32x4: + return rewriteValueAMD64_OpMaskedAddInt32x4(v) + case OpMaskedAddInt32x8: + return rewriteValueAMD64_OpMaskedAddInt32x8(v) + case OpMaskedAddInt64x2: + return rewriteValueAMD64_OpMaskedAddInt64x2(v) + case OpMaskedAddInt64x4: + return rewriteValueAMD64_OpMaskedAddInt64x4(v) + case OpMaskedAddInt64x8: + return rewriteValueAMD64_OpMaskedAddInt64x8(v) + case OpMaskedAddInt8x16: + return rewriteValueAMD64_OpMaskedAddInt8x16(v) + case OpMaskedAddInt8x32: + return rewriteValueAMD64_OpMaskedAddInt8x32(v) + case OpMaskedAddInt8x64: + return rewriteValueAMD64_OpMaskedAddInt8x64(v) + case OpMaskedAddUint16x16: + return rewriteValueAMD64_OpMaskedAddUint16x16(v) + case OpMaskedAddUint16x32: + return rewriteValueAMD64_OpMaskedAddUint16x32(v) + case OpMaskedAddUint16x8: + return rewriteValueAMD64_OpMaskedAddUint16x8(v) + case OpMaskedAddUint32x16: + return rewriteValueAMD64_OpMaskedAddUint32x16(v) + case OpMaskedAddUint32x4: + return rewriteValueAMD64_OpMaskedAddUint32x4(v) + case OpMaskedAddUint32x8: + return rewriteValueAMD64_OpMaskedAddUint32x8(v) + case OpMaskedAddUint64x2: + return rewriteValueAMD64_OpMaskedAddUint64x2(v) + case OpMaskedAddUint64x4: + return rewriteValueAMD64_OpMaskedAddUint64x4(v) + case OpMaskedAddUint64x8: + return rewriteValueAMD64_OpMaskedAddUint64x8(v) + case OpMaskedAddUint8x16: + return rewriteValueAMD64_OpMaskedAddUint8x16(v) + case OpMaskedAddUint8x32: + return rewriteValueAMD64_OpMaskedAddUint8x32(v) + case OpMaskedAddUint8x64: + return rewriteValueAMD64_OpMaskedAddUint8x64(v) + case OpMaskedAndFloat32x16: + return rewriteValueAMD64_OpMaskedAndFloat32x16(v) + case OpMaskedAndFloat32x4: + return rewriteValueAMD64_OpMaskedAndFloat32x4(v) + case OpMaskedAndFloat32x8: + return rewriteValueAMD64_OpMaskedAndFloat32x8(v) + case OpMaskedAndFloat64x2: + return rewriteValueAMD64_OpMaskedAndFloat64x2(v) + case OpMaskedAndFloat64x4: + return rewriteValueAMD64_OpMaskedAndFloat64x4(v) + case OpMaskedAndFloat64x8: + return rewriteValueAMD64_OpMaskedAndFloat64x8(v) + case OpMaskedAndInt32x16: + return rewriteValueAMD64_OpMaskedAndInt32x16(v) + case OpMaskedAndInt32x4: + return rewriteValueAMD64_OpMaskedAndInt32x4(v) + case OpMaskedAndInt32x8: + return rewriteValueAMD64_OpMaskedAndInt32x8(v) + case OpMaskedAndInt64x2: + return rewriteValueAMD64_OpMaskedAndInt64x2(v) + case OpMaskedAndInt64x4: + return rewriteValueAMD64_OpMaskedAndInt64x4(v) + case OpMaskedAndInt64x8: + return rewriteValueAMD64_OpMaskedAndInt64x8(v) + case OpMaskedAndNotFloat32x16: + return rewriteValueAMD64_OpMaskedAndNotFloat32x16(v) + case OpMaskedAndNotFloat32x4: + return rewriteValueAMD64_OpMaskedAndNotFloat32x4(v) + case OpMaskedAndNotFloat32x8: + return rewriteValueAMD64_OpMaskedAndNotFloat32x8(v) + case OpMaskedAndNotFloat64x2: + return rewriteValueAMD64_OpMaskedAndNotFloat64x2(v) + case OpMaskedAndNotFloat64x4: + return rewriteValueAMD64_OpMaskedAndNotFloat64x4(v) + case OpMaskedAndNotFloat64x8: + return rewriteValueAMD64_OpMaskedAndNotFloat64x8(v) + case OpMaskedAndNotInt32x16: + return rewriteValueAMD64_OpMaskedAndNotInt32x16(v) + case OpMaskedAndNotInt32x4: + return rewriteValueAMD64_OpMaskedAndNotInt32x4(v) + case OpMaskedAndNotInt32x8: + return rewriteValueAMD64_OpMaskedAndNotInt32x8(v) + case OpMaskedAndNotInt64x2: + return rewriteValueAMD64_OpMaskedAndNotInt64x2(v) + case OpMaskedAndNotInt64x4: + return rewriteValueAMD64_OpMaskedAndNotInt64x4(v) + case OpMaskedAndNotInt64x8: + return rewriteValueAMD64_OpMaskedAndNotInt64x8(v) + case OpMaskedAndNotUint32x16: + return rewriteValueAMD64_OpMaskedAndNotUint32x16(v) + case OpMaskedAndNotUint32x4: + return rewriteValueAMD64_OpMaskedAndNotUint32x4(v) + case OpMaskedAndNotUint32x8: + return rewriteValueAMD64_OpMaskedAndNotUint32x8(v) + case OpMaskedAndNotUint64x2: + return rewriteValueAMD64_OpMaskedAndNotUint64x2(v) + case OpMaskedAndNotUint64x4: + return rewriteValueAMD64_OpMaskedAndNotUint64x4(v) + case OpMaskedAndNotUint64x8: + return rewriteValueAMD64_OpMaskedAndNotUint64x8(v) + case OpMaskedAndUint32x16: + return rewriteValueAMD64_OpMaskedAndUint32x16(v) + case OpMaskedAndUint32x4: + return rewriteValueAMD64_OpMaskedAndUint32x4(v) + case OpMaskedAndUint32x8: + return rewriteValueAMD64_OpMaskedAndUint32x8(v) + case OpMaskedAndUint64x2: + return rewriteValueAMD64_OpMaskedAndUint64x2(v) + case OpMaskedAndUint64x4: + return rewriteValueAMD64_OpMaskedAndUint64x4(v) + case OpMaskedAndUint64x8: + return rewriteValueAMD64_OpMaskedAndUint64x8(v) + case OpMaskedApproximateReciprocalFloat32x16: + return rewriteValueAMD64_OpMaskedApproximateReciprocalFloat32x16(v) + case OpMaskedApproximateReciprocalFloat32x4: + return rewriteValueAMD64_OpMaskedApproximateReciprocalFloat32x4(v) + case OpMaskedApproximateReciprocalFloat32x8: + return rewriteValueAMD64_OpMaskedApproximateReciprocalFloat32x8(v) + case OpMaskedApproximateReciprocalFloat64x2: + return rewriteValueAMD64_OpMaskedApproximateReciprocalFloat64x2(v) + case OpMaskedApproximateReciprocalFloat64x4: + return rewriteValueAMD64_OpMaskedApproximateReciprocalFloat64x4(v) + case OpMaskedApproximateReciprocalFloat64x8: + return rewriteValueAMD64_OpMaskedApproximateReciprocalFloat64x8(v) + case OpMaskedApproximateReciprocalOfSqrtFloat32x16: + return rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat32x16(v) + case OpMaskedApproximateReciprocalOfSqrtFloat32x4: + return rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat32x4(v) + case OpMaskedApproximateReciprocalOfSqrtFloat32x8: + return rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat32x8(v) + case OpMaskedApproximateReciprocalOfSqrtFloat64x2: + return rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat64x2(v) + case OpMaskedApproximateReciprocalOfSqrtFloat64x4: + return rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat64x4(v) + case OpMaskedApproximateReciprocalOfSqrtFloat64x8: + return rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat64x8(v) + case OpMaskedAverageUint16x16: + return rewriteValueAMD64_OpMaskedAverageUint16x16(v) + case OpMaskedAverageUint16x32: + return rewriteValueAMD64_OpMaskedAverageUint16x32(v) + case OpMaskedAverageUint16x8: + return rewriteValueAMD64_OpMaskedAverageUint16x8(v) + case OpMaskedAverageUint8x16: + return rewriteValueAMD64_OpMaskedAverageUint8x16(v) + case OpMaskedAverageUint8x32: + return rewriteValueAMD64_OpMaskedAverageUint8x32(v) + case OpMaskedAverageUint8x64: + return rewriteValueAMD64_OpMaskedAverageUint8x64(v) + case OpMaskedCeilSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedCeilSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedCeilSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedCeilSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedCeilSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedCeilSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedCeilWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat32x16(v) + case OpMaskedCeilWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat32x4(v) + case OpMaskedCeilWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat32x8(v) + case OpMaskedCeilWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat64x2(v) + case OpMaskedCeilWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat64x4(v) + case OpMaskedCeilWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat64x8(v) + case OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedDiffWithCeilWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat32x16(v) + case OpMaskedDiffWithCeilWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat32x4(v) + case OpMaskedDiffWithCeilWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat32x8(v) + case OpMaskedDiffWithCeilWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat64x2(v) + case OpMaskedDiffWithCeilWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat64x4(v) + case OpMaskedDiffWithCeilWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat64x8(v) + case OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedDiffWithFloorWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat32x16(v) + case OpMaskedDiffWithFloorWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat32x4(v) + case OpMaskedDiffWithFloorWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat32x8(v) + case OpMaskedDiffWithFloorWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat64x2(v) + case OpMaskedDiffWithFloorWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat64x4(v) + case OpMaskedDiffWithFloorWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat64x8(v) + case OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedDiffWithRoundWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat32x16(v) + case OpMaskedDiffWithRoundWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat32x4(v) + case OpMaskedDiffWithRoundWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat32x8(v) + case OpMaskedDiffWithRoundWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat64x2(v) + case OpMaskedDiffWithRoundWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat64x4(v) + case OpMaskedDiffWithRoundWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat64x8(v) + case OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedDiffWithTruncWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat32x16(v) + case OpMaskedDiffWithTruncWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat32x4(v) + case OpMaskedDiffWithTruncWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat32x8(v) + case OpMaskedDiffWithTruncWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat64x2(v) + case OpMaskedDiffWithTruncWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat64x4(v) + case OpMaskedDiffWithTruncWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat64x8(v) + case OpMaskedDivFloat32x16: + return rewriteValueAMD64_OpMaskedDivFloat32x16(v) + case OpMaskedDivFloat32x4: + return rewriteValueAMD64_OpMaskedDivFloat32x4(v) + case OpMaskedDivFloat32x8: + return rewriteValueAMD64_OpMaskedDivFloat32x8(v) + case OpMaskedDivFloat64x2: + return rewriteValueAMD64_OpMaskedDivFloat64x2(v) + case OpMaskedDivFloat64x4: + return rewriteValueAMD64_OpMaskedDivFloat64x4(v) + case OpMaskedDivFloat64x8: + return rewriteValueAMD64_OpMaskedDivFloat64x8(v) + case OpMaskedEqualFloat32x16: + return rewriteValueAMD64_OpMaskedEqualFloat32x16(v) + case OpMaskedEqualFloat32x4: + return rewriteValueAMD64_OpMaskedEqualFloat32x4(v) + case OpMaskedEqualFloat32x8: + return rewriteValueAMD64_OpMaskedEqualFloat32x8(v) + case OpMaskedEqualFloat64x2: + return rewriteValueAMD64_OpMaskedEqualFloat64x2(v) + case OpMaskedEqualFloat64x4: + return rewriteValueAMD64_OpMaskedEqualFloat64x4(v) + case OpMaskedEqualFloat64x8: + return rewriteValueAMD64_OpMaskedEqualFloat64x8(v) + case OpMaskedEqualInt16x16: + return rewriteValueAMD64_OpMaskedEqualInt16x16(v) + case OpMaskedEqualInt16x32: + return rewriteValueAMD64_OpMaskedEqualInt16x32(v) + case OpMaskedEqualInt16x8: + return rewriteValueAMD64_OpMaskedEqualInt16x8(v) + case OpMaskedEqualInt32x16: + return rewriteValueAMD64_OpMaskedEqualInt32x16(v) + case OpMaskedEqualInt32x4: + return rewriteValueAMD64_OpMaskedEqualInt32x4(v) + case OpMaskedEqualInt32x8: + return rewriteValueAMD64_OpMaskedEqualInt32x8(v) + case OpMaskedEqualInt64x2: + return rewriteValueAMD64_OpMaskedEqualInt64x2(v) + case OpMaskedEqualInt64x4: + return rewriteValueAMD64_OpMaskedEqualInt64x4(v) + case OpMaskedEqualInt64x8: + return rewriteValueAMD64_OpMaskedEqualInt64x8(v) + case OpMaskedEqualInt8x16: + return rewriteValueAMD64_OpMaskedEqualInt8x16(v) + case OpMaskedEqualInt8x32: + return rewriteValueAMD64_OpMaskedEqualInt8x32(v) + case OpMaskedEqualInt8x64: + return rewriteValueAMD64_OpMaskedEqualInt8x64(v) + case OpMaskedEqualUint16x16: + return rewriteValueAMD64_OpMaskedEqualUint16x16(v) + case OpMaskedEqualUint16x32: + return rewriteValueAMD64_OpMaskedEqualUint16x32(v) + case OpMaskedEqualUint16x8: + return rewriteValueAMD64_OpMaskedEqualUint16x8(v) + case OpMaskedEqualUint32x16: + return rewriteValueAMD64_OpMaskedEqualUint32x16(v) + case OpMaskedEqualUint32x4: + return rewriteValueAMD64_OpMaskedEqualUint32x4(v) + case OpMaskedEqualUint32x8: + return rewriteValueAMD64_OpMaskedEqualUint32x8(v) + case OpMaskedEqualUint64x2: + return rewriteValueAMD64_OpMaskedEqualUint64x2(v) + case OpMaskedEqualUint64x4: + return rewriteValueAMD64_OpMaskedEqualUint64x4(v) + case OpMaskedEqualUint64x8: + return rewriteValueAMD64_OpMaskedEqualUint64x8(v) + case OpMaskedEqualUint8x16: + return rewriteValueAMD64_OpMaskedEqualUint8x16(v) + case OpMaskedEqualUint8x32: + return rewriteValueAMD64_OpMaskedEqualUint8x32(v) + case OpMaskedEqualUint8x64: + return rewriteValueAMD64_OpMaskedEqualUint8x64(v) + case OpMaskedFloorSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedFloorSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedFloorSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedFloorSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedFloorSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedFloorSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedFloorWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat32x16(v) + case OpMaskedFloorWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat32x4(v) + case OpMaskedFloorWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat32x8(v) + case OpMaskedFloorWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat64x2(v) + case OpMaskedFloorWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat64x4(v) + case OpMaskedFloorWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat64x8(v) + case OpMaskedFusedMultiplyAdd132Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float32x16(v) + case OpMaskedFusedMultiplyAdd132Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float32x4(v) + case OpMaskedFusedMultiplyAdd132Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float32x8(v) + case OpMaskedFusedMultiplyAdd132Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float64x2(v) + case OpMaskedFusedMultiplyAdd132Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float64x4(v) + case OpMaskedFusedMultiplyAdd132Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float64x8(v) + case OpMaskedFusedMultiplyAdd213Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float32x16(v) + case OpMaskedFusedMultiplyAdd213Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float32x4(v) + case OpMaskedFusedMultiplyAdd213Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float32x8(v) + case OpMaskedFusedMultiplyAdd213Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float64x2(v) + case OpMaskedFusedMultiplyAdd213Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float64x4(v) + case OpMaskedFusedMultiplyAdd213Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float64x8(v) + case OpMaskedFusedMultiplyAdd231Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float32x16(v) + case OpMaskedFusedMultiplyAdd231Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float32x4(v) + case OpMaskedFusedMultiplyAdd231Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float32x8(v) + case OpMaskedFusedMultiplyAdd231Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float64x2(v) + case OpMaskedFusedMultiplyAdd231Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float64x4(v) + case OpMaskedFusedMultiplyAdd231Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float64x8(v) + case OpMaskedFusedMultiplyAddSub132Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float32x16(v) + case OpMaskedFusedMultiplyAddSub132Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float32x4(v) + case OpMaskedFusedMultiplyAddSub132Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float32x8(v) + case OpMaskedFusedMultiplyAddSub132Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float64x2(v) + case OpMaskedFusedMultiplyAddSub132Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float64x4(v) + case OpMaskedFusedMultiplyAddSub132Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float64x8(v) + case OpMaskedFusedMultiplyAddSub213Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float32x16(v) + case OpMaskedFusedMultiplyAddSub213Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float32x4(v) + case OpMaskedFusedMultiplyAddSub213Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float32x8(v) + case OpMaskedFusedMultiplyAddSub213Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float64x2(v) + case OpMaskedFusedMultiplyAddSub213Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float64x4(v) + case OpMaskedFusedMultiplyAddSub213Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float64x8(v) + case OpMaskedFusedMultiplyAddSub231Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float32x16(v) + case OpMaskedFusedMultiplyAddSub231Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float32x4(v) + case OpMaskedFusedMultiplyAddSub231Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float32x8(v) + case OpMaskedFusedMultiplyAddSub231Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float64x2(v) + case OpMaskedFusedMultiplyAddSub231Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float64x4(v) + case OpMaskedFusedMultiplyAddSub231Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float64x8(v) + case OpMaskedFusedMultiplySub132Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplySub132Float32x16(v) + case OpMaskedFusedMultiplySub132Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySub132Float32x4(v) + case OpMaskedFusedMultiplySub132Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySub132Float32x8(v) + case OpMaskedFusedMultiplySub132Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplySub132Float64x2(v) + case OpMaskedFusedMultiplySub132Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySub132Float64x4(v) + case OpMaskedFusedMultiplySub132Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySub132Float64x8(v) + case OpMaskedFusedMultiplySub213Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplySub213Float32x16(v) + case OpMaskedFusedMultiplySub213Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySub213Float32x4(v) + case OpMaskedFusedMultiplySub213Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySub213Float32x8(v) + case OpMaskedFusedMultiplySub213Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplySub213Float64x2(v) + case OpMaskedFusedMultiplySub213Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySub213Float64x4(v) + case OpMaskedFusedMultiplySub213Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySub213Float64x8(v) + case OpMaskedFusedMultiplySub231Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplySub231Float32x16(v) + case OpMaskedFusedMultiplySub231Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySub231Float32x4(v) + case OpMaskedFusedMultiplySub231Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySub231Float32x8(v) + case OpMaskedFusedMultiplySub231Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplySub231Float64x2(v) + case OpMaskedFusedMultiplySub231Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySub231Float64x4(v) + case OpMaskedFusedMultiplySub231Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySub231Float64x8(v) + case OpMaskedFusedMultiplySubAdd132Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float32x16(v) + case OpMaskedFusedMultiplySubAdd132Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float32x4(v) + case OpMaskedFusedMultiplySubAdd132Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float32x8(v) + case OpMaskedFusedMultiplySubAdd132Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float64x2(v) + case OpMaskedFusedMultiplySubAdd132Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float64x4(v) + case OpMaskedFusedMultiplySubAdd132Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float64x8(v) + case OpMaskedFusedMultiplySubAdd213Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float32x16(v) + case OpMaskedFusedMultiplySubAdd213Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float32x4(v) + case OpMaskedFusedMultiplySubAdd213Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float32x8(v) + case OpMaskedFusedMultiplySubAdd213Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float64x2(v) + case OpMaskedFusedMultiplySubAdd213Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float64x4(v) + case OpMaskedFusedMultiplySubAdd213Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float64x8(v) + case OpMaskedFusedMultiplySubAdd231Float32x16: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float32x16(v) + case OpMaskedFusedMultiplySubAdd231Float32x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float32x4(v) + case OpMaskedFusedMultiplySubAdd231Float32x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float32x8(v) + case OpMaskedFusedMultiplySubAdd231Float64x2: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float64x2(v) + case OpMaskedFusedMultiplySubAdd231Float64x4: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float64x4(v) + case OpMaskedFusedMultiplySubAdd231Float64x8: + return rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float64x8(v) + case OpMaskedFusedNegativeMultiplyAdd132Float32x16: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float32x16(v) + case OpMaskedFusedNegativeMultiplyAdd132Float32x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float32x4(v) + case OpMaskedFusedNegativeMultiplyAdd132Float32x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float32x8(v) + case OpMaskedFusedNegativeMultiplyAdd132Float64x2: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float64x2(v) + case OpMaskedFusedNegativeMultiplyAdd132Float64x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float64x4(v) + case OpMaskedFusedNegativeMultiplyAdd132Float64x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float64x8(v) + case OpMaskedFusedNegativeMultiplyAdd213Float32x16: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float32x16(v) + case OpMaskedFusedNegativeMultiplyAdd213Float32x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float32x4(v) + case OpMaskedFusedNegativeMultiplyAdd213Float32x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float32x8(v) + case OpMaskedFusedNegativeMultiplyAdd213Float64x2: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float64x2(v) + case OpMaskedFusedNegativeMultiplyAdd213Float64x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float64x4(v) + case OpMaskedFusedNegativeMultiplyAdd213Float64x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float64x8(v) + case OpMaskedFusedNegativeMultiplyAdd231Float32x16: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float32x16(v) + case OpMaskedFusedNegativeMultiplyAdd231Float32x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float32x4(v) + case OpMaskedFusedNegativeMultiplyAdd231Float32x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float32x8(v) + case OpMaskedFusedNegativeMultiplyAdd231Float64x2: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float64x2(v) + case OpMaskedFusedNegativeMultiplyAdd231Float64x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float64x4(v) + case OpMaskedFusedNegativeMultiplyAdd231Float64x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float64x8(v) + case OpMaskedFusedNegativeMultiplySub132Float32x16: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float32x16(v) + case OpMaskedFusedNegativeMultiplySub132Float32x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float32x4(v) + case OpMaskedFusedNegativeMultiplySub132Float32x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float32x8(v) + case OpMaskedFusedNegativeMultiplySub132Float64x2: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float64x2(v) + case OpMaskedFusedNegativeMultiplySub132Float64x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float64x4(v) + case OpMaskedFusedNegativeMultiplySub132Float64x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float64x8(v) + case OpMaskedFusedNegativeMultiplySub213Float32x16: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float32x16(v) + case OpMaskedFusedNegativeMultiplySub213Float32x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float32x4(v) + case OpMaskedFusedNegativeMultiplySub213Float32x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float32x8(v) + case OpMaskedFusedNegativeMultiplySub213Float64x2: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float64x2(v) + case OpMaskedFusedNegativeMultiplySub213Float64x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float64x4(v) + case OpMaskedFusedNegativeMultiplySub213Float64x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float64x8(v) + case OpMaskedFusedNegativeMultiplySub231Float32x16: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float32x16(v) + case OpMaskedFusedNegativeMultiplySub231Float32x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float32x4(v) + case OpMaskedFusedNegativeMultiplySub231Float32x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float32x8(v) + case OpMaskedFusedNegativeMultiplySub231Float64x2: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float64x2(v) + case OpMaskedFusedNegativeMultiplySub231Float64x4: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float64x4(v) + case OpMaskedFusedNegativeMultiplySub231Float64x8: + return rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float64x8(v) + case OpMaskedGreaterEqualFloat32x16: + return rewriteValueAMD64_OpMaskedGreaterEqualFloat32x16(v) + case OpMaskedGreaterEqualFloat32x4: + return rewriteValueAMD64_OpMaskedGreaterEqualFloat32x4(v) + case OpMaskedGreaterEqualFloat32x8: + return rewriteValueAMD64_OpMaskedGreaterEqualFloat32x8(v) + case OpMaskedGreaterEqualFloat64x2: + return rewriteValueAMD64_OpMaskedGreaterEqualFloat64x2(v) + case OpMaskedGreaterEqualFloat64x4: + return rewriteValueAMD64_OpMaskedGreaterEqualFloat64x4(v) + case OpMaskedGreaterEqualFloat64x8: + return rewriteValueAMD64_OpMaskedGreaterEqualFloat64x8(v) + case OpMaskedGreaterEqualInt16x16: + return rewriteValueAMD64_OpMaskedGreaterEqualInt16x16(v) + case OpMaskedGreaterEqualInt16x32: + return rewriteValueAMD64_OpMaskedGreaterEqualInt16x32(v) + case OpMaskedGreaterEqualInt16x8: + return rewriteValueAMD64_OpMaskedGreaterEqualInt16x8(v) + case OpMaskedGreaterEqualInt32x16: + return rewriteValueAMD64_OpMaskedGreaterEqualInt32x16(v) + case OpMaskedGreaterEqualInt32x4: + return rewriteValueAMD64_OpMaskedGreaterEqualInt32x4(v) + case OpMaskedGreaterEqualInt32x8: + return rewriteValueAMD64_OpMaskedGreaterEqualInt32x8(v) + case OpMaskedGreaterEqualInt64x2: + return rewriteValueAMD64_OpMaskedGreaterEqualInt64x2(v) + case OpMaskedGreaterEqualInt64x4: + return rewriteValueAMD64_OpMaskedGreaterEqualInt64x4(v) + case OpMaskedGreaterEqualInt64x8: + return rewriteValueAMD64_OpMaskedGreaterEqualInt64x8(v) + case OpMaskedGreaterEqualInt8x16: + return rewriteValueAMD64_OpMaskedGreaterEqualInt8x16(v) + case OpMaskedGreaterEqualInt8x32: + return rewriteValueAMD64_OpMaskedGreaterEqualInt8x32(v) + case OpMaskedGreaterEqualInt8x64: + return rewriteValueAMD64_OpMaskedGreaterEqualInt8x64(v) + case OpMaskedGreaterEqualUint16x16: + return rewriteValueAMD64_OpMaskedGreaterEqualUint16x16(v) + case OpMaskedGreaterEqualUint16x32: + return rewriteValueAMD64_OpMaskedGreaterEqualUint16x32(v) + case OpMaskedGreaterEqualUint16x8: + return rewriteValueAMD64_OpMaskedGreaterEqualUint16x8(v) + case OpMaskedGreaterEqualUint32x16: + return rewriteValueAMD64_OpMaskedGreaterEqualUint32x16(v) + case OpMaskedGreaterEqualUint32x4: + return rewriteValueAMD64_OpMaskedGreaterEqualUint32x4(v) + case OpMaskedGreaterEqualUint32x8: + return rewriteValueAMD64_OpMaskedGreaterEqualUint32x8(v) + case OpMaskedGreaterEqualUint64x2: + return rewriteValueAMD64_OpMaskedGreaterEqualUint64x2(v) + case OpMaskedGreaterEqualUint64x4: + return rewriteValueAMD64_OpMaskedGreaterEqualUint64x4(v) + case OpMaskedGreaterEqualUint64x8: + return rewriteValueAMD64_OpMaskedGreaterEqualUint64x8(v) + case OpMaskedGreaterEqualUint8x16: + return rewriteValueAMD64_OpMaskedGreaterEqualUint8x16(v) + case OpMaskedGreaterEqualUint8x32: + return rewriteValueAMD64_OpMaskedGreaterEqualUint8x32(v) + case OpMaskedGreaterEqualUint8x64: + return rewriteValueAMD64_OpMaskedGreaterEqualUint8x64(v) + case OpMaskedGreaterFloat32x16: + return rewriteValueAMD64_OpMaskedGreaterFloat32x16(v) + case OpMaskedGreaterFloat32x4: + return rewriteValueAMD64_OpMaskedGreaterFloat32x4(v) + case OpMaskedGreaterFloat32x8: + return rewriteValueAMD64_OpMaskedGreaterFloat32x8(v) + case OpMaskedGreaterFloat64x2: + return rewriteValueAMD64_OpMaskedGreaterFloat64x2(v) + case OpMaskedGreaterFloat64x4: + return rewriteValueAMD64_OpMaskedGreaterFloat64x4(v) + case OpMaskedGreaterFloat64x8: + return rewriteValueAMD64_OpMaskedGreaterFloat64x8(v) + case OpMaskedGreaterInt16x16: + return rewriteValueAMD64_OpMaskedGreaterInt16x16(v) + case OpMaskedGreaterInt16x32: + return rewriteValueAMD64_OpMaskedGreaterInt16x32(v) + case OpMaskedGreaterInt16x8: + return rewriteValueAMD64_OpMaskedGreaterInt16x8(v) + case OpMaskedGreaterInt32x16: + return rewriteValueAMD64_OpMaskedGreaterInt32x16(v) + case OpMaskedGreaterInt32x4: + return rewriteValueAMD64_OpMaskedGreaterInt32x4(v) + case OpMaskedGreaterInt32x8: + return rewriteValueAMD64_OpMaskedGreaterInt32x8(v) + case OpMaskedGreaterInt64x2: + return rewriteValueAMD64_OpMaskedGreaterInt64x2(v) + case OpMaskedGreaterInt64x4: + return rewriteValueAMD64_OpMaskedGreaterInt64x4(v) + case OpMaskedGreaterInt64x8: + return rewriteValueAMD64_OpMaskedGreaterInt64x8(v) + case OpMaskedGreaterInt8x16: + return rewriteValueAMD64_OpMaskedGreaterInt8x16(v) + case OpMaskedGreaterInt8x32: + return rewriteValueAMD64_OpMaskedGreaterInt8x32(v) + case OpMaskedGreaterInt8x64: + return rewriteValueAMD64_OpMaskedGreaterInt8x64(v) + case OpMaskedGreaterUint16x16: + return rewriteValueAMD64_OpMaskedGreaterUint16x16(v) + case OpMaskedGreaterUint16x32: + return rewriteValueAMD64_OpMaskedGreaterUint16x32(v) + case OpMaskedGreaterUint16x8: + return rewriteValueAMD64_OpMaskedGreaterUint16x8(v) + case OpMaskedGreaterUint32x16: + return rewriteValueAMD64_OpMaskedGreaterUint32x16(v) + case OpMaskedGreaterUint32x4: + return rewriteValueAMD64_OpMaskedGreaterUint32x4(v) + case OpMaskedGreaterUint32x8: + return rewriteValueAMD64_OpMaskedGreaterUint32x8(v) + case OpMaskedGreaterUint64x2: + return rewriteValueAMD64_OpMaskedGreaterUint64x2(v) + case OpMaskedGreaterUint64x4: + return rewriteValueAMD64_OpMaskedGreaterUint64x4(v) + case OpMaskedGreaterUint64x8: + return rewriteValueAMD64_OpMaskedGreaterUint64x8(v) + case OpMaskedGreaterUint8x16: + return rewriteValueAMD64_OpMaskedGreaterUint8x16(v) + case OpMaskedGreaterUint8x32: + return rewriteValueAMD64_OpMaskedGreaterUint8x32(v) + case OpMaskedGreaterUint8x64: + return rewriteValueAMD64_OpMaskedGreaterUint8x64(v) + case OpMaskedIsNanFloat32x16: + return rewriteValueAMD64_OpMaskedIsNanFloat32x16(v) + case OpMaskedIsNanFloat32x4: + return rewriteValueAMD64_OpMaskedIsNanFloat32x4(v) + case OpMaskedIsNanFloat32x8: + return rewriteValueAMD64_OpMaskedIsNanFloat32x8(v) + case OpMaskedIsNanFloat64x2: + return rewriteValueAMD64_OpMaskedIsNanFloat64x2(v) + case OpMaskedIsNanFloat64x4: + return rewriteValueAMD64_OpMaskedIsNanFloat64x4(v) + case OpMaskedIsNanFloat64x8: + return rewriteValueAMD64_OpMaskedIsNanFloat64x8(v) + case OpMaskedLessEqualFloat32x16: + return rewriteValueAMD64_OpMaskedLessEqualFloat32x16(v) + case OpMaskedLessEqualFloat32x4: + return rewriteValueAMD64_OpMaskedLessEqualFloat32x4(v) + case OpMaskedLessEqualFloat32x8: + return rewriteValueAMD64_OpMaskedLessEqualFloat32x8(v) + case OpMaskedLessEqualFloat64x2: + return rewriteValueAMD64_OpMaskedLessEqualFloat64x2(v) + case OpMaskedLessEqualFloat64x4: + return rewriteValueAMD64_OpMaskedLessEqualFloat64x4(v) + case OpMaskedLessEqualFloat64x8: + return rewriteValueAMD64_OpMaskedLessEqualFloat64x8(v) + case OpMaskedLessEqualInt16x16: + return rewriteValueAMD64_OpMaskedLessEqualInt16x16(v) + case OpMaskedLessEqualInt16x32: + return rewriteValueAMD64_OpMaskedLessEqualInt16x32(v) + case OpMaskedLessEqualInt16x8: + return rewriteValueAMD64_OpMaskedLessEqualInt16x8(v) + case OpMaskedLessEqualInt32x16: + return rewriteValueAMD64_OpMaskedLessEqualInt32x16(v) + case OpMaskedLessEqualInt32x4: + return rewriteValueAMD64_OpMaskedLessEqualInt32x4(v) + case OpMaskedLessEqualInt32x8: + return rewriteValueAMD64_OpMaskedLessEqualInt32x8(v) + case OpMaskedLessEqualInt64x2: + return rewriteValueAMD64_OpMaskedLessEqualInt64x2(v) + case OpMaskedLessEqualInt64x4: + return rewriteValueAMD64_OpMaskedLessEqualInt64x4(v) + case OpMaskedLessEqualInt64x8: + return rewriteValueAMD64_OpMaskedLessEqualInt64x8(v) + case OpMaskedLessEqualInt8x16: + return rewriteValueAMD64_OpMaskedLessEqualInt8x16(v) + case OpMaskedLessEqualInt8x32: + return rewriteValueAMD64_OpMaskedLessEqualInt8x32(v) + case OpMaskedLessEqualInt8x64: + return rewriteValueAMD64_OpMaskedLessEqualInt8x64(v) + case OpMaskedLessEqualUint16x16: + return rewriteValueAMD64_OpMaskedLessEqualUint16x16(v) + case OpMaskedLessEqualUint16x32: + return rewriteValueAMD64_OpMaskedLessEqualUint16x32(v) + case OpMaskedLessEqualUint16x8: + return rewriteValueAMD64_OpMaskedLessEqualUint16x8(v) + case OpMaskedLessEqualUint32x16: + return rewriteValueAMD64_OpMaskedLessEqualUint32x16(v) + case OpMaskedLessEqualUint32x4: + return rewriteValueAMD64_OpMaskedLessEqualUint32x4(v) + case OpMaskedLessEqualUint32x8: + return rewriteValueAMD64_OpMaskedLessEqualUint32x8(v) + case OpMaskedLessEqualUint64x2: + return rewriteValueAMD64_OpMaskedLessEqualUint64x2(v) + case OpMaskedLessEqualUint64x4: + return rewriteValueAMD64_OpMaskedLessEqualUint64x4(v) + case OpMaskedLessEqualUint64x8: + return rewriteValueAMD64_OpMaskedLessEqualUint64x8(v) + case OpMaskedLessEqualUint8x16: + return rewriteValueAMD64_OpMaskedLessEqualUint8x16(v) + case OpMaskedLessEqualUint8x32: + return rewriteValueAMD64_OpMaskedLessEqualUint8x32(v) + case OpMaskedLessEqualUint8x64: + return rewriteValueAMD64_OpMaskedLessEqualUint8x64(v) + case OpMaskedLessFloat32x16: + return rewriteValueAMD64_OpMaskedLessFloat32x16(v) + case OpMaskedLessFloat32x4: + return rewriteValueAMD64_OpMaskedLessFloat32x4(v) + case OpMaskedLessFloat32x8: + return rewriteValueAMD64_OpMaskedLessFloat32x8(v) + case OpMaskedLessFloat64x2: + return rewriteValueAMD64_OpMaskedLessFloat64x2(v) + case OpMaskedLessFloat64x4: + return rewriteValueAMD64_OpMaskedLessFloat64x4(v) + case OpMaskedLessFloat64x8: + return rewriteValueAMD64_OpMaskedLessFloat64x8(v) + case OpMaskedLessInt16x16: + return rewriteValueAMD64_OpMaskedLessInt16x16(v) + case OpMaskedLessInt16x32: + return rewriteValueAMD64_OpMaskedLessInt16x32(v) + case OpMaskedLessInt16x8: + return rewriteValueAMD64_OpMaskedLessInt16x8(v) + case OpMaskedLessInt32x16: + return rewriteValueAMD64_OpMaskedLessInt32x16(v) + case OpMaskedLessInt32x4: + return rewriteValueAMD64_OpMaskedLessInt32x4(v) + case OpMaskedLessInt32x8: + return rewriteValueAMD64_OpMaskedLessInt32x8(v) + case OpMaskedLessInt64x2: + return rewriteValueAMD64_OpMaskedLessInt64x2(v) + case OpMaskedLessInt64x4: + return rewriteValueAMD64_OpMaskedLessInt64x4(v) + case OpMaskedLessInt64x8: + return rewriteValueAMD64_OpMaskedLessInt64x8(v) + case OpMaskedLessInt8x16: + return rewriteValueAMD64_OpMaskedLessInt8x16(v) + case OpMaskedLessInt8x32: + return rewriteValueAMD64_OpMaskedLessInt8x32(v) + case OpMaskedLessInt8x64: + return rewriteValueAMD64_OpMaskedLessInt8x64(v) + case OpMaskedLessUint16x16: + return rewriteValueAMD64_OpMaskedLessUint16x16(v) + case OpMaskedLessUint16x32: + return rewriteValueAMD64_OpMaskedLessUint16x32(v) + case OpMaskedLessUint16x8: + return rewriteValueAMD64_OpMaskedLessUint16x8(v) + case OpMaskedLessUint32x16: + return rewriteValueAMD64_OpMaskedLessUint32x16(v) + case OpMaskedLessUint32x4: + return rewriteValueAMD64_OpMaskedLessUint32x4(v) + case OpMaskedLessUint32x8: + return rewriteValueAMD64_OpMaskedLessUint32x8(v) + case OpMaskedLessUint64x2: + return rewriteValueAMD64_OpMaskedLessUint64x2(v) + case OpMaskedLessUint64x4: + return rewriteValueAMD64_OpMaskedLessUint64x4(v) + case OpMaskedLessUint64x8: + return rewriteValueAMD64_OpMaskedLessUint64x8(v) + case OpMaskedLessUint8x16: + return rewriteValueAMD64_OpMaskedLessUint8x16(v) + case OpMaskedLessUint8x32: + return rewriteValueAMD64_OpMaskedLessUint8x32(v) + case OpMaskedLessUint8x64: + return rewriteValueAMD64_OpMaskedLessUint8x64(v) + case OpMaskedMaxFloat32x16: + return rewriteValueAMD64_OpMaskedMaxFloat32x16(v) + case OpMaskedMaxFloat32x4: + return rewriteValueAMD64_OpMaskedMaxFloat32x4(v) + case OpMaskedMaxFloat32x8: + return rewriteValueAMD64_OpMaskedMaxFloat32x8(v) + case OpMaskedMaxFloat64x2: + return rewriteValueAMD64_OpMaskedMaxFloat64x2(v) + case OpMaskedMaxFloat64x4: + return rewriteValueAMD64_OpMaskedMaxFloat64x4(v) + case OpMaskedMaxFloat64x8: + return rewriteValueAMD64_OpMaskedMaxFloat64x8(v) + case OpMaskedMaxInt16x16: + return rewriteValueAMD64_OpMaskedMaxInt16x16(v) + case OpMaskedMaxInt16x32: + return rewriteValueAMD64_OpMaskedMaxInt16x32(v) + case OpMaskedMaxInt16x8: + return rewriteValueAMD64_OpMaskedMaxInt16x8(v) + case OpMaskedMaxInt32x16: + return rewriteValueAMD64_OpMaskedMaxInt32x16(v) + case OpMaskedMaxInt32x4: + return rewriteValueAMD64_OpMaskedMaxInt32x4(v) + case OpMaskedMaxInt32x8: + return rewriteValueAMD64_OpMaskedMaxInt32x8(v) + case OpMaskedMaxInt64x2: + return rewriteValueAMD64_OpMaskedMaxInt64x2(v) + case OpMaskedMaxInt64x4: + return rewriteValueAMD64_OpMaskedMaxInt64x4(v) + case OpMaskedMaxInt64x8: + return rewriteValueAMD64_OpMaskedMaxInt64x8(v) + case OpMaskedMaxInt8x16: + return rewriteValueAMD64_OpMaskedMaxInt8x16(v) + case OpMaskedMaxInt8x32: + return rewriteValueAMD64_OpMaskedMaxInt8x32(v) + case OpMaskedMaxInt8x64: + return rewriteValueAMD64_OpMaskedMaxInt8x64(v) + case OpMaskedMaxUint16x16: + return rewriteValueAMD64_OpMaskedMaxUint16x16(v) + case OpMaskedMaxUint16x32: + return rewriteValueAMD64_OpMaskedMaxUint16x32(v) + case OpMaskedMaxUint16x8: + return rewriteValueAMD64_OpMaskedMaxUint16x8(v) + case OpMaskedMaxUint32x16: + return rewriteValueAMD64_OpMaskedMaxUint32x16(v) + case OpMaskedMaxUint32x4: + return rewriteValueAMD64_OpMaskedMaxUint32x4(v) + case OpMaskedMaxUint32x8: + return rewriteValueAMD64_OpMaskedMaxUint32x8(v) + case OpMaskedMaxUint64x2: + return rewriteValueAMD64_OpMaskedMaxUint64x2(v) + case OpMaskedMaxUint64x4: + return rewriteValueAMD64_OpMaskedMaxUint64x4(v) + case OpMaskedMaxUint64x8: + return rewriteValueAMD64_OpMaskedMaxUint64x8(v) + case OpMaskedMaxUint8x16: + return rewriteValueAMD64_OpMaskedMaxUint8x16(v) + case OpMaskedMaxUint8x32: + return rewriteValueAMD64_OpMaskedMaxUint8x32(v) + case OpMaskedMaxUint8x64: + return rewriteValueAMD64_OpMaskedMaxUint8x64(v) + case OpMaskedMinFloat32x16: + return rewriteValueAMD64_OpMaskedMinFloat32x16(v) + case OpMaskedMinFloat32x4: + return rewriteValueAMD64_OpMaskedMinFloat32x4(v) + case OpMaskedMinFloat32x8: + return rewriteValueAMD64_OpMaskedMinFloat32x8(v) + case OpMaskedMinFloat64x2: + return rewriteValueAMD64_OpMaskedMinFloat64x2(v) + case OpMaskedMinFloat64x4: + return rewriteValueAMD64_OpMaskedMinFloat64x4(v) + case OpMaskedMinFloat64x8: + return rewriteValueAMD64_OpMaskedMinFloat64x8(v) + case OpMaskedMinInt16x16: + return rewriteValueAMD64_OpMaskedMinInt16x16(v) + case OpMaskedMinInt16x32: + return rewriteValueAMD64_OpMaskedMinInt16x32(v) + case OpMaskedMinInt16x8: + return rewriteValueAMD64_OpMaskedMinInt16x8(v) + case OpMaskedMinInt32x16: + return rewriteValueAMD64_OpMaskedMinInt32x16(v) + case OpMaskedMinInt32x4: + return rewriteValueAMD64_OpMaskedMinInt32x4(v) + case OpMaskedMinInt32x8: + return rewriteValueAMD64_OpMaskedMinInt32x8(v) + case OpMaskedMinInt64x2: + return rewriteValueAMD64_OpMaskedMinInt64x2(v) + case OpMaskedMinInt64x4: + return rewriteValueAMD64_OpMaskedMinInt64x4(v) + case OpMaskedMinInt64x8: + return rewriteValueAMD64_OpMaskedMinInt64x8(v) + case OpMaskedMinInt8x16: + return rewriteValueAMD64_OpMaskedMinInt8x16(v) + case OpMaskedMinInt8x32: + return rewriteValueAMD64_OpMaskedMinInt8x32(v) + case OpMaskedMinInt8x64: + return rewriteValueAMD64_OpMaskedMinInt8x64(v) + case OpMaskedMinUint16x16: + return rewriteValueAMD64_OpMaskedMinUint16x16(v) + case OpMaskedMinUint16x32: + return rewriteValueAMD64_OpMaskedMinUint16x32(v) + case OpMaskedMinUint16x8: + return rewriteValueAMD64_OpMaskedMinUint16x8(v) + case OpMaskedMinUint32x16: + return rewriteValueAMD64_OpMaskedMinUint32x16(v) + case OpMaskedMinUint32x4: + return rewriteValueAMD64_OpMaskedMinUint32x4(v) + case OpMaskedMinUint32x8: + return rewriteValueAMD64_OpMaskedMinUint32x8(v) + case OpMaskedMinUint64x2: + return rewriteValueAMD64_OpMaskedMinUint64x2(v) + case OpMaskedMinUint64x4: + return rewriteValueAMD64_OpMaskedMinUint64x4(v) + case OpMaskedMinUint64x8: + return rewriteValueAMD64_OpMaskedMinUint64x8(v) + case OpMaskedMinUint8x16: + return rewriteValueAMD64_OpMaskedMinUint8x16(v) + case OpMaskedMinUint8x32: + return rewriteValueAMD64_OpMaskedMinUint8x32(v) + case OpMaskedMinUint8x64: + return rewriteValueAMD64_OpMaskedMinUint8x64(v) + case OpMaskedMulByPowOf2Float32x16: + return rewriteValueAMD64_OpMaskedMulByPowOf2Float32x16(v) + case OpMaskedMulByPowOf2Float32x4: + return rewriteValueAMD64_OpMaskedMulByPowOf2Float32x4(v) + case OpMaskedMulByPowOf2Float32x8: + return rewriteValueAMD64_OpMaskedMulByPowOf2Float32x8(v) + case OpMaskedMulByPowOf2Float64x2: + return rewriteValueAMD64_OpMaskedMulByPowOf2Float64x2(v) + case OpMaskedMulByPowOf2Float64x4: + return rewriteValueAMD64_OpMaskedMulByPowOf2Float64x4(v) + case OpMaskedMulByPowOf2Float64x8: + return rewriteValueAMD64_OpMaskedMulByPowOf2Float64x8(v) + case OpMaskedMulEvenWidenInt64x2: + return rewriteValueAMD64_OpMaskedMulEvenWidenInt64x2(v) + case OpMaskedMulEvenWidenInt64x4: + return rewriteValueAMD64_OpMaskedMulEvenWidenInt64x4(v) + case OpMaskedMulEvenWidenInt64x8: + return rewriteValueAMD64_OpMaskedMulEvenWidenInt64x8(v) + case OpMaskedMulEvenWidenUint64x2: + return rewriteValueAMD64_OpMaskedMulEvenWidenUint64x2(v) + case OpMaskedMulEvenWidenUint64x4: + return rewriteValueAMD64_OpMaskedMulEvenWidenUint64x4(v) + case OpMaskedMulEvenWidenUint64x8: + return rewriteValueAMD64_OpMaskedMulEvenWidenUint64x8(v) + case OpMaskedMulFloat32x16: + return rewriteValueAMD64_OpMaskedMulFloat32x16(v) + case OpMaskedMulFloat32x4: + return rewriteValueAMD64_OpMaskedMulFloat32x4(v) + case OpMaskedMulFloat32x8: + return rewriteValueAMD64_OpMaskedMulFloat32x8(v) + case OpMaskedMulFloat64x2: + return rewriteValueAMD64_OpMaskedMulFloat64x2(v) + case OpMaskedMulFloat64x4: + return rewriteValueAMD64_OpMaskedMulFloat64x4(v) + case OpMaskedMulFloat64x8: + return rewriteValueAMD64_OpMaskedMulFloat64x8(v) + case OpMaskedMulHighInt16x16: + return rewriteValueAMD64_OpMaskedMulHighInt16x16(v) + case OpMaskedMulHighInt16x32: + return rewriteValueAMD64_OpMaskedMulHighInt16x32(v) + case OpMaskedMulHighInt16x8: + return rewriteValueAMD64_OpMaskedMulHighInt16x8(v) + case OpMaskedMulHighUint16x16: + return rewriteValueAMD64_OpMaskedMulHighUint16x16(v) + case OpMaskedMulHighUint16x32: + return rewriteValueAMD64_OpMaskedMulHighUint16x32(v) + case OpMaskedMulHighUint16x8: + return rewriteValueAMD64_OpMaskedMulHighUint16x8(v) + case OpMaskedMulLowInt16x16: + return rewriteValueAMD64_OpMaskedMulLowInt16x16(v) + case OpMaskedMulLowInt16x32: + return rewriteValueAMD64_OpMaskedMulLowInt16x32(v) + case OpMaskedMulLowInt16x8: + return rewriteValueAMD64_OpMaskedMulLowInt16x8(v) + case OpMaskedMulLowInt32x16: + return rewriteValueAMD64_OpMaskedMulLowInt32x16(v) + case OpMaskedMulLowInt32x4: + return rewriteValueAMD64_OpMaskedMulLowInt32x4(v) + case OpMaskedMulLowInt32x8: + return rewriteValueAMD64_OpMaskedMulLowInt32x8(v) + case OpMaskedMulLowInt64x2: + return rewriteValueAMD64_OpMaskedMulLowInt64x2(v) + case OpMaskedMulLowInt64x4: + return rewriteValueAMD64_OpMaskedMulLowInt64x4(v) + case OpMaskedMulLowInt64x8: + return rewriteValueAMD64_OpMaskedMulLowInt64x8(v) + case OpMaskedNotEqualFloat32x16: + return rewriteValueAMD64_OpMaskedNotEqualFloat32x16(v) + case OpMaskedNotEqualFloat32x4: + return rewriteValueAMD64_OpMaskedNotEqualFloat32x4(v) + case OpMaskedNotEqualFloat32x8: + return rewriteValueAMD64_OpMaskedNotEqualFloat32x8(v) + case OpMaskedNotEqualFloat64x2: + return rewriteValueAMD64_OpMaskedNotEqualFloat64x2(v) + case OpMaskedNotEqualFloat64x4: + return rewriteValueAMD64_OpMaskedNotEqualFloat64x4(v) + case OpMaskedNotEqualFloat64x8: + return rewriteValueAMD64_OpMaskedNotEqualFloat64x8(v) + case OpMaskedNotEqualInt16x16: + return rewriteValueAMD64_OpMaskedNotEqualInt16x16(v) + case OpMaskedNotEqualInt16x32: + return rewriteValueAMD64_OpMaskedNotEqualInt16x32(v) + case OpMaskedNotEqualInt16x8: + return rewriteValueAMD64_OpMaskedNotEqualInt16x8(v) + case OpMaskedNotEqualInt32x16: + return rewriteValueAMD64_OpMaskedNotEqualInt32x16(v) + case OpMaskedNotEqualInt32x4: + return rewriteValueAMD64_OpMaskedNotEqualInt32x4(v) + case OpMaskedNotEqualInt32x8: + return rewriteValueAMD64_OpMaskedNotEqualInt32x8(v) + case OpMaskedNotEqualInt64x2: + return rewriteValueAMD64_OpMaskedNotEqualInt64x2(v) + case OpMaskedNotEqualInt64x4: + return rewriteValueAMD64_OpMaskedNotEqualInt64x4(v) + case OpMaskedNotEqualInt64x8: + return rewriteValueAMD64_OpMaskedNotEqualInt64x8(v) + case OpMaskedNotEqualInt8x16: + return rewriteValueAMD64_OpMaskedNotEqualInt8x16(v) + case OpMaskedNotEqualInt8x32: + return rewriteValueAMD64_OpMaskedNotEqualInt8x32(v) + case OpMaskedNotEqualInt8x64: + return rewriteValueAMD64_OpMaskedNotEqualInt8x64(v) + case OpMaskedNotEqualUint16x16: + return rewriteValueAMD64_OpMaskedNotEqualUint16x16(v) + case OpMaskedNotEqualUint16x32: + return rewriteValueAMD64_OpMaskedNotEqualUint16x32(v) + case OpMaskedNotEqualUint16x8: + return rewriteValueAMD64_OpMaskedNotEqualUint16x8(v) + case OpMaskedNotEqualUint32x16: + return rewriteValueAMD64_OpMaskedNotEqualUint32x16(v) + case OpMaskedNotEqualUint32x4: + return rewriteValueAMD64_OpMaskedNotEqualUint32x4(v) + case OpMaskedNotEqualUint32x8: + return rewriteValueAMD64_OpMaskedNotEqualUint32x8(v) + case OpMaskedNotEqualUint64x2: + return rewriteValueAMD64_OpMaskedNotEqualUint64x2(v) + case OpMaskedNotEqualUint64x4: + return rewriteValueAMD64_OpMaskedNotEqualUint64x4(v) + case OpMaskedNotEqualUint64x8: + return rewriteValueAMD64_OpMaskedNotEqualUint64x8(v) + case OpMaskedNotEqualUint8x16: + return rewriteValueAMD64_OpMaskedNotEqualUint8x16(v) + case OpMaskedNotEqualUint8x32: + return rewriteValueAMD64_OpMaskedNotEqualUint8x32(v) + case OpMaskedNotEqualUint8x64: + return rewriteValueAMD64_OpMaskedNotEqualUint8x64(v) + case OpMaskedOrFloat32x16: + return rewriteValueAMD64_OpMaskedOrFloat32x16(v) + case OpMaskedOrFloat32x4: + return rewriteValueAMD64_OpMaskedOrFloat32x4(v) + case OpMaskedOrFloat32x8: + return rewriteValueAMD64_OpMaskedOrFloat32x8(v) + case OpMaskedOrFloat64x2: + return rewriteValueAMD64_OpMaskedOrFloat64x2(v) + case OpMaskedOrFloat64x4: + return rewriteValueAMD64_OpMaskedOrFloat64x4(v) + case OpMaskedOrFloat64x8: + return rewriteValueAMD64_OpMaskedOrFloat64x8(v) + case OpMaskedOrInt32x16: + return rewriteValueAMD64_OpMaskedOrInt32x16(v) + case OpMaskedOrInt32x4: + return rewriteValueAMD64_OpMaskedOrInt32x4(v) + case OpMaskedOrInt32x8: + return rewriteValueAMD64_OpMaskedOrInt32x8(v) + case OpMaskedOrInt64x2: + return rewriteValueAMD64_OpMaskedOrInt64x2(v) + case OpMaskedOrInt64x4: + return rewriteValueAMD64_OpMaskedOrInt64x4(v) + case OpMaskedOrInt64x8: + return rewriteValueAMD64_OpMaskedOrInt64x8(v) + case OpMaskedOrUint32x16: + return rewriteValueAMD64_OpMaskedOrUint32x16(v) + case OpMaskedOrUint32x4: + return rewriteValueAMD64_OpMaskedOrUint32x4(v) + case OpMaskedOrUint32x8: + return rewriteValueAMD64_OpMaskedOrUint32x8(v) + case OpMaskedOrUint64x2: + return rewriteValueAMD64_OpMaskedOrUint64x2(v) + case OpMaskedOrUint64x4: + return rewriteValueAMD64_OpMaskedOrUint64x4(v) + case OpMaskedOrUint64x8: + return rewriteValueAMD64_OpMaskedOrUint64x8(v) + case OpMaskedPairDotProdAccumulateInt32x16: + return rewriteValueAMD64_OpMaskedPairDotProdAccumulateInt32x16(v) + case OpMaskedPairDotProdAccumulateInt32x4: + return rewriteValueAMD64_OpMaskedPairDotProdAccumulateInt32x4(v) + case OpMaskedPairDotProdAccumulateInt32x8: + return rewriteValueAMD64_OpMaskedPairDotProdAccumulateInt32x8(v) + case OpMaskedPairDotProdInt16x16: + return rewriteValueAMD64_OpMaskedPairDotProdInt16x16(v) + case OpMaskedPairDotProdInt16x32: + return rewriteValueAMD64_OpMaskedPairDotProdInt16x32(v) + case OpMaskedPairDotProdInt16x8: + return rewriteValueAMD64_OpMaskedPairDotProdInt16x8(v) + case OpMaskedPopCountInt16x16: + return rewriteValueAMD64_OpMaskedPopCountInt16x16(v) + case OpMaskedPopCountInt16x32: + return rewriteValueAMD64_OpMaskedPopCountInt16x32(v) + case OpMaskedPopCountInt16x8: + return rewriteValueAMD64_OpMaskedPopCountInt16x8(v) + case OpMaskedPopCountInt32x16: + return rewriteValueAMD64_OpMaskedPopCountInt32x16(v) + case OpMaskedPopCountInt32x4: + return rewriteValueAMD64_OpMaskedPopCountInt32x4(v) + case OpMaskedPopCountInt32x8: + return rewriteValueAMD64_OpMaskedPopCountInt32x8(v) + case OpMaskedPopCountInt64x2: + return rewriteValueAMD64_OpMaskedPopCountInt64x2(v) + case OpMaskedPopCountInt64x4: + return rewriteValueAMD64_OpMaskedPopCountInt64x4(v) + case OpMaskedPopCountInt64x8: + return rewriteValueAMD64_OpMaskedPopCountInt64x8(v) + case OpMaskedPopCountInt8x16: + return rewriteValueAMD64_OpMaskedPopCountInt8x16(v) + case OpMaskedPopCountInt8x32: + return rewriteValueAMD64_OpMaskedPopCountInt8x32(v) + case OpMaskedPopCountInt8x64: + return rewriteValueAMD64_OpMaskedPopCountInt8x64(v) + case OpMaskedPopCountUint16x16: + return rewriteValueAMD64_OpMaskedPopCountUint16x16(v) + case OpMaskedPopCountUint16x32: + return rewriteValueAMD64_OpMaskedPopCountUint16x32(v) + case OpMaskedPopCountUint16x8: + return rewriteValueAMD64_OpMaskedPopCountUint16x8(v) + case OpMaskedPopCountUint32x16: + return rewriteValueAMD64_OpMaskedPopCountUint32x16(v) + case OpMaskedPopCountUint32x4: + return rewriteValueAMD64_OpMaskedPopCountUint32x4(v) + case OpMaskedPopCountUint32x8: + return rewriteValueAMD64_OpMaskedPopCountUint32x8(v) + case OpMaskedPopCountUint64x2: + return rewriteValueAMD64_OpMaskedPopCountUint64x2(v) + case OpMaskedPopCountUint64x4: + return rewriteValueAMD64_OpMaskedPopCountUint64x4(v) + case OpMaskedPopCountUint64x8: + return rewriteValueAMD64_OpMaskedPopCountUint64x8(v) + case OpMaskedPopCountUint8x16: + return rewriteValueAMD64_OpMaskedPopCountUint8x16(v) + case OpMaskedPopCountUint8x32: + return rewriteValueAMD64_OpMaskedPopCountUint8x32(v) + case OpMaskedPopCountUint8x64: + return rewriteValueAMD64_OpMaskedPopCountUint8x64(v) + case OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedRoundWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x16(v) + case OpMaskedRoundWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x4(v) + case OpMaskedRoundWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x8(v) + case OpMaskedRoundWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x2(v) + case OpMaskedRoundWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x4(v) + case OpMaskedRoundWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x8(v) + case OpMaskedSaturatedAddInt16x16: + return rewriteValueAMD64_OpMaskedSaturatedAddInt16x16(v) + case OpMaskedSaturatedAddInt16x32: + return rewriteValueAMD64_OpMaskedSaturatedAddInt16x32(v) + case OpMaskedSaturatedAddInt16x8: + return rewriteValueAMD64_OpMaskedSaturatedAddInt16x8(v) + case OpMaskedSaturatedAddInt8x16: + return rewriteValueAMD64_OpMaskedSaturatedAddInt8x16(v) + case OpMaskedSaturatedAddInt8x32: + return rewriteValueAMD64_OpMaskedSaturatedAddInt8x32(v) + case OpMaskedSaturatedAddInt8x64: + return rewriteValueAMD64_OpMaskedSaturatedAddInt8x64(v) + case OpMaskedSaturatedAddUint16x16: + return rewriteValueAMD64_OpMaskedSaturatedAddUint16x16(v) + case OpMaskedSaturatedAddUint16x32: + return rewriteValueAMD64_OpMaskedSaturatedAddUint16x32(v) + case OpMaskedSaturatedAddUint16x8: + return rewriteValueAMD64_OpMaskedSaturatedAddUint16x8(v) + case OpMaskedSaturatedAddUint8x16: + return rewriteValueAMD64_OpMaskedSaturatedAddUint8x16(v) + case OpMaskedSaturatedAddUint8x32: + return rewriteValueAMD64_OpMaskedSaturatedAddUint8x32(v) + case OpMaskedSaturatedAddUint8x64: + return rewriteValueAMD64_OpMaskedSaturatedAddUint8x64(v) + case OpMaskedSaturatedPairDotProdAccumulateInt32x16: + return rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x16(v) + case OpMaskedSaturatedPairDotProdAccumulateInt32x4: + return rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x4(v) + case OpMaskedSaturatedPairDotProdAccumulateInt32x8: + return rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x8(v) + case OpMaskedSaturatedSubInt16x16: + return rewriteValueAMD64_OpMaskedSaturatedSubInt16x16(v) + case OpMaskedSaturatedSubInt16x32: + return rewriteValueAMD64_OpMaskedSaturatedSubInt16x32(v) + case OpMaskedSaturatedSubInt16x8: + return rewriteValueAMD64_OpMaskedSaturatedSubInt16x8(v) + case OpMaskedSaturatedSubInt8x16: + return rewriteValueAMD64_OpMaskedSaturatedSubInt8x16(v) + case OpMaskedSaturatedSubInt8x32: + return rewriteValueAMD64_OpMaskedSaturatedSubInt8x32(v) + case OpMaskedSaturatedSubInt8x64: + return rewriteValueAMD64_OpMaskedSaturatedSubInt8x64(v) + case OpMaskedSaturatedSubUint16x16: + return rewriteValueAMD64_OpMaskedSaturatedSubUint16x16(v) + case OpMaskedSaturatedSubUint16x32: + return rewriteValueAMD64_OpMaskedSaturatedSubUint16x32(v) + case OpMaskedSaturatedSubUint16x8: + return rewriteValueAMD64_OpMaskedSaturatedSubUint16x8(v) + case OpMaskedSaturatedSubUint8x16: + return rewriteValueAMD64_OpMaskedSaturatedSubUint8x16(v) + case OpMaskedSaturatedSubUint8x32: + return rewriteValueAMD64_OpMaskedSaturatedSubUint8x32(v) + case OpMaskedSaturatedSubUint8x64: + return rewriteValueAMD64_OpMaskedSaturatedSubUint8x64(v) + case OpMaskedSaturatedUnsignedSignedPairDotProdUint16x16: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint16x16(v) + case OpMaskedSaturatedUnsignedSignedPairDotProdUint16x32: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint16x32(v) + case OpMaskedSaturatedUnsignedSignedPairDotProdUint16x8: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint16x8(v) + case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16(v) + case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4(v) + case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8(v) + case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16(v) + case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4(v) + case OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8: + return rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8(v) + case OpMaskedSqrtFloat32x16: + return rewriteValueAMD64_OpMaskedSqrtFloat32x16(v) + case OpMaskedSqrtFloat32x4: + return rewriteValueAMD64_OpMaskedSqrtFloat32x4(v) + case OpMaskedSqrtFloat32x8: + return rewriteValueAMD64_OpMaskedSqrtFloat32x8(v) + case OpMaskedSqrtFloat64x2: + return rewriteValueAMD64_OpMaskedSqrtFloat64x2(v) + case OpMaskedSqrtFloat64x4: + return rewriteValueAMD64_OpMaskedSqrtFloat64x4(v) + case OpMaskedSqrtFloat64x8: + return rewriteValueAMD64_OpMaskedSqrtFloat64x8(v) + case OpMaskedSubFloat32x16: + return rewriteValueAMD64_OpMaskedSubFloat32x16(v) + case OpMaskedSubFloat32x4: + return rewriteValueAMD64_OpMaskedSubFloat32x4(v) + case OpMaskedSubFloat32x8: + return rewriteValueAMD64_OpMaskedSubFloat32x8(v) + case OpMaskedSubFloat64x2: + return rewriteValueAMD64_OpMaskedSubFloat64x2(v) + case OpMaskedSubFloat64x4: + return rewriteValueAMD64_OpMaskedSubFloat64x4(v) + case OpMaskedSubFloat64x8: + return rewriteValueAMD64_OpMaskedSubFloat64x8(v) + case OpMaskedSubInt16x16: + return rewriteValueAMD64_OpMaskedSubInt16x16(v) + case OpMaskedSubInt16x32: + return rewriteValueAMD64_OpMaskedSubInt16x32(v) + case OpMaskedSubInt16x8: + return rewriteValueAMD64_OpMaskedSubInt16x8(v) + case OpMaskedSubInt32x16: + return rewriteValueAMD64_OpMaskedSubInt32x16(v) + case OpMaskedSubInt32x4: + return rewriteValueAMD64_OpMaskedSubInt32x4(v) + case OpMaskedSubInt32x8: + return rewriteValueAMD64_OpMaskedSubInt32x8(v) + case OpMaskedSubInt64x2: + return rewriteValueAMD64_OpMaskedSubInt64x2(v) + case OpMaskedSubInt64x4: + return rewriteValueAMD64_OpMaskedSubInt64x4(v) + case OpMaskedSubInt64x8: + return rewriteValueAMD64_OpMaskedSubInt64x8(v) + case OpMaskedSubInt8x16: + return rewriteValueAMD64_OpMaskedSubInt8x16(v) + case OpMaskedSubInt8x32: + return rewriteValueAMD64_OpMaskedSubInt8x32(v) + case OpMaskedSubInt8x64: + return rewriteValueAMD64_OpMaskedSubInt8x64(v) + case OpMaskedSubUint16x16: + return rewriteValueAMD64_OpMaskedSubUint16x16(v) + case OpMaskedSubUint16x32: + return rewriteValueAMD64_OpMaskedSubUint16x32(v) + case OpMaskedSubUint16x8: + return rewriteValueAMD64_OpMaskedSubUint16x8(v) + case OpMaskedSubUint32x16: + return rewriteValueAMD64_OpMaskedSubUint32x16(v) + case OpMaskedSubUint32x4: + return rewriteValueAMD64_OpMaskedSubUint32x4(v) + case OpMaskedSubUint32x8: + return rewriteValueAMD64_OpMaskedSubUint32x8(v) + case OpMaskedSubUint64x2: + return rewriteValueAMD64_OpMaskedSubUint64x2(v) + case OpMaskedSubUint64x4: + return rewriteValueAMD64_OpMaskedSubUint64x4(v) + case OpMaskedSubUint64x8: + return rewriteValueAMD64_OpMaskedSubUint64x8(v) + case OpMaskedSubUint8x16: + return rewriteValueAMD64_OpMaskedSubUint8x16(v) + case OpMaskedSubUint8x32: + return rewriteValueAMD64_OpMaskedSubUint8x32(v) + case OpMaskedSubUint8x64: + return rewriteValueAMD64_OpMaskedSubUint8x64(v) + case OpMaskedTruncSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat32x16(v) + case OpMaskedTruncSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat32x4(v) + case OpMaskedTruncSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat32x8(v) + case OpMaskedTruncSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat64x2(v) + case OpMaskedTruncSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat64x4(v) + case OpMaskedTruncSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat64x8(v) + case OpMaskedTruncWithPrecisionFloat32x16: + return rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat32x16(v) + case OpMaskedTruncWithPrecisionFloat32x4: + return rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat32x4(v) + case OpMaskedTruncWithPrecisionFloat32x8: + return rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat32x8(v) + case OpMaskedTruncWithPrecisionFloat64x2: + return rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat64x2(v) + case OpMaskedTruncWithPrecisionFloat64x4: + return rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat64x4(v) + case OpMaskedTruncWithPrecisionFloat64x8: + return rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat64x8(v) + case OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x16: + return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x16(v) + case OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x4: + return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x4(v) + case OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x8: + return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x8(v) + case OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x16: + return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x16(v) + case OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4: + return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4(v) + case OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8: + return rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8(v) + case OpMaskedXorFloat32x16: + return rewriteValueAMD64_OpMaskedXorFloat32x16(v) + case OpMaskedXorFloat32x4: + return rewriteValueAMD64_OpMaskedXorFloat32x4(v) + case OpMaskedXorFloat32x8: + return rewriteValueAMD64_OpMaskedXorFloat32x8(v) + case OpMaskedXorFloat64x2: + return rewriteValueAMD64_OpMaskedXorFloat64x2(v) + case OpMaskedXorFloat64x4: + return rewriteValueAMD64_OpMaskedXorFloat64x4(v) + case OpMaskedXorFloat64x8: + return rewriteValueAMD64_OpMaskedXorFloat64x8(v) + case OpMaskedXorInt32x16: + return rewriteValueAMD64_OpMaskedXorInt32x16(v) + case OpMaskedXorInt32x4: + return rewriteValueAMD64_OpMaskedXorInt32x4(v) + case OpMaskedXorInt32x8: + return rewriteValueAMD64_OpMaskedXorInt32x8(v) + case OpMaskedXorInt64x2: + return rewriteValueAMD64_OpMaskedXorInt64x2(v) + case OpMaskedXorInt64x4: + return rewriteValueAMD64_OpMaskedXorInt64x4(v) + case OpMaskedXorInt64x8: + return rewriteValueAMD64_OpMaskedXorInt64x8(v) + case OpMaskedXorUint32x16: + return rewriteValueAMD64_OpMaskedXorUint32x16(v) + case OpMaskedXorUint32x4: + return rewriteValueAMD64_OpMaskedXorUint32x4(v) + case OpMaskedXorUint32x8: + return rewriteValueAMD64_OpMaskedXorUint32x8(v) + case OpMaskedXorUint64x2: + return rewriteValueAMD64_OpMaskedXorUint64x2(v) + case OpMaskedXorUint64x4: + return rewriteValueAMD64_OpMaskedXorUint64x4(v) + case OpMaskedXorUint64x8: + return rewriteValueAMD64_OpMaskedXorUint64x8(v) case OpMax32F: return rewriteValueAMD64_OpMax32F(v) case OpMax64F: return rewriteValueAMD64_OpMax64F(v) + case OpMaxFloat32x16: + v.Op = OpAMD64VMAXPS512 + return true + case OpMaxFloat32x4: + v.Op = OpAMD64VMAXPS128 + return true + case OpMaxFloat32x8: + v.Op = OpAMD64VMAXPS256 + return true + case OpMaxFloat64x2: + v.Op = OpAMD64VMAXPD128 + return true + case OpMaxFloat64x4: + v.Op = OpAMD64VMAXPD256 + return true + case OpMaxFloat64x8: + v.Op = OpAMD64VMAXPD512 + return true + case OpMaxInt16x16: + v.Op = OpAMD64VPMAXSW256 + return true + case OpMaxInt16x32: + v.Op = OpAMD64VPMAXSW512 + return true + case OpMaxInt16x8: + v.Op = OpAMD64VPMAXSW128 + return true + case OpMaxInt32x16: + v.Op = OpAMD64VPMAXSD512 + return true + case OpMaxInt32x4: + v.Op = OpAMD64VPMAXSD128 + return true + case OpMaxInt32x8: + v.Op = OpAMD64VPMAXSD256 + return true + case OpMaxInt64x2: + v.Op = OpAMD64VPMAXSQ128 + return true + case OpMaxInt64x4: + v.Op = OpAMD64VPMAXSQ256 + return true + case OpMaxInt64x8: + v.Op = OpAMD64VPMAXSQ512 + return true + case OpMaxInt8x16: + v.Op = OpAMD64VPMAXSB128 + return true + case OpMaxInt8x32: + v.Op = OpAMD64VPMAXSB256 + return true + case OpMaxInt8x64: + v.Op = OpAMD64VPMAXSB512 + return true + case OpMaxUint16x16: + v.Op = OpAMD64VPMAXUW256 + return true + case OpMaxUint16x32: + v.Op = OpAMD64VPMAXUW512 + return true + case OpMaxUint16x8: + v.Op = OpAMD64VPMAXUW128 + return true + case OpMaxUint32x16: + v.Op = OpAMD64VPMAXUD512 + return true + case OpMaxUint32x4: + v.Op = OpAMD64VPMAXUD128 + return true + case OpMaxUint32x8: + v.Op = OpAMD64VPMAXUD256 + return true + case OpMaxUint64x2: + v.Op = OpAMD64VPMAXUQ128 + return true + case OpMaxUint64x4: + v.Op = OpAMD64VPMAXUQ256 + return true + case OpMaxUint64x8: + v.Op = OpAMD64VPMAXUQ512 + return true + case OpMaxUint8x16: + v.Op = OpAMD64VPMAXUB128 + return true + case OpMaxUint8x32: + v.Op = OpAMD64VPMAXUB256 + return true + case OpMaxUint8x64: + v.Op = OpAMD64VPMAXUB512 + return true case OpMin32F: return rewriteValueAMD64_OpMin32F(v) case OpMin64F: return rewriteValueAMD64_OpMin64F(v) + case OpMinFloat32x16: + v.Op = OpAMD64VMINPS512 + return true + case OpMinFloat32x4: + v.Op = OpAMD64VMINPS128 + return true + case OpMinFloat32x8: + v.Op = OpAMD64VMINPS256 + return true + case OpMinFloat64x2: + v.Op = OpAMD64VMINPD128 + return true + case OpMinFloat64x4: + v.Op = OpAMD64VMINPD256 + return true + case OpMinFloat64x8: + v.Op = OpAMD64VMINPD512 + return true + case OpMinInt16x16: + v.Op = OpAMD64VPMINSW256 + return true + case OpMinInt16x32: + v.Op = OpAMD64VPMINSW512 + return true + case OpMinInt16x8: + v.Op = OpAMD64VPMINSW128 + return true + case OpMinInt32x16: + v.Op = OpAMD64VPMINSD512 + return true + case OpMinInt32x4: + v.Op = OpAMD64VPMINSD128 + return true + case OpMinInt32x8: + v.Op = OpAMD64VPMINSD256 + return true + case OpMinInt64x2: + v.Op = OpAMD64VPMINSQ128 + return true + case OpMinInt64x4: + v.Op = OpAMD64VPMINSQ256 + return true + case OpMinInt64x8: + v.Op = OpAMD64VPMINSQ512 + return true + case OpMinInt8x16: + v.Op = OpAMD64VPMINSB128 + return true + case OpMinInt8x32: + v.Op = OpAMD64VPMINSB256 + return true + case OpMinInt8x64: + v.Op = OpAMD64VPMINSB512 + return true + case OpMinUint16x16: + v.Op = OpAMD64VPMINUW256 + return true + case OpMinUint16x32: + v.Op = OpAMD64VPMINUW512 + return true + case OpMinUint16x8: + v.Op = OpAMD64VPMINUW128 + return true + case OpMinUint32x16: + v.Op = OpAMD64VPMINUD512 + return true + case OpMinUint32x4: + v.Op = OpAMD64VPMINUD128 + return true + case OpMinUint32x8: + v.Op = OpAMD64VPMINUD256 + return true + case OpMinUint64x2: + v.Op = OpAMD64VPMINUQ128 + return true + case OpMinUint64x4: + v.Op = OpAMD64VPMINUQ256 + return true + case OpMinUint64x8: + v.Op = OpAMD64VPMINUQ512 + return true + case OpMinUint8x16: + v.Op = OpAMD64VPMINUB128 + return true + case OpMinUint8x32: + v.Op = OpAMD64VPMINUB256 + return true + case OpMinUint8x64: + v.Op = OpAMD64VPMINUB512 + return true case OpMod16: return rewriteValueAMD64_OpMod16(v) case OpMod16u: @@ -922,6 +3763,117 @@ func rewriteValueAMD64(v *Value) bool { case OpMul8: v.Op = OpAMD64MULL return true + case OpMulByPowOf2Float32x16: + v.Op = OpAMD64VSCALEFPS512 + return true + case OpMulByPowOf2Float32x4: + v.Op = OpAMD64VSCALEFPS128 + return true + case OpMulByPowOf2Float32x8: + v.Op = OpAMD64VSCALEFPS256 + return true + case OpMulByPowOf2Float64x2: + v.Op = OpAMD64VSCALEFPD128 + return true + case OpMulByPowOf2Float64x4: + v.Op = OpAMD64VSCALEFPD256 + return true + case OpMulByPowOf2Float64x8: + v.Op = OpAMD64VSCALEFPD512 + return true + case OpMulEvenWidenInt32x4: + v.Op = OpAMD64VPMULDQ128 + return true + case OpMulEvenWidenInt32x8: + v.Op = OpAMD64VPMULDQ256 + return true + case OpMulEvenWidenInt64x2: + v.Op = OpAMD64VPMULDQ128 + return true + case OpMulEvenWidenInt64x4: + v.Op = OpAMD64VPMULDQ256 + return true + case OpMulEvenWidenInt64x8: + v.Op = OpAMD64VPMULDQ512 + return true + case OpMulEvenWidenUint32x4: + v.Op = OpAMD64VPMULUDQ128 + return true + case OpMulEvenWidenUint32x8: + v.Op = OpAMD64VPMULUDQ256 + return true + case OpMulEvenWidenUint64x2: + v.Op = OpAMD64VPMULUDQ128 + return true + case OpMulEvenWidenUint64x4: + v.Op = OpAMD64VPMULUDQ256 + return true + case OpMulEvenWidenUint64x8: + v.Op = OpAMD64VPMULUDQ512 + return true + case OpMulFloat32x16: + v.Op = OpAMD64VMULPS512 + return true + case OpMulFloat32x4: + v.Op = OpAMD64VMULPS128 + return true + case OpMulFloat32x8: + v.Op = OpAMD64VMULPS256 + return true + case OpMulFloat64x2: + v.Op = OpAMD64VMULPD128 + return true + case OpMulFloat64x4: + v.Op = OpAMD64VMULPD256 + return true + case OpMulFloat64x8: + v.Op = OpAMD64VMULPD512 + return true + case OpMulHighInt16x16: + v.Op = OpAMD64VPMULHW256 + return true + case OpMulHighInt16x32: + v.Op = OpAMD64VPMULHW512 + return true + case OpMulHighInt16x8: + v.Op = OpAMD64VPMULHW128 + return true + case OpMulHighUint16x16: + v.Op = OpAMD64VPMULHUW256 + return true + case OpMulHighUint16x32: + v.Op = OpAMD64VPMULHUW512 + return true + case OpMulHighUint16x8: + v.Op = OpAMD64VPMULHUW128 + return true + case OpMulLowInt16x16: + v.Op = OpAMD64VPMULLW256 + return true + case OpMulLowInt16x32: + v.Op = OpAMD64VPMULLW512 + return true + case OpMulLowInt16x8: + v.Op = OpAMD64VPMULLW128 + return true + case OpMulLowInt32x16: + v.Op = OpAMD64VPMULLD512 + return true + case OpMulLowInt32x4: + v.Op = OpAMD64VPMULLD128 + return true + case OpMulLowInt32x8: + v.Op = OpAMD64VPMULLD256 + return true + case OpMulLowInt64x2: + v.Op = OpAMD64VPMULLQ128 + return true + case OpMulLowInt64x4: + v.Op = OpAMD64VPMULLQ256 + return true + case OpMulLowInt64x8: + v.Op = OpAMD64VPMULLQ512 + return true case OpNeg16: v.Op = OpAMD64NEGL return true @@ -959,6 +3911,66 @@ func rewriteValueAMD64(v *Value) bool { return true case OpNot: return rewriteValueAMD64_OpNot(v) + case OpNotEqualFloat32x16: + return rewriteValueAMD64_OpNotEqualFloat32x16(v) + case OpNotEqualFloat32x4: + return rewriteValueAMD64_OpNotEqualFloat32x4(v) + case OpNotEqualFloat32x8: + return rewriteValueAMD64_OpNotEqualFloat32x8(v) + case OpNotEqualFloat64x2: + return rewriteValueAMD64_OpNotEqualFloat64x2(v) + case OpNotEqualFloat64x4: + return rewriteValueAMD64_OpNotEqualFloat64x4(v) + case OpNotEqualFloat64x8: + return rewriteValueAMD64_OpNotEqualFloat64x8(v) + case OpNotEqualInt16x16: + return rewriteValueAMD64_OpNotEqualInt16x16(v) + case OpNotEqualInt16x32: + return rewriteValueAMD64_OpNotEqualInt16x32(v) + case OpNotEqualInt16x8: + return rewriteValueAMD64_OpNotEqualInt16x8(v) + case OpNotEqualInt32x16: + return rewriteValueAMD64_OpNotEqualInt32x16(v) + case OpNotEqualInt32x4: + return rewriteValueAMD64_OpNotEqualInt32x4(v) + case OpNotEqualInt32x8: + return rewriteValueAMD64_OpNotEqualInt32x8(v) + case OpNotEqualInt64x2: + return rewriteValueAMD64_OpNotEqualInt64x2(v) + case OpNotEqualInt64x4: + return rewriteValueAMD64_OpNotEqualInt64x4(v) + case OpNotEqualInt64x8: + return rewriteValueAMD64_OpNotEqualInt64x8(v) + case OpNotEqualInt8x16: + return rewriteValueAMD64_OpNotEqualInt8x16(v) + case OpNotEqualInt8x32: + return rewriteValueAMD64_OpNotEqualInt8x32(v) + case OpNotEqualInt8x64: + return rewriteValueAMD64_OpNotEqualInt8x64(v) + case OpNotEqualUint16x16: + return rewriteValueAMD64_OpNotEqualUint16x16(v) + case OpNotEqualUint16x32: + return rewriteValueAMD64_OpNotEqualUint16x32(v) + case OpNotEqualUint16x8: + return rewriteValueAMD64_OpNotEqualUint16x8(v) + case OpNotEqualUint32x16: + return rewriteValueAMD64_OpNotEqualUint32x16(v) + case OpNotEqualUint32x4: + return rewriteValueAMD64_OpNotEqualUint32x4(v) + case OpNotEqualUint32x8: + return rewriteValueAMD64_OpNotEqualUint32x8(v) + case OpNotEqualUint64x2: + return rewriteValueAMD64_OpNotEqualUint64x2(v) + case OpNotEqualUint64x4: + return rewriteValueAMD64_OpNotEqualUint64x4(v) + case OpNotEqualUint64x8: + return rewriteValueAMD64_OpNotEqualUint64x8(v) + case OpNotEqualUint8x16: + return rewriteValueAMD64_OpNotEqualUint8x16(v) + case OpNotEqualUint8x32: + return rewriteValueAMD64_OpNotEqualUint8x32(v) + case OpNotEqualUint8x64: + return rewriteValueAMD64_OpNotEqualUint8x64(v) case OpOffPtr: return rewriteValueAMD64_OpOffPtr(v) case OpOr16: @@ -976,6 +3988,174 @@ func rewriteValueAMD64(v *Value) bool { case OpOrB: v.Op = OpAMD64ORL return true + case OpOrFloat32x16: + v.Op = OpAMD64VORPS512 + return true + case OpOrFloat32x4: + v.Op = OpAMD64VORPS128 + return true + case OpOrFloat32x8: + v.Op = OpAMD64VORPS256 + return true + case OpOrFloat64x2: + v.Op = OpAMD64VORPD128 + return true + case OpOrFloat64x4: + v.Op = OpAMD64VORPD256 + return true + case OpOrFloat64x8: + v.Op = OpAMD64VORPD512 + return true + case OpOrInt16x16: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt16x8: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt32x16: + v.Op = OpAMD64VPORD512 + return true + case OpOrInt32x4: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt32x8: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt64x2: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt64x4: + v.Op = OpAMD64VPOR256 + return true + case OpOrInt64x8: + v.Op = OpAMD64VPORQ512 + return true + case OpOrInt8x16: + v.Op = OpAMD64VPOR128 + return true + case OpOrInt8x32: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint16x16: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint16x8: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint32x16: + v.Op = OpAMD64VPORD512 + return true + case OpOrUint32x4: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint32x8: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint64x2: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint64x4: + v.Op = OpAMD64VPOR256 + return true + case OpOrUint64x8: + v.Op = OpAMD64VPORQ512 + return true + case OpOrUint8x16: + v.Op = OpAMD64VPOR128 + return true + case OpOrUint8x32: + v.Op = OpAMD64VPOR256 + return true + case OpPairDotProdAccumulateInt32x16: + v.Op = OpAMD64VPDPWSSD512 + return true + case OpPairDotProdAccumulateInt32x4: + v.Op = OpAMD64VPDPWSSD128 + return true + case OpPairDotProdAccumulateInt32x8: + v.Op = OpAMD64VPDPWSSD256 + return true + case OpPairDotProdInt16x16: + v.Op = OpAMD64VPMADDWD256 + return true + case OpPairDotProdInt16x32: + v.Op = OpAMD64VPMADDWD512 + return true + case OpPairDotProdInt16x8: + v.Op = OpAMD64VPMADDWD128 + return true + case OpPairwiseAddFloat32x4: + v.Op = OpAMD64VHADDPS128 + return true + case OpPairwiseAddFloat32x8: + v.Op = OpAMD64VHADDPS256 + return true + case OpPairwiseAddFloat64x2: + v.Op = OpAMD64VHADDPD128 + return true + case OpPairwiseAddFloat64x4: + v.Op = OpAMD64VHADDPD256 + return true + case OpPairwiseAddInt16x16: + v.Op = OpAMD64VPHADDW256 + return true + case OpPairwiseAddInt16x8: + v.Op = OpAMD64VPHADDW128 + return true + case OpPairwiseAddInt32x4: + v.Op = OpAMD64VPHADDD128 + return true + case OpPairwiseAddInt32x8: + v.Op = OpAMD64VPHADDD256 + return true + case OpPairwiseAddUint16x16: + v.Op = OpAMD64VPHADDW256 + return true + case OpPairwiseAddUint16x8: + v.Op = OpAMD64VPHADDW128 + return true + case OpPairwiseAddUint32x4: + v.Op = OpAMD64VPHADDD128 + return true + case OpPairwiseAddUint32x8: + v.Op = OpAMD64VPHADDD256 + return true + case OpPairwiseSubFloat32x4: + v.Op = OpAMD64VHSUBPS128 + return true + case OpPairwiseSubFloat32x8: + v.Op = OpAMD64VHSUBPS256 + return true + case OpPairwiseSubFloat64x2: + v.Op = OpAMD64VHSUBPD128 + return true + case OpPairwiseSubFloat64x4: + v.Op = OpAMD64VHSUBPD256 + return true + case OpPairwiseSubInt16x16: + v.Op = OpAMD64VPHSUBW256 + return true + case OpPairwiseSubInt16x8: + v.Op = OpAMD64VPHSUBW128 + return true + case OpPairwiseSubInt32x4: + v.Op = OpAMD64VPHSUBD128 + return true + case OpPairwiseSubInt32x8: + v.Op = OpAMD64VPHSUBD256 + return true + case OpPairwiseSubUint16x16: + v.Op = OpAMD64VPHSUBW256 + return true + case OpPairwiseSubUint16x8: + v.Op = OpAMD64VPHSUBW128 + return true + case OpPairwiseSubUint32x4: + v.Op = OpAMD64VPHSUBD128 + return true + case OpPairwiseSubUint32x8: + v.Op = OpAMD64VPHSUBD256 + return true case OpPanicBounds: return rewriteValueAMD64_OpPanicBounds(v) case OpPopCount16: @@ -988,6 +4168,78 @@ func rewriteValueAMD64(v *Value) bool { return true case OpPopCount8: return rewriteValueAMD64_OpPopCount8(v) + case OpPopCountInt16x16: + v.Op = OpAMD64VPOPCNTW256 + return true + case OpPopCountInt16x32: + v.Op = OpAMD64VPOPCNTW512 + return true + case OpPopCountInt16x8: + v.Op = OpAMD64VPOPCNTW128 + return true + case OpPopCountInt32x16: + v.Op = OpAMD64VPOPCNTD512 + return true + case OpPopCountInt32x4: + v.Op = OpAMD64VPOPCNTD128 + return true + case OpPopCountInt32x8: + v.Op = OpAMD64VPOPCNTD256 + return true + case OpPopCountInt64x2: + v.Op = OpAMD64VPOPCNTQ128 + return true + case OpPopCountInt64x4: + v.Op = OpAMD64VPOPCNTQ256 + return true + case OpPopCountInt64x8: + v.Op = OpAMD64VPOPCNTQ512 + return true + case OpPopCountInt8x16: + v.Op = OpAMD64VPOPCNTB128 + return true + case OpPopCountInt8x32: + v.Op = OpAMD64VPOPCNTB256 + return true + case OpPopCountInt8x64: + v.Op = OpAMD64VPOPCNTB512 + return true + case OpPopCountUint16x16: + v.Op = OpAMD64VPOPCNTW256 + return true + case OpPopCountUint16x32: + v.Op = OpAMD64VPOPCNTW512 + return true + case OpPopCountUint16x8: + v.Op = OpAMD64VPOPCNTW128 + return true + case OpPopCountUint32x16: + v.Op = OpAMD64VPOPCNTD512 + return true + case OpPopCountUint32x4: + v.Op = OpAMD64VPOPCNTD128 + return true + case OpPopCountUint32x8: + v.Op = OpAMD64VPOPCNTD256 + return true + case OpPopCountUint64x2: + v.Op = OpAMD64VPOPCNTQ128 + return true + case OpPopCountUint64x4: + v.Op = OpAMD64VPOPCNTQ256 + return true + case OpPopCountUint64x8: + v.Op = OpAMD64VPOPCNTQ512 + return true + case OpPopCountUint8x16: + v.Op = OpAMD64VPOPCNTB128 + return true + case OpPopCountUint8x32: + v.Op = OpAMD64VPOPCNTB256 + return true + case OpPopCountUint8x64: + v.Op = OpAMD64VPOPCNTB512 + return true case OpPrefetchCache: v.Op = OpAMD64PrefetchT0 return true @@ -1012,8 +4264,40 @@ func rewriteValueAMD64(v *Value) bool { case OpRound64F: v.Op = OpAMD64LoweredRound64F return true + case OpRoundFloat32x4: + return rewriteValueAMD64_OpRoundFloat32x4(v) + case OpRoundFloat32x8: + return rewriteValueAMD64_OpRoundFloat32x8(v) + case OpRoundFloat64x2: + return rewriteValueAMD64_OpRoundFloat64x2(v) + case OpRoundFloat64x4: + return rewriteValueAMD64_OpRoundFloat64x4(v) + case OpRoundSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat32x16(v) + case OpRoundSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat32x4(v) + case OpRoundSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat32x8(v) + case OpRoundSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat64x2(v) + case OpRoundSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat64x4(v) + case OpRoundSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat64x8(v) case OpRoundToEven: return rewriteValueAMD64_OpRoundToEven(v) + case OpRoundWithPrecisionFloat32x16: + return rewriteValueAMD64_OpRoundWithPrecisionFloat32x16(v) + case OpRoundWithPrecisionFloat32x4: + return rewriteValueAMD64_OpRoundWithPrecisionFloat32x4(v) + case OpRoundWithPrecisionFloat32x8: + return rewriteValueAMD64_OpRoundWithPrecisionFloat32x8(v) + case OpRoundWithPrecisionFloat64x2: + return rewriteValueAMD64_OpRoundWithPrecisionFloat64x2(v) + case OpRoundWithPrecisionFloat64x4: + return rewriteValueAMD64_OpRoundWithPrecisionFloat64x4(v) + case OpRoundWithPrecisionFloat64x8: + return rewriteValueAMD64_OpRoundWithPrecisionFloat64x8(v) case OpRsh16Ux16: return rewriteValueAMD64_OpRsh16Ux16(v) case OpRsh16Ux32: @@ -1078,6 +4362,132 @@ func rewriteValueAMD64(v *Value) bool { return rewriteValueAMD64_OpRsh8x64(v) case OpRsh8x8: return rewriteValueAMD64_OpRsh8x8(v) + case OpSaturatedAddInt16x16: + v.Op = OpAMD64VPADDSW256 + return true + case OpSaturatedAddInt16x32: + v.Op = OpAMD64VPADDSW512 + return true + case OpSaturatedAddInt16x8: + v.Op = OpAMD64VPADDSW128 + return true + case OpSaturatedAddInt8x16: + v.Op = OpAMD64VPADDSB128 + return true + case OpSaturatedAddInt8x32: + v.Op = OpAMD64VPADDSB256 + return true + case OpSaturatedAddInt8x64: + v.Op = OpAMD64VPADDSB512 + return true + case OpSaturatedAddUint16x16: + v.Op = OpAMD64VPADDSW256 + return true + case OpSaturatedAddUint16x32: + v.Op = OpAMD64VPADDSW512 + return true + case OpSaturatedAddUint16x8: + v.Op = OpAMD64VPADDSW128 + return true + case OpSaturatedAddUint8x16: + v.Op = OpAMD64VPADDSB128 + return true + case OpSaturatedAddUint8x32: + v.Op = OpAMD64VPADDSB256 + return true + case OpSaturatedAddUint8x64: + v.Op = OpAMD64VPADDSB512 + return true + case OpSaturatedPairDotProdAccumulateInt32x16: + v.Op = OpAMD64VPDPWSSDS512 + return true + case OpSaturatedPairDotProdAccumulateInt32x4: + v.Op = OpAMD64VPDPWSSDS128 + return true + case OpSaturatedPairDotProdAccumulateInt32x8: + v.Op = OpAMD64VPDPWSSDS256 + return true + case OpSaturatedPairwiseAddInt16x16: + v.Op = OpAMD64VPHADDSW256 + return true + case OpSaturatedPairwiseAddInt16x8: + v.Op = OpAMD64VPHADDSW128 + return true + case OpSaturatedPairwiseSubInt16x16: + v.Op = OpAMD64VPHSUBSW256 + return true + case OpSaturatedPairwiseSubInt16x8: + v.Op = OpAMD64VPHSUBSW128 + return true + case OpSaturatedSubInt16x16: + v.Op = OpAMD64VPSUBSW256 + return true + case OpSaturatedSubInt16x32: + v.Op = OpAMD64VPSUBSW512 + return true + case OpSaturatedSubInt16x8: + v.Op = OpAMD64VPSUBSW128 + return true + case OpSaturatedSubInt8x16: + v.Op = OpAMD64VPSUBSB128 + return true + case OpSaturatedSubInt8x32: + v.Op = OpAMD64VPSUBSB256 + return true + case OpSaturatedSubInt8x64: + v.Op = OpAMD64VPSUBSB512 + return true + case OpSaturatedSubUint16x16: + v.Op = OpAMD64VPSUBSW256 + return true + case OpSaturatedSubUint16x32: + v.Op = OpAMD64VPSUBSW512 + return true + case OpSaturatedSubUint16x8: + v.Op = OpAMD64VPSUBSW128 + return true + case OpSaturatedSubUint8x16: + v.Op = OpAMD64VPSUBSB128 + return true + case OpSaturatedSubUint8x32: + v.Op = OpAMD64VPSUBSB256 + return true + case OpSaturatedSubUint8x64: + v.Op = OpAMD64VPSUBSB512 + return true + case OpSaturatedUnsignedSignedPairDotProdUint16x16: + v.Op = OpAMD64VPMADDUBSW256 + return true + case OpSaturatedUnsignedSignedPairDotProdUint16x32: + v.Op = OpAMD64VPMADDUBSW512 + return true + case OpSaturatedUnsignedSignedPairDotProdUint16x8: + v.Op = OpAMD64VPMADDUBSW128 + return true + case OpSaturatedUnsignedSignedPairDotProdUint8x16: + v.Op = OpAMD64VPMADDUBSW128 + return true + case OpSaturatedUnsignedSignedPairDotProdUint8x32: + v.Op = OpAMD64VPMADDUBSW256 + return true + case OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16: + v.Op = OpAMD64VPDPBUSDS512 + return true + case OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4: + v.Op = OpAMD64VPDPBUSDS128 + return true + case OpSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8: + v.Op = OpAMD64VPDPBUSDS256 + return true + case OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16: + v.Op = OpAMD64VPDPBUSDS512 + return true + case OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4: + v.Op = OpAMD64VPDPBUSDS128 + return true + case OpSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8: + v.Op = OpAMD64VPDPBUSDS256 + return true case OpSelect0: return rewriteValueAMD64_OpSelect0(v) case OpSelect1: @@ -1102,6 +4512,24 @@ func rewriteValueAMD64(v *Value) bool { case OpSignExt8to64: v.Op = OpAMD64MOVBQSX return true + case OpSignInt16x16: + v.Op = OpAMD64VPSIGNW256 + return true + case OpSignInt16x8: + v.Op = OpAMD64VPSIGNW128 + return true + case OpSignInt32x4: + v.Op = OpAMD64VPSIGND128 + return true + case OpSignInt32x8: + v.Op = OpAMD64VPSIGND256 + return true + case OpSignInt8x16: + v.Op = OpAMD64VPSIGNB128 + return true + case OpSignInt8x32: + v.Op = OpAMD64VPSIGNB256 + return true case OpSlicemask: return rewriteValueAMD64_OpSlicemask(v) case OpSpectreIndex: @@ -1114,6 +4542,24 @@ func rewriteValueAMD64(v *Value) bool { case OpSqrt32: v.Op = OpAMD64SQRTSS return true + case OpSqrtFloat32x16: + v.Op = OpAMD64VSQRTPS512 + return true + case OpSqrtFloat32x4: + v.Op = OpAMD64VSQRTPS128 + return true + case OpSqrtFloat32x8: + v.Op = OpAMD64VSQRTPS256 + return true + case OpSqrtFloat64x2: + v.Op = OpAMD64VSQRTPD128 + return true + case OpSqrtFloat64x4: + v.Op = OpAMD64VSQRTPD256 + return true + case OpSqrtFloat64x8: + v.Op = OpAMD64VSQRTPD512 + return true case OpStaticCall: v.Op = OpAMD64CALLstatic return true @@ -1137,9 +4583,99 @@ func rewriteValueAMD64(v *Value) bool { case OpSub8: v.Op = OpAMD64SUBL return true + case OpSubFloat32x16: + v.Op = OpAMD64VADDPS512 + return true + case OpSubFloat32x4: + v.Op = OpAMD64VADDPS128 + return true + case OpSubFloat32x8: + v.Op = OpAMD64VADDPS256 + return true + case OpSubFloat64x2: + v.Op = OpAMD64VADDPD128 + return true + case OpSubFloat64x4: + v.Op = OpAMD64VADDPD256 + return true + case OpSubFloat64x8: + v.Op = OpAMD64VADDPD512 + return true + case OpSubInt16x16: + v.Op = OpAMD64VPSUBW256 + return true + case OpSubInt16x32: + v.Op = OpAMD64VPSUBW512 + return true + case OpSubInt16x8: + v.Op = OpAMD64VPSUBW128 + return true + case OpSubInt32x16: + v.Op = OpAMD64VPSUBD512 + return true + case OpSubInt32x4: + v.Op = OpAMD64VPSUBD128 + return true + case OpSubInt32x8: + v.Op = OpAMD64VPSUBD256 + return true + case OpSubInt64x2: + v.Op = OpAMD64VPSUBQ128 + return true + case OpSubInt64x4: + v.Op = OpAMD64VPSUBQ256 + return true + case OpSubInt64x8: + v.Op = OpAMD64VPSUBQ512 + return true + case OpSubInt8x16: + v.Op = OpAMD64VPSUBB128 + return true + case OpSubInt8x32: + v.Op = OpAMD64VPSUBB256 + return true + case OpSubInt8x64: + v.Op = OpAMD64VPSUBB512 + return true case OpSubPtr: v.Op = OpAMD64SUBQ return true + case OpSubUint16x16: + v.Op = OpAMD64VPSUBW256 + return true + case OpSubUint16x32: + v.Op = OpAMD64VPSUBW512 + return true + case OpSubUint16x8: + v.Op = OpAMD64VPSUBW128 + return true + case OpSubUint32x16: + v.Op = OpAMD64VPSUBD512 + return true + case OpSubUint32x4: + v.Op = OpAMD64VPSUBD128 + return true + case OpSubUint32x8: + v.Op = OpAMD64VPSUBD256 + return true + case OpSubUint64x2: + v.Op = OpAMD64VPSUBQ128 + return true + case OpSubUint64x4: + v.Op = OpAMD64VPSUBQ256 + return true + case OpSubUint64x8: + v.Op = OpAMD64VPSUBQ512 + return true + case OpSubUint8x16: + v.Op = OpAMD64VPSUBB128 + return true + case OpSubUint8x32: + v.Op = OpAMD64VPSUBB256 + return true + case OpSubUint8x64: + v.Op = OpAMD64VPSUBB512 + return true case OpTailCall: v.Op = OpAMD64CALLtail return true @@ -1163,6 +4699,56 @@ func rewriteValueAMD64(v *Value) bool { case OpTrunc64to8: v.Op = OpCopy return true + case OpTruncFloat32x4: + return rewriteValueAMD64_OpTruncFloat32x4(v) + case OpTruncFloat32x8: + return rewriteValueAMD64_OpTruncFloat32x8(v) + case OpTruncFloat64x2: + return rewriteValueAMD64_OpTruncFloat64x2(v) + case OpTruncFloat64x4: + return rewriteValueAMD64_OpTruncFloat64x4(v) + case OpTruncSuppressExceptionWithPrecisionFloat32x16: + return rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat32x16(v) + case OpTruncSuppressExceptionWithPrecisionFloat32x4: + return rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat32x4(v) + case OpTruncSuppressExceptionWithPrecisionFloat32x8: + return rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat32x8(v) + case OpTruncSuppressExceptionWithPrecisionFloat64x2: + return rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat64x2(v) + case OpTruncSuppressExceptionWithPrecisionFloat64x4: + return rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat64x4(v) + case OpTruncSuppressExceptionWithPrecisionFloat64x8: + return rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat64x8(v) + case OpTruncWithPrecisionFloat32x16: + return rewriteValueAMD64_OpTruncWithPrecisionFloat32x16(v) + case OpTruncWithPrecisionFloat32x4: + return rewriteValueAMD64_OpTruncWithPrecisionFloat32x4(v) + case OpTruncWithPrecisionFloat32x8: + return rewriteValueAMD64_OpTruncWithPrecisionFloat32x8(v) + case OpTruncWithPrecisionFloat64x2: + return rewriteValueAMD64_OpTruncWithPrecisionFloat64x2(v) + case OpTruncWithPrecisionFloat64x4: + return rewriteValueAMD64_OpTruncWithPrecisionFloat64x4(v) + case OpTruncWithPrecisionFloat64x8: + return rewriteValueAMD64_OpTruncWithPrecisionFloat64x8(v) + case OpUnsignedSignedQuadDotProdAccumulateInt32x16: + v.Op = OpAMD64VPDPBUSD512 + return true + case OpUnsignedSignedQuadDotProdAccumulateInt32x4: + v.Op = OpAMD64VPDPBUSD128 + return true + case OpUnsignedSignedQuadDotProdAccumulateInt32x8: + v.Op = OpAMD64VPDPBUSD256 + return true + case OpUnsignedSignedQuadDotProdAccumulateUint32x16: + v.Op = OpAMD64VPDPBUSD512 + return true + case OpUnsignedSignedQuadDotProdAccumulateUint32x4: + v.Op = OpAMD64VPDPBUSD128 + return true + case OpUnsignedSignedQuadDotProdAccumulateUint32x8: + v.Op = OpAMD64VPDPBUSD256 + return true case OpWB: v.Op = OpAMD64LoweredWB return true @@ -1178,32 +4764,112 @@ func rewriteValueAMD64(v *Value) bool { case OpXor8: v.Op = OpAMD64XORL return true - case OpZero: - return rewriteValueAMD64_OpZero(v) - case OpZeroExt16to32: - v.Op = OpAMD64MOVWQZX + case OpXorFloat32x16: + v.Op = OpAMD64VXORPS512 return true - case OpZeroExt16to64: - v.Op = OpAMD64MOVWQZX + case OpXorFloat32x4: + v.Op = OpAMD64VXORPS128 return true - case OpZeroExt32to64: - v.Op = OpAMD64MOVLQZX + case OpXorFloat32x8: + v.Op = OpAMD64VXORPS256 return true - case OpZeroExt8to16: - v.Op = OpAMD64MOVBQZX + case OpXorFloat64x2: + v.Op = OpAMD64VXORPD128 return true - case OpZeroExt8to32: - v.Op = OpAMD64MOVBQZX + case OpXorFloat64x4: + v.Op = OpAMD64VXORPD256 return true - case OpZeroExt8to64: - v.Op = OpAMD64MOVBQZX + case OpXorFloat64x8: + v.Op = OpAMD64VXORPD512 return true - } - return false -} -func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { - v_2 := v.Args[2] - v_1 := v.Args[1] + case OpXorInt16x16: + v.Op = OpAMD64VPXOR256 + return true + case OpXorInt16x8: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt32x16: + v.Op = OpAMD64VPXORD512 + return true + case OpXorInt32x4: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt32x8: + v.Op = OpAMD64VPXOR256 + return true + case OpXorInt64x2: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt64x4: + v.Op = OpAMD64VPXOR256 + return true + case OpXorInt64x8: + v.Op = OpAMD64VPXORQ512 + return true + case OpXorInt8x16: + v.Op = OpAMD64VPXOR128 + return true + case OpXorInt8x32: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint16x16: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint16x8: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint32x16: + v.Op = OpAMD64VPXORD512 + return true + case OpXorUint32x4: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint32x8: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint64x2: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint64x4: + v.Op = OpAMD64VPXOR256 + return true + case OpXorUint64x8: + v.Op = OpAMD64VPXORQ512 + return true + case OpXorUint8x16: + v.Op = OpAMD64VPXOR128 + return true + case OpXorUint8x32: + v.Op = OpAMD64VPXOR256 + return true + case OpZero: + return rewriteValueAMD64_OpZero(v) + case OpZeroExt16to32: + v.Op = OpAMD64MOVWQZX + return true + case OpZeroExt16to64: + v.Op = OpAMD64MOVWQZX + return true + case OpZeroExt32to64: + v.Op = OpAMD64MOVLQZX + return true + case OpZeroExt8to16: + v.Op = OpAMD64MOVBQZX + return true + case OpZeroExt8to32: + v.Op = OpAMD64MOVBQZX + return true + case OpZeroExt8to64: + v.Op = OpAMD64MOVBQZX + return true + case OpZeroSIMD: + return rewriteValueAMD64_OpZeroSIMD(v) + } + return false +} +func rewriteValueAMD64_OpAMD64ADCQ(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] v_0 := v.Args[0] // match: (ADCQ x (MOVQconst [c]) carry) // cond: is32Bit(c) @@ -22812,6 +26478,174 @@ func rewriteValueAMD64_OpAMD64TESTWconst(v *Value) bool { } return false } +func rewriteValueAMD64_OpAMD64VPMOVVec16x16ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec16x16ToM (VPMOVMToVec16x16 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec16x16 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec16x32ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec16x32ToM (VPMOVMToVec16x32 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec16x32 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec16x8ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec16x8ToM (VPMOVMToVec16x8 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec16x8 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec32x16ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec32x16ToM (VPMOVMToVec32x16 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec32x16 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec32x4ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec32x4ToM (VPMOVMToVec32x4 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec32x4 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec32x8ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec32x8ToM (VPMOVMToVec32x8 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec32x8 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec64x2ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec64x2ToM (VPMOVMToVec64x2 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec64x2 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec64x4ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec64x4ToM (VPMOVMToVec64x4 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec64x4 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec64x8ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec64x8ToM (VPMOVMToVec64x8 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec64x8 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec8x16ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec8x16ToM (VPMOVMToVec8x16 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec8x16 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec8x32ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec8x32ToM (VPMOVMToVec8x32 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec8x32 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} +func rewriteValueAMD64_OpAMD64VPMOVVec8x64ToM(v *Value) bool { + v_0 := v.Args[0] + // match: (VPMOVVec8x64ToM (VPMOVMToVec8x64 x)) + // result: x + for { + if v_0.Op != OpAMD64VPMOVMToVec8x64 { + break + } + x := v_0.Args[0] + v.copyOf(x) + return true + } + return false +} func rewriteValueAMD64_OpAMD64XADDLlock(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -24291,6 +28125,210 @@ func rewriteValueAMD64_OpCeil(v *Value) bool { return true } } +func rewriteValueAMD64_OpCeilFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat32x4 x) + // result: (VROUNDPS128 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat32x8 x) + // result: (VROUNDPS256 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat64x2 x) + // result: (VROUNDPD128 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilFloat64x4 x) + // result: (VROUNDPD256 [2] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = int8ToAuxInt(2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpCeilWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (CeilWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} func rewriteValueAMD64_OpCondSelect(v *Value) bool { v_2 := v.Args[2] v_1 := v.Args[1] @@ -25424,6 +29462,630 @@ func rewriteValueAMD64_OpCtz8NonZero(v *Value) bool { } return false } +func rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+10] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 10) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithCeilWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithCeilWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+2] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 2) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+9] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+9] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+9] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+9] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+9] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+9] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithFloorWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithFloorWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithRoundWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithRoundWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncWithPrecisionFloat32x16 [a] x) + // result: (VREDUCEPS512 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS512) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncWithPrecisionFloat32x4 [a] x) + // result: (VREDUCEPS128 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS128) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncWithPrecisionFloat32x8 [a] x) + // result: (VREDUCEPS256 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPS256) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncWithPrecisionFloat64x2 [a] x) + // result: (VREDUCEPD128 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD128) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncWithPrecisionFloat64x4 [a] x) + // result: (VREDUCEPD256 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD256) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpDiffWithTruncWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (DiffWithTruncWithPrecisionFloat64x8 [a] x) + // result: (VREDUCEPD512 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VREDUCEPD512) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} func rewriteValueAMD64_OpDiv16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -25574,6 +30236,20 @@ func rewriteValueAMD64_OpDiv8u(v *Value) bool { return true } } +func rewriteValueAMD64_OpDotProdBroadcastFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (DotProdBroadcastFloat64x2 x y) + // result: (VDPPD128 [127] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VDPPD128) + v.AuxInt = int8ToAuxInt(127) + v.AddArg2(x, y) + return true + } +} func rewriteValueAMD64_OpEq16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -25702,1200 +30378,17865 @@ func rewriteValueAMD64_OpEqPtr(v *Value) bool { return true } } -func rewriteValueAMD64_OpFMA(v *Value) bool { - v_2 := v.Args[2] +func rewriteValueAMD64_OpEqualFloat32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - // match: (FMA x y z) - // result: (VFMADD231SD z x y) + b := v.Block + typ := &b.Func.Config.Types + // match: (EqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [0] x y)) for { x := v_0 y := v_1 - z := v_2 - v.reset(OpAMD64VFMADD231SD) - v.AddArg3(z, x, y) + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg2(x, y) + v.AddArg(v0) return true } } -func rewriteValueAMD64_OpFloor(v *Value) bool { +func rewriteValueAMD64_OpEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (Floor x) - // result: (ROUNDSD [1] x) + // match: (EqualFloat32x4 x y) + // result: (VCMPPS128 [0] x y) for { x := v_0 - v.reset(OpAMD64ROUNDSD) - v.AuxInt = int8ToAuxInt(1) - v.AddArg(x) + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(0) + v.AddArg2(x, y) return true } } -func rewriteValueAMD64_OpGetG(v *Value) bool { +func rewriteValueAMD64_OpEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] - // match: (GetG mem) - // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal - // result: (LoweredGetG mem) + // match: (EqualFloat32x8 x y) + // result: (VCMPPS256 [0] x y) for { - mem := v_0 - if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { - break - } - v.reset(OpAMD64LoweredGetG) - v.AddArg(mem) + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(0) + v.AddArg2(x, y) return true } - return false } -func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { - b := v.Block - typ := &b.Func.Config.Types - // match: (HasCPUFeature {s}) - // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) +func rewriteValueAMD64_OpEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (EqualFloat64x2 x y) + // result: (VCMPPD128 [0] x y) for { - s := auxToSym(v.Aux) - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v0.AuxInt = int32ToAuxInt(0) - v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) - v1.Aux = symToAux(s) - v0.AddArg(v1) - v.AddArg(v0) + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(0) + v.AddArg2(x, y) return true } } -func rewriteValueAMD64_OpIsInBounds(v *Value) bool { +func rewriteValueAMD64_OpEqualFloat64x4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (IsInBounds idx len) - // result: (SETB (CMPQ idx len)) + // match: (EqualFloat64x4 x y) + // result: (VCMPPD256 [0] x y) for { - idx := v_0 - len := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(idx, len) - v.AddArg(v0) + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(0) + v.AddArg2(x, y) return true } } -func rewriteValueAMD64_OpIsNonNil(v *Value) bool { +func rewriteValueAMD64_OpEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (IsNonNil p) - // result: (SETNE (TESTQ p p)) + typ := &b.Func.Config.Types + // match: (EqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [0] x y)) for { - p := v_0 - v.reset(OpAMD64SETNE) - v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) - v0.AddArg2(p, p) + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { +func rewriteValueAMD64_OpEqualInt16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (IsSliceInBounds idx len) - // result: (SETBE (CMPQ idx len)) + typ := &b.Func.Config.Types + // match: (EqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPEQW512 x y)) for { - idx := v_0 - len := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(idx, len) + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQW512, typ.Mask) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq16(v *Value) bool { +func rewriteValueAMD64_OpEqualInt32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq16 x y) - // result: (SETLE (CMPW x y)) + typ := &b.Func.Config.Types + // match: (EqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPEQD512 x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQD512, typ.Mask) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq16U(v *Value) bool { +func rewriteValueAMD64_OpEqualInt64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq16U x y) - // result: (SETBE (CMPW x y)) + typ := &b.Func.Config.Types + // match: (EqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQ512, typ.Mask) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq32(v *Value) bool { +func rewriteValueAMD64_OpEqualInt8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq32 x y) - // result: (SETLE (CMPL x y)) + typ := &b.Func.Config.Types + // match: (EqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPEQB512 x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQB512, typ.Mask) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq32F(v *Value) bool { +func rewriteValueAMD64_OpEqualUint16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq32F x y) - // result: (SETGEF (UCOMISS y x)) + typ := &b.Func.Config.Types + // match: (EqualUint16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPUW256 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETGEF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) - v0.AddArg2(y, x) + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq32U(v *Value) bool { +func rewriteValueAMD64_OpEqualUint16x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq32U x y) - // result: (SETBE (CMPL x y)) + typ := &b.Func.Config.Types + // match: (EqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq64(v *Value) bool { +func rewriteValueAMD64_OpEqualUint16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq64 x y) - // result: (SETLE (CMPQ x y)) + typ := &b.Func.Config.Types + // match: (EqualUint16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPUW128 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq64F(v *Value) bool { +func rewriteValueAMD64_OpEqualUint32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq64F x y) - // result: (SETGEF (UCOMISD y x)) + typ := &b.Func.Config.Types + // match: (EqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETGEF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) - v0.AddArg2(y, x) + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq64U(v *Value) bool { +func rewriteValueAMD64_OpEqualUint32x4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq64U x y) - // result: (SETBE (CMPQ x y)) + typ := &b.Func.Config.Types + // match: (EqualUint32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPUD128 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq8(v *Value) bool { +func rewriteValueAMD64_OpEqualUint32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq8 x y) - // result: (SETLE (CMPB x y)) + typ := &b.Func.Config.Types + // match: (EqualUint32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPUD256 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETLE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLeq8U(v *Value) bool { +func rewriteValueAMD64_OpEqualUint64x2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Leq8U x y) - // result: (SETBE (CMPB x y)) + typ := &b.Func.Config.Types + // match: (EqualUint64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPUQ128 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETBE) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLess16(v *Value) bool { +func rewriteValueAMD64_OpEqualUint64x4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less16 x y) - // result: (SETL (CMPW x y)) + typ := &b.Func.Config.Types + // match: (EqualUint64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPUQ256 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLess16U(v *Value) bool { +func rewriteValueAMD64_OpEqualUint64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less16U x y) - // result: (SETB (CMPW x y)) + typ := &b.Func.Config.Types + // match: (EqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLess32(v *Value) bool { +func rewriteValueAMD64_OpEqualUint8x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less32 x y) - // result: (SETL (CMPL x y)) + typ := &b.Func.Config.Types + // match: (EqualUint8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPUB128 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLess32F(v *Value) bool { +func rewriteValueAMD64_OpEqualUint8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less32F x y) - // result: (SETGF (UCOMISS y x)) + typ := &b.Func.Config.Types + // match: (EqualUint8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPUB256 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETGF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) - v0.AddArg2(y, x) + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLess32U(v *Value) bool { +func rewriteValueAMD64_OpEqualUint8x64(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Less32U x y) - // result: (SETB (CMPL x y)) + typ := &b.Func.Config.Types + // match: (EqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [0] x y)) for { x := v_0 y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) v0.AddArg2(x, y) v.AddArg(v0) return true } } -func rewriteValueAMD64_OpLess64(v *Value) bool { +func rewriteValueAMD64_OpFMA(v *Value) bool { + v_2 := v.Args[2] v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (Less64 x y) - // result: (SETL (CMPQ x y)) + // match: (FMA x y z) + // result: (VFMADD231SD z x y) for { x := v_0 y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + z := v_2 + v.reset(OpAMD64VFMADD231SD) + v.AddArg3(z, x, y) return true } } -func rewriteValueAMD64_OpLess64F(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloor(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Less64F x y) - // result: (SETGF (UCOMISD y x)) + // match: (Floor x) + // result: (ROUNDSD [1] x) for { x := v_0 - y := v_1 - v.reset(OpAMD64SETGF) - v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) - v0.AddArg2(y, x) - v.AddArg(v0) + v.reset(OpAMD64ROUNDSD) + v.AuxInt = int8ToAuxInt(1) + v.AddArg(x) return true } } -func rewriteValueAMD64_OpLess64U(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorFloat32x4(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Less64U x y) - // result: (SETB (CMPQ x y)) + // match: (FloorFloat32x4 x) + // result: (VROUNDPS128 [1] x) for { x := v_0 - y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = int8ToAuxInt(1) + v.AddArg(x) return true } } -func rewriteValueAMD64_OpLess8(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorFloat32x8(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Less8 x y) - // result: (SETL (CMPB x y)) + // match: (FloorFloat32x8 x) + // result: (VROUNDPS256 [1] x) for { x := v_0 - y := v_1 - v.reset(OpAMD64SETL) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = int8ToAuxInt(1) + v.AddArg(x) return true } } -func rewriteValueAMD64_OpLess8U(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorFloat64x2(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Less8U x y) - // result: (SETB (CMPB x y)) + // match: (FloorFloat64x2 x) + // result: (VROUNDPD128 [1] x) for { x := v_0 - y := v_1 - v.reset(OpAMD64SETB) - v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) - v0.AddArg2(x, y) - v.AddArg(v0) + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = int8ToAuxInt(1) + v.AddArg(x) return true } } -func rewriteValueAMD64_OpLoad(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorFloat64x4(v *Value) bool { v_0 := v.Args[0] - // match: (Load ptr mem) - // cond: (is64BitInt(t) || isPtr(t)) - // result: (MOVQload ptr mem) + // match: (FloorFloat64x4 x) + // result: (VROUNDPD256 [1] x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is64BitInt(t) || isPtr(t)) { - break - } - v.reset(OpAMD64MOVQload) - v.AddArg2(ptr, mem) + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = int8ToAuxInt(1) + v.AddArg(x) return true } - // match: (Load ptr mem) - // cond: is32BitInt(t) - // result: (MOVLload ptr mem) +} +func rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+9] x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitInt(t)) { - break - } - v.reset(OpAMD64MOVLload) - v.AddArg2(ptr, mem) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) return true } - // match: (Load ptr mem) - // cond: is16BitInt(t) - // result: (MOVWload ptr mem) +} +func rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+9] x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is16BitInt(t)) { - break - } - v.reset(OpAMD64MOVWload) - v.AddArg2(ptr, mem) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) return true } - // match: (Load ptr mem) - // cond: (t.IsBoolean() || is8BitInt(t)) - // result: (MOVBload ptr mem) +} +func rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+9] x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(t.IsBoolean() || is8BitInt(t)) { - break - } - v.reset(OpAMD64MOVBload) - v.AddArg2(ptr, mem) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) return true } - // match: (Load ptr mem) - // cond: is32BitFloat(t) - // result: (MOVSSload ptr mem) +} +func rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+9] x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is32BitFloat(t)) { - break - } - v.reset(OpAMD64MOVSSload) - v.AddArg2(ptr, mem) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) return true } - // match: (Load ptr mem) - // cond: is64BitFloat(t) - // result: (MOVSDload ptr mem) +} +func rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+9] x) for { - t := v.Type - ptr := v_0 - mem := v_1 - if !(is64BitFloat(t)) { - break - } - v.reset(OpAMD64MOVSDload) - v.AddArg2(ptr, mem) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) return true } - return false } -func rewriteValueAMD64_OpLocalAddr(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { v_0 := v.Args[0] - b := v.Block - typ := &b.Func.Config.Types - // match: (LocalAddr {sym} base mem) - // cond: t.Elem().HasPointers() - // result: (LEAQ {sym} (SPanchored base mem)) + // match: (FloorSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+9] x) for { - t := v.Type - sym := auxToSym(v.Aux) - base := v_0 - mem := v_1 - if !(t.Elem().HasPointers()) { - break - } - v.reset(OpAMD64LEAQ) - v.Aux = symToAux(sym) - v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) - v0.AddArg2(base, mem) - v.AddArg(v0) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 9) + v.AddArg(x) return true } - // match: (LocalAddr {sym} base _) - // cond: !t.Elem().HasPointers() - // result: (LEAQ {sym} base) +} +func rewriteValueAMD64_OpFloorWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+1] x) for { - t := v.Type - sym := auxToSym(v.Aux) - base := v_0 - if !(!t.Elem().HasPointers()) { - break - } - v.reset(OpAMD64LEAQ) - v.Aux = symToAux(sym) - v.AddArg(base) + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) return true } - return false } -func rewriteValueAMD64_OpLsh16x16(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorWithPrecisionFloat32x4(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + // match: (FloorWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+1] x) for { - t := v.Type + a := auxIntToInt8(v.AuxInt) x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) return true } - // match: (Lsh16x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpFloorWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+1] x) for { + a := auxIntToInt8(v.AuxInt) x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) return true } - return false } -func rewriteValueAMD64_OpLsh16x32(v *Value) bool { - v_1 := v.Args[1] +func rewriteValueAMD64_OpFloorWithPrecisionFloat64x2(v *Value) bool { v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + // match: (FloorWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+1] x) for { - t := v.Type + a := auxIntToInt8(v.AuxInt) x := v_0 - y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) return true } - // match: (Lsh16x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpFloorWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+1] x) for { + a := auxIntToInt8(v.AuxInt) x := v_0 - y := v_1 - if !(shiftIsBounded(v)) { + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpFloorWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (FloorWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+1] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 1) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpGetG(v *Value) bool { + v_0 := v.Args[0] + // match: (GetG mem) + // cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal + // result: (LoweredGetG mem) + for { + mem := v_0 + if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) { break } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64LoweredGetG) + v.AddArg(mem) return true } return false } -func rewriteValueAMD64_OpLsh16x64(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualFloat32x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh16x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh16x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterEqualFloat32x4 x y) + // result: (VCMPPS128 [5] x y) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(5) v.AddArg2(x, y) return true } - return false } -func rewriteValueAMD64_OpLsh16x8(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualFloat32x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (Lsh16x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + // match: (GreaterEqualFloat32x8 x y) + // result: (VCMPPS256 [5] x y) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(5) + v.AddArg2(x, y) return true } - // match: (Lsh16x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterEqualFloat64x2 x y) + // result: (VCMPPD128 [5] x y) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(5) v.AddArg2(x, y) return true } - return false } -func rewriteValueAMD64_OpLsh32x16(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualFloat64x4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] - b := v.Block - // match: (Lsh32x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + // match: (GreaterEqualFloat64x4 x y) + // result: (VCMPPD256 [5] x y) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) - v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(5) + v.AddArg2(x, y) return true } - // match: (Lsh32x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh32x32(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualInt16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh32x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualInt16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPW256 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh32x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh32x64(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualInt16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh32x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualInt16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPW128 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh32x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh32x8(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualInt32x4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh32x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualInt32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPD128 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh32x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPD256 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh64x16(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualInt64x2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualInt64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPQ128 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh64x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) +} +func rewriteValueAMD64_OpGreaterEqualInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPQ256 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh64x32(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualInt64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh64x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) +} +func rewriteValueAMD64_OpGreaterEqualInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPB128 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh64x64(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualInt8x32(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualInt8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPB256 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh64x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) +} +func rewriteValueAMD64_OpGreaterEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh64x8(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualUint16x16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh64x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPUW256 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDQ) - v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(64) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh64x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLQ x y) +} +func rewriteValueAMD64_OpGreaterEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLQ) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh8x16(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualUint16x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x16 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPUW128 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) - v2.AuxInt = int16ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh8x16 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh8x32(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualUint32x4(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x32 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPUD128 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh8x32 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPUD256 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh8x64(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualUint64x2(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x64 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPUQ128 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) - v2.AuxInt = int32ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh8x64 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPUQ256 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) - v.AddArg2(x, y) + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) return true } - return false } -func rewriteValueAMD64_OpLsh8x8(v *Value) bool { +func rewriteValueAMD64_OpGreaterEqualUint64x8(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] b := v.Block - // match: (Lsh8x8 x y) - // cond: !shiftIsBounded(v) - // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + typ := &b.Func.Config.Types + // match: (GreaterEqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [5] x y)) for { - t := v.Type x := v_0 y := v_1 - if !(!shiftIsBounded(v)) { - break - } - v.reset(OpAMD64ANDL) - v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) v0.AddArg2(x, y) - v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) - v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) - v2.AuxInt = int8ToAuxInt(32) - v2.AddArg(y) - v1.AddArg(v2) - v.AddArg2(v0, v1) + v.AddArg(v0) return true } - // match: (Lsh8x8 x y) - // cond: shiftIsBounded(v) - // result: (SHLL x y) +} +func rewriteValueAMD64_OpGreaterEqualUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPUB128 [5] x y)) for { x := v_0 y := v_1 - if !(shiftIsBounded(v)) { - break - } - v.reset(OpAMD64SHLL) + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPUB256 [5] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterEqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [5] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat32x4 x y) + // result: (VCMPPS128 [6] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(6) v.AddArg2(x, y) return true } - return false +} +func rewriteValueAMD64_OpGreaterFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat32x8 x y) + // result: (VCMPPS256 [6] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(6) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat64x2 x y) + // result: (VCMPPD128 [6] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(6) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (GreaterFloat64x4 x y) + // result: (VCMPPD256 [6] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(6) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpGreaterFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPGTW512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTW512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPGTD512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTD512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPGTQ128 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQ128, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPGTQ512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQ512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPGTB512 x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTB512, typ.Mask) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPUW256 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPUW128 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPUD128 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPUD256 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPUQ128 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPUQ256 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPUB128 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPUB256 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpGreaterUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (GreaterUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [6] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpHasCPUFeature(v *Value) bool { + b := v.Block + typ := &b.Func.Config.Types + // match: (HasCPUFeature {s}) + // result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s}))) + for { + s := auxToSym(v.Aux) + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v0.AuxInt = int32ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64LoweredHasCPUFeature, typ.UInt64) + v1.Aux = symToAux(s) + v0.AddArg(v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsInBounds(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (IsInBounds idx len) + // result: (SETB (CMPQ idx len)) + for { + idx := v_0 + len := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(idx, len) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsNanFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (IsNanFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [3] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsNanFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (IsNanFloat32x4 x y) + // result: (VCMPPS128 [3] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(3) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpIsNanFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (IsNanFloat32x8 x y) + // result: (VCMPPS256 [3] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(3) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpIsNanFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (IsNanFloat64x2 x y) + // result: (VCMPPD128 [3] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(3) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpIsNanFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (IsNanFloat64x4 x y) + // result: (VCMPPD256 [3] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(3) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpIsNanFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (IsNanFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [3] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsNonNil(v *Value) bool { + v_0 := v.Args[0] + b := v.Block + // match: (IsNonNil p) + // result: (SETNE (TESTQ p p)) + for { + p := v_0 + v.reset(OpAMD64SETNE) + v0 := b.NewValue0(v.Pos, OpAMD64TESTQ, types.TypeFlags) + v0.AddArg2(p, p) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpIsSliceInBounds(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (IsSliceInBounds idx len) + // result: (SETBE (CMPQ idx len)) + for { + idx := v_0 + len := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(idx, len) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq16 x y) + // result: (SETLE (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq16U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq16U x y) + // result: (SETBE (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq32 x y) + // result: (SETLE (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq32F x y) + // result: (SETGEF (UCOMISS y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq32U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq32U x y) + // result: (SETBE (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq64 x y) + // result: (SETLE (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq64F x y) + // result: (SETGEF (UCOMISD y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGEF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq64U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq64U x y) + // result: (SETBE (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq8 x y) + // result: (SETLE (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETLE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLeq8U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Leq8U x y) + // result: (SETBE (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETBE) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less16 x y) + // result: (SETL (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess16U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less16U x y) + // result: (SETB (CMPW x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPW, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32 x y) + // result: (SETL (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess32F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32F x y) + // result: (SETGF (UCOMISS y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISS, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess32U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less32U x y) + // result: (SETB (CMPL x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPL, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64 x y) + // result: (SETL (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess64F(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64F x y) + // result: (SETGF (UCOMISD y x)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETGF) + v0 := b.NewValue0(v.Pos, OpAMD64UCOMISD, types.TypeFlags) + v0.AddArg2(y, x) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess64U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less64U x y) + // result: (SETB (CMPQ x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPQ, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less8 x y) + // result: (SETL (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETL) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLess8U(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Less8U x y) + // result: (SETB (CMPB x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64SETB) + v0 := b.NewValue0(v.Pos, OpAMD64CMPB, types.TypeFlags) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat32x4 x y) + // result: (VCMPPS128 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat32x8 x y) + // result: (VCMPPS256 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat64x2 x y) + // result: (VCMPPD128 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessEqualFloat64x4 x y) + // result: (VCMPPD256 [2] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(2) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPW256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPW128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPD128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPD256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPQ128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPQ256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPB128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPB256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPUW256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPUW128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPUD128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPUD256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPUQ128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPUQ256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPUB128 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPUB256 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessEqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [2] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat32x4 x y) + // result: (VCMPPS128 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat32x8 x y) + // result: (VCMPPS256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat64x2 x y) + // result: (VCMPPD128 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (LessFloat64x4 x y) + // result: (VCMPPD256 [1] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(1) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpLessFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPW256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPW128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPD128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPD256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPQ128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPQ256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPB128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPB256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPUW256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPUW128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPUD128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPUD256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPUQ128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPUQ256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPUB128 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPUB256 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLessUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LessUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [1] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpLoad(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (Load ptr mem) + // cond: (is64BitInt(t) || isPtr(t)) + // result: (MOVQload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is64BitInt(t) || isPtr(t)) { + break + } + v.reset(OpAMD64MOVQload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is32BitInt(t) + // result: (MOVLload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is32BitInt(t)) { + break + } + v.reset(OpAMD64MOVLload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is16BitInt(t) + // result: (MOVWload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is16BitInt(t)) { + break + } + v.reset(OpAMD64MOVWload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: (t.IsBoolean() || is8BitInt(t)) + // result: (MOVBload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.IsBoolean() || is8BitInt(t)) { + break + } + v.reset(OpAMD64MOVBload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is32BitFloat(t) + // result: (MOVSSload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is32BitFloat(t)) { + break + } + v.reset(OpAMD64MOVSSload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: is64BitFloat(t) + // result: (MOVSDload ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(is64BitFloat(t)) { + break + } + v.reset(OpAMD64MOVSDload) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: t.Size() == 16 + // result: (VMOVDQUload128 ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VMOVDQUload128) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: t.Size() == 32 + // result: (VMOVDQUload256 ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VMOVDQUload256) + v.AddArg2(ptr, mem) + return true + } + // match: (Load ptr mem) + // cond: t.Size() == 64 + // result: (VMOVDQUload512 ptr mem) + for { + t := v.Type + ptr := v_0 + mem := v_1 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VMOVDQUload512) + v.AddArg2(ptr, mem) + return true + } + return false +} +func rewriteValueAMD64_OpLocalAddr(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (LocalAddr {sym} base mem) + // cond: t.Elem().HasPointers() + // result: (LEAQ {sym} (SPanchored base mem)) + for { + t := v.Type + sym := auxToSym(v.Aux) + base := v_0 + mem := v_1 + if !(t.Elem().HasPointers()) { + break + } + v.reset(OpAMD64LEAQ) + v.Aux = symToAux(sym) + v0 := b.NewValue0(v.Pos, OpSPanchored, typ.Uintptr) + v0.AddArg2(base, mem) + v.AddArg(v0) + return true + } + // match: (LocalAddr {sym} base _) + // cond: !t.Elem().HasPointers() + // result: (LEAQ {sym} base) + for { + t := v.Type + sym := auxToSym(v.Aux) + base := v_0 + if !(!t.Elem().HasPointers()) { + break + } + v.reset(OpAMD64LEAQ) + v.Aux = symToAux(sym) + v.AddArg(base) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh16x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh16x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh32x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh32x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPWconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPLconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPQconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh64x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDQ (SHLQ x y) (SBBQcarrymask (CMPBconst y [64]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDQ) + v0 := b.NewValue0(v.Pos, OpAMD64SHLQ, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBQcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(64) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh64x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLQ x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLQ) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x16 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPWconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPWconst, types.TypeFlags) + v2.AuxInt = int16ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x16 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x32 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPLconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPLconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x32 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x64 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPQconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPQconst, types.TypeFlags) + v2.AuxInt = int32ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x64 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpLsh8x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (Lsh8x8 x y) + // cond: !shiftIsBounded(v) + // result: (ANDL (SHLL x y) (SBBLcarrymask (CMPBconst y [32]))) + for { + t := v.Type + x := v_0 + y := v_1 + if !(!shiftIsBounded(v)) { + break + } + v.reset(OpAMD64ANDL) + v0 := b.NewValue0(v.Pos, OpAMD64SHLL, t) + v0.AddArg2(x, y) + v1 := b.NewValue0(v.Pos, OpAMD64SBBLcarrymask, t) + v2 := b.NewValue0(v.Pos, OpAMD64CMPBconst, types.TypeFlags) + v2.AuxInt = int8ToAuxInt(32) + v2.AddArg(y) + v1.AddArg(v2) + v.AddArg2(v0, v1) + return true + } + // match: (Lsh8x8 x y) + // cond: shiftIsBounded(v) + // result: (SHLL x y) + for { + x := v_0 + y := v_1 + if !(shiftIsBounded(v)) { + break + } + v.reset(OpAMD64SHLL) + v.AddArg2(x, y) + return true + } + return false +} +func rewriteValueAMD64_OpMaskedAbsoluteInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt16x16 x mask) + // result: (VPABSWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt16x32 x mask) + // result: (VPABSWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt16x8 x mask) + // result: (VPABSWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt32x16 x mask) + // result: (VPABSDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt32x4 x mask) + // result: (VPABSDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt32x8 x mask) + // result: (VPABSDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt64x2 x mask) + // result: (VPABSQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt64x4 x mask) + // result: (VPABSQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt64x8 x mask) + // result: (VPABSQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt8x16 x mask) + // result: (VPABSBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt8x32 x mask) + // result: (VPABSBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAbsoluteInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAbsoluteInt8x64 x mask) + // result: (VPABSBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPABSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddFloat32x16 x y mask) + // result: (VADDPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddFloat32x4 x y mask) + // result: (VADDPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddFloat32x8 x y mask) + // result: (VADDPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddFloat64x2 x y mask) + // result: (VADDPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddFloat64x4 x y mask) + // result: (VADDPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddFloat64x8 x y mask) + // result: (VADDPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt16x16 x y mask) + // result: (VPADDWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt16x32 x y mask) + // result: (VPADDWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt16x8 x y mask) + // result: (VPADDWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt32x16 x y mask) + // result: (VPADDDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt32x4 x y mask) + // result: (VPADDDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt32x8 x y mask) + // result: (VPADDDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt64x2 x y mask) + // result: (VPADDQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt64x4 x y mask) + // result: (VPADDQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt64x8 x y mask) + // result: (VPADDQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt8x16 x y mask) + // result: (VPADDBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt8x32 x y mask) + // result: (VPADDBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddInt8x64 x y mask) + // result: (VPADDBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint16x16 x y mask) + // result: (VPADDWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint16x32 x y mask) + // result: (VPADDWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint16x8 x y mask) + // result: (VPADDWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint32x16 x y mask) + // result: (VPADDDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint32x4 x y mask) + // result: (VPADDDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint32x8 x y mask) + // result: (VPADDDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint64x2 x y mask) + // result: (VPADDQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint64x4 x y mask) + // result: (VPADDQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint64x8 x y mask) + // result: (VPADDQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint8x16 x y mask) + // result: (VPADDBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint8x32 x y mask) + // result: (VPADDBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAddUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAddUint8x64 x y mask) + // result: (VPADDBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndFloat32x16 x y mask) + // result: (VANDPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndFloat32x4 x y mask) + // result: (VANDPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndFloat32x8 x y mask) + // result: (VANDPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndFloat64x2 x y mask) + // result: (VANDPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndFloat64x4 x y mask) + // result: (VANDPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndFloat64x8 x y mask) + // result: (VANDPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndInt32x16 x y mask) + // result: (VPANDDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndInt32x4 x y mask) + // result: (VPANDDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndInt32x8 x y mask) + // result: (VPANDDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndInt64x2 x y mask) + // result: (VPANDQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndInt64x4 x y mask) + // result: (VPANDQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndInt64x8 x y mask) + // result: (VPANDQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotFloat32x16 x y mask) + // result: (VANDNPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDNPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotFloat32x4 x y mask) + // result: (VANDNPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDNPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotFloat32x8 x y mask) + // result: (VANDNPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDNPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotFloat64x2 x y mask) + // result: (VANDNPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDNPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotFloat64x4 x y mask) + // result: (VANDNPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDNPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotFloat64x8 x y mask) + // result: (VANDNPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VANDNPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotInt32x16 x y mask) + // result: (VPANDNDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotInt32x4 x y mask) + // result: (VPANDNDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotInt32x8 x y mask) + // result: (VPANDNDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotInt64x2 x y mask) + // result: (VPANDNQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotInt64x4 x y mask) + // result: (VPANDNQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotInt64x8 x y mask) + // result: (VPANDNQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotUint32x16 x y mask) + // result: (VPANDNDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotUint32x4 x y mask) + // result: (VPANDNDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotUint32x8 x y mask) + // result: (VPANDNDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotUint64x2 x y mask) + // result: (VPANDNQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotUint64x4 x y mask) + // result: (VPANDNQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndNotUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndNotUint64x8 x y mask) + // result: (VPANDNQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDNQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndUint32x16 x y mask) + // result: (VPANDDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndUint32x4 x y mask) + // result: (VPANDDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndUint32x8 x y mask) + // result: (VPANDDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndUint64x2 x y mask) + // result: (VPANDQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndUint64x4 x y mask) + // result: (VPANDQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAndUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAndUint64x8 x y mask) + // result: (VPANDQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPANDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalFloat32x16 x mask) + // result: (VRCP14PSMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRCP14PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalFloat32x4 x mask) + // result: (VRCP14PSMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRCP14PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalFloat32x8 x mask) + // result: (VRCP14PSMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRCP14PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalFloat64x2 x mask) + // result: (VRCP14PDMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRCP14PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalFloat64x4 x mask) + // result: (VRCP14PDMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRCP14PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalFloat64x8 x mask) + // result: (VRCP14PDMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRCP14PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalOfSqrtFloat32x16 x mask) + // result: (VRSQRT14PSMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRSQRT14PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalOfSqrtFloat32x4 x mask) + // result: (VRSQRT14PSMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRSQRT14PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalOfSqrtFloat32x8 x mask) + // result: (VRSQRT14PSMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRSQRT14PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalOfSqrtFloat64x2 x mask) + // result: (VRSQRT14PDMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRSQRT14PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalOfSqrtFloat64x4 x mask) + // result: (VRSQRT14PDMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRSQRT14PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedApproximateReciprocalOfSqrtFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedApproximateReciprocalOfSqrtFloat64x8 x mask) + // result: (VRSQRT14PDMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VRSQRT14PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAverageUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAverageUint16x16 x y mask) + // result: (VPAVGWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPAVGWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAverageUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAverageUint16x32 x y mask) + // result: (VPAVGWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPAVGWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAverageUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAverageUint16x8 x y mask) + // result: (VPAVGWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPAVGWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAverageUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAverageUint8x16 x y mask) + // result: (VPAVGBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPAVGBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAverageUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAverageUint8x32 x y mask) + // result: (VPAVGBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPAVGBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedAverageUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedAverageUint8x64 x y mask) + // result: (VPAVGBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPAVGBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+10] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+10] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+10] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+10] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+10] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+10] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+2] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+2] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+2] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+2] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+2] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedCeilWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedCeilWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+2] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+10] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+10] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+10] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+10] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+10] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+10] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 10) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+2] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+2] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+2] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+2] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+2] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithCeilWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithCeilWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+2] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 2) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+9] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+9] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+9] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+9] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+9] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+9] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+1] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+1] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+1] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+1] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+1] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithFloorWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithFloorWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+1] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+8] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+8] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+8] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+8] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+8] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+8] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+0] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+0] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+0] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+0] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+0] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithRoundWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithRoundWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+0] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+11] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+11] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+11] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+11] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+11] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+11] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncWithPrecisionFloat32x16 [a] x mask) + // result: (VREDUCEPSMasked512 [a+3] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncWithPrecisionFloat32x4 [a] x mask) + // result: (VREDUCEPSMasked128 [a+3] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncWithPrecisionFloat32x8 [a] x mask) + // result: (VREDUCEPSMasked256 [a+3] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncWithPrecisionFloat64x2 [a] x mask) + // result: (VREDUCEPDMasked128 [a+3] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncWithPrecisionFloat64x4 [a] x mask) + // result: (VREDUCEPDMasked256 [a+3] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDiffWithTruncWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDiffWithTruncWithPrecisionFloat64x8 [a] x mask) + // result: (VREDUCEPDMasked512 [a+3] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VREDUCEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDivFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDivFloat32x16 x y mask) + // result: (VDIVPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VDIVPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDivFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDivFloat32x4 x y mask) + // result: (VDIVPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VDIVPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDivFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDivFloat32x8 x y mask) + // result: (VDIVPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VDIVPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDivFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDivFloat64x2 x y mask) + // result: (VDIVPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VDIVPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDivFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDivFloat64x4 x y mask) + // result: (VDIVPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VDIVPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedDivFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedDivFloat64x8 x y mask) + // result: (VDIVPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VDIVPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [0] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [0] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [0] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [0] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [0] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [0] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPEQWMasked256 x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQWMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPEQWMasked512 x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQWMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPEQWMasked128 x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQWMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPEQDMasked512 x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQDMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPEQDMasked128 x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQDMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPEQDMasked256 x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQDMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPEQQMasked128 x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPEQQMasked256 x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPEQQMasked512 x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQQMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPEQBMasked128 x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQBMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPEQBMasked256 x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQBMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualInt8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPEQBMasked512 x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPEQBMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [0] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [0] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [0] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [0] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [0] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [0] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [0] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [0] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [0] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [0] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [0] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedEqualUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedEqualUint8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [0] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(0) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+9] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+9] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+9] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+9] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+9] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+9] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 9) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+1] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+1] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+1] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+1] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+1] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFloorWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFloorWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+1] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 1) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd132Float32x16 x y z mask) + // result: (VFMADD132PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD132PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd132Float32x4 x y z mask) + // result: (VFMADD132PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD132PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd132Float32x8 x y z mask) + // result: (VFMADD132PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD132PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd132Float64x2 x y z mask) + // result: (VFMADD132PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD132PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd132Float64x4 x y z mask) + // result: (VFMADD132PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD132PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd132Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd132Float64x8 x y z mask) + // result: (VFMADD132PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD132PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd213Float32x16 x y z mask) + // result: (VFMADD213PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD213PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd213Float32x4 x y z mask) + // result: (VFMADD213PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD213PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd213Float32x8 x y z mask) + // result: (VFMADD213PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD213PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd213Float64x2 x y z mask) + // result: (VFMADD213PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD213PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd213Float64x4 x y z mask) + // result: (VFMADD213PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD213PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd213Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd213Float64x8 x y z mask) + // result: (VFMADD213PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD213PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd231Float32x16 x y z mask) + // result: (VFMADD231PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD231PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd231Float32x4 x y z mask) + // result: (VFMADD231PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD231PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd231Float32x8 x y z mask) + // result: (VFMADD231PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD231PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd231Float64x2 x y z mask) + // result: (VFMADD231PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD231PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd231Float64x4 x y z mask) + // result: (VFMADD231PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD231PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAdd231Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAdd231Float64x8 x y z mask) + // result: (VFMADD231PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADD231PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub132Float32x16 x y z mask) + // result: (VFMADDSUB132PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB132PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub132Float32x4 x y z mask) + // result: (VFMADDSUB132PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB132PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub132Float32x8 x y z mask) + // result: (VFMADDSUB132PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB132PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub132Float64x2 x y z mask) + // result: (VFMADDSUB132PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB132PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub132Float64x4 x y z mask) + // result: (VFMADDSUB132PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB132PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub132Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub132Float64x8 x y z mask) + // result: (VFMADDSUB132PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB132PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub213Float32x16 x y z mask) + // result: (VFMADDSUB213PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB213PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub213Float32x4 x y z mask) + // result: (VFMADDSUB213PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB213PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub213Float32x8 x y z mask) + // result: (VFMADDSUB213PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB213PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub213Float64x2 x y z mask) + // result: (VFMADDSUB213PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB213PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub213Float64x4 x y z mask) + // result: (VFMADDSUB213PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB213PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub213Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub213Float64x8 x y z mask) + // result: (VFMADDSUB213PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB213PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub231Float32x16 x y z mask) + // result: (VFMADDSUB231PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB231PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub231Float32x4 x y z mask) + // result: (VFMADDSUB231PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB231PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub231Float32x8 x y z mask) + // result: (VFMADDSUB231PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB231PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub231Float64x2 x y z mask) + // result: (VFMADDSUB231PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB231PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub231Float64x4 x y z mask) + // result: (VFMADDSUB231PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB231PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplyAddSub231Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplyAddSub231Float64x8 x y z mask) + // result: (VFMADDSUB231PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMADDSUB231PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub132Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub132Float32x16 x y z mask) + // result: (VFMSUB132PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB132PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub132Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub132Float32x4 x y z mask) + // result: (VFMSUB132PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB132PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub132Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub132Float32x8 x y z mask) + // result: (VFMSUB132PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB132PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub132Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub132Float64x2 x y z mask) + // result: (VFMSUB132PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB132PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub132Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub132Float64x4 x y z mask) + // result: (VFMSUB132PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB132PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub132Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub132Float64x8 x y z mask) + // result: (VFMSUB132PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB132PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub213Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub213Float32x16 x y z mask) + // result: (VFMSUB213PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB213PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub213Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub213Float32x4 x y z mask) + // result: (VFMSUB213PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB213PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub213Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub213Float32x8 x y z mask) + // result: (VFMSUB213PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB213PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub213Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub213Float64x2 x y z mask) + // result: (VFMSUB213PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB213PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub213Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub213Float64x4 x y z mask) + // result: (VFMSUB213PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB213PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub213Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub213Float64x8 x y z mask) + // result: (VFMSUB213PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB213PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub231Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub231Float32x16 x y z mask) + // result: (VFMSUB231PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB231PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub231Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub231Float32x4 x y z mask) + // result: (VFMSUB231PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB231PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub231Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub231Float32x8 x y z mask) + // result: (VFMSUB231PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB231PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub231Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub231Float64x2 x y z mask) + // result: (VFMSUB231PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB231PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub231Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub231Float64x4 x y z mask) + // result: (VFMSUB231PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB231PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySub231Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySub231Float64x8 x y z mask) + // result: (VFMSUB231PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUB231PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd132Float32x16 x y z mask) + // result: (VFMSUBADD132PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD132PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd132Float32x4 x y z mask) + // result: (VFMSUBADD132PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD132PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd132Float32x8 x y z mask) + // result: (VFMSUBADD132PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD132PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd132Float64x2 x y z mask) + // result: (VFMSUBADD132PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD132PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd132Float64x4 x y z mask) + // result: (VFMSUBADD132PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD132PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd132Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd132Float64x8 x y z mask) + // result: (VFMSUBADD132PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD132PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd213Float32x16 x y z mask) + // result: (VFMSUBADD213PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD213PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd213Float32x4 x y z mask) + // result: (VFMSUBADD213PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD213PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd213Float32x8 x y z mask) + // result: (VFMSUBADD213PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD213PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd213Float64x2 x y z mask) + // result: (VFMSUBADD213PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD213PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd213Float64x4 x y z mask) + // result: (VFMSUBADD213PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD213PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd213Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd213Float64x8 x y z mask) + // result: (VFMSUBADD213PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD213PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd231Float32x16 x y z mask) + // result: (VFMSUBADD231PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD231PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd231Float32x4 x y z mask) + // result: (VFMSUBADD231PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD231PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd231Float32x8 x y z mask) + // result: (VFMSUBADD231PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD231PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd231Float64x2 x y z mask) + // result: (VFMSUBADD231PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD231PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd231Float64x4 x y z mask) + // result: (VFMSUBADD231PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD231PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedMultiplySubAdd231Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedMultiplySubAdd231Float64x8 x y z mask) + // result: (VFMSUBADD231PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFMSUBADD231PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd132Float32x16 x y z mask) + // result: (VFNMADD132PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD132PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd132Float32x4 x y z mask) + // result: (VFNMADD132PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD132PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd132Float32x8 x y z mask) + // result: (VFNMADD132PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD132PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd132Float64x2 x y z mask) + // result: (VFNMADD132PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD132PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd132Float64x4 x y z mask) + // result: (VFNMADD132PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD132PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd132Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd132Float64x8 x y z mask) + // result: (VFNMADD132PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD132PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd213Float32x16 x y z mask) + // result: (VFNMADD213PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD213PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd213Float32x4 x y z mask) + // result: (VFNMADD213PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD213PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd213Float32x8 x y z mask) + // result: (VFNMADD213PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD213PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd213Float64x2 x y z mask) + // result: (VFNMADD213PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD213PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd213Float64x4 x y z mask) + // result: (VFNMADD213PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD213PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd213Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd213Float64x8 x y z mask) + // result: (VFNMADD213PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD213PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd231Float32x16 x y z mask) + // result: (VFNMADD231PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD231PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd231Float32x4 x y z mask) + // result: (VFNMADD231PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD231PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd231Float32x8 x y z mask) + // result: (VFNMADD231PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD231PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd231Float64x2 x y z mask) + // result: (VFNMADD231PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD231PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd231Float64x4 x y z mask) + // result: (VFNMADD231PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD231PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplyAdd231Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplyAdd231Float64x8 x y z mask) + // result: (VFNMADD231PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMADD231PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub132Float32x16 x y z mask) + // result: (VFNMSUB132PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB132PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub132Float32x4 x y z mask) + // result: (VFNMSUB132PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB132PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub132Float32x8 x y z mask) + // result: (VFNMSUB132PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB132PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub132Float64x2 x y z mask) + // result: (VFNMSUB132PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB132PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub132Float64x4 x y z mask) + // result: (VFNMSUB132PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB132PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub132Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub132Float64x8 x y z mask) + // result: (VFNMSUB132PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB132PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub213Float32x16 x y z mask) + // result: (VFNMSUB213PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB213PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub213Float32x4 x y z mask) + // result: (VFNMSUB213PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB213PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub213Float32x8 x y z mask) + // result: (VFNMSUB213PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB213PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub213Float64x2 x y z mask) + // result: (VFNMSUB213PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB213PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub213Float64x4 x y z mask) + // result: (VFNMSUB213PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB213PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub213Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub213Float64x8 x y z mask) + // result: (VFNMSUB213PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB213PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub231Float32x16 x y z mask) + // result: (VFNMSUB231PSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB231PSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub231Float32x4 x y z mask) + // result: (VFNMSUB231PSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB231PSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub231Float32x8 x y z mask) + // result: (VFNMSUB231PSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB231PSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float64x2(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub231Float64x2 x y z mask) + // result: (VFNMSUB231PDMasked128 x y z (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB231PDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float64x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub231Float64x4 x y z mask) + // result: (VFNMSUB231PDMasked256 x y z (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB231PDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedFusedNegativeMultiplySub231Float64x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedFusedNegativeMultiplySub231Float64x8 x y z mask) + // result: (VFNMSUB231PDMasked512 x y z (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VFNMSUB231PDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [5] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [5] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [5] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [5] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [5] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [5] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [5] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [5] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [5] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [5] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [5] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [5] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [5] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [5] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [5] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [5] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [5] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualInt8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [5] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [5] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [5] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [5] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [5] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [5] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [5] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [5] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [5] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [5] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [5] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [5] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterEqualUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterEqualUint8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [5] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(5) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [6] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [6] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [6] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [6] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [6] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [6] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPGTWMasked256 x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTWMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPGTWMasked512 x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTWMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPGTWMasked128 x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTWMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPGTDMasked512 x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTDMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPGTDMasked128 x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTDMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPGTDMasked256 x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTDMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPGTQMasked128 x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPGTQMasked256 x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPGTQMasked512 x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTQMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPGTBMasked128 x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTBMasked128, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPGTBMasked256 x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTBMasked256, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterInt8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPGTBMasked512 x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPGTBMasked512, typ.Mask) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [6] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [6] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [6] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [6] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [6] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [6] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [6] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [6] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [6] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [6] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [6] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedGreaterUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedGreaterUint8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [6] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(6) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedIsNanFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedIsNanFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [3] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedIsNanFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedIsNanFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [3] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedIsNanFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedIsNanFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [3] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedIsNanFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedIsNanFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [3] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedIsNanFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedIsNanFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [3] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedIsNanFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedIsNanFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [3] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(3) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [2] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [2] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [2] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [2] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [2] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [2] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [2] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [2] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [2] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [2] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [2] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [2] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [2] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [2] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [2] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [2] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [2] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualInt8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [2] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [2] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [2] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [2] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [2] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [2] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [2] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [2] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [2] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [2] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [2] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [2] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessEqualUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessEqualUint8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [2] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(2) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [1] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [1] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [1] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [1] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [1] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [1] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [1] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [1] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [1] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [1] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [1] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [1] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [1] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [1] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [1] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [1] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [1] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessInt8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [1] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [1] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [1] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [1] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [1] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [1] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [1] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [1] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [1] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [1] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [1] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [1] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedLessUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedLessUint8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [1] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(1) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxFloat32x16 x y mask) + // result: (VMAXPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMAXPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxFloat32x4 x y mask) + // result: (VMAXPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMAXPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxFloat32x8 x y mask) + // result: (VMAXPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMAXPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxFloat64x2 x y mask) + // result: (VMAXPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMAXPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxFloat64x4 x y mask) + // result: (VMAXPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMAXPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxFloat64x8 x y mask) + // result: (VMAXPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMAXPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt16x16 x y mask) + // result: (VPMAXSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt16x32 x y mask) + // result: (VPMAXSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt16x8 x y mask) + // result: (VPMAXSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt32x16 x y mask) + // result: (VPMAXSDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt32x4 x y mask) + // result: (VPMAXSDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt32x8 x y mask) + // result: (VPMAXSDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt64x2 x y mask) + // result: (VPMAXSQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt64x4 x y mask) + // result: (VPMAXSQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt64x8 x y mask) + // result: (VPMAXSQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt8x16 x y mask) + // result: (VPMAXSBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt8x32 x y mask) + // result: (VPMAXSBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxInt8x64 x y mask) + // result: (VPMAXSBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint16x16 x y mask) + // result: (VPMAXUWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint16x32 x y mask) + // result: (VPMAXUWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint16x8 x y mask) + // result: (VPMAXUWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint32x16 x y mask) + // result: (VPMAXUDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint32x4 x y mask) + // result: (VPMAXUDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint32x8 x y mask) + // result: (VPMAXUDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint64x2 x y mask) + // result: (VPMAXUQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint64x4 x y mask) + // result: (VPMAXUQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint64x8 x y mask) + // result: (VPMAXUQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint8x16 x y mask) + // result: (VPMAXUBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint8x32 x y mask) + // result: (VPMAXUBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMaxUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMaxUint8x64 x y mask) + // result: (VPMAXUBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMAXUBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinFloat32x16 x y mask) + // result: (VMINPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMINPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinFloat32x4 x y mask) + // result: (VMINPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMINPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinFloat32x8 x y mask) + // result: (VMINPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMINPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinFloat64x2 x y mask) + // result: (VMINPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMINPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinFloat64x4 x y mask) + // result: (VMINPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMINPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinFloat64x8 x y mask) + // result: (VMINPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMINPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt16x16 x y mask) + // result: (VPMINSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt16x32 x y mask) + // result: (VPMINSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt16x8 x y mask) + // result: (VPMINSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt32x16 x y mask) + // result: (VPMINSDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt32x4 x y mask) + // result: (VPMINSDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt32x8 x y mask) + // result: (VPMINSDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt64x2 x y mask) + // result: (VPMINSQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt64x4 x y mask) + // result: (VPMINSQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt64x8 x y mask) + // result: (VPMINSQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt8x16 x y mask) + // result: (VPMINSBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt8x32 x y mask) + // result: (VPMINSBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinInt8x64 x y mask) + // result: (VPMINSBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint16x16 x y mask) + // result: (VPMINUWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint16x32 x y mask) + // result: (VPMINUWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint16x8 x y mask) + // result: (VPMINUWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint32x16 x y mask) + // result: (VPMINUDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint32x4 x y mask) + // result: (VPMINUDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint32x8 x y mask) + // result: (VPMINUDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint64x2 x y mask) + // result: (VPMINUQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint64x4 x y mask) + // result: (VPMINUQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint64x8 x y mask) + // result: (VPMINUQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint8x16 x y mask) + // result: (VPMINUBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint8x32 x y mask) + // result: (VPMINUBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMinUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMinUint8x64 x y mask) + // result: (VPMINUBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMINUBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulByPowOf2Float32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulByPowOf2Float32x16 x y mask) + // result: (VSCALEFPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VSCALEFPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulByPowOf2Float32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulByPowOf2Float32x4 x y mask) + // result: (VSCALEFPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VSCALEFPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulByPowOf2Float32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulByPowOf2Float32x8 x y mask) + // result: (VSCALEFPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VSCALEFPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulByPowOf2Float64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulByPowOf2Float64x2 x y mask) + // result: (VSCALEFPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VSCALEFPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulByPowOf2Float64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulByPowOf2Float64x4 x y mask) + // result: (VSCALEFPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VSCALEFPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulByPowOf2Float64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulByPowOf2Float64x8 x y mask) + // result: (VSCALEFPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VSCALEFPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulEvenWidenInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulEvenWidenInt64x2 x y mask) + // result: (VPMULDQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulEvenWidenInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulEvenWidenInt64x4 x y mask) + // result: (VPMULDQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulEvenWidenInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulEvenWidenInt64x8 x y mask) + // result: (VPMULDQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulEvenWidenUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulEvenWidenUint64x2 x y mask) + // result: (VPMULUDQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULUDQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulEvenWidenUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulEvenWidenUint64x4 x y mask) + // result: (VPMULUDQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULUDQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulEvenWidenUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulEvenWidenUint64x8 x y mask) + // result: (VPMULUDQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULUDQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulFloat32x16 x y mask) + // result: (VMULPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMULPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulFloat32x4 x y mask) + // result: (VMULPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMULPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulFloat32x8 x y mask) + // result: (VMULPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMULPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulFloat64x2 x y mask) + // result: (VMULPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMULPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulFloat64x4 x y mask) + // result: (VMULPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMULPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulFloat64x8 x y mask) + // result: (VMULPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VMULPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulHighInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulHighInt16x16 x y mask) + // result: (VPMULHWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULHWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulHighInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulHighInt16x32 x y mask) + // result: (VPMULHWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULHWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulHighInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulHighInt16x8 x y mask) + // result: (VPMULHWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULHWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulHighUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulHighUint16x16 x y mask) + // result: (VPMULHUWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULHUWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulHighUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulHighUint16x32 x y mask) + // result: (VPMULHUWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULHUWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulHighUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulHighUint16x8 x y mask) + // result: (VPMULHUWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULHUWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt16x16 x y mask) + // result: (VPMULLWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt16x32 x y mask) + // result: (VPMULLWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt16x8 x y mask) + // result: (VPMULLWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt32x16 x y mask) + // result: (VPMULLDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt32x4 x y mask) + // result: (VPMULLDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt32x8 x y mask) + // result: (VPMULLDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt64x2 x y mask) + // result: (VPMULLQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt64x4 x y mask) + // result: (VPMULLQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedMulLowInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedMulLowInt64x8 x y mask) + // result: (VPMULLQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMULLQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualFloat32x16 x y mask) + // result: (VPMOVMToVec32x16 (VCMPPSMasked512 [4] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualFloat32x4 x y mask) + // result: (VPMOVMToVec32x4 (VCMPPSMasked128 [4] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualFloat32x8 x y mask) + // result: (VPMOVMToVec32x8 (VCMPPSMasked256 [4] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPSMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualFloat64x2 x y mask) + // result: (VPMOVMToVec64x2 (VCMPPDMasked128 [4] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualFloat64x4 x y mask) + // result: (VPMOVMToVec64x4 (VCMPPDMasked256 [4] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualFloat64x8 x y mask) + // result: (VPMOVMToVec64x8 (VCMPPDMasked512 [4] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPWMasked256 [4] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPWMasked512 [4] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPWMasked128 [4] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPDMasked512 [4] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPDMasked128 [4] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPDMasked256 [4] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPQMasked128 [4] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPQMasked256 [4] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPQMasked512 [4] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPBMasked128 [4] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPBMasked256 [4] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualInt8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPBMasked512 [4] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint16x16 x y mask) + // result: (VPMOVMToVec16x16 (VPCMPUWMasked256 [4] x y (VPMOVVec16x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint16x32 x y mask) + // result: (VPMOVMToVec16x32 (VPCMPUWMasked512 [4] x y (VPMOVVec16x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint16x8 x y mask) + // result: (VPMOVMToVec16x8 (VPCMPUWMasked128 [4] x y (VPMOVVec16x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUWMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint32x16 x y mask) + // result: (VPMOVMToVec32x16 (VPCMPUDMasked512 [4] x y (VPMOVVec32x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint32x4 x y mask) + // result: (VPMOVMToVec32x4 (VPCMPUDMasked128 [4] x y (VPMOVVec32x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint32x8 x y mask) + // result: (VPMOVMToVec32x8 (VPCMPUDMasked256 [4] x y (VPMOVVec32x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUDMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint64x2 x y mask) + // result: (VPMOVMToVec64x2 (VPCMPUQMasked128 [4] x y (VPMOVVec64x2ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint64x4 x y mask) + // result: (VPMOVMToVec64x4 (VPCMPUQMasked256 [4] x y (VPMOVVec64x4ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint64x8 x y mask) + // result: (VPMOVMToVec64x8 (VPCMPUQMasked512 [4] x y (VPMOVVec64x8ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint8x16 x y mask) + // result: (VPMOVMToVec8x16 (VPCMPUBMasked128 [4] x y (VPMOVVec8x16ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint8x32 x y mask) + // result: (VPMOVMToVec8x32 (VPCMPUBMasked256 [4] x y (VPMOVVec8x32ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedNotEqualUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (MaskedNotEqualUint8x64 x y mask) + // result: (VPMOVMToVec8x64 (VPCMPUBMasked512 [4] x y (VPMOVVec8x64ToM mask))) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUBMasked512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v1 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v1.AddArg(mask) + v0.AddArg3(x, y, v1) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrFloat32x16 x y mask) + // result: (VORPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VORPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrFloat32x4 x y mask) + // result: (VORPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VORPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrFloat32x8 x y mask) + // result: (VORPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VORPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrFloat64x2 x y mask) + // result: (VORPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VORPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrFloat64x4 x y mask) + // result: (VORPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VORPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrFloat64x8 x y mask) + // result: (VORPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VORPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrInt32x16 x y mask) + // result: (VPORDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrInt32x4 x y mask) + // result: (VPORDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrInt32x8 x y mask) + // result: (VPORDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrInt64x2 x y mask) + // result: (VPORQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrInt64x4 x y mask) + // result: (VPORQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrInt64x8 x y mask) + // result: (VPORQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrUint32x16 x y mask) + // result: (VPORDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrUint32x4 x y mask) + // result: (VPORDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrUint32x8 x y mask) + // result: (VPORDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrUint64x2 x y mask) + // result: (VPORQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrUint64x4 x y mask) + // result: (VPORQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedOrUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedOrUint64x8 x y mask) + // result: (VPORQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPORQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPairDotProdAccumulateInt32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPairDotProdAccumulateInt32x16 x y z mask) + // result: (VPDPWSSDMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPWSSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPairDotProdAccumulateInt32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPairDotProdAccumulateInt32x4 x y z mask) + // result: (VPDPWSSDMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPWSSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPairDotProdAccumulateInt32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPairDotProdAccumulateInt32x8 x y z mask) + // result: (VPDPWSSDMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPWSSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPairDotProdInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPairDotProdInt16x16 x y mask) + // result: (VPMADDWDMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMADDWDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPairDotProdInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPairDotProdInt16x32 x y mask) + // result: (VPMADDWDMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMADDWDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPairDotProdInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPairDotProdInt16x8 x y mask) + // result: (VPMADDWDMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMADDWDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt16x16 x mask) + // result: (VPOPCNTWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt16x32 x mask) + // result: (VPOPCNTWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt16x8 x mask) + // result: (VPOPCNTWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt32x16 x mask) + // result: (VPOPCNTDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt32x4 x mask) + // result: (VPOPCNTDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt32x8 x mask) + // result: (VPOPCNTDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt64x2 x mask) + // result: (VPOPCNTQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt64x4 x mask) + // result: (VPOPCNTQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt64x8 x mask) + // result: (VPOPCNTQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt8x16 x mask) + // result: (VPOPCNTBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt8x32 x mask) + // result: (VPOPCNTBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountInt8x64 x mask) + // result: (VPOPCNTBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint16x16 x mask) + // result: (VPOPCNTWMasked256 x (VPMOVVec16x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint16x32 x mask) + // result: (VPOPCNTWMasked512 x (VPMOVVec16x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint16x8 x mask) + // result: (VPOPCNTWMasked128 x (VPMOVVec16x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint32x16 x mask) + // result: (VPOPCNTDMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint32x4 x mask) + // result: (VPOPCNTDMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint32x8 x mask) + // result: (VPOPCNTDMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint64x2 x mask) + // result: (VPOPCNTQMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint64x4 x mask) + // result: (VPOPCNTQMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint64x8 x mask) + // result: (VPOPCNTQMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint8x16 x mask) + // result: (VPOPCNTBMasked128 x (VPMOVVec8x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint8x32 x mask) + // result: (VPOPCNTBMasked256 x (VPMOVVec8x32ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedPopCountUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedPopCountUint8x64 x mask) + // result: (VPOPCNTBMasked512 x (VPMOVVec8x64ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VPOPCNTBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+8] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+8] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+8] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+8] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+8] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+8] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 8) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+0] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+0] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+0] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+0] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+0] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedRoundWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedRoundWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+0] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 0) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddInt16x16 x y mask) + // result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddInt16x32 x y mask) + // result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddInt16x8 x y mask) + // result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddInt8x16 x y mask) + // result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddInt8x32 x y mask) + // result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddInt8x64 x y mask) + // result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddUint16x16 x y mask) + // result: (VPADDSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddUint16x32 x y mask) + // result: (VPADDSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddUint16x8 x y mask) + // result: (VPADDSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddUint8x16 x y mask) + // result: (VPADDSBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddUint8x32 x y mask) + // result: (VPADDSBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedAddUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedAddUint8x64 x y mask) + // result: (VPADDSBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPADDSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedPairDotProdAccumulateInt32x16 x y z mask) + // result: (VPDPWSSDSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPWSSDSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedPairDotProdAccumulateInt32x4 x y z mask) + // result: (VPDPWSSDSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPWSSDSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedPairDotProdAccumulateInt32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedPairDotProdAccumulateInt32x8 x y z mask) + // result: (VPDPWSSDSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPWSSDSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubInt16x16 x y mask) + // result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubInt16x32 x y mask) + // result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubInt16x8 x y mask) + // result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubInt8x16 x y mask) + // result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubInt8x32 x y mask) + // result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubInt8x64 x y mask) + // result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubUint16x16 x y mask) + // result: (VPSUBSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubUint16x32 x y mask) + // result: (VPSUBSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubUint16x8 x y mask) + // result: (VPSUBSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubUint8x16 x y mask) + // result: (VPSUBSBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubUint8x32 x y mask) + // result: (VPSUBSBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedSubUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedSubUint8x64 x y mask) + // result: (VPSUBSBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBSBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedPairDotProdUint16x16 x y mask) + // result: (VPMADDUBSWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMADDUBSWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedPairDotProdUint16x32 x y mask) + // result: (VPMADDUBSWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMADDUBSWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedPairDotProdUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedPairDotProdUint16x8 x y mask) + // result: (VPMADDUBSWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPMADDUBSWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x16 x y z mask) + // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x4 x y z mask) + // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateInt32x8 x y z mask) + // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) + // result: (VPDPBUSDSMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) + // result: (VPDPBUSDSMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSaturatedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) + // result: (VPDPBUSDSMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSqrtFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSqrtFloat32x16 x mask) + // result: (VSQRTPSMasked512 x (VPMOVVec32x16ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VSQRTPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSqrtFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSqrtFloat32x4 x mask) + // result: (VSQRTPSMasked128 x (VPMOVVec32x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VSQRTPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSqrtFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSqrtFloat32x8 x mask) + // result: (VSQRTPSMasked256 x (VPMOVVec32x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VSQRTPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSqrtFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSqrtFloat64x2 x mask) + // result: (VSQRTPDMasked128 x (VPMOVVec64x2ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VSQRTPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSqrtFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSqrtFloat64x4 x mask) + // result: (VSQRTPDMasked256 x (VPMOVVec64x4ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VSQRTPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSqrtFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSqrtFloat64x8 x mask) + // result: (VSQRTPDMasked512 x (VPMOVVec64x8ToM mask)) + for { + x := v_0 + mask := v_1 + v.reset(OpAMD64VSQRTPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubFloat32x16 x y mask) + // result: (VADDPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubFloat32x4 x y mask) + // result: (VADDPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubFloat32x8 x y mask) + // result: (VADDPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubFloat64x2 x y mask) + // result: (VADDPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubFloat64x4 x y mask) + // result: (VADDPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubFloat64x8 x y mask) + // result: (VADDPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VADDPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt16x16 x y mask) + // result: (VPSUBWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt16x32 x y mask) + // result: (VPSUBWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt16x8 x y mask) + // result: (VPSUBWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt32x16 x y mask) + // result: (VPSUBDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt32x4 x y mask) + // result: (VPSUBDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt32x8 x y mask) + // result: (VPSUBDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt64x2 x y mask) + // result: (VPSUBQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt64x4 x y mask) + // result: (VPSUBQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt64x8 x y mask) + // result: (VPSUBQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt8x16 x y mask) + // result: (VPSUBBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt8x32 x y mask) + // result: (VPSUBBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubInt8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubInt8x64 x y mask) + // result: (VPSUBBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint16x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint16x16 x y mask) + // result: (VPSUBWMasked256 x y (VPMOVVec16x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBWMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint16x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint16x32 x y mask) + // result: (VPSUBWMasked512 x y (VPMOVVec16x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBWMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint16x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint16x8 x y mask) + // result: (VPSUBWMasked128 x y (VPMOVVec16x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBWMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec16x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint32x16 x y mask) + // result: (VPSUBDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint32x4 x y mask) + // result: (VPSUBDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint32x8 x y mask) + // result: (VPSUBDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint64x2 x y mask) + // result: (VPSUBQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint64x4 x y mask) + // result: (VPSUBQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint64x8 x y mask) + // result: (VPSUBQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint8x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint8x16 x y mask) + // result: (VPSUBBMasked128 x y (VPMOVVec8x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBBMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint8x32(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint8x32 x y mask) + // result: (VPSUBBMasked256 x y (VPMOVVec8x32ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBBMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x32ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedSubUint8x64(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedSubUint8x64 x y mask) + // result: (VPSUBBMasked512 x y (VPMOVVec8x64ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPSUBBMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec8x64ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncSuppressExceptionWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+11] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncSuppressExceptionWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+11] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncSuppressExceptionWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+11] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncSuppressExceptionWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+11] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncSuppressExceptionWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+11] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncSuppressExceptionWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+11] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 11) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncWithPrecisionFloat32x16 [a] x mask) + // result: (VRNDSCALEPSMasked512 [a+3] x (VPMOVVec32x16ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked512) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncWithPrecisionFloat32x4 [a] x mask) + // result: (VRNDSCALEPSMasked128 [a+3] x (VPMOVVec32x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked128) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncWithPrecisionFloat32x8 [a] x mask) + // result: (VRNDSCALEPSMasked256 [a+3] x (VPMOVVec32x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPSMasked256) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncWithPrecisionFloat64x2 [a] x mask) + // result: (VRNDSCALEPDMasked128 [a+3] x (VPMOVVec64x2ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked128) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncWithPrecisionFloat64x4 [a] x mask) + // result: (VRNDSCALEPDMasked256 [a+3] x (VPMOVVec64x4ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked256) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedTruncWithPrecisionFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedTruncWithPrecisionFloat64x8 [a] x mask) + // result: (VRNDSCALEPDMasked512 [a+3] x (VPMOVVec64x8ToM mask)) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + mask := v_1 + v.reset(OpAMD64VRNDSCALEPDMasked512) + v.AuxInt = int8ToAuxInt(a + 3) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg2(x, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedUnsignedSignedQuadDotProdAccumulateInt32x16 x y z mask) + // result: (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedUnsignedSignedQuadDotProdAccumulateInt32x4 x y z mask) + // result: (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateInt32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedUnsignedSignedQuadDotProdAccumulateInt32x8 x y z mask) + // result: (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x16(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedUnsignedSignedQuadDotProdAccumulateUint32x16 x y z mask) + // result: (VPDPBUSDMasked512 x y z (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x4(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedUnsignedSignedQuadDotProdAccumulateUint32x4 x y z mask) + // result: (VPDPBUSDMasked128 x y z (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedUnsignedSignedQuadDotProdAccumulateUint32x8(v *Value) bool { + v_3 := v.Args[3] + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedUnsignedSignedQuadDotProdAccumulateUint32x8 x y z mask) + // result: (VPDPBUSDMasked256 x y z (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + z := v_2 + mask := v_3 + v.reset(OpAMD64VPDPBUSDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg4(x, y, z, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorFloat32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorFloat32x16 x y mask) + // result: (VXORPSMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VXORPSMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorFloat32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorFloat32x4 x y mask) + // result: (VXORPSMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VXORPSMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorFloat32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorFloat32x8 x y mask) + // result: (VXORPSMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VXORPSMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorFloat64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorFloat64x2 x y mask) + // result: (VXORPDMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VXORPDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorFloat64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorFloat64x4 x y mask) + // result: (VXORPDMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VXORPDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorFloat64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorFloat64x8 x y mask) + // result: (VXORPDMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VXORPDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorInt32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorInt32x16 x y mask) + // result: (VPXORDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorInt32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorInt32x4 x y mask) + // result: (VPXORDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorInt32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorInt32x8 x y mask) + // result: (VPXORDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorInt64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorInt64x2 x y mask) + // result: (VPXORQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorInt64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorInt64x4 x y mask) + // result: (VPXORQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorInt64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorInt64x8 x y mask) + // result: (VPXORQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorUint32x16(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorUint32x16 x y mask) + // result: (VPXORDMasked512 x y (VPMOVVec32x16ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORDMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x16ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorUint32x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorUint32x4 x y mask) + // result: (VPXORDMasked128 x y (VPMOVVec32x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORDMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorUint32x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorUint32x8 x y mask) + // result: (VPXORDMasked256 x y (VPMOVVec32x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORDMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec32x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorUint64x2(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorUint64x2 x y mask) + // result: (VPXORQMasked128 x y (VPMOVVec64x2ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORQMasked128) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x2ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorUint64x4(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorUint64x4 x y mask) + // result: (VPXORQMasked256 x y (VPMOVVec64x4ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORQMasked256) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x4ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } +} +func rewriteValueAMD64_OpMaskedXorUint64x8(v *Value) bool { + v_2 := v.Args[2] + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + // match: (MaskedXorUint64x8 x y mask) + // result: (VPXORQMasked512 x y (VPMOVVec64x8ToM mask)) + for { + x := v_0 + y := v_1 + mask := v_2 + v.reset(OpAMD64VPXORQMasked512) + v0 := b.NewValue0(v.Pos, OpAMD64VPMOVVec64x8ToM, types.TypeMask) + v0.AddArg(mask) + v.AddArg3(x, y, v0) + return true + } } func rewriteValueAMD64_OpMax32F(v *Value) bool { v_1 := v.Args[1] @@ -27737,6 +49078,530 @@ func rewriteValueAMD64_OpNot(v *Value) bool { return true } } +func rewriteValueAMD64_OpNotEqualFloat32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualFloat32x16 x y) + // result: (VPMOVMToVec32x16 (VCMPPS512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPS512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat32x4 x y) + // result: (VCMPPS128 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS128) + v.AuxInt = int8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat32x8 x y) + // result: (VCMPPS256 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPS256) + v.AuxInt = int8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat64x2 x y) + // result: (VCMPPD128 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD128) + v.AuxInt = int8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + // match: (NotEqualFloat64x4 x y) + // result: (VCMPPD256 [4] x y) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VCMPPD256) + v.AuxInt = int8ToAuxInt(4) + v.AddArg2(x, y) + return true + } +} +func rewriteValueAMD64_OpNotEqualFloat64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualFloat64x8 x y) + // result: (VPMOVMToVec64x8 (VCMPPD512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VCMPPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPW256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPW512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPW128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPD512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPD128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPD256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPQ128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPQ256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPQ512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPB128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPB256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualInt8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualInt8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPB512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint16x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint16x16 x y) + // result: (VPMOVMToVec16x16 (VPCMPUW256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint16x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint16x32 x y) + // result: (VPMOVMToVec16x32 (VPCMPUW512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint16x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint16x8 x y) + // result: (VPMOVMToVec16x8 (VPCMPUW128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec16x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUW128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint32x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint32x16 x y) + // result: (VPMOVMToVec32x16 (VPCMPUD512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint32x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint32x4 x y) + // result: (VPMOVMToVec32x4 (VPCMPUD128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint32x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint32x8 x y) + // result: (VPMOVMToVec32x8 (VPCMPUD256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec32x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUD256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint64x2(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint64x2 x y) + // result: (VPMOVMToVec64x2 (VPCMPUQ128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x2) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint64x4(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint64x4 x y) + // result: (VPMOVMToVec64x4 (VPCMPUQ256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x4) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint64x8(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint64x8 x y) + // result: (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec64x8) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUQ512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint8x16(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint8x16 x y) + // result: (VPMOVMToVec8x16 (VPCMPUB128 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x16) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB128, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint8x32(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint8x32 x y) + // result: (VPMOVMToVec8x32 (VPCMPUB256 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x32) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB256, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} +func rewriteValueAMD64_OpNotEqualUint8x64(v *Value) bool { + v_1 := v.Args[1] + v_0 := v.Args[0] + b := v.Block + typ := &b.Func.Config.Types + // match: (NotEqualUint8x64 x y) + // result: (VPMOVMToVec8x64 (VPCMPUB512 [4] x y)) + for { + x := v_0 + y := v_1 + v.reset(OpAMD64VPMOVMToVec8x64) + v0 := b.NewValue0(v.Pos, OpAMD64VPCMPUB512, typ.Mask) + v0.AuxInt = int8ToAuxInt(4) + v0.AddArg2(x, y) + v.AddArg(v0) + return true + } +} func rewriteValueAMD64_OpOffPtr(v *Value) bool { v_0 := v.Args[0] b := v.Block @@ -27851,6 +49716,132 @@ func rewriteValueAMD64_OpPopCount8(v *Value) bool { return true } } +func rewriteValueAMD64_OpRoundFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat32x4 x) + // result: (VROUNDPS128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = int8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat32x8 x) + // result: (VROUNDPS256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = int8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat64x2 x) + // result: (VROUNDPD128 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = int8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundFloat64x4 x) + // result: (VROUNDPD256 [0] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = int8ToAuxInt(0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+8] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 8) + v.AddArg(x) + return true + } +} func rewriteValueAMD64_OpRoundToEven(v *Value) bool { v_0 := v.Args[0] // match: (RoundToEven x) @@ -27863,6 +49854,84 @@ func rewriteValueAMD64_OpRoundToEven(v *Value) bool { return true } } +func rewriteValueAMD64_OpRoundWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpRoundWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (RoundWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+0] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 0) + v.AddArg(x) + return true + } +} func rewriteValueAMD64_OpRsh16Ux16(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -29764,6 +51833,51 @@ func rewriteValueAMD64_OpStore(v *Value) bool { v.AddArg3(ptr, val, mem) return true } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 16 + // result: (VMOVDQUstore128 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64VMOVDQUstore128) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 32 + // result: (VMOVDQUstore256 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64VMOVDQUstore256) + v.AddArg3(ptr, val, mem) + return true + } + // match: (Store {t} ptr val mem) + // cond: t.Size() == 64 + // result: (VMOVDQUstore512 ptr val mem) + for { + t := auxToType(v.Aux) + ptr := v_0 + val := v_1 + mem := v_2 + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64VMOVDQUstore512) + v.AddArg3(ptr, val, mem) + return true + } return false } func rewriteValueAMD64_OpTrunc(v *Value) bool { @@ -29778,6 +51892,210 @@ func rewriteValueAMD64_OpTrunc(v *Value) bool { return true } } +func rewriteValueAMD64_OpTruncFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat32x4 x) + // result: (VROUNDPS128 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS128) + v.AuxInt = int8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat32x8 x) + // result: (VROUNDPS256 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPS256) + v.AuxInt = int8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat64x2 x) + // result: (VROUNDPD128 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD128) + v.AuxInt = int8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncFloat64x4 x) + // result: (VROUNDPD256 [3] x) + for { + x := v_0 + v.reset(OpAMD64VROUNDPD256) + v.AuxInt = int8ToAuxInt(3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncSuppressExceptionWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncSuppressExceptionWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncSuppressExceptionWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncSuppressExceptionWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncSuppressExceptionWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncSuppressExceptionWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncSuppressExceptionWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+11] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 11) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncWithPrecisionFloat32x16(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncWithPrecisionFloat32x16 [a] x) + // result: (VRNDSCALEPS512 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS512) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncWithPrecisionFloat32x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncWithPrecisionFloat32x4 [a] x) + // result: (VRNDSCALEPS128 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS128) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncWithPrecisionFloat32x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncWithPrecisionFloat32x8 [a] x) + // result: (VRNDSCALEPS256 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPS256) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncWithPrecisionFloat64x2(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncWithPrecisionFloat64x2 [a] x) + // result: (VRNDSCALEPD128 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD128) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncWithPrecisionFloat64x4(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncWithPrecisionFloat64x4 [a] x) + // result: (VRNDSCALEPD256 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD256) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} +func rewriteValueAMD64_OpTruncWithPrecisionFloat64x8(v *Value) bool { + v_0 := v.Args[0] + // match: (TruncWithPrecisionFloat64x8 [a] x) + // result: (VRNDSCALEPD512 [a+3] x) + for { + a := auxIntToInt8(v.AuxInt) + x := v_0 + v.reset(OpAMD64VRNDSCALEPD512) + v.AuxInt = int8ToAuxInt(a + 3) + v.AddArg(x) + return true + } +} func rewriteValueAMD64_OpZero(v *Value) bool { v_1 := v.Args[1] v_0 := v.Args[0] @@ -30117,6 +52435,45 @@ func rewriteValueAMD64_OpZero(v *Value) bool { } return false } +func rewriteValueAMD64_OpZeroSIMD(v *Value) bool { + // match: (ZeroSIMD ) + // cond: t.Size() == 16 + // result: (Zero128 ) + for { + t := v.Type + if !(t.Size() == 16) { + break + } + v.reset(OpAMD64Zero128) + v.Type = t + return true + } + // match: (ZeroSIMD ) + // cond: t.Size() == 32 + // result: (Zero256 ) + for { + t := v.Type + if !(t.Size() == 32) { + break + } + v.reset(OpAMD64Zero256) + v.Type = t + return true + } + // match: (ZeroSIMD ) + // cond: t.Size() == 64 + // result: (Zero512 ) + for { + t := v.Type + if !(t.Size() == 64) { + break + } + v.reset(OpAMD64Zero512) + v.Type = t + return true + } + return false +} func rewriteBlockAMD64(b *Block) bool { typ := &b.Func.Config.Types switch b.Kind { diff --git a/src/cmd/compile/internal/ssa/rewritegeneric.go b/src/cmd/compile/internal/ssa/rewritegeneric.go index bfbd3c8522ed24..b7a4ff95d1af63 100644 --- a/src/cmd/compile/internal/ssa/rewritegeneric.go +++ b/src/cmd/compile/internal/ssa/rewritegeneric.go @@ -14149,11 +14149,11 @@ func rewriteValuegeneric_OpLoad(v *Value) bool { return true } // match: (Load _ _) - // cond: t.IsStruct() && CanSSA(t) + // cond: t.IsStruct() && CanSSA(t) && !t.IsSIMD() // result: rewriteStructLoad(v) for { t := v.Type - if !(t.IsStruct() && CanSSA(t)) { + if !(t.IsStruct() && CanSSA(t) && !t.IsSIMD()) { break } v.copyOf(rewriteStructLoad(v)) diff --git a/src/cmd/compile/internal/ssa/value.go b/src/cmd/compile/internal/ssa/value.go index e80b712ddba764..8f921a80037a77 100644 --- a/src/cmd/compile/internal/ssa/value.go +++ b/src/cmd/compile/internal/ssa/value.go @@ -596,6 +596,9 @@ func AutoVar(v *Value) (*ir.Name, int64) { // CanSSA reports whether values of type t can be represented as a Value. func CanSSA(t *types.Type) bool { types.CalcSize(t) + if t.IsSIMD() { + return true + } if t.Size() > int64(4*types.PtrSize) { // 4*Widthptr is an arbitrary constant. We want it // to be at least 3*Widthptr so slices can be registerized. diff --git a/src/cmd/compile/internal/ssagen/intrinsics.go b/src/cmd/compile/internal/ssagen/intrinsics.go index 6b58e7e5914538..186cfc4865ed18 100644 --- a/src/cmd/compile/internal/ssagen/intrinsics.go +++ b/src/cmd/compile/internal/ssagen/intrinsics.go @@ -1602,6 +1602,112 @@ func initIntrinsics(cfg *intrinsicBuildConfig) { return s.newValue1(ssa.OpZeroExt8to64, types.Types[types.TUINT64], out) }, sys.AMD64) + + if buildcfg.Experiment.SIMD { + // Only enable intrinsics, if SIMD experiment. + simdIntrinsics(addF) + } +} + +func opLen1(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue1(op, t, args[0]) + } +} + +func opLen2(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue2(op, t, args[0], args[1]) + } +} + +func opLen3(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue3(op, t, args[0], args[1], args[2]) + } +} + +func opLen4(op ssa.Op, t *types.Type) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return s.newValue4(op, t, args[0], args[1], args[2], args[3]) + } +} + +func plainPanicSimdImm(s *state) { + cmp := s.newValue0(ssa.OpConstBool, types.Types[types.TBOOL]) + cmp.AuxInt = 1 + // TODO: make this a standalone panic instead of reusing the overflow panic. + // Or maybe after we implement the switch table this will be obsolete anyway. + s.check(cmp, ir.Syms.Panicoverflow) +} + +func opLen1Imm8(op ssa.Op, t *types.Type, offset int) func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + return func(s *state, n *ir.CallExpr, args []*ssa.Value) *ssa.Value { + if args[1].Op == ssa.OpConst8 { + return s.newValue1I(op, t, args[1].AuxInt<= 1: + // This gates the experiment -- without it, no user-visible types can be "simd". + // The SSA-visible SIMD types remain. + // TODO after simd has been moved to package simd, remove internal/simd. + switch sym.Name { + case "v128": + simdify(t, true) + return + case "v256": + simdify(t, true) + return + case "v512": + simdify(t, true) + return + } } } fields := t.Fields() + size := calcStructOffset(t, fields, 0) // For non-zero-sized structs which end in a zero-sized field, we @@ -540,6 +587,11 @@ func CalcStructSize(t *Type) { break } } + + if len(t.Fields()) >= 1 && t.Fields()[0].Type.isSIMDTag { + // this catches `type Foo simd.Whatever` -- Foo is also SIMD. + simdify(t, false) + } } // CalcArraySize calculates the size of t, diff --git a/src/cmd/compile/internal/types/type.go b/src/cmd/compile/internal/types/type.go index c4080ed0b526ae..f7b9b0f3f75940 100644 --- a/src/cmd/compile/internal/types/type.go +++ b/src/cmd/compile/internal/types/type.go @@ -201,8 +201,9 @@ type Type struct { intRegs, floatRegs uint8 // registers needed for ABIInternal - flags bitset8 - alg AlgKind // valid if Align > 0 + flags bitset8 + alg AlgKind // valid if Align > 0 + isSIMDTag, isSIMD bool // tag is the marker type, isSIMD means has marker type // size of prefix of object that contains all pointers. valid if Align > 0. // Note that for pointers, this is always PtrSize even if the element type @@ -605,6 +606,12 @@ func newSSA(name string) *Type { return t } +func newSIMD(name string) *Type { + t := newSSA(name) + t.isSIMD = true + return t +} + // NewMap returns a new map Type with key type k and element (aka value) type v. func NewMap(k, v *Type) *Type { t := newType(TMAP) @@ -995,10 +1002,7 @@ func (t *Type) ArgWidth() int64 { func (t *Type) Size() int64 { if t.kind == TSSA { - if t == TypeInt128 { - return 16 - } - return 0 + return t.width } CalcSize(t) return t.width @@ -1626,12 +1630,26 @@ var ( TypeFlags = newSSA("flags") TypeVoid = newSSA("void") TypeInt128 = newSSA("int128") + TypeVec128 = newSIMD("vec128") + TypeVec256 = newSIMD("vec256") + TypeVec512 = newSIMD("vec512") + TypeMask = newSIMD("mask") // not a vector, not 100% sure what this should be. TypeResultMem = newResults([]*Type{TypeMem}) ) func init() { TypeInt128.width = 16 TypeInt128.align = 8 + + TypeVec128.width = 16 + TypeVec128.align = 8 + TypeVec256.width = 32 + TypeVec256.align = 8 + TypeVec512.width = 64 + TypeVec512.align = 8 + + TypeMask.width = 8 // This will depend on the architecture; spilling will be "interesting". + TypeMask.align = 8 } // NewNamed returns a new named type for the given type name. obj should be an @@ -2017,3 +2035,7 @@ var SimType [NTYPE]Kind // Fake package for shape types (see typecheck.Shapify()). var ShapePkg = NewPkg("go.shape", "go.shape") + +func (t *Type) IsSIMD() bool { + return t.isSIMD +} diff --git a/src/cmd/dist/test.go b/src/cmd/dist/test.go index 637433d45135a2..e7f7d98afdc77c 100644 --- a/src/cmd/dist/test.go +++ b/src/cmd/dist/test.go @@ -939,7 +939,9 @@ func (t *tester) registerTests() { // which is darwin,linux,windows/amd64 and darwin/arm64. // // The same logic applies to the release notes that correspond to each api/next file. - if goos == "darwin" || ((goos == "linux" || goos == "windows") && goarch == "amd64") { + // + // TODO: remove the exclusion of goexperiment simd right before dev.simd branch is merged to master. + if goos == "darwin" || ((goos == "linux" || goos == "windows") && (goarch == "amd64" && !strings.Contains(goexperiment, "simd"))) { t.registerTest("API release note check", &goTest{variant: "check", pkg: "cmd/relnote", testFlags: []string{"-check"}}) t.registerTest("API check", &goTest{variant: "check", pkg: "cmd/api", timeout: 5 * time.Minute, testFlags: []string{"-check"}}) } diff --git a/src/go/build/deps_test.go b/src/go/build/deps_test.go index 6d92542e31b652..d62f177b1a024a 100644 --- a/src/go/build/deps_test.go +++ b/src/go/build/deps_test.go @@ -70,6 +70,8 @@ var depsRules = ` internal/goarch < internal/abi; internal/byteorder, internal/cpu, internal/goarch < internal/chacha8rand; + internal/cpu < simd; + # RUNTIME is the core runtime group of packages, all of them very light-weight. internal/abi, internal/chacha8rand, diff --git a/src/go/doc/comment/std.go b/src/go/doc/comment/std.go index 191e1f129107de..73cf9627a02b58 100644 --- a/src/go/doc/comment/std.go +++ b/src/go/doc/comment/std.go @@ -35,6 +35,7 @@ var stdPkgs = []string{ "reflect", "regexp", "runtime", + "simd", "slices", "sort", "strconv", diff --git a/src/internal/buildcfg/exp.go b/src/internal/buildcfg/exp.go index e36ec08a5b0232..17a02415c42b07 100644 --- a/src/internal/buildcfg/exp.go +++ b/src/internal/buildcfg/exp.go @@ -84,6 +84,7 @@ func ParseGOEXPERIMENT(goos, goarch, goexp string) (*ExperimentFlags, error) { AliasTypeParams: true, SwissMap: true, SyncHashTrieMap: true, + SIMD: goarch == "amd64", // TODO remove this (default to false) when dev.simd is merged Dwarf5: dwarf5Supported, } diff --git a/src/internal/cpu/cpu.go b/src/internal/cpu/cpu.go index 760dc0b469d83d..a93eb54ddf0cd7 100644 --- a/src/internal/cpu/cpu.go +++ b/src/internal/cpu/cpu.go @@ -31,8 +31,11 @@ var X86 struct { HasADX bool HasAVX bool HasAVX2 bool + HasAVX512 bool // Virtual feature: F+CD+BW+DQ+VL HasAVX512F bool + HasAVX512CD bool HasAVX512BW bool + HasAVX512DQ bool HasAVX512VL bool HasBMI1 bool HasBMI2 bool @@ -160,6 +163,10 @@ var RISCV64 struct { //go:linkname S390X //go:linkname RISCV64 +// doDerived, if non-nil, is called after processing GODEBUG to set "derived" +// feature flags. +var doDerived func() + // Initialize examines the processor and sets the relevant variables above. // This is called by the runtime package early in program initialization, // before normal init functions are run. env is set by runtime if the OS supports @@ -167,6 +174,9 @@ var RISCV64 struct { func Initialize(env string) { doinit() processOptions(env) + if doDerived != nil { + doDerived() + } } // options contains the cpu debug options that can be used in GODEBUG. diff --git a/src/internal/cpu/cpu_x86.go b/src/internal/cpu/cpu_x86.go index ee812076e96c49..7d6f40c1326759 100644 --- a/src/internal/cpu/cpu_x86.go +++ b/src/internal/cpu/cpu_x86.go @@ -36,7 +36,9 @@ const ( cpuid_BMI2 = 1 << 8 cpuid_ERMS = 1 << 9 cpuid_AVX512F = 1 << 16 + cpuid_AVX512DQ = 1 << 17 cpuid_ADX = 1 << 19 + cpuid_AVX512CD = 1 << 28 cpuid_SHA = 1 << 29 cpuid_AVX512BW = 1 << 30 cpuid_AVX512VL = 1 << 31 @@ -84,7 +86,9 @@ func doinit() { // they can be turned off. options = append(options, option{Name: "avx512f", Feature: &X86.HasAVX512F}, + option{Name: "avx512cd", Feature: &X86.HasAVX512CD}, option{Name: "avx512bw", Feature: &X86.HasAVX512BW}, + option{Name: "avx512dq", Feature: &X86.HasAVX512DQ}, option{Name: "avx512vl", Feature: &X86.HasAVX512VL}, ) } @@ -149,7 +153,9 @@ func doinit() { X86.HasAVX512F = isSet(ebx7, cpuid_AVX512F) && osSupportsAVX512 if X86.HasAVX512F { + X86.HasAVX512CD = isSet(ebx7, cpuid_AVX512CD) X86.HasAVX512BW = isSet(ebx7, cpuid_AVX512BW) + X86.HasAVX512DQ = isSet(ebx7, cpuid_AVX512DQ) X86.HasAVX512VL = isSet(ebx7, cpuid_AVX512VL) } @@ -164,6 +170,17 @@ func doinit() { _, _, _, edxExt1 := cpuid(0x80000001, 0) X86.HasRDTSCP = isSet(edxExt1, cpuid_RDTSCP) + + doDerived = func() { + // Rather than carefully gating on fundamental AVX-512 features, we have + // a virtual "AVX512" feature that captures F+CD+BW+DQ+VL. BW, DQ, and + // VL have a huge effect on which AVX-512 instructions are available, + // and these have all been supported on everything except the earliest + // Phi chips with AVX-512. No CPU has had CD without F, so we include + // it. GOAMD64=v4 also implies exactly this set, and these are all + // included in AVX10.1. + X86.HasAVX512 = X86.HasAVX512F && X86.HasAVX512CD && X86.HasAVX512BW && X86.HasAVX512DQ && X86.HasAVX512VL + } } func isSet(hwc uint32, value uint32) bool { diff --git a/src/internal/goexperiment/exp_simd_off.go b/src/internal/goexperiment/exp_simd_off.go new file mode 100644 index 00000000000000..ebc40b308e384d --- /dev/null +++ b/src/internal/goexperiment/exp_simd_off.go @@ -0,0 +1,8 @@ +// Code generated by mkconsts.go. DO NOT EDIT. + +//go:build !goexperiment.simd + +package goexperiment + +const SIMD = false +const SIMDInt = 0 diff --git a/src/internal/goexperiment/exp_simd_on.go b/src/internal/goexperiment/exp_simd_on.go new file mode 100644 index 00000000000000..137d1dd1ba3fba --- /dev/null +++ b/src/internal/goexperiment/exp_simd_on.go @@ -0,0 +1,8 @@ +// Code generated by mkconsts.go. DO NOT EDIT. + +//go:build goexperiment.simd + +package goexperiment + +const SIMD = true +const SIMDInt = 1 diff --git a/src/internal/goexperiment/flags.go b/src/internal/goexperiment/flags.go index ceff24193d89a5..b693ed883a51d3 100644 --- a/src/internal/goexperiment/flags.go +++ b/src/internal/goexperiment/flags.go @@ -129,4 +129,8 @@ type Flags struct { // GreenTeaGC enables the Green Tea GC implementation. GreenTeaGC bool + + // SIMD enables the simd package and the compiler's handling + // of SIMD intrinsics. + SIMD bool } diff --git a/src/runtime/mkpreempt.go b/src/runtime/mkpreempt.go index 6a9cf77a43fcf0..ec900a23d257e9 100644 --- a/src/runtime/mkpreempt.go +++ b/src/runtime/mkpreempt.go @@ -73,16 +73,14 @@ var regNamesAMD64 = []string{ "X15", } -var out io.Writer - -var arches = map[string]func(){ +var arches = map[string]func(g *gen){ "386": gen386, "amd64": genAMD64, "arm": genARM, "arm64": genARM64, "loong64": genLoong64, - "mips64x": func() { genMIPS(true) }, - "mipsx": func() { genMIPS(false) }, + "mips64x": func(g *gen) { genMIPS(g, true) }, + "mipsx": func(g *gen) { genMIPS(g, false) }, "ppc64x": genPPC64, "riscv64": genRISCV64, "s390x": genS390X, @@ -93,53 +91,58 @@ var beLe = map[string]bool{"mips64x": true, "mipsx": true, "ppc64x": true} func main() { flag.Parse() if flag.NArg() > 0 { - out = os.Stdout for _, arch := range flag.Args() { - gen, ok := arches[arch] + genFn, ok := arches[arch] if !ok { log.Fatalf("unknown arch %s", arch) } - header(arch) - gen() + g := gen{os.Stdout, arch} + g.asmHeader() + genFn(&g) } return } - for arch, gen := range arches { + for arch, genFn := range arches { f, err := os.Create(fmt.Sprintf("preempt_%s.s", arch)) if err != nil { log.Fatal(err) } - out = f - header(arch) - gen() + g := gen{f, arch} + g.asmHeader() + genFn(&g) if err := f.Close(); err != nil { log.Fatal(err) } } } -func header(arch string) { - fmt.Fprintf(out, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n") - if beLe[arch] { - base := arch[:len(arch)-1] - fmt.Fprintf(out, "//go:build %s || %sle\n\n", base, base) +type gen struct { + w io.Writer + goarch string +} + +func (g *gen) asmHeader() { + fmt.Fprintf(g.w, "// Code generated by mkpreempt.go; DO NOT EDIT.\n\n") + if beLe[g.goarch] { + base := g.goarch[:len(g.goarch)-1] + fmt.Fprintf(g.w, "//go:build %s || %sle\n\n", base, base) } - fmt.Fprintf(out, "#include \"go_asm.h\"\n") - if arch == "amd64" { - fmt.Fprintf(out, "#include \"asm_amd64.h\"\n") + fmt.Fprintf(g.w, "#include \"go_asm.h\"\n") + if g.goarch == "amd64" { + fmt.Fprintf(g.w, "#include \"asm_amd64.h\"\n") } - fmt.Fprintf(out, "#include \"textflag.h\"\n\n") - fmt.Fprintf(out, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n") + fmt.Fprintf(g.w, "#include \"textflag.h\"\n\n") + fmt.Fprintf(g.w, "TEXT ·asyncPreempt(SB),NOSPLIT|NOFRAME,$0-0\n") } -func p(f string, args ...any) { +func (g *gen) p(f string, args ...any) { fmted := fmt.Sprintf(f, args...) - fmt.Fprintf(out, "\t%s\n", strings.ReplaceAll(fmted, "\n", "\n\t")) + fmt.Fprintf(g.w, "\t%s\n", strings.ReplaceAll(fmted, "\n", "\n\t")) } -func label(l string) { - fmt.Fprintf(out, "%s\n", l) +func (g *gen) label(l string) { + fmt.Fprintf(g.w, "%s\n", l) } type layout struct { @@ -176,28 +179,30 @@ func (l *layout) addSpecial(save, restore string, size int) { l.stack += size } -func (l *layout) save() { +func (l *layout) save(g *gen) { for _, reg := range l.regs { if reg.save != "" { - p(reg.save, reg.pos) + g.p(reg.save, reg.pos) } else { - p("%s %s, %d(%s)", reg.saveOp, reg.reg, reg.pos, l.sp) + g.p("%s %s, %d(%s)", reg.saveOp, reg.reg, reg.pos, l.sp) } } } -func (l *layout) restore() { +func (l *layout) restore(g *gen) { for i := len(l.regs) - 1; i >= 0; i-- { reg := l.regs[i] if reg.restore != "" { - p(reg.restore, reg.pos) + g.p(reg.restore, reg.pos) } else { - p("%s %d(%s), %s", reg.restoreOp, reg.pos, l.sp, reg.reg) + g.p("%s %d(%s), %s", reg.restoreOp, reg.pos, l.sp, reg.reg) } } } -func gen386() { +func gen386(g *gen) { + p := g.p + p("PUSHFL") // Save general purpose registers. var l = layout{sp: "SP"} @@ -218,22 +223,24 @@ func gen386() { p("ADJSP $%d", lSSE.stack) p("NOP SP") - l.save() + l.save(g) p("#ifndef %s", softfloat) - lSSE.save() + lSSE.save(g) p("#endif") p("CALL ·asyncPreempt2(SB)") p("#ifndef %s", softfloat) - lSSE.restore() + lSSE.restore(g) p("#endif") - l.restore() + l.restore(g) p("ADJSP $%d", -lSSE.stack) p("POPFL") p("RET") } -func genAMD64() { +func genAMD64(g *gen) { + p := g.p + // Assign stack offsets. var l = layout{sp: "SP"} for _, reg := range regNamesAMD64 { @@ -262,19 +269,21 @@ func genAMD64() { p("// But vet doesn't know ADJSP, so suppress vet stack checking") p("NOP SP") - l.save() + l.save(g) - lSSE.save() + lSSE.save(g) p("CALL ·asyncPreempt2(SB)") - lSSE.restore() - l.restore() + lSSE.restore(g) + l.restore(g) p("ADJSP $%d", -lSSE.stack) p("POPFQ") p("POPQ BP") p("RET") } -func genARM() { +func genARM(g *gen) { + p := g.p + // Add integer registers R0-R12. // R13 (SP), R14 (LR), R15 (PC) are special and not saved here. var l = layout{sp: "R13", stack: 4} // add LR slot @@ -303,22 +312,23 @@ func genARM() { } p("MOVW.W R14, -%d(R13)", lfp.stack) // allocate frame, save LR - l.save() + l.save(g) p("MOVB ·goarmsoftfp(SB), R0\nCMP $0, R0\nBNE nofp") // test goarmsoftfp, and skip FP registers if goarmsoftfp!=0. - lfp.save() - label("nofp:") + lfp.save(g) + g.label("nofp:") p("CALL ·asyncPreempt2(SB)") p("MOVB ·goarmsoftfp(SB), R0\nCMP $0, R0\nBNE nofp2") // test goarmsoftfp, and skip FP registers if goarmsoftfp!=0. - lfp.restore() - label("nofp2:") - l.restore() + lfp.restore(g) + g.label("nofp2:") + l.restore(g) p("MOVW %d(R13), R14", lfp.stack) // sigctxt.pushCall pushes LR on stack, restore it p("MOVW.P %d(R13), R15", lfp.stack+4) // load PC, pop frame (including the space pushed by sigctxt.pushCall) p("UNDEF") // shouldn't get here } -func genARM64() { +func genARM64(g *gen) { + p := g.p // Add integer registers R0-R26 // R27 (REGTMP), R28 (g), R29 (FP), R30 (LR), R31 (SP) are special // and not saved here. @@ -362,9 +372,9 @@ func genARM64() { p("MOVD R30, (RSP)") p("#endif") - l.save() + l.save(g) p("CALL ·asyncPreempt2(SB)") - l.restore() + l.restore(g) p("MOVD %d(RSP), R30", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it p("MOVD -8(RSP), R29") // restore frame pointer @@ -373,7 +383,9 @@ func genARM64() { p("RET (R27)") } -func genMIPS(_64bit bool) { +func genMIPS(g *gen, _64bit bool) { + p := g.p + mov := "MOVW" movf := "MOVF" add := "ADD" @@ -428,15 +440,15 @@ func genMIPS(_64bit bool) { p(mov+" R31, -%d(R29)", lfp.stack) p(sub+" $%d, R29", lfp.stack) - l.save() + l.save(g) p("#ifndef %s", softfloat) - lfp.save() + lfp.save(g) p("#endif") p("CALL ·asyncPreempt2(SB)") p("#ifndef %s", softfloat) - lfp.restore() + lfp.restore(g) p("#endif") - l.restore() + l.restore(g) p(mov+" %d(R29), R31", lfp.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it p(mov + " (R29), R23") // load PC to REGTMP @@ -444,7 +456,9 @@ func genMIPS(_64bit bool) { p("JMP (R23)") } -func genLoong64() { +func genLoong64(g *gen) { + p := g.p + mov := "MOVV" movf := "MOVD" add := "ADDV" @@ -478,9 +492,9 @@ func genLoong64() { p(mov+" R1, -%d(R3)", l.stack) p(sub+" $%d, R3", l.stack) - l.save() + l.save(g) p("CALL ·asyncPreempt2(SB)") - l.restore() + l.restore(g) p(mov+" %d(R3), R1", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it p(mov + " (R3), R30") // load PC to REGTMP @@ -488,7 +502,9 @@ func genLoong64() { p("JMP (R30)") } -func genPPC64() { +func genPPC64(g *gen) { + p := g.p + // Add integer registers R3-R29 // R0 (zero), R1 (SP), R30 (g) are special and not saved here. // R2 (TOC pointer in PIC mode), R12 (function entry address in PIC mode) have been saved in sigctxt.pushCall. @@ -528,9 +544,9 @@ func genPPC64() { p("MOVD LR, R31") p("MOVDU R31, -%d(R1)", l.stack) // allocate frame, save PC of interrupted instruction (in LR) - l.save() + l.save(g) p("CALL ·asyncPreempt2(SB)") - l.restore() + l.restore(g) p("MOVD %d(R1), R31", l.stack) // sigctxt.pushCall has pushed LR, R2, R12 (at interrupt) on stack, restore them p("MOVD R31, LR") @@ -543,7 +559,9 @@ func genPPC64() { p("JMP (CTR)") } -func genRISCV64() { +func genRISCV64(g *gen) { + p := g.p + // X0 (zero), X1 (LR), X2 (SP), X3 (GP), X4 (TP), X27 (g), X31 (TMP) are special. var l = layout{sp: "X2", stack: 8} @@ -564,16 +582,18 @@ func genRISCV64() { p("MOV X1, -%d(X2)", l.stack) p("SUB $%d, X2", l.stack) - l.save() + l.save(g) p("CALL ·asyncPreempt2(SB)") - l.restore() + l.restore(g) p("MOV %d(X2), X1", l.stack) p("MOV (X2), X31") p("ADD $%d, X2", l.stack+8) p("JMP (X31)") } -func genS390X() { +func genS390X(g *gen) { + p := g.p + // Add integer registers R0-R12 // R13 (g), R14 (LR), R15 (SP) are special, and not saved here. // Saving R10 (REGTMP) is not necessary, but it is saved anyway. @@ -594,9 +614,9 @@ func genS390X() { p("ADD $-%d, R15", l.stack) p("MOVW R10, 8(R15)") // save flags - l.save() + l.save(g) p("CALL ·asyncPreempt2(SB)") - l.restore() + l.restore(g) p("MOVD %d(R15), R14", l.stack) // sigctxt.pushCall has pushed LR (at interrupt) on stack, restore it p("ADD $%d, R15", l.stack+8) // pop frame (including the space pushed by sigctxt.pushCall) @@ -606,12 +626,14 @@ func genS390X() { p("JMP (R10)") } -func genWasm() { +func genWasm(g *gen) { + p := g.p p("// No async preemption on wasm") p("UNDEF") } -func notImplemented() { +func notImplemented(g *gen) { + p := g.p p("// Not implemented yet") p("JMP ·abort(SB)") } diff --git a/src/simd/cpu.go b/src/simd/cpu.go new file mode 100644 index 00000000000000..52a5614e68eac4 --- /dev/null +++ b/src/simd/cpu.go @@ -0,0 +1,20 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build goexperiment.simd + +// The build condition == if the experiment is not on, cmd/api TestCheck will see this and complain +// see also go/doc/comment, where "simd" is inserted to the package list of the experiment is not on. + +package simd + +import "internal/cpu" + +func HasAVX512BW() bool { + return cpu.X86.HasAVX512BW +} + +func HasAVX512VL() bool { + return cpu.X86.HasAVX512VL +} diff --git a/src/simd/dummy.s b/src/simd/dummy.s new file mode 100644 index 00000000000000..f78313afee7f7f --- /dev/null +++ b/src/simd/dummy.s @@ -0,0 +1,7 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build amd64 + +// Empty file to allow bodyless functions. diff --git a/src/simd/genslice.go b/src/simd/genslice.go new file mode 100644 index 00000000000000..77b9b41c09754e --- /dev/null +++ b/src/simd/genslice.go @@ -0,0 +1,117 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build ignore + +package main + +// this generates all the code to load and store simd +// vectors to/from slices. + +import ( + "bytes" + "flag" + "fmt" + "go/format" + "io" + "os" + "strings" +) + +// //go:noescape +// func LoadUint8x16Slice(s []uint8) Uint8x16 { +// return LoadUint8x16((*[16]uint8)(s[:16])) +// } + +// //go:noescape +// func (x Uint8x16) StoreSlice(s []uint8) { +// x.Store((*[16]uint8)(s[:16])) +// } + +func slice(e string, w, c int, out io.Writer) { + b := w * c + if b < 128 || b > 512 { + return + } + E := strings.ToUpper(e[:1]) + e[1:] + t := fmt.Sprintf("%s%d", e, w) + v := fmt.Sprintf("%s%dx%d", E, w, c) + a := "a" + if strings.Contains("aeiou", e[:1]) { + a = "an" + } + fmt.Fprintf(out, + ` +// Load%sSlice loads %s %s from a slice of at least %d %ss +func Load%sSlice(s []%s) %s { + return Load%s((*[%d]%s)(s)) +} +`, v, a, v, c, t, v, t, v, v, c, t) + + fmt.Fprintf(out, + ` +// StoreSlice stores x into a slice of at least %d %ss +func (x %s) StoreSlice(s []%s) { + x.Store((*[%d]%s)(s)) +} +`, c, t, v, t, c, t) + +} + +func prologue(s string, out io.Writer) { + fmt.Fprintf(out, + `// Code generated by '%s'; DO NOT EDIT. + +//go:build goexperiment.simd + +// The build condition == if the experiment is not on, cmd/api TestCheck will see this and complain +// see also go/doc/comment, where "simd" is inserted to the package list of the experiment is not on. + +package simd + +`, s) +} + +func main() { + filename := flag.String("o", "", "write generated code to this file") + flag.Parse() + + ofile := os.Stdout + + if *filename != "" { + var err error + ofile, err = os.Create(*filename) + if err != nil { + fmt.Fprintf(os.Stderr, "Could not create the output file for the generated code, %v", err) + os.Exit(1) + } + } + + out := new(bytes.Buffer) + + prologue("go run genslice.go -o slice_amd64.go", out) + + vecs := []int{128, 256, 512} + ints := []int{8, 16, 32, 64} + floats := []int{32, 64} + for _, v := range vecs { + for _, w := range ints { + c := v / w + slice("int", w, c, out) + slice("uint", w, c, out) + } + for _, w := range floats { + c := v / w + slice("float", w, c, out) + } + } + b, err := format.Source(out.Bytes()) + if err != nil { + fmt.Fprintf(os.Stderr, "There was a problem formatting the generated code, %v", err) + os.Exit(1) + } else { + ofile.Write(b) + ofile.Close() + } +} diff --git a/src/simd/no_tag.go b/src/simd/no_tag.go new file mode 100644 index 00000000000000..c11fd51b2345d6 --- /dev/null +++ b/src/simd/no_tag.go @@ -0,0 +1,9 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package simd + +// This file has no build tag, so that go generate can run without a build tag. + +//go:generate go run genslice.go -o slice_amd64.go diff --git a/src/simd/simd_test.go b/src/simd/simd_test.go new file mode 100644 index 00000000000000..37e07c96d78618 --- /dev/null +++ b/src/simd/simd_test.go @@ -0,0 +1,228 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build goexperiment.simd + +package simd_test + +import ( + "simd" + "testing" +) + +func TestType(t *testing.T) { + // Testing: + // - Defined as another struct's field is safe + // - Pointer is safe. + // - typedef is safe + // - type alias is safe + // - type conversion is safe + type alias = simd.Int32x4 + type maskT simd.Mask32x4 + type myStruct struct { + x alias + y *simd.Int32x4 + z maskT + } + vals := [4]int32{1, 2, 3, 4} + v := myStruct{x: simd.LoadInt32x4(&vals)} + // masking elements 1 and 2. + maskv := [4]int32{-1, -1, 0, 0} + want := []int32{2, 4, 0, 0} + y := simd.LoadInt32x4(&vals) + v.y = &y + + if !simd.HasAVX512BW() || !simd.HasAVX512VL() { + t.Skip("Test requires HasAVX512BW+VL, not available on this hardware") + return + } + v.z = maskT(simd.LoadInt32x4(&maskv).AsMask32x4()) + *v.y = v.y.MaskedAdd(v.x, simd.Mask32x4(v.z)) + + got := [4]int32{} + v.y.Store(&got) + for i := range 4 { + if want[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i]) + } + } +} + +func TestAdd(t *testing.T) { + xv := [4]int32{1, 2, 3, 4} + yv := [4]int32{5, 6, 7, 8} + want := []int32{6, 8, 10, 12} + x := simd.LoadInt32x4(&xv) + y := simd.LoadInt32x4(&yv) + x = x.Add(y) + got := [4]int32{} + x.Store(&got) + for i := range 4 { + if want[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i]) + } + } +} + +func TestVectorConversion(t *testing.T) { + if !simd.HasAVX512BW() || !simd.HasAVX512VL() { + t.Skip("Test requires HasAVX512BW+VL, not available on this hardware") + return + } + xv := [4]int32{1, 2, 3, 4} + x := simd.LoadInt32x4(&xv) + xPromoted := x.AsInt64x2() + xPromotedDemoted := xPromoted.AsInt32x4() + got := [4]int32{} + xPromotedDemoted.Store(&got) + for i := range 4 { + if xv[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, xv[i], got[i]) + } + } +} + +func TestMaskConversion(t *testing.T) { + if !simd.HasAVX512BW() || !simd.HasAVX512VL() { + t.Skip("Test requires HasAVX512BW+VL, not available on this hardware") + return + } + v := [4]int32{1, 0, 1, 0} + x := simd.LoadInt32x4(&v) + var y simd.Int32x4 + mask := y.Sub(x).AsMask32x4() + v = [4]int32{5, 6, 7, 8} + y = simd.LoadInt32x4(&v) + y = y.MaskedAdd(x, mask) + got := [4]int32{6, 0, 8, 0} + y.Store(&v) + for i := range 4 { + if v[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, v[i], got[i]) + } + } +} + +func TestMaskedAdd(t *testing.T) { + if !simd.HasAVX512BW() || !simd.HasAVX512VL() { + t.Skip("Test requires HasAVX512BW+VL, not available on this hardware") + return + } + xv := [4]int32{1, 2, 3, 4} + yv := [4]int32{5, 6, 7, 8} + // masking elements 1 and 2. + maskv := [4]int32{-1, -1, 0, 0} + want := []int32{6, 8, 0, 0} + x := simd.LoadInt32x4(&xv) + y := simd.LoadInt32x4(&yv) + mask := simd.LoadInt32x4(&maskv).AsMask32x4() + x = x.MaskedAdd(y, mask) + got := [4]int32{} + x.Store(&got) + for i := range 4 { + if want[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i]) + } + } +} + +func TestCompare(t *testing.T) { + xv := [4]int32{5, 1, 5, 3} + yv := [4]int32{3, 3, 3, 3} + want := []int32{8, 0, 8, 0} + x := simd.LoadInt32x4(&xv) + y := simd.LoadInt32x4(&yv) + if !simd.HasAVX512BW() { + t.Skip("Test requires HasAVX512BW, not available on this hardware") + return + } + mask := x.Greater(y) + x = x.MaskedAdd(y, mask) + got := [4]int32{} + x.Store(&got) + for i := range 4 { + if want[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i]) + } + } +} + +func TestSub(t *testing.T) { + xv := [4]int32{5, 5, 5, 3} + yv := [4]int32{3, 3, 3, 3} + want := []int32{2, 2, 2, 0} + x := simd.LoadInt32x4(&xv) + y := simd.LoadInt32x4(&yv) + x = x.Sub(y) + got := [4]int32{} + x.Store(&got) + for i := range 4 { + if want[i] != got[i] { + t.Errorf("Result at %d incorrect: want %d, got %d", i, want[i], got[i]) + } + } +} + +// checkInt8Slices ensures that b and a are equal, to the end of b. +// also serves to use the slices, to prevent accidental optimization. +func checkInt8Slices(t *testing.T, a, b []int8) { + for i := range b { + if a[i] != b[i] { + t.Errorf("a and b differ at index %d, a=%d, b=%d", i, a[i], b[i]) + } + } +} + +func TestSlicesInt8(t *testing.T) { + a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32} + v := simd.LoadInt8x32Slice(a) + b := make([]int8, 32, 32) + v.StoreSlice(b) + checkInt8Slices(t, a, b) +} + +func TestSlicesInt8TooShortLoad(t *testing.T) { + defer func() { + if r := recover(); r != nil { + t.Logf("Saw EXPECTED panic %v", r) + } else { + t.Errorf("Did not see expected panic") + } + }() + a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31} // TOO SHORT, should panic + v := simd.LoadInt8x32Slice(a) + b := make([]int8, 32, 32) + v.StoreSlice(b) + checkInt8Slices(t, a, b) +} + +func TestSlicesInt8TooShortStore(t *testing.T) { + defer func() { + if r := recover(); r != nil { + t.Logf("Saw EXPECTED panic %v", r) + } else { + t.Errorf("Did not see expected panic") + } + }() + a := []int8{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32} + v := simd.LoadInt8x32Slice(a) + b := make([]int8, 31) // TOO SHORT, should panic + v.StoreSlice(b) + checkInt8Slices(t, a, b) +} + +func TestSlicesFloat64(t *testing.T) { + a := []float64{1, 2, 3, 4, 5, 6, 7, 8} // too long, should be fine + v := simd.LoadFloat64x4Slice(a) + b := make([]float64, 4, 4) + v.StoreSlice(b) + for i := range b { + if a[i] != b[i] { + t.Errorf("a and b differ at index %d, a=%f, b=%f", i, a[i], b[i]) + } + } +} diff --git a/src/simd/slice_amd64.go b/src/simd/slice_amd64.go new file mode 100644 index 00000000000000..10050e6b9f82a2 --- /dev/null +++ b/src/simd/slice_amd64.go @@ -0,0 +1,308 @@ +// Code generated by 'go run genslice.go -o slice_amd64.go'; DO NOT EDIT. + +//go:build goexperiment.simd + +// The build condition == if the experiment is not on, cmd/api TestCheck will see this and complain +// see also go/doc/comment, where "simd" is inserted to the package list of the experiment is not on. + +package simd + +// LoadInt8x16Slice loads an Int8x16 from a slice of at least 16 int8s +func LoadInt8x16Slice(s []int8) Int8x16 { + return LoadInt8x16((*[16]int8)(s)) +} + +// StoreSlice stores x into a slice of at least 16 int8s +func (x Int8x16) StoreSlice(s []int8) { + x.Store((*[16]int8)(s)) +} + +// LoadUint8x16Slice loads an Uint8x16 from a slice of at least 16 uint8s +func LoadUint8x16Slice(s []uint8) Uint8x16 { + return LoadUint8x16((*[16]uint8)(s)) +} + +// StoreSlice stores x into a slice of at least 16 uint8s +func (x Uint8x16) StoreSlice(s []uint8) { + x.Store((*[16]uint8)(s)) +} + +// LoadInt16x8Slice loads an Int16x8 from a slice of at least 8 int16s +func LoadInt16x8Slice(s []int16) Int16x8 { + return LoadInt16x8((*[8]int16)(s)) +} + +// StoreSlice stores x into a slice of at least 8 int16s +func (x Int16x8) StoreSlice(s []int16) { + x.Store((*[8]int16)(s)) +} + +// LoadUint16x8Slice loads an Uint16x8 from a slice of at least 8 uint16s +func LoadUint16x8Slice(s []uint16) Uint16x8 { + return LoadUint16x8((*[8]uint16)(s)) +} + +// StoreSlice stores x into a slice of at least 8 uint16s +func (x Uint16x8) StoreSlice(s []uint16) { + x.Store((*[8]uint16)(s)) +} + +// LoadInt32x4Slice loads an Int32x4 from a slice of at least 4 int32s +func LoadInt32x4Slice(s []int32) Int32x4 { + return LoadInt32x4((*[4]int32)(s)) +} + +// StoreSlice stores x into a slice of at least 4 int32s +func (x Int32x4) StoreSlice(s []int32) { + x.Store((*[4]int32)(s)) +} + +// LoadUint32x4Slice loads an Uint32x4 from a slice of at least 4 uint32s +func LoadUint32x4Slice(s []uint32) Uint32x4 { + return LoadUint32x4((*[4]uint32)(s)) +} + +// StoreSlice stores x into a slice of at least 4 uint32s +func (x Uint32x4) StoreSlice(s []uint32) { + x.Store((*[4]uint32)(s)) +} + +// LoadInt64x2Slice loads an Int64x2 from a slice of at least 2 int64s +func LoadInt64x2Slice(s []int64) Int64x2 { + return LoadInt64x2((*[2]int64)(s)) +} + +// StoreSlice stores x into a slice of at least 2 int64s +func (x Int64x2) StoreSlice(s []int64) { + x.Store((*[2]int64)(s)) +} + +// LoadUint64x2Slice loads an Uint64x2 from a slice of at least 2 uint64s +func LoadUint64x2Slice(s []uint64) Uint64x2 { + return LoadUint64x2((*[2]uint64)(s)) +} + +// StoreSlice stores x into a slice of at least 2 uint64s +func (x Uint64x2) StoreSlice(s []uint64) { + x.Store((*[2]uint64)(s)) +} + +// LoadFloat32x4Slice loads a Float32x4 from a slice of at least 4 float32s +func LoadFloat32x4Slice(s []float32) Float32x4 { + return LoadFloat32x4((*[4]float32)(s)) +} + +// StoreSlice stores x into a slice of at least 4 float32s +func (x Float32x4) StoreSlice(s []float32) { + x.Store((*[4]float32)(s)) +} + +// LoadFloat64x2Slice loads a Float64x2 from a slice of at least 2 float64s +func LoadFloat64x2Slice(s []float64) Float64x2 { + return LoadFloat64x2((*[2]float64)(s)) +} + +// StoreSlice stores x into a slice of at least 2 float64s +func (x Float64x2) StoreSlice(s []float64) { + x.Store((*[2]float64)(s)) +} + +// LoadInt8x32Slice loads an Int8x32 from a slice of at least 32 int8s +func LoadInt8x32Slice(s []int8) Int8x32 { + return LoadInt8x32((*[32]int8)(s)) +} + +// StoreSlice stores x into a slice of at least 32 int8s +func (x Int8x32) StoreSlice(s []int8) { + x.Store((*[32]int8)(s)) +} + +// LoadUint8x32Slice loads an Uint8x32 from a slice of at least 32 uint8s +func LoadUint8x32Slice(s []uint8) Uint8x32 { + return LoadUint8x32((*[32]uint8)(s)) +} + +// StoreSlice stores x into a slice of at least 32 uint8s +func (x Uint8x32) StoreSlice(s []uint8) { + x.Store((*[32]uint8)(s)) +} + +// LoadInt16x16Slice loads an Int16x16 from a slice of at least 16 int16s +func LoadInt16x16Slice(s []int16) Int16x16 { + return LoadInt16x16((*[16]int16)(s)) +} + +// StoreSlice stores x into a slice of at least 16 int16s +func (x Int16x16) StoreSlice(s []int16) { + x.Store((*[16]int16)(s)) +} + +// LoadUint16x16Slice loads an Uint16x16 from a slice of at least 16 uint16s +func LoadUint16x16Slice(s []uint16) Uint16x16 { + return LoadUint16x16((*[16]uint16)(s)) +} + +// StoreSlice stores x into a slice of at least 16 uint16s +func (x Uint16x16) StoreSlice(s []uint16) { + x.Store((*[16]uint16)(s)) +} + +// LoadInt32x8Slice loads an Int32x8 from a slice of at least 8 int32s +func LoadInt32x8Slice(s []int32) Int32x8 { + return LoadInt32x8((*[8]int32)(s)) +} + +// StoreSlice stores x into a slice of at least 8 int32s +func (x Int32x8) StoreSlice(s []int32) { + x.Store((*[8]int32)(s)) +} + +// LoadUint32x8Slice loads an Uint32x8 from a slice of at least 8 uint32s +func LoadUint32x8Slice(s []uint32) Uint32x8 { + return LoadUint32x8((*[8]uint32)(s)) +} + +// StoreSlice stores x into a slice of at least 8 uint32s +func (x Uint32x8) StoreSlice(s []uint32) { + x.Store((*[8]uint32)(s)) +} + +// LoadInt64x4Slice loads an Int64x4 from a slice of at least 4 int64s +func LoadInt64x4Slice(s []int64) Int64x4 { + return LoadInt64x4((*[4]int64)(s)) +} + +// StoreSlice stores x into a slice of at least 4 int64s +func (x Int64x4) StoreSlice(s []int64) { + x.Store((*[4]int64)(s)) +} + +// LoadUint64x4Slice loads an Uint64x4 from a slice of at least 4 uint64s +func LoadUint64x4Slice(s []uint64) Uint64x4 { + return LoadUint64x4((*[4]uint64)(s)) +} + +// StoreSlice stores x into a slice of at least 4 uint64s +func (x Uint64x4) StoreSlice(s []uint64) { + x.Store((*[4]uint64)(s)) +} + +// LoadFloat32x8Slice loads a Float32x8 from a slice of at least 8 float32s +func LoadFloat32x8Slice(s []float32) Float32x8 { + return LoadFloat32x8((*[8]float32)(s)) +} + +// StoreSlice stores x into a slice of at least 8 float32s +func (x Float32x8) StoreSlice(s []float32) { + x.Store((*[8]float32)(s)) +} + +// LoadFloat64x4Slice loads a Float64x4 from a slice of at least 4 float64s +func LoadFloat64x4Slice(s []float64) Float64x4 { + return LoadFloat64x4((*[4]float64)(s)) +} + +// StoreSlice stores x into a slice of at least 4 float64s +func (x Float64x4) StoreSlice(s []float64) { + x.Store((*[4]float64)(s)) +} + +// LoadInt8x64Slice loads an Int8x64 from a slice of at least 64 int8s +func LoadInt8x64Slice(s []int8) Int8x64 { + return LoadInt8x64((*[64]int8)(s)) +} + +// StoreSlice stores x into a slice of at least 64 int8s +func (x Int8x64) StoreSlice(s []int8) { + x.Store((*[64]int8)(s)) +} + +// LoadUint8x64Slice loads an Uint8x64 from a slice of at least 64 uint8s +func LoadUint8x64Slice(s []uint8) Uint8x64 { + return LoadUint8x64((*[64]uint8)(s)) +} + +// StoreSlice stores x into a slice of at least 64 uint8s +func (x Uint8x64) StoreSlice(s []uint8) { + x.Store((*[64]uint8)(s)) +} + +// LoadInt16x32Slice loads an Int16x32 from a slice of at least 32 int16s +func LoadInt16x32Slice(s []int16) Int16x32 { + return LoadInt16x32((*[32]int16)(s)) +} + +// StoreSlice stores x into a slice of at least 32 int16s +func (x Int16x32) StoreSlice(s []int16) { + x.Store((*[32]int16)(s)) +} + +// LoadUint16x32Slice loads an Uint16x32 from a slice of at least 32 uint16s +func LoadUint16x32Slice(s []uint16) Uint16x32 { + return LoadUint16x32((*[32]uint16)(s)) +} + +// StoreSlice stores x into a slice of at least 32 uint16s +func (x Uint16x32) StoreSlice(s []uint16) { + x.Store((*[32]uint16)(s)) +} + +// LoadInt32x16Slice loads an Int32x16 from a slice of at least 16 int32s +func LoadInt32x16Slice(s []int32) Int32x16 { + return LoadInt32x16((*[16]int32)(s)) +} + +// StoreSlice stores x into a slice of at least 16 int32s +func (x Int32x16) StoreSlice(s []int32) { + x.Store((*[16]int32)(s)) +} + +// LoadUint32x16Slice loads an Uint32x16 from a slice of at least 16 uint32s +func LoadUint32x16Slice(s []uint32) Uint32x16 { + return LoadUint32x16((*[16]uint32)(s)) +} + +// StoreSlice stores x into a slice of at least 16 uint32s +func (x Uint32x16) StoreSlice(s []uint32) { + x.Store((*[16]uint32)(s)) +} + +// LoadInt64x8Slice loads an Int64x8 from a slice of at least 8 int64s +func LoadInt64x8Slice(s []int64) Int64x8 { + return LoadInt64x8((*[8]int64)(s)) +} + +// StoreSlice stores x into a slice of at least 8 int64s +func (x Int64x8) StoreSlice(s []int64) { + x.Store((*[8]int64)(s)) +} + +// LoadUint64x8Slice loads an Uint64x8 from a slice of at least 8 uint64s +func LoadUint64x8Slice(s []uint64) Uint64x8 { + return LoadUint64x8((*[8]uint64)(s)) +} + +// StoreSlice stores x into a slice of at least 8 uint64s +func (x Uint64x8) StoreSlice(s []uint64) { + x.Store((*[8]uint64)(s)) +} + +// LoadFloat32x16Slice loads a Float32x16 from a slice of at least 16 float32s +func LoadFloat32x16Slice(s []float32) Float32x16 { + return LoadFloat32x16((*[16]float32)(s)) +} + +// StoreSlice stores x into a slice of at least 16 float32s +func (x Float32x16) StoreSlice(s []float32) { + x.Store((*[16]float32)(s)) +} + +// LoadFloat64x8Slice loads a Float64x8 from a slice of at least 8 float64s +func LoadFloat64x8Slice(s []float64) Float64x8 { + return LoadFloat64x8((*[8]float64)(s)) +} + +// StoreSlice stores x into a slice of at least 8 float64s +func (x Float64x8) StoreSlice(s []float64) { + x.Store((*[8]float64)(s)) +} diff --git a/src/simd/stubs_amd64.go b/src/simd/stubs_amd64.go new file mode 100644 index 00000000000000..cf37b5efcedd17 --- /dev/null +++ b/src/simd/stubs_amd64.go @@ -0,0 +1,9335 @@ +// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT. + +//go:build goexperiment.simd + +package simd + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PS, CPU Feature: AVX512EVEX +func (x Float32x16) ApproximateReciprocal() Float32x16 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PS, CPU Feature: AVX512EVEX +func (x Float32x16) ApproximateReciprocalOfSqrt() Float32x16 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPS, CPU Feature: AVX512EVEX +func (x Float32x16) Sqrt() Float32x16 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PS, CPU Feature: AVX512EVEX +func (x Float32x4) ApproximateReciprocal() Float32x4 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRTPS, CPU Feature: AVX +func (x Float32x4) ApproximateReciprocalOfSqrt() Float32x4 + +// Ceil rounds elements up to the nearest integer. +// Const Immediate = 2. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x4) Ceil() Float32x4 + +// Floor rounds elements down to the nearest integer. +// Const Immediate = 1. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x4) Floor() Float32x4 + +// Round rounds elements to the nearest integer. +// Const Immediate = 0. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x4) Round() Float32x4 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPS, CPU Feature: AVX +func (x Float32x4) Sqrt() Float32x4 + +// Trunc truncates elements towards zero. +// Const Immediate = 3. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x4) Trunc() Float32x4 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PS, CPU Feature: AVX512EVEX +func (x Float32x8) ApproximateReciprocal() Float32x8 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRTPS, CPU Feature: AVX +func (x Float32x8) ApproximateReciprocalOfSqrt() Float32x8 + +// Ceil rounds elements up to the nearest integer. +// Const Immediate = 2. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x8) Ceil() Float32x8 + +// Floor rounds elements down to the nearest integer. +// Const Immediate = 1. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x8) Floor() Float32x8 + +// Round rounds elements to the nearest integer. +// Const Immediate = 0. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x8) Round() Float32x8 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPS, CPU Feature: AVX +func (x Float32x8) Sqrt() Float32x8 + +// Trunc truncates elements towards zero. +// Const Immediate = 3. +// +// Asm: VROUNDPS, CPU Feature: AVX +func (x Float32x8) Trunc() Float32x8 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PD, CPU Feature: AVX512EVEX +func (x Float64x2) ApproximateReciprocal() Float64x2 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX +func (x Float64x2) ApproximateReciprocalOfSqrt() Float64x2 + +// Ceil rounds elements up to the nearest integer. +// Const Immediate = 2. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x2) Ceil() Float64x2 + +// Floor rounds elements down to the nearest integer. +// Const Immediate = 1. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x2) Floor() Float64x2 + +// Round rounds elements to the nearest integer. +// Const Immediate = 0. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x2) Round() Float64x2 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPD, CPU Feature: AVX +func (x Float64x2) Sqrt() Float64x2 + +// Trunc truncates elements towards zero. +// Const Immediate = 3. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x2) Trunc() Float64x2 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PD, CPU Feature: AVX512EVEX +func (x Float64x4) ApproximateReciprocal() Float64x4 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX +func (x Float64x4) ApproximateReciprocalOfSqrt() Float64x4 + +// Ceil rounds elements up to the nearest integer. +// Const Immediate = 2. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x4) Ceil() Float64x4 + +// Floor rounds elements down to the nearest integer. +// Const Immediate = 1. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x4) Floor() Float64x4 + +// Round rounds elements to the nearest integer. +// Const Immediate = 0. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x4) Round() Float64x4 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPD, CPU Feature: AVX +func (x Float64x4) Sqrt() Float64x4 + +// Trunc truncates elements towards zero. +// Const Immediate = 3. +// +// Asm: VROUNDPD, CPU Feature: AVX +func (x Float64x4) Trunc() Float64x4 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PD, CPU Feature: AVX512EVEX +func (x Float64x8) ApproximateReciprocal() Float64x8 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX +func (x Float64x8) ApproximateReciprocalOfSqrt() Float64x8 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPD, CPU Feature: AVX512EVEX +func (x Float64x8) Sqrt() Float64x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSW, CPU Feature: AVX2 +func (x Int16x16) Absolute() Int16x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Int16x16) PopCount() Int16x16 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSW, CPU Feature: AVX512EVEX +func (x Int16x32) Absolute() Int16x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Int16x32) PopCount() Int16x32 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSW, CPU Feature: AVX +func (x Int16x8) Absolute() Int16x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Int16x8) PopCount() Int16x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSD, CPU Feature: AVX512EVEX +func (x Int32x16) Absolute() Int32x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Int32x16) PopCount() Int32x16 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSD, CPU Feature: AVX +func (x Int32x4) Absolute() Int32x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Int32x4) PopCount() Int32x4 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSD, CPU Feature: AVX2 +func (x Int32x8) Absolute() Int32x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Int32x8) PopCount() Int32x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSQ, CPU Feature: AVX512EVEX +func (x Int64x2) Absolute() Int64x2 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Int64x2) PopCount() Int64x2 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSQ, CPU Feature: AVX512EVEX +func (x Int64x4) Absolute() Int64x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Int64x4) PopCount() Int64x4 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSQ, CPU Feature: AVX512EVEX +func (x Int64x8) Absolute() Int64x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Int64x8) PopCount() Int64x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSB, CPU Feature: AVX +func (x Int8x16) Absolute() Int8x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Int8x16) PopCount() Int8x16 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSB, CPU Feature: AVX2 +func (x Int8x32) Absolute() Int8x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Int8x32) PopCount() Int8x32 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSB, CPU Feature: AVX512EVEX +func (x Int8x64) Absolute() Int8x64 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Int8x64) PopCount() Int8x64 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Uint16x16) PopCount() Uint16x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Uint16x32) PopCount() Uint16x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Uint16x8) PopCount() Uint16x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Uint32x16) PopCount() Uint32x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Uint32x4) PopCount() Uint32x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Uint32x8) PopCount() Uint32x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Uint64x2) PopCount() Uint64x2 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Uint64x4) PopCount() Uint64x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Uint64x8) PopCount() Uint64x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Uint8x16) PopCount() Uint8x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Uint8x32) PopCount() Uint8x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Uint8x64) PopCount() Uint8x64 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x16) Add(y Float32x16) Float32x16 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPS, CPU Feature: AVX512EVEX +func (x Float32x16) And(y Float32x16) Float32x16 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPS, CPU Feature: AVX512EVEX +func (x Float32x16) AndNot(y Float32x16) Float32x16 + +// Div divides elements of two vectors. +// +// Asm: VDIVPS, CPU Feature: AVX512EVEX +func (x Float32x16) Div(y Float32x16) Float32x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) Equal(y Float32x16) Mask32x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) Greater(y Float32x16) Mask32x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) GreaterEqual(y Float32x16) Mask32x16 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) IsNan(y Float32x16) Mask32x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) Less(y Float32x16) Mask32x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) LessEqual(y Float32x16) Mask32x16 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedApproximateReciprocal(y Mask32x16) Float32x16 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedApproximateReciprocalOfSqrt(y Mask32x16) Float32x16 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedSqrt(y Mask32x16) Float32x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPS, CPU Feature: AVX512EVEX +func (x Float32x16) Max(y Float32x16) Float32x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPS, CPU Feature: AVX512EVEX +func (x Float32x16) Min(y Float32x16) Float32x16 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPS, CPU Feature: AVX512EVEX +func (x Float32x16) Mul(y Float32x16) Float32x16 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPS, CPU Feature: AVX512EVEX +func (x Float32x16) MulByPowOf2(y Float32x16) Float32x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) NotEqual(y Float32x16) Mask32x16 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPS, CPU Feature: AVX512EVEX +func (x Float32x16) Or(y Float32x16) Float32x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x16) Sub(y Float32x16) Float32x16 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPS, CPU Feature: AVX512EVEX +func (x Float32x16) Xor(y Float32x16) Float32x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX +func (x Float32x4) Add(y Float32x4) Float32x4 + +// AddSub subtracts even elements and adds odd elements of two vectors. +// +// Asm: VADDSUBPS, CPU Feature: AVX +func (x Float32x4) AddSub(y Float32x4) Float32x4 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VANDPS, CPU Feature: AVX +func (x Float32x4) And(y Float32x4) Float32x4 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPS, CPU Feature: AVX +func (x Float32x4) AndNot(y Float32x4) Float32x4 + +// Div divides elements of two vectors. +// +// Asm: VDIVPS, CPU Feature: AVX +func (x Float32x4) Div(y Float32x4) Float32x4 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) Equal(y Float32x4) Mask32x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) Greater(y Float32x4) Mask32x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) GreaterEqual(y Float32x4) Mask32x4 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) IsNan(y Float32x4) Mask32x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) Less(y Float32x4) Mask32x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) LessEqual(y Float32x4) Mask32x4 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedApproximateReciprocal(y Mask32x4) Float32x4 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedApproximateReciprocalOfSqrt(y Mask32x4) Float32x4 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedSqrt(y Mask32x4) Float32x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPS, CPU Feature: AVX +func (x Float32x4) Max(y Float32x4) Float32x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPS, CPU Feature: AVX +func (x Float32x4) Min(y Float32x4) Float32x4 + +// Mul multiplies corresponding elements of two vectors. +// +// Asm: VMULPS, CPU Feature: AVX +func (x Float32x4) Mul(y Float32x4) Float32x4 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPS, CPU Feature: AVX512EVEX +func (x Float32x4) MulByPowOf2(y Float32x4) Float32x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x4) NotEqual(y Float32x4) Mask32x4 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VORPS, CPU Feature: AVX +func (x Float32x4) Or(y Float32x4) Float32x4 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VHADDPS, CPU Feature: AVX +func (x Float32x4) PairwiseAdd(y Float32x4) Float32x4 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VHSUBPS, CPU Feature: AVX +func (x Float32x4) PairwiseSub(y Float32x4) Float32x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX +func (x Float32x4) Sub(y Float32x4) Float32x4 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VXORPS, CPU Feature: AVX +func (x Float32x4) Xor(y Float32x4) Float32x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX +func (x Float32x8) Add(y Float32x8) Float32x8 + +// AddSub subtracts even elements and adds odd elements of two vectors. +// +// Asm: VADDSUBPS, CPU Feature: AVX +func (x Float32x8) AddSub(y Float32x8) Float32x8 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VANDPS, CPU Feature: AVX +func (x Float32x8) And(y Float32x8) Float32x8 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPS, CPU Feature: AVX +func (x Float32x8) AndNot(y Float32x8) Float32x8 + +// Div divides elements of two vectors. +// +// Asm: VDIVPS, CPU Feature: AVX +func (x Float32x8) Div(y Float32x8) Float32x8 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) Equal(y Float32x8) Mask32x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) Greater(y Float32x8) Mask32x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) GreaterEqual(y Float32x8) Mask32x8 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) IsNan(y Float32x8) Mask32x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) Less(y Float32x8) Mask32x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) LessEqual(y Float32x8) Mask32x8 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedApproximateReciprocal(y Mask32x8) Float32x8 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedApproximateReciprocalOfSqrt(y Mask32x8) Float32x8 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedSqrt(y Mask32x8) Float32x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPS, CPU Feature: AVX +func (x Float32x8) Max(y Float32x8) Float32x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPS, CPU Feature: AVX +func (x Float32x8) Min(y Float32x8) Float32x8 + +// Mul multiplies corresponding elements of two vectors. +// +// Asm: VMULPS, CPU Feature: AVX +func (x Float32x8) Mul(y Float32x8) Float32x8 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPS, CPU Feature: AVX512EVEX +func (x Float32x8) MulByPowOf2(y Float32x8) Float32x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPS, CPU Feature: AVX +func (x Float32x8) NotEqual(y Float32x8) Mask32x8 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VORPS, CPU Feature: AVX +func (x Float32x8) Or(y Float32x8) Float32x8 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VHADDPS, CPU Feature: AVX +func (x Float32x8) PairwiseAdd(y Float32x8) Float32x8 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VHSUBPS, CPU Feature: AVX +func (x Float32x8) PairwiseSub(y Float32x8) Float32x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX +func (x Float32x8) Sub(y Float32x8) Float32x8 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VXORPS, CPU Feature: AVX +func (x Float32x8) Xor(y Float32x8) Float32x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX +func (x Float64x2) Add(y Float64x2) Float64x2 + +// AddSub subtracts even elements and adds odd elements of two vectors. +// +// Asm: VADDSUBPD, CPU Feature: AVX +func (x Float64x2) AddSub(y Float64x2) Float64x2 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VANDPD, CPU Feature: AVX +func (x Float64x2) And(y Float64x2) Float64x2 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPD, CPU Feature: AVX +func (x Float64x2) AndNot(y Float64x2) Float64x2 + +// Div divides elements of two vectors. +// +// Asm: VDIVPD, CPU Feature: AVX +func (x Float64x2) Div(y Float64x2) Float64x2 + +// DotProdBroadcast multiplies all elements and broadcasts the sum. +// Const Immediate = 127. +// +// Asm: VDPPD, CPU Feature: AVX +func (x Float64x2) DotProdBroadcast(y Float64x2) Float64x2 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) Equal(y Float64x2) Mask64x2 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) Greater(y Float64x2) Mask64x2 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) GreaterEqual(y Float64x2) Mask64x2 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) IsNan(y Float64x2) Mask64x2 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) Less(y Float64x2) Mask64x2 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) LessEqual(y Float64x2) Mask64x2 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedApproximateReciprocal(y Mask64x2) Float64x2 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedApproximateReciprocalOfSqrt(y Mask64x2) Float64x2 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedSqrt(y Mask64x2) Float64x2 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPD, CPU Feature: AVX +func (x Float64x2) Max(y Float64x2) Float64x2 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPD, CPU Feature: AVX +func (x Float64x2) Min(y Float64x2) Float64x2 + +// Mul multiplies corresponding elements of two vectors. +// +// Asm: VMULPD, CPU Feature: AVX +func (x Float64x2) Mul(y Float64x2) Float64x2 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPD, CPU Feature: AVX512EVEX +func (x Float64x2) MulByPowOf2(y Float64x2) Float64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x2) NotEqual(y Float64x2) Mask64x2 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VORPD, CPU Feature: AVX +func (x Float64x2) Or(y Float64x2) Float64x2 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VHADDPD, CPU Feature: AVX +func (x Float64x2) PairwiseAdd(y Float64x2) Float64x2 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VHSUBPD, CPU Feature: AVX +func (x Float64x2) PairwiseSub(y Float64x2) Float64x2 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX +func (x Float64x2) Sub(y Float64x2) Float64x2 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VXORPD, CPU Feature: AVX +func (x Float64x2) Xor(y Float64x2) Float64x2 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX +func (x Float64x4) Add(y Float64x4) Float64x4 + +// AddSub subtracts even elements and adds odd elements of two vectors. +// +// Asm: VADDSUBPD, CPU Feature: AVX +func (x Float64x4) AddSub(y Float64x4) Float64x4 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VANDPD, CPU Feature: AVX +func (x Float64x4) And(y Float64x4) Float64x4 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPD, CPU Feature: AVX +func (x Float64x4) AndNot(y Float64x4) Float64x4 + +// Div divides elements of two vectors. +// +// Asm: VDIVPD, CPU Feature: AVX +func (x Float64x4) Div(y Float64x4) Float64x4 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) Equal(y Float64x4) Mask64x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) Greater(y Float64x4) Mask64x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) GreaterEqual(y Float64x4) Mask64x4 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) IsNan(y Float64x4) Mask64x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) Less(y Float64x4) Mask64x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) LessEqual(y Float64x4) Mask64x4 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedApproximateReciprocal(y Mask64x4) Float64x4 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedApproximateReciprocalOfSqrt(y Mask64x4) Float64x4 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedSqrt(y Mask64x4) Float64x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPD, CPU Feature: AVX +func (x Float64x4) Max(y Float64x4) Float64x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPD, CPU Feature: AVX +func (x Float64x4) Min(y Float64x4) Float64x4 + +// Mul multiplies corresponding elements of two vectors. +// +// Asm: VMULPD, CPU Feature: AVX +func (x Float64x4) Mul(y Float64x4) Float64x4 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPD, CPU Feature: AVX512EVEX +func (x Float64x4) MulByPowOf2(y Float64x4) Float64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPD, CPU Feature: AVX +func (x Float64x4) NotEqual(y Float64x4) Mask64x4 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VORPD, CPU Feature: AVX +func (x Float64x4) Or(y Float64x4) Float64x4 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VHADDPD, CPU Feature: AVX +func (x Float64x4) PairwiseAdd(y Float64x4) Float64x4 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VHSUBPD, CPU Feature: AVX +func (x Float64x4) PairwiseSub(y Float64x4) Float64x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX +func (x Float64x4) Sub(y Float64x4) Float64x4 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VXORPD, CPU Feature: AVX +func (x Float64x4) Xor(y Float64x4) Float64x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x8) Add(y Float64x8) Float64x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPD, CPU Feature: AVX512EVEX +func (x Float64x8) And(y Float64x8) Float64x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPD, CPU Feature: AVX512EVEX +func (x Float64x8) AndNot(y Float64x8) Float64x8 + +// Div divides elements of two vectors. +// +// Asm: VDIVPD, CPU Feature: AVX512EVEX +func (x Float64x8) Div(y Float64x8) Float64x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) Equal(y Float64x8) Mask64x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) Greater(y Float64x8) Mask64x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) GreaterEqual(y Float64x8) Mask64x8 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) IsNan(y Float64x8) Mask64x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) Less(y Float64x8) Mask64x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) LessEqual(y Float64x8) Mask64x8 + +// ApproximateReciprocal computes an approximate reciprocal of each element. +// +// Asm: VRCP14PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedApproximateReciprocal(y Mask64x8) Float64x8 + +// ApproximateReciprocalOfSqrt computes an approximate reciprocal of the square root of each element. +// +// Asm: VRSQRT14PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedApproximateReciprocalOfSqrt(y Mask64x8) Float64x8 + +// Sqrt computes the square root of each element. +// +// Asm: VSQRTPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedSqrt(y Mask64x8) Float64x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPD, CPU Feature: AVX512EVEX +func (x Float64x8) Max(y Float64x8) Float64x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPD, CPU Feature: AVX512EVEX +func (x Float64x8) Min(y Float64x8) Float64x8 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPD, CPU Feature: AVX512EVEX +func (x Float64x8) Mul(y Float64x8) Float64x8 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPD, CPU Feature: AVX512EVEX +func (x Float64x8) MulByPowOf2(y Float64x8) Float64x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) NotEqual(y Float64x8) Mask64x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPD, CPU Feature: AVX512EVEX +func (x Float64x8) Or(y Float64x8) Float64x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x8) Sub(y Float64x8) Float64x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPD, CPU Feature: AVX512EVEX +func (x Float64x8) Xor(y Float64x8) Float64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX2 +func (x Int16x16) Add(y Int16x16) Int16x16 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Int16x16) And(y Int16x16) Int16x16 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Int16x16) AndNot(y Int16x16) Int16x16 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQW, CPU Feature: AVX2 +func (x Int16x16) Equal(y Int16x16) Mask16x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTW, CPU Feature: AVX2 +func (x Int16x16) Greater(y Int16x16) Mask16x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) GreaterEqual(y Int16x16) Mask16x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) Less(y Int16x16) Mask16x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) LessEqual(y Int16x16) Mask16x16 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedAbsolute(y Mask16x16) Int16x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedPopCount(y Mask16x16) Int16x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSW, CPU Feature: AVX2 +func (x Int16x16) Max(y Int16x16) Int16x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSW, CPU Feature: AVX2 +func (x Int16x16) Min(y Int16x16) Int16x16 + +// MulHigh multiplies elements and stores the high part of the result. +// +// Asm: VPMULHW, CPU Feature: AVX2 +func (x Int16x16) MulHigh(y Int16x16) Int16x16 + +// MulLow multiplies elements and stores the low part of the result. +// +// Asm: VPMULLW, CPU Feature: AVX2 +func (x Int16x16) MulLow(y Int16x16) Int16x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) NotEqual(y Int16x16) Mask16x16 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Int16x16) Or(y Int16x16) Int16x16 + +// PairDotProd multiplies the elements and add the pairs together, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDWD, CPU Feature: AVX2 +func (x Int16x16) PairDotProd(y Int16x16) Int32x8 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDW, CPU Feature: AVX2 +func (x Int16x16) PairwiseAdd(y Int16x16) Int16x16 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBW, CPU Feature: AVX2 +func (x Int16x16) PairwiseSub(y Int16x16) Int16x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX2 +func (x Int16x16) SaturatedAdd(y Int16x16) Int16x16 + +// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDSW, CPU Feature: AVX2 +func (x Int16x16) SaturatedPairwiseAdd(y Int16x16) Int16x16 + +// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBSW, CPU Feature: AVX2 +func (x Int16x16) SaturatedPairwiseSub(y Int16x16) Int16x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX2 +func (x Int16x16) SaturatedSub(y Int16x16) Int16x16 + +// Sign returns the product of the first operand with -1, 0, or 1, +// whichever constant is nearest to the value of the second operand. +// +// Asm: VPSIGNW, CPU Feature: AVX2 +func (x Int16x16) Sign(y Int16x16) Int16x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX2 +func (x Int16x16) Sub(y Int16x16) Int16x16 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Int16x16) Xor(y Int16x16) Int16x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Int16x32) Add(y Int16x32) Int16x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQW, CPU Feature: AVX512EVEX +func (x Int16x32) Equal(y Int16x32) Mask16x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTW, CPU Feature: AVX512EVEX +func (x Int16x32) Greater(y Int16x32) Mask16x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) GreaterEqual(y Int16x32) Mask16x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) Less(y Int16x32) Mask16x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) LessEqual(y Int16x32) Mask16x32 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedAbsolute(y Mask16x32) Int16x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedPopCount(y Mask16x32) Int16x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSW, CPU Feature: AVX512EVEX +func (x Int16x32) Max(y Int16x32) Int16x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSW, CPU Feature: AVX512EVEX +func (x Int16x32) Min(y Int16x32) Int16x32 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHW, CPU Feature: AVX512EVEX +func (x Int16x32) MulHigh(y Int16x32) Int16x32 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLW, CPU Feature: AVX512EVEX +func (x Int16x32) MulLow(y Int16x32) Int16x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) NotEqual(y Int16x32) Mask16x32 + +// PairDotProd multiplies the elements and add the pairs together, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDWD, CPU Feature: AVX512EVEX +func (x Int16x32) PairDotProd(y Int16x32) Int32x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Int16x32) SaturatedAdd(y Int16x32) Int16x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Int16x32) SaturatedSub(y Int16x32) Int16x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Int16x32) Sub(y Int16x32) Int16x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX +func (x Int16x8) Add(y Int16x8) Int16x8 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Int16x8) And(y Int16x8) Int16x8 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Int16x8) AndNot(y Int16x8) Int16x8 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQW, CPU Feature: AVX +func (x Int16x8) Equal(y Int16x8) Mask16x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTW, CPU Feature: AVX +func (x Int16x8) Greater(y Int16x8) Mask16x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) GreaterEqual(y Int16x8) Mask16x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) Less(y Int16x8) Mask16x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) LessEqual(y Int16x8) Mask16x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedAbsolute(y Mask16x8) Int16x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedPopCount(y Mask16x8) Int16x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSW, CPU Feature: AVX +func (x Int16x8) Max(y Int16x8) Int16x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSW, CPU Feature: AVX +func (x Int16x8) Min(y Int16x8) Int16x8 + +// MulHigh multiplies elements and stores the high part of the result. +// +// Asm: VPMULHW, CPU Feature: AVX +func (x Int16x8) MulHigh(y Int16x8) Int16x8 + +// MulLow multiplies elements and stores the low part of the result. +// +// Asm: VPMULLW, CPU Feature: AVX +func (x Int16x8) MulLow(y Int16x8) Int16x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) NotEqual(y Int16x8) Mask16x8 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Int16x8) Or(y Int16x8) Int16x8 + +// PairDotProd multiplies the elements and add the pairs together, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDWD, CPU Feature: AVX +func (x Int16x8) PairDotProd(y Int16x8) Int32x4 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDW, CPU Feature: AVX +func (x Int16x8) PairwiseAdd(y Int16x8) Int16x8 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBW, CPU Feature: AVX +func (x Int16x8) PairwiseSub(y Int16x8) Int16x8 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX +func (x Int16x8) SaturatedAdd(y Int16x8) Int16x8 + +// SaturatedPairwiseAdd horizontally adds adjacent pairs of elements with saturation. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDSW, CPU Feature: AVX +func (x Int16x8) SaturatedPairwiseAdd(y Int16x8) Int16x8 + +// SaturatedPairwiseSub horizontally subtracts adjacent pairs of elements with saturation. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBSW, CPU Feature: AVX +func (x Int16x8) SaturatedPairwiseSub(y Int16x8) Int16x8 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX +func (x Int16x8) SaturatedSub(y Int16x8) Int16x8 + +// Sign returns the product of the first operand with -1, 0, or 1, +// whichever constant is nearest to the value of the second operand. +// +// Asm: VPSIGNW, CPU Feature: AVX +func (x Int16x8) Sign(y Int16x8) Int16x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX +func (x Int16x8) Sub(y Int16x8) Int16x8 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Int16x8) Xor(y Int16x8) Int16x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Int32x16) Add(y Int32x16) Int32x16 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Int32x16) And(y Int32x16) Int32x16 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Int32x16) AndNot(y Int32x16) Int32x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQD, CPU Feature: AVX512EVEX +func (x Int32x16) Equal(y Int32x16) Mask32x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTD, CPU Feature: AVX512EVEX +func (x Int32x16) Greater(y Int32x16) Mask32x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) GreaterEqual(y Int32x16) Mask32x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) Less(y Int32x16) Mask32x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) LessEqual(y Int32x16) Mask32x16 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedAbsolute(y Mask32x16) Int32x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedPopCount(y Mask32x16) Int32x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSD, CPU Feature: AVX512EVEX +func (x Int32x16) Max(y Int32x16) Int32x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSD, CPU Feature: AVX512EVEX +func (x Int32x16) Min(y Int32x16) Int32x16 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLD, CPU Feature: AVX512EVEX +func (x Int32x16) MulLow(y Int32x16) Int32x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) NotEqual(y Int32x16) Mask32x16 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Int32x16) Or(y Int32x16) Int32x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Int32x16) Sub(y Int32x16) Int32x16 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Int32x16) Xor(y Int32x16) Int32x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX +func (x Int32x4) Add(y Int32x4) Int32x4 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Int32x4) And(y Int32x4) Int32x4 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Int32x4) AndNot(y Int32x4) Int32x4 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQD, CPU Feature: AVX +func (x Int32x4) Equal(y Int32x4) Mask32x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTD, CPU Feature: AVX +func (x Int32x4) Greater(y Int32x4) Mask32x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) GreaterEqual(y Int32x4) Mask32x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) Less(y Int32x4) Mask32x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) LessEqual(y Int32x4) Mask32x4 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedAbsolute(y Mask32x4) Int32x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedPopCount(y Mask32x4) Int32x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSD, CPU Feature: AVX +func (x Int32x4) Max(y Int32x4) Int32x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSD, CPU Feature: AVX +func (x Int32x4) Min(y Int32x4) Int32x4 + +// MulEvenWiden multiplies even-indexed elements, widening the result. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX +func (x Int32x4) MulEvenWiden(y Int32x4) Int64x2 + +// MulLow multiplies elements and stores the low part of the result. +// +// Asm: VPMULLD, CPU Feature: AVX +func (x Int32x4) MulLow(y Int32x4) Int32x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) NotEqual(y Int32x4) Mask32x4 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Int32x4) Or(y Int32x4) Int32x4 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDD, CPU Feature: AVX +func (x Int32x4) PairwiseAdd(y Int32x4) Int32x4 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBD, CPU Feature: AVX +func (x Int32x4) PairwiseSub(y Int32x4) Int32x4 + +// Sign returns the product of the first operand with -1, 0, or 1, +// whichever constant is nearest to the value of the second operand. +// +// Asm: VPSIGND, CPU Feature: AVX +func (x Int32x4) Sign(y Int32x4) Int32x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX +func (x Int32x4) Sub(y Int32x4) Int32x4 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Int32x4) Xor(y Int32x4) Int32x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX2 +func (x Int32x8) Add(y Int32x8) Int32x8 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Int32x8) And(y Int32x8) Int32x8 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Int32x8) AndNot(y Int32x8) Int32x8 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQD, CPU Feature: AVX2 +func (x Int32x8) Equal(y Int32x8) Mask32x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTD, CPU Feature: AVX2 +func (x Int32x8) Greater(y Int32x8) Mask32x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) GreaterEqual(y Int32x8) Mask32x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) Less(y Int32x8) Mask32x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) LessEqual(y Int32x8) Mask32x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedAbsolute(y Mask32x8) Int32x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedPopCount(y Mask32x8) Int32x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSD, CPU Feature: AVX2 +func (x Int32x8) Max(y Int32x8) Int32x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSD, CPU Feature: AVX2 +func (x Int32x8) Min(y Int32x8) Int32x8 + +// MulEvenWiden multiplies even-indexed elements, widening the result. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX2 +func (x Int32x8) MulEvenWiden(y Int32x8) Int64x4 + +// MulLow multiplies elements and stores the low part of the result. +// +// Asm: VPMULLD, CPU Feature: AVX2 +func (x Int32x8) MulLow(y Int32x8) Int32x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) NotEqual(y Int32x8) Mask32x8 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Int32x8) Or(y Int32x8) Int32x8 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDD, CPU Feature: AVX2 +func (x Int32x8) PairwiseAdd(y Int32x8) Int32x8 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBD, CPU Feature: AVX2 +func (x Int32x8) PairwiseSub(y Int32x8) Int32x8 + +// Sign returns the product of the first operand with -1, 0, or 1, +// whichever constant is nearest to the value of the second operand. +// +// Asm: VPSIGND, CPU Feature: AVX2 +func (x Int32x8) Sign(y Int32x8) Int32x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX2 +func (x Int32x8) Sub(y Int32x8) Int32x8 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Int32x8) Xor(y Int32x8) Int32x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX +func (x Int64x2) Add(y Int64x2) Int64x2 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Int64x2) And(y Int64x2) Int64x2 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Int64x2) AndNot(y Int64x2) Int64x2 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQQ, CPU Feature: AVX +func (x Int64x2) Equal(y Int64x2) Mask64x2 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTQ, CPU Feature: AVX512EVEX +func (x Int64x2) Greater(y Int64x2) Mask64x2 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) GreaterEqual(y Int64x2) Mask64x2 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) Less(y Int64x2) Mask64x2 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) LessEqual(y Int64x2) Mask64x2 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedAbsolute(y Mask64x2) Int64x2 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedPopCount(y Mask64x2) Int64x2 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSQ, CPU Feature: AVX512EVEX +func (x Int64x2) Max(y Int64x2) Int64x2 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSQ, CPU Feature: AVX512EVEX +func (x Int64x2) Min(y Int64x2) Int64x2 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX512EVEX +func (x Int64x2) MulEvenWiden(y Int64x2) Int64x2 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLQ, CPU Feature: AVX512EVEX +func (x Int64x2) MulLow(y Int64x2) Int64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) NotEqual(y Int64x2) Mask64x2 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Int64x2) Or(y Int64x2) Int64x2 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX +func (x Int64x2) Sub(y Int64x2) Int64x2 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Int64x2) Xor(y Int64x2) Int64x2 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX2 +func (x Int64x4) Add(y Int64x4) Int64x4 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Int64x4) And(y Int64x4) Int64x4 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Int64x4) AndNot(y Int64x4) Int64x4 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQQ, CPU Feature: AVX2 +func (x Int64x4) Equal(y Int64x4) Mask64x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTQ, CPU Feature: AVX2 +func (x Int64x4) Greater(y Int64x4) Mask64x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) GreaterEqual(y Int64x4) Mask64x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) Less(y Int64x4) Mask64x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) LessEqual(y Int64x4) Mask64x4 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedAbsolute(y Mask64x4) Int64x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedPopCount(y Mask64x4) Int64x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSQ, CPU Feature: AVX512EVEX +func (x Int64x4) Max(y Int64x4) Int64x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSQ, CPU Feature: AVX512EVEX +func (x Int64x4) Min(y Int64x4) Int64x4 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX512EVEX +func (x Int64x4) MulEvenWiden(y Int64x4) Int64x4 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLQ, CPU Feature: AVX512EVEX +func (x Int64x4) MulLow(y Int64x4) Int64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) NotEqual(y Int64x4) Mask64x4 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Int64x4) Or(y Int64x4) Int64x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX2 +func (x Int64x4) Sub(y Int64x4) Int64x4 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Int64x4) Xor(y Int64x4) Int64x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Int64x8) Add(y Int64x8) Int64x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Int64x8) And(y Int64x8) Int64x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Int64x8) AndNot(y Int64x8) Int64x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQQ, CPU Feature: AVX512EVEX +func (x Int64x8) Equal(y Int64x8) Mask64x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTQ, CPU Feature: AVX512EVEX +func (x Int64x8) Greater(y Int64x8) Mask64x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) GreaterEqual(y Int64x8) Mask64x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) Less(y Int64x8) Mask64x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) LessEqual(y Int64x8) Mask64x8 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedAbsolute(y Mask64x8) Int64x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedPopCount(y Mask64x8) Int64x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSQ, CPU Feature: AVX512EVEX +func (x Int64x8) Max(y Int64x8) Int64x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSQ, CPU Feature: AVX512EVEX +func (x Int64x8) Min(y Int64x8) Int64x8 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX512EVEX +func (x Int64x8) MulEvenWiden(y Int64x8) Int64x8 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLQ, CPU Feature: AVX512EVEX +func (x Int64x8) MulLow(y Int64x8) Int64x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) NotEqual(y Int64x8) Mask64x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Int64x8) Or(y Int64x8) Int64x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Int64x8) Sub(y Int64x8) Int64x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Int64x8) Xor(y Int64x8) Int64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX +func (x Int8x16) Add(y Int8x16) Int8x16 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Int8x16) And(y Int8x16) Int8x16 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Int8x16) AndNot(y Int8x16) Int8x16 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQB, CPU Feature: AVX +func (x Int8x16) Equal(y Int8x16) Mask8x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTB, CPU Feature: AVX +func (x Int8x16) Greater(y Int8x16) Mask8x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) GreaterEqual(y Int8x16) Mask8x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) Less(y Int8x16) Mask8x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) LessEqual(y Int8x16) Mask8x16 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedAbsolute(y Mask8x16) Int8x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedPopCount(y Mask8x16) Int8x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSB, CPU Feature: AVX +func (x Int8x16) Max(y Int8x16) Int8x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSB, CPU Feature: AVX +func (x Int8x16) Min(y Int8x16) Int8x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) NotEqual(y Int8x16) Mask8x16 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Int8x16) Or(y Int8x16) Int8x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX +func (x Int8x16) SaturatedAdd(y Int8x16) Int8x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX +func (x Int8x16) SaturatedSub(y Int8x16) Int8x16 + +// Sign returns the product of the first operand with -1, 0, or 1, +// whichever constant is nearest to the value of the second operand. +// +// Asm: VPSIGNB, CPU Feature: AVX +func (x Int8x16) Sign(y Int8x16) Int8x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX +func (x Int8x16) Sub(y Int8x16) Int8x16 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Int8x16) Xor(y Int8x16) Int8x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX2 +func (x Int8x32) Add(y Int8x32) Int8x32 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Int8x32) And(y Int8x32) Int8x32 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Int8x32) AndNot(y Int8x32) Int8x32 + +// Equal compares for equality. +// Const Immediate = 0. +// +// Asm: VPCMPEQB, CPU Feature: AVX2 +func (x Int8x32) Equal(y Int8x32) Mask8x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTB, CPU Feature: AVX2 +func (x Int8x32) Greater(y Int8x32) Mask8x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) GreaterEqual(y Int8x32) Mask8x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) Less(y Int8x32) Mask8x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) LessEqual(y Int8x32) Mask8x32 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedAbsolute(y Mask8x32) Int8x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedPopCount(y Mask8x32) Int8x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSB, CPU Feature: AVX2 +func (x Int8x32) Max(y Int8x32) Int8x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSB, CPU Feature: AVX2 +func (x Int8x32) Min(y Int8x32) Int8x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) NotEqual(y Int8x32) Mask8x32 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Int8x32) Or(y Int8x32) Int8x32 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX2 +func (x Int8x32) SaturatedAdd(y Int8x32) Int8x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX2 +func (x Int8x32) SaturatedSub(y Int8x32) Int8x32 + +// Sign returns the product of the first operand with -1, 0, or 1, +// whichever constant is nearest to the value of the second operand. +// +// Asm: VPSIGNB, CPU Feature: AVX2 +func (x Int8x32) Sign(y Int8x32) Int8x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX2 +func (x Int8x32) Sub(y Int8x32) Int8x32 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Int8x32) Xor(y Int8x32) Int8x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Int8x64) Add(y Int8x64) Int8x64 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQB, CPU Feature: AVX512EVEX +func (x Int8x64) Equal(y Int8x64) Mask8x64 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTB, CPU Feature: AVX512EVEX +func (x Int8x64) Greater(y Int8x64) Mask8x64 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) GreaterEqual(y Int8x64) Mask8x64 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) Less(y Int8x64) Mask8x64 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) LessEqual(y Int8x64) Mask8x64 + +// Absolute computes the absolute value of each element. +// +// Asm: VPABSB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedAbsolute(y Mask8x64) Int8x64 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedPopCount(y Mask8x64) Int8x64 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSB, CPU Feature: AVX512EVEX +func (x Int8x64) Max(y Int8x64) Int8x64 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSB, CPU Feature: AVX512EVEX +func (x Int8x64) Min(y Int8x64) Int8x64 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) NotEqual(y Int8x64) Mask8x64 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Int8x64) SaturatedAdd(y Int8x64) Int8x64 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Int8x64) SaturatedSub(y Int8x64) Int8x64 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Int8x64) Sub(y Int8x64) Int8x64 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX2 +func (x Uint16x16) Add(y Uint16x16) Uint16x16 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Uint16x16) And(y Uint16x16) Uint16x16 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Uint16x16) AndNot(y Uint16x16) Uint16x16 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGW, CPU Feature: AVX2 +func (x Uint16x16) Average(y Uint16x16) Uint16x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) Equal(y Uint16x16) Mask16x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) Greater(y Uint16x16) Mask16x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) GreaterEqual(y Uint16x16) Mask16x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) Less(y Uint16x16) Mask16x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) LessEqual(y Uint16x16) Mask16x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedPopCount(y Mask16x16) Uint16x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUW, CPU Feature: AVX2 +func (x Uint16x16) Max(y Uint16x16) Uint16x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUW, CPU Feature: AVX2 +func (x Uint16x16) Min(y Uint16x16) Uint16x16 + +// MulHigh multiplies elements and stores the high part of the result. +// +// Asm: VPMULHUW, CPU Feature: AVX2 +func (x Uint16x16) MulHigh(y Uint16x16) Uint16x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) NotEqual(y Uint16x16) Mask16x16 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Uint16x16) Or(y Uint16x16) Uint16x16 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDW, CPU Feature: AVX2 +func (x Uint16x16) PairwiseAdd(y Uint16x16) Uint16x16 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBW, CPU Feature: AVX2 +func (x Uint16x16) PairwiseSub(y Uint16x16) Uint16x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX2 +func (x Uint16x16) SaturatedAdd(y Uint16x16) Uint16x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX2 +func (x Uint16x16) SaturatedSub(y Uint16x16) Uint16x16 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX +func (x Uint16x16) SaturatedUnsignedSignedPairDotProd(y Int16x16) Int16x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX2 +func (x Uint16x16) Sub(y Uint16x16) Uint16x16 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Uint16x16) Xor(y Uint16x16) Uint16x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Uint16x32) Add(y Uint16x32) Uint16x32 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGW, CPU Feature: AVX512EVEX +func (x Uint16x32) Average(y Uint16x32) Uint16x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) Equal(y Uint16x32) Mask16x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) Greater(y Uint16x32) Mask16x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) GreaterEqual(y Uint16x32) Mask16x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) Less(y Uint16x32) Mask16x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) LessEqual(y Uint16x32) Mask16x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedPopCount(y Mask16x32) Uint16x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUW, CPU Feature: AVX512EVEX +func (x Uint16x32) Max(y Uint16x32) Uint16x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUW, CPU Feature: AVX512EVEX +func (x Uint16x32) Min(y Uint16x32) Uint16x32 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MulHigh(y Uint16x32) Uint16x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) NotEqual(y Uint16x32) Mask16x32 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Uint16x32) SaturatedAdd(y Uint16x32) Uint16x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Uint16x32) SaturatedSub(y Uint16x32) Uint16x32 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX +func (x Uint16x32) SaturatedUnsignedSignedPairDotProd(y Int16x32) Int16x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Uint16x32) Sub(y Uint16x32) Uint16x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX +func (x Uint16x8) Add(y Uint16x8) Uint16x8 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Uint16x8) And(y Uint16x8) Uint16x8 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Uint16x8) AndNot(y Uint16x8) Uint16x8 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGW, CPU Feature: AVX +func (x Uint16x8) Average(y Uint16x8) Uint16x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) Equal(y Uint16x8) Mask16x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) Greater(y Uint16x8) Mask16x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) GreaterEqual(y Uint16x8) Mask16x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) Less(y Uint16x8) Mask16x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) LessEqual(y Uint16x8) Mask16x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedPopCount(y Mask16x8) Uint16x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUW, CPU Feature: AVX +func (x Uint16x8) Max(y Uint16x8) Uint16x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUW, CPU Feature: AVX +func (x Uint16x8) Min(y Uint16x8) Uint16x8 + +// MulHigh multiplies elements and stores the high part of the result. +// +// Asm: VPMULHUW, CPU Feature: AVX +func (x Uint16x8) MulHigh(y Uint16x8) Uint16x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) NotEqual(y Uint16x8) Mask16x8 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Uint16x8) Or(y Uint16x8) Uint16x8 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDW, CPU Feature: AVX +func (x Uint16x8) PairwiseAdd(y Uint16x8) Uint16x8 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBW, CPU Feature: AVX +func (x Uint16x8) PairwiseSub(y Uint16x8) Uint16x8 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX +func (x Uint16x8) SaturatedAdd(y Uint16x8) Uint16x8 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX +func (x Uint16x8) SaturatedSub(y Uint16x8) Uint16x8 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX +func (x Uint16x8) SaturatedUnsignedSignedPairDotProd(y Int16x8) Int16x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX +func (x Uint16x8) Sub(y Uint16x8) Uint16x8 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Uint16x8) Xor(y Uint16x8) Uint16x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Uint32x16) Add(y Uint32x16) Uint32x16 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Uint32x16) And(y Uint32x16) Uint32x16 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Uint32x16) AndNot(y Uint32x16) Uint32x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) Equal(y Uint32x16) Mask32x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) Greater(y Uint32x16) Mask32x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) GreaterEqual(y Uint32x16) Mask32x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) Less(y Uint32x16) Mask32x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) LessEqual(y Uint32x16) Mask32x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedPopCount(y Mask32x16) Uint32x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUD, CPU Feature: AVX512EVEX +func (x Uint32x16) Max(y Uint32x16) Uint32x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUD, CPU Feature: AVX512EVEX +func (x Uint32x16) Min(y Uint32x16) Uint32x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) NotEqual(y Uint32x16) Mask32x16 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Uint32x16) Or(y Uint32x16) Uint32x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Uint32x16) Sub(y Uint32x16) Uint32x16 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Uint32x16) Xor(y Uint32x16) Uint32x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX +func (x Uint32x4) Add(y Uint32x4) Uint32x4 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Uint32x4) And(y Uint32x4) Uint32x4 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Uint32x4) AndNot(y Uint32x4) Uint32x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) Equal(y Uint32x4) Mask32x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) Greater(y Uint32x4) Mask32x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) GreaterEqual(y Uint32x4) Mask32x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) Less(y Uint32x4) Mask32x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) LessEqual(y Uint32x4) Mask32x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedPopCount(y Mask32x4) Uint32x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUD, CPU Feature: AVX +func (x Uint32x4) Max(y Uint32x4) Uint32x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUD, CPU Feature: AVX +func (x Uint32x4) Min(y Uint32x4) Uint32x4 + +// MulEvenWiden multiplies even-indexed elements, widening the result. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX +func (x Uint32x4) MulEvenWiden(y Uint32x4) Uint64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) NotEqual(y Uint32x4) Mask32x4 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Uint32x4) Or(y Uint32x4) Uint32x4 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDD, CPU Feature: AVX +func (x Uint32x4) PairwiseAdd(y Uint32x4) Uint32x4 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBD, CPU Feature: AVX +func (x Uint32x4) PairwiseSub(y Uint32x4) Uint32x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX +func (x Uint32x4) Sub(y Uint32x4) Uint32x4 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Uint32x4) Xor(y Uint32x4) Uint32x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX2 +func (x Uint32x8) Add(y Uint32x8) Uint32x8 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Uint32x8) And(y Uint32x8) Uint32x8 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Uint32x8) AndNot(y Uint32x8) Uint32x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) Equal(y Uint32x8) Mask32x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) Greater(y Uint32x8) Mask32x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) GreaterEqual(y Uint32x8) Mask32x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) Less(y Uint32x8) Mask32x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) LessEqual(y Uint32x8) Mask32x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedPopCount(y Mask32x8) Uint32x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUD, CPU Feature: AVX2 +func (x Uint32x8) Max(y Uint32x8) Uint32x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUD, CPU Feature: AVX2 +func (x Uint32x8) Min(y Uint32x8) Uint32x8 + +// MulEvenWiden multiplies even-indexed elements, widening the result. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX2 +func (x Uint32x8) MulEvenWiden(y Uint32x8) Uint64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) NotEqual(y Uint32x8) Mask32x8 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Uint32x8) Or(y Uint32x8) Uint32x8 + +// PairwiseAdd horizontally adds adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0+y1, y2+y3, ..., x0+x1, x2+x3, ...]. +// +// Asm: VPHADDD, CPU Feature: AVX2 +func (x Uint32x8) PairwiseAdd(y Uint32x8) Uint32x8 + +// PairwiseSub horizontally subtracts adjacent pairs of elements. +// For x = [x0, x1, x2, x3, ...] and y = [y0, y1, y2, y3, ...], the result is [y0-y1, y2-y3, ..., x0-x1, x2-x3, ...]. +// +// Asm: VPHSUBD, CPU Feature: AVX2 +func (x Uint32x8) PairwiseSub(y Uint32x8) Uint32x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX2 +func (x Uint32x8) Sub(y Uint32x8) Uint32x8 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Uint32x8) Xor(y Uint32x8) Uint32x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX +func (x Uint64x2) Add(y Uint64x2) Uint64x2 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Uint64x2) And(y Uint64x2) Uint64x2 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Uint64x2) AndNot(y Uint64x2) Uint64x2 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) Equal(y Uint64x2) Mask64x2 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) Greater(y Uint64x2) Mask64x2 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) GreaterEqual(y Uint64x2) Mask64x2 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) Less(y Uint64x2) Mask64x2 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) LessEqual(y Uint64x2) Mask64x2 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedPopCount(y Mask64x2) Uint64x2 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) Max(y Uint64x2) Uint64x2 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) Min(y Uint64x2) Uint64x2 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MulEvenWiden(y Uint64x2) Uint64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) NotEqual(y Uint64x2) Mask64x2 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Uint64x2) Or(y Uint64x2) Uint64x2 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX +func (x Uint64x2) Sub(y Uint64x2) Uint64x2 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Uint64x2) Xor(y Uint64x2) Uint64x2 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX2 +func (x Uint64x4) Add(y Uint64x4) Uint64x4 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Uint64x4) And(y Uint64x4) Uint64x4 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Uint64x4) AndNot(y Uint64x4) Uint64x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) Equal(y Uint64x4) Mask64x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) Greater(y Uint64x4) Mask64x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) GreaterEqual(y Uint64x4) Mask64x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) Less(y Uint64x4) Mask64x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) LessEqual(y Uint64x4) Mask64x4 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedPopCount(y Mask64x4) Uint64x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) Max(y Uint64x4) Uint64x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) Min(y Uint64x4) Uint64x4 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MulEvenWiden(y Uint64x4) Uint64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) NotEqual(y Uint64x4) Mask64x4 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Uint64x4) Or(y Uint64x4) Uint64x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX2 +func (x Uint64x4) Sub(y Uint64x4) Uint64x4 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Uint64x4) Xor(y Uint64x4) Uint64x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Add(y Uint64x8) Uint64x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Uint64x8) And(y Uint64x8) Uint64x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Uint64x8) AndNot(y Uint64x8) Uint64x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Equal(y Uint64x8) Mask64x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Greater(y Uint64x8) Mask64x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) GreaterEqual(y Uint64x8) Mask64x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Less(y Uint64x8) Mask64x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) LessEqual(y Uint64x8) Mask64x8 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedPopCount(y Mask64x8) Uint64x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Max(y Uint64x8) Uint64x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Min(y Uint64x8) Uint64x8 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MulEvenWiden(y Uint64x8) Uint64x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) NotEqual(y Uint64x8) Mask64x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Or(y Uint64x8) Uint64x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Sub(y Uint64x8) Uint64x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Uint64x8) Xor(y Uint64x8) Uint64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX +func (x Uint8x16) Add(y Uint8x16) Uint8x16 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX +func (x Uint8x16) And(y Uint8x16) Uint8x16 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX +func (x Uint8x16) AndNot(y Uint8x16) Uint8x16 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGB, CPU Feature: AVX +func (x Uint8x16) Average(y Uint8x16) Uint8x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) Equal(y Uint8x16) Mask8x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) Greater(y Uint8x16) Mask8x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) GreaterEqual(y Uint8x16) Mask8x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) Less(y Uint8x16) Mask8x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) LessEqual(y Uint8x16) Mask8x16 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedPopCount(y Mask8x16) Uint8x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUB, CPU Feature: AVX +func (x Uint8x16) Max(y Uint8x16) Uint8x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUB, CPU Feature: AVX +func (x Uint8x16) Min(y Uint8x16) Uint8x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) NotEqual(y Uint8x16) Mask8x16 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX +func (x Uint8x16) Or(y Uint8x16) Uint8x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX +func (x Uint8x16) SaturatedAdd(y Uint8x16) Uint8x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX +func (x Uint8x16) SaturatedSub(y Uint8x16) Uint8x16 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX +func (x Uint8x16) SaturatedUnsignedSignedPairDotProd(y Int8x16) Int16x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX +func (x Uint8x16) Sub(y Uint8x16) Uint8x16 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX +func (x Uint8x16) Xor(y Uint8x16) Uint8x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX2 +func (x Uint8x32) Add(y Uint8x32) Uint8x32 + +// And performs a bitwise AND operation between two vectors. +// +// Asm: VPAND, CPU Feature: AVX2 +func (x Uint8x32) And(y Uint8x32) Uint8x32 + +// AndNot performs a bitwise AND NOT operation between two vectors. +// +// Asm: VPANDN, CPU Feature: AVX2 +func (x Uint8x32) AndNot(y Uint8x32) Uint8x32 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGB, CPU Feature: AVX2 +func (x Uint8x32) Average(y Uint8x32) Uint8x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) Equal(y Uint8x32) Mask8x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) Greater(y Uint8x32) Mask8x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) GreaterEqual(y Uint8x32) Mask8x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) Less(y Uint8x32) Mask8x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) LessEqual(y Uint8x32) Mask8x32 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedPopCount(y Mask8x32) Uint8x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUB, CPU Feature: AVX2 +func (x Uint8x32) Max(y Uint8x32) Uint8x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUB, CPU Feature: AVX2 +func (x Uint8x32) Min(y Uint8x32) Uint8x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) NotEqual(y Uint8x32) Mask8x32 + +// Or performs a bitwise OR operation between two vectors. +// +// Asm: VPOR, CPU Feature: AVX2 +func (x Uint8x32) Or(y Uint8x32) Uint8x32 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX2 +func (x Uint8x32) SaturatedAdd(y Uint8x32) Uint8x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX2 +func (x Uint8x32) SaturatedSub(y Uint8x32) Uint8x32 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX2 +func (x Uint8x32) SaturatedUnsignedSignedPairDotProd(y Int8x32) Int16x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX2 +func (x Uint8x32) Sub(y Uint8x32) Uint8x32 + +// Xor performs a bitwise XOR operation between two vectors. +// +// Asm: VPXOR, CPU Feature: AVX2 +func (x Uint8x32) Xor(y Uint8x32) Uint8x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Uint8x64) Add(y Uint8x64) Uint8x64 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGB, CPU Feature: AVX512EVEX +func (x Uint8x64) Average(y Uint8x64) Uint8x64 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) Equal(y Uint8x64) Mask8x64 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) Greater(y Uint8x64) Mask8x64 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) GreaterEqual(y Uint8x64) Mask8x64 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) Less(y Uint8x64) Mask8x64 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) LessEqual(y Uint8x64) Mask8x64 + +// PopCount counts the number of set bits in each element. +// +// Asm: VPOPCNTB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedPopCount(y Mask8x64) Uint8x64 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUB, CPU Feature: AVX512EVEX +func (x Uint8x64) Max(y Uint8x64) Uint8x64 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUB, CPU Feature: AVX512EVEX +func (x Uint8x64) Min(y Uint8x64) Uint8x64 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) NotEqual(y Uint8x64) Mask8x64 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Uint8x64) SaturatedAdd(y Uint8x64) Uint8x64 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Uint8x64) SaturatedSub(y Uint8x64) Uint8x64 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Uint8x64) Sub(y Uint8x64) Uint8x64 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplyAdd132(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplyAdd213(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplyAdd231(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplyAddSub132(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplyAddSub213(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplyAddSub231(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplySub132(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplySub213(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplySub231(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplySubAdd132(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplySubAdd213(y Float32x16, z Float32x16) Float32x16 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedMultiplySubAdd231(y Float32x16, z Float32x16) Float32x16 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedNegativeMultiplyAdd132(y Float32x16, z Float32x16) Float32x16 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedNegativeMultiplyAdd213(y Float32x16, z Float32x16) Float32x16 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedNegativeMultiplyAdd231(y Float32x16, z Float32x16) Float32x16 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedNegativeMultiplySub132(y Float32x16, z Float32x16) Float32x16 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedNegativeMultiplySub213(y Float32x16, z Float32x16) Float32x16 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x16) FusedNegativeMultiplySub231(y Float32x16, z Float32x16) Float32x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedAdd(y Float32x16, z Mask32x16) Float32x16 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedAnd(y Float32x16, z Mask32x16) Float32x16 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedAndNot(y Float32x16, z Mask32x16) Float32x16 + +// Div divides elements of two vectors. +// +// Asm: VDIVPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiv(y Float32x16, z Mask32x16) Float32x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedEqual(y Float32x16, z Mask32x16) Mask32x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedGreater(y Float32x16, z Mask32x16) Mask32x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedGreaterEqual(y Float32x16, z Mask32x16) Mask32x16 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedIsNan(y Float32x16, z Mask32x16) Mask32x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedLess(y Float32x16, z Mask32x16) Mask32x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedLessEqual(y Float32x16, z Mask32x16) Mask32x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedMax(y Float32x16, z Mask32x16) Float32x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedMin(y Float32x16, z Mask32x16) Float32x16 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedMul(y Float32x16, z Mask32x16) Float32x16 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedMulByPowOf2(y Float32x16, z Mask32x16) Float32x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedNotEqual(y Float32x16, z Mask32x16) Mask32x16 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedOr(y Float32x16, z Mask32x16) Float32x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedSub(y Float32x16, z Mask32x16) Float32x16 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedXor(y Float32x16, z Mask32x16) Float32x16 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplyAdd132(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplyAdd213(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplyAdd231(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplyAddSub132(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplyAddSub213(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplyAddSub231(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplySub132(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplySub213(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplySub231(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplySubAdd132(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplySubAdd213(y Float32x4, z Float32x4) Float32x4 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedMultiplySubAdd231(y Float32x4, z Float32x4) Float32x4 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedNegativeMultiplyAdd132(y Float32x4, z Float32x4) Float32x4 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedNegativeMultiplyAdd213(y Float32x4, z Float32x4) Float32x4 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedNegativeMultiplyAdd231(y Float32x4, z Float32x4) Float32x4 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedNegativeMultiplySub132(y Float32x4, z Float32x4) Float32x4 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedNegativeMultiplySub213(y Float32x4, z Float32x4) Float32x4 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x4) FusedNegativeMultiplySub231(y Float32x4, z Float32x4) Float32x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedAdd(y Float32x4, z Mask32x4) Float32x4 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedAnd(y Float32x4, z Mask32x4) Float32x4 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedAndNot(y Float32x4, z Mask32x4) Float32x4 + +// Div divides elements of two vectors. +// +// Asm: VDIVPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiv(y Float32x4, z Mask32x4) Float32x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedEqual(y Float32x4, z Mask32x4) Mask32x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedGreater(y Float32x4, z Mask32x4) Mask32x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedGreaterEqual(y Float32x4, z Mask32x4) Mask32x4 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedIsNan(y Float32x4, z Mask32x4) Mask32x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedLess(y Float32x4, z Mask32x4) Mask32x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedLessEqual(y Float32x4, z Mask32x4) Mask32x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedMax(y Float32x4, z Mask32x4) Float32x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedMin(y Float32x4, z Mask32x4) Float32x4 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedMul(y Float32x4, z Mask32x4) Float32x4 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedMulByPowOf2(y Float32x4, z Mask32x4) Float32x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedNotEqual(y Float32x4, z Mask32x4) Mask32x4 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedOr(y Float32x4, z Mask32x4) Float32x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedSub(y Float32x4, z Mask32x4) Float32x4 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedXor(y Float32x4, z Mask32x4) Float32x4 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplyAdd132(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplyAdd213(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplyAdd231(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplyAddSub132(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplyAddSub213(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplyAddSub231(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplySub132(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplySub213(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplySub231(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplySubAdd132(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplySubAdd213(y Float32x8, z Float32x8) Float32x8 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedMultiplySubAdd231(y Float32x8, z Float32x8) Float32x8 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedNegativeMultiplyAdd132(y Float32x8, z Float32x8) Float32x8 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedNegativeMultiplyAdd213(y Float32x8, z Float32x8) Float32x8 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedNegativeMultiplyAdd231(y Float32x8, z Float32x8) Float32x8 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedNegativeMultiplySub132(y Float32x8, z Float32x8) Float32x8 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedNegativeMultiplySub213(y Float32x8, z Float32x8) Float32x8 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x8) FusedNegativeMultiplySub231(y Float32x8, z Float32x8) Float32x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedAdd(y Float32x8, z Mask32x8) Float32x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedAnd(y Float32x8, z Mask32x8) Float32x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedAndNot(y Float32x8, z Mask32x8) Float32x8 + +// Div divides elements of two vectors. +// +// Asm: VDIVPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiv(y Float32x8, z Mask32x8) Float32x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedEqual(y Float32x8, z Mask32x8) Mask32x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedGreater(y Float32x8, z Mask32x8) Mask32x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedGreaterEqual(y Float32x8, z Mask32x8) Mask32x8 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedIsNan(y Float32x8, z Mask32x8) Mask32x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedLess(y Float32x8, z Mask32x8) Mask32x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedLessEqual(y Float32x8, z Mask32x8) Mask32x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedMax(y Float32x8, z Mask32x8) Float32x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedMin(y Float32x8, z Mask32x8) Float32x8 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedMul(y Float32x8, z Mask32x8) Float32x8 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedMulByPowOf2(y Float32x8, z Mask32x8) Float32x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedNotEqual(y Float32x8, z Mask32x8) Mask32x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedOr(y Float32x8, z Mask32x8) Float32x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedSub(y Float32x8, z Mask32x8) Float32x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedXor(y Float32x8, z Mask32x8) Float32x8 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplyAdd132(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplyAdd213(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplyAdd231(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplyAddSub132(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplyAddSub213(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplyAddSub231(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplySub132(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplySub213(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplySub231(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplySubAdd132(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplySubAdd213(y Float64x2, z Float64x2) Float64x2 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedMultiplySubAdd231(y Float64x2, z Float64x2) Float64x2 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedNegativeMultiplyAdd132(y Float64x2, z Float64x2) Float64x2 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedNegativeMultiplyAdd213(y Float64x2, z Float64x2) Float64x2 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedNegativeMultiplyAdd231(y Float64x2, z Float64x2) Float64x2 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedNegativeMultiplySub132(y Float64x2, z Float64x2) Float64x2 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedNegativeMultiplySub213(y Float64x2, z Float64x2) Float64x2 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x2) FusedNegativeMultiplySub231(y Float64x2, z Float64x2) Float64x2 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedAdd(y Float64x2, z Mask64x2) Float64x2 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedAnd(y Float64x2, z Mask64x2) Float64x2 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedAndNot(y Float64x2, z Mask64x2) Float64x2 + +// Div divides elements of two vectors. +// +// Asm: VDIVPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiv(y Float64x2, z Mask64x2) Float64x2 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedEqual(y Float64x2, z Mask64x2) Mask64x2 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedGreater(y Float64x2, z Mask64x2) Mask64x2 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedGreaterEqual(y Float64x2, z Mask64x2) Mask64x2 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedIsNan(y Float64x2, z Mask64x2) Mask64x2 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedLess(y Float64x2, z Mask64x2) Mask64x2 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedLessEqual(y Float64x2, z Mask64x2) Mask64x2 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedMax(y Float64x2, z Mask64x2) Float64x2 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedMin(y Float64x2, z Mask64x2) Float64x2 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedMul(y Float64x2, z Mask64x2) Float64x2 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedMulByPowOf2(y Float64x2, z Mask64x2) Float64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedNotEqual(y Float64x2, z Mask64x2) Mask64x2 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedOr(y Float64x2, z Mask64x2) Float64x2 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedSub(y Float64x2, z Mask64x2) Float64x2 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedXor(y Float64x2, z Mask64x2) Float64x2 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplyAdd132(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplyAdd213(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplyAdd231(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplyAddSub132(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplyAddSub213(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplyAddSub231(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplySub132(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplySub213(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplySub231(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplySubAdd132(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplySubAdd213(y Float64x4, z Float64x4) Float64x4 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedMultiplySubAdd231(y Float64x4, z Float64x4) Float64x4 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedNegativeMultiplyAdd132(y Float64x4, z Float64x4) Float64x4 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedNegativeMultiplyAdd213(y Float64x4, z Float64x4) Float64x4 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedNegativeMultiplyAdd231(y Float64x4, z Float64x4) Float64x4 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedNegativeMultiplySub132(y Float64x4, z Float64x4) Float64x4 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedNegativeMultiplySub213(y Float64x4, z Float64x4) Float64x4 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x4) FusedNegativeMultiplySub231(y Float64x4, z Float64x4) Float64x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedAdd(y Float64x4, z Mask64x4) Float64x4 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedAnd(y Float64x4, z Mask64x4) Float64x4 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedAndNot(y Float64x4, z Mask64x4) Float64x4 + +// Div divides elements of two vectors. +// +// Asm: VDIVPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiv(y Float64x4, z Mask64x4) Float64x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedEqual(y Float64x4, z Mask64x4) Mask64x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedGreater(y Float64x4, z Mask64x4) Mask64x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedGreaterEqual(y Float64x4, z Mask64x4) Mask64x4 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedIsNan(y Float64x4, z Mask64x4) Mask64x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedLess(y Float64x4, z Mask64x4) Mask64x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedLessEqual(y Float64x4, z Mask64x4) Mask64x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedMax(y Float64x4, z Mask64x4) Float64x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedMin(y Float64x4, z Mask64x4) Float64x4 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedMul(y Float64x4, z Mask64x4) Float64x4 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedMulByPowOf2(y Float64x4, z Mask64x4) Float64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedNotEqual(y Float64x4, z Mask64x4) Mask64x4 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedOr(y Float64x4, z Mask64x4) Float64x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedSub(y Float64x4, z Mask64x4) Float64x4 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedXor(y Float64x4, z Mask64x4) Float64x4 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplyAdd132(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplyAdd213(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplyAdd231(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplyAddSub132(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplyAddSub213(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplyAddSub231(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplySub132(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplySub213(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplySub231(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplySubAdd132(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplySubAdd213(y Float64x8, z Float64x8) Float64x8 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedMultiplySubAdd231(y Float64x8, z Float64x8) Float64x8 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedNegativeMultiplyAdd132(y Float64x8, z Float64x8) Float64x8 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedNegativeMultiplyAdd213(y Float64x8, z Float64x8) Float64x8 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedNegativeMultiplyAdd231(y Float64x8, z Float64x8) Float64x8 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedNegativeMultiplySub132(y Float64x8, z Float64x8) Float64x8 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedNegativeMultiplySub213(y Float64x8, z Float64x8) Float64x8 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x8) FusedNegativeMultiplySub231(y Float64x8, z Float64x8) Float64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedAdd(y Float64x8, z Mask64x8) Float64x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VANDPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedAnd(y Float64x8, z Mask64x8) Float64x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VANDNPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedAndNot(y Float64x8, z Mask64x8) Float64x8 + +// Div divides elements of two vectors. +// +// Asm: VDIVPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiv(y Float64x8, z Mask64x8) Float64x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedEqual(y Float64x8, z Mask64x8) Mask64x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedGreater(y Float64x8, z Mask64x8) Mask64x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedGreaterEqual(y Float64x8, z Mask64x8) Mask64x8 + +// IsNan checks if elements are NaN. Use as x.IsNan(x). +// Const Immediate = 3. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedIsNan(y Float64x8, z Mask64x8) Mask64x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedLess(y Float64x8, z Mask64x8) Mask64x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedLessEqual(y Float64x8, z Mask64x8) Mask64x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VMAXPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedMax(y Float64x8, z Mask64x8) Float64x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VMINPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedMin(y Float64x8, z Mask64x8) Float64x8 + +// Mul multiplies corresponding elements of two vectors, masked. +// +// Asm: VMULPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedMul(y Float64x8, z Mask64x8) Float64x8 + +// MulByPowOf2 multiplies elements by a power of 2. +// +// Asm: VSCALEFPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedMulByPowOf2(y Float64x8, z Mask64x8) Float64x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VCMPPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedNotEqual(y Float64x8, z Mask64x8) Mask64x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VORPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedOr(y Float64x8, z Mask64x8) Float64x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VADDPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedSub(y Float64x8, z Mask64x8) Float64x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VXORPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedXor(y Float64x8, z Mask64x8) Float64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedAdd(y Int16x16, z Mask16x16) Int16x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedEqual(y Int16x16, z Mask16x16) Mask16x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedGreater(y Int16x16, z Mask16x16) Mask16x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedGreaterEqual(y Int16x16, z Mask16x16) Mask16x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedLess(y Int16x16, z Mask16x16) Mask16x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedLessEqual(y Int16x16, z Mask16x16) Mask16x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedMax(y Int16x16, z Mask16x16) Int16x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedMin(y Int16x16, z Mask16x16) Int16x16 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedMulHigh(y Int16x16, z Mask16x16) Int16x16 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedMulLow(y Int16x16, z Mask16x16) Int16x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedNotEqual(y Int16x16, z Mask16x16) Mask16x16 + +// PairDotProd multiplies the elements and add the pairs together, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDWD, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedPairDotProd(y Int16x16, z Mask16x16) Int32x8 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedSaturatedAdd(y Int16x16, z Mask16x16) Int16x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedSaturatedSub(y Int16x16, z Mask16x16) Int16x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Int16x16) MaskedSub(y Int16x16, z Mask16x16) Int16x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedAdd(y Int16x32, z Mask16x32) Int16x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedEqual(y Int16x32, z Mask16x32) Mask16x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedGreater(y Int16x32, z Mask16x32) Mask16x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedGreaterEqual(y Int16x32, z Mask16x32) Mask16x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedLess(y Int16x32, z Mask16x32) Mask16x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedLessEqual(y Int16x32, z Mask16x32) Mask16x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedMax(y Int16x32, z Mask16x32) Int16x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedMin(y Int16x32, z Mask16x32) Int16x32 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedMulHigh(y Int16x32, z Mask16x32) Int16x32 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedMulLow(y Int16x32, z Mask16x32) Int16x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedNotEqual(y Int16x32, z Mask16x32) Mask16x32 + +// PairDotProd multiplies the elements and add the pairs together, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDWD, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedPairDotProd(y Int16x32, z Mask16x32) Int32x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedSaturatedAdd(y Int16x32, z Mask16x32) Int16x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedSaturatedSub(y Int16x32, z Mask16x32) Int16x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Int16x32) MaskedSub(y Int16x32, z Mask16x32) Int16x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedAdd(y Int16x8, z Mask16x8) Int16x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedEqual(y Int16x8, z Mask16x8) Mask16x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedGreater(y Int16x8, z Mask16x8) Mask16x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedGreaterEqual(y Int16x8, z Mask16x8) Mask16x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedLess(y Int16x8, z Mask16x8) Mask16x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedLessEqual(y Int16x8, z Mask16x8) Mask16x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedMax(y Int16x8, z Mask16x8) Int16x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedMin(y Int16x8, z Mask16x8) Int16x8 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedMulHigh(y Int16x8, z Mask16x8) Int16x8 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedMulLow(y Int16x8, z Mask16x8) Int16x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedNotEqual(y Int16x8, z Mask16x8) Mask16x8 + +// PairDotProd multiplies the elements and add the pairs together, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDWD, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedPairDotProd(y Int16x8, z Mask16x8) Int32x4 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedSaturatedAdd(y Int16x8, z Mask16x8) Int16x8 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedSaturatedSub(y Int16x8, z Mask16x8) Int16x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Int16x8) MaskedSub(y Int16x8, z Mask16x8) Int16x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedAdd(y Int32x16, z Mask32x16) Int32x16 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedAnd(y Int32x16, z Mask32x16) Int32x16 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedAndNot(y Int32x16, z Mask32x16) Int32x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedEqual(y Int32x16, z Mask32x16) Mask32x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedGreater(y Int32x16, z Mask32x16) Mask32x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedGreaterEqual(y Int32x16, z Mask32x16) Mask32x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedLess(y Int32x16, z Mask32x16) Mask32x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedLessEqual(y Int32x16, z Mask32x16) Mask32x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedMax(y Int32x16, z Mask32x16) Int32x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedMin(y Int32x16, z Mask32x16) Int32x16 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedMulLow(y Int32x16, z Mask32x16) Int32x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedNotEqual(y Int32x16, z Mask32x16) Mask32x16 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedOr(y Int32x16, z Mask32x16) Int32x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedSub(y Int32x16, z Mask32x16) Int32x16 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedXor(y Int32x16, z Mask32x16) Int32x16 + +// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSD, CPU Feature: AVX512EVEX +func (x Int32x16) PairDotProdAccumulate(y Int16x32, z Int32x16) Int32x16 + +// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSDS, CPU Feature: AVX512EVEX +func (x Int32x16) SaturatedPairDotProdAccumulate(y Int16x32, z Int32x16) Int32x16 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Int32x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16) Int32x16 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Int32x16) UnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16) Int32x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedAdd(y Int32x4, z Mask32x4) Int32x4 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedAnd(y Int32x4, z Mask32x4) Int32x4 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedAndNot(y Int32x4, z Mask32x4) Int32x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedEqual(y Int32x4, z Mask32x4) Mask32x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedGreater(y Int32x4, z Mask32x4) Mask32x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedGreaterEqual(y Int32x4, z Mask32x4) Mask32x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedLess(y Int32x4, z Mask32x4) Mask32x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedLessEqual(y Int32x4, z Mask32x4) Mask32x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedMax(y Int32x4, z Mask32x4) Int32x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedMin(y Int32x4, z Mask32x4) Int32x4 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedMulLow(y Int32x4, z Mask32x4) Int32x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedNotEqual(y Int32x4, z Mask32x4) Mask32x4 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedOr(y Int32x4, z Mask32x4) Int32x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedSub(y Int32x4, z Mask32x4) Int32x4 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedXor(y Int32x4, z Mask32x4) Int32x4 + +// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSD, CPU Feature: AVX_VNNI +func (x Int32x4) PairDotProdAccumulate(y Int32x4, z Int32x4) Int32x4 + +// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSDS, CPU Feature: AVX_VNNI +func (x Int32x4) SaturatedPairDotProdAccumulate(y Int32x4, z Int32x4) Int32x4 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI +func (x Int32x4) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint32x4, z Int32x4) Int32x4 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX_VNNI +func (x Int32x4) UnsignedSignedQuadDotProdAccumulate(y Uint32x4, z Int32x4) Int32x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedAdd(y Int32x8, z Mask32x8) Int32x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedAnd(y Int32x8, z Mask32x8) Int32x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedAndNot(y Int32x8, z Mask32x8) Int32x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedEqual(y Int32x8, z Mask32x8) Mask32x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedGreater(y Int32x8, z Mask32x8) Mask32x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedGreaterEqual(y Int32x8, z Mask32x8) Mask32x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedLess(y Int32x8, z Mask32x8) Mask32x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedLessEqual(y Int32x8, z Mask32x8) Mask32x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedMax(y Int32x8, z Mask32x8) Int32x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedMin(y Int32x8, z Mask32x8) Int32x8 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedMulLow(y Int32x8, z Mask32x8) Int32x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedNotEqual(y Int32x8, z Mask32x8) Mask32x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedOr(y Int32x8, z Mask32x8) Int32x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedSub(y Int32x8, z Mask32x8) Int32x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedXor(y Int32x8, z Mask32x8) Int32x8 + +// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSD, CPU Feature: AVX_VNNI +func (x Int32x8) PairDotProdAccumulate(y Int32x8, z Int32x8) Int32x8 + +// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSDS, CPU Feature: AVX_VNNI +func (x Int32x8) SaturatedPairDotProdAccumulate(y Int32x8, z Int32x8) Int32x8 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI +func (x Int32x8) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint32x8, z Int32x8) Int32x8 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX_VNNI +func (x Int32x8) UnsignedSignedQuadDotProdAccumulate(y Uint32x8, z Int32x8) Int32x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedAdd(y Int64x2, z Mask64x2) Int64x2 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedAnd(y Int64x2, z Mask64x2) Int64x2 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedAndNot(y Int64x2, z Mask64x2) Int64x2 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedEqual(y Int64x2, z Mask64x2) Mask64x2 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedGreater(y Int64x2, z Mask64x2) Mask64x2 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedGreaterEqual(y Int64x2, z Mask64x2) Mask64x2 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedLess(y Int64x2, z Mask64x2) Mask64x2 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedLessEqual(y Int64x2, z Mask64x2) Mask64x2 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedMax(y Int64x2, z Mask64x2) Int64x2 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedMin(y Int64x2, z Mask64x2) Int64x2 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedMulEvenWiden(y Int64x2, z Mask64x2) Int64x2 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedMulLow(y Int64x2, z Mask64x2) Int64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedNotEqual(y Int64x2, z Mask64x2) Mask64x2 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedOr(y Int64x2, z Mask64x2) Int64x2 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedSub(y Int64x2, z Mask64x2) Int64x2 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Int64x2) MaskedXor(y Int64x2, z Mask64x2) Int64x2 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedAdd(y Int64x4, z Mask64x4) Int64x4 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedAnd(y Int64x4, z Mask64x4) Int64x4 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedAndNot(y Int64x4, z Mask64x4) Int64x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedEqual(y Int64x4, z Mask64x4) Mask64x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedGreater(y Int64x4, z Mask64x4) Mask64x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedGreaterEqual(y Int64x4, z Mask64x4) Mask64x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedLess(y Int64x4, z Mask64x4) Mask64x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedLessEqual(y Int64x4, z Mask64x4) Mask64x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedMax(y Int64x4, z Mask64x4) Int64x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedMin(y Int64x4, z Mask64x4) Int64x4 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedMulEvenWiden(y Int64x4, z Mask64x4) Int64x4 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedMulLow(y Int64x4, z Mask64x4) Int64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedNotEqual(y Int64x4, z Mask64x4) Mask64x4 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedOr(y Int64x4, z Mask64x4) Int64x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedSub(y Int64x4, z Mask64x4) Int64x4 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Int64x4) MaskedXor(y Int64x4, z Mask64x4) Int64x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedAdd(y Int64x8, z Mask64x8) Int64x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedAnd(y Int64x8, z Mask64x8) Int64x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedAndNot(y Int64x8, z Mask64x8) Int64x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedEqual(y Int64x8, z Mask64x8) Mask64x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedGreater(y Int64x8, z Mask64x8) Mask64x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedGreaterEqual(y Int64x8, z Mask64x8) Mask64x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedLess(y Int64x8, z Mask64x8) Mask64x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedLessEqual(y Int64x8, z Mask64x8) Mask64x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedMax(y Int64x8, z Mask64x8) Int64x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedMin(y Int64x8, z Mask64x8) Int64x8 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULDQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedMulEvenWiden(y Int64x8, z Mask64x8) Int64x8 + +// MulLow multiplies elements and stores the low part of the result, masked. +// +// Asm: VPMULLQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedMulLow(y Int64x8, z Mask64x8) Int64x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedNotEqual(y Int64x8, z Mask64x8) Mask64x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedOr(y Int64x8, z Mask64x8) Int64x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedSub(y Int64x8, z Mask64x8) Int64x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Int64x8) MaskedXor(y Int64x8, z Mask64x8) Int64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedAdd(y Int8x16, z Mask8x16) Int8x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedEqual(y Int8x16, z Mask8x16) Mask8x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedGreater(y Int8x16, z Mask8x16) Mask8x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedGreaterEqual(y Int8x16, z Mask8x16) Mask8x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedLess(y Int8x16, z Mask8x16) Mask8x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedLessEqual(y Int8x16, z Mask8x16) Mask8x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedMax(y Int8x16, z Mask8x16) Int8x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedMin(y Int8x16, z Mask8x16) Int8x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedNotEqual(y Int8x16, z Mask8x16) Mask8x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedSaturatedAdd(y Int8x16, z Mask8x16) Int8x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedSaturatedSub(y Int8x16, z Mask8x16) Int8x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Int8x16) MaskedSub(y Int8x16, z Mask8x16) Int8x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedAdd(y Int8x32, z Mask8x32) Int8x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedEqual(y Int8x32, z Mask8x32) Mask8x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedGreater(y Int8x32, z Mask8x32) Mask8x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedGreaterEqual(y Int8x32, z Mask8x32) Mask8x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedLess(y Int8x32, z Mask8x32) Mask8x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedLessEqual(y Int8x32, z Mask8x32) Mask8x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedMax(y Int8x32, z Mask8x32) Int8x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedMin(y Int8x32, z Mask8x32) Int8x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedNotEqual(y Int8x32, z Mask8x32) Mask8x32 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedSaturatedAdd(y Int8x32, z Mask8x32) Int8x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedSaturatedSub(y Int8x32, z Mask8x32) Int8x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Int8x32) MaskedSub(y Int8x32, z Mask8x32) Int8x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedAdd(y Int8x64, z Mask8x64) Int8x64 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPEQB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedEqual(y Int8x64, z Mask8x64) Mask8x64 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPGTB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedGreater(y Int8x64, z Mask8x64) Mask8x64 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedGreaterEqual(y Int8x64, z Mask8x64) Mask8x64 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedLess(y Int8x64, z Mask8x64) Mask8x64 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedLessEqual(y Int8x64, z Mask8x64) Mask8x64 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXSB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedMax(y Int8x64, z Mask8x64) Int8x64 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINSB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedMin(y Int8x64, z Mask8x64) Int8x64 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedNotEqual(y Int8x64, z Mask8x64) Mask8x64 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedSaturatedAdd(y Int8x64, z Mask8x64) Int8x64 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedSaturatedSub(y Int8x64, z Mask8x64) Int8x64 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Int8x64) MaskedSub(y Int8x64, z Mask8x64) Int8x64 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedAdd(y Uint16x16, z Mask16x16) Uint16x16 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedAverage(y Uint16x16, z Mask16x16) Uint16x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedEqual(y Uint16x16, z Mask16x16) Mask16x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedGreater(y Uint16x16, z Mask16x16) Mask16x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedGreaterEqual(y Uint16x16, z Mask16x16) Mask16x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedLess(y Uint16x16, z Mask16x16) Mask16x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedLessEqual(y Uint16x16, z Mask16x16) Mask16x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedMax(y Uint16x16, z Mask16x16) Uint16x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedMin(y Uint16x16, z Mask16x16) Uint16x16 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedMulHigh(y Uint16x16, z Mask16x16) Uint16x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedNotEqual(y Uint16x16, z Mask16x16) Mask16x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedSaturatedAdd(y Uint16x16, z Mask16x16) Uint16x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedSaturatedSub(y Uint16x16, z Mask16x16) Uint16x16 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedSaturatedUnsignedSignedPairDotProd(y Int16x16, z Mask16x16) Int16x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Uint16x16) MaskedSub(y Uint16x16, z Mask16x16) Uint16x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedAdd(y Uint16x32, z Mask16x32) Uint16x32 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedAverage(y Uint16x32, z Mask16x32) Uint16x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedEqual(y Uint16x32, z Mask16x32) Mask16x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedGreater(y Uint16x32, z Mask16x32) Mask16x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedGreaterEqual(y Uint16x32, z Mask16x32) Mask16x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedLess(y Uint16x32, z Mask16x32) Mask16x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedLessEqual(y Uint16x32, z Mask16x32) Mask16x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedMax(y Uint16x32, z Mask16x32) Uint16x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedMin(y Uint16x32, z Mask16x32) Uint16x32 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedMulHigh(y Uint16x32, z Mask16x32) Uint16x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedNotEqual(y Uint16x32, z Mask16x32) Mask16x32 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedSaturatedAdd(y Uint16x32, z Mask16x32) Uint16x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedSaturatedSub(y Uint16x32, z Mask16x32) Uint16x32 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedSaturatedUnsignedSignedPairDotProd(y Int16x32, z Mask16x32) Int16x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Uint16x32) MaskedSub(y Uint16x32, z Mask16x32) Uint16x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedAdd(y Uint16x8, z Mask16x8) Uint16x8 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedAverage(y Uint16x8, z Mask16x8) Uint16x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedEqual(y Uint16x8, z Mask16x8) Mask16x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedGreater(y Uint16x8, z Mask16x8) Mask16x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedGreaterEqual(y Uint16x8, z Mask16x8) Mask16x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedLess(y Uint16x8, z Mask16x8) Mask16x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedLessEqual(y Uint16x8, z Mask16x8) Mask16x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedMax(y Uint16x8, z Mask16x8) Uint16x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedMin(y Uint16x8, z Mask16x8) Uint16x8 + +// MulHigh multiplies elements and stores the high part of the result, masked. +// +// Asm: VPMULHUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedMulHigh(y Uint16x8, z Mask16x8) Uint16x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedNotEqual(y Uint16x8, z Mask16x8) Mask16x8 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedSaturatedAdd(y Uint16x8, z Mask16x8) Uint16x8 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedSaturatedSub(y Uint16x8, z Mask16x8) Uint16x8 + +// SaturatedPairDotProd multiplies the elements and add the pairs together with saturation, +// yielding a vector of half as many elements with twice the input element size. +// +// Asm: VPMADDUBSW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedSaturatedUnsignedSignedPairDotProd(y Int16x8, z Mask16x8) Int16x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBW, CPU Feature: AVX512EVEX +func (x Uint16x8) MaskedSub(y Uint16x8, z Mask16x8) Uint16x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedAdd(y Uint32x16, z Mask32x16) Uint32x16 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedAnd(y Uint32x16, z Mask32x16) Uint32x16 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedAndNot(y Uint32x16, z Mask32x16) Uint32x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedEqual(y Uint32x16, z Mask32x16) Mask32x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedGreater(y Uint32x16, z Mask32x16) Mask32x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedGreaterEqual(y Uint32x16, z Mask32x16) Mask32x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedLess(y Uint32x16, z Mask32x16) Mask32x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedLessEqual(y Uint32x16, z Mask32x16) Mask32x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedMax(y Uint32x16, z Mask32x16) Uint32x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedMin(y Uint32x16, z Mask32x16) Uint32x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedNotEqual(y Uint32x16, z Mask32x16) Mask32x16 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedOr(y Uint32x16, z Mask32x16) Uint32x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedSub(y Uint32x16, z Mask32x16) Uint32x16 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedXor(y Uint32x16, z Mask32x16) Uint32x16 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Uint32x16) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16) Uint32x16 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Uint32x16) UnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16) Uint32x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedAdd(y Uint32x4, z Mask32x4) Uint32x4 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedAnd(y Uint32x4, z Mask32x4) Uint32x4 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedAndNot(y Uint32x4, z Mask32x4) Uint32x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedEqual(y Uint32x4, z Mask32x4) Mask32x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedGreater(y Uint32x4, z Mask32x4) Mask32x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedGreaterEqual(y Uint32x4, z Mask32x4) Mask32x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedLess(y Uint32x4, z Mask32x4) Mask32x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedLessEqual(y Uint32x4, z Mask32x4) Mask32x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedMax(y Uint32x4, z Mask32x4) Uint32x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedMin(y Uint32x4, z Mask32x4) Uint32x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedNotEqual(y Uint32x4, z Mask32x4) Mask32x4 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedOr(y Uint32x4, z Mask32x4) Uint32x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedSub(y Uint32x4, z Mask32x4) Uint32x4 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedXor(y Uint32x4, z Mask32x4) Uint32x4 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI +func (x Uint32x4) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint32x4, z Int32x4) Uint32x4 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX_VNNI +func (x Uint32x4) UnsignedSignedQuadDotProdAccumulate(y Uint32x4, z Int32x4) Uint32x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedAdd(y Uint32x8, z Mask32x8) Uint32x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedAnd(y Uint32x8, z Mask32x8) Uint32x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDND, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedAndNot(y Uint32x8, z Mask32x8) Uint32x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedEqual(y Uint32x8, z Mask32x8) Mask32x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedGreater(y Uint32x8, z Mask32x8) Mask32x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedGreaterEqual(y Uint32x8, z Mask32x8) Mask32x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedLess(y Uint32x8, z Mask32x8) Mask32x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedLessEqual(y Uint32x8, z Mask32x8) Mask32x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedMax(y Uint32x8, z Mask32x8) Uint32x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedMin(y Uint32x8, z Mask32x8) Uint32x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedNotEqual(y Uint32x8, z Mask32x8) Mask32x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedOr(y Uint32x8, z Mask32x8) Uint32x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedSub(y Uint32x8, z Mask32x8) Uint32x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedXor(y Uint32x8, z Mask32x8) Uint32x8 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX_VNNI +func (x Uint32x8) SaturatedUnsignedSignedQuadDotProdAccumulate(y Uint32x8, z Int32x8) Uint32x8 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX_VNNI +func (x Uint32x8) UnsignedSignedQuadDotProdAccumulate(y Uint32x8, z Int32x8) Uint32x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedAdd(y Uint64x2, z Mask64x2) Uint64x2 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedAnd(y Uint64x2, z Mask64x2) Uint64x2 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedAndNot(y Uint64x2, z Mask64x2) Uint64x2 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedEqual(y Uint64x2, z Mask64x2) Mask64x2 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedGreater(y Uint64x2, z Mask64x2) Mask64x2 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedGreaterEqual(y Uint64x2, z Mask64x2) Mask64x2 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedLess(y Uint64x2, z Mask64x2) Mask64x2 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedLessEqual(y Uint64x2, z Mask64x2) Mask64x2 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedMax(y Uint64x2, z Mask64x2) Uint64x2 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedMin(y Uint64x2, z Mask64x2) Uint64x2 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedMulEvenWiden(y Uint64x2, z Mask64x2) Uint64x2 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedNotEqual(y Uint64x2, z Mask64x2) Mask64x2 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedOr(y Uint64x2, z Mask64x2) Uint64x2 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedSub(y Uint64x2, z Mask64x2) Uint64x2 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Uint64x2) MaskedXor(y Uint64x2, z Mask64x2) Uint64x2 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedAdd(y Uint64x4, z Mask64x4) Uint64x4 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedAnd(y Uint64x4, z Mask64x4) Uint64x4 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedAndNot(y Uint64x4, z Mask64x4) Uint64x4 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedEqual(y Uint64x4, z Mask64x4) Mask64x4 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedGreater(y Uint64x4, z Mask64x4) Mask64x4 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedGreaterEqual(y Uint64x4, z Mask64x4) Mask64x4 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedLess(y Uint64x4, z Mask64x4) Mask64x4 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedLessEqual(y Uint64x4, z Mask64x4) Mask64x4 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedMax(y Uint64x4, z Mask64x4) Uint64x4 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedMin(y Uint64x4, z Mask64x4) Uint64x4 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedMulEvenWiden(y Uint64x4, z Mask64x4) Uint64x4 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedNotEqual(y Uint64x4, z Mask64x4) Mask64x4 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedOr(y Uint64x4, z Mask64x4) Uint64x4 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedSub(y Uint64x4, z Mask64x4) Uint64x4 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Uint64x4) MaskedXor(y Uint64x4, z Mask64x4) Uint64x4 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedAdd(y Uint64x8, z Mask64x8) Uint64x8 + +// And performs a masked bitwise AND operation between two vectors. +// +// Asm: VPANDQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedAnd(y Uint64x8, z Mask64x8) Uint64x8 + +// AndNot performs a masked bitwise AND NOT operation between two vectors. +// +// Asm: VPANDNQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedAndNot(y Uint64x8, z Mask64x8) Uint64x8 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedEqual(y Uint64x8, z Mask64x8) Mask64x8 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedGreater(y Uint64x8, z Mask64x8) Mask64x8 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedGreaterEqual(y Uint64x8, z Mask64x8) Mask64x8 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedLess(y Uint64x8, z Mask64x8) Mask64x8 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedLessEqual(y Uint64x8, z Mask64x8) Mask64x8 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedMax(y Uint64x8, z Mask64x8) Uint64x8 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedMin(y Uint64x8, z Mask64x8) Uint64x8 + +// MulEvenWiden multiplies even-indexed elements, widening the result, masked. +// Result[i] = v1.Even[i] * v2.Even[i]. +// +// Asm: VPMULUDQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedMulEvenWiden(y Uint64x8, z Mask64x8) Uint64x8 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedNotEqual(y Uint64x8, z Mask64x8) Mask64x8 + +// Or performs a masked bitwise OR operation between two vectors. +// +// Asm: VPORQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedOr(y Uint64x8, z Mask64x8) Uint64x8 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedSub(y Uint64x8, z Mask64x8) Uint64x8 + +// Xor performs a masked bitwise XOR operation between two vectors. +// +// Asm: VPXORQ, CPU Feature: AVX512EVEX +func (x Uint64x8) MaskedXor(y Uint64x8, z Mask64x8) Uint64x8 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedAdd(y Uint8x16, z Mask8x16) Uint8x16 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedAverage(y Uint8x16, z Mask8x16) Uint8x16 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedEqual(y Uint8x16, z Mask8x16) Mask8x16 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedGreater(y Uint8x16, z Mask8x16) Mask8x16 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedGreaterEqual(y Uint8x16, z Mask8x16) Mask8x16 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedLess(y Uint8x16, z Mask8x16) Mask8x16 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedLessEqual(y Uint8x16, z Mask8x16) Mask8x16 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedMax(y Uint8x16, z Mask8x16) Uint8x16 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedMin(y Uint8x16, z Mask8x16) Uint8x16 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedNotEqual(y Uint8x16, z Mask8x16) Mask8x16 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedSaturatedAdd(y Uint8x16, z Mask8x16) Uint8x16 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedSaturatedSub(y Uint8x16, z Mask8x16) Uint8x16 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Uint8x16) MaskedSub(y Uint8x16, z Mask8x16) Uint8x16 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedAdd(y Uint8x32, z Mask8x32) Uint8x32 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedAverage(y Uint8x32, z Mask8x32) Uint8x32 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedEqual(y Uint8x32, z Mask8x32) Mask8x32 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedGreater(y Uint8x32, z Mask8x32) Mask8x32 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedGreaterEqual(y Uint8x32, z Mask8x32) Mask8x32 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedLess(y Uint8x32, z Mask8x32) Mask8x32 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedLessEqual(y Uint8x32, z Mask8x32) Mask8x32 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedMax(y Uint8x32, z Mask8x32) Uint8x32 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedMin(y Uint8x32, z Mask8x32) Uint8x32 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedNotEqual(y Uint8x32, z Mask8x32) Mask8x32 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedSaturatedAdd(y Uint8x32, z Mask8x32) Uint8x32 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedSaturatedSub(y Uint8x32, z Mask8x32) Uint8x32 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Uint8x32) MaskedSub(y Uint8x32, z Mask8x32) Uint8x32 + +// Add adds corresponding elements of two vectors. +// +// Asm: VPADDB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedAdd(y Uint8x64, z Mask8x64) Uint8x64 + +// Average computes the rounded average of corresponding elements. +// +// Asm: VPAVGB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedAverage(y Uint8x64, z Mask8x64) Uint8x64 + +// Equal compares for equality, masked. +// Const Immediate = 0. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedEqual(y Uint8x64, z Mask8x64) Mask8x64 + +// Greater compares for greater than. +// Const Immediate = 6. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedGreater(y Uint8x64, z Mask8x64) Mask8x64 + +// GreaterEqual compares for greater than or equal. +// Const Immediate = 5. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedGreaterEqual(y Uint8x64, z Mask8x64) Mask8x64 + +// Less compares for less than. +// Const Immediate = 1. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedLess(y Uint8x64, z Mask8x64) Mask8x64 + +// LessEqual compares for less than or equal. +// Const Immediate = 2. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedLessEqual(y Uint8x64, z Mask8x64) Mask8x64 + +// Max computes the maximum of corresponding elements. +// +// Asm: VPMAXUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedMax(y Uint8x64, z Mask8x64) Uint8x64 + +// Min computes the minimum of corresponding elements. +// +// Asm: VPMINUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedMin(y Uint8x64, z Mask8x64) Uint8x64 + +// NotEqual compares for inequality. +// Const Immediate = 4. +// +// Asm: VPCMPUB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedNotEqual(y Uint8x64, z Mask8x64) Mask8x64 + +// SaturatedAdd adds corresponding elements of two vectors with saturation. +// +// Asm: VPADDSB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedSaturatedAdd(y Uint8x64, z Mask8x64) Uint8x64 + +// SaturatedSub subtracts corresponding elements of two vectors with saturation. +// +// Asm: VPSUBSB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedSaturatedSub(y Uint8x64, z Mask8x64) Uint8x64 + +// Sub subtracts corresponding elements of two vectors. +// +// Asm: VPSUBB, CPU Feature: AVX512EVEX +func (x Uint8x64) MaskedSub(y Uint8x64, z Mask8x64) Uint8x64 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplyAdd132(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplyAdd213(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplyAdd231(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplyAddSub132(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplyAddSub213(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplyAddSub231(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplySub132(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplySub213(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplySub231(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplySubAdd132(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplySubAdd213(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedMultiplySubAdd231(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedNegativeMultiplyAdd132(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedNegativeMultiplyAdd213(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedNegativeMultiplyAdd231(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedNegativeMultiplySub132(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedNegativeMultiplySub213(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFusedNegativeMultiplySub231(y Float32x16, z Float32x16, u Mask32x16) Float32x16 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplyAdd132(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplyAdd213(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplyAdd231(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplyAddSub132(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplyAddSub213(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplyAddSub231(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplySub132(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplySub213(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplySub231(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplySubAdd132(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplySubAdd213(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedMultiplySubAdd231(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedNegativeMultiplyAdd132(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedNegativeMultiplyAdd213(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedNegativeMultiplyAdd231(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedNegativeMultiplySub132(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedNegativeMultiplySub213(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFusedNegativeMultiplySub231(y Float32x4, z Float32x4, u Mask32x4) Float32x4 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplyAdd132(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplyAdd213(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplyAdd231(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplyAddSub132(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplyAddSub213(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplyAddSub231(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplySub132(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplySub213(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplySub231(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplySubAdd132(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplySubAdd213(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedMultiplySubAdd231(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedNegativeMultiplyAdd132(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedNegativeMultiplyAdd213(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedNegativeMultiplyAdd231(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedNegativeMultiplySub132(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedNegativeMultiplySub213(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFusedNegativeMultiplySub231(y Float32x8, z Float32x8, u Mask32x8) Float32x8 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplyAdd132(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplyAdd213(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplyAdd231(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplyAddSub132(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplyAddSub213(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplyAddSub231(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplySub132(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplySub213(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplySub231(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplySubAdd132(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplySubAdd213(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedMultiplySubAdd231(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedNegativeMultiplyAdd132(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedNegativeMultiplyAdd213(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedNegativeMultiplyAdd231(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedNegativeMultiplySub132(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedNegativeMultiplySub213(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFusedNegativeMultiplySub231(y Float64x2, z Float64x2, u Mask64x2) Float64x2 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplyAdd132(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplyAdd213(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplyAdd231(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplyAddSub132(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplyAddSub213(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplyAddSub231(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplySub132(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplySub213(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplySub231(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplySubAdd132(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplySubAdd213(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedMultiplySubAdd231(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedNegativeMultiplyAdd132(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedNegativeMultiplyAdd213(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedNegativeMultiplyAdd231(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedNegativeMultiplySub132(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedNegativeMultiplySub213(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFusedNegativeMultiplySub231(y Float64x4, z Float64x4, u Mask64x4) Float64x4 + +// FusedMultiplyAdd132 performs `(v1 * v3) + v2`. +// +// Asm: VFMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplyAdd132(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplyAdd213 performs `(v2 * v1) + v3`. +// +// Asm: VFMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplyAdd213(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplyAdd231 performs `(v2 * v3) + v1`. +// +// Asm: VFMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplyAdd231(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplyAddSub132 performs `(v1 * v3) - v2` for odd-indexed elements, and `(v1 * v3) + v2` for even-indexed elements. +// +// Asm: VFMADDSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplyAddSub132(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplyAddSub213 performs `(v2 * v1) - v3` for odd-indexed elements, and `(v2 * v1) + v3` for even-indexed elements. +// +// Asm: VFMADDSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplyAddSub213(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplyAddSub231 performs `(v2 * v3) - v1` for odd-indexed elements, and `(v2 * v3) + v1` for even-indexed elements. +// +// Asm: VFMADDSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplyAddSub231(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplySub132 performs `(v1 * v3) - v2`. +// +// Asm: VFMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplySub132(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplySub213 performs `(v2 * v1) - v3`. +// +// Asm: VFMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplySub213(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplySub231 performs `(v2 * v3) - v1`. +// +// Asm: VFMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplySub231(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplySubAdd132 performs `(v1 * v3) + v2` for odd-indexed elements, and `(v1 * v3) - v2` for even-indexed elements. +// +// Asm: VFMSUBADD132PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplySubAdd132(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplySubAdd213 performs `(v2 * v1) + v3` for odd-indexed elements, and `(v2 * v1) - v3` for even-indexed elements. +// +// Asm: VFMSUBADD213PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplySubAdd213(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedMultiplySubAdd231 performs `(v2 * v3) + v1` for odd-indexed elements, and `(v2 * v3) - v1` for even-indexed elements. +// +// Asm: VFMSUBADD231PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedMultiplySubAdd231(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedNegativeMultiplyAdd132 performs `-(v1 * v3) + v2`. +// +// Asm: VFNMADD132PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedNegativeMultiplyAdd132(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedNegativeMultiplyAdd213 performs `-(v2 * v1) + v3`. +// +// Asm: VFNMADD213PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedNegativeMultiplyAdd213(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedNegativeMultiplyAdd231 performs `-(v2 * v3) + v1`. +// +// Asm: VFNMADD231PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedNegativeMultiplyAdd231(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedNegativeMultiplySub132 performs `-(v1 * v3) - v2`. +// +// Asm: VFNMSUB132PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedNegativeMultiplySub132(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedNegativeMultiplySub213 performs `-(v2 * v1) - v3`. +// +// Asm: VFNMSUB213PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedNegativeMultiplySub213(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// FusedNegativeMultiplySub231 performs `-(v2 * v3) - v1`. +// +// Asm: VFNMSUB231PD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFusedNegativeMultiplySub231(y Float64x8, z Float64x8, u Mask64x8) Float64x8 + +// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedPairDotProdAccumulate(y Int16x32, z Int32x16, u Mask32x16) Int32x16 + +// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSDS, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedSaturatedPairDotProdAccumulate(y Int16x32, z Int32x16, u Mask32x16) Int32x16 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16, u Mask32x16) Int32x16 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Int32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16, u Mask32x16) Int32x16 + +// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedPairDotProdAccumulate(y Int16x8, z Int32x4, u Mask32x4) Int32x4 + +// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSDS, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedSaturatedPairDotProdAccumulate(y Int16x8, z Int32x4, u Mask32x4) Int32x4 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int32x4, u Mask32x4) Int32x4 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Int32x4) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int32x4, u Mask32x4) Int32x4 + +// PairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedPairDotProdAccumulate(y Int16x16, z Int32x8, u Mask32x8) Int32x8 + +// SaturatedPairDotProdAccumulate performs dot products on pairs of elements of y and z and accumulates the results to x. +// +// Asm: VPDPWSSDS, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedSaturatedPairDotProdAccumulate(y Int16x16, z Int32x8, u Mask32x8) Int32x8 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int32x8, u Mask32x8) Int32x8 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Int32x8) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int32x8, u Mask32x8) Int32x8 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16, u Mask32x16) Uint32x16 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Uint32x16) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x64, z Int32x16, u Mask32x16) Uint32x16 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int32x4, u Mask32x4) Uint32x4 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Uint32x4) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x16, z Int32x4, u Mask32x4) Uint32x4 + +// SaturatedUnsignedSignedQuadDotProdAccumulate multiplies performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSDS, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedSaturatedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int32x8, u Mask32x8) Uint32x8 + +// UnsignedSignedQuadDotProdAccumulate performs dot products on groups of 4 elements of y and z and accumulates the results to x. +// +// Asm: VPDPBUSD, CPU Feature: AVX512EVEX +func (x Uint32x8) MaskedUnsignedSignedQuadDotProdAccumulate(y Uint8x32, z Int32x8, u Mask32x8) Uint32x8 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) CeilSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) CeilSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) CeilSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) CeilSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) CeilSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) CeilSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) CeilWithPrecision(imm8 uint8) Float32x16 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) CeilWithPrecision(imm8 uint8) Float32x4 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) CeilWithPrecision(imm8 uint8) Float32x8 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) CeilWithPrecision(imm8 uint8) Float64x2 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) CeilWithPrecision(imm8 uint8) Float64x4 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) CeilWithPrecision(imm8 uint8) Float64x8 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithCeilSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithCeilWithPrecision(imm8 uint8) Float32x16 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithCeilWithPrecision(imm8 uint8) Float32x4 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithCeilWithPrecision(imm8 uint8) Float32x8 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithCeilWithPrecision(imm8 uint8) Float64x2 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithCeilWithPrecision(imm8 uint8) Float64x4 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithCeilWithPrecision(imm8 uint8) Float64x8 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithFloorSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithFloorWithPrecision(imm8 uint8) Float32x16 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithFloorWithPrecision(imm8 uint8) Float32x4 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithFloorWithPrecision(imm8 uint8) Float32x8 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithFloorWithPrecision(imm8 uint8) Float64x2 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithFloorWithPrecision(imm8 uint8) Float64x4 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithFloorWithPrecision(imm8 uint8) Float64x8 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithRoundSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithRoundWithPrecision(imm8 uint8) Float32x16 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithRoundWithPrecision(imm8 uint8) Float32x4 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithRoundWithPrecision(imm8 uint8) Float32x8 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithRoundWithPrecision(imm8 uint8) Float64x2 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithRoundWithPrecision(imm8 uint8) Float64x4 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithRoundWithPrecision(imm8 uint8) Float64x8 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithTruncSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) DiffWithTruncWithPrecision(imm8 uint8) Float32x16 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) DiffWithTruncWithPrecision(imm8 uint8) Float32x4 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) DiffWithTruncWithPrecision(imm8 uint8) Float32x8 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) DiffWithTruncWithPrecision(imm8 uint8) Float64x2 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) DiffWithTruncWithPrecision(imm8 uint8) Float64x4 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) DiffWithTruncWithPrecision(imm8 uint8) Float64x8 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) FloorSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) FloorSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) FloorSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) FloorSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) FloorSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) FloorSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) FloorWithPrecision(imm8 uint8) Float32x16 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) FloorWithPrecision(imm8 uint8) Float32x4 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) FloorWithPrecision(imm8 uint8) Float32x8 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) FloorWithPrecision(imm8 uint8) Float64x2 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) FloorWithPrecision(imm8 uint8) Float64x4 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) FloorWithPrecision(imm8 uint8) Float64x8 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) RoundSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) RoundWithPrecision(imm8 uint8) Float32x16 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) RoundWithPrecision(imm8 uint8) Float32x4 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) RoundWithPrecision(imm8 uint8) Float32x8 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) RoundWithPrecision(imm8 uint8) Float64x2 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) RoundWithPrecision(imm8 uint8) Float64x4 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) RoundWithPrecision(imm8 uint8) Float64x8 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) TruncSuppressExceptionWithPrecision(imm8 uint8) Float32x16 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) TruncSuppressExceptionWithPrecision(imm8 uint8) Float32x4 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) TruncSuppressExceptionWithPrecision(imm8 uint8) Float32x8 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) TruncSuppressExceptionWithPrecision(imm8 uint8) Float64x2 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) TruncSuppressExceptionWithPrecision(imm8 uint8) Float64x4 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) TruncSuppressExceptionWithPrecision(imm8 uint8) Float64x8 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) TruncWithPrecision(imm8 uint8) Float32x16 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) TruncWithPrecision(imm8 uint8) Float32x4 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) TruncWithPrecision(imm8 uint8) Float32x8 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) TruncWithPrecision(imm8 uint8) Float64x2 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) TruncWithPrecision(imm8 uint8) Float64x4 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) TruncWithPrecision(imm8 uint8) Float64x8 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// CeilSuppressExceptionWithPrecision rounds elements up with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedCeilWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedCeilWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedCeilWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedCeilWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedCeilWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// CeilWithPrecision rounds elements up with specified precision, masked. +// Const Immediate = 2. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedCeilWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithCeilSuppressExceptionWithPrecision computes the difference after ceiling with specified precision, suppressing exceptions. +// Const Immediate = 10. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithCeilSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithCeilWithPrecision computes the difference after ceiling with specified precision. +// Const Immediate = 2. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithCeilWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithFloorSuppressExceptionWithPrecision computes the difference after flooring with specified precision, suppressing exceptions. +// Const Immediate = 9. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithFloorWithPrecision computes the difference after flooring with specified precision. +// Const Immediate = 1. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithFloorWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithRoundSuppressExceptionWithPrecision computes the difference after rounding with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithRoundWithPrecision computes the difference after rounding with specified precision. +// Const Immediate = 0. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithRoundWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithTruncSuppressExceptionWithPrecision computes the difference after truncating with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// DiffWithTruncWithPrecision computes the difference after truncating with specified precision. +// Const Immediate = 3. +// +// Asm: VREDUCEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedDiffWithTruncWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// FloorSuppressExceptionWithPrecision rounds elements down with specified precision, suppressing exceptions, masked. +// Const Immediate = 9. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFloorSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedFloorWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedFloorWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedFloorWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedFloorWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedFloorWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// FloorWithPrecision rounds elements down with specified precision, masked. +// Const Immediate = 1. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedFloorWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// RoundSuppressExceptionWithPrecision rounds elements with specified precision, suppressing exceptions. +// Const Immediate = 8. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedRoundSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedRoundWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedRoundWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedRoundWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedRoundWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedRoundWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// RoundWithPrecision rounds elements with specified precision. +// Const Immediate = 0. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedRoundWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// TruncSuppressExceptionWithPrecision truncates elements with specified precision, suppressing exceptions. +// Const Immediate = 11. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedTruncSuppressExceptionWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x16) MaskedTruncWithPrecision(imm uint8, y Mask32x16) Float32x16 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x4) MaskedTruncWithPrecision(imm uint8, y Mask32x4) Float32x4 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPS, CPU Feature: AVX512EVEX +func (x Float32x8) MaskedTruncWithPrecision(imm uint8, y Mask32x8) Float32x8 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x2) MaskedTruncWithPrecision(imm uint8, y Mask64x2) Float64x2 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x4) MaskedTruncWithPrecision(imm uint8, y Mask64x4) Float64x4 + +// TruncWithPrecision truncates elements with specified precision. +// Const Immediate = 3. +// +// Asm: VRNDSCALEPD, CPU Feature: AVX512EVEX +func (x Float64x8) MaskedTruncWithPrecision(imm uint8, y Mask64x8) Float64x8 + +// Float64x8 converts from Float32x16 to Float64x8 +func (from Float32x16) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Float32x16 to Int16x32 +func (from Float32x16) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Float32x16 to Int32x16 +func (from Float32x16) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Float32x16 to Int64x8 +func (from Float32x16) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Float32x16 to Int8x64 +func (from Float32x16) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Float32x16 to Uint16x32 +func (from Float32x16) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Float32x16 to Uint32x16 +func (from Float32x16) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Float32x16 to Uint64x8 +func (from Float32x16) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Float32x16 to Uint8x64 +func (from Float32x16) AsUint8x64() (to Uint8x64) + +// Float64x2 converts from Float32x4 to Float64x2 +func (from Float32x4) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Float32x4 to Int16x8 +func (from Float32x4) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Float32x4 to Int32x4 +func (from Float32x4) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Float32x4 to Int64x2 +func (from Float32x4) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Float32x4 to Int8x16 +func (from Float32x4) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Float32x4 to Uint16x8 +func (from Float32x4) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Float32x4 to Uint32x4 +func (from Float32x4) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Float32x4 to Uint64x2 +func (from Float32x4) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Float32x4 to Uint8x16 +func (from Float32x4) AsUint8x16() (to Uint8x16) + +// Float64x4 converts from Float32x8 to Float64x4 +func (from Float32x8) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Float32x8 to Int16x16 +func (from Float32x8) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Float32x8 to Int32x8 +func (from Float32x8) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Float32x8 to Int64x4 +func (from Float32x8) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Float32x8 to Int8x32 +func (from Float32x8) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Float32x8 to Uint16x16 +func (from Float32x8) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Float32x8 to Uint32x8 +func (from Float32x8) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Float32x8 to Uint64x4 +func (from Float32x8) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Float32x8 to Uint8x32 +func (from Float32x8) AsUint8x32() (to Uint8x32) + +// Float32x4 converts from Float64x2 to Float32x4 +func (from Float64x2) AsFloat32x4() (to Float32x4) + +// Int16x8 converts from Float64x2 to Int16x8 +func (from Float64x2) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Float64x2 to Int32x4 +func (from Float64x2) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Float64x2 to Int64x2 +func (from Float64x2) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Float64x2 to Int8x16 +func (from Float64x2) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Float64x2 to Uint16x8 +func (from Float64x2) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Float64x2 to Uint32x4 +func (from Float64x2) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Float64x2 to Uint64x2 +func (from Float64x2) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Float64x2 to Uint8x16 +func (from Float64x2) AsUint8x16() (to Uint8x16) + +// Float32x8 converts from Float64x4 to Float32x8 +func (from Float64x4) AsFloat32x8() (to Float32x8) + +// Int16x16 converts from Float64x4 to Int16x16 +func (from Float64x4) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Float64x4 to Int32x8 +func (from Float64x4) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Float64x4 to Int64x4 +func (from Float64x4) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Float64x4 to Int8x32 +func (from Float64x4) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Float64x4 to Uint16x16 +func (from Float64x4) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Float64x4 to Uint32x8 +func (from Float64x4) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Float64x4 to Uint64x4 +func (from Float64x4) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Float64x4 to Uint8x32 +func (from Float64x4) AsUint8x32() (to Uint8x32) + +// Float32x16 converts from Float64x8 to Float32x16 +func (from Float64x8) AsFloat32x16() (to Float32x16) + +// Int16x32 converts from Float64x8 to Int16x32 +func (from Float64x8) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Float64x8 to Int32x16 +func (from Float64x8) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Float64x8 to Int64x8 +func (from Float64x8) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Float64x8 to Int8x64 +func (from Float64x8) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Float64x8 to Uint16x32 +func (from Float64x8) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Float64x8 to Uint32x16 +func (from Float64x8) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Float64x8 to Uint64x8 +func (from Float64x8) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Float64x8 to Uint8x64 +func (from Float64x8) AsUint8x64() (to Uint8x64) + +// Float32x8 converts from Int16x16 to Float32x8 +func (from Int16x16) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Int16x16 to Float64x4 +func (from Int16x16) AsFloat64x4() (to Float64x4) + +// Int32x8 converts from Int16x16 to Int32x8 +func (from Int16x16) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Int16x16 to Int64x4 +func (from Int16x16) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Int16x16 to Int8x32 +func (from Int16x16) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Int16x16 to Uint16x16 +func (from Int16x16) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Int16x16 to Uint32x8 +func (from Int16x16) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Int16x16 to Uint64x4 +func (from Int16x16) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Int16x16 to Uint8x32 +func (from Int16x16) AsUint8x32() (to Uint8x32) + +// Float32x16 converts from Int16x32 to Float32x16 +func (from Int16x32) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Int16x32 to Float64x8 +func (from Int16x32) AsFloat64x8() (to Float64x8) + +// Int32x16 converts from Int16x32 to Int32x16 +func (from Int16x32) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Int16x32 to Int64x8 +func (from Int16x32) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Int16x32 to Int8x64 +func (from Int16x32) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Int16x32 to Uint16x32 +func (from Int16x32) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Int16x32 to Uint32x16 +func (from Int16x32) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Int16x32 to Uint64x8 +func (from Int16x32) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Int16x32 to Uint8x64 +func (from Int16x32) AsUint8x64() (to Uint8x64) + +// Float32x4 converts from Int16x8 to Float32x4 +func (from Int16x8) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Int16x8 to Float64x2 +func (from Int16x8) AsFloat64x2() (to Float64x2) + +// Int32x4 converts from Int16x8 to Int32x4 +func (from Int16x8) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Int16x8 to Int64x2 +func (from Int16x8) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Int16x8 to Int8x16 +func (from Int16x8) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Int16x8 to Uint16x8 +func (from Int16x8) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Int16x8 to Uint32x4 +func (from Int16x8) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Int16x8 to Uint64x2 +func (from Int16x8) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Int16x8 to Uint8x16 +func (from Int16x8) AsUint8x16() (to Uint8x16) + +// Float32x16 converts from Int32x16 to Float32x16 +func (from Int32x16) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Int32x16 to Float64x8 +func (from Int32x16) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Int32x16 to Int16x32 +func (from Int32x16) AsInt16x32() (to Int16x32) + +// Int64x8 converts from Int32x16 to Int64x8 +func (from Int32x16) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Int32x16 to Int8x64 +func (from Int32x16) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Int32x16 to Uint16x32 +func (from Int32x16) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Int32x16 to Uint32x16 +func (from Int32x16) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Int32x16 to Uint64x8 +func (from Int32x16) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Int32x16 to Uint8x64 +func (from Int32x16) AsUint8x64() (to Uint8x64) + +// Float32x4 converts from Int32x4 to Float32x4 +func (from Int32x4) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Int32x4 to Float64x2 +func (from Int32x4) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Int32x4 to Int16x8 +func (from Int32x4) AsInt16x8() (to Int16x8) + +// Int64x2 converts from Int32x4 to Int64x2 +func (from Int32x4) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Int32x4 to Int8x16 +func (from Int32x4) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Int32x4 to Uint16x8 +func (from Int32x4) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Int32x4 to Uint32x4 +func (from Int32x4) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Int32x4 to Uint64x2 +func (from Int32x4) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Int32x4 to Uint8x16 +func (from Int32x4) AsUint8x16() (to Uint8x16) + +// Float32x8 converts from Int32x8 to Float32x8 +func (from Int32x8) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Int32x8 to Float64x4 +func (from Int32x8) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Int32x8 to Int16x16 +func (from Int32x8) AsInt16x16() (to Int16x16) + +// Int64x4 converts from Int32x8 to Int64x4 +func (from Int32x8) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Int32x8 to Int8x32 +func (from Int32x8) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Int32x8 to Uint16x16 +func (from Int32x8) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Int32x8 to Uint32x8 +func (from Int32x8) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Int32x8 to Uint64x4 +func (from Int32x8) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Int32x8 to Uint8x32 +func (from Int32x8) AsUint8x32() (to Uint8x32) + +// Float32x4 converts from Int64x2 to Float32x4 +func (from Int64x2) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Int64x2 to Float64x2 +func (from Int64x2) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Int64x2 to Int16x8 +func (from Int64x2) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Int64x2 to Int32x4 +func (from Int64x2) AsInt32x4() (to Int32x4) + +// Int8x16 converts from Int64x2 to Int8x16 +func (from Int64x2) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Int64x2 to Uint16x8 +func (from Int64x2) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Int64x2 to Uint32x4 +func (from Int64x2) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Int64x2 to Uint64x2 +func (from Int64x2) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Int64x2 to Uint8x16 +func (from Int64x2) AsUint8x16() (to Uint8x16) + +// Float32x8 converts from Int64x4 to Float32x8 +func (from Int64x4) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Int64x4 to Float64x4 +func (from Int64x4) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Int64x4 to Int16x16 +func (from Int64x4) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Int64x4 to Int32x8 +func (from Int64x4) AsInt32x8() (to Int32x8) + +// Int8x32 converts from Int64x4 to Int8x32 +func (from Int64x4) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Int64x4 to Uint16x16 +func (from Int64x4) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Int64x4 to Uint32x8 +func (from Int64x4) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Int64x4 to Uint64x4 +func (from Int64x4) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Int64x4 to Uint8x32 +func (from Int64x4) AsUint8x32() (to Uint8x32) + +// Float32x16 converts from Int64x8 to Float32x16 +func (from Int64x8) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Int64x8 to Float64x8 +func (from Int64x8) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Int64x8 to Int16x32 +func (from Int64x8) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Int64x8 to Int32x16 +func (from Int64x8) AsInt32x16() (to Int32x16) + +// Int8x64 converts from Int64x8 to Int8x64 +func (from Int64x8) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Int64x8 to Uint16x32 +func (from Int64x8) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Int64x8 to Uint32x16 +func (from Int64x8) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Int64x8 to Uint64x8 +func (from Int64x8) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Int64x8 to Uint8x64 +func (from Int64x8) AsUint8x64() (to Uint8x64) + +// Float32x4 converts from Int8x16 to Float32x4 +func (from Int8x16) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Int8x16 to Float64x2 +func (from Int8x16) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Int8x16 to Int16x8 +func (from Int8x16) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Int8x16 to Int32x4 +func (from Int8x16) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Int8x16 to Int64x2 +func (from Int8x16) AsInt64x2() (to Int64x2) + +// Uint16x8 converts from Int8x16 to Uint16x8 +func (from Int8x16) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Int8x16 to Uint32x4 +func (from Int8x16) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Int8x16 to Uint64x2 +func (from Int8x16) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Int8x16 to Uint8x16 +func (from Int8x16) AsUint8x16() (to Uint8x16) + +// Float32x8 converts from Int8x32 to Float32x8 +func (from Int8x32) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Int8x32 to Float64x4 +func (from Int8x32) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Int8x32 to Int16x16 +func (from Int8x32) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Int8x32 to Int32x8 +func (from Int8x32) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Int8x32 to Int64x4 +func (from Int8x32) AsInt64x4() (to Int64x4) + +// Uint16x16 converts from Int8x32 to Uint16x16 +func (from Int8x32) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Int8x32 to Uint32x8 +func (from Int8x32) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Int8x32 to Uint64x4 +func (from Int8x32) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Int8x32 to Uint8x32 +func (from Int8x32) AsUint8x32() (to Uint8x32) + +// Float32x16 converts from Int8x64 to Float32x16 +func (from Int8x64) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Int8x64 to Float64x8 +func (from Int8x64) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Int8x64 to Int16x32 +func (from Int8x64) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Int8x64 to Int32x16 +func (from Int8x64) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Int8x64 to Int64x8 +func (from Int8x64) AsInt64x8() (to Int64x8) + +// Uint16x32 converts from Int8x64 to Uint16x32 +func (from Int8x64) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Int8x64 to Uint32x16 +func (from Int8x64) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Int8x64 to Uint64x8 +func (from Int8x64) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Int8x64 to Uint8x64 +func (from Int8x64) AsUint8x64() (to Uint8x64) + +// Float32x8 converts from Uint16x16 to Float32x8 +func (from Uint16x16) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Uint16x16 to Float64x4 +func (from Uint16x16) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Uint16x16 to Int16x16 +func (from Uint16x16) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Uint16x16 to Int32x8 +func (from Uint16x16) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Uint16x16 to Int64x4 +func (from Uint16x16) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Uint16x16 to Int8x32 +func (from Uint16x16) AsInt8x32() (to Int8x32) + +// Uint32x8 converts from Uint16x16 to Uint32x8 +func (from Uint16x16) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Uint16x16 to Uint64x4 +func (from Uint16x16) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Uint16x16 to Uint8x32 +func (from Uint16x16) AsUint8x32() (to Uint8x32) + +// Float32x16 converts from Uint16x32 to Float32x16 +func (from Uint16x32) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Uint16x32 to Float64x8 +func (from Uint16x32) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Uint16x32 to Int16x32 +func (from Uint16x32) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Uint16x32 to Int32x16 +func (from Uint16x32) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Uint16x32 to Int64x8 +func (from Uint16x32) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Uint16x32 to Int8x64 +func (from Uint16x32) AsInt8x64() (to Int8x64) + +// Uint32x16 converts from Uint16x32 to Uint32x16 +func (from Uint16x32) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Uint16x32 to Uint64x8 +func (from Uint16x32) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Uint16x32 to Uint8x64 +func (from Uint16x32) AsUint8x64() (to Uint8x64) + +// Float32x4 converts from Uint16x8 to Float32x4 +func (from Uint16x8) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Uint16x8 to Float64x2 +func (from Uint16x8) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Uint16x8 to Int16x8 +func (from Uint16x8) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Uint16x8 to Int32x4 +func (from Uint16x8) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Uint16x8 to Int64x2 +func (from Uint16x8) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Uint16x8 to Int8x16 +func (from Uint16x8) AsInt8x16() (to Int8x16) + +// Uint32x4 converts from Uint16x8 to Uint32x4 +func (from Uint16x8) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Uint16x8 to Uint64x2 +func (from Uint16x8) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Uint16x8 to Uint8x16 +func (from Uint16x8) AsUint8x16() (to Uint8x16) + +// Float32x16 converts from Uint32x16 to Float32x16 +func (from Uint32x16) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Uint32x16 to Float64x8 +func (from Uint32x16) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Uint32x16 to Int16x32 +func (from Uint32x16) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Uint32x16 to Int32x16 +func (from Uint32x16) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Uint32x16 to Int64x8 +func (from Uint32x16) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Uint32x16 to Int8x64 +func (from Uint32x16) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Uint32x16 to Uint16x32 +func (from Uint32x16) AsUint16x32() (to Uint16x32) + +// Uint64x8 converts from Uint32x16 to Uint64x8 +func (from Uint32x16) AsUint64x8() (to Uint64x8) + +// Uint8x64 converts from Uint32x16 to Uint8x64 +func (from Uint32x16) AsUint8x64() (to Uint8x64) + +// Float32x4 converts from Uint32x4 to Float32x4 +func (from Uint32x4) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Uint32x4 to Float64x2 +func (from Uint32x4) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Uint32x4 to Int16x8 +func (from Uint32x4) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Uint32x4 to Int32x4 +func (from Uint32x4) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Uint32x4 to Int64x2 +func (from Uint32x4) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Uint32x4 to Int8x16 +func (from Uint32x4) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Uint32x4 to Uint16x8 +func (from Uint32x4) AsUint16x8() (to Uint16x8) + +// Uint64x2 converts from Uint32x4 to Uint64x2 +func (from Uint32x4) AsUint64x2() (to Uint64x2) + +// Uint8x16 converts from Uint32x4 to Uint8x16 +func (from Uint32x4) AsUint8x16() (to Uint8x16) + +// Float32x8 converts from Uint32x8 to Float32x8 +func (from Uint32x8) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Uint32x8 to Float64x4 +func (from Uint32x8) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Uint32x8 to Int16x16 +func (from Uint32x8) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Uint32x8 to Int32x8 +func (from Uint32x8) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Uint32x8 to Int64x4 +func (from Uint32x8) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Uint32x8 to Int8x32 +func (from Uint32x8) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Uint32x8 to Uint16x16 +func (from Uint32x8) AsUint16x16() (to Uint16x16) + +// Uint64x4 converts from Uint32x8 to Uint64x4 +func (from Uint32x8) AsUint64x4() (to Uint64x4) + +// Uint8x32 converts from Uint32x8 to Uint8x32 +func (from Uint32x8) AsUint8x32() (to Uint8x32) + +// Float32x4 converts from Uint64x2 to Float32x4 +func (from Uint64x2) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Uint64x2 to Float64x2 +func (from Uint64x2) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Uint64x2 to Int16x8 +func (from Uint64x2) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Uint64x2 to Int32x4 +func (from Uint64x2) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Uint64x2 to Int64x2 +func (from Uint64x2) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Uint64x2 to Int8x16 +func (from Uint64x2) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Uint64x2 to Uint16x8 +func (from Uint64x2) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Uint64x2 to Uint32x4 +func (from Uint64x2) AsUint32x4() (to Uint32x4) + +// Uint8x16 converts from Uint64x2 to Uint8x16 +func (from Uint64x2) AsUint8x16() (to Uint8x16) + +// Float32x8 converts from Uint64x4 to Float32x8 +func (from Uint64x4) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Uint64x4 to Float64x4 +func (from Uint64x4) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Uint64x4 to Int16x16 +func (from Uint64x4) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Uint64x4 to Int32x8 +func (from Uint64x4) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Uint64x4 to Int64x4 +func (from Uint64x4) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Uint64x4 to Int8x32 +func (from Uint64x4) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Uint64x4 to Uint16x16 +func (from Uint64x4) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Uint64x4 to Uint32x8 +func (from Uint64x4) AsUint32x8() (to Uint32x8) + +// Uint8x32 converts from Uint64x4 to Uint8x32 +func (from Uint64x4) AsUint8x32() (to Uint8x32) + +// Float32x16 converts from Uint64x8 to Float32x16 +func (from Uint64x8) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Uint64x8 to Float64x8 +func (from Uint64x8) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Uint64x8 to Int16x32 +func (from Uint64x8) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Uint64x8 to Int32x16 +func (from Uint64x8) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Uint64x8 to Int64x8 +func (from Uint64x8) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Uint64x8 to Int8x64 +func (from Uint64x8) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Uint64x8 to Uint16x32 +func (from Uint64x8) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Uint64x8 to Uint32x16 +func (from Uint64x8) AsUint32x16() (to Uint32x16) + +// Uint8x64 converts from Uint64x8 to Uint8x64 +func (from Uint64x8) AsUint8x64() (to Uint8x64) + +// Float32x4 converts from Uint8x16 to Float32x4 +func (from Uint8x16) AsFloat32x4() (to Float32x4) + +// Float64x2 converts from Uint8x16 to Float64x2 +func (from Uint8x16) AsFloat64x2() (to Float64x2) + +// Int16x8 converts from Uint8x16 to Int16x8 +func (from Uint8x16) AsInt16x8() (to Int16x8) + +// Int32x4 converts from Uint8x16 to Int32x4 +func (from Uint8x16) AsInt32x4() (to Int32x4) + +// Int64x2 converts from Uint8x16 to Int64x2 +func (from Uint8x16) AsInt64x2() (to Int64x2) + +// Int8x16 converts from Uint8x16 to Int8x16 +func (from Uint8x16) AsInt8x16() (to Int8x16) + +// Uint16x8 converts from Uint8x16 to Uint16x8 +func (from Uint8x16) AsUint16x8() (to Uint16x8) + +// Uint32x4 converts from Uint8x16 to Uint32x4 +func (from Uint8x16) AsUint32x4() (to Uint32x4) + +// Uint64x2 converts from Uint8x16 to Uint64x2 +func (from Uint8x16) AsUint64x2() (to Uint64x2) + +// Float32x8 converts from Uint8x32 to Float32x8 +func (from Uint8x32) AsFloat32x8() (to Float32x8) + +// Float64x4 converts from Uint8x32 to Float64x4 +func (from Uint8x32) AsFloat64x4() (to Float64x4) + +// Int16x16 converts from Uint8x32 to Int16x16 +func (from Uint8x32) AsInt16x16() (to Int16x16) + +// Int32x8 converts from Uint8x32 to Int32x8 +func (from Uint8x32) AsInt32x8() (to Int32x8) + +// Int64x4 converts from Uint8x32 to Int64x4 +func (from Uint8x32) AsInt64x4() (to Int64x4) + +// Int8x32 converts from Uint8x32 to Int8x32 +func (from Uint8x32) AsInt8x32() (to Int8x32) + +// Uint16x16 converts from Uint8x32 to Uint16x16 +func (from Uint8x32) AsUint16x16() (to Uint16x16) + +// Uint32x8 converts from Uint8x32 to Uint32x8 +func (from Uint8x32) AsUint32x8() (to Uint32x8) + +// Uint64x4 converts from Uint8x32 to Uint64x4 +func (from Uint8x32) AsUint64x4() (to Uint64x4) + +// Float32x16 converts from Uint8x64 to Float32x16 +func (from Uint8x64) AsFloat32x16() (to Float32x16) + +// Float64x8 converts from Uint8x64 to Float64x8 +func (from Uint8x64) AsFloat64x8() (to Float64x8) + +// Int16x32 converts from Uint8x64 to Int16x32 +func (from Uint8x64) AsInt16x32() (to Int16x32) + +// Int32x16 converts from Uint8x64 to Int32x16 +func (from Uint8x64) AsInt32x16() (to Int32x16) + +// Int64x8 converts from Uint8x64 to Int64x8 +func (from Uint8x64) AsInt64x8() (to Int64x8) + +// Int8x64 converts from Uint8x64 to Int8x64 +func (from Uint8x64) AsInt8x64() (to Int8x64) + +// Uint16x32 converts from Uint8x64 to Uint16x32 +func (from Uint8x64) AsUint16x32() (to Uint16x32) + +// Uint32x16 converts from Uint8x64 to Uint32x16 +func (from Uint8x64) AsUint32x16() (to Uint32x16) + +// Uint64x8 converts from Uint8x64 to Uint64x8 +func (from Uint8x64) AsUint64x8() (to Uint64x8) + +// converts from Mask16x16 to Int16x16 +func (from Mask16x16) AsInt16x16() (to Int16x16) + +// converts from Int16x16 to Mask16x16 +func (from Int16x16) AsMask16x16() (to Mask16x16) + +func (x Mask16x16) And(y Mask16x16) Mask16x16 + +func (x Mask16x16) Or(y Mask16x16) Mask16x16 + +// converts from Mask16x32 to Int16x32 +func (from Mask16x32) AsInt16x32() (to Int16x32) + +// converts from Int16x32 to Mask16x32 +func (from Int16x32) AsMask16x32() (to Mask16x32) + +func (x Mask16x32) And(y Mask16x32) Mask16x32 + +func (x Mask16x32) Or(y Mask16x32) Mask16x32 + +// converts from Mask16x8 to Int16x8 +func (from Mask16x8) AsInt16x8() (to Int16x8) + +// converts from Int16x8 to Mask16x8 +func (from Int16x8) AsMask16x8() (to Mask16x8) + +func (x Mask16x8) And(y Mask16x8) Mask16x8 + +func (x Mask16x8) Or(y Mask16x8) Mask16x8 + +// converts from Mask32x16 to Int32x16 +func (from Mask32x16) AsInt32x16() (to Int32x16) + +// converts from Int32x16 to Mask32x16 +func (from Int32x16) AsMask32x16() (to Mask32x16) + +func (x Mask32x16) And(y Mask32x16) Mask32x16 + +func (x Mask32x16) Or(y Mask32x16) Mask32x16 + +// converts from Mask32x4 to Int32x4 +func (from Mask32x4) AsInt32x4() (to Int32x4) + +// converts from Int32x4 to Mask32x4 +func (from Int32x4) AsMask32x4() (to Mask32x4) + +func (x Mask32x4) And(y Mask32x4) Mask32x4 + +func (x Mask32x4) Or(y Mask32x4) Mask32x4 + +// converts from Mask32x8 to Int32x8 +func (from Mask32x8) AsInt32x8() (to Int32x8) + +// converts from Int32x8 to Mask32x8 +func (from Int32x8) AsMask32x8() (to Mask32x8) + +func (x Mask32x8) And(y Mask32x8) Mask32x8 + +func (x Mask32x8) Or(y Mask32x8) Mask32x8 + +// converts from Mask64x2 to Int64x2 +func (from Mask64x2) AsInt64x2() (to Int64x2) + +// converts from Int64x2 to Mask64x2 +func (from Int64x2) AsMask64x2() (to Mask64x2) + +func (x Mask64x2) And(y Mask64x2) Mask64x2 + +func (x Mask64x2) Or(y Mask64x2) Mask64x2 + +// converts from Mask64x4 to Int64x4 +func (from Mask64x4) AsInt64x4() (to Int64x4) + +// converts from Int64x4 to Mask64x4 +func (from Int64x4) AsMask64x4() (to Mask64x4) + +func (x Mask64x4) And(y Mask64x4) Mask64x4 + +func (x Mask64x4) Or(y Mask64x4) Mask64x4 + +// converts from Mask64x8 to Int64x8 +func (from Mask64x8) AsInt64x8() (to Int64x8) + +// converts from Int64x8 to Mask64x8 +func (from Int64x8) AsMask64x8() (to Mask64x8) + +func (x Mask64x8) And(y Mask64x8) Mask64x8 + +func (x Mask64x8) Or(y Mask64x8) Mask64x8 + +// converts from Mask8x16 to Int8x16 +func (from Mask8x16) AsInt8x16() (to Int8x16) + +// converts from Int8x16 to Mask8x16 +func (from Int8x16) AsMask8x16() (to Mask8x16) + +func (x Mask8x16) And(y Mask8x16) Mask8x16 + +func (x Mask8x16) Or(y Mask8x16) Mask8x16 + +// converts from Mask8x32 to Int8x32 +func (from Mask8x32) AsInt8x32() (to Int8x32) + +// converts from Int8x32 to Mask8x32 +func (from Int8x32) AsMask8x32() (to Mask8x32) + +func (x Mask8x32) And(y Mask8x32) Mask8x32 + +func (x Mask8x32) Or(y Mask8x32) Mask8x32 + +// converts from Mask8x64 to Int8x64 +func (from Mask8x64) AsInt8x64() (to Int8x64) + +// converts from Int8x64 to Mask8x64 +func (from Int8x64) AsMask8x64() (to Mask8x64) + +func (x Mask8x64) And(y Mask8x64) Mask8x64 + +func (x Mask8x64) Or(y Mask8x64) Mask8x64 diff --git a/src/simd/testdata/sample.go b/src/simd/testdata/sample.go new file mode 100644 index 00000000000000..b8e3697b6bf644 --- /dev/null +++ b/src/simd/testdata/sample.go @@ -0,0 +1,154 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package main + +import ( + "fmt" + "os" + "simd" + "unsafe" +) + +func load(s []float64) simd.Float64x4 { + return simd.LoadFloat64x4((*[4]float64)(s[:4])) +} + +type S1 = simd.Float64x4 + +type S2 simd.Float64x4 + +func (s S2) Len() int { + return simd.Float64x4(s).Len() +} + +func (s S2) Load(a []float64) S2 { + return S2(load(a)) +} + +func (s S2) Store(a *[4]float64) { + simd.Float64x4(s).Store(a) +} + +func (s S2) Add(a S2) S2 { + return S2(simd.Float64x4(s).Add(simd.Float64x4(a))) +} + +func (s S2) Mul(a S2) S2 { + return S2(simd.Float64x4(s).Mul(simd.Float64x4(a))) +} + +type S3 struct { + simd.Float64x4 +} + +func ip64_0(a, b []float64) float64 { + s := 0.0 + for i := range a { + s += a[i] * b[i] + } + return s +} + +func ip64_1(a, b []float64) float64 { + var z S1 + sum := z + var i int + stride := z.Len() + for ; i <= len(a)-stride; i += stride { + va := load(a[i:]) + vb := load(b[i:]) + sum = sum.Add(va.Mul(vb)) + } + var tmp [4]float64 + sum.Store(&tmp) + return tmp[0] + tmp[1] + tmp[2] + tmp[3] +} + +func ip64_1a(a, b []float64) float64 { + var z S1 + sum := z + var i int + stride := z.Len() + for ; i <= len(a)-stride; i += stride { + va := load(a[i:]) + vb := load(b[i:]) + sum = FMA(sum, va, vb) + } + var tmp [4]float64 + sum.Store(&tmp) + return tmp[0] + tmp[1] + tmp[2] + tmp[3] +} + +//go:noinline +func FMA(a, b, c simd.Float64x4) simd.Float64x4 { + return a.Add(b.Mul(c)) +} + +func ip64_2(a, b []float64) float64 { + var z S2 + sum := z + var i int + stride := z.Len() + for ; i <= len(a)-stride; i += stride { + va := z.Load(a[i:]) + vb := z.Load(b[i:]) + sum = sum.Add(va.Mul(vb)) + } + var tmp [4]float64 + sum.Store(&tmp) + return tmp[0] + tmp[1] + tmp[2] + tmp[3] +} + +func ip64_3(a, b []float64) float64 { + var z S3 + sum := z + var i int + stride := z.Len() + for ; i <= len(a)-stride; i += stride { + va := load(a[i:]) + vb := load(b[i:]) + sum = S3{sum.Add(va.Mul(vb))} + } + var tmp [4]float64 + sum.Store(&tmp) + return tmp[0] + tmp[1] + tmp[2] + tmp[3] +} + +func main() { + a := []float64{1, 2, 3, 4, 5, 6, 7, 8} + ip0 := ip64_0(a, a) + ip1 := ip64_1(a, a) + ip1a := ip64_1a(a, a) + ip2 := ip64_2(a, a) + ip3 := ip64_3(a, a) + fmt.Printf("Test IP = %f\n", ip0) + fmt.Printf("SIMD IP 1 = %f\n", ip1) + fmt.Printf("SIMD IP 1a = %f\n", ip1a) + fmt.Printf("SIMD IP 2 = %f\n", ip2) + fmt.Printf("SIMD IP 3 = %f\n", ip3) + var z1 S1 + var z2 S2 + var z3 S2 + + s1, s2, s3 := unsafe.Sizeof(z1), unsafe.Sizeof(z2), unsafe.Sizeof(z3) + + fmt.Printf("unsafe.Sizeof(z1, z2, z3)=%d, %d, %d\n", s1, s2, s3) + + fail := false + + if s1 != 32 || s2 != 32 || s3 != 32 { + fmt.Println("Failed a sizeof check, should all be 32") + fail = true + } + + if ip1 != ip0 || ip1a != ip0 || ip2 != ip0 || ip3 != ip0 { + fmt.Println("Failed an inner product check, should all be", ip0) + fail = true + } + + if fail { + os.Exit(1) + } +} diff --git a/src/simd/types_amd64.go b/src/simd/types_amd64.go new file mode 100644 index 00000000000000..ab0f15a89e2a31 --- /dev/null +++ b/src/simd/types_amd64.go @@ -0,0 +1,662 @@ +// Code generated by x/arch/internal/simdgen using 'go run . -xedPath $XED_PATH -o godefs -goroot $GOROOT go.yaml types.yaml categories.yaml'; DO NOT EDIT. + +//go:build goexperiment.simd + +package simd + +// v128 is a tag type that tells the compiler that this is really 128-bit SIMD +type v128 struct { + _128 struct{} +} + +// Int16x8 is a 128-bit SIMD vector of 8 int16 +type Int16x8 struct { + int16x8 v128 + vals [8]int16 +} + +// Len returns the number of elements in a Int16x8 +func (x Int16x8) Len() int { return 8 } + +// LoadInt16x8 loads a Int16x8 from an array +// +//go:noescape +func LoadInt16x8(y *[8]int16) Int16x8 + +// Store stores a Int16x8 to an array +// +//go:noescape +func (x Int16x8) Store(y *[8]int16) + +// Int32x4 is a 128-bit SIMD vector of 4 int32 +type Int32x4 struct { + int32x4 v128 + vals [4]int32 +} + +// Len returns the number of elements in a Int32x4 +func (x Int32x4) Len() int { return 4 } + +// LoadInt32x4 loads a Int32x4 from an array +// +//go:noescape +func LoadInt32x4(y *[4]int32) Int32x4 + +// Store stores a Int32x4 to an array +// +//go:noescape +func (x Int32x4) Store(y *[4]int32) + +// Int8x16 is a 128-bit SIMD vector of 16 int8 +type Int8x16 struct { + int8x16 v128 + vals [16]int8 +} + +// Len returns the number of elements in a Int8x16 +func (x Int8x16) Len() int { return 16 } + +// LoadInt8x16 loads a Int8x16 from an array +// +//go:noescape +func LoadInt8x16(y *[16]int8) Int8x16 + +// Store stores a Int8x16 to an array +// +//go:noescape +func (x Int8x16) Store(y *[16]int8) + +// Int64x2 is a 128-bit SIMD vector of 2 int64 +type Int64x2 struct { + int64x2 v128 + vals [2]int64 +} + +// Len returns the number of elements in a Int64x2 +func (x Int64x2) Len() int { return 2 } + +// LoadInt64x2 loads a Int64x2 from an array +// +//go:noescape +func LoadInt64x2(y *[2]int64) Int64x2 + +// Store stores a Int64x2 to an array +// +//go:noescape +func (x Int64x2) Store(y *[2]int64) + +// Mask64x2 is a 128-bit SIMD vector of 2 int64 +type Mask64x2 struct { + int64x2 v128 + vals [2]int64 +} + +// Float32x4 is a 128-bit SIMD vector of 4 float32 +type Float32x4 struct { + float32x4 v128 + vals [4]float32 +} + +// Len returns the number of elements in a Float32x4 +func (x Float32x4) Len() int { return 4 } + +// LoadFloat32x4 loads a Float32x4 from an array +// +//go:noescape +func LoadFloat32x4(y *[4]float32) Float32x4 + +// Store stores a Float32x4 to an array +// +//go:noescape +func (x Float32x4) Store(y *[4]float32) + +// Float64x2 is a 128-bit SIMD vector of 2 float64 +type Float64x2 struct { + float64x2 v128 + vals [2]float64 +} + +// Len returns the number of elements in a Float64x2 +func (x Float64x2) Len() int { return 2 } + +// LoadFloat64x2 loads a Float64x2 from an array +// +//go:noescape +func LoadFloat64x2(y *[2]float64) Float64x2 + +// Store stores a Float64x2 to an array +// +//go:noescape +func (x Float64x2) Store(y *[2]float64) + +// Uint16x8 is a 128-bit SIMD vector of 8 uint16 +type Uint16x8 struct { + uint16x8 v128 + vals [8]uint16 +} + +// Len returns the number of elements in a Uint16x8 +func (x Uint16x8) Len() int { return 8 } + +// LoadUint16x8 loads a Uint16x8 from an array +// +//go:noescape +func LoadUint16x8(y *[8]uint16) Uint16x8 + +// Store stores a Uint16x8 to an array +// +//go:noescape +func (x Uint16x8) Store(y *[8]uint16) + +// Uint32x4 is a 128-bit SIMD vector of 4 uint32 +type Uint32x4 struct { + uint32x4 v128 + vals [4]uint32 +} + +// Len returns the number of elements in a Uint32x4 +func (x Uint32x4) Len() int { return 4 } + +// LoadUint32x4 loads a Uint32x4 from an array +// +//go:noescape +func LoadUint32x4(y *[4]uint32) Uint32x4 + +// Store stores a Uint32x4 to an array +// +//go:noescape +func (x Uint32x4) Store(y *[4]uint32) + +// Uint64x2 is a 128-bit SIMD vector of 2 uint64 +type Uint64x2 struct { + uint64x2 v128 + vals [2]uint64 +} + +// Len returns the number of elements in a Uint64x2 +func (x Uint64x2) Len() int { return 2 } + +// LoadUint64x2 loads a Uint64x2 from an array +// +//go:noescape +func LoadUint64x2(y *[2]uint64) Uint64x2 + +// Store stores a Uint64x2 to an array +// +//go:noescape +func (x Uint64x2) Store(y *[2]uint64) + +// Uint8x16 is a 128-bit SIMD vector of 16 uint8 +type Uint8x16 struct { + uint8x16 v128 + vals [16]uint8 +} + +// Len returns the number of elements in a Uint8x16 +func (x Uint8x16) Len() int { return 16 } + +// LoadUint8x16 loads a Uint8x16 from an array +// +//go:noescape +func LoadUint8x16(y *[16]uint8) Uint8x16 + +// Store stores a Uint8x16 to an array +// +//go:noescape +func (x Uint8x16) Store(y *[16]uint8) + +// Mask32x4 is a 128-bit SIMD vector of 4 int32 +type Mask32x4 struct { + int32x4 v128 + vals [4]int32 +} + +// Mask16x8 is a 128-bit SIMD vector of 8 int16 +type Mask16x8 struct { + int16x8 v128 + vals [8]int16 +} + +// Mask8x16 is a 128-bit SIMD vector of 16 int8 +type Mask8x16 struct { + int8x16 v128 + vals [16]int8 +} + +// v256 is a tag type that tells the compiler that this is really 256-bit SIMD +type v256 struct { + _256 struct{} +} + +// Int16x16 is a 256-bit SIMD vector of 16 int16 +type Int16x16 struct { + int16x16 v256 + vals [16]int16 +} + +// Len returns the number of elements in a Int16x16 +func (x Int16x16) Len() int { return 16 } + +// LoadInt16x16 loads a Int16x16 from an array +// +//go:noescape +func LoadInt16x16(y *[16]int16) Int16x16 + +// Store stores a Int16x16 to an array +// +//go:noescape +func (x Int16x16) Store(y *[16]int16) + +// Int32x8 is a 256-bit SIMD vector of 8 int32 +type Int32x8 struct { + int32x8 v256 + vals [8]int32 +} + +// Len returns the number of elements in a Int32x8 +func (x Int32x8) Len() int { return 8 } + +// LoadInt32x8 loads a Int32x8 from an array +// +//go:noescape +func LoadInt32x8(y *[8]int32) Int32x8 + +// Store stores a Int32x8 to an array +// +//go:noescape +func (x Int32x8) Store(y *[8]int32) + +// Int8x32 is a 256-bit SIMD vector of 32 int8 +type Int8x32 struct { + int8x32 v256 + vals [32]int8 +} + +// Len returns the number of elements in a Int8x32 +func (x Int8x32) Len() int { return 32 } + +// LoadInt8x32 loads a Int8x32 from an array +// +//go:noescape +func LoadInt8x32(y *[32]int8) Int8x32 + +// Store stores a Int8x32 to an array +// +//go:noescape +func (x Int8x32) Store(y *[32]int8) + +// Int64x4 is a 256-bit SIMD vector of 4 int64 +type Int64x4 struct { + int64x4 v256 + vals [4]int64 +} + +// Len returns the number of elements in a Int64x4 +func (x Int64x4) Len() int { return 4 } + +// LoadInt64x4 loads a Int64x4 from an array +// +//go:noescape +func LoadInt64x4(y *[4]int64) Int64x4 + +// Store stores a Int64x4 to an array +// +//go:noescape +func (x Int64x4) Store(y *[4]int64) + +// Mask64x4 is a 256-bit SIMD vector of 4 int64 +type Mask64x4 struct { + int64x4 v256 + vals [4]int64 +} + +// Float32x8 is a 256-bit SIMD vector of 8 float32 +type Float32x8 struct { + float32x8 v256 + vals [8]float32 +} + +// Len returns the number of elements in a Float32x8 +func (x Float32x8) Len() int { return 8 } + +// LoadFloat32x8 loads a Float32x8 from an array +// +//go:noescape +func LoadFloat32x8(y *[8]float32) Float32x8 + +// Store stores a Float32x8 to an array +// +//go:noescape +func (x Float32x8) Store(y *[8]float32) + +// Float64x4 is a 256-bit SIMD vector of 4 float64 +type Float64x4 struct { + float64x4 v256 + vals [4]float64 +} + +// Len returns the number of elements in a Float64x4 +func (x Float64x4) Len() int { return 4 } + +// LoadFloat64x4 loads a Float64x4 from an array +// +//go:noescape +func LoadFloat64x4(y *[4]float64) Float64x4 + +// Store stores a Float64x4 to an array +// +//go:noescape +func (x Float64x4) Store(y *[4]float64) + +// Uint16x16 is a 256-bit SIMD vector of 16 uint16 +type Uint16x16 struct { + uint16x16 v256 + vals [16]uint16 +} + +// Len returns the number of elements in a Uint16x16 +func (x Uint16x16) Len() int { return 16 } + +// LoadUint16x16 loads a Uint16x16 from an array +// +//go:noescape +func LoadUint16x16(y *[16]uint16) Uint16x16 + +// Store stores a Uint16x16 to an array +// +//go:noescape +func (x Uint16x16) Store(y *[16]uint16) + +// Uint32x8 is a 256-bit SIMD vector of 8 uint32 +type Uint32x8 struct { + uint32x8 v256 + vals [8]uint32 +} + +// Len returns the number of elements in a Uint32x8 +func (x Uint32x8) Len() int { return 8 } + +// LoadUint32x8 loads a Uint32x8 from an array +// +//go:noescape +func LoadUint32x8(y *[8]uint32) Uint32x8 + +// Store stores a Uint32x8 to an array +// +//go:noescape +func (x Uint32x8) Store(y *[8]uint32) + +// Uint64x4 is a 256-bit SIMD vector of 4 uint64 +type Uint64x4 struct { + uint64x4 v256 + vals [4]uint64 +} + +// Len returns the number of elements in a Uint64x4 +func (x Uint64x4) Len() int { return 4 } + +// LoadUint64x4 loads a Uint64x4 from an array +// +//go:noescape +func LoadUint64x4(y *[4]uint64) Uint64x4 + +// Store stores a Uint64x4 to an array +// +//go:noescape +func (x Uint64x4) Store(y *[4]uint64) + +// Uint8x32 is a 256-bit SIMD vector of 32 uint8 +type Uint8x32 struct { + uint8x32 v256 + vals [32]uint8 +} + +// Len returns the number of elements in a Uint8x32 +func (x Uint8x32) Len() int { return 32 } + +// LoadUint8x32 loads a Uint8x32 from an array +// +//go:noescape +func LoadUint8x32(y *[32]uint8) Uint8x32 + +// Store stores a Uint8x32 to an array +// +//go:noescape +func (x Uint8x32) Store(y *[32]uint8) + +// Mask32x8 is a 256-bit SIMD vector of 8 int32 +type Mask32x8 struct { + int32x8 v256 + vals [8]int32 +} + +// Mask16x16 is a 256-bit SIMD vector of 16 int16 +type Mask16x16 struct { + int16x16 v256 + vals [16]int16 +} + +// Mask8x32 is a 256-bit SIMD vector of 32 int8 +type Mask8x32 struct { + int8x32 v256 + vals [32]int8 +} + +// v512 is a tag type that tells the compiler that this is really 512-bit SIMD +type v512 struct { + _512 struct{} +} + +// Int16x32 is a 512-bit SIMD vector of 32 int16 +type Int16x32 struct { + int16x32 v512 + vals [32]int16 +} + +// Len returns the number of elements in a Int16x32 +func (x Int16x32) Len() int { return 32 } + +// LoadInt16x32 loads a Int16x32 from an array +// +//go:noescape +func LoadInt16x32(y *[32]int16) Int16x32 + +// Store stores a Int16x32 to an array +// +//go:noescape +func (x Int16x32) Store(y *[32]int16) + +// Mask16x32 is a 512-bit SIMD vector of 32 int16 +type Mask16x32 struct { + int16x32 v512 + vals [32]int16 +} + +// Int32x16 is a 512-bit SIMD vector of 16 int32 +type Int32x16 struct { + int32x16 v512 + vals [16]int32 +} + +// Len returns the number of elements in a Int32x16 +func (x Int32x16) Len() int { return 16 } + +// LoadInt32x16 loads a Int32x16 from an array +// +//go:noescape +func LoadInt32x16(y *[16]int32) Int32x16 + +// Store stores a Int32x16 to an array +// +//go:noescape +func (x Int32x16) Store(y *[16]int32) + +// Mask32x16 is a 512-bit SIMD vector of 16 int32 +type Mask32x16 struct { + int32x16 v512 + vals [16]int32 +} + +// Int64x8 is a 512-bit SIMD vector of 8 int64 +type Int64x8 struct { + int64x8 v512 + vals [8]int64 +} + +// Len returns the number of elements in a Int64x8 +func (x Int64x8) Len() int { return 8 } + +// LoadInt64x8 loads a Int64x8 from an array +// +//go:noescape +func LoadInt64x8(y *[8]int64) Int64x8 + +// Store stores a Int64x8 to an array +// +//go:noescape +func (x Int64x8) Store(y *[8]int64) + +// Mask64x8 is a 512-bit SIMD vector of 8 int64 +type Mask64x8 struct { + int64x8 v512 + vals [8]int64 +} + +// Int8x64 is a 512-bit SIMD vector of 64 int8 +type Int8x64 struct { + int8x64 v512 + vals [64]int8 +} + +// Len returns the number of elements in a Int8x64 +func (x Int8x64) Len() int { return 64 } + +// LoadInt8x64 loads a Int8x64 from an array +// +//go:noescape +func LoadInt8x64(y *[64]int8) Int8x64 + +// Store stores a Int8x64 to an array +// +//go:noescape +func (x Int8x64) Store(y *[64]int8) + +// Mask8x64 is a 512-bit SIMD vector of 64 int8 +type Mask8x64 struct { + int8x64 v512 + vals [64]int8 +} + +// Float32x16 is a 512-bit SIMD vector of 16 float32 +type Float32x16 struct { + float32x16 v512 + vals [16]float32 +} + +// Len returns the number of elements in a Float32x16 +func (x Float32x16) Len() int { return 16 } + +// LoadFloat32x16 loads a Float32x16 from an array +// +//go:noescape +func LoadFloat32x16(y *[16]float32) Float32x16 + +// Store stores a Float32x16 to an array +// +//go:noescape +func (x Float32x16) Store(y *[16]float32) + +// Float64x8 is a 512-bit SIMD vector of 8 float64 +type Float64x8 struct { + float64x8 v512 + vals [8]float64 +} + +// Len returns the number of elements in a Float64x8 +func (x Float64x8) Len() int { return 8 } + +// LoadFloat64x8 loads a Float64x8 from an array +// +//go:noescape +func LoadFloat64x8(y *[8]float64) Float64x8 + +// Store stores a Float64x8 to an array +// +//go:noescape +func (x Float64x8) Store(y *[8]float64) + +// Uint16x32 is a 512-bit SIMD vector of 32 uint16 +type Uint16x32 struct { + uint16x32 v512 + vals [32]uint16 +} + +// Len returns the number of elements in a Uint16x32 +func (x Uint16x32) Len() int { return 32 } + +// LoadUint16x32 loads a Uint16x32 from an array +// +//go:noescape +func LoadUint16x32(y *[32]uint16) Uint16x32 + +// Store stores a Uint16x32 to an array +// +//go:noescape +func (x Uint16x32) Store(y *[32]uint16) + +// Uint32x16 is a 512-bit SIMD vector of 16 uint32 +type Uint32x16 struct { + uint32x16 v512 + vals [16]uint32 +} + +// Len returns the number of elements in a Uint32x16 +func (x Uint32x16) Len() int { return 16 } + +// LoadUint32x16 loads a Uint32x16 from an array +// +//go:noescape +func LoadUint32x16(y *[16]uint32) Uint32x16 + +// Store stores a Uint32x16 to an array +// +//go:noescape +func (x Uint32x16) Store(y *[16]uint32) + +// Uint64x8 is a 512-bit SIMD vector of 8 uint64 +type Uint64x8 struct { + uint64x8 v512 + vals [8]uint64 +} + +// Len returns the number of elements in a Uint64x8 +func (x Uint64x8) Len() int { return 8 } + +// LoadUint64x8 loads a Uint64x8 from an array +// +//go:noescape +func LoadUint64x8(y *[8]uint64) Uint64x8 + +// Store stores a Uint64x8 to an array +// +//go:noescape +func (x Uint64x8) Store(y *[8]uint64) + +// Uint8x64 is a 512-bit SIMD vector of 64 uint8 +type Uint8x64 struct { + uint8x64 v512 + vals [64]uint8 +} + +// Len returns the number of elements in a Uint8x64 +func (x Uint8x64) Len() int { return 64 } + +// LoadUint8x64 loads a Uint8x64 from an array +// +//go:noescape +func LoadUint8x64(y *[64]uint8) Uint8x64 + +// Store stores a Uint8x64 to an array +// +//go:noescape +func (x Uint8x64) Store(y *[64]uint8)