IDF release/v4.4 fee50c208a

Author: me-no-dev

platform.txt

@@ -329,7 +329,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.4-207-g60b90c5144\\"'),
+        ("IDF_VER", '\\"v4.4.4-235-gfee50c208a\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32.py

@@ -324,7 +324,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.4-207-g60b90c5144\\"'),
+        ("IDF_VER", '\\"v4.4.4-235-gfee50c208a\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32c3.py

@@ -310,7 +310,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.4-207-g60b90c5144\\"'),
+        ("IDF_VER", '\\"v4.4.4-235-gfee50c208a\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s2.py

@@ -328,7 +328,7 @@
         "UNITY_INCLUDE_CONFIG_H",
         "WITH_POSIX",
         "_GNU_SOURCE",
-        ("IDF_VER", '\\"v4.4.4-207-g60b90c5144\\"'),
+        ("IDF_VER", '\\"v4.4.4-235-gfee50c208a\\"'),
         "ESP_PLATFORM",
         "_POSIX_READER_WRITER_LOCKS",
         "ARDUINO_ARCH_ESP32",

tools/platformio-build-esp32s3.py

@@ -220,6 +220,11 @@
 #define CONFIG_ESP32_ECO3_CACHE_LOCK_FIX 1
 #define CONFIG_ESP32_REV_MIN_0 1
 #define CONFIG_ESP32_REV_MIN 0
+#define CONFIG_ESP32_REV_MIN_FULL 0
+#define CONFIG_ESP_REV_MIN_FULL 0
+#define CONFIG_ESP32_REV_MAX_FULL_STR_OPT 1
+#define CONFIG_ESP32_REV_MAX_FULL 399
+#define CONFIG_ESP_REV_MAX_FULL 399
 #define CONFIG_ESP32_DPORT_WORKAROUND 1
 #define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1
 #define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
@@ -443,6 +448,7 @@
 #define CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID 1
 #define CONFIG_LWIP_DHCP_RESTORE_LAST_IP 1
 #define CONFIG_LWIP_DHCP_OPTIONS_LEN 128
+#define CONFIG_LWIP_DHCP_COARSE_TIMER_SECS 1
 #define CONFIG_LWIP_DHCPS 1
 #define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
 #define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
@@ -820,5 +826,5 @@
 #define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
 #define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
-#define CONFIG_ARDUINO_IDF_COMMIT "60b90c5144"
+#define CONFIG_ARDUINO_IDF_COMMIT "fee50c208a"
 #define CONFIG_ARDUINO_IDF_BRANCH "release/v4.4"

tools/sdk/esp32/bin/bootloader_dio_40m.elf

@@ -220,6 +220,11 @@
 #define CONFIG_ESP32_ECO3_CACHE_LOCK_FIX 1
 #define CONFIG_ESP32_REV_MIN_0 1
 #define CONFIG_ESP32_REV_MIN 0
+#define CONFIG_ESP32_REV_MIN_FULL 0
+#define CONFIG_ESP_REV_MIN_FULL 0
+#define CONFIG_ESP32_REV_MAX_FULL_STR_OPT 1
+#define CONFIG_ESP32_REV_MAX_FULL 399
+#define CONFIG_ESP_REV_MAX_FULL 399
 #define CONFIG_ESP32_DPORT_WORKAROUND 1
 #define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1
 #define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
@@ -443,6 +448,7 @@
 #define CONFIG_LWIP_DHCP_DISABLE_VENDOR_CLASS_ID 1
 #define CONFIG_LWIP_DHCP_RESTORE_LAST_IP 1
 #define CONFIG_LWIP_DHCP_OPTIONS_LEN 128
+#define CONFIG_LWIP_DHCP_COARSE_TIMER_SECS 1
 #define CONFIG_LWIP_DHCPS 1
 #define CONFIG_LWIP_DHCPS_LEASE_UNIT 60
 #define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8
@@ -820,5 +826,5 @@
 #define CONFIG_ULP_COPROC_ENABLED CONFIG_ESP32_ULP_COPROC_ENABLED
 #define CONFIG_ULP_COPROC_RESERVE_MEM CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
 #define CONFIG_WARN_WRITE_STRINGS CONFIG_COMPILER_WARN_WRITE_STRINGS
-#define CONFIG_ARDUINO_IDF_COMMIT "60b90c5144"
+#define CONFIG_ARDUINO_IDF_COMMIT "fee50c208a"
 #define CONFIG_ARDUINO_IDF_BRANCH "release/v4.4"

tools/sdk/esp32/bin/bootloader_dio_80m.elf

@@ -79,8 +79,15 @@ typedef struct {
                                 * pin and sets this field to 0xEE=disabled) */
     uint8_t spi_pin_drv[3];     /*!< Drive settings for the SPI flash pins (read by ROM bootloader) */
     esp_chip_id_t chip_id;      /*!< Chip identification number */
-    uint8_t min_chip_rev;       /*!< Minimum chip revision supported by image */
-    uint8_t reserved[8];       /*!< Reserved bytes in additional header space, currently unused */
+    uint8_t min_chip_rev;       /*!< Minimal chip revision supported by image
+                                 * After the Major and Minor revision eFuses were introduced into the chips, this field is no longer used.
+                                 * But for compatibility reasons, we keep this field and the data in it.
+                                 * Use min_chip_rev_full instead.
+                                 * The software interprets this as a Major version for most of the chips and as a Minor version for the ESP32-C3.
+                                 */
+    uint16_t min_chip_rev_full; /*!< Minimal chip revision supported by image, in format: major * 100 + minor */
+    uint16_t max_chip_rev_full; /*!< Maximal chip revision supported by image, in format: major * 100 + minor */
+    uint8_t reserved[4];        /*!< Reserved bytes in additional header space, currently unused */
     uint8_t hash_appended;      /*!< If 1, a SHA256 digest "simple hash" (of the entire image) is appended after the checksum.
                                  * Included in image length. This digest
                                  * is separate to secure boot and only used for detecting corruption.

tools/sdk/esp32/bin/bootloader_dout_40m.elf

@@ -200,7 +200,7 @@ typedef struct {
  */
 esp_err_t esp_secure_boot_verify_ecdsa_signature_block(const esp_secure_boot_sig_block_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest);
 
-#if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3
+#if !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
 /**
  * @brief Structure to hold public key digests calculated from the signature blocks of a single image.
  *
@@ -223,7 +223,7 @@ typedef struct {
  *
  */
 esp_err_t esp_secure_boot_verify_rsa_signature_block(const ets_secure_boot_signature_t *sig_block, const uint8_t *image_digest, uint8_t *verified_digest);
-#endif // !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_3
+#endif // !CONFIG_IDF_TARGET_ESP32 || CONFIG_ESP32_REV_MIN_FULL >= 300
 
 /** @brief Legacy ECDSA verification function
  *

tools/sdk/esp32/bin/bootloader_dout_80m.elf

@@ -741,7 +741,7 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
 esp_err_t esp_efuse_write_keys(const esp_efuse_purpose_t purposes[], uint8_t keys[][32], unsigned number_of_keys);
 
 
-#if CONFIG_ESP32_REV_MIN_3 || !CONFIG_IDF_TARGET_ESP32
+#if CONFIG_ESP32_REV_MIN_FULL >= 300 || !CONFIG_IDF_TARGET_ESP32
 /**
  * @brief Read key digests from efuse. Any revoked/missing digests will be marked as NULL
  *

tools/sdk/esp32/bin/bootloader_qio_40m.elf

@@ -1,21 +1,13 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
 #include "sdkconfig.h"
-#ifdef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -47,4 +39,4 @@ bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash, u
 }
 #endif
 
-#endif // CONFIG_ESP32_REV_MIN_3
+#endif // CONFIG_ESP32_REV_MIN_FULL >= 300

tools/sdk/esp32/bin/bootloader_qio_80m.elf

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,7 +34,7 @@ bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
 
 int ets_secure_boot_check_finish(uint32_t *abstract);
 
-#ifdef CONFIG_ESP32_REV_MIN_3
+#if CONFIG_ESP32_REV_MIN_FULL >= 300
 #include "rsa_pss.h"
 
 #define SECURE_BOOT_NUM_BLOCKS 1
@@ -115,7 +115,7 @@ bool ets_use_secure_boot_v2(void);
 #else
 #define SECURE_BOOT_NUM_BLOCKS 0
 
-#endif /* CONFIG_ESP32_REV_MIN_3 */
+#endif /* CONFIG_ESP32_REV_MIN_FULL >= 300 */
 
 #ifdef __cplusplus
 }

tools/sdk/esp32/bin/bootloader_qout_40m.elf

@@ -38,7 +38,7 @@ extern "C" {
 #define CAN_MSG_FLAG_SELF               TWAI_MSG_FLAG_SELF
 #define CAN_MSG_FLAG_DLC_NON_COMP       TWAI_MSG_FLAG_DLC_NON_COMP
 
-#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200)
 #define CAN_TIMING_CONFIG_12_5KBITS()   TWAI_TIMING_CONFIG_12_5KBITS()
 #define CAN_TIMING_CONFIG_16KBITS()     TWAI_TIMING_CONFIG_16KBITS()
 #define CAN_TIMING_CONFIG_20KBITS()     TWAI_TIMING_CONFIG_20KBITS()

tools/sdk/esp32/bin/bootloader_qout_80m.elf

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -65,7 +57,7 @@ extern "C" {
 #define TWAI_TIMING_CONFIG_5KBITS()     {.brp = 800, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_10KBITS()    {.brp = 400, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
 #endif
-#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN >= 2)
+#if (SOC_TWAI_BRP_MAX > 128) || (CONFIG_ESP32_REV_MIN_FULL >= 200)
 #define TWAI_TIMING_CONFIG_12_5KBITS()  {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_16KBITS()    {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
 #define TWAI_TIMING_CONFIG_20KBITS()    {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}

tools/sdk/esp32/dio_qspi/include/sdkconfig.h

@@ -50,11 +50,9 @@ extern "C" {
 #endif
 
 /** period (in seconds) of the application calling dhcp_coarse_tmr() */
-#if ESP_DHCP
+#ifndef DHCP_COARSE_TIMER_SECS
 #define DHCP_COARSE_TIMER_SECS 1
-#else
-#define DHCP_COARSE_TIMER_SECS 60
-#endif
+#endif /* DHCP_COARSE_TIMER_SECS */
 /** period (in milliseconds) of the application calling dhcp_coarse_tmr() */
 #define DHCP_COARSE_TIMER_MSECS (DHCP_COARSE_TIMER_SECS * 1000UL)
 /** period (in milliseconds) of the application calling dhcp_fine_tmr() */

tools/sdk/esp32/dio_qspi/libspi_flash.a

@@ -21,6 +21,11 @@
 #include "netif/dhcp_state.h"
 #include "sntp/sntp_get_set_time.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /* Enable all Espressif-only options */
 
 /*
@@ -231,6 +236,33 @@
  */
 #define ESP_DHCP_DISABLE_CLIENT_ID      CONFIG_LWIP_DHCP_DISABLE_CLIENT_ID
 
+#define DHCP_DEFINE_CUSTOM_TIMEOUTS     1
+/* Since for embedded devices it's not that hard to miss a discover packet, so lower
+ * the discover retry backoff time from (2,4,8,16,32,60,60)s to (500m,1,2,4,8,15,15)s.
+ */
+ #define DHCP_REQUEST_TIMEOUT_SEQUENCE(state, tries)   (state == DHCP_STATE_REQUESTING ? \
+                                                       (uint16_t)(1 * 1000) : \
+                                                       (uint16_t)(((tries) < 6 ? 1 << (tries) : 60) * 250))
+
+#define DHCP_COARSE_TIMER_SECS CONFIG_LWIP_DHCP_COARSE_TIMER_SECS
+
+static inline uint32_t timeout_from_offered(uint32_t lease, uint32_t min)
+{
+    uint32_t timeout = lease;
+    if (timeout == 0) {
+      timeout = min;
+    }
+    timeout = (timeout + DHCP_COARSE_TIMER_SECS - 1) / DHCP_COARSE_TIMER_SECS;
+    return timeout;
+}
+
+#define DHCP_CALC_TIMEOUT_FROM_OFFERED_T0_LEASE(dhcp) \
+   timeout_from_offered((dhcp)->offered_t0_lease, 120)
+#define DHCP_CALC_TIMEOUT_FROM_OFFERED_T1_RENEW(dhcp) \
+   timeout_from_offered((dhcp)->offered_t1_renew, (dhcp)->t0_timeout >> 1 /* 50% */)
+#define DHCP_CALC_TIMEOUT_FROM_OFFERED_T2_REBIND(dhcp) \
+   timeout_from_offered((dhcp)->offered_t2_rebind, ((dhcp)->t0_timeout / 8) * 7 /* 87.5% */)
+
 /**
  * CONFIG_LWIP_DHCP_RESTORE_LAST_IP==1: Last valid IP address obtained from DHCP server
  * is restored after reset/power-up.
@@ -1111,4 +1143,8 @@
 
 #define SOC_SEND_LOG //printf
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __LWIPOPTS_H__ */

tools/sdk/esp32/dout_qspi/include/sdkconfig.h

@@ -31,7 +31,7 @@
 #ifdef __has_include
 #  if __has_include("sdkconfig.h")
 #    include "sdkconfig.h"
-#    define SOC_CAPS_ECO_VER    CONFIG_ESP32_REV_MIN
+#    define SOC_CAPS_ECO_VER    CONFIG_ESP32_REV_MIN_FULL
 #  endif
 #endif
 
@@ -50,7 +50,7 @@
 #endif
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
-#define SOC_CAPS_ECO_VER_MAX        3
+#define SOC_CAPS_ECO_VER_MAX        301
 
 #define SOC_ADC_SUPPORTED           1
 #define SOC_DAC_SUPPORTED           1
@@ -80,6 +80,7 @@
 /*!< SAR ADC Module*/
 #define SOC_ADC_RTC_CTRL_SUPPORTED              1
 #define SOC_ADC_DIG_CTRL_SUPPORTED              1
+#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT)        ((UNIT == 0) ? 1 : 0)
 #define SOC_ADC_PERIPH_NUM                      (2)
 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM)         ((PERIPH_NUM==0)? 8: 10)
 #define SOC_ADC_MAX_CHANNEL_NUM                 (10)
@@ -101,7 +102,7 @@
 
 
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
-#if SOC_CAPS_ECO_VER >= 1
+#if SOC_CAPS_ECO_VER >= 100
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
 #endif
 
@@ -251,7 +252,7 @@
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
 #define SOC_TWAI_BRP_MIN                        2
-#if SOC_CAPS_ECO_VER >= 2
+#if SOC_CAPS_ECO_VER >= 200
 #  define SOC_TWAI_BRP_MAX              256
 #  define SOC_TWAI_BRP_DIV_SUPPORTED    1
 #  define SOC_TWAI_BRP_DIV_THRESH       128

tools/sdk/esp32/dout_qspi/libspi_flash.a

@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Convenient macros to check current wafer version against a version where some changes are introduced.
+ * Use `ESP_CHIP_REV_ABOVE` for a change introduced before any major versions.
+ * Use `ESP_CHIP_REV_MAJOR_AND_ABOVE` for changes introduced after a major version is added.
+ * For example, on ESP32 we have wafer versions:
+ *
+ * 0.0 -> 1.0 -> 2.0 -> 3.0 -> 3.1 -> N.A.
+ *            |->1.1
+ *
+ * - If we are adding code for a change on 1.1, we should use `ESP_CHIP_REV_MAJOR_AND_ABOVE`
+ *   because there is already major version 2 existing. The condition will be met from 1.1 to 1.99,
+ *   while not inherited by 2.0 and above.
+ *
+ * - If we are adding code for a change on 3.1, we should use `ESP_CHIP_REV_ABOVE`
+ *   because there is no major version 4. The condition will be met from 3.1 to 3.99 and 4.0 and above.
+ *   Even if we add revision 4.0 on this version, the logic will be inherited.
+ */
+
+#define ESP_CHIP_REV_ABOVE(rev, min_rev) ((min_rev) <= (rev))
+#define ESP_CHIP_REV_MAJOR_AND_ABOVE(rev, min_rev) (((rev) / 100 == (min_rev) / 100) && ((rev) >= (min_rev)))
+
+_Static_assert(CONFIG_ESP_REV_MIN_FULL <= CONFIG_ESP_REV_MAX_FULL, "Min version must be less than Max version");
+
+#ifdef __cplusplus
+}
+#endif