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base repository: BrunoLevy/learn-fpga
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head repository: jeras/learn-fpga
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compare: master
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  • 6 commits
  • 1 file changed
  • 1 contributor

Commits on Jun 18, 2022

  1. RTL: cosmetic changes, Verilog-2001 style for parameters and whitespace

    @jeras
    jeras committed Jun 18, 2022
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  2. RTL: dedicated logical operation code fitting in a LUT4

    @jeras
    jeras committed Jun 18, 2022
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  3. RTL: recoded func3 muxes from one-hot to binary, the ALU-mux change m… 

    …ade no difference, the BRANCH-mux change saved 2 LC
    @jeras
    jeras committed Jun 18, 2022
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  4. RTL: cosmetic change only, no functional change

    @jeras
    jeras committed Jun 18, 2022
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  5. RTL: changed system bus write data encoder, reduced size a tiny bit

    @jeras
    jeras committed Jun 18, 2022
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  6. RTL: fixed issue with memory access alignment

    @jeras
    jeras committed Jun 18, 2022
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