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py/asmrv32: Do not use binary literals.
As per discussion in micropython#15347, non-standard binary literals have been removed in favour of their hexadecimal counterparts. Signed-off-by: Alessandro Gatti <[email protected]>
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‎py/asmrv32.h

Lines changed: 79 additions & 88 deletions
Original file line numberDiff line numberDiff line change
@@ -122,305 +122,296 @@ void asm_rv32_end_pass(asm_rv32_t *state);
122122

123123
////////////////////////////////////////////////////////////////////////////////
124124

125-
#define RV32_ENCODE_TYPE_B(op, ft3, rs1, rs2, imm) \
126-
((op & 0b1111111) | ((ft3 & 0b111) << 12) | ((imm & 0b100000000000) >> 4) | \
127-
((imm & 0b11110) << 7) | ((rs1 & 0b11111) << 15) | \
128-
((rs2 & 0b11111) << 20) | ((imm & 0b11111100000) << 20) | \
129-
((imm & 0b1000000000000) << 19))
130-
131-
#define RV32_ENCODE_TYPE_I(op, ft3, rd, rs, imm) \
132-
((op & 0b1111111) | ((rd & 0b11111) << 7) | ((ft3 & 0b111) << 12) | \
133-
((rs & 0b11111) << 15) | ((imm & 0b111111111111) << 20))
134-
135-
#define RV32_ENCODE_TYPE_J(op, rd, imm) \
136-
((op & 0b1111111) | ((rd & 0b11111) << 7) | (imm & 0b11111111000000000000) | \
137-
((imm & 0b100000000000) << 9) | ((imm & 0b11111111110) << 20) | \
138-
((imm & 0b100000000000000000000) << 11))
139-
140-
#define RV32_ENCODE_TYPE_R(op, ft3, ft7, rd, rs1, rs2) \
141-
((op & 0b1111111) | ((rd & 0b11111) << 7) | ((ft3 & 0b111) << 12) | \
142-
((rs1 & 0b11111) << 15) | ((rs2 & 0b11111) << 20) | \
143-
((ft7 & 0b1111111) << 25))
144-
145-
#define RV32_ENCODE_TYPE_S(op, ft3, rs1, rs2, imm) \
146-
((op & 0b1111111) | ((imm & 0b11111) << 7) | ((ft3 & 0b111) << 12) | \
147-
((rs1 & 0b11111) << 15) | ((rs2 & 0b11111) << 20) | \
148-
((imm & 0b111111100000) << 20))
149-
150-
#define RV32_ENCODE_TYPE_U(op, rd, imm) \
151-
((op & 0b1111111) | ((rd & 0b11111) << 7) | \
152-
(imm & 0b11111111111111111111000000000000))
125+
#define RV32_ENCODE_TYPE_B(op, ft3, rs1, rs2, imm) \
126+
((op & 0x7F) | ((ft3 & 0x07) << 12) | ((imm & 0x800) >> 4) | \
127+
((imm & 0x1E) << 7) | ((rs1 & 0x1F) << 15) | ((rs2 & 0x1F) << 20) | \
128+
((imm & 0x7E0) << 20) | ((imm & 0x1000) << 19))
129+
130+
#define RV32_ENCODE_TYPE_I(op, ft3, rd, rs, imm) \
131+
((op & 0x7F) | ((rd & 0x1F) << 7) | ((ft3 & 0x07) << 12) | \
132+
((rs & 0x1F) << 15) | ((imm & 0xFFF) << 20))
133+
134+
#define RV32_ENCODE_TYPE_J(op, rd, imm) \
135+
((op & 0x7F) | ((rd & 0x1F) << 7) | (imm & 0xFF000) | \
136+
((imm & 0x800) << 9) | ((imm & 0x7FE) << 20) | ((imm & 0x100000) << 11))
137+
138+
#define RV32_ENCODE_TYPE_R(op, ft3, ft7, rd, rs1, rs2) \
139+
((op & 0x7F) | ((rd & 0x1F) << 7) | ((ft3 & 0x07) << 12) | \
140+
((rs1 & 0x1F) << 15) | ((rs2 & 0x1F) << 20) | ((ft7 & 0x7F) << 25))
141+
142+
#define RV32_ENCODE_TYPE_S(op, ft3, rs1, rs2, imm) \
143+
((op & 0x7F) | ((imm & 0x1F) << 7) | ((ft3 & 0x07) << 12) | \
144+
((rs1 & 0x1F) << 15) | ((rs2 & 0x1F) << 20) | ((imm & 0xFE0) << 20))
145+
146+
#define RV32_ENCODE_TYPE_U(op, rd, imm) \
147+
((op & 0x7F) | ((rd & 0x1F) << 7) | (imm & 0xFFFFF000))
153148

154149
#define RV32_ENCODE_TYPE_CB(op, ft3, rs, imm) \
155-
((op & 0b11) | ((ft3 & 0b111) << 13) | ((rs & 0b111) << 7) | \
156-
(((imm) & 0b100000000) << 4) | (((imm) & 0b11000000) >> 1) | \
157-
(((imm) & 0b100000) >> 3) | (((imm) & 0b11000) << 7) | \
158-
(((imm) & 0b110) << 2))
150+
((op & 0x03) | ((ft3 & 0x07) << 13) | ((rs & 0x07) << 7) | \
151+
(((imm) & 0x100) << 4) | (((imm) & 0xC0) >> 1) | (((imm) & 0x20) >> 3) | \
152+
(((imm) & 0x18) << 7) | (((imm) & 0x06) << 2))
159153

160154
#define RV32_ENCODE_TYPE_CI(op, ft3, rd, imm) \
161-
((op & 0b11) | ((ft3 & 0b111) << 13) | ((rd & 0b11111) << 7) | \
162-
(((imm) & 0b100000) << 7) | (((imm) & 0b11111) << 2))
155+
((op & 0x03) | ((ft3 & 0x07) << 13) | ((rd & 0x1F) << 7) | \
156+
(((imm) & 0x20) << 7) | (((imm) & 0x1F) << 2))
163157

164158
#define RV32_ENCODE_TYPE_CIW(op, ft3, rd, imm) \
165-
((op & 0b11) | ((ft3 & 0b111) << 13) | ((rd & 0b111) << 2) | \
166-
((imm & 0b1111000000) << 1) | ((imm & 0b110000) << 7) | \
167-
((imm & 0b1000) << 2) | ((imm & 0b100) << 4))
159+
((op & 0x03) | ((ft3 & 0x07) << 13) | ((rd & 0x07) << 2) | \
160+
((imm & 0x3C0) << 1) | ((imm & 0x30) << 7) | \
161+
((imm & 0x08) << 2) | ((imm & 0x04) << 4))
168162

169163
#define RV32_ENCODE_TYPE_CJ(op, ft3, imm) \
170-
((op & 0b11) | ((ft3 & 0b111) << 13) | \
171-
((imm & 0b1110) << 2) | ((imm & 0b1100000000) << 1) | \
172-
((imm & 0b100000000000) << 1) | ((imm & 0b10000000000) >> 2) | \
173-
((imm & 0b10000000) >> 1) | ((imm & 0b1000000) << 1) | \
174-
((imm & 0b100000) >> 3) | ((imm & 0b10000) << 7))
164+
((op & 0x03) | ((ft3 & 0x07) << 13) | ((imm & 0x0E) << 2) | \
165+
((imm & 0x300) << 1) | ((imm & 0x800) << 1) | ((imm & 0x400) >> 2) | \
166+
((imm & 0x80) >> 1) | ((imm & 0x40) << 1) | ((imm & 0x20) >> 3) | \
167+
((imm & 0x10) << 7))
175168

176169
#define RV32_ENCODE_TYPE_CL(op, ft3, rd, rs, imm) \
177-
((op & 0b11) | ((ft3 & 0b111) << 13) | ((rd & 0b111) << 2) | \
178-
((rs & 0b111) << 7) | ((imm & 0b1000000) >> 1) | \
179-
((imm & 0b111000) << 7) | ((imm & 0b100) << 4))
170+
((op & 0x03) | ((ft3 & 0x07) << 13) | ((rd & 0x07) << 2) | \
171+
((rs & 0x07) << 7) | ((imm & 0x40) >> 1) | ((imm & 0x38) << 7) | \
172+
((imm & 0x04) << 4))
180173

181174
#define RV32_ENCODE_TYPE_CR(op, ft4, rs1, rs2) \
182-
((op & 0b11) | ((rs2 & 0b11111) << 2) | ((rs1 & 0b11111) << 7) | \
183-
((ft4 & 0b1111) << 12))
175+
((op & 0x03) | ((rs2 & 0x1F) << 2) | ((rs1 & 0x1F) << 7) | ((ft4 & 0x0F) << 12))
184176

185177
#define RV32_ENCODE_TYPE_CSS(op, ft3, rs, imm) \
186-
((op & 0b11) | ((ft3 & 0b111) << 13) | ((rs & 0b11111) << 2) | \
187-
((imm) & 0b111111) << 7)
178+
((op & 0x03) | ((ft3 & 0x07) << 13) | ((rs & 0x1F) << 2) | ((imm) & 0x3F) << 7)
188179

189180
void asm_rv32_emit_word_opcode(asm_rv32_t *state, mp_uint_t opcode);
190181
void asm_rv32_emit_halfword_opcode(asm_rv32_t *state, mp_uint_t opcode);
191182

192183
// ADD RD, RS1, RS2
193184
static inline void asm_rv32_opcode_add(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
194185
// R: 0000000 ..... ..... 000 ..... 0110011
195-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b000, 0b0000000, rd, rs1, rs2));
186+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x00, 0x00, rd, rs1, rs2));
196187
}
197188

198189
// ADDI RD, RS, IMMEDIATE
199190
static inline void asm_rv32_opcode_addi(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t immediate) {
200191
// I: ............ ..... 000 ..... 0010011
201-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b0010011, 0b000, rd, rs, immediate));
192+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x13, 0x00, rd, rs, immediate));
202193
}
203194

204195
// AND RD, RS1, RS2
205196
static inline void asm_rv32_opcode_and(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
206197
// R: 0000000 ..... ..... 111 ..... 0110011
207-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b111, 0b0000000, rd, rs1, rs2));
198+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x07, 0x00, rd, rs1, rs2));
208199
}
209200

210201
// AUIPC RD, offset
211202
static inline void asm_rv32_opcode_auipc(asm_rv32_t *state, mp_uint_t rd, mp_int_t offset) {
212203
// U: .................... ..... 0010111
213-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_U(0b0010111, rd, offset));
204+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_U(0x17, rd, offset));
214205
}
215206

216207
// BEQ RS1, RS2, OFFSET
217208
static inline void asm_rv32_opcode_beq(asm_rv32_t *state, mp_uint_t rs1, mp_uint_t rs2, mp_int_t offset) {
218209
// B: . ...... ..... ..... 000 .... . 1100011
219-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_B(0b1100011, 0b000, rs1, rs2, offset));
210+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_B(0x63, 0x00, rs1, rs2, offset));
220211
}
221212

222213
// BNE RS1, RS2, OFFSET
223214
static inline void asm_rv32_opcode_bne(asm_rv32_t *state, mp_uint_t rs1, mp_uint_t rs2, mp_int_t offset) {
224215
// B: . ...... ..... ..... 001 .... . 1100011
225-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_B(0b1100011, 0b001, rs1, rs2, offset));
216+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_B(0x63, 0x01, rs1, rs2, offset));
226217
}
227218

228219
// C.ADD RD, RS
229220
static inline void asm_rv32_opcode_cadd(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs) {
230221
// CR: 1001 ..... ..... 10
231-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0b10, 0b1001, rd, rs));
222+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0x02, 0x09, rd, rs));
232223
}
233224

234225
// C.ADDI RD, IMMEDIATE
235226
static inline void asm_rv32_opcode_caddi(asm_rv32_t *state, mp_uint_t rd, mp_int_t immediate) {
236227
// CI: 000 . ..... ..... 01
237-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0b01, 0b000, rd, immediate));
228+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0x01, 0x00, rd, immediate));
238229
}
239230

240231
// C.ADDI4SPN RD', IMMEDIATE
241232
static inline void asm_rv32_opcode_caddi4spn(asm_rv32_t *state, mp_uint_t rd, mp_uint_t immediate) {
242233
// CIW: 000 ........ ... 00
243-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CIW(0b00, 0b000, rd, immediate));
234+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CIW(0x00, 0x00, rd, immediate));
244235
}
245236

246237
// C.BEQZ RS', IMMEDIATE
247238
static inline void asm_rv32_opcode_cbeqz(asm_rv32_t *state, mp_uint_t rs, mp_int_t offset) {
248239
// CB: 110 ... ... ..... 01
249-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CB(0b01, 0b110, rs, offset));
240+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CB(0x01, 0x06, rs, offset));
250241
}
251242

252243
// C.BNEZ RS', IMMEDIATE
253244
static inline void asm_rv32_opcode_cbnez(asm_rv32_t *state, mp_uint_t rs, mp_int_t offset) {
254245
// CB: 111 ... ... ..... 01
255-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CB(0b01, 0b111, rs, offset));
246+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CB(0x01, 0x07, rs, offset));
256247
}
257248

258249
// C.J OFFSET
259250
static inline void asm_rv32_opcode_cj(asm_rv32_t *state, mp_int_t offset) {
260251
// CJ: 101 ........... 01
261-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CJ(0b01, 0b101, offset));
252+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CJ(0x01, 0x05, offset));
262253
}
263254

264255
// C.JALR RS
265256
static inline void asm_rv32_opcode_cjalr(asm_rv32_t *state, mp_uint_t rs) {
266257
// CR: 1001 ..... 00000 10
267-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0b10, 0b1001, rs, 0));
258+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0x02, 0x09, rs, 0));
268259
}
269260

270261
// C.JR RS
271262
static inline void asm_rv32_opcode_cjr(asm_rv32_t *state, mp_uint_t rs) {
272263
// CR: 1000 ..... 00000 10
273-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0b10, 0b1000, rs, 0));
264+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0x02, 0x08, rs, 0));
274265
}
275266

276267
// C.LI RD, IMMEDIATE
277268
static inline void asm_rv32_opcode_cli(asm_rv32_t *state, mp_uint_t rd, mp_int_t immediate) {
278269
// CI: 010 . ..... ..... 01
279-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0b01, 0b010, rd, immediate));
270+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0x01, 0x02, rd, immediate));
280271
}
281272

282273
// C.LUI RD, IMMEDIATE
283274
static inline void asm_rv32_opcode_clui(asm_rv32_t *state, mp_uint_t rd, mp_int_t immediate) {
284275
// CI: 011 . ..... ..... 01
285-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0b01, 0b011, rd, immediate >> 12));
276+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0x01, 0x03, rd, immediate >> 12));
286277
}
287278

288279
// C.LW RD', OFFSET(RS')
289280
static inline void asm_rv32_opcode_clw(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t offset) {
290281
// CL: 010 ... ... .. ... 00
291-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CL(0b00, 0b010, rd, rs, offset));
282+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CL(0x00, 0x02, rd, rs, offset));
292283
}
293284

294285
// C.LWSP RD, OFFSET
295286
static inline void asm_rv32_opcode_clwsp(asm_rv32_t *state, mp_uint_t rd, mp_uint_t offset) {
296287
// CI: 010 . ..... ..... 10
297-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0b10, 0b010, rd, ((offset & 0b11000000) >> 6) | (offset & 0b111100)));
288+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CI(0x02, 0x02, rd, ((offset & 0xC0) >> 6) | (offset & 0x3C)));
298289
}
299290

300291
// C.MV RD, RS
301292
static inline void asm_rv32_opcode_cmv(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs) {
302293
// CR: 1000 ..... ..... 10
303-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0b10, 0b1000, rd, rs));
294+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CR(0x02, 0x08, rd, rs));
304295
}
305296

306297
// C.SWSP RS, OFFSET
307298
static inline void asm_rv32_opcode_cswsp(asm_rv32_t *state, mp_uint_t rs, mp_uint_t offset) {
308299
// CSS: 010 ...... ..... 10
309-
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CSS(0b10, 0b110, rs, ((offset & 0b11000000) >> 6) | (offset & 0b111100)));
300+
asm_rv32_emit_halfword_opcode(state, RV32_ENCODE_TYPE_CSS(0x02, 0x06, rs, ((offset & 0xC0) >> 6) | (offset & 0x3C)));
310301
}
311302

312303
// JALR RD, RS, offset
313304
static inline void asm_rv32_opcode_jalr(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t offset) {
314305
// I: ............ ..... 000 ..... 1100111
315-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b1100111, 0b000, rd, rs, offset));
306+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x67, 0x00, rd, rs, offset));
316307
}
317308

318309
// LBU RD, OFFSET(RS)
319310
static inline void asm_rv32_opcode_lbu(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t offset) {
320311
// I: ............ ..... 100 ..... 0000011
321-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b0000011, 0b100, rd, rs, offset));
312+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x03, 0x04, rd, rs, offset));
322313
}
323314

324315
// LHU RD, OFFSET(RS)
325316
static inline void asm_rv32_opcode_lhu(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t offset) {
326317
// I: ............ ..... 101 ..... 0000011
327-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b0000011, 0b101, rd, rs, offset));
318+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x03, 0x05, rd, rs, offset));
328319
}
329320

330321
// LUI RD, immediate
331322
static inline void asm_rv32_opcode_lui(asm_rv32_t *state, mp_uint_t rd, mp_int_t immediate) {
332323
// U: .................... ..... 0110111
333-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_U(0b0110111, rd, immediate));
324+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_U(0x37, rd, immediate));
334325
}
335326

336327
// LW RD, OFFSET(RS)
337328
static inline void asm_rv32_opcode_lw(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t offset) {
338329
// I: ............ ..... 010 ..... 0000011
339-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b0000011, 0b010, rd, rs, offset));
330+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x03, 0x02, rd, rs, offset));
340331
}
341332

342333
// MUL RD, RS1, RS2
343334
static inline void asm_rv32m_opcode_mul(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
344335
// R: 0000001 ..... ..... 000 ..... 0110011
345-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b000, 0b0000001, rd, rs1, rs2));
336+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x00, 0x01, rd, rs1, rs2));
346337
}
347338

348339
// OR RD, RS1, RS2
349340
static inline void asm_rv32_opcode_or(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
350341
// R: 0000000 ..... ..... 110 ..... 0110011
351-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b110, 0b0000000, rd, rs1, rs2));
342+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x06, 0x00, rd, rs1, rs2));
352343
}
353344

354345
// SLL RD, RS1, RS2
355346
static inline void asm_rv32_opcode_sll(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
356347
// R: 0000000 ..... ..... 001 ..... 0110011
357-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b001, 0b0000000, rd, rs1, rs2));
348+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x01, 0x00, rd, rs1, rs2));
358349
}
359350

360351
// SLLI RD, RS, IMMEDIATE
361352
static inline void asm_rv32_opcode_slli(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_uint_t immediate) {
362353
// I: 0000000..... ..... 001 ..... 0010011
363-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b0010011, 0b001, rd, rs, immediate & 0x1F));
354+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x13, 0x01, rd, rs, immediate & 0x1F));
364355
}
365356

366357
// SRL RD, RS1, RS2
367358
static inline void asm_rv32_opcode_srl(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
368359
// R: 0000000 ..... ..... 101 ..... 0110011
369-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b101, 0b0000000, rd, rs1, rs2));
360+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x05, 0x00, rd, rs1, rs2));
370361
}
371362

372363
// SLT RD, RS1, RS2
373364
static inline void asm_rv32_opcode_slt(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
374365
// R: 0000000 ..... ..... 010 ..... 0110011
375-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b010, 0b0000000, rd, rs1, rs2));
366+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x02, 0x00, rd, rs1, rs2));
376367
}
377368

378369
// SLTU RD, RS1, RS2
379370
static inline void asm_rv32_opcode_sltu(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
380371
// R: 0000000 ..... ..... 011 ..... 0110011
381-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b011, 0b0000000, rd, rs1, rs2));
372+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x03, 0x00, rd, rs1, rs2));
382373
}
383374

384375
// SRA RD, RS1, RS2
385376
static inline void asm_rv32_opcode_sra(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
386377
// R: 0100000 ..... ..... 101 ..... 0110011
387-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b101, 0b0100000, rd, rs1, rs2));
378+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x05, 0x20, rd, rs1, rs2));
388379
}
389380

390381
// SUB RD, RS1, RS2
391382
static inline void asm_rv32_opcode_sub(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
392383
// R: 0100000 ..... ..... 000 ..... 0110011
393-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b000, 0b0100000, rd, rs1, rs2));
384+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x00, 0x20, rd, rs1, rs2));
394385
}
395386

396387
// SB RS2, OFFSET(RS1)
397388
static inline void asm_rv32_opcode_sb(asm_rv32_t *state, mp_uint_t rs2, mp_uint_t rs1, mp_int_t offset) {
398389
// S: ....... ..... ..... 000 ..... 0100011
399-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_S(0b0100011, 0b000, rs1, rs2, offset));
390+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_S(0x23, 0x00, rs1, rs2, offset));
400391
}
401392

402393
// SH RS2, OFFSET(RS1)
403394
static inline void asm_rv32_opcode_sh(asm_rv32_t *state, mp_uint_t rs2, mp_uint_t rs1, mp_int_t offset) {
404395
// S: ....... ..... ..... 001 ..... 0100011
405-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_S(0b0100011, 0b001, rs1, rs2, offset));
396+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_S(0x23, 0x01, rs1, rs2, offset));
406397
}
407398

408399
// SW RS2, OFFSET(RS1)
409400
static inline void asm_rv32_opcode_sw(asm_rv32_t *state, mp_uint_t rs2, mp_uint_t rs1, mp_int_t offset) {
410401
// S: ....... ..... ..... 010 ..... 0100011
411-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_S(0b0100011, 0b010, rs1, rs2, offset));
402+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_S(0x23, 0x02, rs1, rs2, offset));
412403
}
413404

414405
// XOR RD, RS1, RS2
415406
static inline void asm_rv32_opcode_xor(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs1, mp_uint_t rs2) {
416407
// R: 0000000 ..... ..... 100 ..... 0110011
417-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0b0110011, 0b100, 0b0000000, rd, rs1, rs2));
408+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_R(0x33, 0x04, 0x00, rd, rs1, rs2));
418409
}
419410

420411
// XORI RD, RS, IMMEDIATE
421412
static inline void asm_rv32_opcode_xori(asm_rv32_t *state, mp_uint_t rd, mp_uint_t rs, mp_int_t immediate) {
422413
// I: ............ ..... 100 ..... 0010011
423-
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0b0010011, 0b100, rd, rs, immediate));
414+
asm_rv32_emit_word_opcode(state, RV32_ENCODE_TYPE_I(0x13, 0x04, rd, rs, immediate));
424415
}
425416

426417
#define ASM_WORD_SIZE (4)

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