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1 parent e20e87b commit 38b7bb0Copy full SHA for 38b7bb0
hdl/demo/test_card_simple.v
@@ -25,7 +25,7 @@ module test_card_simple #(H_RES=640) (
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wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
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// Colour Output
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- assign o_red = {8{b0 | b1 | b5}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
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- assign o_green = {8{b1 | b2 | b3}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
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- assign o_blue = {8{b3 | b4 | b5}} + {1'b0,{7{b6}}} + {2'b0,{6{b7}}};
+ assign o_red = {8{b0 | b1 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
+ assign o_green = {8{b1 | b2 | b3}} + {2'b0,{6{b6}}} + {b7, 7'b0};
+ assign o_blue = {8{b3 | b4 | b5}} + {2'b0,{6{b6}}} + {b7, 7'b0};
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endmodule
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