diff --git a/src/ESP32SJA1000.cpp b/src/ESP32SJA1000.cpp index 309e030..1f069dd 100644 --- a/src/ESP32SJA1000.cpp +++ b/src/ESP32SJA1000.cpp @@ -3,7 +3,7 @@ #ifdef ARDUINO_ARCH_ESP32 -#include "esp_intr.h" +#include "esp_intr_alloc.h" #include "soc/dport_reg.h" #include "driver/gpio.h" @@ -70,58 +70,89 @@ int ESP32SJA1000Class::begin(long baudRate) modifyRegister(REG_BTR0, 0xc0, 0x40); // SJW = 1 modifyRegister(REG_BTR1, 0x70, 0x10); // TSEG2 = 1 - switch (baudRate) { - case (long)1000E3: - modifyRegister(REG_BTR1, 0x0f, 0x04); - modifyRegister(REG_BTR0, 0x3f, 4); - break; - - case (long)500E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 4); - break; - - case (long)250E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 9); - break; - - case (long)200E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 12); - break; - - case (long)125E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 19); - break; - - case (long)100E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 24); - break; - - case (long)80E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 30); - break; - - case (long)50E3: - modifyRegister(REG_BTR1, 0x0f, 0x0c); - modifyRegister(REG_BTR0, 0x3f, 49); - break; - -/* - Due to limitations in ESP32 hardware and/or RTOS software, baudrate can't be lower than 50kbps. - See https://esp32.com/viewtopic.php?t=2142 -*/ - default: - return 0; - break; + esp_chip_info_t chip; + esp_chip_info(&chip); + + if (baudRate >= 50E3) { + + if (chip.revision >= 2) { + modifyRegister(REG_IER, 0x10, 0); // From rev2 used as "divide BRP by 2" + } + + switch (baudRate) { + case (long)1000E3: + modifyRegister(REG_BTR1, 0x0f, 0x04); + modifyRegister(REG_BTR0, 0x3f, 4); + break; + + case (long)500E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 4); + break; + + case (long)250E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 9); + break; + + case (long)200E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 12); + break; + + case (long)125E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 19); + break; + + case (long)100E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 24); + break; + + case (long)80E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 30); + break; + + case (long)50E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 49); + break; + + default: + return 0; + break; + } + }else { + + if (chip.revision >= 2) { + modifyRegister(REG_IER, 0x10, 0x10); // From rev2 used as "divide BRP by 2" + }else { + return 0; + } + + switch (baudRate) { + + case (long)40E3: + modifyRegister(REG_BTR1, 0x0f, 0x0c); + modifyRegister(REG_BTR0, 0x3f, 30); + break; + + case (long)20E3: + modifyRegister(REG_BTR1, 0x0f, 0x4d); + modifyRegister(REG_BTR0, 0x3f, 30); + break; + + default: + return 0; + break; + } + } modifyRegister(REG_BTR1, 0x80, 0x80); // SAM = 1 - writeRegister(REG_IER, 0xff); // enable all interrupts + modifyRegister(REG_IER, 0xef, 0xef); // enable all interrupts // set filter to allow anything writeRegister(REG_ACRn(0), 0x00); diff --git a/src/MCP2515.cpp b/src/MCP2515.cpp index a153a76..b5472eb 100644 --- a/src/MCP2515.cpp +++ b/src/MCP2515.cpp @@ -103,6 +103,19 @@ int MCP2515Class::begin(long baudRate) { (long)8E6, (long)10E3, { 0x0f, 0xbf, 0x07 } }, { (long)8E6, (long)5E3, { 0x1f, 0xbf, 0x07 } }, + { (long)12E6, (long)1000E3, { 0x00, 0x88, 0x01 } }, + { (long)12E6, (long)500E3, { 0x00, 0x9b, 0x02 } }, + { (long)12E6, (long)250E3, { 0x00, 0xbf, 0x06 } }, + { (long)12E6, (long)200E3, { 0x01, 0xa4, 0x03 } }, + { (long)12E6, (long)125E3, { 0x02, 0xac, 0x03 } }, + { (long)12E6, (long)100E3, { 0x02, 0xb6, 0x04 } }, + { (long)12E6, (long)80E3, { 0x04, 0xa4, 0x03 } }, + { (long)12E6, (long)50E3, { 0x05, 0xb6, 0x04 } }, + { (long)12E6, (long)40E3, { 0x09, 0xa4, 0x03 } }, + { (long)12E6, (long)20E3, { 0x0e, 0xb6, 0x04 } }, + { (long)12E6, (long)10E3, { 0x1d, 0xb6, 0x04 } }, + { (long)12E6, (long)5E3, { 0x3b, 0xb6, 0x04 } }, + { (long)16E6, (long)1000E3, { 0x00, 0xd0, 0x82 } }, { (long)16E6, (long)500E3, { 0x00, 0xf0, 0x86 } }, { (long)16E6, (long)250E3, { 0x41, 0xf1, 0x85 } },