diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml deleted file mode 100644 index 66126073..00000000 --- a/.github/FUNDING.yml +++ /dev/null @@ -1,3 +0,0 @@ -# These are supported funding model platforms - -github: [sandeepmistry] diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml deleted file mode 100644 index 9efea657..00000000 --- a/.github/workflows/compile.yml +++ /dev/null @@ -1,77 +0,0 @@ -name: Build - -on: - push: - branches: '*' - pull_request: - branches: '*' - -jobs: - compile: - strategy: - fail-fast: false - matrix: - variant: - - nRF52DK - - BluzDK - - RedBearLab_nRF51822:version=1_0 - - BBCmicrobit - - BBCmicrobitV2 - - CalliopeMini - - CalliopeminiV3 - - Generic_nRF51822:chip=xxac - - Generic_nRF52832 - - Generic_nRF52833 - - OSHChip - - STCT_nRF52_minidev - - PCA1000X:board_variant=pca10000 - - PCA1000X:board_variant=pca10001 - - PCA1000X:board_variant=nrf6310 - - nRF51Dongle:version=1_1_0 - - Blend2 - - BLENano - - BLENano2 - - TinyBLE - - bluey - - hackaBLE - - hackaBLE_v2 - - Sinobit - - DWM1001-DEV - - SeeedArchLink - - Beacon_PCA20006 - - Waveshare_BLE400 - - ng_beacon - runs-on: ubuntu-latest - name: Compile ${{ matrix.variant }} - steps: - - uses: actions/checkout@v3 - - name: Create blinky sketch to compile - run: | - mkdir blinky - cat > blinky/blinky.ino << EOF - void setup() { - pinMode(LED_BUILTIN, OUTPUT); - } - - void loop() { - digitalWrite(LED_BUILTIN, HIGH); - delay(1000); - digitalWrite(LED_BUILTIN, LOW); - delay(1000); - } - EOF - - uses: arduino/compile-sketches@v1 - with: - cli-version: latest - verbose: true - enable-deltas-report: true - platforms: | - # First we have to install this core so that the tooling is installed - - name: "sandeepmistry:nRF5" - source-url: "https://sandeepmistry.github.io/arduino-nRF5/package_nRF5_boards_index.json" - version: latest - # Now, this will overwrite the core source to use the local version - - name: "sandeepmistry:nRF5" - source-path: . - fqbn: "sandeepmistry:nRF5:${{ matrix.variant }}" - sketch-paths: blinky diff --git a/.piopm b/.piopm new file mode 100644 index 00000000..fae3d6a4 --- /dev/null +++ b/.piopm @@ -0,0 +1 @@ +{"type": "tool", "name": "framework-arduinonordicnrf5", "version": "1.700.201209", "spec": {"owner": "platformio", "id": 8076, "name": "framework-arduinonordicnrf5", "requirements": null, "uri": null}} \ No newline at end of file diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 00000000..c576ed57 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,45 @@ +language: generic +addons: + apt: + packages: + - libc6:i386 + - libstdc++6:i386 +env: + global: + - IDE_VERSION=1.8.5 +before_install: + - wget http://downloads.arduino.cc/arduino-$IDE_VERSION-linux64.tar.xz + - tar xf arduino-$IDE_VERSION-linux64.tar.xz + - mv arduino-$IDE_VERSION $HOME/arduino-ide + - export PATH=$PATH:$HOME/arduino-ide + - arduino --pref "boardsmanager.additional.urls=https://sandeepmistry.github.io/arduino-nRF5/package_nRF5_boards_index.json" --install-boards sandeepmistry:nRF5 > /dev/null + - buildExampleSketch() { arduino --verbose-build --verify --board $1 $HOME/arduino-ide/examples/$2/$3/$3.ino; } +install: + - mkdir -p $HOME/Arduino/hardware/sandeepmistry + - ln -s $PWD $HOME/Arduino/hardware/sandeepmistry/nRF5 +script: + - buildExampleSketch sandeepmistry:nRF5:nRF52DK 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:BluzDK 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:BLENano:version=1_0 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:RedBearLab_nRF51822:version=1_0 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:BBCmicrobit 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:CalliopeMini 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:Generic_nRF51822:chip=xxac 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:Generic_nRF52832 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:OSHChip 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:STCT_nRF52_minidev 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:PCA1000X:board_variant=pca10000 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:PCA1000X:board_variant=pca10001 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:PCA1000X:board_variant=nrf6310 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:nRF51Dongle:version=1_1_0 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:Blend2 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:BLENano2 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:TinyBLE 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:bluey 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:hackaBLE 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:hackaBLE_v2 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:Sinobit 01.Basics BareMinimum + - buildExampleSketch sandeepmistry:nRF5:DWM1001-DEV 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:SeeedArchLink 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:Generic_nRF52833 01.Basics Blink + - buildExampleSketch sandeepmistry:nRF5:BBCmicrobitV2 01.Basics Blink diff --git a/LICENSE b/LICENSE index 776cdc00..07afa1f9 100644 --- a/LICENSE +++ b/LICENSE @@ -1,3 +1,9 @@ +Modifications for Very Low Power +Copyright(c) 2022 Forward Computing and Control Pty. Ltd. NSW Australia. All right reserved. + This code is not warranted to be fit for any purpose. You may only use it at your own risk. + This code may be freely used for both private and commercial use, subject to the LGPL License below + Provide this copyright is maintained. + Copyright (c) 2015 Arduino LLC. All right reserved. Copyright (c) 2016 Sandeep Mistry All right reserved. diff --git a/README.md b/README.md index aa366c5a..5cc9561b 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,19 @@ -# Arduino Core for Nordic Semiconductor nRF5 based boards - -[![Build Status](https://github.com/sandeepmistry/arduino-nRF5/actions/workflows/compile.yml/badge.svg)](https://github.com/sandeepmistry/arduino-nRF5/actions/workflows/compile.yml) [![OpenCollective](https://opencollective.com/arduino-nRF5/backers/badge.svg)](#backers) +# Modified Arduino Core for Nordic Semiconductor nRF52832 bare modules + +This modified version, pfod_lp_nrf52_2023 V11, only supports nRF52832 boards. +The code and libraries from https://github.com/sandeepmistry/arduino-nRF5 and https://github.com/sandeepmistry/arduino-BLEPeripheral have been modified to allow for very low power BLE on nRF52832 bare modules + +See Easy Very Low Power BLE in Arduino -- 2022 + +Modifications by Matthew Ford + (c)2022 Forward Computing and Control Pty. Ltd. + This code is not warranted to be fit for any purpose. You may only use it at your own risk. + This code may be freely used for both private and commercial use, subject to the LGPL License + Provide this copyright is maintained. + +# Arduino Core for Nordic Semiconductor nRF5 based boards + +[![Build Status](https://travis-ci.org/sandeepmistry/arduino-nRF5.svg?branch=master)](https://travis-ci.org/sandeepmistry/arduino-nRF5) [![OpenCollective](https://opencollective.com/arduino-nRF5/backers/badge.svg)](#backers) [![OpenCollective](https://opencollective.com/arduino-nRF5/sponsors/badge.svg)](#sponsors) @@ -80,9 +93,6 @@ Become a sponsor and get your logo on our README on Github with a link to your s ## Supported boards -### nRF52833 - * [BBC micro:bit v2](https://microbit.org/new-microbit/) - * [Calliope mini V3](https://calliope.cc/calliope-mini-3) ### nRF52 * [Plain nRF52 MCU](https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF52832) * [Nordic Semiconductor nRF52 DK](https://www.nordicsemi.com/eng/Products/Bluetooth-Smart-Bluetooth-low-energy/nRF52-DK) @@ -93,7 +103,6 @@ Become a sponsor and get your logo on our README on Github with a link to your s * [RedBear Nano 2](https://github.com/redbear/nRF5x#ble-nano-2) * [Bluey](https://github.com/electronut/ElectronutLabs-bluey) * [hackaBLE](https://github.com/electronut/ElectronutLabs-hackaBLE) - * [hackaBLE_v2](https://github.com/electronut/ElectronutLabs-hackaBLE) * [DWM1001-DEV](https://www.decawave.com/product/dwm1001-development-board/) ### nRF51 @@ -112,7 +121,6 @@ Become a sponsor and get your logo on our README on Github with a link to your s * [ng-beacon](https://github.com/urish/ng-beacon) * [TinyBLE](https://www.seeedstudio.com/Seeed-Tiny-BLE-BLE-%2B-6DOF-Mbed-Platform-p-2268.html) * [Sino:bit](http://sinobit.org) - * [SeeedArchLink](http://wiki.seeedstudio.com/Arch_Link/) ## Installing @@ -195,7 +203,7 @@ The SD consumes ~5k of Ram + some extra based on actual BLE configuration. * Linux: ```~/Arduino``` * Windows: ```~/Documents/Arduino``` 3. Create a folder named ```hardware```, if it does not exist, and change directories to it - 4. Clone this repo: ```git clone https://github.com/sandeepmistry/arduino-nRF5.git sandeepmistry-github/nRF5``` + 4. Clone this repo: ```git clone https://github.com/sandeepmistry/arduino-nRF5.git sandeepmistry/nRF5``` 5. Restart the Arduino IDE ## BLE diff --git a/boards.txt b/boards.txt index dbd04419..bcc15447 100644 --- a/boards.txt +++ b/boards.txt @@ -19,115 +19,160 @@ menu.chip=Chip menu.softdevice=Softdevice menu.version=Version menu.lfclk=Low Frequency Clock +menu.nfc=NFC/GPIOs menu.board_variant=Board Variant -# nRF52833 variants +# nRF52832 variants ################### -Generic_nRF52833.name=Generic nRF52833 - -Generic_nRF52833.upload.tool=sandeepmistry:openocd -Generic_nRF52833.upload.target=nrf52 -Generic_nRF52833.upload.maximum_size=524288 - -Generic_nRF52833.bootloader.tool=sandeepmistry:openocd - -Generic_nRF52833.build.mcu=cortex-m4 -Generic_nRF52833.build.f_cpu=64000000 -Generic_nRF52833.build.board=GENERIC -Generic_nRF52833.build.core=nRF5 -Generic_nRF52833.build.variant=Generic -Generic_nRF52833.build.variant_system_lib= -Generic_nRF52833.build.extra_flags=-DNRF52833_XXAA -Generic_nRF52833.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -Generic_nRF52833.build.ldscript=nrf52833_xxaa.ld - -Generic_nRF52833.menu.softdevice.none=None -Generic_nRF52833.menu.softdevice.none.softdevice=none -Generic_nRF52833.menu.softdevice.none.softdeviceversion= - -Generic_nRF52833.menu.lfclk.lfxo=Crystal Oscillator -Generic_nRF52833.menu.lfclk.lfxo.build.lfclk_flags=-DUSE_LFXO -Generic_nRF52833.menu.lfclk.lfrc=RC Oscillator -Generic_nRF52833.menu.lfclk.lfrc.build.lfclk_flags=-DUSE_LFRC -Generic_nRF52833.menu.lfclk.lfsynt=Synthesized -Generic_nRF52833.menu.lfclk.lfsynt.build.lfclk_flags=-DUSE_LFSYNT +## Generic nRF52832 modules +generic.name=*Generic nRF52832 (LFC crystal) bare modules via CMSIS-DAP + +generic.upload.tool=sandeepmistry:openocd +generic.upload.protocol=cmsis-dap +generic.upload.target=nrf52 +generic.upload.maximum_size=524288 +generic.upload.setup_command=transport select swd; +generic.upload.use_1200bps_touch=false +generic.upload.wait_for_upload_port=false +generic.upload.native_usb=false + +generic.bootloader.tool=sandeepmistry:openocd + +generic.build.mcu=cortex-m4 +generic.build.f_cpu=16000000 +generic.build.board=nRF52832_BARE_MODULE +generic.build.core=nRF5 +generic.build.variant=nRF52832_BARE_MODULE +generic.build.variant_system_lib= +generic.build.more_flags=-DNRF52 -DARDUINO_GENERIC -DCONFIG_NFCT_PINS_AS_GPIOS -DUSE_LFXO +generic.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +generic.build.ldscript=nrf52_xxaa.ld + +generic.menu.softdevice.s132=S132 +generic.menu.softdevice.s132.softdevice=s132 +generic.menu.softdevice.s132.softdeviceversion=2.0.1 +generic.menu.softdevice.s132.upload.maximum_size=409600 +generic.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 +generic.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld + +generic.menu.lfclk.xo=Crystal Oscillator +generic.menu.lfclk.xo.build.lfclk_flags=-DUSE_LFXO + +generic.menu.nfc.no_nfc=P0.09,P0.10 as GPIOs +generic.menu.nfc.no_nfc.build.nfc_flags=-DCONFIG_NFCT_PINS_AS_GPIOS + +## Generic nRF52832 modules using RC osc for RTC +generic_rc.name=*Generic nRF52832 (LFC RC osc) bare modules via CMSIS-DAP + +generic_rc.upload.tool=sandeepmistry:openocd +generic_rc.upload.protocol=cmsis-dap +generic_rc.upload.target=nrf52 +generic_rc.upload.maximum_size=524288 +generic_rc.upload.setup_command=transport select swd; +generic_rc.upload.use_1200bps_touch=false +generic_rc.upload.wait_for_upload_port=false +generic_rc.upload.native_usb=false + +generic_rc.bootloader.tool=sandeepmistry:openocd + +generic_rc.build.mcu=cortex-m4 +generic_rc.build.f_cpu=16000000 +generic_rc.build.board=nRF52832_BARE_MODULE +generic_rc.build.core=nRF5 +generic_rc.build.variant=nRF52832_BARE_MODULE +generic_rc.build.variant_system_lib= +generic_rc.build.more_flags=-DNRF52 -DARDUINO_GENERIC -DCONFIG_NFCT_PINS_AS_GPIOS -DUSE_LFRC +generic_rc.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +generic_rc.build.ldscript=nrf52_xxaa.ld + +generic_rc.menu.softdevice.s132=S132 +generic_rc.menu.softdevice.s132.softdevice=s132 +generic_rc.menu.softdevice.s132.softdeviceversion=2.0.1 +generic_rc.menu.softdevice.s132.upload.maximum_size=409600 +generic_rc.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 +generic_rc.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld + +generic_rc.menu.lfclk.rc=RC Oscillator +generic_rc.menu.lfclk.rc.build.lfclk_flags=-DUSE_LFRC + +generic_rc.menu.nfc.no_nfc=P0.09,P0.10 as GPIOs +generic_rc.menu.nfc.no_nfc.build.nfc_flags=-DCONFIG_NFCT_PINS_AS_GPIOS + +## BLENano2 +BLENano2.name=*RedBear BLE Nano 2 via CMSIS-DAP -BBCmicrobitV2.name=BBC micro:bit V2 - -BBCmicrobitV2.vid.0=0x0d28 -BBCmicrobitV2.pid.0=0x0204 - -BBCmicrobitV2.upload.tool=sandeepmistry:openocd -BBCmicrobitV2.upload.protocol=cmsis-dap -BBCmicrobitV2.upload.target=nrf52 -BBCmicrobitV2.upload.maximum_size=524288 -BBCmicrobitV2.upload.setup_command=transport select swd; -BBCmicrobitV2.upload.use_1200bps_touch=false -BBCmicrobitV2.upload.wait_for_upload_port=false -BBCmicrobitV2.upload.native_usb=false - -BBCmicrobitV2.bootloader.tool=sandeepmistry:openocd +BLENano2.vid.0=0x0204 +BLENano2.pid.0=0x0d28 -BBCmicrobitV2.build.mcu=cortex-m4 -BBCmicrobitV2.build.f_cpu=64000000 -BBCmicrobitV2.build.board=BBC_MICROBIT_V2 -BBCmicrobitV2.build.core=nRF5 -BBCmicrobitV2.build.variant=BBCmicrobitV2 -BBCmicrobitV2.build.variant_system_lib= -BBCmicrobitV2.build.extra_flags=-DNRF52833_XXAA -BBCmicrobitV2.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -BBCmicrobitV2.build.ldscript=nrf52833_xxaa.ld +BLENano2.upload.tool=sandeepmistry:openocd +BLENano2.upload.protocol=cmsis-dap +BLENano2.upload.target=nrf52 +BLENano2.upload.maximum_size=524288 +BLENano2.upload.setup_command=transport select swd; +BLENano2.upload.use_1200bps_touch=false +BLENano2.upload.wait_for_upload_port=false +BLENano2.upload.native_usb=false -BBCmicrobitV2.build.lfclk_flags=-DUSE_LFSYNT +BLENano2.bootloader.tool=sandeepmistry:openocd -BBCmicrobitV2.menu.softdevice.none=None -BBCmicrobitV2.menu.softdevice.none.softdevice=none -BBCmicrobitV2.menu.softdevice.none.softdeviceversion= +BLENano2.build.mcu=cortex-m4 +BLENano2.build.f_cpu=16000000 +BLENano2.build.board=RB_BLE_NANO_2 +BLENano2.build.core=nRF5 +BLENano2.build.variant=RedBear_BLENano2 +BLENano2.build.variant_system_lib= +BLENano2.build.more_flags=-DNRF52 +BLENano2.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +BLENano2.build.ldscript=nrf52_xxaa.ld +BLENano2.build.lfclk_flags=-DUSE_LFXO -# nRF52832 variants -################### +BLENano2.menu.softdevice.s132=S132 +BLENano2.menu.softdevice.s132.softdevice=s132 +BLENano2.menu.softdevice.s132.softdeviceversion=2.0.1 +BLENano2.menu.softdevice.s132.upload.maximum_size=409600 +BLENano2.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 +BLENano2.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld -Generic_nRF52832.name=Generic nRF52 -Generic_nRF52832.upload.tool=sandeepmistry:openocd -Generic_nRF52832.upload.target=nrf52 -Generic_nRF52832.upload.maximum_size=524288 -Generic_nRF52832.bootloader.tool=sandeepmistry:openocd +## SKYLAB_SKB369 Nano2 Replacement +SKYLAB_SKB369_NANO2_REPLACEMENT.name=*SKYLAB SKB369 Nano2 Replacement via CMSIS-DAP -Generic_nRF52832.build.mcu=cortex-m4 -Generic_nRF52832.build.f_cpu=16000000 -Generic_nRF52832.build.board=GENERIC -Generic_nRF52832.build.core=nRF5 -Generic_nRF52832.build.variant=Generic -Generic_nRF52832.build.variant_system_lib= -Generic_nRF52832.build.extra_flags=-DNRF52 -Generic_nRF52832.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -Generic_nRF52832.build.ldscript=nrf52_xxaa.ld +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.tool=sandeepmistry:openocd +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.protocol=cmsis-dap +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.target=nrf52 +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.maximum_size=524288 +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.setup_command=transport select swd; +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.use_1200bps_touch=false +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.wait_for_upload_port=false +SKYLAB_SKB369_NANO2_REPLACEMENT.upload.native_usb=false -Generic_nRF52832.menu.softdevice.none=None -Generic_nRF52832.menu.softdevice.none.softdevice=none -Generic_nRF52832.menu.softdevice.none.softdeviceversion= +SKYLAB_SKB369_NANO2_REPLACEMENT.bootloader.tool=sandeepmistry:openocd -Generic_nRF52832.menu.softdevice.s132=S132 -Generic_nRF52832.menu.softdevice.s132.softdevice=s132 -Generic_nRF52832.menu.softdevice.s132.softdeviceversion=2.0.1 -Generic_nRF52832.menu.softdevice.s132.upload.maximum_size=409600 -Generic_nRF52832.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 -Generic_nRF52832.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld +SKYLAB_SKB369_NANO2_REPLACEMENT.build.mcu=cortex-m4 +SKYLAB_SKB369_NANO2_REPLACEMENT.build.f_cpu=16000000 +SKYLAB_SKB369_NANO2_REPLACEMENT.build.board=SKYLAB_SKB369_Nano2replacement +SKYLAB_SKB369_NANO2_REPLACEMENT.build.core=nRF5 +SKYLAB_SKB369_NANO2_REPLACEMENT.build.variant=SKYLAB_SKB369_Nano2replacement +SKYLAB_SKB369_NANO2_REPLACEMENT.build.variant_system_lib= +SKYLAB_SKB369_NANO2_REPLACEMENT.build.more_flags=-DNRF52 +SKYLAB_SKB369_NANO2_REPLACEMENT.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 +SKYLAB_SKB369_NANO2_REPLACEMENT.build.ldscript=nrf52_xxaa.ld -Generic_nRF52832.menu.lfclk.lfxo=Crystal Oscillator -Generic_nRF52832.menu.lfclk.lfxo.build.lfclk_flags=-DUSE_LFXO -Generic_nRF52832.menu.lfclk.lfrc=RC Oscillator -Generic_nRF52832.menu.lfclk.lfrc.build.lfclk_flags=-DUSE_LFRC -Generic_nRF52832.menu.lfclk.lfsynt=Synthesized -Generic_nRF52832.menu.lfclk.lfsynt.build.lfclk_flags=-DUSE_LFSYNT +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.lfclk.lfrc.build.lfclk_flags=-DUSE_LFXO +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.softdevice.s132=S132 +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.softdevice.s132.softdevice=s132 +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.softdevice.s132.softdeviceversion=2.0.1 +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.softdevice.s132.upload.maximum_size=409600 +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 +SKYLAB_SKB369_NANO2_REPLACEMENT.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld +## BLUEY bluey.name=Electronut labs bluey bluey.upload.tool=sandeepmistry:openocd @@ -142,14 +187,10 @@ bluey.build.board=ELECTRONUT_BLUEY bluey.build.core=nRF5 bluey.build.variant=bluey bluey.build.variant_system_lib= -bluey.build.extra_flags=-DNRF52 +bluey.build.more_flags=-DNRF52 bluey.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 bluey.build.ldscript=nrf52_xxaa.ld -bluey.menu.softdevice.none=None -bluey.menu.softdevice.none.softdevice=none -bluey.menu.softdevice.none.softdeviceversion= - bluey.menu.softdevice.s132=S132 bluey.menu.softdevice.s132.softdevice=s132 bluey.menu.softdevice.s132.softdeviceversion=2.0.1 @@ -180,14 +221,10 @@ hackaBLE.build.board=ELECTRONUT_HACKABLE hackaBLE.build.core=nRF5 hackaBLE.build.variant=hackaBLE hackaBLE.build.variant_system_lib= -hackaBLE.build.extra_flags=-DNRF52 +hackaBLE.build.more_flags=-DNRF52 hackaBLE.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 hackaBLE.build.ldscript=nrf52_xxaa.ld -hackaBLE.menu.softdevice.none=None -hackaBLE.menu.softdevice.none.softdevice=none -hackaBLE.menu.softdevice.none.softdeviceversion= - hackaBLE.menu.softdevice.s132=S132 hackaBLE.menu.softdevice.s132.softdevice=s132 hackaBLE.menu.softdevice.s132.softdeviceversion=2.0.1 @@ -203,43 +240,7 @@ hackaBLE.menu.lfclk.lfsynt=Synthesized hackaBLE.menu.lfclk.lfsynt.build.lfclk_flags=-DUSE_LFSYNT -hackaBLE_v2.name=Electronut labs hackaBLE_v2 - -hackaBLE_v2.upload.tool=sandeepmistry:openocd -hackaBLE_v2.upload.target=nrf52 -hackaBLE_v2.upload.maximum_size=524288 - -hackaBLE_v2.bootloader.tool=sandeepmistry:openocd - -hackaBLE_v2.build.mcu=cortex-m4 -hackaBLE_v2.build.f_cpu=16000000 -hackaBLE_v2.build.board=ELECTRONUT_hackaBLE_v2 -hackaBLE_v2.build.core=nRF5 -hackaBLE_v2.build.variant=hackaBLE_v2 -hackaBLE_v2.build.variant_system_lib= -hackaBLE_v2.build.extra_flags=-DNRF52 -hackaBLE_v2.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -hackaBLE_v2.build.ldscript=nrf52_xxaa.ld - -hackaBLE_v2.menu.softdevice.none=None -hackaBLE_v2.menu.softdevice.none.softdevice=none -hackaBLE_v2.menu.softdevice.none.softdeviceversion= - -hackaBLE_v2.menu.softdevice.s132=S132 -hackaBLE_v2.menu.softdevice.s132.softdevice=s132 -hackaBLE_v2.menu.softdevice.s132.softdeviceversion=2.0.1 -hackaBLE_v2.menu.softdevice.s132.upload.maximum_size=409600 -hackaBLE_v2.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 -hackaBLE_v2.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld - -hackaBLE_v2.menu.lfclk.lfxo=Crystal Oscillator -hackaBLE_v2.menu.lfclk.lfxo.build.lfclk_flags=-DUSE_LFXO -hackaBLE_v2.menu.lfclk.lfrc=RC Oscillator -hackaBLE_v2.menu.lfclk.lfrc.build.lfclk_flags=-DUSE_LFRC -hackaBLE_v2.menu.lfclk.lfsynt=Synthesized -hackaBLE_v2.menu.lfclk.lfsynt.build.lfclk_flags=-DUSE_LFSYNT - -Blend2.name=RedBear Blend 2 +Blend2.name=*RedBear Blend 2 via CMSIS-DAP Blend2.vid.0=0x0204 Blend2.pid.0=0x0d28 @@ -261,16 +262,12 @@ Blend2.build.board=RB_BLEND_2 Blend2.build.core=nRF5 Blend2.build.variant=RedBear_Blend2 Blend2.build.variant_system_lib= -Blend2.build.extra_flags=-DNRF52 +Blend2.build.more_flags=-DNRF52 Blend2.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 Blend2.build.ldscript=nrf52_xxaa.ld Blend2.build.lfclk_flags=-DUSE_LFXO -Blend2.menu.softdevice.none=None -Blend2.menu.softdevice.none.softdevice=none -Blend2.menu.softdevice.none.softdeviceversion= - Blend2.menu.softdevice.s132=S132 Blend2.menu.softdevice.s132.softdevice=s132 Blend2.menu.softdevice.s132.softdeviceversion=2.0.1 @@ -279,47 +276,9 @@ Blend2.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 Blend2.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld -BLENano2.name=RedBear BLE Nano 2 - -BLENano2.vid.0=0x0204 -BLENano2.pid.0=0x0d28 - -BLENano2.upload.tool=sandeepmistry:openocd -BLENano2.upload.protocol=cmsis-dap -BLENano2.upload.target=nrf52 -BLENano2.upload.maximum_size=524288 -BLENano2.upload.setup_command=transport select swd; -BLENano2.upload.use_1200bps_touch=false -BLENano2.upload.wait_for_upload_port=false -BLENano2.upload.native_usb=false - -BLENano2.bootloader.tool=sandeepmistry:openocd - -BLENano2.build.mcu=cortex-m4 -BLENano2.build.f_cpu=16000000 -BLENano2.build.board=RB_BLE_NANO_2 -BLENano2.build.core=nRF5 -BLENano2.build.variant=RedBear_BLENano2 -BLENano2.build.variant_system_lib= -BLENano2.build.extra_flags=-DNRF52 -BLENano2.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -BLENano2.build.ldscript=nrf52_xxaa.ld - -BLENano2.build.lfclk_flags=-DUSE_LFXO - -BLENano2.menu.softdevice.none=None -BLENano2.menu.softdevice.none.softdevice=none -BLENano2.menu.softdevice.none.softdeviceversion= - -BLENano2.menu.softdevice.s132=S132 -BLENano2.menu.softdevice.s132.softdevice=s132 -BLENano2.menu.softdevice.s132.softdeviceversion=2.0.1 -BLENano2.menu.softdevice.s132.upload.maximum_size=409600 -BLENano2.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 -BLENano2.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld -nRF52DK.name=Nordic Semiconductor nRF52 DK +nRF52DK.name=*Nordic Semiconductor nRF52 DK via jlink nRF52DK.vid.0=0x1366 nRF52DK.pid.0=0x1015 @@ -341,16 +300,12 @@ nRF52DK.build.board=NRF52_DK nRF52DK.build.core=nRF5 nRF52DK.build.variant=nRF52DK nRF52DK.build.variant_system_lib= -nRF52DK.build.extra_flags=-DNRF52 +nRF52DK.build.more_flags=-DNRF52 nRF52DK.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 nRF52DK.build.ldscript=nrf52_xxaa.ld nRF52DK.build.lfclk_flags=-DUSE_LFXO -nRF52DK.menu.softdevice.none=None -nRF52DK.menu.softdevice.none.softdevice=none -nRF52DK.menu.softdevice.none.softdeviceversion= - nRF52DK.menu.softdevice.s132=S132 nRF52DK.menu.softdevice.s132.softdevice=s132 nRF52DK.menu.softdevice.s132.softdeviceversion=2.0.1 @@ -373,16 +328,12 @@ STCT_nRF52_minidev.build.board=STCT_NRF52_minidev STCT_nRF52_minidev.build.core=nRF5 STCT_nRF52_minidev.build.variant=Taida_Century_nRF52_minidev STCT_nRF52_minidev.build.variant_system_lib= -STCT_nRF52_minidev.build.extra_flags=-DNRF52 +STCT_nRF52_minidev.build.more_flags=-DNRF52 STCT_nRF52_minidev.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 STCT_nRF52_minidev.build.ldscript=nrf52_xxaa.ld STCT_nRF52_minidev.build.lfclk_flags=-DUSE_LFXO -STCT_nRF52_minidev.menu.softdevice.none=None -STCT_nRF52_minidev.menu.softdevice.none.softdevice=none -STCT_nRF52_minidev.menu.softdevice.none.softdeviceversion= - STCT_nRF52_minidev.menu.softdevice.s132=S132 STCT_nRF52_minidev.menu.softdevice.s132.softdevice=s132 STCT_nRF52_minidev.menu.softdevice.s132.softdeviceversion=2.0.1 @@ -391,663 +342,8 @@ STCT_nRF52_minidev.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51 STCT_nRF52_minidev.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld -# nRF51 variants -################### -Generic_nRF51822.name=Generic nRF51 - -Generic_nRF51822.upload.tool=sandeepmistry:openocd -Generic_nRF51822.upload.target=nrf51 -Generic_nRF51822.upload.maximum_size=262144 - -Generic_nRF51822.bootloader.tool=sandeepmistry:openocd - -Generic_nRF51822.build.mcu=cortex-m0 -Generic_nRF51822.build.f_cpu=16000000 -Generic_nRF51822.build.board=GENERIC -Generic_nRF51822.build.core=nRF5 -Generic_nRF51822.build.variant=Generic -Generic_nRF51822.build.variant_system_lib= -Generic_nRF51822.build.extra_flags=-DNRF51 -Generic_nRF51822.build.float_flags= -Generic_nRF51822.build.ldscript=nrf51_{build.chip}.ld - -Generic_nRF51822.menu.chip.xxaa=16 kB RAM, 256 kB flash (xxaa) -Generic_nRF51822.menu.chip.xxaa.build.chip=xxaa -Generic_nRF51822.menu.chip.xxac=32 kB RAM, 256 kB flash (xxac) -Generic_nRF51822.menu.chip.xxac.build.chip=xxac - -Generic_nRF51822.menu.softdevice.none=None -Generic_nRF51822.menu.softdevice.none.softdevice=none -Generic_nRF51822.menu.softdevice.none.softdeviceversion= - -Generic_nRF51822.menu.softdevice.s110=S110 -Generic_nRF51822.menu.softdevice.s110.softdevice=s110 -Generic_nRF51822.menu.softdevice.s110.softdeviceversion=8.0.0 -Generic_nRF51822.menu.softdevice.s110.upload.maximum_size=151552 -Generic_nRF51822.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -Generic_nRF51822.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_{build.chip}.ld - -Generic_nRF51822.menu.softdevice.s130=S130 -Generic_nRF51822.menu.softdevice.s130.softdevice=s130 -Generic_nRF51822.menu.softdevice.s130.softdeviceversion=2.0.1 -Generic_nRF51822.menu.softdevice.s130.upload.maximum_size=151552 -Generic_nRF51822.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -Generic_nRF51822.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_{build.chip}.ld - -Generic_nRF51822.menu.lfclk.lfxo=Crystal Oscillator -Generic_nRF51822.menu.lfclk.lfxo.build.lfclk_flags=-DUSE_LFXO -Generic_nRF51822.menu.lfclk.lfrc=RC Oscillator -Generic_nRF51822.menu.lfclk.lfrc.build.lfclk_flags=-DUSE_LFRC -Generic_nRF51822.menu.lfclk.lfsynt=Synthesized -Generic_nRF51822.menu.lfclk.lfsynt.build.lfclk_flags=-DUSE_LFSYNT - -BBCmicrobit.name=BBC micro:bit - -BBCmicrobit.vid.0=0x0d28 -BBCmicrobit.pid.0=0x0204 - -BBCmicrobit.upload.tool=sandeepmistry:openocd -BBCmicrobit.upload.protocol=cmsis-dap -BBCmicrobit.upload.target=nrf51 -BBCmicrobit.upload.maximum_size=262144 -BBCmicrobit.upload.setup_command=transport select swd; -BBCmicrobit.upload.use_1200bps_touch=false -BBCmicrobit.upload.wait_for_upload_port=false -BBCmicrobit.upload.native_usb=false - -BBCmicrobit.bootloader.tool=sandeepmistry:openocd - -BBCmicrobit.build.mcu=cortex-m0 -BBCmicrobit.build.f_cpu=16000000 -BBCmicrobit.build.board=BBC_MICROBIT -BBCmicrobit.build.core=nRF5 -BBCmicrobit.build.variant=BBCmicrobit -BBCmicrobit.build.variant_system_lib= -BBCmicrobit.build.extra_flags=-DNRF51 -BBCmicrobit.build.float_flags= -BBCmicrobit.build.ldscript=nrf51_xxaa.ld - -BBCmicrobit.build.lfclk_flags=-DUSE_LFRC - -BBCmicrobit.menu.softdevice.none=None -BBCmicrobit.menu.softdevice.none.softdevice=none -BBCmicrobit.menu.softdevice.none.softdeviceversion= - -BBCmicrobit.menu.softdevice.s110=S110 -BBCmicrobit.menu.softdevice.s110.softdevice=s110 -BBCmicrobit.menu.softdevice.s110.softdeviceversion=8.0.0 -BBCmicrobit.menu.softdevice.s110.upload.maximum_size=151552 -BBCmicrobit.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -BBCmicrobit.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -BBCmicrobit.menu.softdevice.s130=S130 -BBCmicrobit.menu.softdevice.s130.softdevice=s130 -BBCmicrobit.menu.softdevice.s130.softdeviceversion=2.0.1 -BBCmicrobit.menu.softdevice.s130.upload.maximum_size=151552 -BBCmicrobit.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -BBCmicrobit.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - -CalliopeMini.name=Calliope mini - -CalliopeMini.vid.0=0x0d28 -CalliopeMini.pid.0=0x0204 - -CalliopeMini.upload.tool=sandeepmistry:openocd -CalliopeMini.upload.protocol=cmsis-dap -CalliopeMini.upload.target=nrf51 -CalliopeMini.upload.maximum_size=262144 -CalliopeMini.upload.setup_command=transport select swd; -CalliopeMini.upload.use_1200bps_touch=false -CalliopeMini.upload.wait_for_upload_port=false -CalliopeMini.upload.native_usb=false - -CalliopeMini.bootloader.tool=sandeepmistry:openocd - -CalliopeMini.build.mcu=cortex-m0 -CalliopeMini.build.f_cpu=16000000 -CalliopeMini.build.board=CALLIOPE_MINI -CalliopeMini.build.core=nRF5 -CalliopeMini.build.variant=CalliopeMini -CalliopeMini.build.variant_system_lib= -CalliopeMini.build.extra_flags=-DNRF51 -CalliopeMini.build.float_flags= -CalliopeMini.build.ldscript=nrf51_xxaa.ld - -CalliopeMini.build.lfclk_flags=-DUSE_LFRC - -CalliopeMini.menu.softdevice.none=None -CalliopeMini.menu.softdevice.none.softdevice=none -CalliopeMini.menu.softdevice.none.softdeviceversion= - -CalliopeMini.menu.softdevice.s110=S110 -CalliopeMini.menu.softdevice.s110.softdevice=s110 -CalliopeMini.menu.softdevice.s110.softdeviceversion=8.0.0 -CalliopeMini.menu.softdevice.s110.upload.maximum_size=151552 -CalliopeMini.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -CalliopeMini.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -CalliopeMini.menu.softdevice.s130=S130 -CalliopeMini.menu.softdevice.s130.softdevice=s130 -CalliopeMini.menu.softdevice.s130.softdeviceversion=2.0.1 -CalliopeMini.menu.softdevice.s130.upload.maximum_size=151552 -CalliopeMini.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -CalliopeMini.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - -CalliopeminiV3.name=Calliope mini V3 - -CalliopeminiV3.vid.0=0x0d28 -CalliopeminiV3.pid.0=0x0204 - -CalliopeminiV3.upload.tool=sandeepmistry:openocd -CalliopeminiV3.upload.protocol=cmsis-dap -CalliopeminiV3.upload.target=nrf52 -CalliopeminiV3.upload.maximum_size=524288 -CalliopeminiV3.upload.setup_command=transport select swd; -CalliopeminiV3.upload.use_1200bps_touch=false -CalliopeminiV3.upload.wait_for_upload_port=false -CalliopeminiV3.upload.native_usb=false - -CalliopeminiV3.bootloader.tool=sandeepmistry:openocd - -CalliopeminiV3.build.mcu=cortex-m4 -CalliopeminiV3.build.f_cpu=64000000 -CalliopeminiV3.build.board=CALLIOPE_MINI_V3 -CalliopeminiV3.build.core=nRF5 -CalliopeminiV3.build.variant=CalliopeminiV3 -CalliopeminiV3.build.variant_system_lib= -CalliopeminiV3.build.extra_flags=-DNRF52833_XXAA -CalliopeminiV3.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 -CalliopeminiV3.build.ldscript=nrf52833_xxaa.ld - -CalliopeminiV3.build.lfclk_flags=-DUSE_LFSYNT - -CalliopeminiV3.menu.softdevice.none=None -CalliopeminiV3.menu.softdevice.none.softdevice=none -CalliopeminiV3.menu.softdevice.none.softdeviceversion= - -BluzDK.name=Bluz DK - -BluzDK.upload.tool=sandeepmistry:openocd -BluzDK.upload.target=nrf51 -BluzDK.upload.maximum_size=262144 - -BluzDK.bootloader.tool=sandeepmistry:openocd - -BluzDK.build.mcu=cortex-m0 -BluzDK.build.f_cpu=16000000 -BluzDK.build.board=BLUZ_DK -BluzDK.build.core=nRF5 -BluzDK.build.variant=BluzDK -BluzDK.build.variant_system_lib= -BluzDK.build.extra_flags=-DNRF51 -BluzDK.build.float_flags= -BluzDK.build.ldscript=nrf51_xxac.ld - -BluzDK.build.lfclk_flags=-DUSE_LFXO - -BluzDK.menu.softdevice.none=None -BluzDK.menu.softdevice.none.softdevice=none -BluzDK.menu.softdevice.none.softdeviceversion= - -BluzDK.menu.softdevice.s110=S110 -BluzDK.menu.softdevice.s110.softdevice=s110 -BluzDK.menu.softdevice.s110.softdeviceversion=8.0.0 -BluzDK.menu.softdevice.s110.upload.maximum_size=151552 -BluzDK.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -BluzDK.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxac.ld - -BluzDK.menu.softdevice.s130=S130 -BluzDK.menu.softdevice.s130.softdevice=s130 -BluzDK.menu.softdevice.s130.softdeviceversion=2.0.1 -BluzDK.menu.softdevice.s130.upload.maximum_size=151552 -BluzDK.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -BluzDK.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxac.ld - - -PCA1000X.name=Nordic nRF51X22 Development Kit(PCA1000X) - -PCA1000X.upload.tool=sandeepmistry:openocd -PCA1000X.upload.target=nrf51 -PCA1000X.upload.maximum_size=262144 - -PCA1000X.bootloader.tool=sandeepmistry:openocd - -PCA1000X.build.mcu=cortex-m0 -PCA1000X.build.f_cpu=16000000 -PCA1000X.build.board=PCA1000X -PCA1000X.build.core=nRF5 -PCA1000X.build.variant=PCA1000X -PCA1000X.build.variant_system_lib= -PCA1000X.build.extra_flags=-DNRF51 -D{board.variant} -PCA1000X.build.float_flags= -PCA1000X.build.ldscript=nrf51_xxaa.ld - -PCA1000X.build.lfclk_flags=-DUSE_LFXO - -PCA1000X.upload.tool=sandeepmistry:openocd -PCA1000X.upload.protocol=jlink -PCA1000X.upload.target=nrf51 -PCA1000X.upload.maximum_size=262144 -PCA1000X.upload.setup_command=transport select swd; set WORKAREASIZE 0; - -PCA1000X.menu.board_variant.pca10000=PCA10000 -PCA1000X.menu.board_variant.pca10000.board.variant=PCA10000 -PCA1000X.menu.board_variant.pca10001=PCA10001 -PCA1000X.menu.board_variant.pca10001.board.variant=PCA10001 -PCA1000X.menu.board_variant.nrf6310=PCA1000X (via nRF6310) -PCA1000X.menu.board_variant.nrf6310.board.variant=NRF6310 - -PCA1000X.menu.softdevice.none=None -PCA1000X.menu.softdevice.none.softdevice=none -PCA1000X.menu.softdevice.none.softdeviceversion= - -PCA1000X.menu.softdevice.s110=S110 -PCA1000X.menu.softdevice.s110.softdevice=s110 -PCA1000X.menu.softdevice.s110.softdeviceversion=8.0.0 -PCA1000X.menu.softdevice.s110.upload.maximum_size=151552 -PCA1000X.menu.softdevice.s110.build.extra_flags=-DNRF51 -D{board.variant} -DS110 -DNRF51_S110 -PCA1000X.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -PCA1000X.menu.softdevice.s130=S130 -PCA1000X.menu.softdevice.s130.softdevice=s130 -PCA1000X.menu.softdevice.s130.softdeviceversion=2.0.1 -PCA1000X.menu.softdevice.s130.upload.maximum_size=151552 -PCA1000X.menu.softdevice.s130.build.extra_flags=-DNRF51 -D{board.variant} -DS130 -DNRF51_S130 -PCA1000X.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - -PCA1000X.menu.lfclk.lfxo=Crystal Oscillator -PCA1000X.menu.lfclk.lfxo.build.lfclk_flags=-DUSE_LFXO -PCA1000X.menu.lfclk.lfrc=RC Oscillator -PCA1000X.menu.lfclk.lfrc.build.lfclk_flags=-DUSE_LFRC -PCA1000X.menu.lfclk.lfsynt=Synthesized -PCA1000X.menu.lfclk.lfsynt.build.lfclk_flags=-DUSE_LFSYNT - - -nRF51Dongle.name= Nordic nRF51 Dongle (PCA10031) - -nRF51Dongle.upload.tool=sandeepmistry:openocd -nRF51Dongle.upload.protocol=cmsis-dap -nRF51Dongle.upload.target=nrf51 -nRF51Dongle.upload.maximum_size=262144 -nRF51Dongle.upload.setup_command=transport select swd; - -nRF51Dongle.bootloader.tool=sandeepmistry:openocd - -nRF51Dongle.build.mcu=cortex-m0 -nRF51Dongle.build.f_cpu=16000000 -nRF51Dongle.build.board=GENERIC -nRF51Dongle.build.core=nRF5 -nRF51Dongle.build.variant=nRF51Dongle -nRF51Dongle.build.variant_system_lib= -nRF51Dongle.build.extra_flags=-DNRF51 -nRF51Dongle.build.float_flags= -nRF51Dongle.build.ldscript=nrf51_{build.chip}.ld - -nRF51Dongle.build.lfclk_flags=-DUSE_LFXO - -nRF51Dongle.menu.version.1_1_0=1.1.0 -nRF51Dongle.menu.version.1_1_0.build.chip=xxac - -nRF51Dongle.menu.softdevice.none=None -nRF51Dongle.menu.softdevice.none.softdevice=none -nRF51Dongle.menu.softdevice.none.softdeviceversion= - -nRF51Dongle.menu.softdevice.s110=S110 -nRF51Dongle.menu.softdevice.s110.softdevice=s110 -nRF51Dongle.menu.softdevice.s110.softdeviceversion=8.0.0 -nRF51Dongle.menu.softdevice.s110.upload.maximum_size=151552 -nRF51Dongle.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -nRF51Dongle.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_{build.chip}.ld - -nRF51Dongle.menu.softdevice.s130=S130 -nRF51Dongle.menu.softdevice.s130.softdevice=s130 -nRF51Dongle.menu.softdevice.s130.softdeviceversion=2.0.1 -nRF51Dongle.menu.softdevice.s130.upload.maximum_size=151552 -nRF51Dongle.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -nRF51Dongle.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_{build.chip}.ld - -Beacon_PCA20006.name=Nordic Beacon Kit (PCA20006) - -Beacon_PCA20006.upload.tool=sandeepmistry:openocd -Beacon_PCA20006.upload.target=nrf51 -Beacon_PCA20006.upload.maximum_size=262144 - -Beacon_PCA20006.bootloader.tool=sandeepmistry:openocd - -Beacon_PCA20006.build.mcu=cortex-m0 -Beacon_PCA20006.build.f_cpu=16000000 -Beacon_PCA20006.build.board=BOARD_PCA20006 -Beacon_PCA20006.build.core=nRF5 -Beacon_PCA20006.build.variant=PCA20006 -Beacon_PCA20006.build.variant_system_lib= -Beacon_PCA20006.build.extra_flags=-DNRF51 -Beacon_PCA20006.build.float_flags= -Beacon_PCA20006.build.ldscript=nrf51_xxaa.ld - -Beacon_PCA20006.build.lfclk_flags=-DUSE_LFXO - -Beacon_PCA20006.menu.softdevice.none=None -Beacon_PCA20006.menu.softdevice.none.softdevice=none -Beacon_PCA20006.menu.softdevice.none.softdeviceversion= - -Beacon_PCA20006.menu.softdevice.s110=S110 -Beacon_PCA20006.menu.softdevice.s110.softdevice=s110 -Beacon_PCA20006.menu.softdevice.s110.softdeviceversion=8.0.0 -Beacon_PCA20006.menu.softdevice.s110.upload.maximum_size=151552 -Beacon_PCA20006.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -Beacon_PCA20006.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -Beacon_PCA20006.menu.softdevice.s130=S130 -Beacon_PCA20006.menu.softdevice.s130.softdevice=s130 -Beacon_PCA20006.menu.softdevice.s130.softdeviceversion=2.0.1 -Beacon_PCA20006.menu.softdevice.s130.upload.maximum_size=151552 -Beacon_PCA20006.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -Beacon_PCA20006.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - -TinyBLE.name= TinyBLE - -TinyBLE.upload.tool=sandeepmistry:openocd -TinyBLE.upload.protocol=cmsis-dap - -TinyBLE.upload.target=nrf51 -TinyBLE.upload.maximum_size=262144 -TinyBLE.upload.setup_command=transport select swd; - -TinyBLE.bootloader.tool=sandeepmistry:openocd - -TinyBLE.build.mcu=cortex-m0 -TinyBLE.build.f_cpu=16000000 -TinyBLE.build.board=TINYBLE -TinyBLE.build.core=nRF5 -TinyBLE.build.variant=TinyBLE -TinyBLE.build.variant_system_lib= -TinyBLE.build.extra_flags=-DNRF51 -TinyBLE.build.float_flags= -TinyBLE.build.ldscript=nrf51_xxaa.ld - -TinyBLE.build.lfclk_flags=-DUSE_LFXO - -TinyBLE.menu.softdevice.none=None -TinyBLE.menu.softdevice.none.softdevice=none -TinyBLE.menu.softdevice.none.softdeviceversion= - -TinyBLE.menu.softdevice.s110=S110 -TinyBLE.menu.softdevice.s110.softdevice=s110 -TinyBLE.menu.softdevice.s110.softdeviceversion=8.0.0 -TinyBLE.menu.softdevice.s110.upload.maximum_size=151552 -TinyBLE.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -TinyBLE.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -TinyBLE.menu.softdevice.s130=S130 -TinyBLE.menu.softdevice.s130.softdevice=s130 -TinyBLE.menu.softdevice.s130.softdeviceversion=2.0.1 -TinyBLE.menu.softdevice.s130.upload.maximum_size=151552 -TinyBLE.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -TinyBLE.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - - -OSHChip.name=OSHChip - -OSHChip.upload.tool=sandeepmistry:openocd -OSHChip.upload.target=nrf51 -OSHChip.upload.maximum_size=262144 - -OSHChip.bootloader.tool=sandeepmistry:openocd - -OSHChip.build.mcu=cortex-m0 -OSHChip.build.f_cpu=16000000 -OSHChip.build.board=BLUZ_DK -OSHChip.build.core=nRF5 -OSHChip.build.variant=OSHChip -OSHChip.build.variant_system_lib= -OSHChip.build.extra_flags=-DNRF51 -OSHChip.build.float_flags= -OSHChip.build.ldscript=nrf51_xxac.ld - -OSHChip.build.lfclk_flags=-DUSE_LFRC - -OSHChip.menu.softdevice.none=None -OSHChip.menu.softdevice.none.softdevice=none -OSHChip.menu.softdevice.none.softdeviceversion= - -OSHChip.menu.softdevice.s110=S110 -OSHChip.menu.softdevice.s110.softdevice=s110 -OSHChip.menu.softdevice.s110.softdeviceversion=8.0.0 -OSHChip.menu.softdevice.s110.upload.maximum_size=151552 -OSHChip.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -OSHChip.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxac.ld - -OSHChip.menu.softdevice.s130=S130 -OSHChip.menu.softdevice.s130.softdevice=s130 -OSHChip.menu.softdevice.s130.softdeviceversion=2.0.1 -OSHChip.menu.softdevice.s130.upload.maximum_size=151552 -OSHChip.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -OSHChip.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxac.ld - - -BLENano.name=RedBearLab BLE Nano - -BLENano.upload.tool=sandeepmistry:openocd -BLENano.upload.protocol=cmsis-dap -BLENano.upload.target=nrf51 -BLENano.upload.maximum_size=262144 -BLENano.upload.setup_command=transport select swd; - -BLENano.bootloader.tool=sandeepmistry:openocd - -BLENano.build.mcu=cortex-m0 -BLENano.build.f_cpu=16000000 -BLENano.build.board=BLE_NANO -BLENano.build.core=nRF5 -BLENano.build.variant=BLENano -BLENano.build.variant_system_lib= -BLENano.build.extra_flags=-DNRF51 -BLENano.build.float_flags= -BLENano.build.ldscript=nrf51_{build.chip}.ld - -BLENano.build.lfclk_flags=-DUSE_LFXO - -BLENano.menu.version.1_0=1.0 -BLENano.menu.version.1_0.build.chip=xxaa -BLENano.menu.version.1_5=1.5 -BLENano.menu.version.1_5.build.chip=xxac - -BLENano.menu.softdevice.none=None -BLENano.menu.softdevice.none.softdevice=none -BLENano.menu.softdevice.none.softdeviceversion= - -BLENano.menu.softdevice.s110=S110 -BLENano.menu.softdevice.s110.softdevice=s110 -BLENano.menu.softdevice.s110.softdeviceversion=8.0.0 -BLENano.menu.softdevice.s110.upload.maximum_size=151552 -BLENano.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -BLENano.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_{build.chip}.ld - -BLENano.menu.softdevice.s130=S130 -BLENano.menu.softdevice.s130.softdevice=s130 -BLENano.menu.softdevice.s130.softdeviceversion=2.0.1 -BLENano.menu.softdevice.s130.upload.maximum_size=151552 -BLENano.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -BLENano.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_{build.chip}.ld - - -RedBearLab_nRF51822.name=RedBearLab nRF51822 - -RedBearLab_nRF51822.upload.tool=sandeepmistry:openocd -RedBearLab_nRF51822.upload.protocol=cmsis-dap -RedBearLab_nRF51822.upload.target=nrf51 -RedBearLab_nRF51822.upload.maximum_size=262144 -RedBearLab_nRF51822.upload.setup_command=transport select swd; - -RedBearLab_nRF51822.bootloader.tool=sandeepmistry:openocd - -RedBearLab_nRF51822.build.mcu=cortex-m0 -RedBearLab_nRF51822.build.f_cpu=16000000 -RedBearLab_nRF51822.build.board=REDBEARLAB_NRF51822 -RedBearLab_nRF51822.build.core=nRF5 -RedBearLab_nRF51822.build.variant=RedBearLab_nRF51822 -RedBearLab_nRF51822.build.variant_system_lib= -RedBearLab_nRF51822.build.extra_flags=-DNRF51 -RedBearLab_nRF51822.build.float_flags= -RedBearLab_nRF51822.build.ldscript=nrf51_{build.chip}.ld - -RedBearLab_nRF51822.build.lfclk_flags=-DUSE_LFXO - -RedBearLab_nRF51822.menu.version.1_0=1.0 -RedBearLab_nRF51822.menu.version.1_0.build.chip=xxaa -RedBearLab_nRF51822.menu.version.1_5=1.5 -RedBearLab_nRF51822.menu.version.1_5.build.chip=xxac - -RedBearLab_nRF51822.menu.softdevice.none=None -RedBearLab_nRF51822.menu.softdevice.none.softdevice=none -RedBearLab_nRF51822.menu.softdevice.none.softdeviceversion= - -RedBearLab_nRF51822.menu.softdevice.s110=S110 -RedBearLab_nRF51822.menu.softdevice.s110.softdevice=s110 -RedBearLab_nRF51822.menu.softdevice.s110.softdeviceversion=8.0.0 -RedBearLab_nRF51822.menu.softdevice.s110.upload.maximum_size=151552 -RedBearLab_nRF51822.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -RedBearLab_nRF51822.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_{build.chip}.ld - -RedBearLab_nRF51822.menu.softdevice.s130=S130 -RedBearLab_nRF51822.menu.softdevice.s130.softdevice=s130 -RedBearLab_nRF51822.menu.softdevice.s130.softdeviceversion=2.0.1 -RedBearLab_nRF51822.menu.softdevice.s130.upload.maximum_size=151552 -RedBearLab_nRF51822.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -RedBearLab_nRF51822.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_{build.chip}.ld - - -Waveshare_BLE400.name=Waveshare BLE400 - -Waveshare_BLE400.upload.tool=sandeepmistry:openocd -Waveshare_BLE400.upload.target=nrf51 -Waveshare_BLE400.upload.maximum_size=262144 - -Waveshare_BLE400.bootloader.tool=sandeepmistry:openocd - -Waveshare_BLE400.build.mcu=cortex-m0 -Waveshare_BLE400.build.f_cpu=16000000 -Waveshare_BLE400.build.board=WAVESHARE_BLE400 -Waveshare_BLE400.build.core=nRF5 -Waveshare_BLE400.build.variant=Waveshare_BLE400 -Waveshare_BLE400.build.variant_system_lib= -Waveshare_BLE400.build.extra_flags=-DNRF51 -Waveshare_BLE400.build.float_flags= -Waveshare_BLE400.build.ldscript=nrf51_{build.chip}.ld - -Waveshare_BLE400.build.lfclk_flags=-DUSE_LFXO - -Waveshare_BLE400.menu.chip.xxaa=16 kB RAM, 256 kB flash (xxaa) -Waveshare_BLE400.menu.chip.xxaa.build.chip=xxaa -Waveshare_BLE400.menu.chip.xxac=32 kB RAM, 256 kB flash (xxac) -Waveshare_BLE400.menu.chip.xxac.build.chip=xxac - -Waveshare_BLE400.menu.softdevice.none=None -Waveshare_BLE400.menu.softdevice.none.softdevice=none -Waveshare_BLE400.menu.softdevice.none.softdeviceversion= - -Waveshare_BLE400.menu.softdevice.s110=S110 -Waveshare_BLE400.menu.softdevice.s110.softdevice=s110 -Waveshare_BLE400.menu.softdevice.s110.softdeviceversion=8.0.0 -Waveshare_BLE400.menu.softdevice.s110.upload.maximum_size=151552 -Waveshare_BLE400.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -Waveshare_BLE400.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_{build.chip}.ld - -Waveshare_BLE400.menu.softdevice.s130=S130 -Waveshare_BLE400.menu.softdevice.s130.softdevice=s130 -Waveshare_BLE400.menu.softdevice.s130.softdeviceversion=2.0.1 -Waveshare_BLE400.menu.softdevice.s130.upload.maximum_size=151552 -Waveshare_BLE400.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -Waveshare_BLE400.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_{build.chip}.ld - - -ng_beacon.name=ng-beacon - -ng_beacon.upload.tool=sandeepmistry:openocd -ng_beacon.upload.target=nrf51 -ng_beacon.upload.maximum_size=262144 - -ng_beacon.bootloader.tool=sandeepmistry:openocd - -ng_beacon.build.mcu=cortex-m0 -ng_beacon.build.f_cpu=16000000 -ng_beacon.build.board=NG_BEACON -ng_beacon.build.core=nRF5 -ng_beacon.build.variant=ng-beacon -ng_beacon.build.variant_system_lib= -ng_beacon.build.extra_flags=-DNRF51 -ng_beacon.build.float_flags= -ng_beacon.build.ldscript=nrf51_xxaa.ld - -ng_beacon.build.lfclk_flags=-DUSE_LFRC - -ng_beacon.menu.softdevice.none=None -ng_beacon.menu.softdevice.none.softdevice=none -ng_beacon.menu.softdevice.none.softdeviceversion= - -ng_beacon.menu.softdevice.s110=S110 -ng_beacon.menu.softdevice.s110.softdevice=s110 -ng_beacon.menu.softdevice.s110.softdeviceversion=8.0.0 -ng_beacon.menu.softdevice.s110.upload.maximum_size=151552 -ng_beacon.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -ng_beacon.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -ng_beacon.menu.softdevice.s130=S130 -ng_beacon.menu.softdevice.s130.softdevice=s130 -ng_beacon.menu.softdevice.s130.softdeviceversion=2.0.1 -ng_beacon.menu.softdevice.s130.upload.maximum_size=151552 -ng_beacon.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -ng_beacon.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - - -Sinobit.name=Sino:bit - -Sinobit.vid.0=0x0d28 -Sinobit.pid.0=0x0204 - -Sinobit.upload.tool=sandeepmistry:openocd -Sinobit.upload.protocol=cmsis-dap -Sinobit.upload.target=nrf51 -Sinobit.upload.maximum_size=262144 -Sinobit.upload.setup_command=transport select swd; -Sinobit.upload.use_1200bps_touch=false -Sinobit.upload.wait_for_upload_port=false -Sinobit.upload.native_usb=false - -Sinobit.bootloader.tool=sandeepmistry:openocd - -Sinobit.build.mcu=cortex-m0 -Sinobit.build.f_cpu=16000000 -Sinobit.build.board=SINOBIT -Sinobit.build.core=nRF5 -Sinobit.build.variant=Sinobit -Sinobit.build.variant_system_lib= -Sinobit.build.extra_flags=-DNRF51 -Sinobit.build.float_flags= -Sinobit.build.ldscript=nrf51_xxaa.ld - -Sinobit.build.lfclk_flags=-DUSE_LFRC - -Sinobit.menu.softdevice.none=None -Sinobit.menu.softdevice.none.softdevice=none -Sinobit.menu.softdevice.none.softdeviceversion= - -Sinobit.menu.softdevice.s110=S110 -Sinobit.menu.softdevice.s110.softdevice=s110 -Sinobit.menu.softdevice.s110.softdeviceversion=8.0.0 -Sinobit.menu.softdevice.s110.upload.maximum_size=151552 -Sinobit.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -Sinobit.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -Sinobit.menu.softdevice.s130=S130 -Sinobit.menu.softdevice.s130.softdevice=s130 -Sinobit.menu.softdevice.s130.softdeviceversion=2.0.1 -Sinobit.menu.softdevice.s130.upload.maximum_size=151552 -Sinobit.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -Sinobit.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - -DWM1001-DEV.name=decaWave DWM1001 Module Development Board +DWM1001-DEV.name=*decaWave DWM1001 Module Development Board via jlink DWM1001-DEV.upload.tool=sandeepmistry:openocd DWM1001-DEV.upload.protocol=jlink @@ -1066,15 +362,12 @@ DWM1001-DEV.build.board=DWM1001_DEV DWM1001-DEV.build.core=nRF5 DWM1001-DEV.build.variant=DWM1001-DEV DWM1001-DEV.build.variant_system_lib= -DWM1001-DEV.build.extra_flags=-DNRF52 +DWM1001-DEV.build.more_flags=-DNRF52 DWM1001-DEV.build.float_flags=-mfloat-abi=hard -mfpu=fpv4-sp-d16 DWM1001-DEV.build.ldscript=nrf52_xxaa.ld DWM1001-DEV.build.lfclk_flags=-DUSE_LFXO -DWM1001-DEV.menu.softdevice.none=None -DWM1001-DEV.menu.softdevice.none.softdevice=none -DWM1001-DEV.menu.softdevice.none.softdeviceversion= DWM1001-DEV.menu.softdevice.s132=S132 DWM1001-DEV.menu.softdevice.s132.softdevice=s132 @@ -1082,43 +375,3 @@ DWM1001-DEV.menu.softdevice.s132.softdeviceversion=2.0.1 DWM1001-DEV.menu.softdevice.s132.upload.maximum_size=409600 DWM1001-DEV.menu.softdevice.s132.build.extra_flags=-DNRF52 -DS132 -DNRF51_S132 DWM1001-DEV.menu.softdevice.s132.build.ldscript=armgcc_s132_nrf52832_xxaa.ld - -SeeedArchLink.name=Seeed Arch Link - -SeeedArchLink.upload.tool=sandeepmistry:openocd -SeeedArchLink.upload.target=nrf51 -SeeedArchLink.upload.protocol=cmsis-dap -SeeedArchLink.upload.maximum_size=262144 - -SeeedArchLink.bootloader.tool=sandeepmistry:openocd - -SeeedArchLink.build.mcu=cortex-m0 -SeeedArchLink.build.f_cpu=16000000 -SeeedArchLink.build.board=ARCHLINK -SeeedArchLink.build.core=nRF5 -SeeedArchLink.build.variant=SeeedArchLink -SeeedArchLink.build.variant_system_lib= -SeeedArchLink.build.extra_flags=-DNRF51 -SeeedArchLink.build.float_flags= -SeeedArchLink.build.ldscript=nrf51_xxaa.ld - -SeeedArchLink.build.lfclk_flags=-DUSE_LFXO - -SeeedArchLink.menu.softdevice.none=None -SeeedArchLink.menu.softdevice.none.softdevice=none -SeeedArchLink.menu.softdevice.none.softdeviceversion= - -SeeedArchLink.menu.softdevice.s110=S110 -SeeedArchLink.menu.softdevice.s110.softdevice=s110 -SeeedArchLink.menu.softdevice.s110.softdeviceversion=8.0.0 -SeeedArchLink.menu.softdevice.s110.upload.maximum_size=151552 -SeeedArchLink.menu.softdevice.s110.build.extra_flags=-DNRF51 -DS110 -DNRF51_S110 -SeeedArchLink.menu.softdevice.s110.build.ldscript=armgcc_s110_nrf51822_xxaa.ld - -SeeedArchLink.menu.softdevice.s130=S130 -SeeedArchLink.menu.softdevice.s130.softdevice=s130 -SeeedArchLink.menu.softdevice.s130.softdeviceversion=2.0.1 -SeeedArchLink.menu.softdevice.s130.upload.maximum_size=151552 -SeeedArchLink.menu.softdevice.s130.build.extra_flags=-DNRF51 -DS130 -DNRF51_S130 -SeeedArchLink.menu.softdevice.s130.build.ldscript=armgcc_s130_nrf51822_xxaa.ld - diff --git a/cores/nRF5/Arduino.h b/cores/nRF5/Arduino.h index 87bbcdac..c2d16063 100644 --- a/cores/nRF5/Arduino.h +++ b/cores/nRF5/Arduino.h @@ -7,9 +7,6 @@ #include #include -#include "nrf.h" -#include "nrf_peripherals.h" - typedef bool boolean; typedef uint8_t byte; typedef uint16_t word; @@ -20,12 +17,29 @@ typedef uint16_t word; #include "avr/pgmspace.h" #include "avr/interrupt.h" + #include "itoa.h" +#ifdef __cplusplus +#include "lp_timer.h" +#endif // __cplusplus + #ifdef __cplusplus extern "C"{ #endif // __cplusplus +// put loop() to sleep waiting for trigger and then process trigger when it wakes up +void sleep(); + +// put loop() to sleep +void waitForTrigger(); + +// process any queued triggers +void processTrigger(); + +float getChipTemperature(); // the not very accurate nRF52 on chip temp in 0.25C increments +int32_t getRawChipTemperature(); // == getChipTemperature * 4 + #include "wiring_constants.h" #define clockCyclesPerMicrosecond() ( SystemCoreClock / 1000000L ) @@ -95,23 +109,12 @@ void loop( void ) ; #define bit(b) (1UL << (b)) -#if (GPIO_COUNT == 1) -#define gpioBaseForPin(P) ( NRF_GPIO ) -#define digitalPinToPort(P) ( (NRF_GPIO_Type *) gpioBaseForPin(P) ) -#define digitalPinToPin(P) ( g_ADigitalPinMap[P] ) -#define digitalPinToBitMask(P) ( 1 << digitalPinToPin(P) ) -#elif (GPIO_COUNT == 2) -#define gpioBaseForPin(P) ( (g_ADigitalPinMap[P] & 0x20) ? NRF_P1 : NRF_P0 ) -#define digitalPinToPort(P) ( (NRF_GPIO_Type *) gpioBaseForPin(P) ) -#define digitalPinToPin(P) ( g_ADigitalPinMap[P] & 0x1f ) -#define digitalPinToBitMask(P) ( 1 << digitalPinToPin(P) ) -#else -#error "Unsupported GPIO_COUNT" -#endif - -#define portOutputRegister(port) ( &(port->OUT) ) +#define digitalPinToPort(P) ( &(NRF_GPIO[P]) ) +#define digitalPinToBitMask(P) ( 1 << g_ADigitalPinMap[P] ) +//#define analogInPinToBit(P) ( ) +#define portOutputRegister(port) ( &(port->OUTSET) ) #define portInputRegister(port) ( &(port->IN) ) -#define portModeRegister(port) ( &(port->DIR) ) +#define portModeRegister(port) ( &(port->DIRSET) ) #define digitalPinHasPWM(P) ( true ) /* diff --git a/cores/nRF5/BLEAttribute.cpp b/cores/nRF5/BLEAttribute.cpp new file mode 100644 index 00000000..3cb82eec --- /dev/null +++ b/cores/nRF5/BLEAttribute.cpp @@ -0,0 +1,19 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEAttribute.h" + +BLEAttribute::BLEAttribute(const char* uuid, enum BLEAttributeType type) : + _uuid(uuid), + _type(type) +{ +} + + +const char* BLEAttribute::uuid() const { + return this->_uuid; +} + +enum BLEAttributeType BLEAttribute::type() const { + return this->_type; +} diff --git a/cores/nRF5/BLEAttribute.h b/cores/nRF5/BLEAttribute.h new file mode 100644 index 00000000..7f48d9ec --- /dev/null +++ b/cores/nRF5/BLEAttribute.h @@ -0,0 +1,36 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_ATTRIBUTE_H_ +#define _BLE_ATTRIBUTE_H_ + +enum BLEAttributeType { + BLETypeService = 0x2800, + BLETypeCharacteristic = 0x2803, + BLETypeDescriptor = 0x2900 +}; + +enum BLEProperty { + BLEBroadcast = 0x01, + BLERead = 0x02, + BLEWriteWithoutResponse = 0x04, + BLEWrite = 0x08, + BLENotify = 0x10, + BLEIndicate = 0x20 +}; + +class BLEAttribute +{ + public: + BLEAttribute(const char* uuid, enum BLEAttributeType type); + const char* uuid() const; + // void setuuid(const char* uuid); + + enum BLEAttributeType type() const; + const char* _uuid; + + private: + enum BLEAttributeType _type; +}; + +#endif diff --git a/cores/nRF5/BLEBondStore.cpp b/cores/nRF5/BLEBondStore.cpp new file mode 100644 index 00000000..3862b713 --- /dev/null +++ b/cores/nRF5/BLEBondStore.cpp @@ -0,0 +1,127 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifdef __AVR__ + #include +#elif defined(__RFduino__) +#define FLASH_WAIT_READY { \ + while (NRF_NVMC->READY == NVMC_READY_READY_Busy) {}; \ +} +#elif defined(NRF51) || defined(NRF52) + #include +#else + #warning "BLEBondStore persistent storage not supported on this platform" +#endif + +#include "Arduino.h" + +#include "BLEBondStore.h" + +BLEBondStore::BLEBondStore(int offset) +#if defined(__AVR__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + : _offset(offset) +#elif defined(NRF51) || defined(NRF52) || defined(__RFduino__) + : _flashPageStartAddress((uint32_t *)(NRF_FICR->CODEPAGESIZE * (NRF_FICR->CODESIZE - 1 - (uint32_t)offset))) +#endif +{ +} + +bool BLEBondStore::hasData() { +#if defined(__AVR__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + return (eeprom_read_byte((unsigned char *)this->_offset) == 0x01); +#elif defined(NRF51) || defined(NRF52) || defined(__RFduino__) + return (*this->_flashPageStartAddress != 0xFFFFFFFF); +#else + return false; +#endif +} + +void BLEBondStore::clearData() { +#if defined(__AVR__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + eeprom_write_byte((unsigned char *)this->_offset, 0x00); +#elif defined(NRF51) || defined(NRF52) + int32_t pageNo = (uint32_t)_flashPageStartAddress / NRF_FICR->CODEPAGESIZE; + + while(sd_flash_page_erase(pageNo) == NRF_ERROR_BUSY); +#elif defined(__RFduino__) + + // turn on flash erase enable + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Een << NVMC_CONFIG_WEN_Pos); + + // wait until ready + FLASH_WAIT_READY + + // erase page + NRF_NVMC->ERASEPAGE = (uint32_t)this->_flashPageStartAddress; + + // wait until ready + FLASH_WAIT_READY + + // turn off flash erase enable + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); + + // wait until ready + FLASH_WAIT_READY +#endif +} + +void BLEBondStore::putData(const unsigned char* data, unsigned int offset, unsigned int length) { +#if defined(__AVR__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + eeprom_write_byte((unsigned char *)this->_offset, 0x01); + + for (unsigned int i = 0; i < length; i++) { + eeprom_write_byte((unsigned char *)this->_offset + offset + i + 1, data[i]); + } +#elif defined(NRF51) || defined(NRF52) // ignores offset + this->clearData(); + + while (sd_flash_write((uint32_t*)_flashPageStartAddress, (uint32_t*)data, (uint32_t)length/4) == NRF_ERROR_BUSY); +#elif defined(__RFduino__) // ignores offset + this->clearData(); + + // turn on flash write enable + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos); + + // wait until ready + FLASH_WAIT_READY + + uint32_t *out = this->_flashPageStartAddress; + uint32_t *in = (uint32_t*)data; + + for(unsigned char i = 0; i < length; i += 4) { // assumes length is multiple of 4 + *out = *in; + + out++; + in++; + } + + // wait until ready + FLASH_WAIT_READY + + // turn off flash write enable + NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos); + + // wait until ready + FLASH_WAIT_READY +#endif +} + +void BLEBondStore::getData(unsigned char* data, unsigned int offset, unsigned int length) { +#if defined(__AVR__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + for (unsigned int i = 0; i < length; i++) { + data[i] = eeprom_read_byte((unsigned char *)this->_offset + offset + i + 1); + } +#elif defined(NRF51) || defined(NRF52) || defined(__RFduino__) // ignores offset + uint32_t *in = this->_flashPageStartAddress; + uint32_t *out = (uint32_t*)data; + + offset = offset; + + for(unsigned int i = 0; i < length; i += 4) { // assumes length is multiple of 4 + *out = *in; + + out++; + in++; + } +#endif +} diff --git a/cores/nRF5/BLEBondStore.h b/cores/nRF5/BLEBondStore.h new file mode 100644 index 00000000..66e1b045 --- /dev/null +++ b/cores/nRF5/BLEBondStore.h @@ -0,0 +1,22 @@ +#ifndef _BLE_BOND_STORE_H_ +#define _BLE_BOND_STORE_H_ + +class BLEBondStore +{ + public: + BLEBondStore(int offset = 0); + + bool hasData(); + void clearData(); + void putData(const unsigned char* data, unsigned int offset, unsigned int length); + void getData(unsigned char* data, unsigned int offset, unsigned int length); + + private: +#if defined(__AVR__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + int _offset; +#elif defined(NRF51)|| defined(NRF52) || defined(__RFduino__) + uint32_t* _flashPageStartAddress; +#endif +}; + +#endif diff --git a/cores/nRF5/BLECentral.cpp b/cores/nRF5/BLECentral.cpp new file mode 100644 index 00000000..5d10a14e --- /dev/null +++ b/cores/nRF5/BLECentral.cpp @@ -0,0 +1,61 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" + +#include "BLEPeripheral.h" + +#include "BLECentral.h" +#include "BLEUtil.h" + +BLECentral::BLECentral(BLEPeripheral* peripheral) : + _peripheral(peripheral) +{ + this->clearAddress(); +} + +BLECentral::operator bool() const { + unsigned char zero[6] = {0, 0, 0, 0, 0, 0}; + + return (memcmp(this->_address, zero, sizeof(this->_address)) != 0); +} + +bool BLECentral::operator==(const BLECentral& rhs) const { + return (memcmp(this->_address, rhs._address, sizeof(this->_address)) == 0); +} + +bool BLECentral::operator!=(const BLECentral& rhs) const { + return !(*this == rhs); +} + +bool BLECentral::connected() { + this->poll(); + + return (*this && *this == this->_peripheral->central()); +} + +const char* BLECentral::address() const { + static char address[18]; + + BLEUtil::addressToString(this->_address, address); + + return address; +} + +bool BLECentral::poll() { + return this->_peripheral->poll(); +} + +void BLECentral::disconnect() { + if (this->connected()) { + this->_peripheral->disconnect(); + } +} + +void BLECentral::setAddress(const unsigned char* address) { + memcpy(this->_address, address, sizeof(this->_address)); +} + +void BLECentral::clearAddress() { + memset(this->_address, 0x00, sizeof(this->_address)); +} diff --git a/cores/nRF5/BLECentral.h b/cores/nRF5/BLECentral.h new file mode 100644 index 00000000..bd5e02a3 --- /dev/null +++ b/cores/nRF5/BLECentral.h @@ -0,0 +1,34 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_CENTRAL_H_ +#define _BLE_CENTRAL_H_ + +class BLEPeripheral; + +class BLECentral +{ + friend class BLEPeripheral; + + public: + operator bool() const; + bool operator==(const BLECentral& rhs) const; + bool operator!=(const BLECentral& rhs) const; + + bool connected(); + const char* address() const; + bool poll(); + + void disconnect(); + + protected: + BLECentral(BLEPeripheral* peripheral); + void setAddress(const unsigned char* address); + void clearAddress(); + + private: + BLEPeripheral* _peripheral; + unsigned char _address[6]; +}; + +#endif diff --git a/cores/nRF5/BLECharacteristic.cpp b/cores/nRF5/BLECharacteristic.cpp new file mode 100644 index 00000000..c97927c8 --- /dev/null +++ b/cores/nRF5/BLECharacteristic.cpp @@ -0,0 +1,150 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" + +#include "BLEDeviceLimits.h" + +#include "BLECharacteristic.h" + +BLECharacteristic::BLECharacteristic(const char* uuid, unsigned char properties, unsigned char valueSize) : + BLELocalAttribute(uuid, BLETypeCharacteristic), + _valueSize(min(valueSize, BLE_ATTRIBUTE_MAX_VALUE_LENGTH)), + _value(NULL), + _valueLength(0), + _properties(properties), + _written(false), + _subscribed(false), + _listener(NULL) +{ + memset(this->_eventHandlers, 0x00, sizeof(this->_eventHandlers)); + + if (valueSize) { + this->_value = (unsigned char*)malloc(this->_valueSize); + } +} + +BLECharacteristic::BLECharacteristic(const char* uuid, unsigned char properties, const char* value) : + BLELocalAttribute(uuid, BLETypeCharacteristic), + _valueSize(min(strlen(value), BLE_ATTRIBUTE_MAX_VALUE_LENGTH)), + _value(NULL), + _valueLength(0), + _properties(properties), + _written(false), + _subscribed(false), + _listener(NULL) +{ + memset(this->_eventHandlers, 0x00, sizeof(this->_eventHandlers)); + + this->_value = (unsigned char*)malloc(this->_valueSize); + this->setValue(value); +} + +BLECharacteristic::~BLECharacteristic() { + if (this->_value) { + free(this->_value); + } +} + +unsigned char BLECharacteristic::properties() const { + return this->_properties; +} + +unsigned char BLECharacteristic::valueSize() const { + return this->_valueSize; +} + +unsigned const char* BLECharacteristic::value() const { + return this->_value; +} + +unsigned char BLECharacteristic::valueLength() const { + return this->_valueLength; +} + +bool BLECharacteristic::fixedLength() const { + return false; +} + +unsigned char BLECharacteristic::operator[] (int offset) const { + return this->_value[offset]; +} + +bool BLECharacteristic::setValue(const unsigned char value[], unsigned char length) { + bool success = true; + + this->_valueLength = min(length, this->_valueSize); + + memcpy(this->_value, value, this->_valueLength); + + if (this->_listener) { + success = this->_listener->characteristicValueChanged(*this); + } + + return success; +} + +bool BLECharacteristic::setValue(const char* value) { + return this->setValue((const unsigned char *)value, strlen(value)); +} + +bool BLECharacteristic::broadcast() { + bool success = false; + + if (this->_listener) { + success = this->_listener->broadcastCharacteristic(*this); + } + + return success; +} + +bool BLECharacteristic::written() { + bool written = this->_written; + + this->_written = false; + + return written; +} + +void BLECharacteristic::setValue(BLECentral& central, const unsigned char value[], unsigned char length) { + this->setValue(value, length); + + this->_written = true; + + BLECharacteristicEventHandler eventHandler = this->_eventHandlers[BLEWritten]; + if (eventHandler) { + eventHandler(central, *this); + } +} + +bool BLECharacteristic::subscribed() { + return this->_subscribed; +} + +void BLECharacteristic::setSubscribed(BLECentral& central, bool subscribed) { + this->_subscribed = subscribed; + + BLECharacteristicEventHandler eventHandler = this->_eventHandlers[subscribed ? BLESubscribed : BLEUnsubscribed]; + + if (eventHandler) { + eventHandler(central, *this); + } +} + +bool BLECharacteristic::canNotify() { + return (this->_listener) ? this->_listener->canNotifyCharacteristic(*this) : false; +} + +bool BLECharacteristic::canIndicate() { + return (this->_listener) ? this->_listener->canIndicateCharacteristic(*this) : false; +} + +void BLECharacteristic::setEventHandler(BLECharacteristicEvent event, BLECharacteristicEventHandler eventHandler) { + if (event < sizeof(this->_eventHandlers)) { + this->_eventHandlers[event] = eventHandler; + } +} + +void BLECharacteristic::setValueChangeListener(BLECharacteristicValueChangeListener& listener) { + this->_listener = &listener; +} diff --git a/cores/nRF5/BLECharacteristic.h b/cores/nRF5/BLECharacteristic.h new file mode 100644 index 00000000..d632733b --- /dev/null +++ b/cores/nRF5/BLECharacteristic.h @@ -0,0 +1,80 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_CHARACTERISTIC_H_ +#define _BLE_CHARACTERISTIC_H_ + +#include "BLELocalAttribute.h" + +enum BLECharacteristicEvent { + BLEWritten = 0, + BLESubscribed = 1, + BLEUnsubscribed = 2 +}; + +class BLECentral; +class BLECharacteristic; + +typedef void (*BLECharacteristicEventHandler)(BLECentral& central, BLECharacteristic& characteristic); + +class BLECharacteristicValueChangeListener +{ + public: + virtual bool characteristicValueChanged(BLECharacteristic& /*characteristic*/) { return false; } + virtual bool broadcastCharacteristic(BLECharacteristic& /*characteristic*/) { return false; } + virtual bool canNotifyCharacteristic(BLECharacteristic& /*characteristic*/) { return false; } + virtual bool canIndicateCharacteristic(BLECharacteristic& /*characteristic*/) { return false; } +}; + +class BLECharacteristic : public BLELocalAttribute +{ + friend class BLEPeripheral; + + public: + BLECharacteristic(const char* uuid, unsigned char properties, unsigned char valueSize); + BLECharacteristic(const char* uuid, unsigned char properties, const char* value); + + virtual ~BLECharacteristic(); + + unsigned char properties() const; + + virtual unsigned char valueSize() const; + virtual const unsigned char* value() const; + virtual unsigned char valueLength() const; + virtual unsigned char operator[] (int offset) const; + + virtual bool fixedLength() const; + + virtual bool setValue(const unsigned char value[], unsigned char length); + virtual bool setValue(const char* value); + + bool broadcast(); + + bool written(); + bool subscribed(); + bool canNotify(); + bool canIndicate(); + + void setEventHandler(BLECharacteristicEvent event, BLECharacteristicEventHandler eventHandler); + + protected: + virtual void setValue(BLECentral& central, const unsigned char value[], unsigned char length); + void setSubscribed(BLECentral& central, bool written); + + void setValueChangeListener(BLECharacteristicValueChangeListener& listener); + + unsigned char _valueSize; + unsigned char* _value; + unsigned char _valueLength; + + private: + unsigned char _properties; + + bool _written; + bool _subscribed; + + BLECharacteristicValueChangeListener* _listener; + BLECharacteristicEventHandler _eventHandlers[3]; +}; + +#endif diff --git a/cores/nRF5/BLEConstantCharacteristic.cpp b/cores/nRF5/BLEConstantCharacteristic.cpp new file mode 100644 index 00000000..a543935c --- /dev/null +++ b/cores/nRF5/BLEConstantCharacteristic.cpp @@ -0,0 +1,30 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEConstantCharacteristic.h" + +BLEConstantCharacteristic::BLEConstantCharacteristic(const char* uuid, const unsigned char value[], unsigned char length) : + BLEFixedLengthCharacteristic(uuid, BLERead, (unsigned char)0) +{ + this->_valueLength = this->_valueSize = length; + this->_value = (unsigned char*)value; +} + +BLEConstantCharacteristic::BLEConstantCharacteristic(const char* uuid, const char* value) : + BLEFixedLengthCharacteristic(uuid, BLERead, (unsigned char)0) +{ + this->_valueLength = this->_valueSize = strlen(value); + this->_value = (unsigned char*)value; +} + +BLEConstantCharacteristic::~BLEConstantCharacteristic() { + this->_value = NULL; // null so super destructor doesn't try to free +} + +bool BLEConstantCharacteristic::setValue(const unsigned char /*value*/[], unsigned char /*length*/) { + return false; +} + +bool BLEConstantCharacteristic::setValue(const char* /*value*/) { + return false; +} diff --git a/cores/nRF5/BLEConstantCharacteristic.h b/cores/nRF5/BLEConstantCharacteristic.h new file mode 100644 index 00000000..adcb29cf --- /dev/null +++ b/cores/nRF5/BLEConstantCharacteristic.h @@ -0,0 +1,22 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_CONSTANT_CHARACTERISTIC_H_ +#define _BLE_CONSTANT_CHARACTERISTIC_H_ + +#include "Arduino.h" + +#include "BLEFixedLengthCharacteristic.h" + +class BLEConstantCharacteristic : public BLEFixedLengthCharacteristic { + public: + BLEConstantCharacteristic(const char* uuid, const unsigned char value[], unsigned char length); + BLEConstantCharacteristic(const char* uuid, const char* value); + + virtual ~BLEConstantCharacteristic(); + + virtual bool setValue(const unsigned char value[], unsigned char length); + virtual bool setValue(const char* value); +}; + +#endif diff --git a/cores/nRF5/BLEDescriptor.cpp b/cores/nRF5/BLEDescriptor.cpp new file mode 100644 index 00000000..423278be --- /dev/null +++ b/cores/nRF5/BLEDescriptor.cpp @@ -0,0 +1,37 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" + +#include "BLEDeviceLimits.h" + +#include "BLEDescriptor.h" + +BLEDescriptor::BLEDescriptor(const char* uuid, const unsigned char value[], unsigned char valueLength) : + BLELocalAttribute(uuid, BLETypeDescriptor), + _value(value), + _valueLength(valueLength) +{ +} + +BLEDescriptor::BLEDescriptor(const char* uuid, const char* value) : + BLELocalAttribute(uuid, BLETypeDescriptor), + _value((const unsigned char*)value), + _valueLength(strlen(value)) +{ +} + +BLEDescriptor::~BLEDescriptor() { +} + +const unsigned char* BLEDescriptor::value() const { + return this->_value; +} + +unsigned char BLEDescriptor::valueLength() const { + return this->_valueLength; +} + +unsigned char BLEDescriptor::operator[] (int offset) const { + return this->_value[offset]; +} diff --git a/cores/nRF5/BLEDescriptor.h b/cores/nRF5/BLEDescriptor.h new file mode 100644 index 00000000..e4ae0787 --- /dev/null +++ b/cores/nRF5/BLEDescriptor.h @@ -0,0 +1,27 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_DESCRIPTOR_H_ +#define _BLE_DESCRIPTOR_H_ + +#include "BLELocalAttribute.h" + +class BLEDescriptor : public BLELocalAttribute +{ + public: + BLEDescriptor(const char* uuid, const unsigned char value[], unsigned char valueLength); + BLEDescriptor(const char* uuid, const char* value); + + virtual ~BLEDescriptor(); + + virtual const unsigned char* value() const; + virtual unsigned char valueLength() const; + virtual unsigned char operator[] (int offset) const; + + private: + const char* _uuid; + const unsigned char* _value; + unsigned char _valueLength; +}; + +#endif diff --git a/cores/nRF5/BLEDevice.cpp b/cores/nRF5/BLEDevice.cpp new file mode 100644 index 00000000..50d68531 --- /dev/null +++ b/cores/nRF5/BLEDevice.cpp @@ -0,0 +1,69 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" + +#include "BLEDevice.h" +#include "bleConstants.h" + + +BLEDevice::BLEDevice() : + _advertisingInterval(DEFAULT_ADVERTISING_INTERVAL_ms), + _minimumConnectionInterval(DEFAULT_MIN_CONNECTION_INTERVAL_ms), + _maximumConnectionInterval(DEFAULT_MAX_CONNECTION_INTERVAL_ms), + _slaveLatency(DEFAULT_SLAVE_LATENCY), + _connectable(DEFAULT_CONNECTABLE), + _bondStore(NULL), + _eventListener(NULL), + _scanResponseHandler(NULL) +{ +} + +BLEDevice::~BLEDevice() { +} + +unsigned short BLEDevice::getAdvertisingInterval() { + return _advertisingInterval; // in ms +} + +unsigned short BLEDevice::getMaximumConnectionInterval() { + return _maximumConnectionInterval; // in ms +} + +bool BLEDevice::getConnectable() { + return _connectable; +} + + +void BLEDevice::setEventListener(BLEDeviceEventListener* eventListener) { + this->_eventListener = eventListener; +} + +void BLEDevice::setAdvertisingTimeout(uint16_t timeout_in_secs) { + this->_advertisingTimeout = timeout_in_secs; +} + +void BLEDevice::setAdvertisingInterval(unsigned short advertisingInterval) { + this->_advertisingInterval = advertisingInterval; +} + +void BLEDevice::setConnectionInterval(unsigned short minimumConnectionInterval, unsigned short maximumConnectionInterval) { + if (maximumConnectionInterval < minimumConnectionInterval) { + maximumConnectionInterval = minimumConnectionInterval; + } + + this->_minimumConnectionInterval = minimumConnectionInterval; + this->_maximumConnectionInterval = maximumConnectionInterval; +} + +void BLEDevice::setSlaveLatency(unsigned short slaveLatency) { + this->_slaveLatency = slaveLatency; +} + +void BLEDevice::setConnectable(bool connectable) { + this->_connectable = connectable; +} + +void BLEDevice::setBondStore(BLEBondStore& bondStore) { + this->_bondStore = &bondStore; +} diff --git a/cores/nRF5/BLEDevice.h b/cores/nRF5/BLEDevice.h new file mode 100644 index 00000000..d940845e --- /dev/null +++ b/cores/nRF5/BLEDevice.h @@ -0,0 +1,129 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_DEVICE_H_ +#define _BLE_DEVICE_H_ + +#include "BLEBondStore.h" +#include "BLECharacteristic.h" +#include "BLELocalAttribute.h" +#include "BLERemoteAttribute.h" +#include "BLERemoteCharacteristic.h" +#include "BLERemoteService.h" + +#include "SDK\components\softdevice\s132\headers\ble_gap.h" +/** Scanner response handler. +*/ +typedef void (*ble_scan_response_handler_t) (ble_gap_evt_adv_report_t* report); + +struct BLEEirData +{ + unsigned char length; + unsigned char type; + unsigned char data[BLE_EIR_DATA_MAX_VALUE_LENGTH]; +}; + +class BLEDevice; + +class BLEDeviceEventListener +{ + public: + virtual void BLEDeviceConnected(BLEDevice& /*device*/, const unsigned char* /*address*/) { } + virtual void BLEDeviceDisconnected(BLEDevice& /*device*/) { } + virtual void BLEDeviceBonded(BLEDevice& /*device*/) { } + virtual void BLEDeviceRemoteServicesDiscovered(BLEDevice& /*device*/) { } + + virtual void BLEDeviceCharacteristicValueChanged(BLEDevice& /*device*/, BLECharacteristic& /*characteristic*/, const unsigned char* /*value*/, unsigned char /*valueLength*/) { } + virtual void BLEDeviceCharacteristicSubscribedChanged(BLEDevice& /*device*/, BLECharacteristic& /*characteristic*/, bool /*subscribed*/) { } + + virtual void BLEDeviceRemoteCharacteristicValueChanged(BLEDevice& /*device*/, BLERemoteCharacteristic& /*characteristic*/, const unsigned char* /*value*/, unsigned char /*valueLength*/) { } + + + virtual void BLEDeviceAddressReceived(BLEDevice& /*device*/, const unsigned char* /*address*/) { } + virtual void BLEDeviceTemperatureReceived(BLEDevice& /*device*/, float /*temperature*/) { } + virtual void BLEDeviceBatteryLevelReceived(BLEDevice& /*device*/, float /*batteryLevel*/) { } +}; + + +class BLEDevice +{ + + friend class BLEPeripheral; + + protected: + BLEDevice(); + + + virtual ~BLEDevice(); + + virtual bool startScanning(ble_scan_response_handler_t scanResponseHandler) {return false;} // not supported + virtual bool stopScanning() {return false;} // not supported + // update these while not scanning and then call startScanning() to apply them + virtual void setScanInterval(uint16_t interval, uint16_t window) {} // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms + virtual void setActiveScan(bool enable) {} // Request scan response data, default is false + virtual void setScanTimeout(uint16_t timeout) {}; // 0 = Don't stop scanning after n seconds + + void setEventListener(BLEDeviceEventListener* eventListener); + + void setAdvertisingTimeout(uint16_t timeout_in_secs); // 0 means never timeout + void setAdvertisingInterval(unsigned short advertisingInterval); + void setConnectionInterval(unsigned short minimumConnectionInterval, unsigned short maximumConnectionInterval); + void setSlaveLatency(unsigned short slaveLatency); + void setConnectable(bool connectable); + void setBondStore(BLEBondStore& bondStore); + + virtual void begin(unsigned char /*advertisementDataSize*/, + BLEEirData * /*advertisementData*/, + unsigned char /*scanDataSize*/, + BLEEirData * /*scanData*/, + BLELocalAttribute** /*localAttributes*/, + unsigned char /*numLocalAttributes*/, + BLERemoteAttribute** /*remoteAttributes*/, + unsigned char /*numRemoteAttributes*/) { } + + virtual bool poll() {return true;} + + virtual void end() { } + + virtual bool setTxPower(int /*txPower*/) { return false; } + + virtual void disconnect() { } + + virtual bool updateCharacteristicValue(BLECharacteristic& /*characteristic*/) { return false; } + virtual bool broadcastCharacteristic(BLECharacteristic& /*characteristic*/) { return false; } + virtual bool canNotifyCharacteristic(BLECharacteristic& /*characteristic*/) { return false; } + virtual bool canIndicateCharacteristic(BLECharacteristic& /*characteristic*/) { return false; } + + virtual bool canReadRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool readRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool canWriteRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool writeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/, const unsigned char /*value*/[], unsigned char /*length*/) { return false; } + virtual bool canSubscribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool subscribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool canUnsubscribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool unsubcribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + + virtual void requestAddress() { } + virtual void requestTemperature() { } + virtual void requestBatteryLevel() { } + + public: + virtual bool startAdvertising() {return true;} + unsigned short getAdvertisingInterval(); // in ms + unsigned short getMaximumConnectionInterval(); // in ms + bool getConnectable(); + + protected: + ble_scan_response_handler_t _scanResponseHandler; + unsigned short _advertisingInterval; // in ms + uint16_t _advertisingTimeout; // in seconds 0 to 65535 + unsigned short _minimumConnectionInterval; // in ms + unsigned short _maximumConnectionInterval; // in ms + unsigned short _slaveLatency; + bool _connectable; + + BLEBondStore* _bondStore; + BLEDeviceEventListener* _eventListener; +}; + +#endif diff --git a/cores/nRF5/BLEDeviceLimits.h b/cores/nRF5/BLEDeviceLimits.h new file mode 100644 index 00000000..139878f2 --- /dev/null +++ b/cores/nRF5/BLEDeviceLimits.h @@ -0,0 +1,39 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_LIMITS_H_ +#define _BLE_LIMITS_H_ + +#include + +#ifndef __AVR__ + +#ifndef max +#define max(a,b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif + +#endif + +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + +#define BLE_ADVERTISEMENT_DATA_MAX_VALUE_LENGTH 26 +#define BLE_SCAN_DATA_MAX_VALUE_LENGTH 29 +#define BLE_EIR_DATA_MAX_VALUE_LENGTH 29 +#define BLE_ATTRIBUTE_MAX_VALUE_LENGTH 20 +#define BLE_REMOTE_ATTRIBUTE_MAX_VALUE_LENGTH 22 + +#else + +#define BLE_ADVERTISEMENT_DATA_MAX_VALUE_LENGTH 20 +#define BLE_SCAN_DATA_MAX_VALUE_LENGTH 20 +#define BLE_EIR_DATA_MAX_VALUE_LENGTH 20 +#define BLE_ATTRIBUTE_MAX_VALUE_LENGTH 20 +#define BLE_REMOTE_ATTRIBUTE_MAX_VALUE_LENGTH 22 + +#endif + +#endif diff --git a/cores/nRF5/BLEFixedLengthCharacteristic.cpp b/cores/nRF5/BLEFixedLengthCharacteristic.cpp new file mode 100644 index 00000000..05d7f935 --- /dev/null +++ b/cores/nRF5/BLEFixedLengthCharacteristic.cpp @@ -0,0 +1,19 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEFixedLengthCharacteristic.h" + +BLEFixedLengthCharacteristic::BLEFixedLengthCharacteristic(const char* uuid, unsigned char properties, unsigned char valueSize) : + BLECharacteristic(uuid, properties, valueSize) +{ + this->_valueLength = valueSize; +} + +BLEFixedLengthCharacteristic::BLEFixedLengthCharacteristic(const char* uuid, unsigned char properties, const char* value) : + BLECharacteristic(uuid, properties, value) +{ +} + +bool BLEFixedLengthCharacteristic::fixedLength() const { + return true; +} diff --git a/cores/nRF5/BLEFixedLengthCharacteristic.h b/cores/nRF5/BLEFixedLengthCharacteristic.h new file mode 100644 index 00000000..519c0649 --- /dev/null +++ b/cores/nRF5/BLEFixedLengthCharacteristic.h @@ -0,0 +1,17 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_FIXED_LENGTH_CHARACTERISTIC_H_ +#define _BLE_FIXED_LENGTH_CHARACTERISTIC_H_ + +#include "BLECharacteristic.h" + +class BLEFixedLengthCharacteristic : public BLECharacteristic { + public: + BLEFixedLengthCharacteristic(const char* uuid, unsigned char properties, unsigned char valueSize); + BLEFixedLengthCharacteristic(const char* uuid, unsigned char properties, const char* value); + + virtual bool fixedLength() const; +}; + +#endif diff --git a/cores/nRF5/BLEHID.cpp b/cores/nRF5/BLEHID.cpp new file mode 100644 index 00000000..4adbad44 --- /dev/null +++ b/cores/nRF5/BLEHID.cpp @@ -0,0 +1,46 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEHIDPeripheral.h" + +#include "BLEHID.h" + +unsigned char BLEHID::_numHids = 0; + +BLEHID::BLEHID(const unsigned char* descriptor, unsigned char descriptorLength, unsigned char reportIdOffset) : + _reportId(0), + _descriptor(descriptor), + _descriptorLength(descriptorLength), + _reportIdOffset(reportIdOffset) +{ + _numHids++; +} + +void BLEHID::setReportId(unsigned char reportId) { + this->_reportId = reportId; +} + +unsigned char BLEHID::getDescriptorLength() { + return this->_descriptorLength; +} + +unsigned char BLEHID::getDescriptorValueAtOffset(unsigned char offset) { + if (offset == this->_reportIdOffset && this->_reportIdOffset) { + return this->_reportId; + } else { + return pgm_read_byte_near(&this->_descriptor[offset]); + } +} + +unsigned char BLEHID::numHids() { + return _numHids; +} + +void BLEHID::sendData(BLECharacteristic& characteristic, unsigned char data[], unsigned char length) { + // wait until we can notify + while(!characteristic.canNotify()) { + BLEHIDPeripheral::instance()->poll(); + } + + characteristic.setValue(data, length); +} diff --git a/cores/nRF5/BLEHID.h b/cores/nRF5/BLEHID.h new file mode 100644 index 00000000..fe531e61 --- /dev/null +++ b/cores/nRF5/BLEHID.h @@ -0,0 +1,38 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_HID_H_ +#define _BLE_HID_H_ + +#include "BLELocalAttribute.h" +#include "BLECharacteristic.h" + +class BLEHID +{ + friend class BLEHIDPeripheral; + + public: + BLEHID(const unsigned char* descriptor, unsigned char descriptorLength, unsigned char reportIdOffset); + + unsigned char getDescriptorLength(); + unsigned char getDescriptorValueAtOffset(unsigned char offset); + + protected: + static unsigned char numHids(); + + void sendData(BLECharacteristic& characteristic, unsigned char data[], unsigned char dataLength); + + virtual void setReportId(unsigned char reportId); + virtual unsigned char numAttributes() { return 0; } + virtual BLELocalAttribute** attributes() { return 0; } + + private: + static unsigned char _numHids; + + unsigned char _reportId; + const unsigned char* _descriptor; + unsigned char _descriptorLength; + unsigned char _reportIdOffset; +}; + +#endif diff --git a/cores/nRF5/BLEHIDPeripheral.cpp b/cores/nRF5/BLEHIDPeripheral.cpp new file mode 100644 index 00000000..3b48613b --- /dev/null +++ b/cores/nRF5/BLEHIDPeripheral.cpp @@ -0,0 +1,85 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEHIDPeripheral.h" + +static const PROGMEM unsigned char hidInformationCharacteriticValue[] = { 0x11, 0x01, 0x00, 0x03 }; + +BLEHIDPeripheral* BLEHIDPeripheral::_instance = NULL; + +BLEHIDPeripheral::BLEHIDPeripheral(unsigned char req, unsigned char rdy, unsigned char rst) : + BLEPeripheral(req, rdy, rst), + _bleBondStore(), + + _hidService("1812"), + _hidReportMapCharacteristic(), + _hidInformationCharacteristic("2a4a", hidInformationCharacteriticValue, sizeof(hidInformationCharacteriticValue)), + _hidControlPointCharacteristic("2a4c", BLEWriteWithoutResponse), + + _reportIdOffset(0), + + _hids(NULL), + _numHids(0) +{ + _instance = this; +} + +BLEHIDPeripheral::~BLEHIDPeripheral() { + if (this->_hids) { + free(this->_hids); + } +} + +BLEHIDPeripheral* BLEHIDPeripheral::instance() { + return _instance; +} + +void BLEHIDPeripheral::begin() { + this->setBondStore(this->_bleBondStore); + + this->setAdvertisedServiceUuid(this->_hidService.uuid()); + + this->addAttribute(this->_hidService); + this->addAttribute(this->_hidInformationCharacteristic); + this->addAttribute(this->_hidControlPointCharacteristic); + this->addAttribute(this->_hidReportMapCharacteristic); + + for (int i = 0; i < this->_numHids; i++) { + BLEHID *hid = this->_hids[i]; + + unsigned char numAttributes = hid->numAttributes(); + BLELocalAttribute** attributes = hid->attributes(); + + for (int j = 0; j < numAttributes; j++) { + this->addAttribute(*attributes[j]); + } + } + + this->_hidReportMapCharacteristic.setHids(this->_hids, this->_numHids); + + // begin initialization + BLEPeripheral::begin(); +} + +void BLEHIDPeripheral::clearBondStoreData() { + this->_bleBondStore.clearData(); +} + +void BLEHIDPeripheral::setReportIdOffset(unsigned char reportIdOffset) { + this->_reportIdOffset = reportIdOffset; +} + +bool BLEHIDPeripheral::poll() { + return BLEPeripheral::poll(); +} + +void BLEHIDPeripheral::addHID(BLEHID& hid) { + if (this->_hids == NULL) { + this->_hids = (BLEHID**)malloc(sizeof(BLEHID*) * BLEHID::numHids()); + } + + hid.setReportId(this->_numHids + this->_reportIdOffset); + + this->_hids[this->_numHids] = &hid; + this->_numHids++; +} diff --git a/cores/nRF5/BLEHIDPeripheral.h b/cores/nRF5/BLEHIDPeripheral.h new file mode 100644 index 00000000..ad179d8c --- /dev/null +++ b/cores/nRF5/BLEHIDPeripheral.h @@ -0,0 +1,47 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_HID_PERIPHERAL_H_ +#define _BLE_HID_PERIPHERAL_H_ + +#include "BLEHID.h" +#include "BLEHIDReportMapCharacteristic.h" +#include "BLEPeripheral.h" + +class BLEHIDPeripheral : public BLEPeripheral +{ + friend class BLEHID; + + public: + BLEHIDPeripheral(unsigned char req = BLE_DEFAULT_REQ, unsigned char rdy = BLE_DEFAULT_RDY, unsigned char rst = BLE_DEFAULT_RST); + ~BLEHIDPeripheral(); + + void begin(); + + void clearBondStoreData(); + void setReportIdOffset(unsigned char reportIdOffset); + + bool poll(); + + void addHID(BLEHID& hid); + + protected: + static BLEHIDPeripheral* instance(); + + private: + static BLEHIDPeripheral* _instance; + + BLEBondStore _bleBondStore; + + BLEService _hidService; + BLEHIDReportMapCharacteristic _hidReportMapCharacteristic; + BLEProgmemConstantCharacteristic _hidInformationCharacteristic; + BLEUnsignedCharCharacteristic _hidControlPointCharacteristic; + + unsigned char _reportIdOffset; + + BLEHID** _hids; + unsigned char _numHids; +}; + +#endif diff --git a/cores/nRF5/BLEHIDReportMapCharacteristic.cpp b/cores/nRF5/BLEHIDReportMapCharacteristic.cpp new file mode 100644 index 00000000..e3f10df9 --- /dev/null +++ b/cores/nRF5/BLEHIDReportMapCharacteristic.cpp @@ -0,0 +1,46 @@ +#include "BLEHIDReportMapCharacteristic.h" + +BLEHIDReportMapCharacteristic::BLEHIDReportMapCharacteristic() : + BLEConstantCharacteristic("2a4b", NULL, 0), + _hids(NULL), + _numHids(0) +{ + +} + +unsigned char BLEHIDReportMapCharacteristic::valueSize() const { + unsigned char valueSize = 0; + + for (unsigned char i = 0; i < this->_numHids; i++) { + valueSize += this->_hids[i]->getDescriptorLength(); + } + + return valueSize; +} + +unsigned char BLEHIDReportMapCharacteristic::valueLength() const { + return this->valueSize(); +} + +unsigned char BLEHIDReportMapCharacteristic::operator[] (int offset) const { + unsigned char value = 0x00; + unsigned char totalOffset = 0; + + for (unsigned char i = 0; i < this->_numHids; i++) { + unsigned char descriptorLength = this->_hids[i]->getDescriptorLength(); + + if ((offset >= totalOffset) && (offset < (totalOffset + descriptorLength))) { + value = this->_hids[i]->getDescriptorValueAtOffset(offset - totalOffset); + break; + } + + totalOffset += descriptorLength; + } + + return value; +} + +void BLEHIDReportMapCharacteristic::setHids(BLEHID** hids, unsigned char numHids) { + this->_hids = hids; + this->_numHids = numHids; +} diff --git a/cores/nRF5/BLEHIDReportMapCharacteristic.h b/cores/nRF5/BLEHIDReportMapCharacteristic.h new file mode 100644 index 00000000..80b80e9a --- /dev/null +++ b/cores/nRF5/BLEHIDReportMapCharacteristic.h @@ -0,0 +1,28 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_HID_REPORT_MAP_CHARACTERISTIC_H_ +#define _BLE_HID_REPORT_MAP_CHARACTERISTIC_H_ + +#include "BLEHID.h" +#include "BLEConstantCharacteristic.h" + +class BLEHIDReportMapCharacteristic : public BLEConstantCharacteristic +{ + friend class BLEHID; + + public: + BLEHIDReportMapCharacteristic(); + + virtual unsigned char valueSize() const; + virtual unsigned char valueLength() const; + virtual unsigned char operator[] (int offset) const; + + void setHids(BLEHID** hids, unsigned char numHids); + + private: + BLEHID** _hids; + unsigned char _numHids; +}; + +#endif diff --git a/cores/nRF5/BLEHIDReportReferenceDescriptor.cpp b/cores/nRF5/BLEHIDReportReferenceDescriptor.cpp new file mode 100644 index 00000000..df7349e2 --- /dev/null +++ b/cores/nRF5/BLEHIDReportReferenceDescriptor.cpp @@ -0,0 +1,18 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEHIDReportReferenceDescriptor.h" + +BLEHIDReportReferenceDescriptor::BLEHIDReportReferenceDescriptor(BLEHIDDescriptorType type) : + BLEDescriptor("2908", this->_value, sizeof(_value)) +{ + this->_value[0] = 0x00; + this->_value[1] = type; +} + +BLEHIDReportReferenceDescriptor::~BLEHIDReportReferenceDescriptor() { +} + +void BLEHIDReportReferenceDescriptor::setReportId(unsigned char reportId) { + this->_value[0] = reportId; +} diff --git a/cores/nRF5/BLEHIDReportReferenceDescriptor.h b/cores/nRF5/BLEHIDReportReferenceDescriptor.h new file mode 100644 index 00000000..f7a53de0 --- /dev/null +++ b/cores/nRF5/BLEHIDReportReferenceDescriptor.h @@ -0,0 +1,27 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_HID_REPORT_REFERENCE_DESCRIPTOR_H_ +#define _BLE_HID_REPORT_REFERENCE_DESCRIPTOR_H_ + +#include "BLEDescriptor.h" + +enum BLEHIDDescriptorType { + BLEHIDDescriptorTypeInput = 0x01, + BLEHIDDescriptorTypeOutput = 0x02 +}; + +class BLEHIDReportReferenceDescriptor : public BLEDescriptor +{ + public: + BLEHIDReportReferenceDescriptor(BLEHIDDescriptorType type); + + virtual ~BLEHIDReportReferenceDescriptor(); + + void setReportId(unsigned char reportId); + + private: + unsigned char _value[2]; +}; + +#endif diff --git a/cores/nRF5/BLEKeyboard.cpp b/cores/nRF5/BLEKeyboard.cpp new file mode 100644 index 00000000..af5d9003 --- /dev/null +++ b/cores/nRF5/BLEKeyboard.cpp @@ -0,0 +1,289 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEKeyboard.h" + +static const PROGMEM unsigned char descriptorValue[] = { + // From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidComboC.c + // permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xA1, 0x01, // COLLECTION (Application) + 0x85, 0x00, // REPORT_ID + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x05, 0x07, // USAGE_PAGE (Keyboard)(Key Codes) + 0x19, 0xE0, // USAGE_MINIMUM (Keyboard LeftControl)(224) + 0x29, 0xE7, // USAGE_MAXIMUM (Keyboard Right GUI)(231) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) ; Modifier byte + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) ; Reserved byte +#ifdef USE_LED_REPORT + 0x95, 0x05, // REPORT_COUNT (5) + 0x75, 0x01, // REPORT_SIZE (1) + 0x05, 0x08, // USAGE_PAGE (LEDs) + 0x19, 0x01, // USAGE_MINIMUM (Num Lock) + 0x29, 0x05, // USAGE_MAXIMUM (Kana) + 0x91, 0x02, // OUTPUT (Data,Var,Abs) ; LED report + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x03, // REPORT_SIZE (3) + 0x91, 0x03, // OUTPUT (Cnst,Var,Abs) ; LED report padding +#endif + 0x95, 0x05, // REPORT_COUNT (5) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x26, 0xA4, 0x00, // LOGICAL_MAXIMUM (164) + 0x05, 0x07, // USAGE_PAGE (Keyboard)(Key Codes) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated))(0) + 0x2A, 0xA4, 0x00, // USAGE_MAXIMUM (Keyboard Application)(164) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xC0 // END_COLLECTION +}; + +BLEKeyboard::BLEKeyboard() : + BLEHID(descriptorValue, sizeof(descriptorValue), 7), + _reportCharacteristic("2a4d", BLERead | BLENotify, 8), + _reportReferenceDescriptor(BLEHIDDescriptorTypeInput) +{ + memset(this->_value, 0, sizeof(this->_value)); +} + +size_t BLEKeyboard::write(uint8_t k) { + uint8_t code; + uint8_t modifier; + + this->keyToCodeAndModifier(k, code, modifier); + + return (this->press(code, modifier) && this->release(code, modifier)); +} + +size_t BLEKeyboard::press(uint8_t code, uint8_t modifiers) { + size_t written = 0; + + if (code != 0) { + for (unsigned int i = 2; i < sizeof(this->_value); i++) { + if (this->_value[i] == 0) { + this->_value[0] |= modifiers; + this->_value[i] = code; + + written = 1; + break; + } + } + } else if (modifiers) { + this->_value[0] |= modifiers; + written = 1; + } + + if (written) { + this->sendValue(); + } + + return written; +} + +size_t BLEKeyboard::release(uint8_t code, uint8_t modifiers) { + size_t cleared = 0; + + if (code != 0) { + for (unsigned int i = 2; i < sizeof(this->_value); i++) { + if (this->_value[i] == code) { + this->_value[0] &= ~modifiers; + this->_value[i] = 0; + + cleared = 1; + break; + } + } + } else if (modifiers) { + this->_value[0] &= ~modifiers; + cleared = 1; + } + + if (cleared) { + this->sendValue(); + } + + return cleared; +} + +void BLEKeyboard::releaseAll(void) { + memset(this->_value, 0, sizeof(this->_value)); + + this->sendValue(); +} + +void BLEKeyboard::setReportId(unsigned char reportId) { + BLEHID::setReportId(reportId); + + this->_reportReferenceDescriptor.setReportId(reportId); +} + +unsigned char BLEKeyboard::numAttributes() { + return 2; +} + +BLELocalAttribute** BLEKeyboard::attributes() { + static BLELocalAttribute* attributes[2]; + + attributes[0] = &this->_reportCharacteristic; + attributes[1] = &this->_reportReferenceDescriptor; + + return attributes; +} + +void BLEKeyboard::sendValue() { + BLEHID::sendData(this->_reportCharacteristic, this->_value, sizeof(this->_value)); +} + + +#define SHIFT 0x80 + +static const PROGMEM unsigned char asciiMap[] = { + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + KEYCODE_BACKSPACE, // '\b' + KEYCODE_TAB, // '\t' + KEYCODE_ENTER, // '\n' + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + KEYCODE_SPACE, // ' ' + 0x1e | SHIFT, // '!' + 0x34 | SHIFT, // '"' + 0x20 | SHIFT, // '#' + 0x21 | SHIFT, // '$' + 0x22 | SHIFT, // '%' + 0x24 | SHIFT, // '&' + 0x34, // ''' + 0x26 | SHIFT, // '(' + 0x27 | SHIFT, // ')' + 0x25 | SHIFT, // '*' + 0x2e | SHIFT, // '+' + KEYCODE_COMMA, // ',' + KEYCODE_MINUS, // '-' + KEYCODE_PERIOD, // '.' + KEYCODE_SLASH, // '/' + KEYCODE_0, // '0' + KEYCODE_1, // '1' + KEYCODE_2, // '2' + KEYCODE_3, // '3' + KEYCODE_4, // '4' + KEYCODE_5, // '5' + KEYCODE_6, // '6' + KEYCODE_7, // '7' + KEYCODE_8, // '8' + KEYCODE_9, // '9' + 0x33 | SHIFT, // ':' + 0x33, // ';' + 0x36 | SHIFT, // '<' + KEYCODE_EQUAL, // '=' + 0x37 | SHIFT, // '>' + 0x38 | SHIFT, // '?' + 0x1f | SHIFT, // '@' + KEYCODE_A | SHIFT, // 'A' + KEYCODE_B | SHIFT, // 'B' + KEYCODE_C | SHIFT, // 'C' + KEYCODE_D | SHIFT, // 'D' + KEYCODE_E | SHIFT, // 'E' + KEYCODE_F | SHIFT, // 'F' + KEYCODE_G | SHIFT, // 'G' + KEYCODE_H | SHIFT, // 'H' + KEYCODE_I | SHIFT, // 'I' + KEYCODE_J | SHIFT, // 'J' + KEYCODE_K | SHIFT, // 'K' + KEYCODE_L | SHIFT, // 'L' + KEYCODE_M | SHIFT, // 'M' + KEYCODE_N | SHIFT, // 'N' + KEYCODE_O | SHIFT, // 'O' + KEYCODE_P | SHIFT, // 'P' + KEYCODE_Q | SHIFT, // 'Q' + KEYCODE_R | SHIFT, // 'R' + KEYCODE_S | SHIFT, // 'S' + KEYCODE_T | SHIFT, // 'T' + KEYCODE_U | SHIFT, // 'U' + KEYCODE_V | SHIFT, // 'V' + KEYCODE_W | SHIFT, // 'W' + KEYCODE_X | SHIFT, // 'X' + KEYCODE_Y | SHIFT, // 'Y' + KEYCODE_Z | SHIFT, // 'Z' + KEYCODE_SQBRAK_LEFT, // '[' + KEYCODE_BACKSLASH, // '\' + KEYCODE_SQBRAK_RIGHT, // ']' + 0x23 | SHIFT, // '^' + 0x2d | SHIFT, // '_' + 0x35, // '`' + KEYCODE_A, // 'a' + KEYCODE_B, // 'b' + KEYCODE_C, // 'c' + KEYCODE_D, // 'd' + KEYCODE_E, // 'e' + KEYCODE_F, // 'f' + KEYCODE_G, // 'g' + KEYCODE_H, // 'h' + KEYCODE_I, // 'i' + KEYCODE_J, // 'j' + KEYCODE_K, // 'k' + KEYCODE_L, // 'l' + KEYCODE_M, // 'm' + KEYCODE_N, // 'n' + KEYCODE_O, // 'o' + KEYCODE_P, // 'p' + KEYCODE_Q, // 'q' + KEYCODE_R, // 'r' + KEYCODE_S, // 's' + KEYCODE_T, // 't' + KEYCODE_U, // 'u' + KEYCODE_V, // 'v' + KEYCODE_W, // 'w' + KEYCODE_X, // 'x' + KEYCODE_Y, // 'y' + KEYCODE_Z, // 'z' + 0x2f | SHIFT, // '{' + 0x31 | SHIFT, // '|' + 0x30 | SHIFT, // '}' + 0x35 | SHIFT, // '~' + 0x0 +}; + +void BLEKeyboard::keyToCodeAndModifier(uint8_t k, uint8_t& code, uint8_t& modifier) { + code = 0; + modifier = 0; + + if (k < 128) { + code = pgm_read_byte(asciiMap + k); + + if (code & 0x80) { + modifier = KEYCODE_MOD_LEFT_SHIFT; + code &= 0x7f; + } + } +} diff --git a/cores/nRF5/BLEKeyboard.h b/cores/nRF5/BLEKeyboard.h new file mode 100644 index 00000000..617e3512 --- /dev/null +++ b/cores/nRF5/BLEKeyboard.h @@ -0,0 +1,140 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_KEYBOARD_H_ +#define _BLE_KEYBOARD_H_ + +#include "Arduino.h" + +#include "BLECharacteristic.h" +#include "BLEHIDReportReferenceDescriptor.h" +#include "BLEHID.h" + +// From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidCombo.h +// permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + +// LED state masks +#define KB_LED_NUM 0x01 +#define KB_LED_CAPS 0x02 +#define KB_LED_SCROLL 0x04 + +// some convenience definitions for modifier keys +#define KEYCODE_MOD_LEFT_CONTROL 0x01 +#define KEYCODE_MOD_LEFT_SHIFT 0x02 +#define KEYCODE_MOD_LEFT_ALT 0x04 +#define KEYCODE_MOD_LEFT_GUI 0x08 +#define KEYCODE_MOD_RIGHT_CONTROL 0x10 +#define KEYCODE_MOD_RIGHT_SHIFT 0x20 +#define KEYCODE_MOD_RIGHT_ALT 0x40 +#define KEYCODE_MOD_RIGHT_GUI 0x80 + +// some more keycodes +#define KEYCODE_LEFT_CONTROL 0xE0 +#define KEYCODE_LEFT_SHIFT 0xE1 +#define KEYCODE_LEFT_ALT 0xE2 +#define KEYCODE_LEFT_GUI 0xE3 +#define KEYCODE_RIGHT_CONTROL 0xE4 +#define KEYCODE_RIGHT_SHIFT 0xE5 +#define KEYCODE_RIGHT_ALT 0xE6 +#define KEYCODE_RIGHT_GUI 0xE7 +#define KEYCODE_1 0x1E +#define KEYCODE_2 0x1F +#define KEYCODE_3 0x20 +#define KEYCODE_4 0x21 +#define KEYCODE_5 0x22 +#define KEYCODE_6 0x23 +#define KEYCODE_7 0x24 +#define KEYCODE_8 0x25 +#define KEYCODE_9 0x26 +#define KEYCODE_0 0x27 +#define KEYCODE_A 0x04 +#define KEYCODE_B 0x05 +#define KEYCODE_C 0x06 +#define KEYCODE_D 0x07 +#define KEYCODE_E 0x08 +#define KEYCODE_F 0x09 +#define KEYCODE_G 0x0A +#define KEYCODE_H 0x0B +#define KEYCODE_I 0x0C +#define KEYCODE_J 0x0D +#define KEYCODE_K 0x0E +#define KEYCODE_L 0x0F +#define KEYCODE_M 0x10 +#define KEYCODE_N 0x11 +#define KEYCODE_O 0x12 +#define KEYCODE_P 0x13 +#define KEYCODE_Q 0x14 +#define KEYCODE_R 0x15 +#define KEYCODE_S 0x16 +#define KEYCODE_T 0x17 +#define KEYCODE_U 0x18 +#define KEYCODE_V 0x19 +#define KEYCODE_W 0x1A +#define KEYCODE_X 0x1B +#define KEYCODE_Y 0x1C +#define KEYCODE_Z 0x1D +#define KEYCODE_COMMA 0x36 +#define KEYCODE_PERIOD 0x37 +#define KEYCODE_MINUS 0x2D +#define KEYCODE_EQUAL 0x2E +#define KEYCODE_BACKSLASH 0x31 +#define KEYCODE_SQBRAK_LEFT 0x2F +#define KEYCODE_SQBRAK_RIGHT 0x30 +#define KEYCODE_SLASH 0x38 +#define KEYCODE_F1 0x3A +#define KEYCODE_F2 0x3B +#define KEYCODE_F3 0x3C +#define KEYCODE_F4 0x3D +#define KEYCODE_F5 0x3E +#define KEYCODE_F6 0x3F +#define KEYCODE_F7 0x40 +#define KEYCODE_F8 0x41 +#define KEYCODE_F9 0x42 +#define KEYCODE_F10 0x43 +#define KEYCODE_F11 0x44 +#define KEYCODE_F12 0x45 +#define KEYCODE_APP 0x65 +#define KEYCODE_ENTER 0x28 +#define KEYCODE_BACKSPACE 0x2A +#define KEYCODE_ESC 0x29 +#define KEYCODE_TAB 0x2B +#define KEYCODE_SPACE 0x2C +#define KEYCODE_INSERT 0x49 +#define KEYCODE_HOME 0x4A +#define KEYCODE_PAGE_UP 0x4B +#define KEYCODE_DELETE 0x4C +#define KEYCODE_END 0x4D +#define KEYCODE_PAGE_DOWN 0x4E +#define KEYCODE_PRINTSCREEN 0x46 +#define KEYCODE_ARROW_RIGHT 0x4F +#define KEYCODE_ARROW_LEFT 0x50 +#define KEYCODE_ARROW_DOWN 0x51 +#define KEYCODE_ARROW_UP 0x52 + +class BLEKeyboard : public BLEHID, public Print +{ + public: + BLEKeyboard(); + + virtual size_t write(uint8_t k); + virtual size_t press(uint8_t keycode, uint8_t modifiers = 0); + virtual size_t release(uint8_t keycode, uint8_t modifiers = 0); + virtual void releaseAll(); + + protected: + virtual void setReportId(unsigned char reportId); + virtual unsigned char numAttributes(); + virtual BLELocalAttribute** attributes(); + + private: + void sendValue(); + void keyToCodeAndModifier(uint8_t k, uint8_t& code, uint8_t& modifier); + + private: + BLECharacteristic _reportCharacteristic; + BLEHIDReportReferenceDescriptor _reportReferenceDescriptor; + + unsigned char _value[8]; +}; + +#endif diff --git a/cores/nRF5/BLELocalAttribute.cpp b/cores/nRF5/BLELocalAttribute.cpp new file mode 100644 index 00000000..fd061097 --- /dev/null +++ b/cores/nRF5/BLELocalAttribute.cpp @@ -0,0 +1,16 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLELocalAttribute.h" + +unsigned char BLELocalAttribute::_numAttributes = 0; + +BLELocalAttribute::BLELocalAttribute(const char* uuid, enum BLEAttributeType type) : + BLEAttribute(uuid, type) +{ + _numAttributes++; +} + +unsigned char BLELocalAttribute::numAttributes() { + return _numAttributes; +} diff --git a/cores/nRF5/BLELocalAttribute.h b/cores/nRF5/BLELocalAttribute.h new file mode 100644 index 00000000..19dbe38b --- /dev/null +++ b/cores/nRF5/BLELocalAttribute.h @@ -0,0 +1,23 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_LOCAL_ATTRIBUTE_H_ +#define _BLE_LOCAL_ATTRIBUTE_H_ + +#include "BLEAttribute.h" + +class BLELocalAttribute : public BLEAttribute +{ + friend class BLEPeripheral; + + public: + BLELocalAttribute(const char* uuid, enum BLEAttributeType type); + + protected: + static unsigned char numAttributes(); + + private: + static unsigned char _numAttributes; +}; + +#endif diff --git a/cores/nRF5/BLEMouse.cpp b/cores/nRF5/BLEMouse.cpp new file mode 100644 index 00000000..297a8e45 --- /dev/null +++ b/cores/nRF5/BLEMouse.cpp @@ -0,0 +1,97 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEMouse.h" + +static const PROGMEM unsigned char descriptorValue[] = { + // From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidComboC.c + // permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xa1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + 0xA1, 0x00, // COLLECTION (Physical) + 0x85, 0x00, // REPORT_ID + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM + 0x29, 0x03, // USAGE_MAXIMUM + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x03, // INPUT (Const,Var,Abs) + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7F, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x02, // REPORT_COUNT (2) + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xC0, // END_COLLECTION + 0xC0 // END COLLECTION +}; + +BLEMouse::BLEMouse() : + BLEHID(descriptorValue, sizeof(descriptorValue), 11), + _reportCharacteristic("2a4d", BLERead | BLENotify, 4), + _reportReferenceDescriptor(BLEHIDDescriptorTypeInput), + _button(0) +{ +} + +void BLEMouse::click(uint8_t b) { + this->press(b); + this->release(b); +} + +void BLEMouse::move(signed char x, signed char y, signed char wheel) { + unsigned char mouseMove[4]= { 0x00, 0x00, 0x00, 0x00 }; + + // send key code + mouseMove[0] = this->_button; + mouseMove[1] = x; + mouseMove[2] = y; + mouseMove[3] = wheel; + + this->sendData(this->_reportCharacteristic, mouseMove, sizeof(mouseMove)); +} + +void BLEMouse::press(uint8_t b) { + this->_button |= b; + + this->move(0, 0, 0); +} + +void BLEMouse::release(uint8_t b) { + this->_button &= ~b; + + this->move(0, 0, 0); +} + +bool BLEMouse::isPressed(uint8_t b) { + return ((this->_button & b) != 0); +} + +void BLEMouse::setReportId(unsigned char reportId) { + BLEHID::setReportId(reportId); + + this->_reportReferenceDescriptor.setReportId(reportId); +} + +unsigned char BLEMouse::numAttributes() { + return 2; +} + +BLELocalAttribute** BLEMouse::attributes() { + static BLELocalAttribute* attributes[2]; + + attributes[0] = &this->_reportCharacteristic; + attributes[1] = &this->_reportReferenceDescriptor; + + return attributes; +} diff --git a/cores/nRF5/BLEMouse.h b/cores/nRF5/BLEMouse.h new file mode 100644 index 00000000..5b1b57bc --- /dev/null +++ b/cores/nRF5/BLEMouse.h @@ -0,0 +1,44 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_MOUSE_H_ +#define _BLE_MOUSE_H_ + +#include "Arduino.h" + +#include "BLECharacteristic.h" +#include "BLEHIDReportReferenceDescriptor.h" +#include "BLEHID.h" + +// From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidCombo.h +// permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + +// use these masks with the "move" function +#define MOUSEBTN_LEFT_MASK 0x01 +#define MOUSEBTN_RIGHT_MASK 0x02 +#define MOUSEBTN_MIDDLE_MASK 0x04 + +class BLEMouse : public BLEHID +{ + public: + BLEMouse(); + + void click(uint8_t b = MOUSEBTN_LEFT_MASK); + void move(signed char x, signed char y, signed char wheel = 0); + void press(uint8_t b = MOUSEBTN_LEFT_MASK); + void release(uint8_t b = MOUSEBTN_LEFT_MASK); + bool isPressed(uint8_t b = MOUSEBTN_LEFT_MASK); + + protected: + virtual void setReportId(unsigned char reportId); + virtual unsigned char numAttributes(); + virtual BLELocalAttribute** attributes(); + + private: + BLECharacteristic _reportCharacteristic; + BLEHIDReportReferenceDescriptor _reportReferenceDescriptor; + + unsigned char _button; +}; + +#endif diff --git a/cores/nRF5/BLEMultimedia.cpp b/cores/nRF5/BLEMultimedia.cpp new file mode 100644 index 00000000..ade37d8e --- /dev/null +++ b/cores/nRF5/BLEMultimedia.cpp @@ -0,0 +1,65 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEMultimedia.h" + +static const PROGMEM unsigned char descriptorValue[] = { + // From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidComboC.c + // permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + + // this second multimedia key report is what handles the multimedia keys + 0x05, 0x0C, // USAGE_PAGE (Consumer Devices) + 0x09, 0x01, // USAGE (Consumer Control) + 0xA1, 0x01, // COLLECTION (Application) + 0x85, 0x00, // REPORT_ID + 0x19, 0x00, // USAGE_MINIMUM (Unassigned) + 0x2A, 0x3C, 0x02, // USAGE_MAXIMUM + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x26, 0x3C, 0x02, // LOGICAL_MAXIMUM + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x10, // REPORT_SIZE (16) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xC0 // END_COLLECTION +}; + +BLEMultimedia::BLEMultimedia() : + BLEHID(descriptorValue, sizeof(descriptorValue), 7), + _reportCharacteristic("2a4d", BLERead | BLENotify, 2), + _reportReferenceDescriptor(BLEHIDDescriptorTypeInput) +{ +} + +size_t BLEMultimedia::write(uint8_t k) { + uint8_t multimediaKeyPress[2]= { 0x00, 0x00 }; + + // send key code + multimediaKeyPress[0] = k; + + for (int i = 0; i < 2; i++) { + this->sendData(this->_reportCharacteristic, multimediaKeyPress, sizeof(multimediaKeyPress)); + + // send cleared code + multimediaKeyPress[0] = 0x00; + } + + return 1; +} + +void BLEMultimedia::setReportId(unsigned char reportId) { + BLEHID::setReportId(reportId); + + this->_reportReferenceDescriptor.setReportId(reportId); +} + +unsigned char BLEMultimedia::numAttributes() { + return 2; +} + +BLELocalAttribute** BLEMultimedia::attributes() { + static BLELocalAttribute* attributes[2]; + + attributes[0] = &this->_reportCharacteristic; + attributes[1] = &this->_reportReferenceDescriptor; + + return attributes; +} diff --git a/cores/nRF5/BLEMultimedia.h b/cores/nRF5/BLEMultimedia.h new file mode 100644 index 00000000..3fc15e04 --- /dev/null +++ b/cores/nRF5/BLEMultimedia.h @@ -0,0 +1,58 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_MULTIMEDIA_H_ +#define _BLE_MULTIMEDIA_H_ + +#include "Arduino.h" + +#include "BLECharacteristic.h" +#include "BLEHIDReportReferenceDescriptor.h" +#include "BLEHID.h" + +// From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidCombo.h +// permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + +// multimedia keys +#define MMKEY_KB_VOL_UP 0x80 // do not use +#define MMKEY_KB_VOL_DOWN 0x81 // do not use +#define MMKEY_VOL_UP 0xE9 +#define MMKEY_VOL_DOWN 0xEA +#define MMKEY_SCAN_NEXT_TRACK 0xB5 +#define MMKEY_SCAN_PREV_TRACK 0xB6 +#define MMKEY_STOP 0xB7 +#define MMKEY_PLAYPAUSE 0xCD +#define MMKEY_MUTE 0xE2 +#define MMKEY_BASSBOOST 0xE5 +#define MMKEY_LOUDNESS 0xE7 +#define MMKEY_KB_EXECUTE 0x74 +#define MMKEY_KB_HELP 0x75 +#define MMKEY_KB_MENU 0x76 +#define MMKEY_KB_SELECT 0x77 +#define MMKEY_KB_STOP 0x78 +#define MMKEY_KB_AGAIN 0x79 +#define MMKEY_KB_UNDO 0x7A +#define MMKEY_KB_CUT 0x7B +#define MMKEY_KB_COPY 0x7C +#define MMKEY_KB_PASTE 0x7D +#define MMKEY_KB_FIND 0x7E +#define MMKEY_KB_MUTE 0x7F // do not use + +class BLEMultimedia : public BLEHID +{ + public: + BLEMultimedia(); + + size_t write(uint8_t k); + + protected: + virtual void setReportId(unsigned char reportId); + virtual unsigned char numAttributes(); + virtual BLELocalAttribute** attributes(); + + private: + BLECharacteristic _reportCharacteristic; + BLEHIDReportReferenceDescriptor _reportReferenceDescriptor; +}; + +#endif diff --git a/cores/nRF5/BLEPeripheral.cpp b/cores/nRF5/BLEPeripheral.cpp new file mode 100644 index 00000000..a51ea1d6 --- /dev/null +++ b/cores/nRF5/BLEPeripheral.cpp @@ -0,0 +1,622 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEUuid.h" + +#include "BLEDeviceLimits.h" +#include "BLEUtil.h" + +#include "BLEPeripheral.h" + +//#define BLE_PERIPHERAL_DEBUG + +#define DEFAULT_DEVICE_NAME "Arduino" +#define DEFAULT_APPEARANCE 0x0000 + + +#ifdef __cplusplus +extern "C" void BLEPeripheralInstancePoll() { + if (BLEPeripheral::pollInstance != NULL) { + BLEPeripheral::pollInstance->poll(); + } +} +#endif // #ifdef __cplusplus + +BLEPeripheral* BLEPeripheral::pollInstance = NULL; // allocate space for the static + +/*------------------------------------------------------------------*/ +/* Paser helper from modified from Adafruit BLEScanner.cpp code + NOTE: the return and args differ from Adafruit's method + ------------------------------------------------------------------*/ +/**************************************************************************/ +/*! + @file BLEScanner.cpp + @author hathach (tinyusb.org) + + @section LICENSE + + Software License Agreement (BSD License) + + Copyright (c) 2018, Adafruit Industries (adafruit.com) + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. Neither the name of the copyright holders nor the + names of its contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY + DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +/**************************************************************************/ +/** + parseScanDataByType + NOTE: the return and args differ from Adafruit's method + @param scandata + @param scanlen + @param type a type from ble_gap.h BLE_GAP_AD_TYPE_xxx defines + @param buf Output buffer + @param lenWritten pointer to uint8_t returns the number of bytes written to result + @return pointer to static reused buffer which is overwritted on each call and so needs to be copied if to be kept + returns NULL if not found +*/ +uint8_t* BLEPeripheral::parseScanDataByType(const uint8_t* scandata, uint8_t scanlen, uint8_t type, uint8_t& lenWritten) { + + static uint8_t buf[BLE_ADV_LEN+1]; // +1 for '\0' + + memset(buf, 0, sizeof(buf)); // clear return ALWAYS + lenWritten = 0; + uint8_t bufsize = BLE_ADV_LEN; + uint8_t len = 0; + uint8_t const* ptr = NULL; + + if ( scanlen < 2 ) { + return 0; + } + + // len (1+data), type, data + while ( scanlen ) { + if ( scandata[1] == type ) { + len = (scandata[0] - 1); + ptr = (scandata + 2); + break; + } else { + scanlen -= (scandata[0] + 1); + scandata += (scandata[0] + 1); + } + } + + // not found return 0 + if (ptr == NULL) { + return NULL; + } + + // Only check len if bufsize is input + if (len > bufsize) { + len = bufsize; + } + + memcpy(buf, ptr, len); + // note if pass in bufsize max adv len then should always have len < bufsize + lenWritten = len; + return buf; +} + +uint8_t* BLEPeripheral::parseScanDataByType(const ble_gap_evt_adv_report_t* report, uint8_t type, uint8_t& lenWritten) { + return parseScanDataByType(report->data, report->dlen, type, lenWritten); +} + +bool BLEPeripheral::isScanResponse(ble_gap_evt_adv_report_t* report) { + uint8_t scan_response_type = report->scan_rsp; + return (scan_response_type != 0); +} +bool BLEPeripheral::isScanAdvertise(ble_gap_evt_adv_report_t* report) { + uint8_t scan_response_type = report->scan_rsp; + return (scan_response_type == 0); +} +uint8_t* BLEPeripheral::getScanData(ble_gap_evt_adv_report_t* report) { + return report->data; +} +uint8_t BLEPeripheral::getScanDataLen(ble_gap_evt_adv_report_t* report) { + return report->dlen; +} + +bool BLEPeripheral::isConnectable(ble_gap_evt_adv_report_t* report) { + return (report->type == BLE_GAP_ADV_TYPE_ADV_IND || report->type == BLE_GAP_ADV_TYPE_ADV_DIRECT_IND); +} +int BLEPeripheral::getScanRSSI(ble_gap_evt_adv_report_t* report) { + return report->rssi; +} + +const uint8_t* BLEPeripheral::getScanAddress(ble_gap_evt_adv_report_t* report) { + return (report->peer_addr.addr); +} + + +BLEPeripheral::BLEPeripheral(unsigned char req, unsigned char rdy, unsigned char rst) : +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + _nRF51822(), +#else + _nRF8001(req, rdy, rst), +#endif + + _advertisedServiceUuid(NULL), + _serviceSolicitationUuid(NULL), + _manufacturerData(NULL), + _manufacturerDataLength(0), + _localAdvertName(NULL), // if this set local name sent in advert + _localName(NULL), // if this sent local name sent in scan response + + _localAttributes(NULL), + _numLocalAttributes(0), + _remoteAttributes(NULL), + _numRemoteAttributes(0), + + _genericAccessService("1800"), + _deviceNameCharacteristic("2a00", BLERead, 19), + _appearanceCharacteristic("2a01", BLERead, 2), + _genericAttributeService("1801"), + _servicesChangedCharacteristic("2a05", BLEIndicate, 4), + + _remoteGenericAttributeService("1801"), + _remoteServicesChangedCharacteristic("2a05", BLEIndicate), + + _central(this) +{ +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + this->_device = &this->_nRF51822; +#else + this->_device = &this->_nRF8001; +#endif + + memset(this->_eventHandlers, 0x00, sizeof(this->_eventHandlers)); + + this->setDeviceName(DEFAULT_DEVICE_NAME); + this->setAppearance(DEFAULT_APPEARANCE); + + this->_device->setEventListener(this); + pollInstance = this; +} + +BLEPeripheral::~BLEPeripheral() { + this->end(); + + if (this->_remoteAttributes) { + free(this->_remoteAttributes); + } + + if (this->_localAttributes) { + free(this->_localAttributes); + } + pollInstance = NULL; +} + +void BLEPeripheral::setConnectedHandler(void(*connectHandler)(BLECentral& central)) { + setEventHandler(BLEConnected, connectHandler); +} +void BLEPeripheral::setDisconnectedHandler(void(*disconnectHandler)(BLECentral& central)){ + setEventHandler(BLEDisconnected, disconnectHandler); +} + +// returns false if failed +bool BLEPeripheral::startScanning(ble_scan_response_handler_t scan_response_handler) { + return this->_device->startScanning(scan_response_handler); +} + +bool BLEPeripheral::stopScanning() { + return this->_device->stopScanning(); // does not clear handler +} + +void BLEPeripheral::setScanInterval(uint16_t interval, uint16_t window) { + this->_device->setScanInterval(interval, window); // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms +} +void BLEPeripheral::setActiveScan(bool enable) { + // Request scan response data, default is false + this->_device->setActiveScan(enable); // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms +} +void BLEPeripheral::setScanTimeout(uint16_t timeout) { + // 0 = Don't stop scanning after n seconds + this->_device->setScanTimeout(timeout); // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms +} + +void BLEPeripheral::begin() { + unsigned char advertisementDataSize = 0; + + BLEEirData advertisementData[3]; + BLEEirData scanData; + + scanData.length = 0; + + unsigned char remainingAdvertisementDataLength = BLE_ADVERTISEMENT_DATA_MAX_VALUE_LENGTH + 2; + if (this->_serviceSolicitationUuid){ + BLEUuid serviceSolicitationUuid = BLEUuid(this->_serviceSolicitationUuid); + + unsigned char uuidLength = serviceSolicitationUuid.length(); + advertisementData[advertisementDataSize].length = uuidLength; + advertisementData[advertisementDataSize].type = (uuidLength > 2) ? 0x15 : 0x14; + + memcpy(advertisementData[advertisementDataSize].data, serviceSolicitationUuid.data(), uuidLength); + advertisementDataSize += 1; + remainingAdvertisementDataLength -= uuidLength + 2; + } + if (this->_advertisedServiceUuid){ + BLEUuid advertisedServiceUuid = BLEUuid(this->_advertisedServiceUuid); + + unsigned char uuidLength = advertisedServiceUuid.length(); + if (uuidLength + 2 <= remainingAdvertisementDataLength) { + advertisementData[advertisementDataSize].length = uuidLength; + advertisementData[advertisementDataSize].type = (uuidLength > 2) ? 0x06 : 0x02; + + memcpy(advertisementData[advertisementDataSize].data, advertisedServiceUuid.data(), uuidLength); + advertisementDataSize += 1; + remainingAdvertisementDataLength -= uuidLength + 2; + } + } + if (this->_manufacturerData && this->_manufacturerDataLength > 0) { + if (remainingAdvertisementDataLength >= 3) { + unsigned char dataLength = this->_manufacturerDataLength; + + if (dataLength + 2 > remainingAdvertisementDataLength) { + dataLength = remainingAdvertisementDataLength - 2; + } + + advertisementData[advertisementDataSize].length = dataLength; + advertisementData[advertisementDataSize].type = 0xff; + + memcpy(advertisementData[advertisementDataSize].data, this->_manufacturerData, dataLength); + advertisementDataSize += 1; + remainingAdvertisementDataLength -= dataLength + 2; + } + } +// THIS ADDS LOCAL NAME TO ADVERT PACKET + if (this->_localAdvertName){ + if (remainingAdvertisementDataLength >= 3) { + unsigned char dataLength = strlen(this->_localAdvertName); + + if (dataLength + 2 > remainingAdvertisementDataLength) { + dataLength = remainingAdvertisementDataLength - 2; + } + + advertisementData[advertisementDataSize].length = dataLength; + advertisementData[advertisementDataSize].type = (dataLength > dataLength) ? 0x08 : 0x09; + + memcpy(advertisementData[advertisementDataSize].data, this->_localAdvertName, dataLength); + advertisementDataSize += 1; + remainingAdvertisementDataLength -= dataLength + 2; + } + } + + // this adds LOCAL name to scan data + if (this->_localName){ + unsigned char localNameLength = strlen(this->_localName); + scanData.length = localNameLength; + + if (scanData.length > BLE_SCAN_DATA_MAX_VALUE_LENGTH) { + scanData.length = BLE_SCAN_DATA_MAX_VALUE_LENGTH; + } + + scanData.type = (localNameLength > scanData.length) ? 0x08 : 0x09; + + memcpy(scanData.data, this->_localName, scanData.length); + } + + if (this->_localAttributes == NULL) { + this->initLocalAttributes(); + } + + for (int i = 0; i < this->_numLocalAttributes; i++) { + BLELocalAttribute* localAttribute = this->_localAttributes[i]; + if (localAttribute->type() == BLETypeCharacteristic) { + BLECharacteristic* characteristic = (BLECharacteristic*)localAttribute; + + characteristic->setValueChangeListener(*this); + } + } + + for (int i = 0; i < this->_numRemoteAttributes; i++) { + BLERemoteAttribute* remoteAttribute = this->_remoteAttributes[i]; + if (remoteAttribute->type() == BLETypeCharacteristic) { + BLERemoteCharacteristic* remoteCharacteristic = (BLERemoteCharacteristic*)remoteAttribute; + + remoteCharacteristic->setValueChangeListener(*this); + } + } + + if (this->_numRemoteAttributes) { + this->addRemoteAttribute(this->_remoteGenericAttributeService); + this->addRemoteAttribute(this->_remoteServicesChangedCharacteristic); + } + + this->_device->begin(advertisementDataSize, advertisementData, + scanData.length > 0 ? 1 : 0, &scanData, + this->_localAttributes, this->_numLocalAttributes, + this->_remoteAttributes, this->_numRemoteAttributes); + + this->_device->requestAddress(); +} + +bool BLEPeripheral::poll() { + return this->_device->poll(); +} + +void BLEPeripheral::end() { + this->_device->end(); +} + +void BLEPeripheral::setAdvertisedServiceUuid(const char* advertisedServiceUuid) { + this->_advertisedServiceUuid = advertisedServiceUuid; +} + +void BLEPeripheral::setServiceSolicitationUuid(const char* serviceSolicitationUuid) { + this->_serviceSolicitationUuid = serviceSolicitationUuid; +} + +void BLEPeripheral::setManufacturerData(const unsigned char manufacturerData[], unsigned char manufacturerDataLength) { + this->_manufacturerData = manufacturerData; + this->_manufacturerDataLength = manufacturerDataLength; +} + +void BLEPeripheral::setName(const char* localScanName) { + setLocalName(localScanName); +} + +void BLEPeripheral::setLocalName(const char* localScanName) { + this->_localName = localScanName; +} + +void BLEPeripheral::setAdvertisedName(const char *localAdvertName) { // set name in advert packet + this->_localAdvertName = localAdvertName; +} + +void BLEPeripheral::setConnectable(bool connectable) { + this->_device->setConnectable(connectable); +} + +bool BLEPeripheral::setTxPower(int txPower) { + return this->_device->setTxPower(txPower); +} + +void BLEPeripheral::setBondStore(BLEBondStore& bondStore) { + this->_device->setBondStore(bondStore); +} + +void BLEPeripheral::setDeviceName(const char* deviceName) { + this->_deviceNameCharacteristic.setValue(deviceName); +} + +void BLEPeripheral::setAppearance(unsigned short appearance) { + this->_appearanceCharacteristic.setValue((unsigned char *)&appearance, sizeof(appearance)); +} + +void BLEPeripheral::addAttribute(BLELocalAttribute& attribute) { + this->addLocalAttribute(attribute); +} + +void BLEPeripheral::addLocalAttribute(BLELocalAttribute& localAttribute) { + if (this->_localAttributes == NULL) { + this->initLocalAttributes(); + } + + this->_localAttributes[this->_numLocalAttributes] = &localAttribute; + this->_numLocalAttributes++; +} + +void BLEPeripheral::addRemoteAttribute(BLERemoteAttribute& remoteAttribute) { + if (this->_remoteAttributes == NULL) { + this->_remoteAttributes = (BLERemoteAttribute**)malloc(BLERemoteAttribute::numAttributes() * sizeof(BLERemoteAttribute*)); + } + + this->_remoteAttributes[this->_numRemoteAttributes] = &remoteAttribute; + this->_numRemoteAttributes++; +} + +void BLEPeripheral::setAdvertisingInterval(unsigned short advertisingInterval) { + this->_device->setAdvertisingInterval(advertisingInterval); +} + +void BLEPeripheral::setAdvertisingTimeout(uint16_t advertisingTimeout_secs) { + this->_device->setAdvertisingTimeout(advertisingTimeout_secs); +} + +bool BLEPeripheral::setAdvertising(bool on) { + bool rtn = false; + if (isConnected()) { + return false; + } + if (on) { + rtn = _device->startAdvertising(); + } else { + rtn = (sd_ble_gap_adv_stop() == NRF_SUCCESS); + } + return rtn; +} + +void BLEPeripheral::setConnectionInterval(unsigned short minimumConnectionInterval, unsigned short maximumConnectionInterval) { + this->_device->setConnectionInterval(minimumConnectionInterval, maximumConnectionInterval); +} + +void BLEPeripheral::setSlaveLatency(unsigned short slaveLatency) { + this->_device->setSlaveLatency(slaveLatency); +} + +void BLEPeripheral::disconnect() { + this->_device->disconnect(); +} + +BLECentral BLEPeripheral::central() { + this->poll(); + + return this->_central; +} + +bool BLEPeripheral::isConnected() { + return connected(); +} + +bool BLEPeripheral::connected() { + this->poll(); + + return this->_central; +} + +void BLEPeripheral::setEventHandler(BLEPeripheralEvent event, BLEPeripheralEventHandler eventHandler) { + if (event < sizeof(this->_eventHandlers)) { + this->_eventHandlers[event] = eventHandler; + } +} + +bool BLEPeripheral::characteristicValueChanged(BLECharacteristic& characteristic) { + return this->_device->updateCharacteristicValue(characteristic); +} + +bool BLEPeripheral::broadcastCharacteristic(BLECharacteristic& characteristic) { + return this->_device->broadcastCharacteristic(characteristic); +} + +bool BLEPeripheral::canNotifyCharacteristic(BLECharacteristic& characteristic) { + return this->_device->canNotifyCharacteristic(characteristic); +} + +bool BLEPeripheral::canIndicateCharacteristic(BLECharacteristic& characteristic) { + return this->_device->canIndicateCharacteristic(characteristic); +} + +bool BLEPeripheral::canReadRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->canReadRemoteCharacteristic(characteristic); +} + +bool BLEPeripheral::readRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->readRemoteCharacteristic(characteristic); +} + +bool BLEPeripheral::canWriteRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->canWriteRemoteCharacteristic(characteristic); +} + +bool BLEPeripheral::writeRemoteCharacteristic(BLERemoteCharacteristic& characteristic, const unsigned char value[], unsigned char length) { + return this->_device->writeRemoteCharacteristic(characteristic, value, length); +} + +bool BLEPeripheral::canSubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->canSubscribeRemoteCharacteristic(characteristic); +} + +bool BLEPeripheral::subscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->subscribeRemoteCharacteristic(characteristic); +} + +bool BLEPeripheral::canUnsubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->canUnsubscribeRemoteCharacteristic(characteristic); +} + +bool BLEPeripheral::unsubcribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->_device->unsubcribeRemoteCharacteristic(characteristic); +} + +void BLEPeripheral::BLEDeviceConnected(BLEDevice& /*device*/, const unsigned char* address) { + this->_central.setAddress(address); + +#ifdef BLE_PERIPHERAL_DEBUG + Serial.print(F("Peripheral connected to central: ")); + Serial.println(this->_central.address()); +#endif + + BLEPeripheralEventHandler eventHandler = this->_eventHandlers[BLEConnected]; + if (eventHandler) { + eventHandler(this->_central); + } +} + +void BLEPeripheral::BLEDeviceDisconnected(BLEDevice& /*device*/) { +#ifdef BLE_PERIPHERAL_DEBUG + Serial.print(F("Peripheral disconnected from central: ")); + Serial.println(this->_central.address()); +#endif + + BLEPeripheralEventHandler eventHandler = this->_eventHandlers[BLEDisconnected]; + if (eventHandler) { + eventHandler(this->_central); + } + + this->_central.clearAddress(); +} + +void BLEPeripheral::BLEDeviceBonded(BLEDevice& /*device*/) { +#ifdef BLE_PERIPHERAL_DEBUG + Serial.print(F("Peripheral bonded: ")); + Serial.println(this->_central.address()); +#endif + + BLEPeripheralEventHandler eventHandler = this->_eventHandlers[BLEBonded]; + if (eventHandler) { + eventHandler(this->_central); + } +} + +void BLEPeripheral::BLEDeviceRemoteServicesDiscovered(BLEDevice& /*device*/) { +#ifdef BLE_PERIPHERAL_DEBUG + Serial.print(F("Peripheral discovered central remote services: ")); + Serial.println(this->_central.address()); +#endif + + BLEPeripheralEventHandler eventHandler = this->_eventHandlers[BLERemoteServicesDiscovered]; + if (eventHandler) { + eventHandler(this->_central); + } +} + +void BLEPeripheral::BLEDeviceCharacteristicValueChanged(BLEDevice& /*device*/, BLECharacteristic& characteristic, const unsigned char* value, unsigned char valueLength) { + characteristic.setValue(this->_central, value, valueLength); +} + +void BLEPeripheral::BLEDeviceCharacteristicSubscribedChanged(BLEDevice& /*device*/, BLECharacteristic& characteristic, bool subscribed) { + characteristic.setSubscribed(this->_central, subscribed); +} + +void BLEPeripheral::BLEDeviceRemoteCharacteristicValueChanged(BLEDevice& /*device*/, BLERemoteCharacteristic& remoteCharacteristic, const unsigned char* value, unsigned char valueLength) { + remoteCharacteristic.setValue(this->_central, value, valueLength); +} + +void BLEPeripheral::BLEDeviceAddressReceived(BLEDevice& /*device*/, const unsigned char* /*address*/) { +#ifdef BLE_PERIPHERAL_DEBUG + char addressStr[18]; + + BLEUtil::addressToString(address, addressStr); + + Serial.print(F("Peripheral address: ")); + Serial.println(addressStr); +#endif +} + +void BLEPeripheral::BLEDeviceTemperatureReceived(BLEDevice& /*device*/, float /*temperature*/) { +} + +void BLEPeripheral::BLEDeviceBatteryLevelReceived(BLEDevice& /*device*/, float /*batteryLevel*/) { +} + +void BLEPeripheral::initLocalAttributes() { + this->_localAttributes = (BLELocalAttribute**)malloc(BLELocalAttribute::numAttributes() * sizeof(BLELocalAttribute*)); + + this->_localAttributes[0] = &this->_genericAccessService; + this->_localAttributes[1] = &this->_deviceNameCharacteristic; + this->_localAttributes[2] = &this->_appearanceCharacteristic; + + this->_localAttributes[3] = &this->_genericAttributeService; + this->_localAttributes[4] = &this->_servicesChangedCharacteristic; + + this->_numLocalAttributes = 5; +} diff --git a/cores/nRF5/BLEPeripheral.h b/cores/nRF5/BLEPeripheral.h new file mode 100644 index 00000000..5a1ae000 --- /dev/null +++ b/cores/nRF5/BLEPeripheral.h @@ -0,0 +1,237 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_PERIPHERAL_H_ +#define _BLE_PERIPHERAL_H_ + +#include "bleConstants.h" + +#include "Arduino.h" + +#include "BLEBondStore.h" +#include "BLECentral.h" +#include "BLEConstantCharacteristic.h" +#include "BLEDescriptor.h" +#include "BLEDevice.h" +#include "BLEFixedLengthCharacteristic.h" +#include "BLELocalAttribute.h" +#include "BLEProgmemConstantCharacteristic.h" +#include "BLERemoteAttribute.h" +#include "BLERemoteCharacteristic.h" +#include "BLERemoteService.h" +#include "BLEService.h" +#include "BLETypedCharacteristics.h" + +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + #include "nRF51822.h" +#else + #include "nRF8001.h" +#endif + +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + #define BLE_DEFAULT_REQ -1 + #define BLE_DEFAULT_RDY -1 + #define BLE_DEFAULT_RST -1 +#elif defined(BLEND_MICRO) + #define BLE_DEFAULT_REQ 6 + #define BLE_DEFAULT_RDY 7 + #define BLE_DEFAULT_RST 4 +#elif defined(BLEND) + #define BLE_DEFAULT_REQ 9 + #define BLE_DEFAULT_RDY 8 + #define BLE_DEFAULT_RST 4 +#else + #define BLE_DEFAULT_REQ 10 + #define BLE_DEFAULT_RDY 2 + #define BLE_DEFAULT_RST 9 +#endif + + +enum BLEPeripheralEvent { + BLEConnected = 0, + BLEDisconnected = 1, + BLEBonded = 2, + BLERemoteServicesDiscovered = 3 +}; + +typedef void (*BLEPeripheralEventHandler)(BLECentral& central); + +class BLEPeripheral : public BLEDeviceEventListener, + public BLECharacteristicValueChangeListener, + public BLERemoteCharacteristicValueChangeListener +{ + public: + BLEPeripheral(unsigned char req = BLE_DEFAULT_REQ, unsigned char rdy = BLE_DEFAULT_RDY, unsigned char rst = BLE_DEFAULT_RST); + virtual ~BLEPeripheral(); + + static BLEPeripheral* pollInstance; // used for polling if not NULL + + static const size_t BLE_ADDR_LEN = 6; + static const size_t BLE_ADV_LEN = 31; + static uint8_t* parseScanDataByType(const uint8_t* scandata, uint8_t scanlen, uint8_t type, uint8_t& lenWritten); + static uint8_t* parseScanDataByType(const ble_gap_evt_adv_report_t* report, uint8_t type, uint8_t& lenWritten); + static bool isScanResponse(ble_gap_evt_adv_report_t* report); + static bool isScanAdvertise(ble_gap_evt_adv_report_t* report); + static uint8_t* getScanData(ble_gap_evt_adv_report_t* report); + static uint8_t getScanDataLen(ble_gap_evt_adv_report_t* report); + static bool isConnectable(ble_gap_evt_adv_report_t* report); + static int getScanRSSI(ble_gap_evt_adv_report_t* report); + static const uint8_t* getScanAddress(ble_gap_evt_adv_report_t* report); + + + void begin(); // this starts advertising so need to call stopAdvertising() if needed + virtual bool poll(); // use sub-class implementation if any + void end(); + + virtual void setConnectedHandler(void(*connectHandler)(BLECentral& central)); + virtual void setDisconnectedHandler(void(*disconnectHandler)(BLECentral& central)); + virtual bool isConnected(); + + // NOTE: scanning is a high current process, while running the nRF52832 uses ~3mA + virtual bool startScanning(ble_scan_response_handler_t scan_response_handler); // returns false if failed + /* Function for stopping the scanning. + * Note This functions returns immediately, but the scanning is actually stopped after the next radio slot. + */ + virtual bool stopScanning(); // does not clear handler + + // update these while not scanning and then call startScanning() to apply them + virtual void setScanInterval(uint16_t interval, uint16_t window); // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms + virtual void setActiveScan(bool enable); // Request scan response data, default is false + virtual void setScanTimeout(uint16_t timeout_sec); //NOTE: this timeout is in seconds!! // 0 = Don't stop scanning after n seconds + + void setAdvertisedServiceUuid(const char* advertisedServiceUuid); + void setServiceSolicitationUuid(const char* serviceSolicitationUuid); + void setManufacturerData(const unsigned char manufacturerData[], unsigned char manufacturerDataLength); + void setAdvertisedName(const char *localAdvertName); // set name in advert packet + virtual void setLocalName(const char *localScanName); // this sets scan packet + virtual void setName(const char *localScanName); // this sets scan packet + + // setAdvertisingTimeout in sec + // e.g. to set 2s advertising interval use + // setAdvertisingTimeout(2); + // and then setAdvertising(true) to start for 2sec then stop + // setAdvertisingTimeout(0); // never turns off advertising + void setAdvertisingTimeout(uint16_t advertisingTimeout_secs); + + // call setAdvertising(true) to start advertising with current advertisingTimeout + // call setAdvertising(false) to stop advertising regardless + bool setAdvertising(bool turnOn); + + bool stopAdvertising() { return setAdvertising(false); } + bool startAdvertising() { return setAdvertising(true); } + + // setAdvertisingInterval in ms + // e.g. to set 100ms advertising interval use + // setAdvertisingInterval(100); + // must be in the range 20ms to 10240ms (10.24sec) + // default is 500ms + void setAdvertisingInterval(unsigned short advertisingInterval); + + // must be between 8ms and 4000ms + // internally stored in 1.25 ms increments, but this method expects ms arguments + // e.g. to set 50ms min, 100ms max connection intervals use + // setConnectionInterval(50,100); + // must be between 8ms and 4000ms + // defaults are 100ms min and 150ms max + void setConnectionInterval(unsigned short minimumConnectionInterval, unsigned short maximumConnectionInterval); + + // must be in the range + // 0 to ((4000 / connectionInterval_ms) ). + // i.e. must respond within supervision timeout even if no data + // default connectionSupervisionTimeout is 4sec see bleConstants.h + // default is 0 + void setSlaveLatency(unsigned short slaveLatency); + + // default txPower is +4 (maximum) + // available settings -40, -30, -20, -16, -12, -8, -4, 0, 4 + bool setTxPower(int txPower); + + // default true (connectable) + void setConnectable(bool connectable); + void setBondStore(BLEBondStore& bondStore); + + + // default deviceName "Arduino" + void setDeviceName(const char* deviceName); + void setAppearance(unsigned short appearance); + + void addAttribute(BLELocalAttribute& attribute); + void addLocalAttribute(BLELocalAttribute& localAttribute); + void addRemoteAttribute(BLERemoteAttribute& remoteAttribute); + + void disconnect(); + + BLECentral central(); + bool connected(); + + void setEventHandler(BLEPeripheralEvent event, BLEPeripheralEventHandler eventHandler); + + protected: + bool characteristicValueChanged(BLECharacteristic& characteristic); + bool broadcastCharacteristic(BLECharacteristic& characteristic); + bool canNotifyCharacteristic(BLECharacteristic& characteristic); + bool canIndicateCharacteristic(BLECharacteristic& characteristic); + + bool canReadRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + bool readRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + bool canWriteRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + bool writeRemoteCharacteristic(BLERemoteCharacteristic& characteristic, const unsigned char value[], unsigned char length); + bool canSubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + bool subscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + bool canUnsubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + bool unsubcribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + + virtual void BLEDeviceConnected(BLEDevice& device, const unsigned char* address); + virtual void BLEDeviceDisconnected(BLEDevice& device); + virtual void BLEDeviceBonded(BLEDevice& device); + virtual void BLEDeviceRemoteServicesDiscovered(BLEDevice& device); + + virtual void BLEDeviceCharacteristicValueChanged(BLEDevice& device, BLECharacteristic& characteristic, const unsigned char* value, unsigned char valueLength); + virtual void BLEDeviceCharacteristicSubscribedChanged(BLEDevice& device, BLECharacteristic& characteristic, bool subscribed); + + virtual void BLEDeviceRemoteCharacteristicValueChanged(BLEDevice& device, BLERemoteCharacteristic& remoteCharacteristic, const unsigned char* value, unsigned char valueLength); + + virtual void BLEDeviceAddressReceived(BLEDevice& device, const unsigned char* address); + virtual void BLEDeviceTemperatureReceived(BLEDevice& device, float temperature); + virtual void BLEDeviceBatteryLevelReceived(BLEDevice& device, float batteryLevel); + + private: + void initLocalAttributes(); + + protected: + BLEDevice* _device; + + private: + +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + nRF51822 _nRF51822; +#else + nRF8001 _nRF8001; +#endif + + const char* _advertisedServiceUuid; + const char* _serviceSolicitationUuid; + const unsigned char* _manufacturerData; + unsigned char _manufacturerDataLength; + const char* _localName; // if this set localname sent in scan response + const char* _localAdvertName; // if this set local name sent in advert + + BLELocalAttribute** _localAttributes; + unsigned char _numLocalAttributes; + BLERemoteAttribute** _remoteAttributes; + unsigned char _numRemoteAttributes; + + BLEService _genericAccessService; + BLECharacteristic _deviceNameCharacteristic; + BLECharacteristic _appearanceCharacteristic; + BLEService _genericAttributeService; + BLECharacteristic _servicesChangedCharacteristic; + + BLERemoteService _remoteGenericAttributeService; + BLERemoteCharacteristic _remoteServicesChangedCharacteristic; + + BLECentral _central; + BLEPeripheralEventHandler _eventHandlers[4]; +}; + +#endif diff --git a/cores/nRF5/BLEProgmemConstantCharacteristic.cpp b/cores/nRF5/BLEProgmemConstantCharacteristic.cpp new file mode 100644 index 00000000..f7c1f107 --- /dev/null +++ b/cores/nRF5/BLEProgmemConstantCharacteristic.cpp @@ -0,0 +1,25 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEProgmemConstantCharacteristic.h" + +BLEProgmemConstantCharacteristic::BLEProgmemConstantCharacteristic(const char* uuid, const unsigned char value[], unsigned char length) : + BLEConstantCharacteristic(uuid, value, length) +{ +} + +BLEProgmemConstantCharacteristic::BLEProgmemConstantCharacteristic(const char* uuid, const char* value) : +#ifdef __AVR__ + BLEConstantCharacteristic(uuid, (const unsigned char *)value, strlen_P(value)) +#else + BLEConstantCharacteristic(uuid, value) +#endif +{ +} + +BLEProgmemConstantCharacteristic::~BLEProgmemConstantCharacteristic() { +} + +unsigned char BLEProgmemConstantCharacteristic::operator[] (int offset) const { + return pgm_read_byte_near(&this->_value[offset]); +} diff --git a/cores/nRF5/BLEProgmemConstantCharacteristic.h b/cores/nRF5/BLEProgmemConstantCharacteristic.h new file mode 100644 index 00000000..0608d4b5 --- /dev/null +++ b/cores/nRF5/BLEProgmemConstantCharacteristic.h @@ -0,0 +1,21 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_PROGMEM_CONSTANT_CHARACTERISTIC_H_ +#define _BLE_PROGMEM_CONSTANT_CHARACTERISTIC_H_ + +#include "Arduino.h" + +#include "BLEConstantCharacteristic.h" + +class BLEProgmemConstantCharacteristic : public BLEConstantCharacteristic { + public: + BLEProgmemConstantCharacteristic(const char* uuid, const unsigned char value[], unsigned char length); + BLEProgmemConstantCharacteristic(const char* uuid, const char* value); + + virtual ~BLEProgmemConstantCharacteristic(); + + virtual unsigned char operator[] (int offset) const; +}; + +#endif diff --git a/cores/nRF5/BLERemoteAttribute.cpp b/cores/nRF5/BLERemoteAttribute.cpp new file mode 100644 index 00000000..26b56c62 --- /dev/null +++ b/cores/nRF5/BLERemoteAttribute.cpp @@ -0,0 +1,16 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLERemoteAttribute.h" + +unsigned char BLERemoteAttribute::_numAttributes = 0; + +BLERemoteAttribute::BLERemoteAttribute(const char* uuid, enum BLEAttributeType type) : + BLEAttribute(uuid, type) +{ + _numAttributes++; +} + +unsigned char BLERemoteAttribute::numAttributes() { + return _numAttributes; +} diff --git a/cores/nRF5/BLERemoteAttribute.h b/cores/nRF5/BLERemoteAttribute.h new file mode 100644 index 00000000..defe3724 --- /dev/null +++ b/cores/nRF5/BLERemoteAttribute.h @@ -0,0 +1,23 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_REMOTE_ATTRIBUTE_H_ +#define _BLE_REMOTE_ATTRIBUTE_H_ + +#include "BLEAttribute.h" + +class BLERemoteAttribute : public BLEAttribute +{ + friend class BLEPeripheral; + + public: + BLERemoteAttribute(const char* uuid, enum BLEAttributeType type); + + protected: + static unsigned char numAttributes(); + + private: + static unsigned char _numAttributes; +}; + +#endif diff --git a/cores/nRF5/BLERemoteCharacteristic.cpp b/cores/nRF5/BLERemoteCharacteristic.cpp new file mode 100644 index 00000000..120a6e4b --- /dev/null +++ b/cores/nRF5/BLERemoteCharacteristic.cpp @@ -0,0 +1,141 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" + +#include "BLERemoteCharacteristic.h" + +BLERemoteCharacteristic::BLERemoteCharacteristic(const char* uuid, unsigned char properties) : + BLERemoteAttribute(uuid, BLETypeCharacteristic), + _properties(properties), + _valueLength(0), + _valueUpdated(false), + _listener(NULL) +{ + memset(this->_eventHandlers, 0x00, sizeof(this->_eventHandlers)); +} + +BLERemoteCharacteristic::~BLERemoteCharacteristic() { +} + +unsigned char BLERemoteCharacteristic::properties() const { + return this->_properties; +} + +const unsigned char* BLERemoteCharacteristic::value() const { + return this->_value; +} + +unsigned char BLERemoteCharacteristic::valueLength() const { + return this->_valueLength; +} + +bool BLERemoteCharacteristic::canRead() { + bool result = false; + + if (this->_listener) { + result = this->_listener->canReadRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::read() { + bool result = false; + + if (this->_listener) { + result = this->_listener->readRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::canWrite() { + bool result = false; + + if (this->_listener) { + result = this->_listener->canWriteRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::write(const unsigned char value[], unsigned char length) { + bool result = false; + + if (this->_listener) { + result = this->_listener->writeRemoteCharacteristic(*this, value, length); + } + + return result; +} + +bool BLERemoteCharacteristic::canSubscribe() { + bool result = false; + + if (this->_listener) { + result = this->_listener->canSubscribeRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::subscribe() { + bool result = false; + + if (this->_listener) { + result = this->_listener->subscribeRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::canUnsubscribe() { + bool result = false; + + if (this->_listener) { + result = this->_listener->canUnsubscribeRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::unsubscribe() { + bool result = false; + + if (this->_listener) { + result = this->_listener->unsubcribeRemoteCharacteristic(*this); + } + + return result; +} + +bool BLERemoteCharacteristic::valueUpdated() { + bool valueUpdated = this->_valueUpdated; + + this->_valueUpdated = false; + + return valueUpdated; +} + +void BLERemoteCharacteristic::setEventHandler(BLERemoteCharacteristicEvent event, BLERemoteCharacteristicEventHandler eventHandler) { + if (event < sizeof(this->_eventHandlers)) { + this->_eventHandlers[event] = eventHandler; + } +} + +void BLERemoteCharacteristic::setValue(BLECentral& central, const unsigned char value[], unsigned char length) { + this->_valueLength = length; + memcpy(this->_value, value, length); + + this->_valueUpdated = true; + + BLERemoteCharacteristicEventHandler eventHandler = this->_eventHandlers[BLEValueUpdated]; + if (eventHandler) { + eventHandler(central, *this); + } +} + +void BLERemoteCharacteristic::setValueChangeListener(BLERemoteCharacteristicValueChangeListener& listener) { + this->_listener = &listener; +} \ No newline at end of file diff --git a/cores/nRF5/BLERemoteCharacteristic.h b/cores/nRF5/BLERemoteCharacteristic.h new file mode 100644 index 00000000..9c369bd5 --- /dev/null +++ b/cores/nRF5/BLERemoteCharacteristic.h @@ -0,0 +1,78 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_REMOTE_CHARACTERISTIC_H_ +#define _BLE_REMOTE_CHARACTERISTIC_H_ + +#include "BLERemoteAttribute.h" +#include "BLEDeviceLimits.h" + +enum BLERemoteCharacteristicEvent { + BLEValueUpdated = 0 +}; + +class BLECentral; +class BLERemoteCharacteristic; + +class BLERemoteCharacteristicValueChangeListener +{ + public: + virtual bool canReadRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool readRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + + virtual bool canWriteRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool writeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/, const unsigned char /*value*/[], unsigned char /*length*/) { return false; } + + virtual bool canSubscribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool subscribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool canUnsubscribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } + virtual bool unsubcribeRemoteCharacteristic(BLERemoteCharacteristic& /*characteristic*/) { return false; } +}; + +typedef void (*BLERemoteCharacteristicEventHandler)(BLECentral& central, BLERemoteCharacteristic& characteristic); + +class BLERemoteCharacteristic : public BLERemoteAttribute +{ + friend class BLEPeripheral; + + public: + BLERemoteCharacteristic(const char* uuid, unsigned char properties); + + virtual ~BLERemoteCharacteristic(); + + unsigned char properties() const; + + const unsigned char* value() const; + unsigned char valueLength() const; + + bool canRead(); + bool read(); + bool canWrite(); + bool write(const unsigned char value[], unsigned char length); + bool canSubscribe(); + bool subscribe(); + bool canUnsubscribe(); + bool unsubscribe(); + + bool valueUpdated(); + + void setEventHandler(BLERemoteCharacteristicEvent event, BLERemoteCharacteristicEventHandler eventHandler); + + protected: + void setValue(BLECentral& central, const unsigned char value[], unsigned char length); + + void setValueChangeListener(BLERemoteCharacteristicValueChangeListener& listener); + + private: + unsigned char _properties; + + unsigned char _valueLength; + unsigned char _value[BLE_REMOTE_ATTRIBUTE_MAX_VALUE_LENGTH]; + + bool _valueUpdated; + + BLERemoteCharacteristicValueChangeListener* _listener; + BLERemoteCharacteristicEventHandler _eventHandlers[1]; +}; + +#endif diff --git a/cores/nRF5/BLERemoteService.cpp b/cores/nRF5/BLERemoteService.cpp new file mode 100644 index 00000000..3b58a2c4 --- /dev/null +++ b/cores/nRF5/BLERemoteService.cpp @@ -0,0 +1,9 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLERemoteService.h" + +BLERemoteService::BLERemoteService(const char* uuid) : + BLERemoteAttribute(uuid, BLETypeService) +{ +} diff --git a/cores/nRF5/BLERemoteService.h b/cores/nRF5/BLERemoteService.h new file mode 100644 index 00000000..3153588a --- /dev/null +++ b/cores/nRF5/BLERemoteService.h @@ -0,0 +1,15 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_REMOTE_SERVICE_H_ +#define _BLE_REMOTE_SERVICE_H_ + +#include "BLERemoteAttribute.h" + +class BLERemoteService : public BLERemoteAttribute +{ + public: + BLERemoteService(const char* uuid); +}; + +#endif diff --git a/cores/nRF5/BLEService.cpp b/cores/nRF5/BLEService.cpp new file mode 100644 index 00000000..933deea4 --- /dev/null +++ b/cores/nRF5/BLEService.cpp @@ -0,0 +1,9 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLEService.h" + +BLEService::BLEService(const char* uuid) : + BLELocalAttribute(uuid, BLETypeService) +{ +} diff --git a/cores/nRF5/BLEService.h b/cores/nRF5/BLEService.h new file mode 100644 index 00000000..68b564f6 --- /dev/null +++ b/cores/nRF5/BLEService.h @@ -0,0 +1,15 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_SERVICE_H_ +#define _BLE_SERVICE_H_ + +#include "BLELocalAttribute.h" + +class BLEService : public BLELocalAttribute +{ + public: + BLEService(const char* uuid); +}; + +#endif diff --git a/cores/nRF5/BLESystemControl.cpp b/cores/nRF5/BLESystemControl.cpp new file mode 100644 index 00000000..de50953c --- /dev/null +++ b/cores/nRF5/BLESystemControl.cpp @@ -0,0 +1,68 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLESystemControl.h" + +static const PROGMEM unsigned char descriptorValue[] = { + // From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidComboC.c + // permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + + // system controls, like power, needs a 3rd different report and report descriptor + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x80, // USAGE (System Control) + 0xA1, 0x01, // COLLECTION (Application) + 0x85, 0x00, // REPORT_ID + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x02, // REPORT_SIZE (2) + 0x15, 0x01, // LOGICAL_MINIMUM (1) + 0x25, 0x03, // LOGICAL_MAXIMUM (3) + 0x09, 0x82, // USAGE (System Sleep) + 0x09, 0x81, // USAGE (System Power) + 0x09, 0x83, // USAGE (System Wakeup) + 0x81, 0x60, // INPUT + 0x75, 0x06, // REPORT_SIZE (6) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + 0xC0 // END_COLLECTION +}; + +BLESystemControl::BLESystemControl() : + BLEHID(descriptorValue, sizeof(descriptorValue), 7), + _reportCharacteristic("2a4d", BLERead | BLENotify, 4), + _reportReferenceDescriptor(BLEHIDDescriptorTypeInput) +{ +} + +size_t BLESystemControl::write(uint8_t k) { + uint8_t sysCtrlKeyPress[1]= { 0x00 }; + + // send key code + sysCtrlKeyPress[0] = k; + + for (int i = 0; i < 2; i++) { + this->sendData(this->_reportCharacteristic, sysCtrlKeyPress, sizeof(sysCtrlKeyPress)); + + // send cleared code + sysCtrlKeyPress[0] = 0x00; + } + + return 1; +} + +void BLESystemControl::setReportId(unsigned char reportId) { + BLEHID::setReportId(reportId); + + this->_reportReferenceDescriptor.setReportId(reportId); +} + +unsigned char BLESystemControl::numAttributes() { + return 2; +} + +BLELocalAttribute** BLESystemControl::attributes() { + static BLELocalAttribute* attributes[2]; + + attributes[0] = &this->_reportCharacteristic; + attributes[1] = &this->_reportReferenceDescriptor; + + return attributes; +} diff --git a/cores/nRF5/BLESystemControl.h b/cores/nRF5/BLESystemControl.h new file mode 100644 index 00000000..22c616b4 --- /dev/null +++ b/cores/nRF5/BLESystemControl.h @@ -0,0 +1,38 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_SYSTEM_CONTROL_H_ +#define _BLE_SYSTEM_CONTROL_H_ + +#include "Arduino.h" + +#include "BLECharacteristic.h" +#include "BLEHIDReportReferenceDescriptor.h" +#include "BLEHID.h" + +// From: https://github.com/adafruit/Adafruit-Trinket-USB/blob/master/TrinketHidCombo/TrinketHidCombo.h +// permission to use under MIT license by @ladyada (https://github.com/adafruit/Adafruit-Trinket-USB/issues/10) + +// system control keys +#define SYSCTRLKEY_POWER 0x01 +#define SYSCTRLKEY_SLEEP 0x02 +#define SYSCTRLKEY_WAKE 0x03 + +class BLESystemControl : public BLEHID +{ + public: + BLESystemControl(); + + size_t write(uint8_t k); + + protected: + virtual void setReportId(unsigned char reportId); + virtual unsigned char numAttributes(); + virtual BLELocalAttribute** attributes(); + + private: + BLECharacteristic _reportCharacteristic; + BLEHIDReportReferenceDescriptor _reportReferenceDescriptor; +}; + +#endif diff --git a/cores/nRF5/BLETypedCharacteristic.h b/cores/nRF5/BLETypedCharacteristic.h new file mode 100644 index 00000000..6bb3d99b --- /dev/null +++ b/cores/nRF5/BLETypedCharacteristic.h @@ -0,0 +1,78 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_TYPED_CHARACTERISTIC_H_ +#define _BLE_TYPED_CHARACTERISTIC_H_ + +#include "Arduino.h" + +#include "BLEFixedLengthCharacteristic.h" + +template class BLETypedCharacteristic : public BLEFixedLengthCharacteristic +{ + public: + BLETypedCharacteristic(const char* uuid, unsigned char properties); + + bool setValue(T value); + T value(); + + bool setValueLE(T value); + T valueLE(); + + bool setValueBE(T value); + T valueBE(); + + private: + T byteSwap(T value); +}; + +template BLETypedCharacteristic::BLETypedCharacteristic(const char* uuid, unsigned char properties) : + BLEFixedLengthCharacteristic(uuid, properties, sizeof(T)) +{ + T value; + memset(&value, 0x00, sizeof(value)); + + this->setValue(value); +} + +template bool BLETypedCharacteristic::setValue(T value) { + return this->BLECharacteristic::setValue((unsigned char*)&value, sizeof(T)); +} + +template T BLETypedCharacteristic::value() { + T value; + + memcpy(&value, (unsigned char*)this->BLECharacteristic::value(), this->BLECharacteristic::valueSize()); + + return value; +} + +template bool BLETypedCharacteristic::setValueLE(T value) { + return this->setValue(value); +} + +template T BLETypedCharacteristic::valueLE() { + return this->getValue(); +} + +template bool BLETypedCharacteristic::setValueBE(T value) { + return this->setValue(this->byteSwap(value)); +} + +template T BLETypedCharacteristic::valueBE() { + return this->byteSwap(this->value()); +} + +template T BLETypedCharacteristic::byteSwap(T value) { + T result; + unsigned char* src = (unsigned char*)&value; + unsigned char* dst = (unsigned char*)&result; + + for (int i = 0; i < sizeof(T); i++) { + dst[i] = src[sizeof(T) - i - 1]; + } + + return result; +} + +#endif diff --git a/cores/nRF5/BLETypedCharacteristics.cpp b/cores/nRF5/BLETypedCharacteristics.cpp new file mode 100644 index 00000000..494c50d0 --- /dev/null +++ b/cores/nRF5/BLETypedCharacteristics.cpp @@ -0,0 +1,48 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "BLETypedCharacteristics.h" + +BLEBoolCharacteristic::BLEBoolCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLECharCharacteristic::BLECharCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEUnsignedCharCharacteristic::BLEUnsignedCharCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEShortCharacteristic::BLEShortCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEUnsignedShortCharacteristic::BLEUnsignedShortCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEIntCharacteristic::BLEIntCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEUnsignedIntCharacteristic::BLEUnsignedIntCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLELongCharacteristic::BLELongCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEUnsignedLongCharacteristic::BLEUnsignedLongCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEFloatCharacteristic::BLEFloatCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} + +BLEDoubleCharacteristic::BLEDoubleCharacteristic(const char* uuid, unsigned char properties) : + BLETypedCharacteristic(uuid, properties) { +} diff --git a/cores/nRF5/BLETypedCharacteristics.h b/cores/nRF5/BLETypedCharacteristics.h new file mode 100644 index 00000000..8a60e400 --- /dev/null +++ b/cores/nRF5/BLETypedCharacteristics.h @@ -0,0 +1,64 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_TYPED_CHARACTERISTICS_H_ +#define _BLE_TYPED_CHARACTERISTICS_H_ + +#include "BLETypedCharacteristic.h" + +class BLEBoolCharacteristic : public BLETypedCharacteristic { + public: + BLEBoolCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLECharCharacteristic : public BLETypedCharacteristic { + public: + BLECharCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEUnsignedCharCharacteristic : public BLETypedCharacteristic { + public: + BLEUnsignedCharCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEShortCharacteristic : public BLETypedCharacteristic { + public: + BLEShortCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEUnsignedShortCharacteristic : public BLETypedCharacteristic { + public: + BLEUnsignedShortCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEIntCharacteristic : public BLETypedCharacteristic { + public: + BLEIntCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEUnsignedIntCharacteristic : public BLETypedCharacteristic { + public: + BLEUnsignedIntCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLELongCharacteristic : public BLETypedCharacteristic { + public: + BLELongCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEUnsignedLongCharacteristic : public BLETypedCharacteristic { + public: + BLEUnsignedLongCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEFloatCharacteristic : public BLETypedCharacteristic { + public: + BLEFloatCharacteristic(const char* uuid, unsigned char properties); +}; + +class BLEDoubleCharacteristic : public BLETypedCharacteristic { + public: + BLEDoubleCharacteristic(const char* uuid, unsigned char properties); +}; + +#endif diff --git a/cores/nRF5/BLEUtil.cpp b/cores/nRF5/BLEUtil.cpp new file mode 100644 index 00000000..dfa3de4f --- /dev/null +++ b/cores/nRF5/BLEUtil.cpp @@ -0,0 +1,42 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" +#include "Stream.h" +#include "BLEUtil.h" + +void BLEUtil::addressToString(const unsigned char *in, char* out) { + String address = ""; + String hex; + + for (int i = 5; i >= 0; i--) { + if (in[i] < 0x10) { + address += "0"; + } + + hex = String(in[i], 16); + address += hex; + + if (i > 0) { + address += ":"; + } + } + + address.toCharArray(out, 18); +} + +void BLEUtil::printBuffer(Stream* stream, const unsigned char* buffer, unsigned char length) { + if (stream == NULL) { + return; + } + for (int i = 0; i < length; i++) { + if ((buffer[i] & 0xf0) == 00) { + stream->print("0"); + } + + stream->print(buffer[i], HEX); + stream->print(" "); + } + stream->println(); +} + diff --git a/cores/nRF5/BLEUtil.h b/cores/nRF5/BLEUtil.h new file mode 100644 index 00000000..2b3f9828 --- /dev/null +++ b/cores/nRF5/BLEUtil.h @@ -0,0 +1,16 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_UTIL_H_ +#define _BLE_UTIL_H_ + +#include "Stream.h" +class BLEUtil +{ + public: + static void addressToString(const unsigned char *in, char* out); + + static void printBuffer(Stream *stream, const unsigned char* buffer, unsigned char length); +}; + +#endif diff --git a/cores/nRF5/BLEUuid.cpp b/cores/nRF5/BLEUuid.cpp new file mode 100644 index 00000000..0c5ac1c4 --- /dev/null +++ b/cores/nRF5/BLEUuid.cpp @@ -0,0 +1,39 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "Arduino.h" + +#include "BLEUuid.h" + +BLEUuid::BLEUuid(const char * str) : + _str(str) +{ + char temp[] = {0, 0, 0}; + + this->_length = 0; + for (int i = strlen(str) - 1; i >= 0 && this->_length < MAX_UUID_LENGTH; i -= 2) { + if (str[i] == '-') { + i++; + continue; + } + + temp[0] = str[i - 1]; + temp[1] = str[i]; + + this->_data[this->_length] = strtoul(temp, NULL, 16); + + this->_length++; + } +} + +const char* BLEUuid::str() const { + return this->_str; +} + +const unsigned char* BLEUuid::data() const { + return this->_data; +} + +unsigned char BLEUuid::length() const { + return this->_length; +} diff --git a/cores/nRF5/BLEUuid.h b/cores/nRF5/BLEUuid.h new file mode 100644 index 00000000..dad965d8 --- /dev/null +++ b/cores/nRF5/BLEUuid.h @@ -0,0 +1,24 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _BLE_UUID_H_ +#define _BLE_UUID_H_ + +#define MAX_UUID_LENGTH 16 + +class BLEUuid +{ + public: + BLEUuid(const char * str); + + const char* str() const; + const unsigned char* data() const; + unsigned char length() const; + + private: + const char* _str; + unsigned char _data[MAX_UUID_LENGTH]; + unsigned char _length; +}; + +#endif diff --git a/cores/nRF5/EddystoneBeacon.cpp b/cores/nRF5/EddystoneBeacon.cpp new file mode 100644 index 00000000..cc0ecdab --- /dev/null +++ b/cores/nRF5/EddystoneBeacon.cpp @@ -0,0 +1,124 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "EddystoneBeacon.h" + +#define MAX_SERVICE_DATA_SIZE 20 + +#define FLAGS_UID 0x00 +#define FLAGS_URL 0x10 +#define FLAGS_TLM 0x20 + +static const char* EDDYSTONE_URL_BEACON_PREFIX_SUBSTITUTIONS[] = { + "http://www./", + "https://www./", + "http://", + "https://", + "urn:uuid:" +}; + +static const char* EDDYSTONE_URL_BEACON_SUFFIX_SUBSTITUTIONS[] = { + ".com/", + ".org/", + ".edu/", + ".net/", + ".info/", + ".biz/", + ".gov/", + ".com", + ".org", + ".edu", + ".net", + ".info", + ".biz", + ".gov" +}; + +EddystoneBeacon::EddystoneBeacon(unsigned char req, unsigned char rdy, unsigned char rst) : + BLEPeripheral(req, rdy, rst), + _bleService("feaa"), + _bleCharacteristic("feab", BLERead | BLEBroadcast, MAX_SERVICE_DATA_SIZE) +{ + this->setConnectable(false); + + this->addAttribute(this->_bleService); + this->addAttribute(this->_bleCharacteristic); +} + +void EddystoneBeacon::begin(char power, const BLEUuid& uid) { + unsigned char serviceData[MAX_SERVICE_DATA_SIZE]; + + this->_power = power; + + memset(serviceData, 0x00, sizeof(serviceData)); + serviceData[0] = FLAGS_UID; + serviceData[1] = this->_power; + + const unsigned char* uidData = uid.data(); + for (int i = 0; i < 16; i++) { + serviceData[i + 2] = uidData[15 - i]; + } + + serviceData[18] = 0x00; // Reserved for future use, must be: 0x00 + serviceData[19] = 0x00; // Reserved for future use, must be: 0x00 + + this->_bleCharacteristic.setValue(serviceData, sizeof(serviceData)); + + this->setAdvertisedServiceUuid(this->_bleService.uuid()); + + BLEPeripheral::begin(); + + this->_bleCharacteristic.broadcast(); +} + +void EddystoneBeacon::begin(char power, const char* uri) { + this->_power = power; + this->setURI(uri); + + this->setAdvertisedServiceUuid(this->_bleService.uuid()); + + BLEPeripheral::begin(); + + this->_bleCharacteristic.broadcast(); +} + +void EddystoneBeacon::setURI(const char* uri) { + unsigned char serviceData[MAX_SERVICE_DATA_SIZE]; + + serviceData[0] = FLAGS_URL; + serviceData[1] = this->_power; + unsigned char compressedURIlength = this->compressURI(uri, (char *)&serviceData[2], sizeof(serviceData) - 2); + + this->_bleCharacteristic.setValue(serviceData, 2 + compressedURIlength); +} + +unsigned char EddystoneBeacon::compressURI(const char* uri, char *compressedUri, unsigned char compressedUriSize) { + String uriString = uri; + + // replace prefixes + for (unsigned int i = 0; i < (sizeof(EDDYSTONE_URL_BEACON_PREFIX_SUBSTITUTIONS) / sizeof(char *)); i++) { + String replacement = " "; + replacement[0] = (char)(i | 0x80); // set high bit, String.replace does not like '\0' replacement + + uriString.replace(EDDYSTONE_URL_BEACON_PREFIX_SUBSTITUTIONS[i], replacement); + } + + // replace suffixes + for (unsigned int i = 0; i < (sizeof(EDDYSTONE_URL_BEACON_SUFFIX_SUBSTITUTIONS) / sizeof(char *)); i++) { + String replacement = " "; + replacement[0] = (char)(i | 0x80); // set high bit, String.replace does not like '\0' replacement + + uriString.replace(EDDYSTONE_URL_BEACON_SUFFIX_SUBSTITUTIONS[i], replacement); + } + + unsigned char i = 0; + for (i = 0; i < uriString.length() && i < compressedUriSize; i++) { + compressedUri[i] = (uriString[i] & 0x7f); // assign byte after clearing hight bit + } + + return i; +} + +void EddystoneBeacon::loop() { + this->poll(); +} diff --git a/cores/nRF5/EddystoneBeacon.h b/cores/nRF5/EddystoneBeacon.h new file mode 100644 index 00000000..707b6d9c --- /dev/null +++ b/cores/nRF5/EddystoneBeacon.h @@ -0,0 +1,30 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _EDDYSTONE_BEACON_H_ +#define _EDDYSTONE_BEACON_H_ + +#include "BLEPeripheral.h" +#include "BLEUuid.h" + +class EddystoneBeacon : public BLEPeripheral +{ + public: + EddystoneBeacon(unsigned char req = BLE_DEFAULT_REQ, unsigned char rdy = BLE_DEFAULT_RDY, unsigned char rst = BLE_DEFAULT_RST); + + void begin(char power, const BLEUuid& uid); + void begin(char power, const char* uri); + void loop(); + + void setURI(const char* uri); + + private: + unsigned char compressURI(const char* uri, char *compressedUri, unsigned char compressedUriSize); + + char _power; + + BLEService _bleService; + BLECharacteristic _bleCharacteristic; +}; + +#endif diff --git a/cores/nRF5/HardwareSerial.h b/cores/nRF5/HardwareSerial.h index 07225c4a..62508e78 100644 --- a/cores/nRF5/HardwareSerial.h +++ b/cores/nRF5/HardwareSerial.h @@ -67,9 +67,9 @@ class HardwareSerial : public Stream { public: - virtual void begin(unsigned long) = 0; - virtual void begin(unsigned long baudrate, uint16_t config) = 0; - virtual void end() = 0; + virtual void begin(unsigned long); + virtual void begin(unsigned long baudrate, uint16_t config); + virtual void end(); virtual int available(void) = 0; virtual int peek(void) = 0; virtual int read(void) = 0; diff --git a/cores/nRF5/SDK/components/device/compiler_abstraction.h b/cores/nRF5/SDK/components/device/compiler_abstraction.h index 548cde95..6a41e8e3 100755 --- a/cores/nRF5/SDK/components/device/compiler_abstraction.h +++ b/cores/nRF5/SDK/components/device/compiler_abstraction.h @@ -1,47 +1,37 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef _COMPILER_ABSTRACTION_H #define _COMPILER_ABSTRACTION_H /*lint ++flb "Enter library region" */ -#ifndef NRF_STRING_CONCATENATE_IMPL - #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs -#endif -#ifndef NRF_STRING_CONCATENATE - #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs) -#endif - #if defined ( __CC_ARM ) #ifndef __ASM @@ -60,58 +50,8 @@ POSSIBILITY OF SUCH DAMAGE. #define __ALIGN(n) __align(n) #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - - #ifndef __UNUSED - #define __UNUSED __attribute__((unused)) - #endif - - #define GET_SP() __current_sp() - - #ifndef NRF_STATIC_ASSERT - #define NRF_STATIC_ASSERT(cond, msg) \ - ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) } - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - - #ifndef __ASM - #define __ASM __asm - #endif - - #ifndef __INLINE - #define __INLINE __inline - #endif - - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - - #ifndef __ALIGN - #define __ALIGN(n) __attribute__((aligned(n))) - #endif - - #ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) - #endif - - #ifndef __UNUSED - #define __UNUSED __attribute__((unused)) - #endif - #define GET_SP() __current_sp() - #ifndef NRF_STATIC_ASSERT - #ifdef __cplusplus - #ifndef _Static_assert - #define _Static_assert static_assert - #endif - #endif - #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) - #endif - #elif defined ( __ICCARM__ ) #ifndef __ASM @@ -126,26 +66,14 @@ POSSIBILITY OF SUCH DAMAGE. #define __WEAK __weak #endif + /* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */ #ifndef __ALIGN - #define STRING_PRAGMA(x) _Pragma(#x) - #define __ALIGN(n) STRING_PRAGMA(data_alignment = n) + #define __ALIGN(n) #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - - #ifndef __UNUSED - #define __UNUSED - #endif - #define GET_SP() __get_SP() - #ifndef NRF_STATIC_ASSERT - #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) - #endif - -#elif defined ( __GNUC__ ) || defined ( __clang__ ) +#elif defined ( __GNUC__ ) #ifndef __ASM #define __ASM __asm @@ -163,32 +91,14 @@ POSSIBILITY OF SUCH DAMAGE. #define __ALIGN(n) __attribute__((aligned(n))) #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - - #ifndef __UNUSED - #define __UNUSED __attribute__((unused)) - #endif - #define GET_SP() gcc_current_sp() static inline unsigned int gcc_current_sp(void) { - unsigned int stack_pointer = 0; - __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer)); - return stack_pointer; + register unsigned sp __ASM("sp"); + return sp; } - #ifndef NRF_STATIC_ASSERT - #ifdef __cplusplus - #ifndef _Static_assert - #define _Static_assert static_assert - #endif - #endif - #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg) - #endif - #elif defined ( __TASKING__ ) #ifndef __ASM @@ -206,40 +116,11 @@ POSSIBILITY OF SUCH DAMAGE. #ifndef __ALIGN #define __ALIGN(n) __align(n) #endif - - /* Not defined for TASKING. */ - #ifndef __PACKED - #define __PACKED - #endif - - #ifndef __UNUSED - #define __UNUSED __attribute__((unused)) - #endif #define GET_SP() __get_MSP() - #ifndef NRF_STATIC_ASSERT - #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg) - #endif - #endif -#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \ - NRF_STATIC_ASSERT( \ - ( \ - (major < MDK_MAJOR_VERSION) || \ - (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \ - (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \ - ), "MDK version mismatch.") - -#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \ - NRF_STATIC_ASSERT( \ - ( \ - (major != MDK_MAJOR_VERSION) || \ - (major != MDK_MAJOR_VERSION) || \ - (major != MDK_MAJOR_VERSION) \ - ), "MDK version mismatch.") - /*lint --flb "Leave library region" */ #endif diff --git a/cores/nRF5/SDK/components/device/nrf.h b/cores/nRF5/SDK/components/device/nrf.h index 63087ce7..fa24afad 100755 --- a/cores/nRF5/SDK/components/device/nrf.h +++ b/cores/nRF5/SDK/components/device/nrf.h @@ -1,187 +1,66 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef NRF_H #define NRF_H /* MDK version */ -#define MDK_MAJOR_VERSION 8 -#define MDK_MINOR_VERSION 37 -#define MDK_MICRO_VERSION 0 - - -/* Define coprocessor domains */ -#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK) - #ifndef NRF5340_XXAA - #define NRF5340_XXAA - #endif -#endif -#if defined (NRF5340_XXAA_APPLICATION) - #ifndef NRF_APPLICATION - #define NRF_APPLICATION - #endif -#endif -#if defined (NRF5340_XXAA_NETWORK) - #ifndef NRF_NETWORK - #define NRF_NETWORK - #endif -#endif - -/* Apply compatibility macros for old nRF5340 macros */ -#if defined(NRF5340_XXAA) - #if defined (NRF_APPLICATION) - #ifndef NRF5340_XXAA_APPLICATION - #define NRF5340_XXAA_APPLICATION - #endif - #endif - #if defined (NRF_NETWORK) - #ifndef NRF5340_XXAA_NETWORK - #define NRF5340_XXAA_NETWORK - #endif - #endif -#endif - -/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */ -#if defined (NRF51) ||\ - defined (NRF51422_XXAA) ||\ - defined (NRF51422_XXAB) ||\ - defined (NRF51422_XXAC) ||\ - defined (NRF51801_XXAB) ||\ - defined (NRF51802_XXAA) ||\ - defined (NRF51822_XXAA) ||\ - defined (NRF51822_XXAB) ||\ - defined (NRF51822_XXAC) ||\ - defined (NRF51824_XXAA) - #ifndef NRF51_SERIES - #define NRF51_SERIES - #endif - #ifndef NRF51 - #define NRF51 - #endif -#endif - -/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */ -#if defined (NRF52) - #ifndef NRF52832_XXAA - #define NRF52832_XXAA - #endif -#endif - -/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */ -#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA) - #ifndef NRF52_SERIES - #define NRF52_SERIES - #endif -#endif - -/* Define NRF53_SERIES for common use in nRF53 series devices. */ -#if defined (NRF5340_XXAA) - #ifndef NRF53_SERIES - #define NRF53_SERIES - #endif -#endif - -/* Define NRF91_SERIES for common use in nRF91 series devices. */ -#if defined (NRF9160_XXAA) - #ifndef NRF91_SERIES - #define NRF91_SERIES - #endif -#endif - -/* Device selection for device includes. */ -#if defined (NRF51) - #include "nrf51.h" - #include "nrf51_bitfields.h" - #include "nrf51_deprecated.h" - -#elif defined (NRF52805_XXAA) - #include "nrf52805.h" - #include "nrf52805_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #include "nrf52810_to_nrf52811.h" -#elif defined (NRF52810_XXAA) - #include "nrf52810.h" - #include "nrf52810_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #include "nrf52810_name_change.h" -#elif defined (NRF52811_XXAA) - #include "nrf52811.h" - #include "nrf52811_bitfields.h" - #include "nrf51_to_nrf52810.h" - #include "nrf52_to_nrf52810.h" - #include "nrf52810_to_nrf52811.h" -#elif defined (NRF52820_XXAA) - #include "nrf52820.h" - #include "nrf52820_bitfields.h" - #include "nrf51_to_nrf52.h" - #include "nrf52_to_nrf52833.h" - #include "nrf52833_to_nrf52820.h" -#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB) - #include "nrf52.h" - #include "nrf52_bitfields.h" - #include "nrf51_to_nrf52.h" - #include "nrf52_name_change.h" -#elif defined (NRF52833_XXAA) - #include "nrf52833.h" - #include "nrf52833_bitfields.h" - #include "nrf52_to_nrf52833.h" - #include "nrf51_to_nrf52.h" -#elif defined (NRF52840_XXAA) - #include "nrf52840.h" - #include "nrf52840_bitfields.h" - #include "nrf51_to_nrf52840.h" - #include "nrf52_to_nrf52840.h" - -#elif defined (NRF5340_XXAA) - #if defined(NRF_APPLICATION) - #include "nrf5340_application.h" - #include "nrf5340_application_bitfields.h" - #elif defined (NRF_NETWORK) - #include "nrf5340_network.h" - #include "nrf5340_network_bitfields.h" - #endif - -#elif defined (NRF9160_XXAA) - #include "nrf9160.h" - #include "nrf9160_bitfields.h" - #include "nrf9160_name_change.h" - +#define MDK_MAJOR_VERSION 8 +#define MDK_MINOR_VERSION 5 +#define MDK_MICRO_VERSION 0 + +#if defined(_WIN32) + /* Do not include nrf51 specific files when building for PC host */ +#elif defined(__unix) + /* Do not include nrf51 specific files when building for PC host */ +#elif defined(__APPLE__) + /* Do not include nrf51 specific files when building for PC host */ #else - #error "Device must be defined. See nrf.h." -#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */ -#include "compiler_abstraction.h" + /* Family selection for family includes. */ + #if defined (NRF51) + #include "nrf51.h" + #include "nrf51_bitfields.h" + #include "nrf51_deprecated.h" + #elif defined (NRF52) + #include "nrf52.h" + #include "nrf52_bitfields.h" + #include "nrf51_to_nrf52.h" + #include "nrf52_name_change.h" + #else + #error "Device family must be defined. See nrf.h." + #endif /* NRF51, NRF52 */ + + #include "compiler_abstraction.h" + +#endif /* _WIN32 || __unix || __APPLE__ */ #endif /* NRF_H */ diff --git a/cores/nRF5/SDK/components/device/nrf51.h b/cores/nRF5/SDK/components/device/nrf51.h index 1498c180..b615497e 100755 --- a/cores/nRF5/SDK/components/device/nrf51.h +++ b/cores/nRF5/SDK/components/device/nrf51.h @@ -1,40 +1,46 @@ -/* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * + +/****************************************************************************************************//** * @file nrf51.h - * @brief CMSIS HeaderFile - * @version 522 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:07 - * from File 'nrf51.svd', - * last modified on Wednesday, 04.11.2020 12:48:00 - */ + * + * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for + * nrf51 from Nordic Semiconductor. + * + * @version V522 + * @date 23. February 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf51.svd' Version 522, + * + * @par Copyright (c) 2013, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ @@ -42,12 +48,10 @@ * @{ */ - /** @addtogroup nrf51 * @{ */ - #ifndef NRF51_H #define NRF51_H @@ -56,1249 +60,1226 @@ extern "C" { #endif -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ +/* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { -/* ======================================= ARM Cortex-M0 Specific Interrupt Numbers ======================================== */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ -/* =========================================== nrf51 Specific Interrupt Numbers ============================================ */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UART0_IRQn = 2, /*!< 2 UART0 */ - SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ - SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - ADC_IRQn = 7, /*!< 7 ADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ - SWI0_IRQn = 20, /*!< 20 SWI0 */ - SWI1_IRQn = 21, /*!< 21 SWI1 */ - SWI2_IRQn = 22, /*!< 22 SWI2 */ - SWI3_IRQn = 23, /*!< 23 SWI3 */ - SWI4_IRQn = 24, /*!< 24 SWI4 */ - SWI5_IRQn = 25 /*!< 25 SWI5 */ +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UART0_IRQn = 2, /*!< 2 UART0 */ + SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ + SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + ADC_IRQn = 7, /*!< 7 ADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ + SWI0_IRQn = 20, /*!< 20 SWI0 */ + SWI1_IRQn = 21, /*!< 21 SWI1 */ + SWI2_IRQn = 22, /*!< 22 SWI2 */ + SWI3_IRQn = 23, /*!< 23 SWI3 */ + SWI4_IRQn = 24, /*!< 24 SWI4 */ + SWI5_IRQn = 25 /*!< 25 SWI5 */ } IRQn_Type; +/** @addtogroup Configuration_of_CMSIS + * @{ + */ -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================== Configuration of the ARM Cortex-M0 Processor and Core Peripherals =========================== */ -#define __CM0_REV 0x0301U /*!< CM0 Core Revision */ -#define __DSP_PRESENT 0 /*!< DSP present or not */ -#define __VTOR_PRESENT 0 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 0 /*!< MPU present */ -#define __FPU_PRESENT 0 /*!< FPU present */ +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** @} */ /* End of group Configuration_of_CMSIS */ -#include "core_cm0.h" /*!< ARM Cortex-M0 processor and core peripherals */ -#include "system_nrf51.h" /*!< nrf51 System */ +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_nrf51.h" /*!< nrf51 System */ -#ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO -#endif +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ -/* ======================================== Start of section using anonymous unions ======================================== */ -#if defined (__CC_ARM) + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) #pragma push #pragma anon_unions -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) +#elif defined(__GNUC__) /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - - -/** - * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks.) - */ typedef struct { - __OM uint32_t EN; /*!< (@ 0x00000000) Enable channel group. */ - __OM uint32_t DIS; /*!< (@ 0x00000004) Disable channel group. */ -} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */ + __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */ + __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */ + __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */ + __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */ + __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ +} AMLI_RAMPRI_Type; - -/** - * @brief PPI_CH [CH] (PPI Channel.) - */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Channel event end-point. */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Channel task end-point. */ -} PPI_CH_Type; /*!< Size = 8 (0x8) */ - - -/** @} */ /* End of group Device_Peripheral_clusters */ - + __IO uint32_t SCK; /*!< Pin select for SCK. */ + __IO uint32_t MOSI; /*!< Pin select for MOSI. */ + __IO uint32_t MISO; /*!< Pin select for MISO. */ +} SPIM_PSEL_Type; -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ + __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ +} SPIM_RXD_Type; +typedef struct { + __IO uint32_t PTR; /*!< Data pointer. */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ + __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ +} SPIM_TXD_Type; -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ +typedef struct { + __O uint32_t EN; /*!< Enable channel group. */ + __O uint32_t DIS; /*!< Disable channel group. */ +} PPI_TASKS_CHG_Type; +typedef struct { + __IO uint32_t EEP; /*!< Channel event end-point. */ + __IO uint32_t TEP; /*!< Channel task end-point. */ +} PPI_CH_Type; -/* =========================================================================================================================== */ -/* ================ POWER ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ /** * @brief Power Control. (POWER) */ -typedef struct { /*!< (@ 0x40000000) POWER Structure */ - __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode. */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency). */ - __IM uint32_t RESERVED1[34]; - __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning. */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[61]; - __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason. */ - __IM uint32_t RESERVED4[9]; - __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Ram status register. */ - __IM uint32_t RESERVED5[53]; - __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System off register. */ - __IM uint32_t RESERVED6[3]; - __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure configuration. */ - __IM uint32_t RESERVED7[2]; - __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register. This register - is a retained register. */ - __IM uint32_t RESERVED8; - __IOM uint32_t RAMON; /*!< (@ 0x00000524) Ram on/off. */ - __IM uint32_t RESERVED9[7]; - __IOM uint32_t RESET; /*!< (@ 0x00000544) Pin reset functionality configuration register. - This register is a retained register. */ - __IM uint32_t RESERVED10[3]; - __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Ram on/off. */ - __IM uint32_t RESERVED11[8]; - __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DCDC converter enable configuration register. */ - __IM uint32_t RESERVED12[291]; - __IOM uint32_t DCDCFORCE; /*!< (@ 0x00000A08) DCDC power-up force register. */ -} NRF_POWER_Type; /*!< Size = 2572 (0xa0c) */ - - - -/* =========================================================================================================================== */ -/* ================ CLOCK ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __IO uint32_t RESETREAS; /*!< Reset reason. */ + __I uint32_t RESERVED4[9]; + __I uint32_t RAMSTATUS; /*!< Ram status register. */ + __I uint32_t RESERVED5[53]; + __O uint32_t SYSTEMOFF; /*!< System off register. */ + __I uint32_t RESERVED6[3]; + __IO uint32_t POFCON; /*!< Power failure configuration. */ + __I uint32_t RESERVED7[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained + register. */ + __I uint32_t RESERVED8; + __IO uint32_t RAMON; /*!< Ram on/off. */ + __I uint32_t RESERVED9[7]; + __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register + is a retained register. */ + __I uint32_t RESERVED10[3]; + __IO uint32_t RAMONB; /*!< Ram on/off. */ + __I uint32_t RESERVED11[8]; + __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ + __I uint32_t RESERVED12[291]; + __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ /** * @brief Clock control. (CLOCK) */ -typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ - __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK clock source. */ - __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK clock source. */ - __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK clock source. */ - __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK clock source. */ - __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFCLK RC oscillator. */ - __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer. */ - __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer. */ - __IM uint32_t RESERVED[57]; - __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started. */ - __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK oscillator started. */ - __IM uint32_t RESERVED1; - __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator completed. */ - __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout. */ - __IM uint32_t RESERVED2[124]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[63]; - __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Task HFCLKSTART trigger status. */ - __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) High frequency clock status. */ - __IM uint32_t RESERVED4; - __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Task LFCLKSTART triggered status. */ - __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) Low frequency clock status. */ - __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Clock source for the LFCLK clock, set when task - LKCLKSTART is triggered. */ - __IM uint32_t RESERVED5[62]; - __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK clock. */ - __IM uint32_t RESERVED6[7]; - __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval. */ - __IM uint32_t RESERVED7[5]; - __IOM uint32_t XTALFREQ; /*!< (@ 0x00000550) Crystal frequency. */ -} NRF_CLOCK_Type; /*!< Size = 1364 (0x554) */ - - - -/* =========================================================================================================================== */ -/* ================ MPU ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ + __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ + __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ + __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is + triggered. */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval. */ + __I uint32_t RESERVED7[5]; + __IO uint32_t XTALFREQ; /*!< Crystal frequency. */ +} NRF_CLOCK_Type; + + +/* ================================================================================ */ +/* ================ MPU ================ */ +/* ================================================================================ */ /** * @brief Memory Protection Unit. (MPU) */ -typedef struct { /*!< (@ 0x40000000) MPU Structure */ - __IM uint32_t RESERVED[330]; - __IOM uint32_t PERR0; /*!< (@ 0x00000528) Configuration of peripherals in mpu regions. */ - __IOM uint32_t RLENR0; /*!< (@ 0x0000052C) Length of RAM region 0. */ - __IM uint32_t RESERVED1[52]; - __IOM uint32_t PROTENSET0; /*!< (@ 0x00000600) Erase and write protection bit enable set register. */ - __IOM uint32_t PROTENSET1; /*!< (@ 0x00000604) Erase and write protection bit enable set register. */ - __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable erase and write protection mechanism - in debug mode. */ - __IOM uint32_t PROTBLOCKSIZE; /*!< (@ 0x0000060C) Erase and write protection block size. */ -} NRF_MPU_Type; /*!< Size = 1552 (0x610) */ +typedef struct { /*!< MPU Structure */ + __I uint32_t RESERVED0[330]; + __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ + __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ + __I uint32_t RESERVED1[52]; + __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ + __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ +} NRF_MPU_Type; - -/* =========================================================================================================================== */ -/* ================ RADIO ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ AMLI ================ */ +/* ================================================================================ */ /** - * @brief The radio. (RADIO) + * @brief AHB Multi-Layer Interface. (AMLI) */ -typedef struct { /*!< (@ 0x40001000) RADIO Structure */ - __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable radio in TX mode. */ - __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable radio in RX mode. */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start radio. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop radio. */ - __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable radio. */ - __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one sample of the receive - signal strength. */ - __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement. */ - __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter. */ - __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter. */ - __IM uint32_t RESERVED[55]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) Ready event. */ - __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address event. */ - __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Payload event. */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) End event. */ - __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) Disable event. */ - __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received - packet. */ - __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last - received packet. */ - __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of the receive signal strength complete. - A new RSSI sample is ready for readout at - the RSSISAMPLE register. */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value specified - in BCC register. */ - __IM uint32_t RESERVED2[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the radio. */ - __IM uint32_t RESERVED3[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED4[61]; - __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status of received packet. */ - __IM uint32_t RESERVED5; - __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address. */ - __IM uint32_t RXCRC; /*!< (@ 0x0000040C) Received CRC. */ - __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index. */ - __IM uint32_t RESERVED6[60]; - __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer. Decision point: START task. */ - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency. */ - __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power. */ - __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation. */ - __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration 0. */ - __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration 1. */ - __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Radio base address 0. Decision point: START task. */ - __IOM uint32_t BASE1; /*!< (@ 0x00000520) Radio base address 1. Decision point: START task. */ - __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0 to 3. */ - __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4 to 7. */ - __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select. */ - __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select. */ - __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration. */ - __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial. */ - __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value. */ - __IOM uint32_t TEST; /*!< (@ 0x00000540) Test features enable register. */ - __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in microseconds. */ - __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample. */ - __IM uint32_t RESERVED7; - __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state. */ - __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value. */ - __IM uint32_t RESERVED8[2]; - __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare. */ - __IM uint32_t RESERVED9[39]; - __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Device address base segment. */ - __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Device address prefix. */ - __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration. */ - __IM uint32_t RESERVED10[56]; - __IOM uint32_t OVERRIDE0; /*!< (@ 0x00000724) Trim value override register 0. */ - __IOM uint32_t OVERRIDE1; /*!< (@ 0x00000728) Trim value override register 1. */ - __IOM uint32_t OVERRIDE2; /*!< (@ 0x0000072C) Trim value override register 2. */ - __IOM uint32_t OVERRIDE3; /*!< (@ 0x00000730) Trim value override register 3. */ - __IOM uint32_t OVERRIDE4; /*!< (@ 0x00000734) Trim value override register 4. */ - __IM uint32_t RESERVED11[561]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< AMLI Structure */ + __I uint32_t RESERVED0[896]; + AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */ +} NRF_AMLI_Type; + + +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ /** - * @brief Universal Asynchronous Receiver/Transmitter. (UART0) + * @brief The radio. (RADIO) */ -typedef struct { /*!< (@ 0x40002000) UART0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver. */ - __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver. */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter. */ - __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter. */ - __IM uint32_t RESERVED[3]; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART. */ - __IM uint32_t RESERVED1[56]; - __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS activated. */ - __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS deactivated. */ - __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD. */ - __IM uint32_t RESERVED2[4]; - __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD. */ - __IM uint32_t RESERVED3; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected. */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout. */ - __IM uint32_t RESERVED5[46]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for UART. */ - __IM uint32_t RESERVED6[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED7[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source. Write error field to 1 to clear - error. */ - __IM uint32_t RESERVED8[31]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART and acquire IOs. */ - __IM uint32_t RESERVED9; - __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS. */ - __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD. */ - __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS. */ - __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD. */ - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register. On read action the buffer pointer - is displaced. Once read the character is - consumed. If read when no character available, - the UART will stop working. */ - __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register. */ - __IM uint32_t RESERVED10; - __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) UART Baudrate. */ - __IM uint32_t RESERVED11[17]; - __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control - register. */ - __IM uint32_t RESERVED12[675]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_UART_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI0 ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */ + __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */ + __O uint32_t TASKS_START; /*!< Start radio. */ + __O uint32_t TASKS_STOP; /*!< Stop radio. */ + __O uint32_t TASKS_DISABLE; /*!< Disable radio. */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */ + __I uint32_t RESERVED0[55]; + __IO uint32_t EVENTS_READY; /*!< Ready event. */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */ + __IO uint32_t EVENTS_END; /*!< End event. */ + __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI + sample is ready for readout at the RSSISAMPLE register. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */ + __I uint32_t RESERVED2[53]; + __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED4[61]; + __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ + __I uint32_t RESERVED5; + __I uint32_t RXMATCH; /*!< Received address. */ + __I uint32_t RXCRC; /*!< Received CRC. */ + __I uint32_t DAI; /*!< Device address match index. */ + __I uint32_t RESERVED6[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ + __IO uint32_t FREQUENCY; /*!< Frequency. */ + __IO uint32_t TXPOWER; /*!< Output power. */ + __IO uint32_t MODE; /*!< Data rate and modulation. */ + __IO uint32_t PCNF0; /*!< Packet configuration 0. */ + __IO uint32_t PCNF1; /*!< Packet configuration 1. */ + __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */ + __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */ + __IO uint32_t TXADDRESS; /*!< Transmit address select. */ + __IO uint32_t RXADDRESSES; /*!< Receive address select. */ + __IO uint32_t CRCCNF; /*!< CRC configuration. */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial. */ + __IO uint32_t CRCINIT; /*!< CRC initial value. */ + __IO uint32_t TEST; /*!< Test features enable register. */ + __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ + __I uint32_t RESERVED7; + __I uint32_t STATE; /*!< Current radio state. */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ + __I uint32_t RESERVED8[2]; + __IO uint32_t BCC; /*!< Bit counter compare. */ + __I uint32_t RESERVED9[39]; + __IO uint32_t DAB[8]; /*!< Device address base segment. */ + __IO uint32_t DAP[8]; /*!< Device address prefix. */ + __IO uint32_t DACNF; /*!< Device address match configuration. */ + __I uint32_t RESERVED10[56]; + __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ + __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ + __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ + __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ + __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ + __I uint32_t RESERVED11[561]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ /** - * @brief SPI master 0. (SPI0) + * @brief Universal Asynchronous Receiver/Transmitter. (UART) */ -typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ - __IM uint32_t RESERVED[66]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received. */ - __IM uint32_t RESERVED1[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED2[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI. */ - __IM uint32_t RESERVED3; - __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ - __IOM uint32_t PSELMOSI; /*!< (@ 0x0000050C) Pin select for MOSI. */ - __IOM uint32_t PSELMISO; /*!< (@ 0x00000510) Pin select for MISO. */ - __IM uint32_t RESERVED4; - __IM uint32_t RXD; /*!< (@ 0x00000518) RX data. */ - __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data. */ - __IM uint32_t RESERVED5; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ - __IM uint32_t RESERVED6[11]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ - __IM uint32_t RESERVED7[681]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_SPI_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ TWI0 ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS activated. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected. */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */ + __I uint32_t RESERVED9; + __IO uint32_t PSELRTS; /*!< Pin select for RTS. */ + __IO uint32_t PSELTXD; /*!< Pin select for TXD. */ + __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ + __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ + __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. + Once read the character is consumed. If read when no character + available, the UART will stop working. */ + __O uint32_t TXD; /*!< TXD register. */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< UART Baudrate. */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */ + __I uint32_t RESERVED12[675]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ /** - * @brief Two-wire interface master 0. (TWI0) + * @brief SPI master 0. (SPI) */ -typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start 2-Wire master receive sequence. */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start 2-Wire master transmit sequence. */ - __IM uint32_t RESERVED1[2]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop 2-Wire transaction. */ - __IM uint32_t RESERVED2; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend 2-Wire transaction. */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume 2-Wire transaction. */ - __IM uint32_t RESERVED3[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Two-wire stopped. */ - __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) Two-wire ready to deliver new RXD byte received. */ - __IM uint32_t RESERVED4[4]; - __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) Two-wire finished sending last TXD byte. */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Two-wire error detected. */ - __IM uint32_t RESERVED6[4]; - __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) Two-wire byte boundary. */ - __IM uint32_t RESERVED7[3]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Two-wire suspended. */ - __IM uint32_t RESERVED8[45]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for TWI. */ - __IM uint32_t RESERVED9[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED10[110]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Two-wire error source. Write error field to 1 - to clear error. */ - __IM uint32_t RESERVED11[14]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable two-wire master. */ - __IM uint32_t RESERVED12; - __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL. */ - __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA. */ - __IM uint32_t RESERVED13[2]; - __IM uint32_t RXD; /*!< (@ 0x00000518) RX data register. */ - __IOM uint32_t TXD; /*!< (@ 0x0000051C) TX data register. */ - __IM uint32_t RESERVED14; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) Two-wire frequency. */ - __IM uint32_t RESERVED15[24]; - __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the two-wire transfer. */ - __IM uint32_t RESERVED16[668]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_TWI_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ SPIS1 ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI. */ + __I uint32_t RESERVED3; + __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ + __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ + __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RX data. */ + __IO uint32_t TXD; /*!< TX data. */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED7[681]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ /** - * @brief SPI slave 1. (SPIS1) + * @brief Two-wire interface master 0. (TWI) */ -typedef struct { /*!< (@ 0x40004000) SPIS1 Structure */ - __IM uint32_t RESERVED[9]; - __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore. */ - __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore. */ - __IM uint32_t RESERVED1[54]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed. */ - __IM uint32_t RESERVED2[2]; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired. */ - __IM uint32_t RESERVED4[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for SPIS. */ - __IM uint32_t RESERVED5[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED6[61]; - __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status. */ - __IM uint32_t RESERVED7[15]; - __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction. */ - __IM uint32_t RESERVED8[47]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIS. */ - __IM uint32_t RESERVED9; - __IOM uint32_t PSELSCK; /*!< (@ 0x00000508) Pin select for SCK. */ - __IOM uint32_t PSELMISO; /*!< (@ 0x0000050C) Pin select for MISO. */ - __IOM uint32_t PSELMOSI; /*!< (@ 0x00000510) Pin select for MOSI. */ - __IOM uint32_t PSELCSN; /*!< (@ 0x00000514) Pin select for CSN. */ - __IM uint32_t RESERVED10[7]; - __IOM uint32_t RXDPTR; /*!< (@ 0x00000534) RX data pointer. */ - __IOM uint32_t MAXRX; /*!< (@ 0x00000538) Maximum number of bytes in the receive buffer. */ - __IM uint32_t AMOUNTRX; /*!< (@ 0x0000053C) Number of bytes received in last granted transaction. */ - __IM uint32_t RESERVED11; - __IOM uint32_t TXDPTR; /*!< (@ 0x00000544) TX data pointer. */ - __IOM uint32_t MAXTX; /*!< (@ 0x00000548) Maximum number of bytes in the transmit buffer. */ - __IM uint32_t AMOUNTTX; /*!< (@ 0x0000054C) Number of bytes transmitted in last granted transaction. */ - __IM uint32_t RESERVED12; - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register. */ - __IM uint32_t RESERVED13; - __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. */ - __IM uint32_t RESERVED14[24]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. */ - __IM uint32_t RESERVED15[654]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_SPIS_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ GPIOTE ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */ + __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable two-wire master. */ + __I uint32_t RESERVED12; + __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ + __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RX data register. */ + __IO uint32_t TXD; /*!< TX data register. */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ + __I uint32_t RESERVED16[668]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ /** - * @brief GPIO tasks and events. (GPIOTE) + * @brief SPI slave 1. (SPIS) */ -typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ - __OM uint32_t TASKS_OUT[4]; /*!< (@ 0x00000000) Tasks asssociated with GPIOTE channels. */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_IN[4]; /*!< (@ 0x00000100) Tasks asssociated with GPIOTE channels. */ - __IM uint32_t RESERVED1[27]; - __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple pins. */ - __IM uint32_t RESERVED2[97]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[129]; - __IOM uint32_t CONFIG[4]; /*!< (@ 0x00000510) Channel configuration registers. */ - __IM uint32_t RESERVED4[695]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_GPIOTE_Type; /*!< Size = 4096 (0x1000) */ +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status. */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction. */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPIS. */ + __I uint32_t RESERVED9; + __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ + __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ + __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ + __IO uint32_t PSELCSN; /*!< Pin select for CSN. */ + __I uint32_t RESERVED10[7]; + __IO uint32_t RXDPTR; /*!< RX data pointer. */ + __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ + __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ + __I uint32_t RESERVED11; + __IO uint32_t TXDPTR; /*!< TX data pointer. */ + __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ + __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED15[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ +/** + * @brief SPI master with easyDMA 1. (SPIM) + */ -/* =========================================================================================================================== */ -/* ================ ADC ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction. */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */ + __I uint32_t RESERVED4[3]; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */ + __I uint32_t RESERVED5[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */ + __I uint32_t RESERVED6[109]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED7[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM. */ + __I uint32_t RESERVED8; + SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */ + __I uint32_t RESERVED9[4]; + __IO uint32_t FREQUENCY; /*!< SPI frequency. */ + __I uint32_t RESERVED10[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */ + __I uint32_t RESERVED11; + SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED13[26]; + __IO uint32_t ORC; /*!< Over-read character. */ + __I uint32_t RESERVED14[654]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ /** - * @brief Analog to digital converter. (ADC) + * @brief GPIO tasks and events. (GPIOTE) */ -typedef struct { /*!< (@ 0x40007000) ADC Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start an ADC conversion. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop ADC. */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) ADC conversion complete. */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED2[61]; - __IM uint32_t BUSY; /*!< (@ 0x00000400) ADC busy register. */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) ADC enable. */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) ADC configuration register. */ - __IM uint32_t RESULT; /*!< (@ 0x00000508) Result of ADC conversion. */ - __IM uint32_t RESERVED4[700]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_ADC_Type; /*!< Size = 4096 (0x1000) */ +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ + __I uint32_t RESERVED1[27]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */ + __I uint32_t RESERVED2[97]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[129]; + __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ + __I uint32_t RESERVED4[695]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_GPIOTE_Type; +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ -/* =========================================================================================================================== */ -/* ================ TIMER0 ================ */ -/* =========================================================================================================================== */ + +/** + * @brief Analog to digital converter. (ADC) + */ + +typedef struct { /*!< ADC Structure */ + __O uint32_t TASKS_START; /*!< Start an ADC conversion. */ + __O uint32_t TASKS_STOP; /*!< Stop ADC. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[61]; + __I uint32_t BUSY; /*!< ADC busy register. */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< ADC enable. */ + __IO uint32_t CONFIG; /*!< ADC configuration register. */ + __I uint32_t RESULT; /*!< Result of ADC conversion. */ + __I uint32_t RESERVED4[700]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_ADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ /** - * @brief Timer 0. (TIMER0) + * @brief Timer 0. (TIMER) */ -typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer. */ - __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (In counter mode). */ - __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear timer. */ - __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Shutdown timer. */ - __IM uint32_t RESERVED[11]; - __OM uint32_t TASKS_CAPTURE[4]; /*!< (@ 0x00000040) Capture Timer value to CC[n] registers. */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ - __IM uint32_t RESERVED2[44]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for Timer. */ - __IM uint32_t RESERVED3[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED4[126]; - __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer Mode selection. */ - __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Sets timer behaviour. */ - __IM uint32_t RESERVED5; - __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) 4-bit prescaler to source clock frequency (max - value 9). Source clock frequency is divided - by 2^SCALE. */ - __IM uint32_t RESERVED6[11]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ - __IM uint32_t RESERVED7[683]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_TIMER_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ RTC0 ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer. */ + __O uint32_t TASKS_STOP; /*!< Stop Timer. */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ + __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ + __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ + __I uint32_t RESERVED2[44]; + __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED4[126]; + __IO uint32_t MODE; /*!< Timer Mode selection. */ + __IO uint32_t BITMODE; /*!< Sets timer behaviour. */ + __I uint32_t RESERVED5; + __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source + clock frequency is divided by 2^SCALE. */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CC[4]; /*!< Capture/compare registers. */ + __I uint32_t RESERVED7[683]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ /** - * @brief Real time counter 0. (RTC0) + * @brief Real time counter 0. (RTC) */ -typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC Counter. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC Counter. */ - __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC Counter. */ - __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFFFF0. */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment. */ - __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow. */ - __IM uint32_t RESERVED1[14]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Compare event on CC[n] match. */ - __IM uint32_t RESERVED2[109]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[13]; - __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Configures event enable routing to PPI for each - RTC event. */ - __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable events routing to PPI. The reading of - this register gives the value of EVTEN. */ - __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable events routing to PPI. The reading of - this register gives the value of EVTEN. */ - __IM uint32_t RESERVED4[110]; - __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value. */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). - Must be written when RTC is STOPed. */ - __IM uint32_t RESERVED5[13]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Capture/compare registers. */ - __IM uint32_t RESERVED6[683]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_RTC_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ TEMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC Counter. */ + __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */ + __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives + the value of EVTEN. */ + __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register + gives the value of EVTEN. */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value. */ + __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is STOPed. */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Capture/compare registers. */ + __I uint32_t RESERVED6[683]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ /** * @brief Temperature Sensor. (TEMP) */ -typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement. */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready - event. */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED2[127]; - __IM int32_t TEMP; /*!< (@ 0x00000508) Die temperature in degC, 2's complement format, - 0.25 degC pecision. */ - __IM uint32_t RESERVED3[700]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_TEMP_Type; /*!< Size = 4096 (0x1000) */ - +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement. */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ + __I uint32_t RESERVED3[700]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_TEMP_Type; -/* =========================================================================================================================== */ -/* ================ RNG ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ /** * @brief Random Number Generator. (RNG) */ -typedef struct { /*!< (@ 0x4000D000) RNG Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the random number generator. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the random number generator. */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) New random number generated and written to VALUE - register. */ - __IM uint32_t RESERVED1[63]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the RNG. */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register */ - __IM uint32_t RESERVED3[126]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ - __IM uint32_t VALUE; /*!< (@ 0x00000508) RNG random number. */ - __IM uint32_t RESERVED4[700]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_RNG_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ ECB ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Start the random number generator. */ + __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t VALUE; /*!< RNG random number. */ + __I uint32_t RESERVED4[700]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_RNG_Type; + + +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ /** * @brief AES ECB Mode Encryption. (ECB) */ -typedef struct { /*!< (@ 0x4000E000) ECB Structure */ - __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt. If a crypto operation - is running, this will not initiate a new - encryption and the ERRORECB event will be - triggered. */ - __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Stop current ECB encryption. If a crypto operation - is running, this will will trigger the ERRORECB - event. */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete. */ - __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted due to a STOPECB task - or due to an error. */ - __IM uint32_t RESERVED1[127]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointer. */ - __IM uint32_t RESERVED3[701]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_ECB_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ AAR ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this + will not initiate a new encryption and the ERRORECB event will + be triggered. */ + __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, + this will will trigger the ERRORECB event. */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an + error. */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */ + __I uint32_t RESERVED3[701]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_ECB_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ /** * @brief Accelerated Address Resolver. (AAR) */ -typedef struct { /*!< (@ 0x4000F000) AAR Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified - in the IRK data structure. */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses. */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure completed. */ - __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved. */ - __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved. */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status. */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR. */ - __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of Identity root Keys in the IRK data - structure. */ - __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to the IRK data structure. */ - __IM uint32_t RESERVED5; - __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address (6 bytes). */ - __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary - storage during resolution. A minimum of - 3 bytes must be reserved. */ - __IM uint32_t RESERVED6[697]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_AAR_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ CCM ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure. */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status. */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR. */ + __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */ + __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during + resolution. A minimum of 3 bytes must be reserved. */ + __I uint32_t RESERVED6[697]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ /** * @brief AES CCM Mode Encryption. (CCM) */ -typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation - will stop by itself when completed. */ - __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encrypt/decrypt. This operation will stop - by itself when completed. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encrypt/decrypt. */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation completed. */ - __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt completed. */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Error happened. */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the CCM. */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) CCM RX MIC check result. */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) CCM enable. */ - __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode. */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to a data structure holding AES key and - NONCE vector. */ - __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Pointer to the input packet. */ - __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Pointer to the output packet. */ - __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to a scratch data area used for temporary - storage during resolution. A minimum of - 43 bytes must be reserved. */ - __IM uint32_t RESERVED5[697]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_CCM_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ WDT ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when + completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ + __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< CCM enable. */ + __IO uint32_t MODE; /*!< Operation mode. */ + __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ + __IO uint32_t INPTR; /*!< Pointer to the input packet. */ + __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during + resolution. A minimum of 43 bytes must be reserved. */ + __I uint32_t RESERVED5[697]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ /** * @brief Watchdog Timer. (WDT) */ -typedef struct { /*!< (@ 0x40010000) WDT Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog. */ - __IM uint32_t RESERVED[63]; - __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout. */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED2[61]; - __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Watchdog running status. */ - __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status. */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value in number of 32kiHz clock - cycles. */ - __IOM uint32_t RREN; /*!< (@ 0x00000508) Reload request enable. */ - __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register. */ - __IM uint32_t RESERVED4[60]; - __OM uint32_t RR[8]; /*!< (@ 0x00000600) Reload requests registers. */ - __IM uint32_t RESERVED5[631]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_WDT_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ QDEC ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Watchdog running status. */ + __I uint32_t REQSTATUS; /*!< Request status. */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */ + __IO uint32_t RREN; /*!< Reload request enable. */ + __IO uint32_t CONFIG; /*!< Configuration register. */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Reload requests registers. */ + __I uint32_t RESERVED5[631]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_WDT_Type; + + +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ /** * @brief Rotary decoder. (QDEC) */ -typedef struct { /*!< (@ 0x40012000) QDEC Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the quadrature decoder. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the quadrature decoder. */ - __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Transfers the content from ACC registers to ACCREAD - registers, and clears the ACC registers. */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) A new sample is written to the sample register. */ - __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) REPORTPER number of samples accumulated in ACC - register, and ACC register different than - zero. */ - __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow. */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the QDEC. */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the QDEC. */ - __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity. */ - __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period. */ - __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value. */ - __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to generate an EVENT_REPORTRDY. */ - __IM int32_t ACC; /*!< (@ 0x00000514) Accumulated valid transitions register. */ - __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of ACC register. Value generated by - the TASKS_READCLEACC task. */ - __IOM uint32_t PSELLED; /*!< (@ 0x0000051C) Pin select for LED output. */ - __IOM uint32_t PSELA; /*!< (@ 0x00000520) Pin select for phase A input. */ - __IOM uint32_t PSELB; /*!< (@ 0x00000524) Pin select for phase B input. */ - __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable debouncer input filters. */ - __IM uint32_t RESERVED4[5]; - __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time LED is switched ON before the sample. */ - __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Accumulated double (error) transitions register. */ - __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of ACCDBL register. Value generated - by the TASKS_READCLEACC task. */ - __IM uint32_t RESERVED5[684]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_QDEC_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ LPCOMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */ + __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */ + __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, + and clears the ACC registers. */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */ + __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and + ACC register different than zero. */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the QDEC. */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity. */ + __IO uint32_t SAMPLEPER; /*!< Sample period. */ + __I int32_t SAMPLE; /*!< Motion sample value. */ + __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */ + __I int32_t ACC; /*!< Accumulated valid transitions register. */ + __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC + task. */ + __IO uint32_t PSELLED; /*!< Pin select for LED output. */ + __IO uint32_t PSELA; /*!< Pin select for phase A input. */ + __IO uint32_t PSELB; /*!< Pin select for phase B input. */ + __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */ + __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC + task. */ + __I uint32_t RESERVED5[684]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ /** * @brief Low power comparator. (LPCOMP) */ -typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the comparator. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop the comparator. */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value. */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid. */ - __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Input voltage crossed the threshold going down. */ - __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Input voltage crossed the threshold going up. */ - __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Input voltage crossed the threshold in any direction. */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts for the LPCOMP. */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Interrupt enable set register. */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Interrupt enable clear register. */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t RESULT; /*!< (@ 0x00000400) Result of last compare. */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the LPCOMP. */ - __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select. */ - __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select. */ - __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select. */ - __IM uint32_t RESERVED5[4]; - __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration. */ - __IM uint32_t RESERVED6[694]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control. */ -} NRF_LPCOMP_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ SWI ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start the comparator. */ + __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */ + __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ + __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ + __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ + __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Result of last compare. */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */ + __IO uint32_t PSEL; /*!< Input pin select. */ + __IO uint32_t REFSEL; /*!< Reference select. */ + __IO uint32_t EXTREFSEL; /*!< External reference select. */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration. */ + __I uint32_t RESERVED6[694]; + __IO uint32_t POWER; /*!< Peripheral power control. */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ /** * @brief SW Interrupts. (SWI) */ -typedef struct { /*!< (@ 0x40014000) SWI Structure */ - __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ -} NRF_SWI_Type; /*!< Size = 4 (0x4) */ +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; - -/* =========================================================================================================================== */ -/* ================ NVMC ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ /** * @brief Non Volatile Memory Controller. (NVMC) */ -typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ - __IM uint32_t RESERVED[256]; - __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag. */ - __IM uint32_t RESERVED1[64]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register. */ +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag. */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register. */ union { - __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile - memory page. */ - __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Register for erasing a non-protected non-volatile - memory page. */ + __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */ }; - __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory. */ - __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Register for erasing a protected non-volatile - memory page. */ - __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for start erasing User Information Congfiguration - Registers. */ -} NRF_NVMC_Type; /*!< Size = 1304 (0x518) */ - + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */ + __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */ + __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */ +} NRF_NVMC_Type; -/* =========================================================================================================================== */ -/* ================ PPI ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ /** * @brief PPI controller. (PPI) */ -typedef struct { /*!< (@ 0x4001F000) PPI Structure */ - __IOM PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< (@ 0x00000000) Channel group tasks. */ - __IM uint32_t RESERVED[312]; - __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable. */ - __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set. */ - __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear. */ - __IM uint32_t RESERVED1; - __IOM PPI_CH_Type CH[16]; /*!< (@ 0x00000510) PPI Channel. */ - __IM uint32_t RESERVED2[156]; - __IOM uint32_t CHG[4]; /*!< (@ 0x00000800) Channel group configuration. */ -} NRF_PPI_Type; /*!< Size = 2064 (0x810) */ - +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ + __I uint32_t RESERVED0[312]; + __IO uint32_t CHEN; /*!< Channel enable. */ + __IO uint32_t CHENSET; /*!< Channel enable set. */ + __IO uint32_t CHENCLR; /*!< Channel enable clear. */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[16]; /*!< PPI Channel. */ + __I uint32_t RESERVED2[156]; + __IO uint32_t CHG[4]; /*!< Channel group configuration. */ +} NRF_PPI_Type; -/* =========================================================================================================================== */ -/* ================ FICR ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ /** * @brief Factory Information Configuration. (FICR) */ -typedef struct { /*!< (@ 0x10000000) FICR Structure */ - __IM uint32_t RESERVED[4]; - __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size in bytes. */ - __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size in pages. */ - __IM uint32_t RESERVED1[4]; - __IM uint32_t CLENR0; /*!< (@ 0x00000028) Length of code region 0 in bytes. */ - __IM uint32_t PPFC; /*!< (@ 0x0000002C) Pre-programmed factory code present. */ - __IM uint32_t RESERVED2; - __IM uint32_t NUMRAMBLOCK; /*!< (@ 0x00000034) Number of individualy controllable RAM blocks. */ +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */ + __I uint32_t CODESIZE; /*!< Code memory size in pages. */ + __I uint32_t RESERVED1[4]; + __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */ + __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ + __I uint32_t RESERVED2; + __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ union { - __IM uint32_t SIZERAMBLOCKS; /*!< (@ 0x00000038) Size of RAM blocks in bytes. */ - __IM uint32_t SIZERAMBLOCK[4]; /*!< (@ 0x00000038) Deprecated array of size of RAM block in bytes. - This name is kept for backward compatinility - purposes. Use SIZERAMBLOCKS instead. */ + __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is + kept for backward compatinility purposes. Use SIZERAMBLOCKS + instead. */ + __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ }; - __IM uint32_t RESERVED3[5]; - __IM uint32_t CONFIGID; /*!< (@ 0x0000005C) Configuration identifier. */ - __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Device identifier. */ - __IM uint32_t RESERVED4[6]; - __IM uint32_t ER[4]; /*!< (@ 0x00000080) Encryption root. */ - __IM uint32_t IR[4]; /*!< (@ 0x00000090) Identity root. */ - __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type. */ - __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Device address. */ - __IM uint32_t OVERRIDEEN; /*!< (@ 0x000000AC) Radio calibration override enable. */ - __IM uint32_t NRF_1MBIT[5]; /*!< (@ 0x000000B0) Override values for the OVERRIDEn registers in - RADIO for NRF_1Mbit mode. */ - __IM uint32_t RESERVED5[10]; - __IM uint32_t BLE_1MBIT[5]; /*!< (@ 0x000000EC) Override values for the OVERRIDEn registers in - RADIO for BLE_1Mbit mode. */ -} NRF_FICR_Type; /*!< Size = 256 (0x100) */ - - - -/* =========================================================================================================================== */ -/* ================ UICR ================ */ -/* =========================================================================================================================== */ + __I uint32_t RESERVED3[5]; + __I uint32_t CONFIGID; /*!< Configuration identifier. */ + __I uint32_t DEVICEID[2]; /*!< Device identifier. */ + __I uint32_t RESERVED4[6]; + __I uint32_t ER[4]; /*!< Encryption root. */ + __I uint32_t IR[4]; /*!< Identity root. */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ + __I uint32_t DEVICEADDR[2]; /*!< Device address. */ + __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ + __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit + mode. */ + __I uint32_t RESERVED5[10]; + __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit + mode. */ +} NRF_FICR_Type; + + +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ /** * @brief User Information Configuration. (UICR) */ -typedef struct { /*!< (@ 0x10001000) UICR Structure */ - __IOM uint32_t CLENR0; /*!< (@ 0x00000000) Length of code region 0. */ - __IOM uint32_t RBPCONF; /*!< (@ 0x00000004) Readback protection configuration. */ - __IOM uint32_t XTALFREQ; /*!< (@ 0x00000008) Reset value for CLOCK XTALFREQ register. */ - __IM uint32_t RESERVED; - __IM uint32_t FWID; /*!< (@ 0x00000010) Firmware ID. */ +typedef struct { /*!< UICR Structure */ + __IO uint32_t CLENR0; /*!< Length of code region 0. */ + __IO uint32_t RBPCONF; /*!< Readback protection configuration. */ + __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */ + __I uint32_t RESERVED0; + __I uint32_t FWID; /*!< Firmware ID. */ union { - __IOM uint32_t BOOTLOADERADDR; /*!< (@ 0x00000014) Bootloader start address. */ - __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Reserved for Nordic firmware design. */ + __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ + __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */ }; - __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Reserved for Nordic hardware design. */ - __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Reserved for customer. */ -} NRF_UICR_Type; /*!< Size = 256 (0x100) */ + __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ + __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ +} NRF_UICR_Type; - -/* =========================================================================================================================== */ -/* ================ GPIO ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ /** * @brief General purpose input and output. (GPIO) */ -typedef struct { /*!< (@ 0x50000000) GPIO Structure */ - __IM uint32_t RESERVED[321]; - __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port. */ - __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port. */ - __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port. */ - __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port. */ - __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins. */ - __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register. */ - __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register. */ - __IM uint32_t RESERVED1[120]; - __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Configuration of GPIO pins. */ -} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define NRF_POWER_BASE 0x40000000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_MPU_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_ADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI_BASE 0x40014000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_GPIO_BASE 0x50000000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) -#define NRF_MPU ((NRF_MPU_Type*) NRF_MPU_BASE) -#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) -#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) -#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) -#define NRF_ADC ((NRF_ADC_Type*) NRF_ADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) -#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) -#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) -#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) -#define NRF_SWI ((NRF_SWI_Type*) NRF_SWI_BASE) -#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) -#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) -#define NRF_GPIO ((NRF_GPIO_Type*) NRF_GPIO_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - - -/* ========================================= End of section using anonymous unions ========================================= */ -#if defined (__CC_ARM) +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port. */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */ + __I uint32_t IN; /*!< Read GPIO port. */ + __IO uint32_t DIR; /*!< Direction of GPIO pins. */ + __IO uint32_t DIRSET; /*!< DIR set register. */ + __IO uint32_t DIRCLR; /*!< DIR clear register. */ + __I uint32_t RESERVED1[120]; + __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ +} NRF_GPIO_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) #pragma pop -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) /* leave anonymous unions enabled */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) +#elif defined(__GNUC__) /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) +#elif defined(__TMS470__) /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) +#elif defined(__TASKING__) #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type #endif + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_MPU_BASE 0x40000000UL +#define NRF_AMLI_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_ADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI_BASE 0x40014000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_GPIO_BASE 0x50000000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) +#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf51 */ +/** @} */ /* End of group Nordic Semiconductor */ + #ifdef __cplusplus } #endif -#endif /* NRF51_H */ +#endif /* nrf51_H */ -/** @} */ /* End of group nrf51 */ - -/** @} */ /* End of group Nordic Semiconductor */ diff --git a/cores/nRF5/SDK/components/device/nrf51422_peripherals.h b/cores/nRF5/SDK/components/device/nrf51422_peripherals.h index ce69474e..8aa49fca 100644 --- a/cores/nRF5/SDK/components/device/nrf51422_peripherals.h +++ b/cores/nRF5/SDK/components/device/nrf51422_peripherals.h @@ -1,54 +1,37 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - -/* This file is deprecated */ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef _NRF51422_PERIPHERALS_H #define _NRF51422_PERIPHERALS_H -/* Clock Peripheral */ -#define CLOCK_PRESENT -#define CLOCK_COUNT 1 - -/* Power Peripheral */ -#define POWER_PRESENT -#define POWER_COUNT 1 - -#define POWER_FEATURE_RAMON_REGISTERS_PRESENT - -/* Non-Volatile Memory Controller */ -#define NVMC_PRESENT -#define NVMC_COUNT 1 - /* Software Interrupts */ #define SWI_PRESENT #define SWI_COUNT 6 @@ -59,8 +42,6 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_PIN_NUM 32 -#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL - /* MPU and BPROT */ #define BPROT_PRESENT @@ -71,8 +52,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm - /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 @@ -92,7 +71,6 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_COUNT 1 #define PPI_CH_NUM 16 -#define PPI_FIXED_CH_NUM 12 #define PPI_GROUP_NUM 4 /* Timer/Counter */ @@ -134,8 +112,6 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PRESENT #define SPIS_COUNT 1 -#define SPIS1_EASYDMA_MAXCNT_SIZE 8 - /* Two Wire Interface Master */ #define TWI_PRESENT #define TWI_COUNT 2 diff --git a/cores/nRF5/SDK/components/device/nrf51802_peripherals.h b/cores/nRF5/SDK/components/device/nrf51802_peripherals.h index ebadd532..96b389a2 100644 --- a/cores/nRF5/SDK/components/device/nrf51802_peripherals.h +++ b/cores/nRF5/SDK/components/device/nrf51802_peripherals.h @@ -1,54 +1,37 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - -/* This file is deprecated */ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef _NRF51802_PERIPHERALS_H #define _NRF51802_PERIPHERALS_H -/* Clock Peripheral */ -#define CLOCK_PRESENT -#define CLOCK_COUNT 1 - -/* Power Peripheral */ -#define POWER_PRESENT -#define POWER_COUNT 1 - -#define POWER_FEATURE_RAMON_REGISTERS_PRESENT - -/* Non-Volatile Memory Controller */ -#define NVMC_PRESENT -#define NVMC_COUNT 1 - /* Software Interrupts */ #define SWI_PRESENT #define SWI_COUNT 6 @@ -59,8 +42,6 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_PIN_NUM 32 -#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL - /* MPU and BPROT */ #define BPROT_PRESENT @@ -71,8 +52,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm - /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 @@ -92,7 +71,6 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_COUNT 1 #define PPI_CH_NUM 16 -#define PPI_FIXED_CH_NUM 12 #define PPI_GROUP_NUM 4 /* Timer/Counter */ @@ -134,8 +112,6 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PRESENT #define SPIS_COUNT 1 -#define SPIS1_EASYDMA_MAXCNT_SIZE 8 - /* Two Wire Interface Master */ #define TWI_PRESENT #define TWI_COUNT 2 diff --git a/cores/nRF5/SDK/components/device/nrf51822_peripherals.h b/cores/nRF5/SDK/components/device/nrf51822_peripherals.h index e57ec795..38c32023 100644 --- a/cores/nRF5/SDK/components/device/nrf51822_peripherals.h +++ b/cores/nRF5/SDK/components/device/nrf51822_peripherals.h @@ -1,55 +1,37 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - - -/* This file is deprecated */ +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef _NRF51822_PERIPHERALS_H #define _NRF51822_PERIPHERALS_H -/* Clock Peripheral */ -#define CLOCK_PRESENT -#define CLOCK_COUNT 1 - -/* Power Peripheral */ -#define POWER_PRESENT -#define POWER_COUNT 1 - -#define POWER_FEATURE_RAMON_REGISTERS_PRESENT - -/* Non-Volatile Memory Controller */ -#define NVMC_PRESENT -#define NVMC_COUNT 1 - /* Software Interrupts */ #define SWI_PRESENT #define SWI_COUNT 6 @@ -60,8 +42,6 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_PIN_NUM 32 -#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL - /* MPU and BPROT */ #define BPROT_PRESENT @@ -72,8 +52,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm - /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 @@ -93,7 +71,6 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_COUNT 1 #define PPI_CH_NUM 16 -#define PPI_FIXED_CH_NUM 12 #define PPI_GROUP_NUM 4 /* Timer/Counter */ @@ -135,8 +112,6 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PRESENT #define SPIS_COUNT 1 -#define SPIS1_EASYDMA_MAXCNT_SIZE 8 - /* Two Wire Interface Master */ #define TWI_PRESENT #define TWI_COUNT 2 diff --git a/cores/nRF5/SDK/components/device/nrf51_bitfields.h b/cores/nRF5/SDK/components/device/nrf51_bitfields.h index 46508b77..5c5af9a6 100755 --- a/cores/nRF5/SDK/components/device/nrf51_bitfields.h +++ b/cores/nRF5/SDK/components/device/nrf51_bitfields.h @@ -1,35 +1,32 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef __NRF51_BITS_H #define __NRF51_BITS_H @@ -224,6 +221,604 @@ POSSIBILITY OF SUCH DAMAGE. #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +/* Peripheral: AMLI */ +/* Description: AHB Multi-Layer Interface. */ + +/* Register: AMLI_RAMPRI_CPU0 */ +/* Description: Configurable priority configuration register for CPU0. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_SPIS1 */ +/* Description: Configurable priority configuration register for SPIS1. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_RADIO */ +/* Description: Configurable priority configuration register for RADIO. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_ECB */ +/* Description: Configurable priority configuration register for ECB. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_CCM */ +/* Description: Configurable priority configuration register for CCM. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Register: AMLI_RAMPRI_AAR */ +/* Description: Configurable priority configuration register for AAR. */ + +/* Bits 31..28 : Configuration field for RAM block 7. */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 27..24 : Configuration field for RAM block 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 23..20 : Configuration field for RAM block 5. */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 19..16 : Configuration field for RAM block 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 15..12 : Configuration field for RAM block 3. */ +#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 11..8 : Configuration field for RAM block 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 7..4 : Configuration field for RAM block 1. */ +#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ + +/* Bits 3..0 : Configuration field for RAM block 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ + + /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption. */ @@ -2326,7 +2921,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is bellow the reference threshold. */ +#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ /* Register: LPCOMP_ENABLE */ @@ -5175,6 +5770,174 @@ POSSIBILITY OF SUCH DAMAGE. #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ +/* Peripheral: SPIM */ +/* Description: SPI master with easyDMA 1. */ + +/* Register: SPIM_INTENSET */ +/* Description: Interrupt enable set register. */ + +/* Bit 19 : Enable interrupt on STARTED event. */ +#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 8 : Enable interrupt on ENDTX event. */ +#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 4 : Enable interrupt on ENDRX event. */ +#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ + +/* Bit 1 : Enable interrupt on STOPPED event. */ +#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ + +/* Register: SPIM_INTENCLR */ +/* Description: Interrupt enable clear register. */ + +/* Bit 19 : Disable interrupt on STARTED event. */ +#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ +#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 8 : Disable interrupt on ENDTX event. */ +#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ +#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 4 : Disable interrupt on ENDRX event. */ +#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ +#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Bit 1 : Disable interrupt on STOPPED event. */ +#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ +#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ +#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ +#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ + +/* Register: SPIM_ENABLE */ +/* Description: Enable SPIM. */ + +/* Bits 3..0 : Enable or disable SPIM. */ +#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ +#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ +#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ + +/* Register: SPIM_FREQUENCY */ +/* Description: SPI frequency. */ + +/* Bits 31..0 : SPI master data rate. */ +#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ +#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ +#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ + +/* Register: SPIM_RXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_RXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to receive. */ + +/* Bits 7..0 : Maximum number of buffer bytes to receive. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_RXD_AMOUNT */ +/* Description: Number of bytes received in the last transaction. */ + +/* Bits 7..0 : Number of bytes received in the last transaction. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_TXD_PTR */ +/* Description: Data pointer. */ + +/* Bits 31..0 : Data pointer. */ +#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ +#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ + +/* Register: SPIM_TXD_MAXCNT */ +/* Description: Maximum number of buffer bytes to send. */ + +/* Bits 7..0 : Maximum number of buffer bytes to send. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ +#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ + +/* Register: SPIM_TXD_AMOUNT */ +/* Description: Number of bytes sent in the last transaction. */ + +/* Bits 7..0 : Number of bytes sent in the last transaction. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ +#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ + +/* Register: SPIM_CONFIG */ +/* Description: Configuration register. */ + +/* Bit 2 : Serial clock (SCK) polarity. */ +#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ +#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ +#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ +#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ + +/* Bit 1 : Serial clock (SCK) phase. */ +#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ +#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ +#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ +#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ + +/* Bit 0 : Bit order. */ +#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ +#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ +#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ +#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ + +/* Register: SPIM_ORC */ +/* Description: Over-read character. */ + +/* Bits 7..0 : Over-read character. */ +#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ +#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ + +/* Register: SPIM_POWER */ +/* Description: Peripheral power control. */ + +/* Bit 0 : Peripheral power control. */ +#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ +#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ +#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ +#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ + + /* Peripheral: SPIS */ /* Description: SPI slave 1. */ @@ -5694,7 +6457,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps). */ +#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ /* Register: TWI_ADDRESS */ /* Description: Address used in the two-wire transfer. */ @@ -5888,9 +6651,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ diff --git a/cores/nRF5/SDK/components/device/nrf51_deprecated.h b/cores/nRF5/SDK/components/device/nrf51_deprecated.h index b328d3cf..0c7d7dfd 100755 --- a/cores/nRF5/SDK/components/device/nrf51_deprecated.h +++ b/cores/nRF5/SDK/components/device/nrf51_deprecated.h @@ -1,34 +1,32 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef NRF51_DEPRECATED_H #define NRF51_DEPRECATED_H @@ -47,10 +45,8 @@ POSSIBILITY OF SUCH DAMAGE. /* LPCOMP */ /* The interrupt ISR was renamed. Adding old name to the macros. */ -#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler -#define LPCOMP_COMP_IRQn LPCOMP_IRQn -/* Corrected typo in RESULT register. */ -#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below +#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn LPCOMP_IRQn /* MPU */ @@ -432,11 +428,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included - -/* SPIS */ -/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */ -#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included diff --git a/cores/nRF5/SDK/components/device/nrf51_to_nrf52.h b/cores/nRF5/SDK/components/device/nrf51_to_nrf52.h index 4fd14863..16ae6f7f 100755 --- a/cores/nRF5/SDK/components/device/nrf51_to_nrf52.h +++ b/cores/nRF5/SDK/components/device/nrf51_to_nrf52.h @@ -1,34 +1,32 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef NRF51_TO_NRF52_H #define NRF51_TO_NRF52_H @@ -37,2315 +35,897 @@ POSSIBILITY OF SUCH DAMAGE. /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the - * functionality is gone, there old names are not defined, so compilation will fail. Note that also includes macros + * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros * from the nrf51_deprecated.h file. */ /* IRQ */ /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ -#ifndef UART0_IRQHandler - #define UART0_IRQHandler UARTE0_UART0_IRQHandler -#endif -#ifndef SPI0_TWI0_IRQHandler - #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler -#endif -#ifndef SPI1_TWI1_IRQHandler - #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler -#endif -#ifndef ADC_IRQHandler - #define ADC_IRQHandler SAADC_IRQHandler -#endif -#ifndef LPCOMP_IRQHandler - #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler -#endif -#ifndef SWI0_IRQHandler - #define SWI0_IRQHandler SWI0_EGU0_IRQHandler -#endif -#ifndef SWI1_IRQHandler - #define SWI1_IRQHandler SWI1_EGU1_IRQHandler -#endif -#ifndef SWI2_IRQHandler - #define SWI2_IRQHandler SWI2_EGU2_IRQHandler -#endif -#ifndef SWI3_IRQHandler - #define SWI3_IRQHandler SWI3_EGU3_IRQHandler -#endif -#ifndef SWI4_IRQHandler - #define SWI4_IRQHandler SWI4_EGU4_IRQHandler -#endif -#ifndef SWI5_IRQHandler - #define SWI5_IRQHandler SWI5_EGU5_IRQHandler -#endif - -#ifndef UART0_IRQn - #define UART0_IRQn UARTE0_UART0_IRQn -#endif -#ifndef SPI0_TWI0_IRQn - #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn -#endif -#ifndef SPI1_TWI1_IRQn - #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn -#endif -#ifndef ADC_IRQn - #define ADC_IRQn SAADC_IRQn -#endif -#ifndef LPCOMP_IRQn - #define LPCOMP_IRQn COMP_LPCOMP_IRQn -#endif -#ifndef SWI0_IRQn - #define SWI0_IRQn SWI0_EGU0_IRQn -#endif -#ifndef SWI1_IRQn - #define SWI1_IRQn SWI1_EGU1_IRQn -#endif -#ifndef SWI2_IRQn - #define SWI2_IRQn SWI2_EGU2_IRQn -#endif -#ifndef SWI3_IRQn - #define SWI3_IRQn SWI3_EGU3_IRQn -#endif -#ifndef SWI4_IRQn - #define SWI4_IRQn SWI4_EGU4_IRQn -#endif -#ifndef SWI5_IRQn - #define SWI5_IRQn SWI5_EGU5_IRQn -#endif +#define UART0_IRQHandler UARTE0_UART0_IRQHandler +#define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler +#define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler +#define ADC_IRQHandler SAADC_IRQHandler +#define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler +#define SWI0_IRQHandler SWI0_EGU0_IRQHandler +#define SWI1_IRQHandler SWI1_EGU1_IRQHandler +#define SWI2_IRQHandler SWI2_EGU2_IRQHandler +#define SWI3_IRQHandler SWI3_EGU3_IRQHandler +#define SWI4_IRQHandler SWI4_EGU4_IRQHandler +#define SWI5_IRQHandler SWI5_EGU5_IRQHandler + +#define UART0_IRQn UARTE0_UART0_IRQn +#define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn +#define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn +#define ADC_IRQn SAADC_IRQn +#define LPCOMP_IRQn COMP_LPCOMP_IRQn +#define SWI0_IRQn SWI0_EGU0_IRQn +#define SWI1_IRQn SWI1_EGU1_IRQn +#define SWI2_IRQn SWI2_EGU2_IRQn +#define SWI3_IRQn SWI3_EGU3_IRQn +#define SWI4_IRQn SWI4_EGU4_IRQn +#define SWI5_IRQn SWI5_EGU5_IRQn /* UICR */ /* Register RBPCONF was renamed to APPROTECT. */ -#ifndef RBPCONF - #define RBPCONF APPROTECT -#endif - -#ifndef UICR_RBPCONF_PALL_Pos - #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos -#endif -#ifndef UICR_RBPCONF_PALL_Msk - #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk -#endif -#ifndef UICR_RBPCONF_PALL_Enabled - #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled -#endif -#ifndef UICR_RBPCONF_PALL_Disabled - #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled -#endif +#define RBPCONF APPROTECT + +#define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos +#define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk +#define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled +#define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled + /* GPIO */ /* GPIO port was renamed to P0. */ -#ifndef NRF_GPIO - #define NRF_GPIO NRF_P0 -#endif -#ifndef NRF_GPIO_BASE - #define NRF_GPIO_BASE NRF_P0_BASE -#endif - -/* QDEC */ -/* The registers PSELA, PSELB and PSELLED were restructured into a struct. */ -#ifndef PSELLED - #define PSELLED PSEL.LED -#endif -#ifndef PSELA - #define PSELA PSEL.A -#endif -#ifndef PSELB - #define PSELB PSEL.B -#endif +#define NRF_GPIO NRF_P0 +#define NRF_GPIO_BASE NRF_P0_BASE /* SPIS */ /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ -#ifndef PSELSCK - #define PSELSCK PSEL.SCK -#endif -#ifndef PSELMISO - #define PSELMISO PSEL.MISO -#endif -#ifndef PSELMOSI - #define PSELMOSI PSEL.MOSI -#endif -#ifndef PSELCSN - #define PSELCSN PSEL.CSN -#endif +#define PSELSCK PSEL.SCK +#define PSELMISO PSEL.MISO +#define PSELMOSI PSEL.MOSI +#define PSELCSN PSEL.CSN /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ -#ifndef RXDPTR - #define RXDPTR RXD.PTR -#endif -#ifndef MAXRX - #define MAXRX RXD.MAXCNT -#endif -#ifndef AMOUNTRX - #define AMOUNTRX RXD.AMOUNT -#endif - -#ifndef SPIS_MAXRX_MAXRX_Pos - #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos -#endif -#ifndef SPIS_MAXRX_MAXRX_Msk - #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk -#endif - -#ifndef SPIS_AMOUNTRX_AMOUNTRX_Pos - #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos -#endif -#ifndef SPIS_AMOUNTRX_AMOUNTRX_Msk - #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk -#endif +#define RXDPTR RXD.PTR +#define MAXRX RXD.MAXCNT +#define AMOUNTRX RXD.AMOUNT + +#define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ -#ifndef TXDPTR - #define TXDPTR TXD.PTR -#endif -#ifndef MAXTX - #define MAXTX TXD.MAXCNT -#endif -#ifndef AMOUNTTX - #define AMOUNTTX TXD.AMOUNT -#endif - -#ifndef SPIS_MAXTX_MAXTX_Pos - #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos -#endif -#ifndef SPIS_MAXTX_MAXTX_Msk - #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk -#endif - -#ifndef SPIS_AMOUNTTX_AMOUNTTX_Pos - #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos -#endif -#ifndef SPIS_AMOUNTTX_AMOUNTTX_Msk - #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk -#endif +#define TXDPTR TXD.PTR +#define MAXTX TXD.MAXCNT +#define AMOUNTTX TXD.AMOUNT + +#define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos +#define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk + +#define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos +#define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk + /* MPU */ /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ -#ifndef NRF_MPU - #define NRF_MPU NRF_BPROT -#endif +#define NRF_MPU NRF_BPROT /* Register DISABLEINDEBUG macros were affected. */ -#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos - #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos -#endif -#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk - #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk -#endif -#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled - #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled -#endif -#ifndef MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled - #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled -#endif +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled +#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ -#ifndef PROTENSET0 - #define PROTENSET0 CONFIG0 -#endif -#ifndef PROTENSET1 - #define PROTENSET1 CONFIG1 -#endif - -#ifndef MPU_PROTENSET1_PROTREG63_Pos - #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG63_Msk - #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG63_Disabled - #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG63_Enabled - #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG63_Set - #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG62_Pos - #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG62_Msk - #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG62_Disabled - #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG62_Enabled - #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG62_Set - #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG61_Pos - #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG61_Msk - #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG61_Disabled - #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG61_Enabled - #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG61_Set - #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG60_Pos - #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG60_Msk - #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG60_Disabled - #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG60_Enabled - #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG60_Set - #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG59_Pos - #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG59_Msk - #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG59_Disabled - #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG59_Enabled - #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG59_Set - #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG58_Pos - #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG58_Msk - #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG58_Disabled - #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG58_Enabled - #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG58_Set - #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG57_Pos - #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG57_Msk - #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG57_Disabled - #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG57_Enabled - #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG57_Set - #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG56_Pos - #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG56_Msk - #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG56_Disabled - #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG56_Enabled - #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG56_Set - #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG55_Pos - #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG55_Msk - #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG55_Disabled - #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG55_Enabled - #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG55_Set - #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG54_Pos - #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG54_Msk - #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG54_Disabled - #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG54_Enabled - #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG54_Set - #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG53_Pos - #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG53_Msk - #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG53_Disabled - #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG53_Enabled - #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG53_Set - #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG52_Pos - #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG52_Msk - #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG52_Disabled - #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG52_Enabled - #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG52_Set - #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG51_Pos - #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG51_Msk - #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG51_Disabled - #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG51_Enabled - #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG51_Set - #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG50_Pos - #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG50_Msk - #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG50_Disabled - #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG50_Enabled - #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG50_Set - #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG49_Pos - #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG49_Msk - #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG49_Disabled - #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG49_Enabled - #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG49_Set - #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG48_Pos - #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG48_Msk - #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG48_Disabled - #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG48_Enabled - #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG48_Set - #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG47_Pos - #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG47_Msk - #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG47_Disabled - #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG47_Enabled - #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG47_Set - #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG46_Pos - #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG46_Msk - #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG46_Disabled - #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG46_Enabled - #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG46_Set - #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG45_Pos - #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG45_Msk - #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG45_Disabled - #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG45_Enabled - #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG45_Set - #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG44_Pos - #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG44_Msk - #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG44_Disabled - #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG44_Enabled - #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG44_Set - #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG43_Pos - #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG43_Msk - #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG43_Disabled - #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG43_Enabled - #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG43_Set - #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG42_Pos - #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG42_Msk - #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG42_Disabled - #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG42_Enabled - #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG42_Set - #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG41_Pos - #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG41_Msk - #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG41_Disabled - #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG41_Enabled - #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG41_Set - #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG40_Pos - #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG40_Msk - #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG40_Disabled - #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG40_Enabled - #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG40_Set - #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG39_Pos - #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG39_Msk - #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG39_Disabled - #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG39_Enabled - #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG39_Set - #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG38_Pos - #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG38_Msk - #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG38_Disabled - #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG38_Enabled - #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG38_Set - #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG37_Pos - #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG37_Msk - #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG37_Disabled - #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG37_Enabled - #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG37_Set - #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG36_Pos - #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG36_Msk - #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG36_Disabled - #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG36_Enabled - #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG36_Set - #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG35_Pos - #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG35_Msk - #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG35_Disabled - #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG35_Enabled - #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG35_Set - #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG34_Pos - #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG34_Msk - #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG34_Disabled - #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG34_Enabled - #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG34_Set - #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG33_Pos - #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG33_Msk - #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG33_Disabled - #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG33_Enabled - #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG33_Set - #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled -#endif - -#ifndef MPU_PROTENSET1_PROTREG32_Pos - #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos -#endif -#ifndef MPU_PROTENSET1_PROTREG32_Msk - #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk -#endif -#ifndef MPU_PROTENSET1_PROTREG32_Disabled - #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled -#endif -#ifndef MPU_PROTENSET1_PROTREG32_Enabled - #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled -#endif -#ifndef MPU_PROTENSET1_PROTREG32_Set - #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG31_Pos - #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG31_Msk - #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG31_Disabled - #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG31_Enabled - #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG31_Set - #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG30_Pos - #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG30_Msk - #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG30_Disabled - #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG30_Enabled - #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG30_Set - #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG29_Pos - #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG29_Msk - #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG29_Disabled - #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG29_Enabled - #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG29_Set - #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG28_Pos - #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG28_Msk - #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG28_Disabled - #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG28_Enabled - #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG28_Set - #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG27_Pos - #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG27_Msk - #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG27_Disabled - #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG27_Enabled - #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG27_Set - #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG26_Pos - #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG26_Msk - #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG26_Disabled - #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG26_Enabled - #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG26_Set - #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG25_Pos - #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG25_Msk - #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG25_Disabled - #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG25_Enabled - #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG25_Set - #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG24_Pos - #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG24_Msk - #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG24_Disabled - #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG24_Enabled - #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG24_Set - #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG23_Pos - #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG23_Msk - #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG23_Disabled - #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG23_Enabled - #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG23_Set - #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG22_Pos - #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG22_Msk - #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG22_Disabled - #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG22_Enabled - #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG22_Set - #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG21_Pos - #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG21_Msk - #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG21_Disabled - #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG21_Enabled - #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG21_Set - #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG20_Pos - #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG20_Msk - #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG20_Disabled - #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG20_Enabled - #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG20_Set - #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG19_Pos - #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG19_Msk - #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG19_Disabled - #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG19_Enabled - #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG19_Set - #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG18_Pos - #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG18_Msk - #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG18_Disabled - #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG18_Enabled - #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG18_Set - #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG17_Pos - #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG17_Msk - #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG17_Disabled - #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG17_Enabled - #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG17_Set - #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG16_Pos - #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG16_Msk - #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG16_Disabled - #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG16_Enabled - #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG16_Set - #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG16_Set - #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG15_Msk - #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG15_Disabled - #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG15_Enabled - #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG15_Set - #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG14_Pos - #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG14_Msk - #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG14_Disabled - #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG14_Enabled - #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG14_Set - #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG13_Pos - #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG13_Msk - #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG13_Disabled - #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG13_Enabled - #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG13_Set - #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG12_Pos - #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG12_Msk - #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG12_Disabled - #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG12_Enabled - #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG12_Set - #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG11_Pos - #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG11_Msk - #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG11_Disabled - #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG11_Enabled - #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG11_Set - #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG10_Pos - #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG10_Msk - #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG10_Disabled - #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG10_Enabled - #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG10_Set - #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG9_Pos - #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG9_Msk - #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG9_Disabled - #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG9_Enabled - #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG9_Set - #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG8_Pos - #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG8_Msk - #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG8_Disabled - #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG8_Enabled - #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG8_Set - #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG7_Pos - #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG7_Msk - #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG7_Disabled - #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG7_Enabled - #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG7_Set - #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG6_Pos - #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG6_Msk - #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG6_Disabled - #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG6_Enabled - #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG6_Set - #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG5_Pos - #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG5_Msk - #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG5_Disabled - #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG5_Enabled - #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG5_Set - #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG4_Pos - #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG4_Msk - #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG4_Disabled - #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG4_Enabled - #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG4_Set - #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG3_Pos - #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG3_Msk - #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG3_Disabled - #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG3_Enabled - #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG3_Set - #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG2_Pos - #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG2_Msk - #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG2_Disabled - #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG2_Enabled - #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG2_Set - #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG1_Pos - #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG1_Msk - #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG1_Disabled - #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG1_Enabled - #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG1_Set - #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled -#endif - -#ifndef MPU_PROTENSET0_PROTREG0_Pos - #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos -#endif -#ifndef MPU_PROTENSET0_PROTREG0_Msk - #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk -#endif -#ifndef MPU_PROTENSET0_PROTREG0_Disabled - #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled -#endif -#ifndef MPU_PROTENSET0_PROTREG0_Enabled - #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled -#endif -#ifndef MPU_PROTENSET0_PROTREG0_Set - #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled -#endif +#define PROTENSET0 CONFIG0 +#define PROTENSET1 CONFIG1 + +#define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos +#define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk +#define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled +#define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled +#define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled + +#define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos +#define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk +#define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled +#define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled +#define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled + +#define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos +#define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk +#define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled +#define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled +#define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled + +#define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos +#define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk +#define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled +#define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled +#define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled + +#define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos +#define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk +#define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled +#define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled +#define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled + +#define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos +#define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk +#define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled +#define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled +#define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled + +#define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos +#define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk +#define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled +#define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled +#define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled + +#define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos +#define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk +#define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled +#define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled +#define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled + +#define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos +#define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk +#define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled +#define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled +#define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled + +#define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos +#define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk +#define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled +#define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled +#define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled + +#define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos +#define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk +#define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled +#define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled +#define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled + +#define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos +#define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk +#define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled +#define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled +#define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled + +#define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos +#define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk +#define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled +#define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled +#define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled + +#define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos +#define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk +#define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled +#define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled +#define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled + +#define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos +#define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk +#define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled +#define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled +#define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled + +#define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos +#define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk +#define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled +#define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled +#define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled + +#define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos +#define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk +#define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled +#define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled +#define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled + +#define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos +#define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk +#define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled +#define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled +#define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled + +#define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos +#define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk +#define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled +#define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled +#define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled + +#define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos +#define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk +#define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled +#define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled +#define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled + +#define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos +#define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk +#define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled +#define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled +#define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled + +#define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos +#define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk +#define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled +#define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled +#define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled + +#define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos +#define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk +#define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled +#define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled +#define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled + +#define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos +#define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk +#define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled +#define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled +#define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled + +#define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos +#define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk +#define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled +#define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled +#define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled + +#define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos +#define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk +#define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled +#define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled +#define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled + +#define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos +#define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk +#define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled +#define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled +#define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled + +#define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos +#define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk +#define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled +#define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled +#define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled + +#define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos +#define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk +#define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled +#define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled +#define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled + +#define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos +#define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk +#define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled +#define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled +#define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled + +#define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos +#define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk +#define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled +#define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled +#define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled + +#define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos +#define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk +#define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled +#define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled +#define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled + +#define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos +#define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk +#define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled +#define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled +#define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled + +#define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos +#define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk +#define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled +#define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled +#define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled + +#define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos +#define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk +#define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled +#define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled +#define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled + +#define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos +#define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk +#define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled +#define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled +#define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled + +#define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos +#define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk +#define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled +#define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled +#define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled + +#define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos +#define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk +#define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled +#define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled +#define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled + +#define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos +#define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk +#define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled +#define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled +#define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled + +#define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos +#define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk +#define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled +#define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled +#define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled + +#define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos +#define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk +#define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled +#define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled +#define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled + +#define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos +#define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk +#define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled +#define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled +#define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled + +#define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos +#define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk +#define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled +#define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled +#define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled + +#define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos +#define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk +#define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled +#define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled +#define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled + +#define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos +#define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk +#define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled +#define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled +#define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled + +#define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos +#define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk +#define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled +#define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled +#define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled + +#define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos +#define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk +#define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled +#define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled +#define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled + +#define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos +#define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk +#define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled +#define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled +#define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled + +#define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos +#define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk +#define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled +#define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled +#define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled + +#define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos +#define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk +#define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled +#define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled +#define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled + +#define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos +#define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk +#define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled +#define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled +#define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled + +#define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos +#define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk +#define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled +#define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled +#define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled + +#define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos +#define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk +#define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled +#define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled +#define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled + +#define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos +#define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk +#define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled +#define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled +#define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled + +#define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos +#define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk +#define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled +#define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled +#define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled + +#define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos +#define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk +#define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled +#define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled +#define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled + +#define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos +#define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk +#define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled +#define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled +#define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled + +#define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos +#define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk +#define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled +#define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled +#define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled + +#define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos +#define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk +#define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled +#define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled +#define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled + +#define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos +#define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk +#define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled +#define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled +#define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled + +#define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos +#define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk +#define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled +#define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled +#define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled + +#define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos +#define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk +#define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled +#define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled +#define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled + +#define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos +#define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk +#define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled +#define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled +#define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled + +#define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos +#define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk +#define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled +#define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled +#define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled /* From nrf51_deprecated.h */ /* NVMC */ /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ -#ifndef ERASEPROTECTEDPAGE - #define ERASEPROTECTEDPAGE ERASEPCR0 -#endif +#define ERASEPROTECTEDPAGE ERASEPCR0 /* IRQ */ /* COMP module was eliminated. Adapted to nrf52 headers. */ -#ifndef LPCOMP_COMP_IRQHandler - #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler -#endif -#ifndef LPCOMP_COMP_IRQn - #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn -#endif - - -/* REFSEL register redefined enumerated values and added some more. */ -#ifndef LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling LPCOMP_REFSEL_REFSEL_Ref1_8Vdd -#endif -#ifndef LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref2_8Vdd -#endif -#ifndef LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref3_8Vdd -#endif -#ifndef LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref4_8Vdd -#endif -#ifndef LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref5_8Vdd -#endif -#ifndef LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref6_8Vdd -#endif -#ifndef LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling - #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling LPCOMP_REFSEL_REFSEL_Ref7_8Vdd -#endif +#define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler +#define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn + /* RADIO */ /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ -#ifndef RADIO_CRCCNF_SKIP_ADDR_Pos - #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos -#endif -#ifndef RADIO_CRCCNF_SKIP_ADDR_Msk - #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk -#endif -#ifndef RADIO_CRCCNF_SKIP_ADDR_Include - #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include -#endif -#ifndef RADIO_CRCCNF_SKIP_ADDR_Skip - #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip -#endif +#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos +#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk +#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include +#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip /* FICR */ /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ -#ifndef DEVICEID0 - #define DEVICEID0 DEVICEID[0] -#endif -#ifndef DEVICEID1 - #define DEVICEID1 DEVICEID[1] -#endif +#define DEVICEID0 DEVICEID[0] +#define DEVICEID1 DEVICEID[1] /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ -#ifndef ER0 - #define ER0 ER[0] -#endif -#ifndef ER1 - #define ER1 ER[1] -#endif -#ifndef ER2 - #define ER2 ER[2] -#endif -#ifndef ER3 - #define ER3 ER[3] -#endif +#define ER0 ER[0] +#define ER1 ER[1] +#define ER2 ER[2] +#define ER3 ER[3] /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ -#ifndef IR0 - #define IR0 IR[0] -#endif -#ifndef IR1 - #define IR1 IR[1] -#endif -#ifndef IR2 - #define IR2 IR[2] -#endif -#ifndef IR3 - #define IR3 IR[3] -#endif +#define IR0 IR[0] +#define IR1 IR[1] +#define IR2 IR[2] +#define IR3 IR[3] /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ -#ifndef DEVICEADDR0 - #define DEVICEADDR0 DEVICEADDR[0] -#endif -#ifndef DEVICEADDR1 - #define DEVICEADDR1 DEVICEADDR[1] -#endif +#define DEVICEADDR0 DEVICEADDR[0] +#define DEVICEADDR1 DEVICEADDR[1] /* PPI */ /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ -#ifndef TASKS_CHG0EN - #define TASKS_CHG0EN TASKS_CHG[0].EN -#endif -#ifndef TASKS_CHG0DIS - #define TASKS_CHG0DIS TASKS_CHG[0].DIS -#endif -#ifndef TASKS_CHG1EN - #define TASKS_CHG1EN TASKS_CHG[1].EN -#endif -#ifndef TASKS_CHG1DIS - #define TASKS_CHG1DIS TASKS_CHG[1].DIS -#endif -#ifndef TASKS_CHG2EN - #define TASKS_CHG2EN TASKS_CHG[2].EN -#endif -#ifndef TASKS_CHG2DIS - #define TASKS_CHG2DIS TASKS_CHG[2].DIS -#endif -#ifndef TASKS_CHG3EN - #define TASKS_CHG3EN TASKS_CHG[3].EN -#endif -#ifndef TASKS_CHG3DIS - #define TASKS_CHG3DIS TASKS_CHG[3].DIS -#endif +#define TASKS_CHG0EN TASKS_CHG[0].EN +#define TASKS_CHG0DIS TASKS_CHG[0].DIS +#define TASKS_CHG1EN TASKS_CHG[1].EN +#define TASKS_CHG1DIS TASKS_CHG[1].DIS +#define TASKS_CHG2EN TASKS_CHG[2].EN +#define TASKS_CHG2DIS TASKS_CHG[2].DIS +#define TASKS_CHG3EN TASKS_CHG[3].EN +#define TASKS_CHG3DIS TASKS_CHG[3].DIS /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ -#ifndef CH0_EEP - #define CH0_EEP CH[0].EEP -#endif -#ifndef CH0_TEP - #define CH0_TEP CH[0].TEP -#endif -#ifndef CH1_EEP - #define CH1_EEP CH[1].EEP -#endif -#ifndef CH1_TEP - #define CH1_TEP CH[1].TEP -#endif -#ifndef CH2_EEP - #define CH2_EEP CH[2].EEP -#endif -#ifndef CH2_TEP - #define CH2_TEP CH[2].TEP -#endif -#ifndef CH3_EEP - #define CH3_EEP CH[3].EEP -#endif -#ifndef CH3_TEP - #define CH3_TEP CH[3].TEP -#endif -#ifndef CH4_EEP - #define CH4_EEP CH[4].EEP -#endif -#ifndef CH4_TEP - #define CH4_TEP CH[4].TEP -#endif -#ifndef CH5_EEP - #define CH5_EEP CH[5].EEP -#endif -#ifndef CH5_TEP - #define CH5_TEP CH[5].TEP -#endif -#ifndef CH6_EEP - #define CH6_EEP CH[6].EEP -#endif -#ifndef CH6_TEP - #define CH6_TEP CH[6].TEP -#endif -#ifndef CH7_EEP - #define CH7_EEP CH[7].EEP -#endif -#ifndef CH7_TEP - #define CH7_TEP CH[7].TEP -#endif -#ifndef CH8_EEP - #define CH8_EEP CH[8].EEP -#endif -#ifndef CH8_TEP - #define CH8_TEP CH[8].TEP -#endif -#ifndef CH9_EEP - #define CH9_EEP CH[9].EEP -#endif -#ifndef CH9_TEP - #define CH9_TEP CH[9].TEP -#endif -#ifndef CH10_EEP - #define CH10_EEP CH[10].EEP -#endif -#ifndef CH10_TEP - #define CH10_TEP CH[10].TEP -#endif -#ifndef CH11_EEP - #define CH11_EEP CH[11].EEP -#endif -#ifndef CH11_TEP - #define CH11_TEP CH[11].TEP -#endif -#ifndef CH12_EEP - #define CH12_EEP CH[12].EEP -#endif -#ifndef CH12_TEP - #define CH12_TEP CH[12].TEP -#endif -#ifndef CH13_EEP - #define CH13_EEP CH[13].EEP -#endif -#ifndef CH13_TEP - #define CH13_TEP CH[13].TEP -#endif -#ifndef CH14_EEP - #define CH14_EEP CH[14].EEP -#endif -#ifndef CH14_TEP - #define CH14_TEP CH[14].TEP -#endif -#ifndef CH15_EEP - #define CH15_EEP CH[15].EEP -#endif -#ifndef CH15_TEP - #define CH15_TEP CH[15].TEP -#endif +#define CH0_EEP CH[0].EEP +#define CH0_TEP CH[0].TEP +#define CH1_EEP CH[1].EEP +#define CH1_TEP CH[1].TEP +#define CH2_EEP CH[2].EEP +#define CH2_TEP CH[2].TEP +#define CH3_EEP CH[3].EEP +#define CH3_TEP CH[3].TEP +#define CH4_EEP CH[4].EEP +#define CH4_TEP CH[4].TEP +#define CH5_EEP CH[5].EEP +#define CH5_TEP CH[5].TEP +#define CH6_EEP CH[6].EEP +#define CH6_TEP CH[6].TEP +#define CH7_EEP CH[7].EEP +#define CH7_TEP CH[7].TEP +#define CH8_EEP CH[8].EEP +#define CH8_TEP CH[8].TEP +#define CH9_EEP CH[9].EEP +#define CH9_TEP CH[9].TEP +#define CH10_EEP CH[10].EEP +#define CH10_TEP CH[10].TEP +#define CH11_EEP CH[11].EEP +#define CH11_TEP CH[11].TEP +#define CH12_EEP CH[12].EEP +#define CH12_TEP CH[12].TEP +#define CH13_EEP CH[13].EEP +#define CH13_TEP CH[13].TEP +#define CH14_EEP CH[14].EEP +#define CH14_TEP CH[14].TEP +#define CH15_EEP CH[15].EEP +#define CH15_TEP CH[15].TEP /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ -#ifndef CHG0 - #define CHG0 CHG[0] -#endif -#ifndef CHG1 - #define CHG1 CHG[1] -#endif -#ifndef CHG2 - #define CHG2 CHG[2] -#endif -#ifndef CHG3 - #define CHG3 CHG[3] -#endif +#define CHG0 CHG[0] +#define CHG1 CHG[1] +#define CHG2 CHG[2] +#define CHG3 CHG[3] /* All bitfield macros for the CHGx registers therefore changed name. */ -#ifndef PPI_CHG0_CH15_Pos - #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos -#endif -#ifndef PPI_CHG0_CH15_Msk - #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk -#endif -#ifndef PPI_CHG0_CH15_Excluded - #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded -#endif -#ifndef PPI_CHG0_CH15_Included - #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included -#endif - -#ifndef PPI_CHG0_CH14_Pos - #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos -#endif -#ifndef PPI_CHG0_CH14_Msk - #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk -#endif -#ifndef PPI_CHG0_CH14_Excluded - #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded -#endif -#ifndef PPI_CHG0_CH14_Included - #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included -#endif - -#ifndef PPI_CHG0_CH13_Pos - #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos -#endif -#ifndef PPI_CHG0_CH13_Msk - #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk -#endif -#ifndef PPI_CHG0_CH13_Excluded - #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded -#endif -#ifndef PPI_CHG0_CH13_Included - #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included -#endif - -#ifndef PPI_CHG0_CH12_Pos - #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos -#endif -#ifndef PPI_CHG0_CH12_Msk - #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk -#endif -#ifndef PPI_CHG0_CH12_Excluded - #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded -#endif -#ifndef PPI_CHG0_CH12_Included - #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included -#endif - -#ifndef PPI_CHG0_CH11_Pos - #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos -#endif -#ifndef PPI_CHG0_CH11_Msk - #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk -#endif -#ifndef PPI_CHG0_CH11_Excluded - #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded -#endif -#ifndef PPI_CHG0_CH11_Included - #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included -#endif - -#ifndef PPI_CHG0_CH10_Pos - #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos -#endif -#ifndef PPI_CHG0_CH10_Msk - #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk -#endif -#ifndef PPI_CHG0_CH10_Excluded - #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded -#endif -#ifndef PPI_CHG0_CH10_Included - #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included -#endif - -#ifndef PPI_CHG0_CH9_Pos - #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos -#endif -#ifndef PPI_CHG0_CH9_Msk - #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk -#endif -#ifndef PPI_CHG0_CH9_Excluded - #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded -#endif -#ifndef PPI_CHG0_CH9_Included - #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included -#endif - -#ifndef PPI_CHG0_CH8_Pos - #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos -#endif -#ifndef PPI_CHG0_CH8_Msk - #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk -#endif -#ifndef PPI_CHG0_CH8_Excluded - #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded -#endif -#ifndef PPI_CHG0_CH8_Included - #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included -#endif - -#ifndef PPI_CHG0_CH7_Pos - #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos -#endif -#ifndef PPI_CHG0_CH7_Msk - #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk -#endif -#ifndef PPI_CHG0_CH7_Excluded - #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded -#endif -#ifndef PPI_CHG0_CH7_Included - #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included -#endif - -#ifndef PPI_CHG0_CH6_Pos - #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos -#endif -#ifndef PPI_CHG0_CH6_Msk - #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk -#endif -#ifndef PPI_CHG0_CH6_Excluded - #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded -#endif -#ifndef PPI_CHG0_CH6_Included - #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included -#endif - -#ifndef PPI_CHG0_CH5_Pos - #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos -#endif -#ifndef PPI_CHG0_CH5_Msk - #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk -#endif -#ifndef PPI_CHG0_CH5_Excluded - #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded -#endif -#ifndef PPI_CHG0_CH5_Included - #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included -#endif - -#ifndef PPI_CHG0_CH4_Pos - #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos -#endif -#ifndef PPI_CHG0_CH4_Msk - #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk -#endif -#ifndef PPI_CHG0_CH4_Excluded - #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded -#endif -#ifndef PPI_CHG0_CH4_Included - #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included -#endif - -#ifndef PPI_CHG0_CH3_Pos - #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos -#endif -#ifndef PPI_CHG0_CH3_Msk - #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk -#endif -#ifndef PPI_CHG0_CH3_Excluded - #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded -#endif -#ifndef PPI_CHG0_CH3_Included - #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included -#endif - -#ifndef PPI_CHG0_CH2_Pos - #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos -#endif -#ifndef PPI_CHG0_CH2_Msk - #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk -#endif -#ifndef PPI_CHG0_CH2_Excluded - #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded -#endif -#ifndef PPI_CHG0_CH2_Included - #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included -#endif - -#ifndef PPI_CHG0_CH1_Pos - #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos -#endif -#ifndef PPI_CHG0_CH1_Msk - #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk -#endif -#ifndef PPI_CHG0_CH1_Excluded - #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded -#endif -#ifndef PPI_CHG0_CH1_Included - #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included -#endif - -#ifndef PPI_CHG0_CH0_Pos - #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos -#endif -#ifndef PPI_CHG0_CH0_Msk - #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk -#endif -#ifndef PPI_CHG0_CH0_Excluded - #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded -#endif -#ifndef PPI_CHG0_CH0_Included - #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included -#endif - -#ifndef PPI_CHG1_CH15_Pos - #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos -#endif -#ifndef PPI_CHG1_CH15_Msk - #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk -#endif -#ifndef PPI_CHG1_CH15_Excluded - #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded -#endif -#ifndef PPI_CHG1_CH15_Included - #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included -#endif - -#ifndef PPI_CHG1_CH14_Pos - #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos -#endif -#ifndef PPI_CHG1_CH14_Msk - #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk -#endif -#ifndef PPI_CHG1_CH14_Excluded - #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded -#endif -#ifndef PPI_CHG1_CH14_Included - #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included -#endif - -#ifndef PPI_CHG1_CH13_Pos - #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos -#endif -#ifndef PPI_CHG1_CH13_Msk - #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk -#endif -#ifndef PPI_CHG1_CH13_Excluded - #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded -#endif -#ifndef PPI_CHG1_CH13_Included - #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included -#endif - -#ifndef PPI_CHG1_CH12_Pos - #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos -#endif -#ifndef PPI_CHG1_CH12_Msk - #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk -#endif -#ifndef PPI_CHG1_CH12_Excluded - #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded -#endif -#ifndef PPI_CHG1_CH12_Included - #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included -#endif - -#ifndef PPI_CHG1_CH11_Pos - #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos -#endif -#ifndef PPI_CHG1_CH11_Msk - #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk -#endif -#ifndef PPI_CHG1_CH11_Excluded - #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded -#endif -#ifndef PPI_CHG1_CH11_Included - #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included -#endif - -#ifndef PPI_CHG1_CH10_Pos - #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos -#endif -#ifndef PPI_CHG1_CH10_Msk - #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk -#endif -#ifndef PPI_CHG1_CH10_Excluded - #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded -#endif -#ifndef PPI_CHG1_CH10_Included - #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included -#endif - -#ifndef PPI_CHG1_CH9_Pos - #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos -#endif -#ifndef PPI_CHG1_CH9_Msk - #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk -#endif -#ifndef PPI_CHG1_CH9_Excluded - #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded -#endif -#ifndef PPI_CHG1_CH9_Included - #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included -#endif - -#ifndef PPI_CHG1_CH8_Pos - #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos -#endif -#ifndef PPI_CHG1_CH8_Msk - #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk -#endif -#ifndef PPI_CHG1_CH8_Excluded - #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded -#endif -#ifndef PPI_CHG1_CH8_Included - #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included -#endif - -#ifndef PPI_CHG1_CH7_Pos - #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos -#endif -#ifndef PPI_CHG1_CH7_Msk - #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk -#endif -#ifndef PPI_CHG1_CH7_Excluded - #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded -#endif -#ifndef PPI_CHG1_CH7_Included - #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included -#endif - -#ifndef PPI_CHG1_CH6_Pos - #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos -#endif -#ifndef PPI_CHG1_CH6_Msk - #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk -#endif -#ifndef PPI_CHG1_CH6_Excluded - #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded -#endif -#ifndef PPI_CHG1_CH6_Included - #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included -#endif - -#ifndef PPI_CHG1_CH5_Pos - #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos -#endif -#ifndef PPI_CHG1_CH5_Msk - #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk -#endif -#ifndef PPI_CHG1_CH5_Excluded - #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded -#endif -#ifndef PPI_CHG1_CH5_Included - #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included -#endif - -#ifndef PPI_CHG1_CH4_Pos - #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos -#endif -#ifndef PPI_CHG1_CH4_Msk - #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk -#endif -#ifndef PPI_CHG1_CH4_Excluded - #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded -#endif -#ifndef PPI_CHG1_CH4_Included - #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included -#endif - -#ifndef PPI_CHG1_CH3_Pos - #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos -#endif -#ifndef PPI_CHG1_CH3_Msk - #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk -#endif -#ifndef PPI_CHG1_CH3_Excluded - #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded -#endif -#ifndef PPI_CHG1_CH3_Included - #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included -#endif - -#ifndef PPI_CHG1_CH2_Pos - #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos -#endif -#ifndef PPI_CHG1_CH2_Msk - #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk -#endif -#ifndef PPI_CHG1_CH2_Excluded - #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded -#endif -#ifndef PPI_CHG1_CH2_Included - #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included -#endif - -#ifndef PPI_CHG1_CH1_Pos - #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos -#endif -#ifndef PPI_CHG1_CH1_Msk - #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk -#endif -#ifndef PPI_CHG1_CH1_Excluded - #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded -#endif -#ifndef PPI_CHG1_CH1_Included - #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included -#endif - -#ifndef PPI_CHG1_CH0_Pos - #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos -#endif -#ifndef PPI_CHG1_CH0_Msk - #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk -#endif -#ifndef PPI_CHG1_CH0_Excluded - #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded -#endif -#ifndef PPI_CHG1_CH0_Included - #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included -#endif - -#ifndef PPI_CHG2_CH15_Pos - #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos -#endif -#ifndef PPI_CHG2_CH15_Msk - #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk -#endif -#ifndef PPI_CHG2_CH15_Excluded - #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded -#endif -#ifndef PPI_CHG2_CH15_Included - #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included -#endif - -#ifndef PPI_CHG2_CH14_Pos - #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos -#endif -#ifndef PPI_CHG2_CH14_Msk - #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk -#endif -#ifndef PPI_CHG2_CH14_Excluded - #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded -#endif -#ifndef PPI_CHG2_CH14_Included - #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included -#endif - -#ifndef PPI_CHG2_CH13_Pos - #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos -#endif -#ifndef PPI_CHG2_CH13_Msk - #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk -#endif -#ifndef PPI_CHG2_CH13_Excluded - #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded -#endif -#ifndef PPI_CHG2_CH13_Included - #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included -#endif - -#ifndef PPI_CHG2_CH12_Pos - #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos -#endif -#ifndef PPI_CHG2_CH12_Msk - #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk -#endif -#ifndef PPI_CHG2_CH12_Excluded - #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded -#endif -#ifndef PPI_CHG2_CH12_Included - #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included -#endif - -#ifndef PPI_CHG2_CH11_Pos - #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos -#endif -#ifndef PPI_CHG2_CH11_Msk - #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk -#endif -#ifndef PPI_CHG2_CH11_Excluded - #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded -#endif -#ifndef PPI_CHG2_CH11_Included - #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included -#endif - -#ifndef PPI_CHG2_CH10_Pos - #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos -#endif -#ifndef PPI_CHG2_CH10_Msk - #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk -#endif -#ifndef PPI_CHG2_CH10_Excluded - #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded -#endif -#ifndef PPI_CHG2_CH10_Included - #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included -#endif - -#ifndef PPI_CHG2_CH9_Pos - #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos -#endif -#ifndef PPI_CHG2_CH9_Msk - #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk -#endif -#ifndef PPI_CHG2_CH9_Excluded - #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded -#endif -#ifndef PPI_CHG2_CH9_Included - #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included -#endif - -#ifndef PPI_CHG2_CH8_Pos - #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos -#endif -#ifndef PPI_CHG2_CH8_Msk - #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk -#endif -#ifndef PPI_CHG2_CH8_Excluded - #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded -#endif -#ifndef PPI_CHG2_CH8_Included - #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included -#endif - -#ifndef PPI_CHG2_CH7_Pos - #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos -#endif -#ifndef PPI_CHG2_CH7_Msk - #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk -#endif -#ifndef PPI_CHG2_CH7_Excluded - #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded -#endif -#ifndef PPI_CHG2_CH7_Included - #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included -#endif - -#ifndef PPI_CHG2_CH6_Pos - #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos -#endif -#ifndef PPI_CHG2_CH6_Msk - #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk -#endif -#ifndef PPI_CHG2_CH6_Excluded - #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded -#endif -#ifndef PPI_CHG2_CH6_Included - #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included -#endif - -#ifndef PPI_CHG2_CH5_Pos - #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos -#endif -#ifndef PPI_CHG2_CH5_Msk - #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk -#endif -#ifndef PPI_CHG2_CH5_Excluded - #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded -#endif -#ifndef PPI_CHG2_CH5_Included - #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included -#endif - -#ifndef PPI_CHG2_CH4_Pos - #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos -#endif -#ifndef PPI_CHG2_CH4_Msk - #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk -#endif -#ifndef PPI_CHG2_CH4_Excluded - #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded -#endif -#ifndef PPI_CHG2_CH4_Included - #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included -#endif - -#ifndef PPI_CHG2_CH3_Pos - #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos -#endif -#ifndef PPI_CHG2_CH3_Msk - #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk -#endif -#ifndef PPI_CHG2_CH3_Excluded - #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded -#endif -#ifndef PPI_CHG2_CH3_Included - #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included -#endif - -#ifndef PPI_CHG2_CH2_Pos - #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos -#endif -#ifndef PPI_CHG2_CH2_Msk - #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk -#endif -#ifndef PPI_CHG2_CH2_Excluded - #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded -#endif -#ifndef PPI_CHG2_CH2_Included - #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included -#endif - -#ifndef PPI_CHG2_CH1_Pos - #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos -#endif -#ifndef PPI_CHG2_CH1_Msk - #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk -#endif -#ifndef PPI_CHG2_CH1_Excluded - #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded -#endif -#ifndef PPI_CHG2_CH1_Included - #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included -#endif - -#ifndef PPI_CHG2_CH0_Pos - #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos -#endif -#ifndef PPI_CHG2_CH0_Msk - #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk -#endif -#ifndef PPI_CHG2_CH0_Excluded - #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded -#endif -#ifndef PPI_CHG2_CH0_Included - #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included -#endif - -#ifndef PPI_CHG3_CH15_Pos - #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos -#endif -#ifndef PPI_CHG3_CH15_Msk - #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk -#endif -#ifndef PPI_CHG3_CH15_Excluded - #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded -#endif -#ifndef PPI_CHG3_CH15_Included - #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included -#endif - -#ifndef PPI_CHG3_CH14_Pos - #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos -#endif -#ifndef PPI_CHG3_CH14_Msk - #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk -#endif -#ifndef PPI_CHG3_CH14_Excluded - #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded -#endif -#ifndef PPI_CHG3_CH14_Included - #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included -#endif - -#ifndef PPI_CHG3_CH13_Pos - #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos -#endif -#ifndef PPI_CHG3_CH13_Msk - #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk -#endif -#ifndef PPI_CHG3_CH13_Excluded - #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded -#endif -#ifndef PPI_CHG3_CH13_Included - #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included -#endif - -#ifndef PPI_CHG3_CH12_Pos - #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos -#endif -#ifndef PPI_CHG3_CH12_Msk - #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk -#endif -#ifndef PPI_CHG3_CH12_Excluded - #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded -#endif -#ifndef PPI_CHG3_CH12_Included - #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included -#endif - -#ifndef PPI_CHG3_CH11_Pos - #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos -#endif -#ifndef PPI_CHG3_CH11_Msk - #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk -#endif -#ifndef PPI_CHG3_CH11_Excluded - #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded -#endif -#ifndef PPI_CHG3_CH11_Included - #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included -#endif - -#ifndef PPI_CHG3_CH10_Pos - #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos -#endif -#ifndef PPI_CHG3_CH10_Msk - #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk -#endif -#ifndef PPI_CHG3_CH10_Excluded - #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded -#endif -#ifndef PPI_CHG3_CH10_Included - #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included -#endif - -#ifndef PPI_CHG3_CH9_Pos - #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos -#endif -#ifndef PPI_CHG3_CH9_Msk - #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk -#endif -#ifndef PPI_CHG3_CH9_Excluded - #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded -#endif -#ifndef PPI_CHG3_CH9_Included - #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included -#endif - -#ifndef PPI_CHG3_CH8_Pos - #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos -#endif -#ifndef PPI_CHG3_CH8_Msk - #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk -#endif -#ifndef PPI_CHG3_CH8_Excluded - #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded -#endif -#ifndef PPI_CHG3_CH8_Included - #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included -#endif - -#ifndef PPI_CHG3_CH7_Pos - #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos -#endif -#ifndef PPI_CHG3_CH7_Msk - #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk -#endif -#ifndef PPI_CHG3_CH7_Excluded - #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded -#endif -#ifndef PPI_CHG3_CH7_Included - #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included -#endif - -#ifndef PPI_CHG3_CH6_Pos - #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos -#endif -#ifndef PPI_CHG3_CH6_Msk - #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk -#endif -#ifndef PPI_CHG3_CH6_Excluded - #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded -#endif -#ifndef PPI_CHG3_CH6_Included - #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included -#endif - -#ifndef PPI_CHG3_CH5_Pos - #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos -#endif -#ifndef PPI_CHG3_CH5_Msk - #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk -#endif -#ifndef PPI_CHG3_CH5_Excluded - #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded -#endif -#ifndef PPI_CHG3_CH5_Included - #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included -#endif - -#ifndef PPI_CHG3_CH4_Pos - #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos -#endif -#ifndef PPI_CHG3_CH4_Msk - #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk -#endif -#ifndef PPI_CHG3_CH4_Excluded - #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded -#endif -#ifndef PPI_CHG3_CH4_Included - #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included -#endif - -#ifndef PPI_CHG3_CH3_Pos - #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos -#endif -#ifndef PPI_CHG3_CH3_Msk - #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk -#endif -#ifndef PPI_CHG3_CH3_Excluded - #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded -#endif -#ifndef PPI_CHG3_CH3_Included - #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included -#endif - -#ifndef PPI_CHG3_CH2_Pos - #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos -#endif -#ifndef PPI_CHG3_CH2_Msk - #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk -#endif -#ifndef PPI_CHG3_CH2_Excluded - #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded -#endif -#ifndef PPI_CHG3_CH2_Included - #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included -#endif - -#ifndef PPI_CHG3_CH1_Pos - #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos -#endif -#ifndef PPI_CHG3_CH1_Msk - #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk -#endif -#ifndef PPI_CHG3_CH1_Excluded - #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded -#endif -#ifndef PPI_CHG3_CH1_Included - #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included -#endif - -#ifndef PPI_CHG3_CH0_Pos - #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos -#endif -#ifndef PPI_CHG3_CH0_Msk - #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk -#endif -#ifndef PPI_CHG3_CH0_Excluded - #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#endif -#ifndef PPI_CHG3_CH0_Included - #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included -#endif +#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included + +#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos +#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk +#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded +#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included + +#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos +#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk +#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded +#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included + +#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos +#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk +#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded +#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included + +#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos +#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk +#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded +#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included + +#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos +#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk +#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded +#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included + +#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos +#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk +#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded +#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included + +#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos +#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk +#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded +#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included + +#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos +#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk +#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded +#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included + +#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos +#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk +#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded +#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included + +#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos +#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk +#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded +#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included + +#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos +#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk +#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded +#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included + +#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos +#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk +#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded +#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included + +#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos +#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk +#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded +#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included + +#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos +#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk +#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded +#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included + +#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos +#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk +#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded +#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included + +#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos +#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk +#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded +#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included + diff --git a/cores/nRF5/SDK/components/device/nrf52.h b/cores/nRF5/SDK/components/device/nrf52.h index 120e14c1..412ecef0 100755 --- a/cores/nRF5/SDK/components/device/nrf52.h +++ b/cores/nRF5/SDK/components/device/nrf52.h @@ -1,40 +1,46 @@ -/* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * + +/****************************************************************************************************//** * @file nrf52.h - * @brief CMSIS HeaderFile - * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:08 - * from File 'nrf52.svd', - * last modified on Wednesday, 04.11.2020 12:48:00 - */ + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * nrf52 from Nordic Semiconductor. + * + * @version V1 + * @date 23. February 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf52.svd' Version 1, + * + * @par Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ @@ -42,12 +48,10 @@ * @{ */ - /** @addtogroup nrf52 * @{ */ - #ifndef NRF52_H #define NRF52_H @@ -56,2388 +60,2066 @@ extern "C" { #endif -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ +/* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { -/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ -/* =========================================== nrf52 Specific Interrupt Numbers ============================================ */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ - NFCT_IRQn = 5, /*!< 5 NFCT */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - SAADC_IRQn = 7, /*!< 7 SAADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ - SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ - SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ - SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ - SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ - SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ - SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ - TIMER3_IRQn = 26, /*!< 26 TIMER3 */ - TIMER4_IRQn = 27, /*!< 27 TIMER4 */ - PWM0_IRQn = 28, /*!< 28 PWM0 */ - PDM_IRQn = 29, /*!< 29 PDM */ - MWU_IRQn = 32, /*!< 32 MWU */ - PWM1_IRQn = 33, /*!< 33 PWM1 */ - PWM2_IRQn = 34, /*!< 34 PWM2 */ - SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ - RTC2_IRQn = 36, /*!< 36 RTC2 */ - I2S_IRQn = 37, /*!< 37 I2S */ - FPU_IRQn = 38 /*!< 38 FPU */ +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38 /*!< 38 FPU */ } IRQn_Type; +/** @addtogroup Configuration_of_CMSIS + * @{ + */ -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ -#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ -#define __DSP_PRESENT 1 /*!< DSP present or not */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 1 /*!< MPU present */ -#define __FPU_PRESENT 1 /*!< FPU present */ +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ /** @} */ /* End of group Configuration_of_CMSIS */ -#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ -#include "system_nrf52.h" /*!< nrf52 System */ +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_nrf52.h" /*!< nrf52 System */ -#ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO -#endif +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ -/* ======================================== Start of section using anonymous unions ======================================== */ -#if defined (__CC_ARM) + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) #pragma push #pragma anon_unions -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) +#elif defined(__GNUC__) /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - - -/** - * @brief FICR_INFO [INFO] (Device info) - */ typedef struct { - __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ - __IM uint32_t VARIANT; /*!< (@ 0x00000004) Part Variant, Hardware version and Production - configuration */ - __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ - __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ - __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ - __IOM uint32_t UNUSED0[3]; /*!< (@ 0x00000014) Description collection[0]: Unspecified */ -} FICR_INFO_Type; /*!< Size = 32 (0x20) */ + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ +} FICR_INFO_Type; - -/** - * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) - */ typedef struct { - __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0. */ - __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1. */ - __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2. */ - __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3. */ - __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4. */ - __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5. */ - __IM uint32_t B0; /*!< (@ 0x00000018) y-intercept B0. */ - __IM uint32_t B1; /*!< (@ 0x0000001C) y-intercept B1. */ - __IM uint32_t B2; /*!< (@ 0x00000020) y-intercept B2. */ - __IM uint32_t B3; /*!< (@ 0x00000024) y-intercept B3. */ - __IM uint32_t B4; /*!< (@ 0x00000028) y-intercept B4. */ - __IM uint32_t B5; /*!< (@ 0x0000002C) y-intercept B5. */ - __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0. */ - __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1. */ - __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2. */ - __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3. */ - __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4. */ -} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ - + __I uint32_t A0; /*!< Slope definition A0. */ + __I uint32_t A1; /*!< Slope definition A1. */ + __I uint32_t A2; /*!< Slope definition A2. */ + __I uint32_t A3; /*!< Slope definition A3. */ + __I uint32_t A4; /*!< Slope definition A4. */ + __I uint32_t A5; /*!< Slope definition A5. */ + __I uint32_t B0; /*!< y-intercept B0. */ + __I uint32_t B1; /*!< y-intercept B1. */ + __I uint32_t B2; /*!< y-intercept B2. */ + __I uint32_t B3; /*!< y-intercept B3. */ + __I uint32_t B4; /*!< y-intercept B4. */ + __I uint32_t B5; /*!< y-intercept B5. */ + __I uint32_t T0; /*!< Segment end T0. */ + __I uint32_t T1; /*!< Segment end T1. */ + __I uint32_t T2; /*!< Segment end T2. */ + __I uint32_t T3; /*!< Segment end T3. */ + __I uint32_t T4; /*!< Segment end T4. */ +} FICR_TEMP_Type; -/** - * @brief FICR_NFC [NFC] (Unspecified) - */ typedef struct { - __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC Tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ - __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC Tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ - __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC Tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ - __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC Tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST and NFCID1_LAST. */ -} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; - -/** - * @brief POWER_RAM [RAM] (Unspecified) - */ typedef struct { - __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster[0]: RAM0 power control register */ - __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster[0]: RAM0 power control set - register */ - __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster[0]: RAM0 power control clear - register */ - __IM uint32_t RESERVED; -} POWER_RAM_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ + __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ + __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ + __I uint32_t RESERVED0; +} POWER_RAM_Type; -/** - * @brief UARTE_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ - __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ - __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ - __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ -} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t CPU0; /*!< AHB bus master priority register for CPU0 */ + __IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and + TWIS1 */ + __IO uint32_t RADIO; /*!< AHB bus master priority register for RADIO */ + __IO uint32_t ECB; /*!< AHB bus master priority register for ECB */ + __IO uint32_t CCM; /*!< AHB bus master priority register for CCM */ + __IO uint32_t AAR; /*!< AHB bus master priority register for AAR */ + __IO uint32_t SAADC; /*!< AHB bus master priority register for SAADC */ + __IO uint32_t UARTE; /*!< AHB bus master priority register for UARTE */ + __IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and + TWIS0 */ + __IO uint32_t SERIAL2; /*!< AHB bus master priority register for SPIM2 and SPIS2 */ + __IO uint32_t NFCT; /*!< AHB bus master priority register for NFCT */ + __IO uint32_t I2S; /*!< AHB bus master priority register for I2S */ + __IO uint32_t PDM; /*!< AHB bus master priority register for PDM */ + __IO uint32_t PWM; /*!< AHB bus master priority register for PWM0, PWM1 and PWM2 */ +} AMLI_RAMPRI_Type; - -/** - * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ -} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t RTS; /*!< Pin select for RTS signal */ + __IO uint32_t TXD; /*!< Pin select for TXD signal */ + __IO uint32_t CTS; /*!< Pin select for CTS signal */ + __IO uint32_t RXD; /*!< Pin select for RXD signal */ +} UARTE_PSEL_Type; -/** - * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ -} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; -/** - * @brief SPIM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ - __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ - __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ -} SPIM_PSEL_Type; /*!< Size = 12 (0xc) */ + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; - -/** - * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ +} SPIM_PSEL_Type; -/** - * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_RXD_Type; - -/** - * @brief SPIS_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ - __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ - __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ - __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ -} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_TXD_Type; -/** - * @brief SPIS_RXD [RXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ -} SPIS_RXD_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t CSN; /*!< Pin select for CSN signal */ +} SPIS_PSEL_Type; -/** - * @brief SPIS_TXD [TXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ -} SPIS_TXD_Type; /*!< Size = 12 (0xc) */ + __IO uint32_t PTR; /*!< RXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; - -/** - * @brief TWIM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ - __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ -} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t PTR; /*!< TXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; -/** - * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIM_PSEL_Type; - -/** - * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_RXD_Type; -/** - * @brief TWIS_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ - __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ -} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_TXD_Type; - -/** - * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ -} TWIS_RXD_Type; /*!< Size = 12 (0xc) */ + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIS_PSEL_Type; - -/** - * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ -} TWIS_TXD_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PTR; /*!< RXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; -/** - * @brief SPI_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ - __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI */ - __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO */ -} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + __IO uint32_t PTR; /*!< TXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; - -/** - * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) - */ typedef struct { - __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frames */ -} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ - + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI */ + __IO uint32_t MISO; /*!< Pin select for MISO */ +} SPI_PSEL_Type; -/** - * @brief NFCT_TXD [TXD] (Unspecified) - */ typedef struct { - __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ - __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ -} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t RX; /*!< Result of last incoming frames */ +} NFCT_FRAMESTATUS_Type; - -/** - * @brief NFCT_RXD [RXD] (Unspecified) - */ typedef struct { - __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ -} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ + __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ +} NFCT_TXD_Type; -/** - * @brief SAADC_EVENTS_CH [EVENTS_CH] (Unspecified) - */ typedef struct { - __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster[0]: Last results is equal - or above CH[0].LIMIT.HIGH */ - __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster[0]: Last results is equal - or below CH[0].LIMIT.LOW */ -} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ + __I uint32_t AMOUNT; /*!< Size of last incoming frame */ +} NFCT_RXD_Type; -/** - * @brief SAADC_CH [CH] (Unspecified) - */ typedef struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster[0]: Input positive pin selection - for CH[0] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster[0]: Input negative pin selection - for CH[0] */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster[0]: Input configuration for - CH[0] */ - __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster[0]: High/low limits for event - monitoring a channel */ -} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ + __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; - -/** - * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of buffer words to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of buffer words transferred since last - START */ -} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ + __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ + __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ + __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring + a channel */ +} SAADC_CH_Type; -/** - * @brief QDEC_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ - __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ - __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ -} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ + __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ +} SAADC_RESULT_Type; - -/** - * @brief PWM_SEQ [SEQ] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster[0]: Beginning address in - Data RAM of this sequence */ - __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster[0]: Amount of values (duty - cycles) in this sequence */ - __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster[0]: Amount of additional - PWM periods between samples loaded into - compare register */ - __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster[0]: Time added after the - sequence */ - __IM uint32_t RESERVED[4]; -} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ - + __IO uint32_t LED; /*!< Pin select for LED signal */ + __IO uint32_t A; /*!< Pin select for A signal */ + __IO uint32_t B; /*!< Pin select for B signal */ +} QDEC_PSEL_Type; -/** - * @brief PWM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection[0]: Output pin select - for PWM channel 0 */ -} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence + A */ + __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence + A */ + __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between + samples loaded to compare register (load every CNT+1 PWM periods) */ + __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ + __I uint32_t RESERVED1[4]; +} PWM_SEQ_Type; -/** - * @brief PDM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ - __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ -} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel + 0 */ +} PWM_PSEL_Type; - -/** - * @brief PDM_SAMPLE [SAMPLE] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with - EasyDMA */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA - mode */ -} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ + __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; -/** - * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) - */ typedef struct { - __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster[0]: Enable channel group - 0 */ - __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster[0]: Disable channel group - 0 */ -} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ + __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ +} PDM_SAMPLE_Type; - -/** - * @brief PPI_CH [CH] (PPI Channel) - */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster[0]: Channel 0 task end-point */ -} PPI_CH_Type; /*!< Size = 8 (0x8) */ - + __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ + __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ +} PPI_TASKS_CHG_Type; -/** - * @brief PPI_FORK [FORK] (Fork) - */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster[0]: Channel 0 task end-point */ -} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; - -/** - * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Unspecified) - */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to region - 0 detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to region - 0 detected */ -} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; - -/** - * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Unspecified) - */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster[0]: Write access to peripheral - region 0 detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster[0]: Read access to peripheral - region 0 detected */ -} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ +} MWU_EVENTS_REGION_Type; -/** - * @brief MWU_PERREGION [PERREGION] (Unspecified) - */ typedef struct { - __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster[0]: Source of event/interrupt - in region 0, write access detected while - corresponding subregion was enabled for - watching */ - __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster[0]: Source of event/interrupt - in region 0, read access detected while - corresponding subregion was enabled for - watching */ -} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 + detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ +} MWU_EVENTS_PREGION_Type; - -/** - * @brief MWU_REGION [REGION] (Unspecified) - */ typedef struct { - __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Start address for region - 0 */ - __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: End address of region - 0 */ - __IM uint32_t RESERVED[2]; -} MWU_REGION_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, write access detected while corresponding subregion was enabled + for watching */ + __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, read access detected while corresponding subregion was enabled + for watching */ +} MWU_PERREGION_Type; -/** - * @brief MWU_PREGION [PREGION] (Unspecified) - */ typedef struct { - __IM uint32_t START; /*!< (@ 0x00000000) Description cluster[0]: Reserved for future use */ - __IM uint32_t END; /*!< (@ 0x00000004) Description cluster[0]: Reserved for future use */ - __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster[0]: Subregions of region - 0 */ - __IM uint32_t RESERVED; -} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ + __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ + __I uint32_t RESERVED2[2]; +} MWU_REGION_Type; - -/** - * @brief I2S_CONFIG [CONFIG] (Unspecified) - */ typedef struct { - __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ - __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ - __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ - __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ - __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ - __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ - __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ - __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ - __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ - __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ -} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ - + __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ + __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ + __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ + __I uint32_t RESERVED3; +} MWU_PREGION_Type; -/** - * @brief I2S_RXD [RXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ -} I2S_RXD_Type; /*!< Size = 4 (0x4) */ - + __IO uint32_t MODE; /*!< I2S mode. */ + __IO uint32_t RXEN; /*!< Reception (RX) enable. */ + __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ + __IO uint32_t MCKEN; /*!< Master clock generator enable. */ + __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ + __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ + __IO uint32_t SWIDTH; /*!< Sample width. */ + __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ + __IO uint32_t FORMAT; /*!< Frame format. */ + __IO uint32_t CHANNELS; /*!< Enable channels. */ +} I2S_CONFIG_Type; -/** - * @brief I2S_TXD [TXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ -} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ +} I2S_RXD_Type; - -/** - * @brief I2S_RXTXD [RXTXD] (Unspecified) - */ typedef struct { - __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ -} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ - + __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ +} I2S_TXD_Type; -/** - * @brief I2S_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ - __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ - __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ - __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ - __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ -} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ - - -/** @} */ /* End of group Device_Peripheral_clusters */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ + __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; +typedef struct { + __IO uint32_t MCK; /*!< Pin select for MCK signal. */ + __IO uint32_t SCK; /*!< Pin select for SCK signal. */ + __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ + __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ + __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ +} I2S_PSEL_Type; -/* =========================================================================================================================== */ -/* ================ FICR ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ /** * @brief Factory Information Configuration Registers (FICR) */ -typedef struct { /*!< (@ 0x10000000) FICR Structure */ - __IM uint32_t RESERVED[4]; - __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ - __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ - __IM uint32_t RESERVED1[18]; - __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection[0]: Device identifier */ - __IM uint32_t RESERVED2[6]; - __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection[0]: Encryption Root, word - 0 */ - __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection[0]: Identity Root, word - 0 */ - __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ - __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection[0]: Device address 0 */ - __IM uint32_t RESERVED3[21]; - __IOM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ - __IM uint32_t RESERVED4[185]; - __IOM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization - coefficients */ - __IM uint32_t RESERVED5[2]; - __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ -} NRF_FICR_Type; /*!< Size = 1120 (0x460) */ - - - -/* =========================================================================================================================== */ -/* ================ UICR ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ + __I uint32_t CODESIZE; /*!< Code memory size */ + __I uint32_t RESERVED1[18]; + __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ + __I uint32_t RESERVED2[6]; + __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */ + __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ + __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ + __I uint32_t RESERVED3[21]; + FICR_INFO_Type INFO; /*!< Device info */ + __I uint32_t RESERVED4[185]; + FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ + __I uint32_t RESERVED5[2]; + FICR_NFC_Type NFC; /*!< Unspecified */ +} NRF_FICR_Type; + + +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ /** * @brief User Information Configuration Registers (UICR) */ -typedef struct { /*!< (@ 0x10001000) UICR Structure */ - __IOM uint32_t UNUSED0; /*!< (@ 0x00000000) Unspecified */ - __IOM uint32_t UNUSED1; /*!< (@ 0x00000004) Unspecified */ - __IOM uint32_t UNUSED2; /*!< (@ 0x00000008) Unspecified */ - __IM uint32_t RESERVED; - __IOM uint32_t UNUSED3; /*!< (@ 0x00000010) Unspecified */ - __IOM uint32_t NRFFW[15]; /*!< (@ 0x00000014) Description collection[0]: Reserved for Nordic - firmware design */ - __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection[0]: Reserved for Nordic - hardware design */ - __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection[0]: Reserved for customer */ - __IM uint32_t RESERVED1[64]; - __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection[0]: Mapping of the nRESET - function (see POWER chapter for details) */ - __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access Port protection */ - __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: - NFC antenna or GPIO */ -} NRF_UICR_Type; /*!< Size = 528 (0x210) */ +typedef struct { /*!< UICR Structure */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t UNUSED1; /*!< Unspecified */ + __IO uint32_t UNUSED2; /*!< Unspecified */ + __I uint32_t RESERVED0; + __IO uint32_t UNUSED3; /*!< Unspecified */ + __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ + __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ + __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ + __I uint32_t RESERVED1[64]; + __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see + POWER chapter for details) */ + __IO uint32_t APPROTECT; /*!< Access Port protection */ + __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna + or GPIO */ +} NRF_UICR_Type; - -/* =========================================================================================================================== */ -/* ================ BPROT ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ BPROT ================ */ +/* ================================================================================ */ /** * @brief Block Protect (BPROT) */ -typedef struct { /*!< (@ 0x40000000) BPROT Structure */ - __IM uint32_t RESERVED[384]; - __IOM uint32_t CONFIG0; /*!< (@ 0x00000600) Block protect configuration register 0 */ - __IOM uint32_t CONFIG1; /*!< (@ 0x00000604) Block protect configuration register 1 */ - __IOM uint32_t DISABLEINDEBUG; /*!< (@ 0x00000608) Disable protection mechanism in debug interface - mode */ - __IOM uint32_t UNUSED0; /*!< (@ 0x0000060C) Unspecified */ - __IOM uint32_t CONFIG2; /*!< (@ 0x00000610) Block protect configuration register 2 */ - __IOM uint32_t CONFIG3; /*!< (@ 0x00000614) Block protect configuration register 3 */ -} NRF_BPROT_Type; /*!< Size = 1560 (0x618) */ - +typedef struct { /*!< BPROT Structure */ + __I uint32_t RESERVED0[384]; + __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */ + __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */ + __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */ + __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */ +} NRF_BPROT_Type; -/* =========================================================================================================================== */ -/* ================ POWER ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ /** * @brief Power control (POWER) */ -typedef struct { /*!< (@ 0x40000000) POWER Structure */ - __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable constant latency mode */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable low power mode (variable latency) */ - __IM uint32_t RESERVED1[34]; - __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ - __IM uint32_t RESERVED2[2]; - __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ - __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ - __IM uint32_t RESERVED3[122]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[61]; - __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ - __IM uint32_t RESERVED5[9]; - __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ - __IM uint32_t RESERVED6[53]; - __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ - __IM uint32_t RESERVED7[3]; - __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power failure comparator configuration */ - __IM uint32_t RESERVED8[2]; - __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ - __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ - __IOM uint32_t RAMON; /*!< (@ 0x00000524) Deprecated register - RAM on/off register (this - register is retained) */ - __IM uint32_t RESERVED9[11]; - __IOM uint32_t RAMONB; /*!< (@ 0x00000554) Deprecated register - RAM on/off register (this - register is retained) */ - __IM uint32_t RESERVED10[8]; - __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) DC/DC enable register */ - __IM uint32_t RESERVED11[225]; - __IOM POWER_RAM_Type RAM[8]; /*!< (@ 0x00000900) Unspecified */ -} NRF_POWER_Type; /*!< Size = 2432 (0x980) */ - - - -/* =========================================================================================================================== */ -/* ================ CLOCK ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ + __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ + __I uint32_t RESERVED3[122]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t RESETREAS; /*!< Reset reason */ + __I uint32_t RESERVED5[9]; + __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ + __I uint32_t RESERVED6[53]; + __O uint32_t SYSTEMOFF; /*!< System OFF register */ + __I uint32_t RESERVED7[3]; + __IO uint32_t POFCON; /*!< Power failure comparator configuration */ + __I uint32_t RESERVED8[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register */ + __IO uint32_t GPREGRET2; /*!< General purpose retention register */ + __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is + retained) */ + __I uint32_t RESERVED9[11]; + __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is + retained) */ + __I uint32_t RESERVED10[8]; + __IO uint32_t DCDCEN; /*!< DC/DC enable register */ + __I uint32_t RESERVED11[225]; + POWER_RAM_Type RAM[8]; /*!< Unspecified */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ /** * @brief Clock control (CLOCK) */ -typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ - __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFCLK crystal oscillator */ - __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFCLK crystal oscillator */ - __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK source */ - __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK source */ - __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC oscillator */ - __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ - __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ - __IM uint32_t RESERVED[57]; - __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFCLK oscillator started */ - __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ - __IM uint32_t RESERVED1; - __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFCLK RC oscillator complete event */ - __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ - __IM uint32_t RESERVED2[124]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[63]; - __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been - triggered */ - __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ - __IM uint32_t RESERVED4; - __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been - triggered */ - __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ - __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART - task was triggered */ - __IM uint32_t RESERVED5[62]; - __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ - __IM uint32_t RESERVED6[7]; - __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ - __IM uint32_t RESERVED7[8]; - __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the Trace Port debug interface */ -} NRF_CLOCK_Type; /*!< Size = 1376 (0x560) */ - - - -/* =========================================================================================================================== */ -/* ================ RADIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief 2.4 GHz Radio (RADIO) - */ - -typedef struct { /*!< (@ 0x40001000) RADIO Structure */ - __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ - __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ - __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ - __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of - the receive signal strength. */ - __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ - __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ - __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ - __IM uint32_t RESERVED[55]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ - __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ - __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ - __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ - __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received - packet */ - __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last - received packet */ - __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete. */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value. */ - __IM uint32_t RESERVED2; - __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ - __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ - __IM uint32_t RESERVED3[50]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED4[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED5[61]; - __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ - __IM uint32_t RESERVED6; - __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ - __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ - __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ - __IM uint32_t RESERVED7[60]; - __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ - __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ - __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ - __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ - __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ - __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ - __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ - __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ - __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ - __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ - __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ - __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ - __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ - __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ - __IOM uint32_t UNUSED0; /*!< (@ 0x00000540) Unspecified */ - __IOM uint32_t TIFS; /*!< (@ 0x00000544) Inter Frame Spacing in us */ - __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ - __IM uint32_t RESERVED8; - __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ - __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ - __IM uint32_t RESERVED9[2]; - __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ - __IM uint32_t RESERVED10[39]; - __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection[0]: Device address base - segment 0 */ - __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection[0]: Device address prefix - 0 */ - __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ - __IM uint32_t RESERVED11[3]; - __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ - __IM uint32_t RESERVED12[618]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ -} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ UARTE0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief UART with EasyDMA (UARTE0) - */ - -typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ - __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ - __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ - __IM uint32_t RESERVED[7]; - __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ - __IM uint32_t RESERVED1[52]; - __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ - __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ - __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet - transferred to Data RAM) */ - __IM uint32_t RESERVED2; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ - __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ - __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ - __IM uint32_t RESERVED6; - __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ - __IM uint32_t RESERVED7[41]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED8[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ - __IM uint32_t RESERVED10[31]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ - __IM uint32_t RESERVED11; - __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[3]; - __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source - selected. */ - __IM uint32_t RESERVED13[3]; - __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IM uint32_t RESERVED14; - __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED15[7]; - __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ -} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Universal Asynchronous Receiver/Transmitter (UART0) - */ - -typedef struct { /*!< (@ 0x40002000) UART0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ - __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ - __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ - __IM uint32_t RESERVED[3]; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ - __IM uint32_t RESERVED1[56]; - __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ - __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ - __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ - __IM uint32_t RESERVED2[4]; - __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ - __IM uint32_t RESERVED3; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ - __IM uint32_t RESERVED5[46]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED6[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED7[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ - __IM uint32_t RESERVED8[31]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ - __IM uint32_t RESERVED9; - __IOM uint32_t PSELRTS; /*!< (@ 0x00000508) Pin select for RTS */ - __IOM uint32_t PSELTXD; /*!< (@ 0x0000050C) Pin select for TXD */ - __IOM uint32_t PSELCTS; /*!< (@ 0x00000510) Pin select for CTS */ - __IOM uint32_t PSELRXD; /*!< (@ 0x00000514) Pin select for RXD */ - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ - __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ - __IM uint32_t RESERVED10; - __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate */ - __IM uint32_t RESERVED11[17]; - __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ -} NRF_UART_Type; /*!< Size = 1392 (0x570) */ - - - -/* =========================================================================================================================== */ -/* ================ SPIM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) - */ - -typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ - __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ - __IM uint32_t RESERVED1; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ - __IM uint32_t RESERVED2[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ - __IM uint32_t RESERVED4; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ - __IM uint32_t RESERVED6[10]; - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ - __IM uint32_t RESERVED7[44]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED8[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ - __IM uint32_t RESERVED10; - __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED11[4]; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK - source selected. */ - __IM uint32_t RESERVED12[3]; - __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED13[26]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character clocked out in - case and over-read of the TXD buffer. */ -} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ - - - -/* =========================================================================================================================== */ -/* ================ SPIS0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI Slave 0 (SPIS0) - */ - -typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ - __IM uint32_t RESERVED[9]; - __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ - __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave - to acquire it */ - __IM uint32_t RESERVED1[54]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ - __IM uint32_t RESERVED2[2]; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ - __IM uint32_t RESERVED4[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED5[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED6[61]; - __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ - __IM uint32_t RESERVED7[15]; - __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ - __IM uint32_t RESERVED8[47]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ - __IM uint32_t RESERVED9; - __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED10[7]; - __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ - __IM uint32_t RESERVED11; - __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ - __IM uint32_t RESERVED12; - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED13; - __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case - of an ignored transaction. */ - __IM uint32_t RESERVED14[24]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ -} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ - - - -/* =========================================================================================================================== */ -/* ================ TWIM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) - */ +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ + __I uint32_t HFCLKSTAT; /*!< HFCLK status */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ + __I uint32_t LFCLKSTAT; /*!< LFCLK status */ + __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour + as RESETREAS) */ + __I uint32_t RESERVED7[8]; + __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; -typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ - __IM uint32_t RESERVED1[2]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the - TWI master is not suspended. */ - __IM uint32_t RESERVED2; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ - __IM uint32_t RESERVED3[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ - __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ - __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ - __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ - __IM uint32_t RESERVED6[2]; - __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ - __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last - byte */ - __IM uint32_t RESERVED7[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED8[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[110]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ - __IM uint32_t RESERVED10[14]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ - __IM uint32_t RESERVED11; - __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[5]; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ - __IM uint32_t RESERVED13[3]; - __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED14[13]; - __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ -} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ - - - -/* =========================================================================================================================== */ -/* ================ TWIS0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) - */ -typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ - __IM uint32_t RESERVED[5]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ - __IM uint32_t RESERVED1; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ - __IM uint32_t RESERVED2[3]; - __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ - __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ - __IM uint32_t RESERVED3[51]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ - __IM uint32_t RESERVED5[9]; - __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ - __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ - __IM uint32_t RESERVED6[4]; - __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ - __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ - __IM uint32_t RESERVED7[37]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED8[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[113]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ - __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had - a match */ - __IM uint32_t RESERVED10[10]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ - __IM uint32_t RESERVED11; - __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[9]; - __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IM uint32_t RESERVED13; - __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED14[14]; - __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection[0]: TWI slave address - 0 */ - __IM uint32_t RESERVED15; - __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match - mechanism */ - __IM uint32_t RESERVED16[10]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case - of an over-read of the transmit buffer. */ -} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI0 ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ AMLI ================ */ +/* ================================================================================ */ /** - * @brief Serial Peripheral Interface 0 (SPI0) + * @brief AHB Multi-Layer Interface (AMLI) */ -typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ - __IM uint32_t RESERVED[66]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ - __IM uint32_t RESERVED1[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ - __IM uint32_t RESERVED3; - __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED4; - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ - __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ - __IM uint32_t RESERVED5; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency */ - __IM uint32_t RESERVED6[11]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ -} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ +typedef struct { /*!< AMLI Structure */ + __I uint32_t RESERVED0[896]; + AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure */ +} NRF_AMLI_Type; - -/* =========================================================================================================================== */ -/* ================ TWI0 ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ /** - * @brief I2C compatible Two-Wire Interface 0 (TWI0) + * @brief 2.4 GHz Radio (RADIO) */ -typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ - __IM uint32_t RESERVED1[2]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ - __IM uint32_t RESERVED2; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ - __IM uint32_t RESERVED3[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ - __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ - __IM uint32_t RESERVED4[4]; - __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ - __IM uint32_t RESERVED6[4]; - __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte - that is sent or received */ - __IM uint32_t RESERVED7[3]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ - __IM uint32_t RESERVED8[45]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED9[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED10[110]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ - __IM uint32_t RESERVED11[14]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ - __IM uint32_t RESERVED12; - __IOM uint32_t PSELSCL; /*!< (@ 0x00000508) Pin select for SCL */ - __IOM uint32_t PSELSDA; /*!< (@ 0x0000050C) Pin select for SDA */ - __IM uint32_t RESERVED13[2]; - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ - __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ - __IM uint32_t RESERVED14; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency */ - __IM uint32_t RESERVED15[24]; - __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ -} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ - - - -/* =========================================================================================================================== */ -/* ================ NFCT ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ + __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ + __O uint32_t TASKS_START; /*!< Start RADIO */ + __O uint32_t TASKS_STOP; /*!< Stop RADIO */ + __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal + strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ + __I uint32_t RESERVED0[55]; + __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ + __IO uint32_t EVENTS_END; /*!< Packet sent or received */ + __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ + __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ + __I uint32_t RESERVED3[50]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED4[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[61]; + __I uint32_t CRCSTATUS; /*!< CRC status */ + __I uint32_t RESERVED6; + __I uint32_t RXMATCH; /*!< Received address */ + __I uint32_t RXCRC; /*!< CRC field of previously received packet */ + __I uint32_t DAI; /*!< Device address match index */ + __I uint32_t RESERVED7[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer */ + __IO uint32_t FREQUENCY; /*!< Frequency */ + __IO uint32_t TXPOWER; /*!< Output power */ + __IO uint32_t MODE; /*!< Data rate and modulation */ + __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ + __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ + __IO uint32_t BASE0; /*!< Base address 0 */ + __IO uint32_t BASE1; /*!< Base address 1 */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ + __IO uint32_t TXADDRESS; /*!< Transmit address select */ + __IO uint32_t RXADDRESSES; /*!< Receive address select */ + __IO uint32_t CRCCNF; /*!< CRC configuration */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial */ + __IO uint32_t CRCINIT; /*!< CRC initial value */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample */ + __I uint32_t RESERVED8; + __I uint32_t STATE; /*!< Current radio state */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ + __I uint32_t RESERVED9[2]; + __IO uint32_t BCC; /*!< Bit counter compare */ + __I uint32_t RESERVED10[39]; + __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ + __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ + __IO uint32_t DACNF; /*!< Device address match configuration */ + __I uint32_t RESERVED11[3]; + __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ + __I uint32_t RESERVED12[618]; + __IO uint32_t POWER; /*!< Peripheral power control */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UARTE ================ */ +/* ================================================================================ */ + + +/** + * @brief UART with EasyDMA (UARTE) + */ + +typedef struct { /*!< UARTE Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[7]; + __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ + __I uint32_t RESERVED1[52]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ + __I uint32_t RESERVED3[3]; + __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ + __I uint32_t RESERVED6; + __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ + __I uint32_t RESERVED7[41]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED11; + UARTE_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t BAUDRATE; /*!< Baud rate */ + __I uint32_t RESERVED13[3]; + UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED14; + UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED15[7]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED9; + __IO uint32_t PSELRTS; /*!< Pin select for RTS */ + __IO uint32_t PSELTXD; /*!< Pin select for TXD */ + __IO uint32_t PSELCTS; /*!< Pin select for CTS */ + __IO uint32_t PSELRXD; /*!< Pin select for RXD */ + __I uint32_t RXD; /*!< RXD register */ + __O uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< Baud rate */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[125]; + __IO uint32_t ENABLE; /*!< Enable SPIM */ + __I uint32_t RESERVED10; + SPIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED11[4]; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED12[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13[26]; + __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read + of the TXD buffer. */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI Slave 0 (SPIS) + */ + +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status register */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPI slave */ + __I uint32_t RESERVED9; + SPIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED10[7]; + SPIS_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED11; + SPIS_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored + transaction. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ TWIM ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) + */ + +typedef struct { /*!< TWIM Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is + not suspended. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[8]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been + issued, TWI traffic is now suspended. */ + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[2]; + __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ + __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ + __I uint32_t RESERVED7[39]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[14]; + __IO uint32_t ENABLE; /*!< Enable TWIM */ + __I uint32_t RESERVED11; + TWIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[5]; + __IO uint32_t FREQUENCY; /*!< TWI frequency */ + __I uint32_t RESERVED13[3]; + TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[13]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWIM_Type; + + +/* ================================================================================ */ +/* ================ TWIS ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) + */ + +typedef struct { /*!< TWIS Structure */ + __I uint32_t RESERVED0[5]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED2[3]; + __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ + __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ + __I uint32_t RESERVED3[51]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[9]; + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_WRITE; /*!< Write command received */ + __IO uint32_t EVENTS_READ; /*!< Read command received */ + __I uint32_t RESERVED7[37]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[113]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t MATCH; /*!< Status register indicating which address had a match */ + __I uint32_t RESERVED10[10]; + __IO uint32_t ENABLE; /*!< Enable TWIS */ + __I uint32_t RESERVED11; + TWIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[9]; + TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED13; + TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[14]; + __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ + __I uint32_t RESERVED16[10]; + __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read + of the transmit buffer. */ +} NRF_TWIS_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI */ + __I uint32_t RESERVED3; + SPI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or + received */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable TWI */ + __I uint32_t RESERVED12; + __IO uint32_t PSELSCL; /*!< Pin select for SCL */ + __IO uint32_t PSELSDA; /*!< Pin select for SDA */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< TWI frequency */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ NFCT ================ */ +/* ================================================================================ */ /** * @brief NFC-A compatible radio (NFCT) */ -typedef struct { /*!< (@ 0x40005000) NFCT Structure */ - __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFC peripheral for incoming and outgoing - frames, change state to activated */ - __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFC peripheral */ - __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to - sense mode */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of a outgoing frame, change - state to transmit */ - __IM uint32_t RESERVED[3]; - __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ - __IM uint32_t RESERVED1; - __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ - __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ - __IM uint32_t RESERVED2[53]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFC peripheral is ready to receive and send - frames */ - __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ - __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ - __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted - frame */ - __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air - symbol of a frame */ - __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received - frame */ - __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data have been checked (CRC, parity) - and transferred to RAM, and EasyDMA has - ended accessing the RX buffer */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register - contains details on the source of the error. */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX - register contains details on the source - of the error. */ - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) - in Data RAM full. */ - __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA - has ended accessing the TX buffer */ - __IM uint32_t RESERVED4; - __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ - __IM uint32_t RESERVED5[3]; - __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC Auto collision resolution error reported. */ - __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC Auto collision resolution successfully completed */ - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ - __IM uint32_t RESERVED6[43]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED7[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED8[62]; - __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ - __IM uint32_t RESERVED9; - __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ - __IM uint32_t RESERVED10[8]; - __IM uint32_t CURRENTLOADCTRL; /*!< (@ 0x00000430) Current value driven to the NFC Load Control */ - __IM uint32_t RESERVED11[2]; - __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ - __IM uint32_t RESERVED12[49]; - __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ - __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ - __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ - __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in - Data RAM */ - __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of allocated for TXD and RXD data storage - buffer in Data RAM */ - __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ - __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ - __IM uint32_t RESERVED13[26]; - __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ - __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ - __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ - __IM uint32_t RESERVED14; - __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ - __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ -} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ - - - -/* =========================================================================================================================== */ -/* ================ GPIOTE ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< NFCT Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change + state to activated */ + __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */ + __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ + __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ + __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ + __I uint32_t RESERVED2[53]; + __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */ + __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ + __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ + __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ + __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ + __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ + __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred + to RAM, and EasyDMA has ended accessing the RX buffer */ + __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details + on the source of the error. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains + details on the source of the error. */ + __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended + accessing the TX buffer */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ + __I uint32_t RESERVED5[3]; + __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */ + __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */ + __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ + __I uint32_t RESERVED6[43]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED7[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED8[62]; + __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ + __I uint32_t RESERVED9; + NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ + __I uint32_t RESERVED10[8]; + __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */ + __I uint32_t RESERVED11[2]; + __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ + __I uint32_t RESERVED12[49]; + __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ + __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ + __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ + __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ + __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data + RAM */ + NFCT_TXD_Type TXD; /*!< Unspecified */ + NFCT_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED13[26]; + __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ + __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ + __I uint32_t RESERVED14; + __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ + __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ /** * @brief GPIO Tasks and Events (GPIOTE) */ -typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ - __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection[0]: Task for writing to - pin specified in CONFIG[0].PSEL. Action - on pin is configured in CONFIG[0].POLARITY. */ - __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection[0]: Task for writing to - pin specified in CONFIG[0].PSEL. Action - on pin is to set it high. */ - __IM uint32_t RESERVED1[4]; - __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection[0]: Task for writing to - pin specified in CONFIG[0].PSEL. Action - on pin is to set it low. */ - __IM uint32_t RESERVED2[32]; - __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection[0]: Event generated from - pin specified in CONFIG[0].PSEL */ - __IM uint32_t RESERVED3[23]; - __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins - with SENSE mechanism enabled */ - __IM uint32_t RESERVED4[97]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED5[129]; - __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection[0]: Configuration for - OUT[n], SET[n] and CLR[n] tasks and IN[n] - event */ -} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ - - - -/* =========================================================================================================================== */ -/* ================ SAADC ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it high. */ + __I uint32_t RESERVED1[4]; + __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it low. */ + __I uint32_t RESERVED2[32]; + __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified + in CONFIG[0].PSEL */ + __I uint32_t RESERVED3[23]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism + enabled */ + __I uint32_t RESERVED4[97]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[129]; + __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] + and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; + + +/* ================================================================================ */ +/* ================ SAADC ================ */ +/* ================================================================================ */ /** * @brief Analog to Digital Converter (SAADC) */ -typedef struct { /*!< (@ 0x40007000) SAADC Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the ADC and prepare the result buffer in - RAM */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Take one ADC sample, if scan is enabled all channels - are sampled */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop the ADC and terminate any on-going conversion */ - __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The ADC has started */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The ADC has filled up the Result buffer */ - __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending - on the mode, multiple conversions might - be needed for a result to be transferred - to RAM. */ - __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) A result is ready to get transferred to RAM. */ - __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The ADC has stopped */ - __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Unspecified */ - __IM uint32_t RESERVED1[106]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[61]; - __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable ADC */ - __IM uint32_t RESERVED4[3]; - __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ - __IM uint32_t RESERVED5[24]; - __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ - __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. OVERSAMPLE should - not be combined with SCAN. The RESOLUTION - is applied before averaging, thus for high - OVERSAMPLE a higher RESOLUTION should be - used. */ - __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ - __IM uint32_t RESERVED6[12]; - __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ -} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ - - - -/* =========================================================================================================================== */ -/* ================ TIMER0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Timer/Counter 0 (TIMER0) - */ - -typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ - __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ - __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ - __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ - __IM uint32_t RESERVED[11]; - __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection[0]: Capture Timer value - to CC[0] register */ - __IM uint32_t RESERVED1[58]; - __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] - match */ - __IM uint32_t RESERVED2[42]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED3[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[126]; - __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ - __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ - __IM uint32_t RESERVED5; - __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ - __IM uint32_t RESERVED6[11]; - __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection[0]: Capture/Compare register - 0 */ -} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ - - - -/* =========================================================================================================================== */ -/* ================ RTC0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Real time counter 0 (RTC0) - */ - -typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ - __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ - __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ - __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ - __IM uint32_t RESERVED1[14]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection[0]: Compare event on CC[0] - match */ - __IM uint32_t RESERVED2[109]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[13]; - __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ - __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ - __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ - __IM uint32_t RESERVED4[110]; - __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu - t be written when RTC is stopped */ - __IM uint32_t RESERVED5[13]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection[0]: Compare register 0 */ -} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ - - - -/* =========================================================================================================================== */ -/* ================ TEMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< SAADC Structure */ + __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ + __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ + __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ + __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ + __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ + __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, + multiple conversions might be needed for a result to be transferred + to RAM. */ + __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ + __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ + __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ + SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED1[106]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t STATUS; /*!< Status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< Enable or disable ADC */ + __I uint32_t RESERVED4[3]; + SAADC_CH_Type CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED5[24]; + __IO uint32_t RESOLUTION; /*!< Resolution configuration */ + __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined + with SCAN. The RESOLUTION is applied before averaging, thus + for high OVERSAMPLE a higher RESOLUTION should be used. */ + __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ + __I uint32_t RESERVED6[12]; + SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ +} NRF_SAADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ + + +/** + * @brief Timer/Counter 0 (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer */ + __O uint32_t TASKS_STOP; /*!< Stop Timer */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ + __O uint32_t TASKS_CLEAR; /*!< Clear time */ + __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ + __I uint32_t RESERVED1[58]; + __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[42]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[126]; + __IO uint32_t MODE; /*!< Timer mode selection */ + __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ + __I uint32_t RESERVED5; + __IO uint32_t PRESCALER; /*!< Timer prescaler register */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real time counter 0 (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ + __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Enable or disable event routing */ + __IO uint32_t EVTENSET; /*!< Enable event routing */ + __IO uint32_t EVTENCLR; /*!< Disable event routing */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value */ + __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must + be written when RTC is stopped */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ /** * @brief Temperature Sensor (TEMP) */ -typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[127]; - __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ - __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ - __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ -} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ - - - -/* =========================================================================================================================== */ -/* ================ RNG ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ + __I uint32_t RESERVED3[5]; + __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ + __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ + __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ + __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ + __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ + __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ + __I uint32_t RESERVED4[2]; + __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ + __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ + __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ + __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ + __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ + __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ + __I uint32_t RESERVED5[2]; + __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ + __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ + __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ + __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ + __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ +} NRF_TEMP_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ /** * @brief Random Number Generator (RNG) */ -typedef struct { /*!< (@ 0x4000D000) RNG Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number - written to the VALUE register */ - __IM uint32_t RESERVED1[63]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[126]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ - __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ -} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ - +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Task starting the random number generator */ + __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to + the VALUE register */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t VALUE; /*!< Output random number */ +} NRF_RNG_Type; -/* =========================================================================================================================== */ -/* ================ ECB ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ /** * @brief AES ECB Mode Encryption (ECB) */ -typedef struct { /*!< (@ 0x4000E000) ECB Structure */ - __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ - __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ - __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB - task or due to an error */ - __IM uint32_t RESERVED1[127]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ -} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ + __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to + an error */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ +} NRF_ECB_Type; - -/* =========================================================================================================================== */ -/* ================ CCM ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ /** * @brief AES CCM Mode Encryption (CCM) */ -typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation - will stop by itself when completed. */ - __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will - stop by itself when completed. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ - __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) CCM error event */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ - __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and - NONCE vector */ - __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ - __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ - __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ -} NRF_CCM_Type; /*!< Size = 1304 (0x518) */ - - - -/* =========================================================================================================================== */ -/* ================ AAR ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself + when completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ + __IO uint32_t EVENTS_ERROR; /*!< CCM error event */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< MIC check result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable */ + __IO uint32_t MODE; /*!< Operation mode */ + __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ + __IO uint32_t INPTR; /*!< Input pointer */ + __IO uint32_t OUTPTR; /*!< Output pointer */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ /** * @brief Accelerated Address Resolver (AAR) */ -typedef struct { /*!< (@ 0x4000F000) AAR Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified - in the IRK data structure */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ - __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ - __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ - __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ - __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ - __IM uint32_t RESERVED5; - __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ - __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ -} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ - - - -/* =========================================================================================================================== */ -/* ================ WDT ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR */ + __IO uint32_t NIRK; /*!< Number of IRKs */ + __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ /** * @brief Watchdog Timer (WDT) */ -typedef struct { /*!< (@ 0x40010000) WDT Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ - __IM uint32_t RESERVED[63]; - __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[61]; - __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ - __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ - __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ - __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ - __IM uint32_t RESERVED4[60]; - __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection[0]: Reload request 0 */ -} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ - +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Run status */ + __I uint32_t REQSTATUS; /*!< Request status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value */ + __IO uint32_t RREN; /*!< Enable register for reload request registers */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; -/* =========================================================================================================================== */ -/* ================ QDEC ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ /** * @brief Quadrature Decoder (QDEC) */ -typedef struct { /*!< (@ 0x40012000) QDEC Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ - __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ - __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ - __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ - __IM uint32_t RESERVED[59]; - __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value - written to the SAMPLE register */ - __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ - __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ - __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ - __IM uint32_t RESERVED1[59]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ - __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ - __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ - __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ - __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY - and DBLRDY events can be generated */ - __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ - __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the - READCLRACC or RDCLRACC task */ - __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ - __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ - __IM uint32_t RESERVED4[5]; - __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ - __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected - double transitions */ - __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC - or RDCLRDBL task */ -} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ - - - -/* =========================================================================================================================== */ -/* ================ COMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ + __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ + __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ + __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ + __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ + __I uint32_t RESERVED0[59]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to + the SAMPLE register */ + __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ + __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ + __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ + __I uint32_t RESERVED1[59]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity */ + __IO uint32_t SAMPLEPER; /*!< Sample period */ + __I int32_t SAMPLE; /*!< Motion sample value */ + __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events + can be generated */ + __I int32_t ACC; /*!< Register accumulating the valid transitions */ + __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC + task */ + QDEC_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t DBFEN; /*!< Enable input debounce filters */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ + __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL + task */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ /** * @brief Comparator (COMP) */ -typedef struct { /*!< (@ 0x40013000) COMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ - __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ - __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ - __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED2[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ - __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ - __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ - __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ - __IM uint32_t RESERVED5[8]; - __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ - __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ - __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ - __IOM uint32_t ISOURCE; /*!< (@ 0x0000053C) Current source select on analog input */ -} NRF_COMP_Type; /*!< Size = 1344 (0x540) */ - - - -/* =========================================================================================================================== */ -/* ================ LPCOMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< COMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< COMP enable */ + __IO uint32_t PSEL; /*!< Pin select */ + __IO uint32_t REFSEL; /*!< Reference source select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[8]; + __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ + __IO uint32_t MODE; /*!< Mode configuration */ + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ + __IO uint32_t ISOURCE; /*!< Current source select on analog input */ +} NRF_COMP_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ /** * @brief Low Power Comparator (LPCOMP) */ -typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ - __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ - __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ - __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ - __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ - __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ - __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ - __IM uint32_t RESERVED5[4]; - __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ - __IM uint32_t RESERVED6[5]; - __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ -} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ - - - -/* =========================================================================================================================== */ -/* ================ SWI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Software interrupt 0 (SWI0) - */ - -typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ - __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ -} NRF_SWI_Type; /*!< Size = 4 (0x4) */ - - - -/* =========================================================================================================================== */ -/* ================ EGU0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Event Generator Unit 0 (EGU0) - */ - -typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ - __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection[0]: Trigger 0 for triggering - the corresponding TRIGGERED[0] event */ - __IM uint32_t RESERVED[48]; - __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection[0]: Event number 0 generated - by triggering the corresponding TRIGGER[0] - task */ - __IM uint32_t RESERVED1[112]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ -} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ - - +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable LPCOMP */ + __IO uint32_t PSEL; /*!< Input pin select */ + __IO uint32_t REFSEL; /*!< Reference select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration */ + __I uint32_t RESERVED6[5]; + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ + + +/** + * @brief Software interrupt 0 (SWI) + */ + +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; + + +/* ================================================================================ */ +/* ================ EGU ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Generator Unit 0 (EGU) + */ + +typedef struct { /*!< EGU Structure */ + __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding + TRIGGERED[0] event */ + __I uint32_t RESERVED0[48]; + __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering + the corresponding TRIGGER[0] task */ + __I uint32_t RESERVED1[112]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ +} NRF_EGU_Type; + + +/* ================================================================================ */ +/* ================ PWM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current + PWM period, and stops sequence playback */ + __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all + enabled channels from sequence 0, and starts playing that sequence + at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes + PWM generation to start it was not running. */ + __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels + if DECODER.MODE=NextStep. Does not cause PWM generation to start + it was not running. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer + generated */ + __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence + 0 */ + __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence + 0, when last value from RAM has been applied to wave counter */ + __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ + __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times + defined in LOOP.CNT */ + __I uint32_t RESERVED2[56]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[125]; + __IO uint32_t ENABLE; /*!< PWM module enable register */ + __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ + __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ + __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ + __IO uint32_t DECODER; /*!< Configuration of the decoder */ + __IO uint32_t LOOP; /*!< Amount of playback of a loop */ + __I uint32_t RESERVED5[2]; + PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ + PWM_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_PWM_Type; + -/* =========================================================================================================================== */ -/* ================ PWM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Pulse Width Modulation Unit 0 (PWM0) - */ - -typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at - the end of current PWM period, and stops - sequence playback */ - __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection[0]: Loads the first PWM - value on all enabled channels from sequence - 0, and starts playing that sequence at the - rate defined in SEQ[0]REFRESH and/or DECODER.MODE. - Causes PWM generation to start it was not - running. */ - __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on - all enabled channels if DECODER.MODE=NextStep. - Does not cause PWM generation to start it - was not running. */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses - are no longer generated */ - __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection[0]: First PWM period started - on sequence 0 */ - __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection[0]: Emitted at end of - every sequence 0, when last value from RAM - has been applied to wave counter */ - __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ - __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount - of times defined in LOOP.CNT */ - __IM uint32_t RESERVED2[56]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcut register */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ - __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ - __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter - counts */ - __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ - __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ - __IOM uint32_t LOOP; /*!< (@ 0x00000514) Amount of playback of a loop */ - __IM uint32_t RESERVED5[2]; - __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ - __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ -} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ - - - -/* =========================================================================================================================== */ -/* ================ PDM ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ PDM ================ */ +/* ================================================================================ */ /** * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) */ -typedef struct { /*!< (@ 0x4001D000) PDM Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified - by SAMPLE.MAXCNT (or the last sample after - a STOP task has been received) to Data RAM */ - __IM uint32_t RESERVED1[125]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ - __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ - __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' - signals */ - __IM uint32_t RESERVED3[3]; - __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ - __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ - __IM uint32_t RESERVED4[8]; - __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ - __IM uint32_t RESERVED5[6]; - __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ -} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ - - - -/* =========================================================================================================================== */ -/* ================ NVMC ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< PDM Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ + __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ + __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ + __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT + (or the last sample after a STOP task has been received) to + Data RAM */ + __I uint32_t RESERVED1[125]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< PDM module enable register */ + __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ + __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ + __I uint32_t RESERVED3[3]; + __IO uint32_t GAINL; /*!< Left output gain adjustment */ + __IO uint32_t GAINR; /*!< Right output gain adjustment */ + __I uint32_t RESERVED4[8]; + PDM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED5[6]; + PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ +} NRF_PDM_Type; + + +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ /** * @brief Non Volatile Memory Controller (NVMC) */ -typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ - __IM uint32_t RESERVED[256]; - __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ - __IM uint32_t RESERVED1[64]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register */ union { - __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in Code area */ - __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a - page in Code area. Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ }; - __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ - __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a - page in Code area. Equivalent to ERASEPAGE. */ - __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing User Information Configuration - Registers */ - __IM uint32_t RESERVED2[10]; - __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-Code cache configuration register. */ - __IM uint32_t RESERVED3; - __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-Code cache hit counter. */ - __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-Code cache miss counter. */ -} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ - + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ + __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ + __I uint32_t RESERVED2[10]; + __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ + __I uint32_t RESERVED3; + __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ + __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ +} NRF_NVMC_Type; -/* =========================================================================================================================== */ -/* ================ PPI ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ /** * @brief Programmable Peripheral Interconnect (PPI) */ -typedef struct { /*!< (@ 0x4001F000) PPI Structure */ - __IOM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ - __IM uint32_t RESERVED[308]; - __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ - __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ - __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ - __IM uint32_t RESERVED1; - __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ - __IM uint32_t RESERVED2[148]; - __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection[0]: Channel group 0 */ - __IM uint32_t RESERVED3[62]; - __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ -} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ + __I uint32_t RESERVED0[308]; + __IO uint32_t CHEN; /*!< Channel enable register */ + __IO uint32_t CHENSET; /*!< Channel enable set register */ + __IO uint32_t CHENCLR; /*!< Channel enable clear register */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[20]; /*!< PPI Channel */ + __I uint32_t RESERVED2[148]; + __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ + __I uint32_t RESERVED3[62]; + PPI_FORK_Type FORK[32]; /*!< Fork */ +} NRF_PPI_Type; - -/* =========================================================================================================================== */ -/* ================ MWU ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ MWU ================ */ +/* ================================================================================ */ /** * @brief Memory Watch Unit (MWU) */ -typedef struct { /*!< (@ 0x40020000) MWU Structure */ - __IM uint32_t RESERVED[64]; - __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Unspecified */ - __IM uint32_t RESERVED1[16]; - __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Unspecified */ - __IM uint32_t RESERVED2[100]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable non-maskable interrupt */ - __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable non-maskable interrupt */ - __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable non-maskable interrupt */ - __IM uint32_t RESERVED4[53]; - __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ - __IM uint32_t RESERVED5[64]; - __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ - __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ - __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ - __IM uint32_t RESERVED6[57]; - __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ - __IM uint32_t RESERVED7[32]; - __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ -} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ - - - -/* =========================================================================================================================== */ -/* ================ I2S ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< MWU Structure */ + __I uint32_t RESERVED0[64]; + MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED1[16]; + MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED2[100]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[5]; + __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ + __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ + __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ + __I uint32_t RESERVED4[53]; + MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED5[64]; + __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ + __IO uint32_t REGIONENSET; /*!< Enable regions watch */ + __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ + __I uint32_t RESERVED6[57]; + MWU_REGION_Type REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED7[32]; + MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ +} NRF_MWU_Type; + + +/* ================================================================================ */ +/* ================ I2S ================ */ +/* ================================================================================ */ /** * @brief Inter-IC Sound (I2S) */ -typedef struct { /*!< (@ 0x40025000) I2S Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK - generator when this is enabled. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. - Triggering this task will cause the {event:STOPPED} - event to be generated. */ - __IM uint32_t RESERVED[63]; - __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal - double-buffers. When the I2S module is started - and RX is enabled, this event will be generated - for every RXTXD.MAXCNT words that are received - on the SDIN pin. */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal - double-buffers. When the I2S module is started - and TX is enabled, this event will be generated - for every RXTXD.MAXCNT words that are sent - on the SDOUT pin. */ - __IM uint32_t RESERVED2[122]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ - __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ - __IM uint32_t RESERVED4[3]; - __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ - __IM uint32_t RESERVED5; - __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ - __IM uint32_t RESERVED6[3]; - __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ - __IM uint32_t RESERVED7[3]; - __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ -} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ - - - -/* =========================================================================================================================== */ -/* ================ FPU ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< I2S Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when + this is enabled. */ + __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this + task will cause the {event:STOPPED} event to be generated. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __I uint32_t RESERVED2[122]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable I2S module. */ + I2S_CONFIG_Type CONFIG; /*!< Unspecified */ + __I uint32_t RESERVED4[3]; + I2S_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED5; + I2S_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED6[3]; + I2S_RXTXD_Type RXTXD; /*!< Unspecified */ + __I uint32_t RESERVED7[3]; + I2S_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_I2S_Type; + + +/* ================================================================================ */ +/* ================ FPU ================ */ +/* ================================================================================ */ /** * @brief FPU (FPU) */ -typedef struct { /*!< (@ 0x40026000) FPU Structure */ - __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ -} NRF_FPU_Type; /*!< Size = 4 (0x4) */ - +typedef struct { /*!< FPU Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_FPU_Type; -/* =========================================================================================================================== */ -/* ================ P0 ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ /** - * @brief GPIO Port 1 (P0) + * @brief GPIO Port 1 (GPIO) */ -typedef struct { /*!< (@ 0x50000000) P0 Structure */ - __IM uint32_t RESERVED[321]; - __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ - __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ - __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ - __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ - __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ - __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ - __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ - __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that - have met the criteria set in the PIN_CNF[n].SENSE - registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour - and LDETECT mode */ - __IM uint32_t RESERVED1[118]; - __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection[0]: Configuration of GPIO - pins */ -} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ + __I uint32_t IN; /*!< Read GPIO port */ + __IO uint32_t DIR; /*!< Direction of GPIO pins */ + __IO uint32_t DIRSET; /*!< DIR set register */ + __IO uint32_t DIRCLR; /*!< DIR clear register */ + __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria + set in the PIN_CNF[n].SENSE registers */ + __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ + __I uint32_t RESERVED1[118]; + __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ +} NRF_GPIO_Type; -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_BPROT_BASE 0x40000000UL -#define NRF_POWER_BASE 0x40000000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UARTE0_BASE 0x40002000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_SPIM0_BASE 0x40003000UL -#define NRF_SPIS0_BASE 0x40003000UL -#define NRF_TWIM0_BASE 0x40003000UL -#define NRF_TWIS0_BASE 0x40003000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_SPIM1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_TWIM1_BASE 0x40004000UL -#define NRF_TWIS1_BASE 0x40004000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_NFCT_BASE 0x40005000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_SAADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_COMP_BASE 0x40013000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI0_BASE 0x40014000UL -#define NRF_EGU0_BASE 0x40014000UL -#define NRF_SWI1_BASE 0x40015000UL -#define NRF_EGU1_BASE 0x40015000UL -#define NRF_SWI2_BASE 0x40016000UL -#define NRF_EGU2_BASE 0x40016000UL -#define NRF_SWI3_BASE 0x40017000UL -#define NRF_EGU3_BASE 0x40017000UL -#define NRF_SWI4_BASE 0x40018000UL -#define NRF_EGU4_BASE 0x40018000UL -#define NRF_SWI5_BASE 0x40019000UL -#define NRF_EGU5_BASE 0x40019000UL -#define NRF_TIMER3_BASE 0x4001A000UL -#define NRF_TIMER4_BASE 0x4001B000UL -#define NRF_PWM0_BASE 0x4001C000UL -#define NRF_PDM_BASE 0x4001D000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_MWU_BASE 0x40020000UL -#define NRF_PWM1_BASE 0x40021000UL -#define NRF_PWM2_BASE 0x40022000UL -#define NRF_SPIM2_BASE 0x40023000UL -#define NRF_SPIS2_BASE 0x40023000UL -#define NRF_SPI2_BASE 0x40023000UL -#define NRF_RTC2_BASE 0x40024000UL -#define NRF_I2S_BASE 0x40025000UL -#define NRF_FPU_BASE 0x40026000UL -#define NRF_P0_BASE 0x50000000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) -#define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) -#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) -#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) -#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) -#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) -#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) -#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) -#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) -#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) -#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) -#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) -#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) -#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) -#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) -#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) -#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) -#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) -#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) -#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) -#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) -#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) -#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) -#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) -#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) -#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) -#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) -#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) -#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) -#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) -#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) -#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) -#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) -#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) -#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) -#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) -#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) -#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) -#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) -#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) -#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) -#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) -#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) -#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) -#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) -#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) -#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - - -/* ========================================= End of section using anonymous unions ========================================= */ -#if defined (__CC_ARM) +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) #pragma pop -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) /* leave anonymous unions enabled */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) +#elif defined(__GNUC__) /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) +#elif defined(__TMS470__) /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) +#elif defined(__TASKING__) #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type #endif + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_BPROT_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_AMLI_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_P0_BASE 0x50000000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE) +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) +#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf52 */ +/** @} */ /* End of group Nordic Semiconductor */ + #ifdef __cplusplus } #endif -#endif /* NRF52_H */ - -/** @} */ /* End of group nrf52 */ +#endif /* nrf52_H */ -/** @} */ /* End of group Nordic Semiconductor */ diff --git a/cores/nRF5/SDK/components/device/nrf52832_peripherals.h b/cores/nRF5/SDK/components/device/nrf52832_peripherals.h index 722e2115..18fbbef4 100644 --- a/cores/nRF5/SDK/components/device/nrf52832_peripherals.h +++ b/cores/nRF5/SDK/components/device/nrf52832_peripherals.h @@ -1,60 +1,37 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef _NRF52832_PERIPHERALS_H #define _NRF52832_PERIPHERALS_H -/* Clock Peripheral */ -#define CLOCK_PRESENT -#define CLOCK_COUNT 1 - -/* Power Peripheral */ -#define POWER_PRESENT -#define POWER_COUNT 1 - -#define POWER_FEATURE_RAM_REGISTERS_PRESENT -#if defined(NRF52832_XXAA) - #define POWER_FEATURE_RAM_REGISTERS_COUNT 8 -#elif defined(NRF52832_XXAB) - #define POWER_FEATURE_RAM_REGISTERS_COUNT 4 -#endif - -/* Non-Volatile Memory Controller */ -#define NVMC_PRESENT -#define NVMC_COUNT 1 - -#define NVMC_FEATURE_CACHE_PRESENT - /* Floating Point Unit */ #define FPU_PRESENT #define FPU_COUNT 1 @@ -77,27 +54,16 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_PIN_NUM 32 -#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL - /* MPU and BPROT */ #define BPROT_PRESENT #define BPROT_REGIONS_SIZE 4096 - -#if defined(NRF52832_XXAA) - #define BPROT_REGIONS_NUM 128 -#elif defined(NRF52832_XXAB) - #define BPROT_REGIONS_NUM 64 -#endif +#define BPROT_REGIONS_NUM 128 /* Radio */ #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_EASYDMA_MAXCNT_SIZE 8 - -#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm - /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 @@ -116,14 +82,11 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_PRESENT #define NFCT_COUNT 1 -#define NFCT_EASYDMA_MAXCNT_SIZE 9 - /* Peripheral to Peripheral Interconnect */ #define PPI_PRESENT #define PPI_COUNT 1 #define PPI_CH_NUM 20 -#define PPI_FIXED_CH_NUM 12 #define PPI_GROUP_NUM 6 #define PPI_FEATURE_FORKS_PRESENT @@ -182,34 +145,10 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PRESENT #define SPIM_COUNT 3 -#define SPIM0_MAX_DATARATE 8 -#define SPIM1_MAX_DATARATE 8 -#define SPIM2_MAX_DATARATE 8 - -#define SPIM0_FEATURE_HARDWARE_CSN_PRESENT 0 -#define SPIM1_FEATURE_HARDWARE_CSN_PRESENT 0 -#define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 - -#define SPIM0_FEATURE_DCX_PRESENT 0 -#define SPIM1_FEATURE_DCX_PRESENT 0 -#define SPIM2_FEATURE_DCX_PRESENT 0 - -#define SPIM0_FEATURE_RXDELAY_PRESENT 0 -#define SPIM1_FEATURE_RXDELAY_PRESENT 0 -#define SPIM2_FEATURE_RXDELAY_PRESENT 0 - -#define SPIM0_EASYDMA_MAXCNT_SIZE 8 -#define SPIM1_EASYDMA_MAXCNT_SIZE 8 -#define SPIM2_EASYDMA_MAXCNT_SIZE 8 - /* Serial Peripheral Interface Slave with DMA*/ #define SPIS_PRESENT #define SPIS_COUNT 3 -#define SPIS0_EASYDMA_MAXCNT_SIZE 8 -#define SPIS1_EASYDMA_MAXCNT_SIZE 8 -#define SPIS2_EASYDMA_MAXCNT_SIZE 8 - /* Two Wire Interface Master */ #define TWI_PRESENT #define TWI_COUNT 2 @@ -218,16 +157,10 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PRESENT #define TWIM_COUNT 2 -#define TWIM0_EASYDMA_MAXCNT_SIZE 8 -#define TWIM1_EASYDMA_MAXCNT_SIZE 8 - /* Two Wire Interface Slave with DMA */ #define TWIS_PRESENT #define TWIS_COUNT 2 -#define TWIS0_EASYDMA_MAXCNT_SIZE 8 -#define TWIS1_EASYDMA_MAXCNT_SIZE 8 - /* Universal Asynchronous Receiver-Transmitter */ #define UART_PRESENT #define UART_COUNT 1 @@ -236,8 +169,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PRESENT #define UARTE_COUNT 1 -#define UARTE0_EASYDMA_MAXCNT_SIZE 8 - /* Quadrature Decoder */ #define QDEC_PRESENT #define QDEC_COUNT 1 @@ -246,10 +177,6 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PRESENT #define SAADC_COUNT 1 -#define SAADC_EASYDMA_MAXCNT_SIZE 15 - -#define SAADC_CH_NUM 8 - /* GPIO Tasks and Events */ #define GPIOTE_PRESENT #define GPIOTE_COUNT 1 @@ -279,21 +206,13 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM1_CH_NUM 4 #define PWM2_CH_NUM 4 -#define PWM0_EASYDMA_MAXCNT_SIZE 15 -#define PWM1_EASYDMA_MAXCNT_SIZE 15 -#define PWM2_EASYDMA_MAXCNT_SIZE 15 - /* Pulse Density Modulator */ #define PDM_PRESENT #define PDM_COUNT 1 -#define PDM_EASYDMA_MAXCNT_SIZE 15 - /* Inter-IC Sound Interface */ #define I2S_PRESENT #define I2S_COUNT 1 -#define I2S_EASYDMA_MAXCNT_SIZE 14 - #endif // _NRF52832_PERIPHERALS_H diff --git a/cores/nRF5/SDK/components/device/nrf52840.h b/cores/nRF5/SDK/components/device/nrf52840.h index 296d613d..465ade15 100644 --- a/cores/nRF5/SDK/components/device/nrf52840.h +++ b/cores/nRF5/SDK/components/device/nrf52840.h @@ -1,40 +1,46 @@ -/* - * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * + +/****************************************************************************************************//** * @file nrf52840.h - * @brief CMSIS HeaderFile - * @version 1 - * @date 04. November 2020 - * @note Generated by SVDConv V3.3.35 on Wednesday, 04.11.2020 13:48:08 - * from File 'nrf52840.svd', - * last modified on Wednesday, 04.11.2020 12:48:01 - */ + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * nrf52840 from Nordic Semiconductor. + * + * @version V1 + * @date 18. November 2016 + * + * @note Generated with SVDConv V2.81d + * from CMSIS SVD File 'nrf52840.svd' Version 1, + * + * @par Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + *******************************************************************************************************/ @@ -42,12 +48,10 @@ * @{ */ - /** @addtogroup nrf52840 * @{ */ - #ifndef NRF52840_H #define NRF52840_H @@ -56,2873 +60,2358 @@ extern "C" { #endif -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ +/* ------------------------- Interrupt Number Definition ------------------------ */ typedef enum { -/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ -/* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ - SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ - SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ - NFCT_IRQn = 5, /*!< 5 NFCT */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - SAADC_IRQn = 7, /*!< 7 SAADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ - SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ - SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ - SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ - SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ - SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ - SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ - TIMER3_IRQn = 26, /*!< 26 TIMER3 */ - TIMER4_IRQn = 27, /*!< 27 TIMER4 */ - PWM0_IRQn = 28, /*!< 28 PWM0 */ - PDM_IRQn = 29, /*!< 29 PDM */ - MWU_IRQn = 32, /*!< 32 MWU */ - PWM1_IRQn = 33, /*!< 33 PWM1 */ - PWM2_IRQn = 34, /*!< 34 PWM2 */ - SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ - RTC2_IRQn = 36, /*!< 36 RTC2 */ - I2S_IRQn = 37, /*!< 37 I2S */ - FPU_IRQn = 38, /*!< 38 FPU */ - USBD_IRQn = 39, /*!< 39 USBD */ - UARTE1_IRQn = 40, /*!< 40 UARTE1 */ - QSPI_IRQn = 41, /*!< 41 QSPI */ - CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ - PWM3_IRQn = 45, /*!< 45 PWM3 */ - SPIM3_IRQn = 47 /*!< 47 SPIM3 */ +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- nrf52840 Specific Interrupt Numbers -------------------- */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38, /*!< 38 FPU */ + USBD_IRQn = 39, /*!< 39 USBD */ + UARTE1_IRQn = 40, /*!< 40 UARTE1 */ + QSPI_IRQn = 41, /*!< 41 QSPI */ + CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ + SPIM3_IRQn = 43, /*!< 43 SPIM3 */ + PWM3_IRQn = 45 /*!< 45 PWM3 */ } IRQn_Type; +/** @addtogroup Configuration_of_CMSIS + * @{ + */ -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ -#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ -#define __DSP_PRESENT 1 /*!< DSP present or not */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __MPU_PRESENT 1 /*!< MPU present */ -#define __FPU_PRESENT 1 /*!< FPU present */ +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ /** @} */ /* End of group Configuration_of_CMSIS */ -#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ -#include "system_nrf52840.h" /*!< nrf52840 System */ +#include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ +#include "system_nrf52840.h" /*!< nrf52840 System */ -#ifndef __IM /*!< Fallback for older CMSIS versions */ - #define __IM __I -#endif -#ifndef __OM /*!< Fallback for older CMSIS versions */ - #define __OM __O -#endif -#ifndef __IOM /*!< Fallback for older CMSIS versions */ - #define __IOM __IO -#endif + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ -/* ======================================== Start of section using anonymous unions ======================================== */ -#if defined (__CC_ARM) +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) #pragma push #pragma anon_unions -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" - #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" - #pragma clang diagnostic ignored "-Wnested-anon-types" -#elif defined (__GNUC__) +#elif defined(__GNUC__) /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ #else #warning Not supported compiler type #endif -/* =========================================================================================================================== */ -/* ================ Device Specific Cluster Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_clusters - * @{ - */ - - -/** - * @brief FICR_INFO [INFO] (Device info) - */ typedef struct { - __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ - __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ - __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ - __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ - __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ -} FICR_INFO_Type; /*!< Size = 20 (0x14) */ - + __I uint32_t PART; /*!< Part code */ + __I uint32_t VARIANT; /*!< Part variant (hardware version and production configuration). */ + __I uint32_t PACKAGE; /*!< Package option */ + __I uint32_t RAM; /*!< RAM variant */ + __I uint32_t FLASH; /*!< Flash variant */ + __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */ +} FICR_INFO_Type; -/** - * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) - */ typedef struct { - __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ - __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ - __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ - __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ - __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ - __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ - __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ - __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ - __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ - __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ - __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ - __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ - __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ - __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ - __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ - __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ - __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ -} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ - + __I uint32_t A0; /*!< Slope definition A0. */ + __I uint32_t A1; /*!< Slope definition A1. */ + __I uint32_t A2; /*!< Slope definition A2. */ + __I uint32_t A3; /*!< Slope definition A3. */ + __I uint32_t A4; /*!< Slope definition A4. */ + __I uint32_t A5; /*!< Slope definition A5. */ + __I uint32_t B0; /*!< y-intercept B0. */ + __I uint32_t B1; /*!< y-intercept B1. */ + __I uint32_t B2; /*!< y-intercept B2. */ + __I uint32_t B3; /*!< y-intercept B3. */ + __I uint32_t B4; /*!< y-intercept B4. */ + __I uint32_t B5; /*!< y-intercept B5. */ + __I uint32_t T0; /*!< Segment end T0. */ + __I uint32_t T1; /*!< Segment end T1. */ + __I uint32_t T2; /*!< Segment end T2. */ + __I uint32_t T3; /*!< Segment end T3. */ + __I uint32_t T4; /*!< Segment end T4. */ +} FICR_TEMP_Type; -/** - * @brief FICR_NFC [NFC] (Unspecified) - */ typedef struct { - __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST, and NFCID1_LAST. */ - __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST, and NFCID1_LAST. */ - __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST, and NFCID1_LAST. */ - __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read - these values to populate NFCID1_3RD_LAST, - NFCID1_2ND_LAST, and NFCID1_LAST. */ -} FICR_NFC_Type; /*!< Size = 16 (0x10) */ - + __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ + __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to + populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ +} FICR_NFC_Type; -/** - * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) - */ typedef struct { - __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ - __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ - __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ - __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ - __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ - __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ - __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ - __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ -} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ - + __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */ + __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */ + __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */ + __I uint32_t RESERVED0; +} POWER_RAM_Type; -/** - * @brief POWER_RAM [RAM] (Unspecified) - */ typedef struct { - __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ - __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ - __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear - register */ - __IM uint32_t RESERVED; -} POWER_RAM_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t RTS; /*!< Pin select for RTS signal */ + __IO uint32_t TXD; /*!< Pin select for TXD signal */ + __IO uint32_t CTS; /*!< Pin select for CTS signal */ + __IO uint32_t RXD; /*!< Pin select for RXD signal */ +} UARTE_PSEL_Type; -/** - * @brief UART_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ - __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ - __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ - __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ -} UART_PSEL_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; -/** - * @brief UARTE_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ - __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ - __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ - __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ -} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; -/** - * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ -} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t RTS; /*!< Pin select for RTS */ + __IO uint32_t TXD; /*!< Pin select for TXD */ + __IO uint32_t CTS; /*!< Pin select for CTS */ + __IO uint32_t RXD; /*!< Pin select for RXD */ +} UART_PSEL_Type; -/** - * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ -} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t CSN; /*!< Pin select for CSN */ +} SPIM_PSEL_Type; -/** - * @brief SPI_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ - __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ - __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ -} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_RXD_Type; -/** - * @brief SPIM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ - __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ - __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ - __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ -} SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} SPIM_TXD_Type; -/** - * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t RXDELAY; /*!< Sample delay for input serial data on MISO */ + __IO uint32_t CSNDUR; /*!< Minimum duration between edge of CSN and edge of SCK and minimum + duration CSN must stay high between transactions */ +} SPIM_IFTIMING_Type; - -/** - * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t CSN; /*!< Pin select for CSN signal */ +} SPIS_PSEL_Type; - -/** - * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) - */ typedef struct { - __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ - __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge - of SCK and minimum duration CSN must stay - high between transactions */ -} SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t PTR; /*!< RXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */ +} SPIS_RXD_Type; - -/** - * @brief SPIS_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ - __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ - __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ - __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ -} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t PTR; /*!< TXD data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */ +} SPIS_TXD_Type; - -/** - * @brief SPIS_RXD [RXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIM_PSEL_Type; - -/** - * @brief SPIS_TXD [TXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_RXD_Type; - -/** - * @brief TWI_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ - __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ -} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ + __IO uint32_t LIST; /*!< EasyDMA list type */ +} TWIM_TXD_Type; - -/** - * @brief TWIM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ - __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ -} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t SCL; /*!< Pin select for SCL signal */ + __IO uint32_t SDA; /*!< Pin select for SDA signal */ +} TWIS_PSEL_Type; - -/** - * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< RXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */ +} TWIS_RXD_Type; -/** - * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< TXD Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */ +} TWIS_TXD_Type; -/** - * @brief TWIS_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ - __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ -} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t SCK; /*!< Pin select for SCK */ + __IO uint32_t MOSI; /*!< Pin select for MOSI signal */ + __IO uint32_t MISO; /*!< Pin select for MISO signal */ +} SPI_PSEL_Type; -/** - * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t SCL; /*!< Pin select for SCL */ + __IO uint32_t SDA; /*!< Pin select for SDA */ +} TWI_PSEL_Type; -/** - * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ - __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ -} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t RX; /*!< Result of last incoming frame */ +} NFCT_FRAMESTATUS_Type; -/** - * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) - */ typedef struct { - __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ -} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ - + __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */ + __IO uint32_t AMOUNT; /*!< Size of outgoing frame */ +} NFCT_TXD_Type; -/** - * @brief NFCT_TXD [TXD] (Unspecified) - */ typedef struct { - __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ - __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ -} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */ + __I uint32_t AMOUNT; /*!< Size of last incoming frame */ +} NFCT_RXD_Type; -/** - * @brief NFCT_RXD [RXD] (Unspecified) - */ typedef struct { - __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ -} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */ + __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; -/** - * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) - */ typedef struct { - __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or - above CH[n].LIMIT.HIGH */ - __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or - below CH[n].LIMIT.LOW */ -} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */ + __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */ + __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */ + __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring + a channel */ +} SAADC_CH_Type; -/** - * @brief SAADC_CH [CH] (Unspecified) - */ typedef struct { - __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection - for CH[n] */ - __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection - for CH[n] */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for - CH[n] */ - __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event - monitoring of a channel */ -} SAADC_CH_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */ + __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */ +} SAADC_RESULT_Type; -/** - * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written - to output RAM buffer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM - buffer since the previous START task */ -} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t LED; /*!< Pin select for LED signal */ + __IO uint32_t A; /*!< Pin select for A signal */ + __IO uint32_t B; /*!< Pin select for B signal */ +} QDEC_PSEL_Type; -/** - * @brief QDEC_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ - __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ - __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ -} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence + A */ + __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence + A */ + __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between + samples loaded to compare register (load every CNT+1 PWM periods) */ + __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */ + __I uint32_t RESERVED1[4]; +} PWM_SEQ_Type; -/** - * @brief PWM_SEQ [SEQ] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM - of this sequence */ - __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) - in this sequence */ - __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM - periods between samples loaded into compare - register */ - __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ - __IM uint32_t RESERVED[4]; -} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ - + __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel + 0 */ +} PWM_PSEL_Type; -/** - * @brief PWM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for - PWM channel n */ -} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ - + __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */ + __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; -/** - * @brief PDM_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ - __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ -} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */ + __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */ +} PDM_SAMPLE_Type; -/** - * @brief PDM_SAMPLE [SAMPLE] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with - EasyDMA */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA - mode */ -} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t ADDR; /*!< Description cluster[0]: Configure the word-aligned start address + of region 0 to protect */ + __IO uint32_t SIZE; /*!< Description cluster[0]: Size of region to protect counting from + address ACL[0].ADDR. Write '0' as no effect. */ + __IO uint32_t PERM; /*!< Description cluster[0]: Access permissions for region 0 as defined + by start address ACL[0].ADDR and size ACL[0].SIZE */ + __IO uint32_t UNUSED0; /*!< Unspecified */ +} ACL_ACL_Type; -/** - * @brief ACL_ACL [ACL] (Unspecified) - */ typedef struct { - __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Configure the word-aligned - start address of region n to protect */ - __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect - counting from address ACL[n].ADDR. Write - '0' as no effect. */ - __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region - n as defined by start address ACL[n].ADDR - and size ACL[n].SIZE */ - __IM uint32_t RESERVED; -} ACL_ACL_Type; /*!< Size = 16 (0x10) */ - + __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */ + __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */ +} PPI_TASKS_CHG_Type; -/** - * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) - */ typedef struct { - __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ - __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ -} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */ + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_CH_Type; -/** - * @brief PPI_CH [CH] (PPI Channel) - */ typedef struct { - __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */ - __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */ -} PPI_CH_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */ +} PPI_FORK_Type; -/** - * @brief PPI_FORK [FORK] (Fork) - */ typedef struct { - __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */ -} PPI_FORK_Type; /*!< Size = 4 (0x4) */ - + __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */ +} MWU_EVENTS_REGION_Type; -/** - * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) - */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n - detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n - detected */ -} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0 + detected */ + __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */ +} MWU_EVENTS_PREGION_Type; -/** - * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) - */ typedef struct { - __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral - region n detected */ - __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral - region n detected */ -} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, write access detected while corresponding subregion was enabled + for watching */ + __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region + 0, read access detected while corresponding subregion was enabled + for watching */ +} MWU_PERREGION_Type; -/** - * @brief MWU_PERREGION [PERREGION] (Unspecified) - */ typedef struct { - __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt - in region n, write access detected while - corresponding subregion was enabled for - watching */ - __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt - in region n, read access detected while - corresponding subregion was enabled for - watching */ -} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ - + __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */ + __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */ + __I uint32_t RESERVED2[2]; +} MWU_REGION_Type; -/** - * @brief MWU_REGION [REGION] (Unspecified) - */ typedef struct { - __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region - n */ - __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ - __IM uint32_t RESERVED[2]; -} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */ + __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */ + __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */ + __I uint32_t RESERVED3; +} MWU_PREGION_Type; - -/** - * @brief MWU_PREGION [PREGION] (Unspecified) - */ typedef struct { - __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ - __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ - __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ - __IM uint32_t RESERVED; -} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + __IO uint32_t MODE; /*!< I2S mode. */ + __IO uint32_t RXEN; /*!< Reception (RX) enable. */ + __IO uint32_t TXEN; /*!< Transmission (TX) enable. */ + __IO uint32_t MCKEN; /*!< Master clock generator enable. */ + __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */ + __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */ + __IO uint32_t SWIDTH; /*!< Sample width. */ + __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */ + __IO uint32_t FORMAT; /*!< Frame format. */ + __IO uint32_t CHANNELS; /*!< Enable channels. */ +} I2S_CONFIG_Type; - -/** - * @brief I2S_CONFIG [CONFIG] (Unspecified) - */ typedef struct { - __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ - __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ - __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ - __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ - __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ - __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ - __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ - __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ - __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ - __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ -} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + __IO uint32_t PTR; /*!< Receive buffer RAM start address. */ +} I2S_RXD_Type; - -/** - * @brief I2S_RXD [RXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ -} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */ +} I2S_TXD_Type; - -/** - * @brief I2S_TXD [TXD] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ -} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; - -/** - * @brief I2S_RXTXD [RXTXD] (Unspecified) - */ typedef struct { - __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ -} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + __IO uint32_t MCK; /*!< Pin select for MCK signal. */ + __IO uint32_t SCK; /*!< Pin select for SCK signal. */ + __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */ + __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */ + __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */ +} I2S_PSEL_Type; - -/** - * @brief I2S_PSEL [PSEL] (Unspecified) - */ typedef struct { - __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ - __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ - __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ - __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ - __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ -} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + __I uint32_t EPIN[8]; /*!< Description collection[0]: IN endpoint halted status. Can be + used as is as response to a GetStatus() request to endpoint. */ + __I uint32_t RESERVED4; + __I uint32_t EPOUT[8]; /*!< Description collection[0]: OUT endpoint halted status. Can be + used as is as response to a GetStatus() request to endpoint. */ +} USBD_HALTED_Type; - -/** - * @brief USBD_HALTED [HALTED] (Unspecified) - */ typedef struct { - __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. - Can be used as is as response to a GetStatus() - request to endpoint. */ - __IM uint32_t RESERVED; - __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. - Can be used as is as response to a GetStatus() - request to endpoint. */ -} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ + __IO uint32_t EPOUT[8]; /*!< Description collection[0]: Amount of bytes received last in + the data stage of this OUT endpoint */ + __IO uint32_t ISOOUT; /*!< Amount of bytes received last on this iso OUT data endpoint */ +} USBD_SIZE_Type; - -/** - * @brief USBD_SIZE [SIZE] (Unspecified) - */ typedef struct { - __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received - last in the data stage of this OUT endpoint */ - __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT - data endpoint */ -} USBD_SIZE_Type; /*!< Size = 36 (0x24) */ - + __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */ + __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last + transaction */ + __I uint32_t RESERVED5[2]; +} USBD_EPIN_Type; -/** - * @brief USBD_EPIN [EPIN] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes - to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred - in the last transaction */ - __IM uint32_t RESERVED[2]; -} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; -/** - * @brief USBD_ISOIN [ISOIN] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ -} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PTR; /*!< Description cluster[0]: Data pointer */ + __IO uint32_t MAXCNT; /*!< Description cluster[0]: Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Description cluster[0]: Number of bytes transferred in the last + transaction */ + __I uint32_t RESERVED6[2]; +} USBD_EPOUT_Type; -/** - * @brief USBD_EPOUT [EPOUT] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes - to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred - in the last transaction */ - __IM uint32_t RESERVED[2]; -} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ - + __IO uint32_t PTR; /*!< Data pointer */ + __IO uint32_t MAXCNT; /*!< Maximum number of bytes to transfer */ + __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; -/** - * @brief USBD_ISOOUT [ISOOUT] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ - __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ - __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ -} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t SRC; /*!< Flash memory source address */ + __IO uint32_t DST; /*!< RAM destination address */ + __IO uint32_t CNT; /*!< Read transfer length */ +} QSPI_READ_Type; -/** - * @brief QSPI_READ [READ] (Unspecified) - */ typedef struct { - __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ - __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ - __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ -} QSPI_READ_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t DST; /*!< Flash destination address */ + __IO uint32_t SRC; /*!< RAM source address */ + __IO uint32_t CNT; /*!< Write transfer length */ +} QSPI_WRITE_Type; -/** - * @brief QSPI_WRITE [WRITE] (Unspecified) - */ typedef struct { - __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ - __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ - __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ -} QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ - + __IO uint32_t PTR; /*!< Start address of flash block to be erased */ + __IO uint32_t LEN; /*!< Size of block to be erased. */ +} QSPI_ERASE_Type; -/** - * @brief QSPI_ERASE [ERASE] (Unspecified) - */ typedef struct { - __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ - __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ -} QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ + __IO uint32_t SCK; /*!< Pin select for serial clock SCK */ + __IO uint32_t CSN; /*!< Pin select for chip select signal CSN. */ + __I uint32_t RESERVED7; + __IO uint32_t IO0; /*!< Pin select for serial data MOSI/IO0. */ + __IO uint32_t IO1; /*!< Pin select for serial data MISO/IO1. */ + __IO uint32_t IO2; /*!< Pin select for serial data IO2. */ + __IO uint32_t IO3; /*!< Pin select for serial data IO3. */ +} QSPI_PSEL_Type; -/** - * @brief QSPI_PSEL [PSEL] (Unspecified) - */ -typedef struct { - __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ - __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ - __IM uint32_t RESERVED; - __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ - __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ - __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ - __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ -} QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ - - -/** @} */ /* End of group Device_Peripheral_clusters */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - - - -/* =========================================================================================================================== */ -/* ================ FICR ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ FICR ================ */ +/* ================================================================================ */ /** - * @brief Factory information configuration registers (FICR) + * @brief Factory Information Configuration Registers (FICR) */ -typedef struct { /*!< (@ 0x10000000) FICR Structure */ - __IM uint32_t RESERVED[4]; - __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ - __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ - __IM uint32_t RESERVED1[18]; - __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ - __IM uint32_t RESERVED2[6]; - __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word - n */ - __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ - __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ - __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ - __IM uint32_t RESERVED3[21]; - __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ - __IM uint32_t RESERVED4[143]; - __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature - n */ - __IM uint32_t RESERVED5[42]; - __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization - coefficients */ - __IM uint32_t RESERVED6[2]; - __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ - __IM uint32_t RESERVED7[488]; - __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ -} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ - - - -/* =========================================================================================================================== */ -/* ================ UICR ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< FICR Structure */ + __I uint32_t RESERVED0[4]; + __I uint32_t CODEPAGESIZE; /*!< Code memory page size */ + __I uint32_t CODESIZE; /*!< Code memory size */ + __I uint32_t RESERVED1[18]; + __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */ + __I uint32_t RESERVED2[6]; + __I uint32_t ER[4]; /*!< Description collection[0]: Encryption root, word 0 */ + __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */ + __I uint32_t DEVICEADDRTYPE; /*!< Device address type */ + __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */ + __I uint32_t RESERVED3[21]; + FICR_INFO_Type INFO; /*!< Device info */ + __I uint32_t RESERVED4[185]; + FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */ + __I uint32_t RESERVED5[2]; + FICR_NFC_Type NFC; /*!< Unspecified */ +} NRF_FICR_Type; -/** - * @brief User information configuration registers (UICR) - */ - -typedef struct { /*!< (@ 0x10001000) UICR Structure */ - __IM uint32_t RESERVED[5]; - __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware - design */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware - design */ - __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET - function (see POWER chapter for details) */ - __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ - __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: - NFC antenna or GPIO */ - __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ - __IM uint32_t RESERVED3[60]; - __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) GPIO reference voltage / external output supply - voltage in high voltage mode */ -} NRF_UICR_Type; /*!< Size = 776 (0x308) */ - - - -/* =========================================================================================================================== */ -/* ================ CLOCK ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ UICR ================ */ +/* ================================================================================ */ /** - * @brief Clock control (CLOCK) + * @brief User Information Configuration Registers (UICR) */ -typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ - __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ - __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ - __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ - __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ - __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ - __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ - __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ - __IM uint32_t RESERVED[57]; - __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ - __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ - __IM uint32_t RESERVED1; - __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ - __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ - __IM uint32_t RESERVED2[5]; - __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready - to process new tasks */ - __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready - to process new tasks */ - __IM uint32_t RESERVED3[117]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[63]; - __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been - triggered */ - __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ - __IM uint32_t RESERVED5; - __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been - triggered */ - __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ - __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART - task was triggered */ - __IM uint32_t RESERVED6[62]; - __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ - __IM uint32_t RESERVED7[3]; - __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering - the TASKS_HFCLKSTART task. */ - __IM uint32_t RESERVED8[3]; - __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ - __IM uint32_t RESERVED9[8]; - __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ - __IM uint32_t RESERVED10[21]; - __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ -} NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ - - - -/* =========================================================================================================================== */ -/* ================ POWER ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< UICR Structure */ + __IO uint32_t UNUSED0; /*!< Unspecified */ + __IO uint32_t UNUSED1; /*!< Unspecified */ + __IO uint32_t UNUSED2; /*!< Unspecified */ + __I uint32_t RESERVED0; + __IO uint32_t UNUSED3; /*!< Unspecified */ + __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */ + __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */ + __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */ + __I uint32_t RESERVED1[64]; + __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function */ + __IO uint32_t APPROTECT; /*!< Access port protection */ + __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna + or GPIO */ + __I uint32_t RESERVED2[60]; + __IO uint32_t EXTSUPPLY; /*!< Enable external circuitry to be supplied from VDD pin. Applicable + in 'High voltage mode' only. */ + __IO uint32_t REGOUT0; /*!< GPIO reference voltage / external output supply voltage in 'High + voltage mode'. */ +} NRF_UICR_Type; -/** - * @brief Power control (POWER) - */ - -typedef struct { /*!< (@ 0x40000000) POWER Structure */ - __IM uint32_t RESERVED[30]; - __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ - __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ - __IM uint32_t RESERVED1[34]; - __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ - __IM uint32_t RESERVED2[2]; - __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ - __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ - __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ - __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ - __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ - __IM uint32_t RESERVED3[119]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[61]; - __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ - __IM uint32_t RESERVED5[9]; - __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ - __IM uint32_t RESERVED6[3]; - __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ - __IM uint32_t RESERVED7[49]; - __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ - __IM uint32_t RESERVED8[3]; - __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ - __IM uint32_t RESERVED9[2]; - __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ - __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ - __IM uint32_t RESERVED10[21]; - __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ - __IM uint32_t RESERVED11; - __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */ - __IM uint32_t RESERVED12[47]; - __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ - __IM uint32_t RESERVED13[175]; - __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ -} NRF_POWER_Type; /*!< Size = 2448 (0x990) */ - - - -/* =========================================================================================================================== */ -/* ================ P0 ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ POWER ================ */ +/* ================================================================================ */ /** - * @brief GPIO Port 1 (P0) - */ - -typedef struct { /*!< (@ 0x50000000) P0 Structure */ - __IM uint32_t RESERVED[321]; - __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ - __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ - __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ - __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ - __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ - __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ - __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ - __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that - have met the criteria set in the PIN_CNF[n].SENSE - registers */ - __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour - and LDETECT mode */ - __IM uint32_t RESERVED1[118]; - __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO - pins */ -} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ - - - -/* =========================================================================================================================== */ -/* ================ RADIO ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief 2.4 GHz radio (RADIO) - */ - -typedef struct { /*!< (@ 0x40001000) RADIO Structure */ - __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ - __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ - __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ - __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of - the receive signal strength */ - __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ - __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ - __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ - __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE - 802.15.4 mode */ - __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ - __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE - 802.15.4 mode */ - __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ - __IM uint32_t RESERVED[51]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ - __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ - __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ - __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ - __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received - packet */ - __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last - received packet */ - __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ - __IM uint32_t RESERVED2; - __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ - __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ - __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ - __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new - ED sample is ready for readout from the - RADIO.EDSAMPLE register. */ - __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ - __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ - __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ - __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ - __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed - from Ble_LR125Kbit to Ble_LR500Kbit. */ - __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started - TX path */ - __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started - RX path */ - __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator. */ - __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and - Ieee802154_250Kbit modes when last bit is - sent on air. */ - __IM uint32_t RESERVED4[36]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED5[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED6[61]; - __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ - __IM uint32_t RESERVED7; - __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ - __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ - __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ - __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ - __IM uint32_t RESERVED8[59]; - __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ - __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ - __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ - __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ - __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ - __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ - __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ - __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ - __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ - __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ - __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ - __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ - __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ - __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ - __IM uint32_t RESERVED9; - __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ - __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ - __IM uint32_t RESERVED10; - __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ - __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ - __IM uint32_t RESERVED11[2]; - __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ - __IM uint32_t RESERVED12[39]; - __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment - n */ - __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix - n */ - __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ - __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ - __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ - __IM uint32_t RESERVED13; - __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ - __IM uint32_t RESERVED14[3]; - __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ - __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ - __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ - __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ - __IM uint32_t RESERVED15[611]; - __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ -} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ - - - -/* =========================================================================================================================== */ -/* ================ UART0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Universal Asynchronous Receiver/Transmitter (UART0) - */ - -typedef struct { /*!< (@ 0x40002000) UART0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ - __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ - __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ - __IM uint32_t RESERVED[3]; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ - __IM uint32_t RESERVED1[56]; - __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ - __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ - __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ - __IM uint32_t RESERVED2[4]; - __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ - __IM uint32_t RESERVED3; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ - __IM uint32_t RESERVED5[46]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED6[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED7[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ - __IM uint32_t RESERVED8[31]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ - __IM uint32_t RESERVED9; - __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ - __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ - __IM uint32_t RESERVED10; - __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source - selected. */ - __IM uint32_t RESERVED11[17]; - __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ -} NRF_UART_Type; /*!< Size = 1392 (0x570) */ - - - -/* =========================================================================================================================== */ -/* ================ UARTE0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief UART with EasyDMA 0 (UARTE0) - */ - -typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ - __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ - __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ - __IM uint32_t RESERVED[7]; - __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ - __IM uint32_t RESERVED1[52]; - __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ - __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ - __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet - transferred to Data RAM) */ - __IM uint32_t RESERVED2; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ - __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ - __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ - __IM uint32_t RESERVED6; - __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ - __IM uint32_t RESERVED7[41]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED8[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[93]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write - one to clear. */ - __IM uint32_t RESERVED10[31]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ - __IM uint32_t RESERVED11; - __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[3]; - __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source - selected. */ - __IM uint32_t RESERVED13[3]; - __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IM uint32_t RESERVED14; - __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED15[7]; - __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ -} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ - - - -/* =========================================================================================================================== */ -/* ================ SPI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Serial Peripheral Interface 0 (SPI0) - */ - -typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ - __IM uint32_t RESERVED[66]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ - __IM uint32_t RESERVED1[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ - __IM uint32_t RESERVED3; - __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED4; - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ - __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ - __IM uint32_t RESERVED5; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK - source selected. */ - __IM uint32_t RESERVED6[11]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ -} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ - - - -/* =========================================================================================================================== */ -/* ================ SPIM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) - */ - -typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ - __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ - __IM uint32_t RESERVED1; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ - __IM uint32_t RESERVED2[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ - __IM uint32_t RESERVED4; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ - __IM uint32_t RESERVED6[10]; - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ - __IM uint32_t RESERVED7[44]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED8[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[61]; - __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields - in this register is set to STALL by hardware - whenever a stall occurres and can be cleared - (set to NOSTALL) by the CPU. */ - __IM uint32_t RESERVED10[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ - __IM uint32_t RESERVED11; - __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[3]; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK - source selected. */ - __IM uint32_t RESERVED13[3]; - __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED14[2]; - __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ - __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ - __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ - __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ - __IM uint32_t RESERVED15[19]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have - been transmitted in the case when RXD.MAXCNT - is greater than TXD.MAXCNT */ -} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ - - - -/* =========================================================================================================================== */ -/* ================ SPIS0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief SPI Slave 0 (SPIS0) - */ - -typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ - __IM uint32_t RESERVED[9]; - __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ - __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave - to acquire it */ - __IM uint32_t RESERVED1[54]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ - __IM uint32_t RESERVED2[2]; - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ - __IM uint32_t RESERVED4[53]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED5[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED6[61]; - __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ - __IM uint32_t RESERVED7[15]; - __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ - __IM uint32_t RESERVED8[47]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ - __IM uint32_t RESERVED9; - __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED10[7]; - __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ - __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ - __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ - __IM uint32_t RESERVED11; - __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case - of an ignored transaction. */ - __IM uint32_t RESERVED12[24]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ -} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ - - - -/* =========================================================================================================================== */ -/* ================ TWI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2C compatible Two-Wire Interface 0 (TWI0) - */ - -typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ - __IM uint32_t RESERVED1[2]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ - __IM uint32_t RESERVED2; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ - __IM uint32_t RESERVED3[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ - __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ - __IM uint32_t RESERVED4[4]; - __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ - __IM uint32_t RESERVED5; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ - __IM uint32_t RESERVED6[4]; - __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte - that is sent or received */ - __IM uint32_t RESERVED7[3]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ - __IM uint32_t RESERVED8[45]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED9[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED10[110]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ - __IM uint32_t RESERVED11[14]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ - __IM uint32_t RESERVED12; - __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED13[2]; - __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ - __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ - __IM uint32_t RESERVED14; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK - source selected. */ - __IM uint32_t RESERVED15[24]; - __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ -} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ - - - -/* =========================================================================================================================== */ -/* ================ TWIM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + * @brief Power control (POWER) */ -typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ - __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ - __IM uint32_t RESERVED1[2]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the - TWI master is not suspended. */ - __IM uint32_t RESERVED2; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ - __IM uint32_t RESERVED3[56]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ - __IM uint32_t RESERVED5[8]; - __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND - task has been issued, TWI traffic is now - suspended. */ - __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ - __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ - __IM uint32_t RESERVED6[2]; - __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ - __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last - byte */ - __IM uint32_t RESERVED7[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED8[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[110]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ - __IM uint32_t RESERVED10[14]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ - __IM uint32_t RESERVED11; - __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[5]; - __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK - source selected. */ - __IM uint32_t RESERVED13[3]; - __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED14[13]; - __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ -} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ - - - -/* =========================================================================================================================== */ -/* ================ TWIS0 ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< POWER Structure */ + __I uint32_t RESERVED0[30]; + __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */ + __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */ + __I uint32_t RESERVED1[34]; + __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */ + __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */ + __IO uint32_t EVENTS_USBDETECTED; /*!< Voltage supply detected on VBUS */ + __IO uint32_t EVENTS_USBREMOVED; /*!< Voltage supply removed from VBUS */ + __IO uint32_t EVENTS_USBPWRRDY; /*!< USB 3.3 V supply ready */ + __I uint32_t RESERVED3[119]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t RESETREAS; /*!< Reset reason */ + __I uint32_t RESERVED5[9]; + __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */ + __I uint32_t RESERVED6[3]; + __I uint32_t USBREGSTATUS; /*!< USB supply status */ + __I uint32_t RESERVED7[49]; + __O uint32_t SYSTEMOFF; /*!< System OFF register */ + __I uint32_t RESERVED8[3]; + __IO uint32_t POFCON; /*!< Power failure comparator configuration */ + __I uint32_t RESERVED9[2]; + __IO uint32_t GPREGRET; /*!< General purpose retention register */ + __IO uint32_t GPREGRET2; /*!< General purpose retention register */ + __I uint32_t RESERVED10[21]; + __IO uint32_t DCDCEN; /*!< Enable DC/DC converter for REG1 stage. */ + __I uint32_t RESERVED11; + __IO uint32_t DCDCEN0; /*!< Enable DC/DC converter for REG0 stage. */ + __I uint32_t RESERVED12[47]; + __I uint32_t MAINREGSTATUS; /*!< Main supply status */ + __I uint32_t RESERVED13[175]; + POWER_RAM_Type RAM[9]; /*!< Unspecified */ +} NRF_POWER_Type; + + +/* ================================================================================ */ +/* ================ CLOCK ================ */ +/* ================================================================================ */ /** - * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + * @brief Clock control (CLOCK) */ -typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ - __IM uint32_t RESERVED[5]; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ - __IM uint32_t RESERVED1; - __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ - __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ - __IM uint32_t RESERVED2[3]; - __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ - __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ - __IM uint32_t RESERVED3[51]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ - __IM uint32_t RESERVED4[7]; - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ - __IM uint32_t RESERVED5[9]; - __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ - __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ - __IM uint32_t RESERVED6[4]; - __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ - __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ - __IM uint32_t RESERVED7[37]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED8[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED9[113]; - __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ - __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had - a match */ - __IM uint32_t RESERVED10[10]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ - __IM uint32_t RESERVED11; - __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ - __IM uint32_t RESERVED12[9]; - __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ - __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ - __IM uint32_t RESERVED13[13]; - __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ - __IM uint32_t RESERVED14; - __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match - mechanism */ - __IM uint32_t RESERVED15[10]; - __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case - of an over-read of the transmit buffer. */ -} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ - - - -/* =========================================================================================================================== */ -/* ================ NFCT ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< CLOCK Structure */ + __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */ + __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */ + __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */ + __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */ + __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC or LFULP oscillator */ + __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */ + __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */ + __I uint32_t RESERVED0[57]; + __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */ + __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */ + __I uint32_t RESERVED1; + __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */ + __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */ + __I uint32_t RESERVED2[124]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[63]; + __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */ + __I uint32_t HFCLKSTAT; /*!< HFCLK status */ + __I uint32_t RESERVED4; + __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */ + __I uint32_t LFCLKSTAT; /*!< LFCLK status */ + __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ + __I uint32_t RESERVED5[62]; + __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */ + __I uint32_t RESERVED6[7]; + __IO uint32_t CTIV; /*!< Calibration timer interval */ + __I uint32_t RESERVED7[8]; + __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */ +} NRF_CLOCK_Type; + + +/* ================================================================================ */ +/* ================ RADIO ================ */ +/* ================================================================================ */ + + +/** + * @brief 2.4 GHz Radio (RADIO) + */ + +typedef struct { /*!< RADIO Structure */ + __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */ + __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */ + __O uint32_t TASKS_START; /*!< Start RADIO */ + __O uint32_t TASKS_STOP; /*!< Stop RADIO */ + __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */ + __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal + strength. */ + __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */ + __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */ + __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */ + __O uint32_t TASKS_EDSTART; /*!< Start the Energy Detect measurement used in IEEE 802.15.4 mode */ + __O uint32_t TASKS_EDSTOP; /*!< Stop the Energy Detect measurement */ + __O uint32_t TASKS_CCASTART; /*!< Start the Clear Channel Assessment used in IEEE 802.15.4 mode */ + __O uint32_t TASKS_CCASTOP; /*!< Stop the Clear Channel Assessment */ + __I uint32_t RESERVED0[51]; + __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */ + __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */ + __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */ + __IO uint32_t EVENTS_END; /*!< Packet sent or received */ + __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */ + __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */ + __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */ + __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */ + __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */ + __IO uint32_t EVENTS_FRAMESTART; /*!< IEEE 802.15.4 length field received */ + __IO uint32_t EVENTS_EDEND; /*!< Sampling of Energy Detection complete. A new ED sample is ready + for readout from the RADIO.EDSAMPLE register */ + __IO uint32_t EVENTS_EDSTOPPED; /*!< The sampling of Energy Detection has stopped */ + __IO uint32_t EVENTS_CCAIDLE; /*!< Wireless medium in idle - clear to send */ + __IO uint32_t EVENTS_CCABUSY; /*!< Wireless medium busy - do not send */ + __IO uint32_t EVENTS_CCASTOPPED; /*!< The CCA has stopped */ + __IO uint32_t EVENTS_RATEBOOST; /*!< Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit + to Ble_LR500Kbit. */ + __IO uint32_t EVENTS_TXREADY; /*!< RADIO has ramped up and is ready to be started TX path */ + __IO uint32_t EVENTS_RXREADY; /*!< RADIO has ramped up and is ready to be started RX path */ + __IO uint32_t EVENTS_MHRMATCH; /*!< MAC Header match found. */ + __I uint32_t RESERVED3[40]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED4[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[61]; + __I uint32_t CRCSTATUS; /*!< CRC status */ + __I uint32_t RESERVED6; + __I uint32_t RXMATCH; /*!< Received address */ + __I uint32_t RXCRC; /*!< CRC field of previously received packet */ + __I uint32_t DAI; /*!< Device address match index */ + __I uint32_t RESERVED7[60]; + __IO uint32_t PACKETPTR; /*!< Packet pointer */ + __IO uint32_t FREQUENCY; /*!< Frequency */ + __IO uint32_t TXPOWER; /*!< Output power */ + __IO uint32_t MODE; /*!< Data rate and modulation */ + __IO uint32_t PCNF0; /*!< Packet configuration register 0 */ + __IO uint32_t PCNF1; /*!< Packet configuration register 1 */ + __IO uint32_t BASE0; /*!< Base address 0 */ + __IO uint32_t BASE1; /*!< Base address 1 */ + __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */ + __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */ + __IO uint32_t TXADDRESS; /*!< Transmit address select */ + __IO uint32_t RXADDRESSES; /*!< Receive address select */ + __IO uint32_t CRCCNF; /*!< CRC configuration */ + __IO uint32_t CRCPOLY; /*!< CRC polynomial */ + __IO uint32_t CRCINIT; /*!< CRC initial value */ + __I uint32_t RESERVED8; + __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */ + __I uint32_t RSSISAMPLE; /*!< RSSI sample */ + __I uint32_t RESERVED9; + __I uint32_t STATE; /*!< Current radio state */ + __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */ + __I uint32_t RESERVED10[2]; + __IO uint32_t BCC; /*!< Bit counter compare */ + __I uint32_t RESERVED11[39]; + __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */ + __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */ + __IO uint32_t DACNF; /*!< Device address match configuration */ + __IO uint32_t MHRMATCHCONF; /*!< Search Pattern Configuration */ + __IO uint32_t MHRMATCHMAS; /*!< Pattern mask */ + __I uint32_t RESERVED12; + __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */ + __I uint32_t RESERVED13[3]; + __IO uint32_t SFD; /*!< IEEE 802.15.4 Start of Frame Delimiter */ + __IO uint32_t EDCNT; /*!< IEEE 802.15.4 Energy Detect Loop Count */ + __IO uint32_t EDSAMPLE; /*!< IEEE 802.15.4 Energy Detect Level */ + __IO uint32_t CCACTRL; /*!< IEEE 802.15.4 Clear Channel Assessment Control */ + __I uint32_t RESERVED14[611]; + __IO uint32_t POWER; /*!< Peripheral power control */ +} NRF_RADIO_Type; + + +/* ================================================================================ */ +/* ================ UARTE ================ */ +/* ================================================================================ */ + + +/** + * @brief UART with EasyDMA 0 (UARTE) + */ + +typedef struct { /*!< UARTE Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[7]; + __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */ + __I uint32_t RESERVED1[52]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD (but potentially not yet transferred to + Data RAM) */ + __I uint32_t RESERVED2; + __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */ + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */ + __I uint32_t RESERVED6; + __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */ + __I uint32_t RESERVED7[41]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[93]; + __IO uint32_t ERRORSRC; /*!< Error source Note : this register is read / write one to clear. */ + __I uint32_t RESERVED10[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED11; + UARTE_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED14; + UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED15[7]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART) + */ + +typedef struct { /*!< UART Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */ + __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */ + __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */ + __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */ + __I uint32_t RESERVED1[56]; + __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */ + __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */ + __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */ + __I uint32_t RESERVED2[4]; + __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */ + __I uint32_t RESERVED3; + __IO uint32_t EVENTS_ERROR; /*!< Error detected */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */ + __I uint32_t RESERVED5[46]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED6[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED7[93]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED8[31]; + __IO uint32_t ENABLE; /*!< Enable UART */ + __I uint32_t RESERVED9; + UART_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RXD; /*!< RXD register */ + __O uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED10; + __IO uint32_t BAUDRATE; /*!< Baud rate. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED11[17]; + __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */ +} NRF_UART_Type; + + +/* ================================================================================ */ +/* ================ SPIM ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM) + */ + +typedef struct { /*!< SPIM Structure */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_START; /*!< Start SPI transaction */ + __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */ + __I uint32_t RESERVED2[56]; + __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */ + __I uint32_t RESERVED6[10]; + __IO uint32_t EVENTS_STARTED; /*!< Transaction started */ + __I uint32_t RESERVED7[44]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[61]; + __IO uint32_t STALLSTAT; /*!< Stall status for EasyDMA RAM accesses. The fields in this register + is set to STALL by hardware whenever a stall occurres and can + be cleared (set to NOSTALL) by the CPU. */ + __I uint32_t RESERVED10[63]; + __IO uint32_t ENABLE; /*!< Enable SPIM */ + __I uint32_t RESERVED11; + SPIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[3]; + __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED14[2]; + SPIM_IFTIMING_Type IFTIMING; /*!< Unspecified */ + __I uint32_t RESERVED15[22]; + __IO uint32_t ORC; /*!< Byte transmitted after TXD.MAXCNT bytes have been transmitted + in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; + + +/* ================================================================================ */ +/* ================ SPIS ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI Slave 0 (SPIS) + */ + +typedef struct { /*!< SPIS Structure */ + __I uint32_t RESERVED0[9]; + __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */ + __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */ + __I uint32_t RESERVED1[54]; + __IO uint32_t EVENTS_END; /*!< Granted transaction completed */ + __I uint32_t RESERVED2[2]; + __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ + __I uint32_t RESERVED3[5]; + __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */ + __I uint32_t RESERVED4[53]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED5[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED6[61]; + __I uint32_t SEMSTAT; /*!< Semaphore status register */ + __I uint32_t RESERVED7[15]; + __IO uint32_t STATUS; /*!< Status from last transaction */ + __I uint32_t RESERVED8[47]; + __IO uint32_t ENABLE; /*!< Enable SPI slave */ + __I uint32_t RESERVED9; + SPIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED10[7]; + SPIS_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED11; + SPIS_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED12; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED13; + __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored + transaction. */ + __I uint32_t RESERVED14[24]; + __IO uint32_t ORC; /*!< Over-read character */ +} NRF_SPIS_Type; + + +/* ================================================================================ */ +/* ================ TWIM ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM) + */ + +typedef struct { /*!< TWIM Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is + not suspended. */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[8]; + __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been + issued, TWI traffic is now suspended. */ + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[2]; + __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */ + __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */ + __I uint32_t RESERVED7[39]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED10[14]; + __IO uint32_t ENABLE; /*!< Enable TWIM */ + __I uint32_t RESERVED11; + TWIM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[5]; + __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED13[3]; + TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */ + TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[13]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWIM_Type; + + +/* ================================================================================ */ +/* ================ TWIS ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS) + */ + +typedef struct { /*!< TWIS Structure */ + __I uint32_t RESERVED0[5]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED2[3]; + __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */ + __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */ + __I uint32_t RESERVED3[51]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __I uint32_t RESERVED4[7]; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED5[9]; + __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */ + __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_WRITE; /*!< Write command received */ + __IO uint32_t EVENTS_READ; /*!< Read command received */ + __I uint32_t RESERVED7[37]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED8[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED9[113]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t MATCH; /*!< Status register indicating which address had a match */ + __I uint32_t RESERVED10[10]; + __IO uint32_t ENABLE; /*!< Enable TWIS */ + __I uint32_t RESERVED11; + TWIS_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED12[9]; + TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */ + __I uint32_t RESERVED13; + TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */ + __I uint32_t RESERVED14[14]; + __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */ + __I uint32_t RESERVED15; + __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */ + __I uint32_t RESERVED16[10]; + __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read + of the transmit buffer. */ +} NRF_TWIS_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI) + */ + +typedef struct { /*!< SPI Structure */ + __I uint32_t RESERVED0[66]; + __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */ + __I uint32_t RESERVED1[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable SPI */ + __I uint32_t RESERVED3; + SPI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED4; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED5; + __IO uint32_t FREQUENCY; /*!< SPI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED6[11]; + __IO uint32_t CONFIG; /*!< Configuration register */ +} NRF_SPI_Type; + + +/* ================================================================================ */ +/* ================ TWI ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI) + */ + +typedef struct { /*!< TWI Structure */ + __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */ + __I uint32_t RESERVED1[2]; + __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */ + __I uint32_t RESERVED2; + __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */ + __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */ + __I uint32_t RESERVED3[56]; + __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */ + __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */ + __I uint32_t RESERVED4[4]; + __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */ + __I uint32_t RESERVED5; + __IO uint32_t EVENTS_ERROR; /*!< TWI error */ + __I uint32_t RESERVED6[4]; + __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or + received */ + __I uint32_t RESERVED7[3]; + __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */ + __I uint32_t RESERVED8[45]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED9[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED10[110]; + __IO uint32_t ERRORSRC; /*!< Error source */ + __I uint32_t RESERVED11[14]; + __IO uint32_t ENABLE; /*!< Enable TWI */ + __I uint32_t RESERVED12; + TWI_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED13[2]; + __I uint32_t RXD; /*!< RXD register */ + __IO uint32_t TXD; /*!< TXD register */ + __I uint32_t RESERVED14; + __IO uint32_t FREQUENCY; /*!< TWI frequency. Accuracy depends on the HFCLK source selected. */ + __I uint32_t RESERVED15[24]; + __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */ +} NRF_TWI_Type; + + +/* ================================================================================ */ +/* ================ NFCT ================ */ +/* ================================================================================ */ /** * @brief NFC-A compatible radio (NFCT) */ -typedef struct { /*!< (@ 0x40005000) NFCT Structure */ - __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing - frames, change state to activated */ - __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ - __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to - sense mode */ - __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change - state to transmit */ - __IM uint32_t RESERVED[3]; - __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ - __IM uint32_t RESERVED1; - __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ - __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ - __IM uint32_t RESERVED2[53]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send - frames */ - __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ - __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ - __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted - frame */ - __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air - symbol of a frame */ - __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received - frame */ - __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) - and transferred to RAM, and EasyDMA has - ended accessing the RX buffer */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register - contains details on the source of the error. */ - __IM uint32_t RESERVED3[2]; - __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX - register contains details on the source - of the error. */ - __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) - in Data RAM full. */ - __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA - has ended accessing the TX buffer */ - __IM uint32_t RESERVED4; - __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ - __IM uint32_t RESERVED5[3]; - __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ - __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ - __IM uint32_t RESERVED6[43]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED7[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED8[62]; - __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ - __IM uint32_t RESERVED9; - __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ - __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ - __IM uint32_t RESERVED10[3]; - __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ - __IM uint32_t RESERVED11[6]; - __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ - __IM uint32_t RESERVED12[49]; - __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ - __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ - __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ - __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in - Data RAM */ - __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD - data storage each */ - __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ - __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ - __IM uint32_t RESERVED13[26]; - __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ - __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ - __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ - __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. - This setting must be done before the NFCT - peripheral is enabled. */ - __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ - __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ -} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ - - - -/* =========================================================================================================================== */ -/* ================ GPIOTE ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< NFCT Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate NFCT peripheral for incoming and outgoing frames, change + state to activated */ + __O uint32_t TASKS_DISABLE; /*!< Disable NFCT peripheral */ + __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */ + __O uint32_t TASKS_STARTTX; /*!< Start transmission of an outgoing frame, change state to transmit */ + __I uint32_t RESERVED0[3]; + __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */ + __I uint32_t RESERVED1; + __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */ + __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */ + __I uint32_t RESERVED2[53]; + __IO uint32_t EVENTS_READY; /*!< The NFCT peripheral is ready to receive and send frames */ + __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */ + __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */ + __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */ + __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */ + __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */ + __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data has been checked (CRC, parity) and transferred + to RAM, and EasyDMA has ended accessing the RX buffer */ + __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details + on the source of the error. */ + __I uint32_t RESERVED3[2]; + __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains + details on the source of the error. */ + __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ + __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended + accessing the TX buffer */ + __I uint32_t RESERVED4; + __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */ + __I uint32_t RESERVED5[3]; + __IO uint32_t EVENTS_COLLISION; /*!< NFC auto collision resolution error reported. */ + __IO uint32_t EVENTS_SELECTED; /*!< NFC auto collision resolution successfully completed */ + __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */ + __I uint32_t RESERVED6[43]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED7[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED8[62]; + __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */ + __I uint32_t RESERVED9; + NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */ + __I uint32_t NFCTAGSTATE; /*!< NfcTag state register */ + __I uint32_t RESERVED10[10]; + __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */ + __I uint32_t RESERVED11[49]; + __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */ + __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */ + __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */ + __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */ + __IO uint32_t MAXLEN; /*!< Size of the RAM buffer allocated to TXD and RXD data storage + each */ + NFCT_TXD_Type TXD; /*!< Unspecified */ + NFCT_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED12[26]; + __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */ + __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */ + __IO uint32_t AUTOCOLRESCONFIG; /*!< Controls the auto collision resolution function. This setting + must be done before the NFCT peripheral is enabled. */ + __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */ + __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; + + +/* ================================================================================ */ +/* ================ GPIOTE ================ */ +/* ================================================================================ */ /** * @brief GPIO Tasks and Events (GPIOTE) */ -typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ - __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin - specified in CONFIG[n].PSEL. Action on pin - is configured in CONFIG[n].POLARITY. */ - __IM uint32_t RESERVED[4]; - __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin - specified in CONFIG[n].PSEL. Action on pin - is to set it high. */ - __IM uint32_t RESERVED1[4]; - __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin - specified in CONFIG[n].PSEL. Action on pin - is to set it low. */ - __IM uint32_t RESERVED2[32]; - __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from - pin specified in CONFIG[n].PSEL */ - __IM uint32_t RESERVED3[23]; - __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins - with SENSE mechanism enabled */ - __IM uint32_t RESERVED4[97]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED5[129]; - __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], - SET[n] and CLR[n] tasks and IN[n] event */ -} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ - - - -/* =========================================================================================================================== */ -/* ================ SAADC ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) - */ - -typedef struct { /*!< (@ 0x40007000) SAADC Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer - in RAM */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ - __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ - __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending - on the configuration, multiple conversions - might be needed for a result to be transferred - to RAM. */ - __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ - __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ - __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ - __IM uint32_t RESERVED1[106]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[61]; - __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ - __IM uint32_t RESERVED4[3]; - __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ - __IM uint32_t RESERVED5[24]; - __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ - __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is - applied before averaging, thus for high - OVERSAMPLE a higher RESOLUTION should be - used. */ - __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ - __IM uint32_t RESERVED6[12]; - __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ -} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ - - - -/* =========================================================================================================================== */ -/* ================ TIMER0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Timer/Counter 0 (TIMER0) - */ - -typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ - __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ - __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ - __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ - __IM uint32_t RESERVED[11]; - __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to - CC[n] register */ - __IM uint32_t RESERVED1[58]; - __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] - match */ - __IM uint32_t RESERVED2[42]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED3[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[126]; - __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ - __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ - __IM uint32_t RESERVED5; - __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ - __IM uint32_t RESERVED6[11]; - __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register - n */ -} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ - - - -/* =========================================================================================================================== */ -/* ================ RTC0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Real time counter 0 (RTC0) - */ - -typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ - __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ - __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ - __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ - __IM uint32_t RESERVED1[14]; - __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] - match */ - __IM uint32_t RESERVED2[109]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[13]; - __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ - __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ - __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ - __IM uint32_t RESERVED4[110]; - __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ - __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Mu - t be written when RTC is stopped */ - __IM uint32_t RESERVED5[13]; - __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ -} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ - - - -/* =========================================================================================================================== */ -/* ================ TEMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< GPIOTE Structure */ + __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */ + __I uint32_t RESERVED0[4]; + __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it high. */ + __I uint32_t RESERVED1[4]; + __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified + in CONFIG[0].PSEL. Action on pin is to set it low. */ + __I uint32_t RESERVED2[32]; + __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified + in CONFIG[0].PSEL */ + __I uint32_t RESERVED3[23]; + __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism + enabled */ + __I uint32_t RESERVED4[97]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED5[129]; + __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n] + and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; + + +/* ================================================================================ */ +/* ================ SAADC ================ */ +/* ================================================================================ */ + + +/** + * @brief Analog to Digital Converter (SAADC) + */ + +typedef struct { /*!< SAADC Structure */ + __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */ + __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */ + __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */ + __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */ + __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */ + __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode, + multiple conversions might be needed for a result to be transferred + to RAM. */ + __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */ + __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */ + __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */ + SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED1[106]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t STATUS; /*!< Status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t ENABLE; /*!< Enable or disable ADC */ + __I uint32_t RESERVED4[3]; + SAADC_CH_Type CH[8]; /*!< Unspecified */ + __I uint32_t RESERVED5[24]; + __IO uint32_t RESOLUTION; /*!< Resolution configuration */ + __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined + with SCAN. The RESOLUTION is applied before averaging, thus + for high OVERSAMPLE a higher RESOLUTION should be used. */ + __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */ + __I uint32_t RESERVED6[12]; + SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */ +} NRF_SAADC_Type; + + +/* ================================================================================ */ +/* ================ TIMER ================ */ +/* ================================================================================ */ + + +/** + * @brief Timer/Counter 0 (TIMER) + */ + +typedef struct { /*!< TIMER Structure */ + __O uint32_t TASKS_START; /*!< Start Timer */ + __O uint32_t TASKS_STOP; /*!< Stop Timer */ + __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */ + __O uint32_t TASKS_CLEAR; /*!< Clear time */ + __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */ + __I uint32_t RESERVED0[11]; + __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */ + __I uint32_t RESERVED1[58]; + __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[42]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __I uint32_t STATUS; /*!< Timer status */ + __I uint32_t RESERVED5[64]; + __IO uint32_t MODE; /*!< Timer mode selection */ + __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */ + __I uint32_t RESERVED6; + __IO uint32_t PRESCALER; /*!< Timer prescaler register */ + __I uint32_t RESERVED7[11]; + __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */ +} NRF_TIMER_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real time counter 0 (RTC) + */ + +typedef struct { /*!< RTC Structure */ + __O uint32_t TASKS_START; /*!< Start RTC COUNTER */ + __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */ + __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */ + __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */ + __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */ + __I uint32_t RESERVED1[14]; + __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */ + __I uint32_t RESERVED2[109]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[13]; + __IO uint32_t EVTEN; /*!< Enable or disable event routing */ + __IO uint32_t EVTENSET; /*!< Enable event routing */ + __IO uint32_t EVTENCLR; /*!< Disable event routing */ + __I uint32_t RESERVED4[110]; + __I uint32_t COUNTER; /*!< Current COUNTER value */ + __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must + be written when RTC is stopped */ + __I uint32_t RESERVED5[13]; + __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */ +} NRF_RTC_Type; + + +/* ================================================================================ */ +/* ================ TEMP ================ */ +/* ================================================================================ */ /** * @brief Temperature Sensor (TEMP) */ -typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[127]; - __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */ - __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */ - __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */ - __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */ - __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */ - __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */ - __IM uint32_t RESERVED4[2]; - __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */ - __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */ - __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */ - __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */ - __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */ - __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */ - __IM uint32_t RESERVED5[2]; - __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */ - __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */ - __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */ - __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */ - __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */ -} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ - - - -/* =========================================================================================================================== */ -/* ================ RNG ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< TEMP Structure */ + __O uint32_t TASKS_START; /*!< Start temperature measurement */ + __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[127]; + __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */ + __I uint32_t RESERVED3[5]; + __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */ + __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */ + __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */ + __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */ + __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */ + __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */ + __I uint32_t RESERVED4[2]; + __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */ + __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */ + __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */ + __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */ + __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */ + __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */ + __I uint32_t RESERVED5[2]; + __IO uint32_t T0; /*!< End point of 1st piece wise linear function */ + __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */ + __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */ + __IO uint32_t T3; /*!< End point of 4th piece wise linear function */ + __IO uint32_t T4; /*!< End point of 5th piece wise linear function */ +} NRF_TEMP_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ /** * @brief Random Number Generator (RNG) */ -typedef struct { /*!< (@ 0x4000D000) RNG Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number - written to the VALUE register */ - __IM uint32_t RESERVED1[63]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[126]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ - __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ -} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ - +typedef struct { /*!< RNG Structure */ + __O uint32_t TASKS_START; /*!< Task starting the random number generator */ + __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to + the VALUE register */ + __I uint32_t RESERVED1[63]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[126]; + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t VALUE; /*!< Output random number */ +} NRF_RNG_Type; -/* =========================================================================================================================== */ -/* ================ ECB ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ ECB ================ */ +/* ================================================================================ */ /** * @brief AES ECB Mode Encryption (ECB) */ -typedef struct { /*!< (@ 0x4000E000) ECB Structure */ - __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ - __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ - __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB - task or due to an error */ - __IM uint32_t RESERVED1[127]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ -} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ +typedef struct { /*!< ECB Structure */ + __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */ + __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */ + __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to + an error */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[126]; + __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */ +} NRF_ECB_Type; - -/* =========================================================================================================================== */ -/* ================ AAR ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ CCM ================ */ +/* ================================================================================ */ /** - * @brief Accelerated Address Resolver (AAR) + * @brief AES CCM Mode Encryption (CCM) */ -typedef struct { /*!< (@ 0x4000F000) AAR Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified - in the IRK data structure */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ - __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ - __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ - __IM uint32_t RESERVED2[126]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ - __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ - __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ - __IM uint32_t RESERVED5; - __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ - __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ -} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ - - - -/* =========================================================================================================================== */ -/* ================ CCM ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< CCM Structure */ + __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by + itself when completed. */ + __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself + when completed. */ + __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */ + __O uint32_t TASKS_RATEOVERRIDE; /*!< Override DATARATE setting in MODE register with the contents + of the RATEOVERRIDE register for any ongoing encryption/decryption */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */ + __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */ + __IO uint32_t EVENTS_ERROR; /*!< Deprecated register - CCM error event */ + __I uint32_t RESERVED1[61]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t MICSTATUS; /*!< MIC check result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable */ + __IO uint32_t MODE; /*!< Operation mode */ + __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */ + __IO uint32_t INPTR; /*!< Input pointer */ + __IO uint32_t OUTPTR; /*!< Output pointer */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ + __IO uint32_t MAXPACKETSIZE; /*!< Length of key-stream generated when MODE.LENGTH = Extended. */ + __IO uint32_t RATEOVERRIDE; /*!< Data rate override setting. */ +} NRF_CCM_Type; + + +/* ================================================================================ */ +/* ================ AAR ================ */ +/* ================================================================================ */ /** - * @brief AES CCM Mode Encryption (CCM) + * @brief Accelerated Address Resolver (AAR) */ -typedef struct { /*!< (@ 0x4000F000) CCM Structure */ - __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation - will stop by itself when completed. */ - __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will - stop by itself when completed. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ - __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with - the contents of the RATEOVERRIDE register - for any ongoing encryption/decryption */ - __IM uint32_t RESERVED[60]; - __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */ - __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ - __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ - __IM uint32_t RESERVED1[61]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ - __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ - __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and - NONCE vector */ - __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ - __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ - __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ - __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH - = Extended. */ - __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ -} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ - - - -/* =========================================================================================================================== */ -/* ================ WDT ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< AAR Structure */ + __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK + data structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */ + __I uint32_t RESERVED1[61]; + __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */ + __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */ + __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */ + __I uint32_t RESERVED2[126]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t STATUS; /*!< Resolution status */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable AAR */ + __IO uint32_t NIRK; /*!< Number of IRKs */ + __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */ + __I uint32_t RESERVED5; + __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */ + __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */ +} NRF_AAR_Type; + + +/* ================================================================================ */ +/* ================ WDT ================ */ +/* ================================================================================ */ /** * @brief Watchdog Timer (WDT) */ -typedef struct { /*!< (@ 0x40010000) WDT Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ - __IM uint32_t RESERVED[63]; - __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ - __IM uint32_t RESERVED1[128]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[61]; - __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ - __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ - __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ - __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ - __IM uint32_t RESERVED4[60]; - __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ -} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ - +typedef struct { /*!< WDT Structure */ + __O uint32_t TASKS_START; /*!< Start the watchdog */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */ + __I uint32_t RESERVED1[128]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[61]; + __I uint32_t RUNSTATUS; /*!< Run status */ + __I uint32_t REQSTATUS; /*!< Request status */ + __I uint32_t RESERVED3[63]; + __IO uint32_t CRV; /*!< Counter reload value */ + __IO uint32_t RREN; /*!< Enable register for reload request registers */ + __IO uint32_t CONFIG; /*!< Configuration register */ + __I uint32_t RESERVED4[60]; + __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */ +} NRF_WDT_Type; -/* =========================================================================================================================== */ -/* ================ QDEC ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ QDEC ================ */ +/* ================================================================================ */ /** * @brief Quadrature Decoder (QDEC) */ -typedef struct { /*!< (@ 0x40012000) QDEC Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ - __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ - __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ - __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ - __IM uint32_t RESERVED[59]; - __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value - written to the SAMPLE register */ - __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ - __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ - __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ - __IM uint32_t RESERVED1[59]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ - __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ - __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ - __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ - __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY - and DBLRDY events can be generated */ - __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ - __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the - READCLRACC or RDCLRACC task */ - __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ - __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ - __IM uint32_t RESERVED4[5]; - __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ - __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected - double transitions */ - __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC - or RDCLRDBL task */ -} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ - - - -/* =========================================================================================================================== */ -/* ================ COMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< QDEC Structure */ + __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */ + __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */ + __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */ + __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */ + __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */ + __I uint32_t RESERVED0[59]; + __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to + the SAMPLE register */ + __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */ + __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */ + __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */ + __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */ + __I uint32_t RESERVED1[59]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */ + __IO uint32_t LEDPOL; /*!< LED output pin polarity */ + __IO uint32_t SAMPLEPER; /*!< Sample period */ + __I int32_t SAMPLE; /*!< Motion sample value */ + __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events + can be generated */ + __I int32_t ACC; /*!< Register accumulating the valid transitions */ + __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC + task */ + QDEC_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t DBFEN; /*!< Enable input debounce filters */ + __I uint32_t RESERVED4[5]; + __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */ + __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */ + __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL + task */ +} NRF_QDEC_Type; + + +/* ================================================================================ */ +/* ================ COMP ================ */ +/* ================================================================================ */ /** * @brief Comparator (COMP) */ -typedef struct { /*!< (@ 0x40013000) COMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ - __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ - __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ - __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED2[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ - __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ - __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ - __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ - __IM uint32_t RESERVED5[8]; - __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ - __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ - __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ -} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ - - - -/* =========================================================================================================================== */ -/* ================ LPCOMP ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< COMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< COMP enable */ + __IO uint32_t PSEL; /*!< Pin select */ + __IO uint32_t REFSEL; /*!< Reference source select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[8]; + __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */ + __IO uint32_t MODE; /*!< Mode configuration */ + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ + __IO uint32_t ISOURCE; /*!< Current source select on analog input */ +} NRF_COMP_Type; + + +/* ================================================================================ */ +/* ================ LPCOMP ================ */ +/* ================================================================================ */ /** * @brief Low Power Comparator (LPCOMP) */ -typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ - __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ - __IM uint32_t RESERVED[61]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ - __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ - __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ - __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED2[64]; - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[61]; - __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ - __IM uint32_t RESERVED4[63]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ - __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ - __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ - __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ - __IM uint32_t RESERVED5[4]; - __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ - __IM uint32_t RESERVED6[5]; - __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ -} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ - - - -/* =========================================================================================================================== */ -/* ================ EGU0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Event Generator Unit 0 (EGU0) - */ - -typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ - __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering - the corresponding TRIGGERED[n] event */ - __IM uint32_t RESERVED[48]; - __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated - by triggering the corresponding TRIGGER[n] - task */ - __IM uint32_t RESERVED1[112]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ -} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ +typedef struct { /*!< LPCOMP Structure */ + __O uint32_t TASKS_START; /*!< Start comparator */ + __O uint32_t TASKS_STOP; /*!< Stop comparator */ + __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */ + __I uint32_t RESERVED0[61]; + __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */ + __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */ + __IO uint32_t EVENTS_UP; /*!< Upward crossing */ + __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */ + __I uint32_t RESERVED1[60]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED2[64]; + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[61]; + __I uint32_t RESULT; /*!< Compare result */ + __I uint32_t RESERVED4[63]; + __IO uint32_t ENABLE; /*!< Enable LPCOMP */ + __IO uint32_t PSEL; /*!< Input pin select */ + __IO uint32_t REFSEL; /*!< Reference select */ + __IO uint32_t EXTREFSEL; /*!< External reference select */ + __I uint32_t RESERVED5[4]; + __IO uint32_t ANADETECT; /*!< Analog detect configuration */ + __I uint32_t RESERVED6[5]; + __IO uint32_t HYST; /*!< Comparator hysteresis enable */ +} NRF_LPCOMP_Type; + + +/* ================================================================================ */ +/* ================ SWI ================ */ +/* ================================================================================ */ + + +/** + * @brief Software interrupt 0 (SWI) + */ + +typedef struct { /*!< SWI Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_SWI_Type; + + +/* ================================================================================ */ +/* ================ EGU ================ */ +/* ================================================================================ */ + + +/** + * @brief Event Generator Unit 0 (EGU) + */ + +typedef struct { /*!< EGU Structure */ + __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding + TRIGGERED[0] event */ + __I uint32_t RESERVED0[48]; + __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering + the corresponding TRIGGER[0] task */ + __I uint32_t RESERVED1[112]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ +} NRF_EGU_Type; + + +/* ================================================================================ */ +/* ================ PWM ================ */ +/* ================================================================================ */ + + +/** + * @brief Pulse Width Modulation Unit 0 (PWM) + */ + +typedef struct { /*!< PWM Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current + PWM period, and stops sequence playback */ + __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all + enabled channels from sequence 0, and starts playing that sequence + at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes + PWM generation to start it was not running. */ + __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels + if DECODER.MODE=NextStep. Does not cause PWM generation to start + it was not running. */ + __I uint32_t RESERVED1[60]; + __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer + generated */ + __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence + 0 */ + __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence + 0, when last value from RAM has been applied to wave counter */ + __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */ + __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times + defined in LOOP.CNT */ + __I uint32_t RESERVED2[56]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[125]; + __IO uint32_t ENABLE; /*!< PWM module enable register */ + __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */ + __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */ + __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */ + __IO uint32_t DECODER; /*!< Configuration of the decoder */ + __IO uint32_t LOOP; /*!< Amount of playback of a loop */ + __I uint32_t RESERVED5[2]; + PWM_SEQ_Type SEQ[2]; /*!< Unspecified */ + PWM_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_PWM_Type; + - - -/* =========================================================================================================================== */ -/* ================ SWI0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Software interrupt 0 (SWI0) - */ - -typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ - __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ -} NRF_SWI_Type; /*!< Size = 4 (0x4) */ - - - -/* =========================================================================================================================== */ -/* ================ PWM0 ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Pulse width modulation unit 0 (PWM0) - */ - -typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at - the end of current PWM period, and stops - sequence playback */ - __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value - on all enabled channels from sequence n, - and starts playing that sequence at the - rate defined in SEQ[n]REFRESH and/or DECODER.MODE. - Causes PWM generation to start if not running. */ - __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on - all enabled channels if DECODER.MODE=NextStep. - Does not cause PWM generation to start if - not running. */ - __IM uint32_t RESERVED1[60]; - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses - are no longer generated */ - __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started - on sequence n */ - __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every - sequence n, when last value from RAM has - been applied to wave counter */ - __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ - __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount - of times defined in LOOP.CNT */ - __IM uint32_t RESERVED2[56]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ - __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ - __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter - counts */ - __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ - __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ - __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ - __IM uint32_t RESERVED5[2]; - __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ - __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ -} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ - - - -/* =========================================================================================================================== */ -/* ================ PDM ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ PDM ================ */ +/* ================================================================================ */ /** * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) */ -typedef struct { /*!< (@ 0x4001D000) PDM Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ - __IM uint32_t RESERVED[62]; - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ - __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified - by SAMPLE.MAXCNT (or the last sample after - a STOP task has been received) to Data RAM */ - __IM uint32_t RESERVED1[125]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ - __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ - __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' - signals */ - __IM uint32_t RESERVED3[3]; - __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ - __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ - __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output - sample rate. Change PDMCLKCTRL accordingly. */ - __IM uint32_t RESERVED4[7]; - __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ - __IM uint32_t RESERVED5[6]; - __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ -} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ - - - -/* =========================================================================================================================== */ -/* ================ ACL ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< PDM Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */ + __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */ + __I uint32_t RESERVED0[62]; + __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */ + __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */ + __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT + (or the last sample after a STOP task has been received) to + Data RAM */ + __I uint32_t RESERVED1[125]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< PDM module enable register */ + __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */ + __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */ + __I uint32_t RESERVED3[3]; + __IO uint32_t GAINL; /*!< Left output gain adjustment */ + __IO uint32_t GAINR; /*!< Right output gain adjustment */ + __IO uint32_t RATIO; /*!< Selects the ratio between PDM_CLK and output sample rate. Change + PDMCLKCTRL accordingly. */ + __I uint32_t RESERVED4[7]; + PDM_PSEL_Type PSEL; /*!< Unspecified */ + __I uint32_t RESERVED5[6]; + PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */ +} NRF_PDM_Type; + + +/* ================================================================================ */ +/* ================ NVMC ================ */ +/* ================================================================================ */ /** - * @brief Access control lists (ACL) + * @brief Non Volatile Memory Controller (NVMC) */ -typedef struct { /*!< (@ 0x4001E000) ACL Structure */ - __IM uint32_t RESERVED[512]; - __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ -} NRF_ACL_Type; /*!< Size = 2176 (0x880) */ - +typedef struct { /*!< NVMC Structure */ + __I uint32_t RESERVED0[256]; + __I uint32_t READY; /*!< Ready flag */ + __I uint32_t RESERVED1[64]; + __IO uint32_t CONFIG; /*!< Configuration register */ + + union { + __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */ + }; + __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */ + __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area. + Equivalent to ERASEPAGE. */ + __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */ + __I uint32_t RESERVED2[10]; + __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */ + __I uint32_t RESERVED3; + __IO uint32_t IHIT; /*!< I-Code cache hit counter. */ + __IO uint32_t IMISS; /*!< I-Code cache miss counter. */ +} NRF_NVMC_Type; -/* =========================================================================================================================== */ -/* ================ NVMC ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ ACL ================ */ +/* ================================================================================ */ /** - * @brief Non Volatile Memory Controller (NVMC) + * @brief Access control lists (ACL) */ -typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ - __IM uint32_t RESERVED[256]; - __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ - __IM uint32_t RESERVED1; - __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ - __IM uint32_t RESERVED2[62]; - __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ - - union { - __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ - __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a - page in code area. Equivalent to ERASEPAGE. */ - }; - __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ - __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a - page in code area. Equivalent to ERASEPAGE. */ - __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration - registers */ - __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code - area */ - __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ - __IM uint32_t RESERVED3[8]; - __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register. */ - __IM uint32_t RESERVED4; - __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter. */ - __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter. */ -} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ +typedef struct { /*!< ACL Structure */ + __I uint32_t RESERVED0[449]; + __IO uint32_t DISABLEINDEBUG; /*!< Disable all ACL protection mechanisms for regions while in debug + mode */ + __I uint32_t RESERVED1[62]; + ACL_ACL_Type ACL[8]; /*!< Unspecified */ +} NRF_ACL_Type; - -/* =========================================================================================================================== */ -/* ================ PPI ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ PPI ================ */ +/* ================================================================================ */ /** * @brief Programmable Peripheral Interconnect (PPI) */ -typedef struct { /*!< (@ 0x4001F000) PPI Structure */ - __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ - __IM uint32_t RESERVED[308]; - __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ - __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ - __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ - __IM uint32_t RESERVED1; - __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ - __IM uint32_t RESERVED2[148]; - __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ - __IM uint32_t RESERVED3[62]; - __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ -} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ - +typedef struct { /*!< PPI Structure */ + PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */ + __I uint32_t RESERVED0[308]; + __IO uint32_t CHEN; /*!< Channel enable register */ + __IO uint32_t CHENSET; /*!< Channel enable set register */ + __IO uint32_t CHENCLR; /*!< Channel enable clear register */ + __I uint32_t RESERVED1; + PPI_CH_Type CH[20]; /*!< PPI Channel */ + __I uint32_t RESERVED2[148]; + __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */ + __I uint32_t RESERVED3[62]; + PPI_FORK_Type FORK[32]; /*!< Fork */ +} NRF_PPI_Type; -/* =========================================================================================================================== */ -/* ================ MWU ================ */ -/* =========================================================================================================================== */ +/* ================================================================================ */ +/* ================ MWU ================ */ +/* ================================================================================ */ /** * @brief Memory Watch Unit (MWU) */ -typedef struct { /*!< (@ 0x40020000) MWU Structure */ - __IM uint32_t RESERVED[64]; - __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ - __IM uint32_t RESERVED1[16]; - __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ - __IM uint32_t RESERVED2[100]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[5]; - __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ - __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ - __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ - __IM uint32_t RESERVED4[53]; - __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ - __IM uint32_t RESERVED5[64]; - __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ - __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ - __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ - __IM uint32_t RESERVED6[57]; - __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ - __IM uint32_t RESERVED7[32]; - __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ -} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ - - - -/* =========================================================================================================================== */ -/* ================ I2S ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< MWU Structure */ + __I uint32_t RESERVED0[64]; + MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED1[16]; + MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED2[100]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[5]; + __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */ + __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */ + __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */ + __I uint32_t RESERVED4[53]; + MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */ + __I uint32_t RESERVED5[64]; + __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */ + __IO uint32_t REGIONENSET; /*!< Enable regions watch */ + __IO uint32_t REGIONENCLR; /*!< Disable regions watch */ + __I uint32_t RESERVED6[57]; + MWU_REGION_Type REGION[4]; /*!< Unspecified */ + __I uint32_t RESERVED7[32]; + MWU_PREGION_Type PREGION[2]; /*!< Unspecified */ +} NRF_MWU_Type; + + +/* ================================================================================ */ +/* ================ I2S ================ */ +/* ================================================================================ */ /** * @brief Inter-IC Sound (I2S) */ -typedef struct { /*!< (@ 0x40025000) I2S Structure */ - __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK - generator when this is enabled. */ - __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. - Triggering this task will cause the STOPPED - event to be generated. */ - __IM uint32_t RESERVED[63]; - __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal - double-buffers. When the I2S module is started - and RX is enabled, this event will be generated - for every RXTXD.MAXCNT words that are received - on the SDIN pin. */ - __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ - __IM uint32_t RESERVED1[2]; - __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal - double-buffers. When the I2S module is started - and TX is enabled, this event will be generated - for every RXTXD.MAXCNT words that are sent - on the SDOUT pin. */ - __IM uint32_t RESERVED2[122]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED3[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ - __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ - __IM uint32_t RESERVED4[3]; - __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ - __IM uint32_t RESERVED5; - __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ - __IM uint32_t RESERVED6[3]; - __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ - __IM uint32_t RESERVED7[3]; - __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ -} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ - - - -/* =========================================================================================================================== */ -/* ================ FPU ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< I2S Structure */ + __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when + this is enabled. */ + __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this + task will cause the {event:STOPPED} event to be generated. */ + __I uint32_t RESERVED0[63]; + __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers. + When the I2S module is started and RX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */ + __I uint32_t RESERVED1[2]; + __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers. + When the I2S module is started and TX is enabled, this event + will be generated for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __I uint32_t RESERVED2[122]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED3[125]; + __IO uint32_t ENABLE; /*!< Enable I2S module. */ + I2S_CONFIG_Type CONFIG; /*!< Unspecified */ + __I uint32_t RESERVED4[3]; + I2S_RXD_Type RXD; /*!< Unspecified */ + __I uint32_t RESERVED5; + I2S_TXD_Type TXD; /*!< Unspecified */ + __I uint32_t RESERVED6[3]; + I2S_RXTXD_Type RXTXD; /*!< Unspecified */ + __I uint32_t RESERVED7[3]; + I2S_PSEL_Type PSEL; /*!< Unspecified */ +} NRF_I2S_Type; + + +/* ================================================================================ */ +/* ================ FPU ================ */ +/* ================================================================================ */ /** * @brief FPU (FPU) */ -typedef struct { /*!< (@ 0x40026000) FPU Structure */ - __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ -} NRF_FPU_Type; /*!< Size = 4 (0x4) */ - - - -/* =========================================================================================================================== */ -/* ================ USBD ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief Universal serial bus device (USBD) - */ - -typedef struct { /*!< (@ 0x40027000) USBD Structure */ - __IM uint32_t RESERVED; - __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR - and EPIN[n].MAXCNT registers values, and - enables endpoint IN n to respond to traffic - from host */ - __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers - values, and enables sending data on ISO - endpoint */ - __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR - and EPOUT[n].MAXCNT registers values, and - enables endpoint n to respond to traffic - from host */ - __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers - values, and enables receiving of data on - ISO endpoint */ - __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ - __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ - __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint - 0 */ - __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined - in the DPDMVALUE register */ - __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state - (USB engine takes control) */ - __IM uint32_t RESERVED1[40]; - __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected - on USB lines */ - __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, - or EPOUT[n].PTR and EPOUT[n].MAXCNT registers - have been captured on all endpoints reported - in the EPSTATUS register */ - __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer - has been consumed. The RAM buffer can be - accessed safely by software. */ - __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place - on the control endpoint */ - __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The - RAM buffer can be accessed safely by software. */ - __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer - has been consumed. The RAM buffer can be - accessed safely by software. */ - __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The - RAM buffer can be accessed safely by software. */ - __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition - has been detected on USB lines */ - __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific - events has occurred. Check EVENTCAUSE register - to find the cause. */ - __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) - on the control endpoint */ - __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, - indicated by the EPDATASTATUS register */ - __IM uint32_t RESERVED2[39]; - __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ - __IM uint32_t RESERVED3[63]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED4[61]; - __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ - __IM uint32_t RESERVED5[7]; - __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ - __IM uint32_t RESERVED6; - __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA - registers have been captured */ - __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an - acknowledged data transfer has occurred - (EPDATA event) */ - __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ - __IM uint32_t RESERVED7[3]; - __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ - __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ - __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ - __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ - __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ - __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ - __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ - __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ - __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ - __IM uint32_t RESERVED8[15]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ - __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ - __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by - the DPDMDRIVE task. The DPDMNODRIVE task - reverts the control of the lines to MAC - IP (no forcing). */ - __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ - __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ - __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ - __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ - __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ - __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame - counter */ - __IM uint32_t RESERVED9[2]; - __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during - USB suspend */ - __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint - to an IN token when no data is ready to - be sent */ - __IM uint32_t RESERVED10[51]; - __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ - __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ - __IM uint32_t RESERVED11[21]; - __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ - __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ -} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ - - - -/* =========================================================================================================================== */ -/* ================ QSPI ================ */ -/* =========================================================================================================================== */ +typedef struct { /*!< FPU Structure */ + __I uint32_t UNUSED; /*!< Unused. */ +} NRF_FPU_Type; + + +/* ================================================================================ */ +/* ================ USBD ================ */ +/* ================================================================================ */ + + +/** + * @brief Universal Serial Bus device (USBD) + */ + +typedef struct { /*!< USBD Structure */ + __I uint32_t RESERVED0; + __O uint32_t TASKS_STARTEPIN[8]; /*!< Description collection[0]: Captures the EPIN[0].PTR, EPIN[0].MAXCNT + and EPIN[0].CONFIG registers values, and enables endpoint IN + 0 to respond to traffic from host */ + __O uint32_t TASKS_STARTISOIN; /*!< Captures the ISOIN.PTR, ISOIN.MAXCNT and ISOIN.CONFIG registers + values, and enables sending data on iso endpoint */ + __O uint32_t TASKS_STARTEPOUT[8]; /*!< Description collection[0]: Captures the EPOUT[0].PTR, EPOUT[0].MAXCNT + and EPOUT[0].CONFIG registers values, and enables endpoint 0 + to respond to traffic from host */ + __O uint32_t TASKS_STARTISOOUT; /*!< Captures the ISOOUT.PTR, ISOOUT.MAXCNT and ISOOUT.CONFIG registers + values, and enables receiving of data on iso endpoint */ + __O uint32_t TASKS_EP0RCVOUT; /*!< Allows OUT data stage on control endpoint 0 */ + __O uint32_t TASKS_EP0STATUS; /*!< Allows status stage on control endpoint 0 */ + __O uint32_t TASKS_EP0STALL; /*!< STALLs data and status stage on control endpoint 0 */ + __O uint32_t TASKS_DPDMDRIVE; /*!< Forces D+ and D-lines to the state defined in the DPDMVALUE + register */ + __O uint32_t TASKS_DPDMNODRIVE; /*!< Stops forcing D+ and D- lines to any state (USB engine takes + control) */ + __I uint32_t RESERVED1[40]; + __IO uint32_t EVENTS_USBRESET; /*!< Signals that a USB reset condition has been detected on the + USB lines */ + __IO uint32_t EVENTS_STARTED; /*!< Confirms that the EPIN[n].PTR, EPIN[n].MAXCNT, EPIN[n].CONFIG, + or EPOUT[n].PTR, EPOUT[n].MAXCNT and EPOUT[n].CONFIG registers + have been captured on all endpoints reported in the EPSTATUS + register */ + __IO uint32_t EVENTS_ENDEPIN[8]; /*!< Description collection[0]: The whole EPIN[0] buffer has been + consumed. The RAM buffer can be accessed safely by software. */ + __IO uint32_t EVENTS_EP0DATADONE; /*!< An acknowledged data transfer has taken place on the control + endpoint */ + __IO uint32_t EVENTS_ENDISOIN; /*!< The whole ISOIN buffer has been consumed. The RAM buffer can + be accessed safely by software. */ + __IO uint32_t EVENTS_ENDEPOUT[8]; /*!< Description collection[0]: The whole EPOUT[0] buffer has been + consumed. The RAM buffer can be accessed safely by software. */ + __IO uint32_t EVENTS_ENDISOOUT; /*!< The whole ISOOUT buffer has been consumed. The RAM buffer can + be accessed safely by software. */ + __IO uint32_t EVENTS_SOF; /*!< Signals that a SOF (start of frame) condition has been detected + on the USB lines */ + __IO uint32_t EVENTS_USBEVENT; /*!< An event or an error not covered by specific events has occurred, + check EVENTCAUSE register to find the cause */ + __IO uint32_t EVENTS_EP0SETUP; /*!< A valid SETUP token has been received (and acknowledged) on + the control endpoint */ + __IO uint32_t EVENTS_EPDATA; /*!< A data transfer has occurred on a data endpoint, indicated by + the EPDATASTATUS register */ + __IO uint32_t EVENTS_ACCESSFAULT; /*!< Access to an unavailable USB register has been attempted (software + or EasyDMA). This event can get fired even when USBD is not + ENABLEd. */ + __I uint32_t RESERVED2[38]; + __IO uint32_t SHORTS; /*!< Shortcut register */ + __I uint32_t RESERVED3[63]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED4[61]; + __IO uint32_t EVENTCAUSE; /*!< Details on event that caused the USBEVENT event */ + __I uint32_t BUSSTATE; /*!< Provides the logic state of the D+ and D- lines */ + __I uint32_t RESERVED5[6]; + USBD_HALTED_Type HALTED; /*!< Unspecified */ + __I uint32_t RESERVED6; + __IO uint32_t EPSTATUS; /*!< Provides information on which endpoint's EasyDMA registers have + been captured */ + __IO uint32_t EPDATASTATUS; /*!< Provides information on which endpoint(s) an acknowledged data + transfer has occurred (EPDATA event) */ + __I uint32_t USBADDR; /*!< Device USB address */ + __I uint32_t RESERVED7[3]; + __I uint32_t BMREQUESTTYPE; /*!< SETUP data, byte 0, bmRequestType */ + __I uint32_t BREQUEST; /*!< SETUP data, byte 1, bRequest */ + __I uint32_t WVALUEL; /*!< SETUP data, byte 2, LSB of wValue */ + __I uint32_t WVALUEH; /*!< SETUP data, byte 3, MSB of wValue */ + __I uint32_t WINDEXL; /*!< SETUP data, byte 4, LSB of wIndex */ + __I uint32_t WINDEXH; /*!< SETUP data, byte 5, MSB of wIndex */ + __I uint32_t WLENGTHL; /*!< SETUP data, byte 6, LSB of wLength */ + __I uint32_t WLENGTHH; /*!< SETUP data, byte 7, MSB of wLength */ + USBD_SIZE_Type SIZE; /*!< Unspecified */ + __I uint32_t RESERVED8[15]; + __IO uint32_t ENABLE; /*!< Enable USB */ + __IO uint32_t USBPULLUP; /*!< Control of the USB pull-up */ + __IO uint32_t DPDMVALUE; /*!< State at which the DPDMDRIVE task will force D+ and D-. The + DPDMNODRIVE task reverts the control of the lines to MAC IP + (no forcing). */ + __IO uint32_t DTOGGLE; /*!< Data toggle control and status. */ + __IO uint32_t EPINEN; /*!< Endpoint IN enable */ + __IO uint32_t EPOUTEN; /*!< Endpoint OUT enable */ + __O uint32_t EPSTALL; /*!< STALL endpoints */ + __IO uint32_t ISOSPLIT; /*!< Controls the split of ISO buffers */ + __I uint32_t FRAMECNTR; /*!< Returns the current value of the start of frame counter */ + __I uint32_t RESERVED9[3]; + __IO uint32_t ISOINCONFIG; /*!< Controls the response of the ISO IN endpoint to an IN token + when no data is ready to be sent */ + __I uint32_t RESERVED10[51]; + USBD_EPIN_Type EPIN[8]; /*!< Unspecified */ + USBD_ISOIN_Type ISOIN; /*!< Unspecified */ + __I uint32_t RESERVED11[21]; + USBD_EPOUT_Type EPOUT[8]; /*!< Unspecified */ + USBD_ISOOUT_Type ISOOUT; /*!< Unspecified */ +} NRF_USBD_Type; + + +/* ================================================================================ */ +/* ================ QSPI ================ */ +/* ================================================================================ */ /** * @brief External flash interface (QSPI) */ -typedef struct { /*!< (@ 0x40029000) QSPI Structure */ - __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ - __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to - internal RAM */ - __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external - flash memory */ - __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ - __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ - __IM uint32_t RESERVED[59]; - __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be - generated as a response to any QSPI task. */ - __IM uint32_t RESERVED1[127]; - __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ - __IM uint32_t RESERVED2[125]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected - in PSELn registers */ - __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ - __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ - __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ - __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ - __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute - in Place operation. */ - __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ - __IM uint32_t RESERVED3[46]; - __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ - __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ - __IM uint32_t RESERVED4[3]; - __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep - power-down mode (DPM). */ - __IM uint32_t RESERVED5[3]; - __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ - __IM uint32_t RESERVED6[3]; - __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ - __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ - __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ - __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ -} NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ - - - -/* =========================================================================================================================== */ -/* ================ CC_HOST_RGF ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) - */ - -typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ - __IM uint32_t RESERVED[1678]; - __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ - __IM uint32_t RESERVED1[4]; - __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. - When this register is set, K_PRTL can not - be used and a zeroed key will be used instead. - The value of this register is saved in the - CRYPTOCELL AO power domain. */ - __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value - of this register is saved in the CRYPTOCELL - AO power domain. Reading from this address - returns the K_DR valid status indicating - if K_DR is successfully retained. */ - __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value - of this register is saved in the CRYPTOCELL - AO power domain. */ - __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value - of this register is saved in the CRYPTOCELL - AO power domain. */ - __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The - value of this register is saved in the CRYPTOCELL - AO power domain. */ - __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL - subsystem */ -} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ - - - -/* =========================================================================================================================== */ -/* ================ CRYPTOCELL ================ */ -/* =========================================================================================================================== */ - - -/** - * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) - */ - -typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ - __IM uint32_t RESERVED[320]; - __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ -} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ - - -/** @} */ /* End of group Device_Peripheral_peripherals */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_peripheralAddr - * @{ - */ - -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_POWER_BASE 0x40000000UL -#define NRF_P0_BASE 0x50000000UL -#define NRF_P1_BASE 0x50000300UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_UARTE0_BASE 0x40002000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_SPIM0_BASE 0x40003000UL -#define NRF_SPIS0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_TWIM0_BASE 0x40003000UL -#define NRF_TWIS0_BASE 0x40003000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_SPIM1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_TWIM1_BASE 0x40004000UL -#define NRF_TWIS1_BASE 0x40004000UL -#define NRF_NFCT_BASE 0x40005000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_SAADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_COMP_BASE 0x40013000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_EGU0_BASE 0x40014000UL -#define NRF_SWI0_BASE 0x40014000UL -#define NRF_EGU1_BASE 0x40015000UL -#define NRF_SWI1_BASE 0x40015000UL -#define NRF_EGU2_BASE 0x40016000UL -#define NRF_SWI2_BASE 0x40016000UL -#define NRF_EGU3_BASE 0x40017000UL -#define NRF_SWI3_BASE 0x40017000UL -#define NRF_EGU4_BASE 0x40018000UL -#define NRF_SWI4_BASE 0x40018000UL -#define NRF_EGU5_BASE 0x40019000UL -#define NRF_SWI5_BASE 0x40019000UL -#define NRF_TIMER3_BASE 0x4001A000UL -#define NRF_TIMER4_BASE 0x4001B000UL -#define NRF_PWM0_BASE 0x4001C000UL -#define NRF_PDM_BASE 0x4001D000UL -#define NRF_ACL_BASE 0x4001E000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_MWU_BASE 0x40020000UL -#define NRF_PWM1_BASE 0x40021000UL -#define NRF_PWM2_BASE 0x40022000UL -#define NRF_SPI2_BASE 0x40023000UL -#define NRF_SPIM2_BASE 0x40023000UL -#define NRF_SPIS2_BASE 0x40023000UL -#define NRF_RTC2_BASE 0x40024000UL -#define NRF_I2S_BASE 0x40025000UL -#define NRF_FPU_BASE 0x40026000UL -#define NRF_USBD_BASE 0x40027000UL -#define NRF_UARTE1_BASE 0x40028000UL -#define NRF_QSPI_BASE 0x40029000UL -#define NRF_CC_HOST_RGF_BASE 0x5002A000UL -#define NRF_CRYPTOCELL_BASE 0x5002A000UL -#define NRF_PWM3_BASE 0x4002D000UL -#define NRF_SPIM3_BASE 0x4002F000UL - -/** @} */ /* End of group Device_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup Device_Peripheral_declaration - * @{ - */ - -#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) -#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) -#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) -#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) -#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) -#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) -#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) -#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) -#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) -#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) -#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) -#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) -#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) -#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) -#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) -#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) -#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) -#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) -#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) -#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) -#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) -#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) -#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) -#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) -#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) -#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) -#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) -#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) -#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) -#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) -#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) -#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) -#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) -#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) -#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) -#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) -#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) -#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) -#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) -#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) -#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) -#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) -#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) -#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) -#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) -#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) -#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) -#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) -#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) -#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) -#define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) -#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) -#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) -#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) -#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) - -/** @} */ /* End of group Device_Peripheral_declaration */ - - -/* ========================================= End of section using anonymous unions ========================================= */ -#if defined (__CC_ARM) +typedef struct { /*!< QSPI Structure */ + __O uint32_t TASKS_ACTIVATE; /*!< Activate QSPI interface */ + __O uint32_t TASKS_READSTART; /*!< Start transfer from external flash memory to internal RAM */ + __O uint32_t TASKS_WRITESTART; /*!< Start transfer from internal RAM to external flash memory */ + __O uint32_t TASKS_ERASESTART; /*!< Start external flash memory erase operation */ + __I uint32_t RESERVED0[60]; + __IO uint32_t EVENTS_READY; /*!< QSPI peripheral is ready. This event will be generated as a + response to any QSPI task. */ + __I uint32_t RESERVED1[127]; + __IO uint32_t INTEN; /*!< Enable or disable interrupt */ + __IO uint32_t INTENSET; /*!< Enable interrupt */ + __IO uint32_t INTENCLR; /*!< Disable interrupt */ + __I uint32_t RESERVED2[125]; + __IO uint32_t ENABLE; /*!< Enable QSPI peripheral and acquire the pins selected in PSELn + registers */ + QSPI_READ_Type READ; /*!< Unspecified */ + QSPI_WRITE_Type WRITE; /*!< Unspecified */ + QSPI_ERASE_Type ERASE; /*!< Unspecified */ + QSPI_PSEL_Type PSEL; /*!< Unspecified */ + __IO uint32_t XIPOFFSET; /*!< Address offset into the external memory for Execute in Place + operation. */ + __IO uint32_t IFCONFIG0; /*!< Interface configuration. */ + __I uint32_t RESERVED3[46]; + __IO uint32_t IFCONFIG1; /*!< Interface configuration. */ + __I uint32_t STATUS; /*!< Status register. */ + __I uint32_t RESERVED4[3]; + __IO uint32_t DPMDUR; /*!< Set the duration required to enter/exit deep power-down mode + (DPM). */ + __I uint32_t RESERVED5[3]; + __IO uint32_t ADDRCONF; /*!< Extended address configuration. */ + __I uint32_t RESERVED6[3]; + __IO uint32_t CINSTRCONF; /*!< Custom instruction configuration register. */ + __IO uint32_t CINSTRDAT0; /*!< Custom instruction data register 0. */ + __IO uint32_t CINSTRDAT1; /*!< Custom instruction data register 1. */ + __IO uint32_t IFTIMING; /*!< SPI interface timing. */ +} NRF_QSPI_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Port 1 (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t RESERVED0[321]; + __IO uint32_t OUT; /*!< Write GPIO port */ + __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */ + __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */ + __I uint32_t IN; /*!< Read GPIO port */ + __IO uint32_t DIR; /*!< Direction of GPIO pins */ + __IO uint32_t DIRSET; /*!< DIR set register */ + __IO uint32_t DIRCLR; /*!< DIR clear register */ + __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria + set in the PIN_CNF[n].SENSE registers */ + __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */ + __I uint32_t RESERVED1[118]; + __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */ +} NRF_GPIO_Type; + + +/* ================================================================================ */ +/* ================ CRYPTOCELL ================ */ +/* ================================================================================ */ + + +/** + * @brief ARM CryptoCell register interface (CRYPTOCELL) + */ + +typedef struct { /*!< CRYPTOCELL Structure */ + __I uint32_t RESERVED0[320]; + __IO uint32_t ENABLE; /*!< Control power and clock for ARM CryptoCell subsystem */ +} NRF_CRYPTOCELL_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) #pragma pop -#elif defined (__ICCARM__) +#elif defined(__ICCARM__) /* leave anonymous unions enabled */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) +#elif defined(__GNUC__) /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) +#elif defined(__TMS470__) /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) +#elif defined(__TASKING__) #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type #endif + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_USBD_BASE 0x40027000UL +#define NRF_UARTE1_BASE 0x40028000UL +#define NRF_QSPI_BASE 0x40029000UL +#define NRF_SPIM3_BASE 0x4002B000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL +#define NRF_CRYPTOCELL_BASE 0x5002A000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) +#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) +#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE) +#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE) +#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) +#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) +#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) +#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) +#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE) +#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE) +#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE) +#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE) +#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE) +#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE) +#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE) +#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE) +#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE) +#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE) +#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE) +#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE) +#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) +#define NRF_ACL ((NRF_ACL_Type *) NRF_ACL_BASE) +#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE) +#define NRF_USBD ((NRF_USBD_Type *) NRF_USBD_BASE) +#define NRF_UARTE1 ((NRF_UARTE_Type *) NRF_UARTE1_BASE) +#define NRF_QSPI ((NRF_QSPI_Type *) NRF_QSPI_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type *) NRF_SPIM3_BASE) +#define NRF_PWM3 ((NRF_PWM_Type *) NRF_PWM3_BASE) +#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type *) NRF_P1_BASE) +#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type *) NRF_CRYPTOCELL_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group nrf52840 */ +/** @} */ /* End of group Nordic Semiconductor */ + #ifdef __cplusplus } #endif -#endif /* NRF52840_H */ +#endif /* nrf52840_H */ -/** @} */ /* End of group nrf52840 */ - -/** @} */ /* End of group Nordic Semiconductor */ diff --git a/cores/nRF5/SDK/components/device/nrf52840_bitfields.h b/cores/nRF5/SDK/components/device/nrf52840_bitfields.h index 5252f4c3..d3f0bbdc 100644 --- a/cores/nRF5/SDK/components/device/nrf52840_bitfields.h +++ b/cores/nRF5/SDK/components/device/nrf52840_bitfields.h @@ -1,35 +1,33 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef __NRF52840_BITS_H #define __NRF52840_BITS_H @@ -38,67 +36,24 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: AAR */ /* Description: Accelerated Address Resolver */ -/* Register: AAR_TASKS_START */ -/* Description: Start resolving addresses based on IRKs specified in the IRK data structure */ - -/* Bit 0 : Start resolving addresses based on IRKs specified in the IRK data structure */ -#define AAR_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define AAR_TASKS_START_TASKS_START_Msk (0x1UL << AAR_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define AAR_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: AAR_TASKS_STOP */ -/* Description: Stop resolving addresses */ - -/* Bit 0 : Stop resolving addresses */ -#define AAR_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define AAR_TASKS_STOP_TASKS_STOP_Msk (0x1UL << AAR_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define AAR_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: AAR_EVENTS_END */ -/* Description: Address resolution procedure complete */ - -/* Bit 0 : Address resolution procedure complete */ -#define AAR_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ -#define AAR_EVENTS_END_EVENTS_END_Msk (0x1UL << AAR_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define AAR_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define AAR_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ - -/* Register: AAR_EVENTS_RESOLVED */ -/* Description: Address resolved */ - -/* Bit 0 : Address resolved */ -#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos (0UL) /*!< Position of EVENTS_RESOLVED field. */ -#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Msk (0x1UL << AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Pos) /*!< Bit mask of EVENTS_RESOLVED field. */ -#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_NotGenerated (0UL) /*!< Event not generated */ -#define AAR_EVENTS_RESOLVED_EVENTS_RESOLVED_Generated (1UL) /*!< Event generated */ - -/* Register: AAR_EVENTS_NOTRESOLVED */ -/* Description: Address not resolved */ - -/* Bit 0 : Address not resolved */ -#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos (0UL) /*!< Position of EVENTS_NOTRESOLVED field. */ -#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Msk (0x1UL << AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Pos) /*!< Bit mask of EVENTS_NOTRESOLVED field. */ -#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_NotGenerated (0UL) /*!< Event not generated */ -#define AAR_EVENTS_NOTRESOLVED_EVENTS_NOTRESOLVED_Generated (1UL) /*!< Event generated */ - /* Register: AAR_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for event NOTRESOLVED */ +/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event RESOLVED */ +/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event END */ +/* Bit 0 : Write '1' to Enable interrupt for END event */ #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -108,21 +63,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for event NOTRESOLVED */ +/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event RESOLVED */ +/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event END */ +/* Bit 0 : Write '1' to Disable interrupt for END event */ #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -169,7 +124,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: AAR_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved. */ +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ @@ -177,102 +132,52 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: ACL */ /* Description: Access control lists */ +/* Register: ACL_DISABLEINDEBUG */ +/* Description: Disable all ACL protection mechanisms for regions while in debug mode */ + +/* Bit 0 : Disable the protection mechanism for regions while in debug mode. */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << ACL_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< ACL is enabled in debug mode */ +#define ACL_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< ACL is disabled in debug mode */ + /* Register: ACL_ACL_ADDR */ -/* Description: Description cluster: Configure the word-aligned start address of region n to protect */ +/* Description: Description cluster[0]: Configure the word-aligned start address of region 0 to protect */ -/* Bits 31..0 : Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. */ +/* Bits 31..0 : Valid word-aligned start address of region 0 to protect. Address must point to a flash page boundary. */ #define ACL_ACL_ADDR_ADDR_Pos (0UL) /*!< Position of ADDR field. */ #define ACL_ACL_ADDR_ADDR_Msk (0xFFFFFFFFUL << ACL_ACL_ADDR_ADDR_Pos) /*!< Bit mask of ADDR field. */ /* Register: ACL_ACL_SIZE */ -/* Description: Description cluster: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. */ +/* Description: Description cluster[0]: Size of region to protect counting from address ACL[0].ADDR. Write '0' as no effect. */ -/* Bits 31..0 : Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512 kB. */ +/* Bits 31..0 : Size of flash region 0 in bytes. Must be a multiple of the flash page size. */ #define ACL_ACL_SIZE_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define ACL_ACL_SIZE_SIZE_Msk (0xFFFFFFFFUL << ACL_ACL_SIZE_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: ACL_ACL_PERM */ -/* Description: Description cluster: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE */ +/* Description: Description cluster[0]: Access permissions for region 0 as defined by start address ACL[0].ADDR and size ACL[0].SIZE */ -/* Bit 2 : Configure read permissions for region n. Write '0' has no effect. */ +/* Bit 2 : Configure read permissions for region 0. Write '0' has no effect. */ #define ACL_ACL_PERM_READ_Pos (2UL) /*!< Position of READ field. */ #define ACL_ACL_PERM_READ_Msk (0x1UL << ACL_ACL_PERM_READ_Pos) /*!< Bit mask of READ field. */ -#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region n */ -#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region n */ +#define ACL_ACL_PERM_READ_Enable (0UL) /*!< Allow read instructions to region 0 */ +#define ACL_ACL_PERM_READ_Disable (1UL) /*!< Block read instructions to region 0 */ -/* Bit 1 : Configure write and erase permissions for region n. Write '0' has no effect. */ +/* Bit 1 : Configure write and erase permissions for region 0. Write '0' has no effect. */ #define ACL_ACL_PERM_WRITE_Pos (1UL) /*!< Position of WRITE field. */ #define ACL_ACL_PERM_WRITE_Msk (0x1UL << ACL_ACL_PERM_WRITE_Pos) /*!< Bit mask of WRITE field. */ -#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region n */ -#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region n */ +#define ACL_ACL_PERM_WRITE_Enable (0UL) /*!< Allow write and erase instructions to region 0 */ +#define ACL_ACL_PERM_WRITE_Disable (1UL) /*!< Block write and erase instructions to region 0 */ /* Peripheral: CCM */ /* Description: AES CCM Mode Encryption */ -/* Register: CCM_TASKS_KSGEN */ -/* Description: Start generation of key-stream. This operation will stop by itself when completed. */ - -/* Bit 0 : Start generation of key-stream. This operation will stop by itself when completed. */ -#define CCM_TASKS_KSGEN_TASKS_KSGEN_Pos (0UL) /*!< Position of TASKS_KSGEN field. */ -#define CCM_TASKS_KSGEN_TASKS_KSGEN_Msk (0x1UL << CCM_TASKS_KSGEN_TASKS_KSGEN_Pos) /*!< Bit mask of TASKS_KSGEN field. */ -#define CCM_TASKS_KSGEN_TASKS_KSGEN_Trigger (1UL) /*!< Trigger task */ - -/* Register: CCM_TASKS_CRYPT */ -/* Description: Start encryption/decryption. This operation will stop by itself when completed. */ - -/* Bit 0 : Start encryption/decryption. This operation will stop by itself when completed. */ -#define CCM_TASKS_CRYPT_TASKS_CRYPT_Pos (0UL) /*!< Position of TASKS_CRYPT field. */ -#define CCM_TASKS_CRYPT_TASKS_CRYPT_Msk (0x1UL << CCM_TASKS_CRYPT_TASKS_CRYPT_Pos) /*!< Bit mask of TASKS_CRYPT field. */ -#define CCM_TASKS_CRYPT_TASKS_CRYPT_Trigger (1UL) /*!< Trigger task */ - -/* Register: CCM_TASKS_STOP */ -/* Description: Stop encryption/decryption */ - -/* Bit 0 : Stop encryption/decryption */ -#define CCM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define CCM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << CCM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define CCM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: CCM_TASKS_RATEOVERRIDE */ -/* Description: Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ - -/* Bit 0 : Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption */ -#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos (0UL) /*!< Position of TASKS_RATEOVERRIDE field. */ -#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Msk (0x1UL << CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Pos) /*!< Bit mask of TASKS_RATEOVERRIDE field. */ -#define CCM_TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Trigger (1UL) /*!< Trigger task */ - -/* Register: CCM_EVENTS_ENDKSGEN */ -/* Description: Key-stream generation complete */ - -/* Bit 0 : Key-stream generation complete */ -#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos (0UL) /*!< Position of EVENTS_ENDKSGEN field. */ -#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Msk (0x1UL << CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Pos) /*!< Bit mask of EVENTS_ENDKSGEN field. */ -#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_NotGenerated (0UL) /*!< Event not generated */ -#define CCM_EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Generated (1UL) /*!< Event generated */ - -/* Register: CCM_EVENTS_ENDCRYPT */ -/* Description: Encrypt/decrypt complete */ - -/* Bit 0 : Encrypt/decrypt complete */ -#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos (0UL) /*!< Position of EVENTS_ENDCRYPT field. */ -#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Msk (0x1UL << CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Pos) /*!< Bit mask of EVENTS_ENDCRYPT field. */ -#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_NotGenerated (0UL) /*!< Event not generated */ -#define CCM_EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Generated (1UL) /*!< Event generated */ - -/* Register: CCM_EVENTS_ERROR */ -/* Description: Deprecated register - CCM error event */ - -/* Bit 0 : Deprecated field - CCM error event */ -#define CCM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define CCM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << CCM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define CCM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define CCM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - /* Register: CCM_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 0 : Shortcut between event ENDKSGEN and task CRYPT */ +/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ @@ -281,21 +186,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Deprecated intsetfield - Write '1' to enable interrupt for event ERROR */ +/* Bit 2 : Write '1' to Enable interrupt for ERROR event */ #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event ENDCRYPT */ +/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event ENDKSGEN */ +/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -305,21 +210,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Deprecated intclrfield - Write '1' to disable interrupt for event ERROR */ +/* Bit 2 : Write '1' to Disable interrupt for ERROR event */ #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event ENDCRYPT */ +/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event ENDKSGEN */ +/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ @@ -350,8 +255,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : Packet length configuration */ #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ -#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. */ -#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. */ +#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packets up to 27 bytes will be generated. */ +#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packets up to MAXPACKETSIZE bytes will be generated. */ /* Bits 17..16 : Radio data rate that the CCM shall run synchronous with */ #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ @@ -391,15 +296,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CCM_SCRATCHPTR */ /* Description: Pointer to data area used for temporary storage */ -/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, - MIC generation and encryption/decryption. */ +/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ /* Register: CCM_MAXPACKETSIZE */ /* Description: Length of key-stream generated when MODE.LENGTH = Extended. */ -/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. */ +/* Bits 7..0 : Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet to be encrypted/decrypted. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos (0UL) /*!< Position of MAXPACKETSIZE field. */ #define CCM_MAXPACKETSIZE_MAXPACKETSIZE_Msk (0xFFUL << CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) /*!< Bit mask of MAXPACKETSIZE field. */ @@ -415,224 +319,34 @@ POSSIBILITY OF SUCH DAMAGE. #define CCM_RATEOVERRIDE_RATEOVERRIDE_500Kbps (3UL) /*!< 500 Kbps */ -/* Peripheral: CC_HOST_RGF */ -/* Description: CRYPTOCELL HOST_RGF interface */ - -/* Register: CC_HOST_RGF_HOST_CRYPTOKEY_SEL */ -/* Description: AES hardware key select */ - -/* Bits 1..0 : Select the source of the HW key that is used by the AES engine */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos (0UL) /*!< Position of HOST_CRYPTOKEY_SEL field. */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Msk (0x3UL << CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Pos) /*!< Bit mask of HOST_CRYPTOKEY_SEL field. */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_DR (0UL) /*!< Use device root key K_DR from CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_K_PRTL (1UL) /*!< Use hard-coded RTL key K_PRTL */ -#define CC_HOST_RGF_HOST_CRYPTOKEY_SEL_HOST_CRYPTOKEY_SEL_Session (2UL) /*!< Use provided session key */ - -/* Register: CC_HOST_RGF_HOST_IOT_KPRTL_LOCK */ -/* Description: This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ - -/* Bit 0 : This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. */ -#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos (0UL) /*!< Position of HOST_IOT_KPRTL_LOCK field. */ -#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Pos) /*!< Bit mask of HOST_IOT_KPRTL_LOCK field. */ -#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Disabled (0UL) /*!< K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL */ -#define CC_HOST_RGF_HOST_IOT_KPRTL_LOCK_HOST_IOT_KPRTL_LOCK_Enabled (1UL) /*!< K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. */ - -/* Register: CC_HOST_RGF_HOST_IOT_KDR0 */ -/* Description: This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. */ - -/* Bits 31..0 : Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos (0UL) /*!< Position of HOST_IOT_KDR0 field. */ -#define CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR0_HOST_IOT_KDR0_Pos) /*!< Bit mask of HOST_IOT_KDR0 field. */ - -/* Register: CC_HOST_RGF_HOST_IOT_KDR1 */ -/* Description: This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ - -/* Bits 31..0 : K_DR bits 63:32 */ -#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos (0UL) /*!< Position of HOST_IOT_KDR1 field. */ -#define CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR1_HOST_IOT_KDR1_Pos) /*!< Bit mask of HOST_IOT_KDR1 field. */ - -/* Register: CC_HOST_RGF_HOST_IOT_KDR2 */ -/* Description: This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ - -/* Bits 31..0 : K_DR bits 95:64 */ -#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos (0UL) /*!< Position of HOST_IOT_KDR2 field. */ -#define CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR2_HOST_IOT_KDR2_Pos) /*!< Bit mask of HOST_IOT_KDR2 field. */ - -/* Register: CC_HOST_RGF_HOST_IOT_KDR3 */ -/* Description: This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. */ - -/* Bits 31..0 : K_DR bits 127:96 */ -#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos (0UL) /*!< Position of HOST_IOT_KDR3 field. */ -#define CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Msk (0xFFFFFFFFUL << CC_HOST_RGF_HOST_IOT_KDR3_HOST_IOT_KDR3_Pos) /*!< Bit mask of HOST_IOT_KDR3 field. */ - -/* Register: CC_HOST_RGF_HOST_IOT_LCS */ -/* Description: Controls lifecycle state (LCS) for CRYPTOCELL subsystem */ - -/* Bit 8 : This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos (8UL) /*!< Position of LCS_IS_VALID field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Msk (0x1UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Pos) /*!< Bit mask of LCS_IS_VALID field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Invalid (0UL) /*!< A valid LCS is not yet retained in the CRYPTOCELL AO power domain */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_IS_VALID_Valid (1UL) /*!< A valid LCS is successfully retained in the CRYPTOCELL AO power domain */ - -/* Bits 2..0 : Lifecycle state value. This field is write-once per reset. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos (0UL) /*!< Position of LCS field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Msk (0x7UL << CC_HOST_RGF_HOST_IOT_LCS_LCS_Pos) /*!< Bit mask of LCS field. */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Debug (0UL) /*!< CC310 operates in debug mode */ -#define CC_HOST_RGF_HOST_IOT_LCS_LCS_Secure (2UL) /*!< CC310 operates in secure mode */ - - /* Peripheral: CLOCK */ /* Description: Clock control */ -/* Register: CLOCK_TASKS_HFCLKSTART */ -/* Description: Start HFXO crystal oscillator */ - -/* Bit 0 : Start HFXO crystal oscillator */ -#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos (0UL) /*!< Position of TASKS_HFCLKSTART field. */ -#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Msk (0x1UL << CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Pos) /*!< Bit mask of TASKS_HFCLKSTART field. */ -#define CLOCK_TASKS_HFCLKSTART_TASKS_HFCLKSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_HFCLKSTOP */ -/* Description: Stop HFXO crystal oscillator */ - -/* Bit 0 : Stop HFXO crystal oscillator */ -#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos (0UL) /*!< Position of TASKS_HFCLKSTOP field. */ -#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Pos) /*!< Bit mask of TASKS_HFCLKSTOP field. */ -#define CLOCK_TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_LFCLKSTART */ -/* Description: Start LFCLK */ - -/* Bit 0 : Start LFCLK */ -#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos (0UL) /*!< Position of TASKS_LFCLKSTART field. */ -#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Msk (0x1UL << CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Pos) /*!< Bit mask of TASKS_LFCLKSTART field. */ -#define CLOCK_TASKS_LFCLKSTART_TASKS_LFCLKSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_LFCLKSTOP */ -/* Description: Stop LFCLK */ - -/* Bit 0 : Stop LFCLK */ -#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos (0UL) /*!< Position of TASKS_LFCLKSTOP field. */ -#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Msk (0x1UL << CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Pos) /*!< Bit mask of TASKS_LFCLKSTOP field. */ -#define CLOCK_TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_CAL */ -/* Description: Start calibration of LFRC */ - -/* Bit 0 : Start calibration of LFRC */ -#define CLOCK_TASKS_CAL_TASKS_CAL_Pos (0UL) /*!< Position of TASKS_CAL field. */ -#define CLOCK_TASKS_CAL_TASKS_CAL_Msk (0x1UL << CLOCK_TASKS_CAL_TASKS_CAL_Pos) /*!< Bit mask of TASKS_CAL field. */ -#define CLOCK_TASKS_CAL_TASKS_CAL_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_CTSTART */ -/* Description: Start calibration timer */ - -/* Bit 0 : Start calibration timer */ -#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos (0UL) /*!< Position of TASKS_CTSTART field. */ -#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Msk (0x1UL << CLOCK_TASKS_CTSTART_TASKS_CTSTART_Pos) /*!< Bit mask of TASKS_CTSTART field. */ -#define CLOCK_TASKS_CTSTART_TASKS_CTSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_TASKS_CTSTOP */ -/* Description: Stop calibration timer */ - -/* Bit 0 : Stop calibration timer */ -#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos (0UL) /*!< Position of TASKS_CTSTOP field. */ -#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Msk (0x1UL << CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Pos) /*!< Bit mask of TASKS_CTSTOP field. */ -#define CLOCK_TASKS_CTSTOP_TASKS_CTSTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: CLOCK_EVENTS_HFCLKSTARTED */ -/* Description: HFXO crystal oscillator started */ - -/* Bit 0 : HFXO crystal oscillator started */ -#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_HFCLKSTARTED field. */ -#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_HFCLKSTARTED field. */ -#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: CLOCK_EVENTS_LFCLKSTARTED */ -/* Description: LFCLK started */ - -/* Bit 0 : LFCLK started */ -#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos (0UL) /*!< Position of EVENTS_LFCLKSTARTED field. */ -#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Msk (0x1UL << CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Pos) /*!< Bit mask of EVENTS_LFCLKSTARTED field. */ -#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: CLOCK_EVENTS_DONE */ -/* Description: Calibration of LFRC completed */ - -/* Bit 0 : Calibration of LFRC completed */ -#define CLOCK_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ -#define CLOCK_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << CLOCK_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ -#define CLOCK_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ - -/* Register: CLOCK_EVENTS_CTTO */ -/* Description: Calibration timer timeout */ - -/* Bit 0 : Calibration timer timeout */ -#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos (0UL) /*!< Position of EVENTS_CTTO field. */ -#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Msk (0x1UL << CLOCK_EVENTS_CTTO_EVENTS_CTTO_Pos) /*!< Bit mask of EVENTS_CTTO field. */ -#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_CTTO_EVENTS_CTTO_Generated (1UL) /*!< Event generated */ - -/* Register: CLOCK_EVENTS_CTSTARTED */ -/* Description: Calibration timer has been started and is ready to process new tasks */ - -/* Bit 0 : Calibration timer has been started and is ready to process new tasks */ -#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos (0UL) /*!< Position of EVENTS_CTSTARTED field. */ -#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Msk (0x1UL << CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Pos) /*!< Bit mask of EVENTS_CTSTARTED field. */ -#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_CTSTARTED_EVENTS_CTSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: CLOCK_EVENTS_CTSTOPPED */ -/* Description: Calibration timer has been stopped and is ready to process new tasks */ - -/* Bit 0 : Calibration timer has been stopped and is ready to process new tasks */ -#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos (0UL) /*!< Position of EVENTS_CTSTOPPED field. */ -#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Msk (0x1UL << CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Pos) /*!< Bit mask of EVENTS_CTSTOPPED field. */ -#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define CLOCK_EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Generated (1UL) /*!< Event generated */ - /* Register: CLOCK_INTENSET */ /* Description: Enable interrupt */ -/* Bit 11 : Write '1' to enable interrupt for event CTSTOPPED */ -#define CLOCK_INTENSET_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ -#define CLOCK_INTENSET_CTSTOPPED_Msk (0x1UL << CLOCK_INTENSET_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ -#define CLOCK_INTENSET_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_CTSTOPPED_Set (1UL) /*!< Enable */ - -/* Bit 10 : Write '1' to enable interrupt for event CTSTARTED */ -#define CLOCK_INTENSET_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ -#define CLOCK_INTENSET_CTSTARTED_Msk (0x1UL << CLOCK_INTENSET_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ -#define CLOCK_INTENSET_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENSET_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENSET_CTSTARTED_Set (1UL) /*!< Enable */ - -/* Bit 4 : Write '1' to enable interrupt for event CTTO */ +/* Bit 4 : Write '1' to Enable interrupt for CTTO event */ #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event DONE */ +/* Bit 3 : Write '1' to Enable interrupt for DONE event */ #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event LFCLKSTARTED */ +/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event HFCLKSTARTED */ +/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -642,42 +356,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 11 : Write '1' to disable interrupt for event CTSTOPPED */ -#define CLOCK_INTENCLR_CTSTOPPED_Pos (11UL) /*!< Position of CTSTOPPED field. */ -#define CLOCK_INTENCLR_CTSTOPPED_Msk (0x1UL << CLOCK_INTENCLR_CTSTOPPED_Pos) /*!< Bit mask of CTSTOPPED field. */ -#define CLOCK_INTENCLR_CTSTOPPED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_CTSTOPPED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_CTSTOPPED_Clear (1UL) /*!< Disable */ - -/* Bit 10 : Write '1' to disable interrupt for event CTSTARTED */ -#define CLOCK_INTENCLR_CTSTARTED_Pos (10UL) /*!< Position of CTSTARTED field. */ -#define CLOCK_INTENCLR_CTSTARTED_Msk (0x1UL << CLOCK_INTENCLR_CTSTARTED_Pos) /*!< Bit mask of CTSTARTED field. */ -#define CLOCK_INTENCLR_CTSTARTED_Disabled (0UL) /*!< Read: Disabled */ -#define CLOCK_INTENCLR_CTSTARTED_Enabled (1UL) /*!< Read: Enabled */ -#define CLOCK_INTENCLR_CTSTARTED_Clear (1UL) /*!< Disable */ - -/* Bit 4 : Write '1' to disable interrupt for event CTTO */ +/* Bit 4 : Write '1' to Disable interrupt for CTTO event */ #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event DONE */ +/* Bit 3 : Write '1' to Disable interrupt for DONE event */ #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event LFCLKSTARTED */ +/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event HFCLKSTARTED */ +/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -729,9 +429,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Source of LFCLK */ #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ -#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ -#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ +#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSTAT_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */ /* Register: CLOCK_LFCLKSRCCOPY */ /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ @@ -739,9 +440,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ -#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ -#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ +#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSRCCOPY_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */ /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK */ @@ -761,18 +463,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator (LFRC) */ -#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator (LFXO) */ -#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK (LFSYNT) */ - -/* Register: CLOCK_HFXODEBOUNCE */ -/* Description: HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. */ - -/* Bits 7..0 : HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. */ -#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos (0UL) /*!< Position of HFXODEBOUNCE field. */ -#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Msk (0xFFUL << CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Pos) /*!< Bit mask of HFXODEBOUNCE field. */ -#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db256us (0x10UL) /*!< 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. */ -#define CLOCK_HFXODEBOUNCE_HFXODEBOUNCE_Db1024us (0x40UL) /*!< 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. */ +#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ +#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ +#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ +#define CLOCK_LFCLKSRC_SRC_LFULP (3UL) /*!< 32.768 kHz ultra low power RC oscillator */ /* Register: CLOCK_CTIV */ /* Description: Calibration timer interval */ @@ -782,130 +476,55 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ /* Register: CLOCK_TRACECONFIG */ -/* Description: Clocking options for the trace port debug interface */ +/* Description: Clocking options for the Trace Port debug interface */ -/* Bits 17..16 : Pin multiplexing of trace signals. See pin assignment chapter for more details. */ +/* Bits 17..16 : Pin multiplexing of trace signals. */ #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ -#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< No trace signals routed to pins. All pins can be used as regular GPIOs. */ -#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. */ -#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. */ +#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ +#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ -/* Bits 1..0 : Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. */ +/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz trace port clock (TRACECLK = 16 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz trace port clock (TRACECLK = 8 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz trace port clock (TRACECLK = 4 MHz) */ -#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz trace port clock (TRACECLK = 2 MHz) */ - -/* Register: CLOCK_LFRCMODE */ -/* Description: LFRC mode configuration */ - -/* Bit 16 : Active LFRC mode. This field is read only. */ -#define CLOCK_LFRCMODE_STATUS_Pos (16UL) /*!< Position of STATUS field. */ -#define CLOCK_LFRCMODE_STATUS_Msk (0x1UL << CLOCK_LFRCMODE_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_LFRCMODE_STATUS_Normal (0UL) /*!< Normal mode */ -#define CLOCK_LFRCMODE_STATUS_ULP (1UL) /*!< Ultra-low power mode (ULP) */ - -/* Bit 0 : Set LFRC mode */ -#define CLOCK_LFRCMODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define CLOCK_LFRCMODE_MODE_Msk (0x1UL << CLOCK_LFRCMODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define CLOCK_LFRCMODE_MODE_Normal (0UL) /*!< Normal mode */ -#define CLOCK_LFRCMODE_MODE_ULP (1UL) /*!< Ultra-low power mode (ULP) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ +#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ /* Peripheral: COMP */ /* Description: Comparator */ -/* Register: COMP_TASKS_START */ -/* Description: Start comparator */ - -/* Bit 0 : Start comparator */ -#define COMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define COMP_TASKS_START_TASKS_START_Msk (0x1UL << COMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define COMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: COMP_TASKS_STOP */ -/* Description: Stop comparator */ - -/* Bit 0 : Stop comparator */ -#define COMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define COMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << COMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define COMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: COMP_TASKS_SAMPLE */ -/* Description: Sample comparator value */ - -/* Bit 0 : Sample comparator value */ -#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ -#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << COMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ -#define COMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ - -/* Register: COMP_EVENTS_READY */ -/* Description: COMP is ready and output is valid */ - -/* Bit 0 : COMP is ready and output is valid */ -#define COMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ -#define COMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << COMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ -#define COMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ -#define COMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ - -/* Register: COMP_EVENTS_DOWN */ -/* Description: Downward crossing */ - -/* Bit 0 : Downward crossing */ -#define COMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ -#define COMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << COMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ -#define COMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ -#define COMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ - -/* Register: COMP_EVENTS_UP */ -/* Description: Upward crossing */ - -/* Bit 0 : Upward crossing */ -#define COMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ -#define COMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << COMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ -#define COMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ -#define COMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ - -/* Register: COMP_EVENTS_CROSS */ -/* Description: Downward or upward crossing */ - -/* Bit 0 : Downward or upward crossing */ -#define COMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ -#define COMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << COMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ -#define COMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ -#define COMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ - /* Register: COMP_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 4 : Shortcut between event CROSS and task STOP */ +/* Bit 4 : Shortcut between CROSS event and STOP task */ #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event UP and task STOP */ +/* Bit 3 : Shortcut between UP event and STOP task */ #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event DOWN and task STOP */ +/* Bit 2 : Shortcut between DOWN event and STOP task */ #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event READY and task STOP */ +/* Bit 1 : Shortcut between READY event and STOP task */ #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event READY and task SAMPLE */ +/* Bit 0 : Shortcut between READY event and SAMPLE task */ #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -914,25 +533,25 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 3 : Enable or disable interrupt for event CROSS */ +/* Bit 3 : Enable or disable interrupt for CROSS event */ #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event UP */ +/* Bit 2 : Enable or disable interrupt for UP event */ #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event DOWN */ +/* Bit 1 : Enable or disable interrupt for DOWN event */ #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event READY */ +/* Bit 0 : Enable or disable interrupt for READY event */ #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -941,28 +560,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for event CROSS */ +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event UP */ +/* Bit 2 : Write '1' to Enable interrupt for UP event */ #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event DOWN */ +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event READY */ +/* Bit 0 : Write '1' to Enable interrupt for READY event */ #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -972,28 +591,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for event CROSS */ +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event UP */ +/* Bit 2 : Write '1' to Disable interrupt for UP event */ #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event DOWN */ +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event READY */ +/* Bit 0 : Write '1' to Disable interrupt for READY event */ #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -1034,7 +653,7 @@ POSSIBILITY OF SUCH DAMAGE. #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ /* Register: COMP_REFSEL */ -/* Description: Reference source select for single-ended mode */ +/* Description: Reference source select */ /* Bits 2..0 : Reference select */ #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ @@ -1043,22 +662,16 @@ POSSIBILITY OF SUCH DAMAGE. #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ -#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ +#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ /* Register: COMP_EXTREFSEL */ /* Description: External reference select */ -/* Bits 2..0 : External analog reference select */ +/* Bit 0 : External analog reference select */ #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ /* Register: COMP_TH */ /* Description: Threshold configuration for hysteresis unit */ @@ -1074,18 +687,18 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_MODE */ /* Description: Mode configuration */ -/* Bit 8 : Main operation modes */ +/* Bit 8 : Main operation mode */ #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ -/* Bits 1..0 : Speed and power modes */ +/* Bits 1..0 : Speed and power mode */ #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ -#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ +#define COMP_MODE_SP_High (2UL) /*!< High speed mode */ /* Register: COMP_HYST */ /* Description: Comparator hysteresis enable */ @@ -1096,68 +709,45 @@ POSSIBILITY OF SUCH DAMAGE. #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ +/* Register: COMP_ISOURCE */ +/* Description: Current source select on analog input */ + +/* Bits 1..0 : Comparator hysteresis */ +#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ +#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ +#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ +#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ + /* Peripheral: CRYPTOCELL */ -/* Description: ARM TrustZone CryptoCell register interface */ +/* Description: ARM CryptoCell register interface */ /* Register: CRYPTOCELL_ENABLE */ -/* Description: Enable CRYPTOCELL subsystem */ +/* Description: Control power and clock for ARM CryptoCell subsystem */ -/* Bit 0 : Enable or disable the CRYPTOCELL subsystem */ +/* Bit 0 : Enable or disable the CryptoCell subsystem */ #define CRYPTOCELL_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define CRYPTOCELL_ENABLE_ENABLE_Msk (0x1UL << CRYPTOCELL_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CRYPTOCELL subsystem disabled */ -#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CRYPTOCELL subsystem enabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Disabled (0UL) /*!< CryptoCell subsystem disabled */ +#define CRYPTOCELL_ENABLE_ENABLE_Enabled (1UL) /*!< CryptoCell subsystem enabled */ /* Peripheral: ECB */ /* Description: AES ECB Mode Encryption */ -/* Register: ECB_TASKS_STARTECB */ -/* Description: Start ECB block encrypt */ - -/* Bit 0 : Start ECB block encrypt */ -#define ECB_TASKS_STARTECB_TASKS_STARTECB_Pos (0UL) /*!< Position of TASKS_STARTECB field. */ -#define ECB_TASKS_STARTECB_TASKS_STARTECB_Msk (0x1UL << ECB_TASKS_STARTECB_TASKS_STARTECB_Pos) /*!< Bit mask of TASKS_STARTECB field. */ -#define ECB_TASKS_STARTECB_TASKS_STARTECB_Trigger (1UL) /*!< Trigger task */ - -/* Register: ECB_TASKS_STOPECB */ -/* Description: Abort a possible executing ECB operation */ - -/* Bit 0 : Abort a possible executing ECB operation */ -#define ECB_TASKS_STOPECB_TASKS_STOPECB_Pos (0UL) /*!< Position of TASKS_STOPECB field. */ -#define ECB_TASKS_STOPECB_TASKS_STOPECB_Msk (0x1UL << ECB_TASKS_STOPECB_TASKS_STOPECB_Pos) /*!< Bit mask of TASKS_STOPECB field. */ -#define ECB_TASKS_STOPECB_TASKS_STOPECB_Trigger (1UL) /*!< Trigger task */ - -/* Register: ECB_EVENTS_ENDECB */ -/* Description: ECB block encrypt complete */ - -/* Bit 0 : ECB block encrypt complete */ -#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos (0UL) /*!< Position of EVENTS_ENDECB field. */ -#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Msk (0x1UL << ECB_EVENTS_ENDECB_EVENTS_ENDECB_Pos) /*!< Bit mask of EVENTS_ENDECB field. */ -#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_NotGenerated (0UL) /*!< Event not generated */ -#define ECB_EVENTS_ENDECB_EVENTS_ENDECB_Generated (1UL) /*!< Event generated */ - -/* Register: ECB_EVENTS_ERRORECB */ -/* Description: ECB block encrypt aborted because of a STOPECB task or due to an error */ - -/* Bit 0 : ECB block encrypt aborted because of a STOPECB task or due to an error */ -#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos (0UL) /*!< Position of EVENTS_ERRORECB field. */ -#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Msk (0x1UL << ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Pos) /*!< Bit mask of EVENTS_ERRORECB field. */ -#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_NotGenerated (0UL) /*!< Event not generated */ -#define ECB_EVENTS_ERRORECB_EVENTS_ERRORECB_Generated (1UL) /*!< Event generated */ - /* Register: ECB_INTENSET */ /* Description: Enable interrupt */ -/* Bit 1 : Write '1' to enable interrupt for event ERRORECB */ +/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event ENDECB */ +/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1167,14 +757,14 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: ECB_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 1 : Write '1' to disable interrupt for event ERRORECB */ +/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event ENDECB */ +/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ @@ -1192,117 +782,100 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: EGU */ /* Description: Event Generator Unit 0 */ -/* Register: EGU_TASKS_TRIGGER */ -/* Description: Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event */ - -/* Bit 0 : Trigger n for triggering the corresponding TRIGGERED[n] event */ -#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos (0UL) /*!< Position of TASKS_TRIGGER field. */ -#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Msk (0x1UL << EGU_TASKS_TRIGGER_TASKS_TRIGGER_Pos) /*!< Bit mask of TASKS_TRIGGER field. */ -#define EGU_TASKS_TRIGGER_TASKS_TRIGGER_Trigger (1UL) /*!< Trigger task */ - -/* Register: EGU_EVENTS_TRIGGERED */ -/* Description: Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task */ - -/* Bit 0 : Event number n generated by triggering the corresponding TRIGGER[n] task */ -#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos (0UL) /*!< Position of EVENTS_TRIGGERED field. */ -#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Msk (0x1UL << EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Pos) /*!< Bit mask of EVENTS_TRIGGERED field. */ -#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_NotGenerated (0UL) /*!< Event not generated */ -#define EGU_EVENTS_TRIGGERED_EVENTS_TRIGGERED_Generated (1UL) /*!< Event generated */ - /* Register: EGU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 15 : Enable or disable interrupt for event TRIGGERED[15] */ +/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for event TRIGGERED[14] */ +/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for event TRIGGERED[13] */ +/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for event TRIGGERED[12] */ +/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for event TRIGGERED[11] */ +/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for event TRIGGERED[10] */ +/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for event TRIGGERED[9] */ +/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for event TRIGGERED[8] */ +/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event TRIGGERED[7] */ +/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event TRIGGERED[6] */ +/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event TRIGGERED[5] */ +/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event TRIGGERED[4] */ +/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event TRIGGERED[3] */ +/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event TRIGGERED[2] */ +/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event TRIGGERED[1] */ +/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event TRIGGERED[0] */ +/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ @@ -1311,112 +884,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 15 : Write '1' to enable interrupt for event TRIGGERED[15] */ +/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for event TRIGGERED[14] */ +/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for event TRIGGERED[13] */ +/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for event TRIGGERED[12] */ +/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for event TRIGGERED[11] */ +/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for event TRIGGERED[10] */ +/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event TRIGGERED[9] */ +/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for event TRIGGERED[8] */ +/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event TRIGGERED[7] */ +/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event TRIGGERED[6] */ +/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event TRIGGERED[5] */ +/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event TRIGGERED[4] */ +/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event TRIGGERED[3] */ +/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event TRIGGERED[2] */ +/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event TRIGGERED[1] */ +/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event TRIGGERED[0] */ +/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1426,112 +999,112 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: EGU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 15 : Write '1' to disable interrupt for event TRIGGERED[15] */ +/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for event TRIGGERED[14] */ +/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for event TRIGGERED[13] */ +/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for event TRIGGERED[12] */ +/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for event TRIGGERED[11] */ +/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for event TRIGGERED[10] */ +/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event TRIGGERED[9] */ +/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for event TRIGGERED[8] */ +/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event TRIGGERED[7] */ +/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event TRIGGERED[6] */ +/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event TRIGGERED[5] */ +/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event TRIGGERED[4] */ +/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event TRIGGERED[3] */ +/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event TRIGGERED[2] */ +/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event TRIGGERED[1] */ +/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event TRIGGERED[0] */ +/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ @@ -1540,7 +1113,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: FICR */ -/* Description: Factory information configuration registers */ +/* Description: Factory Information Configuration Registers */ /* Register: FICR_CODEPAGESIZE */ /* Description: Code memory page size */ @@ -1557,23 +1130,23 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ /* Register: FICR_DEVICEID */ -/* Description: Description collection: Device identifier */ +/* Description: Description collection[0]: Device identifier */ /* Bits 31..0 : 64 bit unique device identifier */ #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ /* Register: FICR_ER */ -/* Description: Description collection: Encryption root, word n */ +/* Description: Description collection[0]: Encryption root, word 0 */ -/* Bits 31..0 : Encryption root, word n */ +/* Bits 31..0 : Encryption root, word 0 */ #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ /* Register: FICR_IR */ -/* Description: Description collection: Identity Root, word n */ +/* Description: Description collection[0]: Identity Root, word 0 */ -/* Bits 31..0 : Identity Root, word n */ +/* Bits 31..0 : Identity Root, word 0 */ #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ @@ -1587,7 +1160,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ /* Register: FICR_DEVICEADDR */ -/* Description: Description collection: Device address n */ +/* Description: Description collection[0]: Device address 0 */ /* Bits 31..0 : 48 bit device address */ #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ @@ -1599,23 +1172,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 31..0 : Part code */ #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ -#define FICR_INFO_PART_PART_N52833 (0x52833UL) /*!< nRF52833 */ #define FICR_INFO_PART_PART_N52840 (0x52840UL) /*!< nRF52840 */ #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_VARIANT */ -/* Description: Build code (hardware version and production configuration) */ +/* Description: Part variant (hardware version and production configuration). */ -/* Bits 31..0 : Build code (hardware version and production configuration). Encoded as ASCII. */ +/* Bits 31..0 : Part variant (hardware version and production configuration). Encoded as ASCII. */ #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ +#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ -#define FICR_INFO_VARIANT_VARIANT_AACA (0x41414341UL) /*!< AACA */ -#define FICR_INFO_VARIANT_VARIANT_BAAA (0x42414141UL) /*!< BAAA */ -#define FICR_INFO_VARIANT_VARIANT_CAAA (0x43414141UL) /*!< CAAA */ +#define FICR_INFO_VARIANT_VARIANT_ABBA (0x41424241UL) /*!< ABBA */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -1625,7 +1196,6 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QI (0x2004UL) /*!< QIxx - 73-pin aQFN */ -#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - WLCSP */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -1654,136 +1224,127 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_FLASH_FLASH_K2048 (0x800UL) /*!< 2 MByte FLASH */ #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ -/* Register: FICR_PRODTEST */ -/* Description: Description collection: Production test signature n */ - -/* Bits 31..0 : Production test signature n */ -#define FICR_PRODTEST_PRODTEST_Pos (0UL) /*!< Position of PRODTEST field. */ -#define FICR_PRODTEST_PRODTEST_Msk (0xFFFFFFFFUL << FICR_PRODTEST_PRODTEST_Pos) /*!< Bit mask of PRODTEST field. */ -#define FICR_PRODTEST_PRODTEST_Done (0xBB42319FUL) /*!< Production tests done */ -#define FICR_PRODTEST_PRODTEST_NotDone (0xFFFFFFFFUL) /*!< Production tests not done */ - /* Register: FICR_TEMP_A0 */ -/* Description: Slope definition A0 */ +/* Description: Slope definition A0. */ /* Bits 11..0 : A (slope definition) register. */ #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ /* Register: FICR_TEMP_A1 */ -/* Description: Slope definition A1 */ +/* Description: Slope definition A1. */ /* Bits 11..0 : A (slope definition) register. */ #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ /* Register: FICR_TEMP_A2 */ -/* Description: Slope definition A2 */ +/* Description: Slope definition A2. */ /* Bits 11..0 : A (slope definition) register. */ #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ /* Register: FICR_TEMP_A3 */ -/* Description: Slope definition A3 */ +/* Description: Slope definition A3. */ /* Bits 11..0 : A (slope definition) register. */ #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ /* Register: FICR_TEMP_A4 */ -/* Description: Slope definition A4 */ +/* Description: Slope definition A4. */ /* Bits 11..0 : A (slope definition) register. */ #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ /* Register: FICR_TEMP_A5 */ -/* Description: Slope definition A5 */ +/* Description: Slope definition A5. */ /* Bits 11..0 : A (slope definition) register. */ #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ /* Register: FICR_TEMP_B0 */ -/* Description: Y-intercept B0 */ +/* Description: y-intercept B0. */ /* Bits 13..0 : B (y-intercept) */ #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ /* Register: FICR_TEMP_B1 */ -/* Description: Y-intercept B1 */ +/* Description: y-intercept B1. */ /* Bits 13..0 : B (y-intercept) */ #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ /* Register: FICR_TEMP_B2 */ -/* Description: Y-intercept B2 */ +/* Description: y-intercept B2. */ /* Bits 13..0 : B (y-intercept) */ #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ /* Register: FICR_TEMP_B3 */ -/* Description: Y-intercept B3 */ +/* Description: y-intercept B3. */ /* Bits 13..0 : B (y-intercept) */ #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ /* Register: FICR_TEMP_B4 */ -/* Description: Y-intercept B4 */ +/* Description: y-intercept B4. */ /* Bits 13..0 : B (y-intercept) */ #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ /* Register: FICR_TEMP_B5 */ -/* Description: Y-intercept B5 */ +/* Description: y-intercept B5. */ /* Bits 13..0 : B (y-intercept) */ #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ /* Register: FICR_TEMP_T0 */ -/* Description: Segment end T0 */ +/* Description: Segment end T0. */ -/* Bits 7..0 : T (segment end) register */ +/* Bits 7..0 : T (segment end)register. */ #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_TEMP_T1 */ -/* Description: Segment end T1 */ +/* Description: Segment end T1. */ -/* Bits 7..0 : T (segment end) register */ +/* Bits 7..0 : T (segment end)register. */ #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_TEMP_T2 */ -/* Description: Segment end T2 */ +/* Description: Segment end T2. */ -/* Bits 7..0 : T (segment end) register */ +/* Bits 7..0 : T (segment end)register. */ #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_TEMP_T3 */ -/* Description: Segment end T3 */ +/* Description: Segment end T3. */ -/* Bits 7..0 : T (segment end) register */ +/* Bits 7..0 : T (segment end)register. */ #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_TEMP_T4 */ -/* Description: Segment end T4 */ +/* Description: Segment end T4. */ -/* Bits 7..0 : T (segment end) register */ +/* Bits 7..0 : T (segment end)register. */ #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ /* Register: FICR_NFC_TAGHEADER0 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 3 */ #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ @@ -1802,7 +1363,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ /* Register: FICR_NFC_TAGHEADER1 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 7 */ #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ @@ -1821,7 +1382,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ /* Register: FICR_NFC_TAGHEADER2 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 11 */ #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ @@ -1840,7 +1401,7 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ /* Register: FICR_NFC_TAGHEADER3 */ -/* Description: Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST, and NFCID1_LAST. */ +/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ /* Bits 31..24 : Unique identifier byte 15 */ #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ @@ -1858,168 +1419,70 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ -/* Register: FICR_TRNG90B_BYTES */ -/* Description: Amount of bytes for the required entropy bits */ - -/* Bits 31..0 : Amount of bytes for the required entropy bits */ -#define FICR_TRNG90B_BYTES_BYTES_Pos (0UL) /*!< Position of BYTES field. */ -#define FICR_TRNG90B_BYTES_BYTES_Msk (0xFFFFFFFFUL << FICR_TRNG90B_BYTES_BYTES_Pos) /*!< Bit mask of BYTES field. */ - -/* Register: FICR_TRNG90B_RCCUTOFF */ -/* Description: Repetition counter cutoff */ - -/* Bits 31..0 : Repetition counter cutoff */ -#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos (0UL) /*!< Position of RCCUTOFF field. */ -#define FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_RCCUTOFF_RCCUTOFF_Pos) /*!< Bit mask of RCCUTOFF field. */ - -/* Register: FICR_TRNG90B_APCUTOFF */ -/* Description: Adaptive proportion cutoff */ - -/* Bits 31..0 : Adaptive proportion cutoff */ -#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos (0UL) /*!< Position of APCUTOFF field. */ -#define FICR_TRNG90B_APCUTOFF_APCUTOFF_Msk (0xFFFFFFFFUL << FICR_TRNG90B_APCUTOFF_APCUTOFF_Pos) /*!< Bit mask of APCUTOFF field. */ - -/* Register: FICR_TRNG90B_STARTUP */ -/* Description: Amount of bytes for the startup tests */ - -/* Bits 31..0 : Amount of bytes for the startup tests */ -#define FICR_TRNG90B_STARTUP_STARTUP_Pos (0UL) /*!< Position of STARTUP field. */ -#define FICR_TRNG90B_STARTUP_STARTUP_Msk (0xFFFFFFFFUL << FICR_TRNG90B_STARTUP_STARTUP_Pos) /*!< Bit mask of STARTUP field. */ - -/* Register: FICR_TRNG90B_ROSC1 */ -/* Description: Sample count for ring oscillator 1 */ - -/* Bits 31..0 : Sample count for ring oscillator 1 */ -#define FICR_TRNG90B_ROSC1_ROSC1_Pos (0UL) /*!< Position of ROSC1 field. */ -#define FICR_TRNG90B_ROSC1_ROSC1_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC1_ROSC1_Pos) /*!< Bit mask of ROSC1 field. */ - -/* Register: FICR_TRNG90B_ROSC2 */ -/* Description: Sample count for ring oscillator 2 */ - -/* Bits 31..0 : Sample count for ring oscillator 2 */ -#define FICR_TRNG90B_ROSC2_ROSC2_Pos (0UL) /*!< Position of ROSC2 field. */ -#define FICR_TRNG90B_ROSC2_ROSC2_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC2_ROSC2_Pos) /*!< Bit mask of ROSC2 field. */ - -/* Register: FICR_TRNG90B_ROSC3 */ -/* Description: Sample count for ring oscillator 3 */ - -/* Bits 31..0 : Sample count for ring oscillator 3 */ -#define FICR_TRNG90B_ROSC3_ROSC3_Pos (0UL) /*!< Position of ROSC3 field. */ -#define FICR_TRNG90B_ROSC3_ROSC3_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC3_ROSC3_Pos) /*!< Bit mask of ROSC3 field. */ - -/* Register: FICR_TRNG90B_ROSC4 */ -/* Description: Sample count for ring oscillator 4 */ - -/* Bits 31..0 : Sample count for ring oscillator 4 */ -#define FICR_TRNG90B_ROSC4_ROSC4_Pos (0UL) /*!< Position of ROSC4 field. */ -#define FICR_TRNG90B_ROSC4_ROSC4_Msk (0xFFFFFFFFUL << FICR_TRNG90B_ROSC4_ROSC4_Pos) /*!< Bit mask of ROSC4 field. */ - /* Peripheral: GPIOTE */ /* Description: GPIO Tasks and Events */ -/* Register: GPIOTE_TASKS_OUT */ -/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ - -/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. */ -#define GPIOTE_TASKS_OUT_TASKS_OUT_Pos (0UL) /*!< Position of TASKS_OUT field. */ -#define GPIOTE_TASKS_OUT_TASKS_OUT_Msk (0x1UL << GPIOTE_TASKS_OUT_TASKS_OUT_Pos) /*!< Bit mask of TASKS_OUT field. */ -#define GPIOTE_TASKS_OUT_TASKS_OUT_Trigger (1UL) /*!< Trigger task */ - -/* Register: GPIOTE_TASKS_SET */ -/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ - -/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. */ -#define GPIOTE_TASKS_SET_TASKS_SET_Pos (0UL) /*!< Position of TASKS_SET field. */ -#define GPIOTE_TASKS_SET_TASKS_SET_Msk (0x1UL << GPIOTE_TASKS_SET_TASKS_SET_Pos) /*!< Bit mask of TASKS_SET field. */ -#define GPIOTE_TASKS_SET_TASKS_SET_Trigger (1UL) /*!< Trigger task */ - -/* Register: GPIOTE_TASKS_CLR */ -/* Description: Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ - -/* Bit 0 : Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. */ -#define GPIOTE_TASKS_CLR_TASKS_CLR_Pos (0UL) /*!< Position of TASKS_CLR field. */ -#define GPIOTE_TASKS_CLR_TASKS_CLR_Msk (0x1UL << GPIOTE_TASKS_CLR_TASKS_CLR_Pos) /*!< Bit mask of TASKS_CLR field. */ -#define GPIOTE_TASKS_CLR_TASKS_CLR_Trigger (1UL) /*!< Trigger task */ - -/* Register: GPIOTE_EVENTS_IN */ -/* Description: Description collection: Event generated from pin specified in CONFIG[n].PSEL */ - -/* Bit 0 : Event generated from pin specified in CONFIG[n].PSEL */ -#define GPIOTE_EVENTS_IN_EVENTS_IN_Pos (0UL) /*!< Position of EVENTS_IN field. */ -#define GPIOTE_EVENTS_IN_EVENTS_IN_Msk (0x1UL << GPIOTE_EVENTS_IN_EVENTS_IN_Pos) /*!< Bit mask of EVENTS_IN field. */ -#define GPIOTE_EVENTS_IN_EVENTS_IN_NotGenerated (0UL) /*!< Event not generated */ -#define GPIOTE_EVENTS_IN_EVENTS_IN_Generated (1UL) /*!< Event generated */ - -/* Register: GPIOTE_EVENTS_PORT */ -/* Description: Event generated from multiple input GPIO pins with SENSE mechanism enabled */ - -/* Bit 0 : Event generated from multiple input GPIO pins with SENSE mechanism enabled */ -#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos (0UL) /*!< Position of EVENTS_PORT field. */ -#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Msk (0x1UL << GPIOTE_EVENTS_PORT_EVENTS_PORT_Pos) /*!< Bit mask of EVENTS_PORT field. */ -#define GPIOTE_EVENTS_PORT_EVENTS_PORT_NotGenerated (0UL) /*!< Event not generated */ -#define GPIOTE_EVENTS_PORT_EVENTS_PORT_Generated (1UL) /*!< Event generated */ - /* Register: GPIOTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 31 : Write '1' to enable interrupt for event PORT */ +/* Bit 31 : Write '1' to Enable interrupt for PORT event */ #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event IN[7] */ +/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event IN[6] */ +/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event IN[5] */ +/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event IN[4] */ +/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event IN[3] */ +/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event IN[2] */ +/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event IN[1] */ +/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event IN[0] */ +/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -2029,63 +1492,63 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIOTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 31 : Write '1' to disable interrupt for event PORT */ +/* Bit 31 : Write '1' to Disable interrupt for PORT event */ #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event IN[7] */ +/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event IN[6] */ +/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event IN[5] */ +/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event IN[4] */ +/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event IN[3] */ +/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event IN[2] */ +/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event IN[1] */ +/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event IN[0] */ +/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ @@ -2093,7 +1556,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ /* Register: GPIOTE_CONFIG */ -/* Description: Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ +/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ @@ -2109,9 +1572,9 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ -/* Bit 13 : Port number */ +/* Bits 14..13 : Port number */ #define GPIOTE_CONFIG_PORT_Pos (13UL) /*!< Position of PORT field. */ -#define GPIOTE_CONFIG_PORT_Msk (0x1UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ +#define GPIOTE_CONFIG_PORT_Msk (0x3UL << GPIOTE_CONFIG_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ @@ -2128,69 +1591,22 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: I2S */ /* Description: Inter-IC Sound */ -/* Register: I2S_TASKS_START */ -/* Description: Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ - -/* Bit 0 : Starts continuous I2S transfer. Also starts MCK generator when this is enabled. */ -#define I2S_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define I2S_TASKS_START_TASKS_START_Msk (0x1UL << I2S_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define I2S_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: I2S_TASKS_STOP */ -/* Description: Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ - -/* Bit 0 : Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. */ -#define I2S_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define I2S_TASKS_STOP_TASKS_STOP_Msk (0x1UL << I2S_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define I2S_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: I2S_EVENTS_RXPTRUPD */ -/* Description: The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ - -/* Bit 0 : The RXD.PTR register has been copied to internal double-buffers. - When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. */ -#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos (0UL) /*!< Position of EVENTS_RXPTRUPD field. */ -#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Msk (0x1UL << I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Pos) /*!< Bit mask of EVENTS_RXPTRUPD field. */ -#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ -#define I2S_EVENTS_RXPTRUPD_EVENTS_RXPTRUPD_Generated (1UL) /*!< Event generated */ - -/* Register: I2S_EVENTS_STOPPED */ -/* Description: I2S transfer stopped. */ - -/* Bit 0 : I2S transfer stopped. */ -#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << I2S_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define I2S_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: I2S_EVENTS_TXPTRUPD */ -/* Description: The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ - -/* Bit 0 : The TDX.PTR register has been copied to internal double-buffers. - When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. */ -#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos (0UL) /*!< Position of EVENTS_TXPTRUPD field. */ -#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Msk (0x1UL << I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Pos) /*!< Bit mask of EVENTS_TXPTRUPD field. */ -#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_NotGenerated (0UL) /*!< Event not generated */ -#define I2S_EVENTS_TXPTRUPD_EVENTS_TXPTRUPD_Generated (1UL) /*!< Event generated */ - /* Register: I2S_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 5 : Enable or disable interrupt for event TXPTRUPD */ +/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event STOPPED */ +/* Bit 2 : Enable or disable interrupt for STOPPED event */ #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event RXPTRUPD */ +/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ @@ -2199,21 +1615,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENSET */ /* Description: Enable interrupt */ -/* Bit 5 : Write '1' to enable interrupt for event TXPTRUPD */ +/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event RXPTRUPD */ +/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2223,21 +1639,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: I2S_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 5 : Write '1' to disable interrupt for event TXPTRUPD */ +/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event RXPTRUPD */ +/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ @@ -2308,6 +1724,11 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ +#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ /* Register: I2S_CONFIG_RATIO */ /* Description: MCK / LRCK ratio. */ @@ -2393,9 +1814,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ -#define I2S_PSEL_MCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define I2S_PSEL_MCK_PORT_Msk (0x1UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ +/* Bits 9..8 : Port number */ +#define I2S_PSEL_MCK_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_MCK_PORT_Msk (0x3UL << I2S_PSEL_MCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2410,9 +1831,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ -#define I2S_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define I2S_PSEL_SCK_PORT_Msk (0x1UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ +/* Bits 9..8 : Port number */ +#define I2S_PSEL_SCK_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SCK_PORT_Msk (0x3UL << I2S_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2427,9 +1848,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ -#define I2S_PSEL_LRCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define I2S_PSEL_LRCK_PORT_Msk (0x1UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */ +/* Bits 9..8 : Port number */ +#define I2S_PSEL_LRCK_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_LRCK_PORT_Msk (0x3UL << I2S_PSEL_LRCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2444,9 +1865,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ -#define I2S_PSEL_SDIN_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define I2S_PSEL_SDIN_PORT_Msk (0x1UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ +/* Bits 9..8 : Port number */ +#define I2S_PSEL_SDIN_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDIN_PORT_Msk (0x3UL << I2S_PSEL_SDIN_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2461,9 +1882,9 @@ POSSIBILITY OF SUCH DAMAGE. #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ -#define I2S_PSEL_SDOUT_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define I2S_PSEL_SDOUT_PORT_Msk (0x1UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ +/* Bits 9..8 : Port number */ +#define I2S_PSEL_SDOUT_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define I2S_PSEL_SDOUT_PORT_Msk (0x3UL << I2S_PSEL_SDOUT_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -2473,94 +1894,34 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: LPCOMP */ /* Description: Low Power Comparator */ -/* Register: LPCOMP_TASKS_START */ -/* Description: Start comparator */ - -/* Bit 0 : Start comparator */ -#define LPCOMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define LPCOMP_TASKS_START_TASKS_START_Msk (0x1UL << LPCOMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define LPCOMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: LPCOMP_TASKS_STOP */ -/* Description: Stop comparator */ - -/* Bit 0 : Stop comparator */ -#define LPCOMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define LPCOMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << LPCOMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define LPCOMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: LPCOMP_TASKS_SAMPLE */ -/* Description: Sample comparator value */ - -/* Bit 0 : Sample comparator value */ -#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ -#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ -#define LPCOMP_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ - -/* Register: LPCOMP_EVENTS_READY */ -/* Description: LPCOMP is ready and output is valid */ - -/* Bit 0 : LPCOMP is ready and output is valid */ -#define LPCOMP_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ -#define LPCOMP_EVENTS_READY_EVENTS_READY_Msk (0x1UL << LPCOMP_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ -#define LPCOMP_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ -#define LPCOMP_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ - -/* Register: LPCOMP_EVENTS_DOWN */ -/* Description: Downward crossing */ - -/* Bit 0 : Downward crossing */ -#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos (0UL) /*!< Position of EVENTS_DOWN field. */ -#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Msk (0x1UL << LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Pos) /*!< Bit mask of EVENTS_DOWN field. */ -#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_NotGenerated (0UL) /*!< Event not generated */ -#define LPCOMP_EVENTS_DOWN_EVENTS_DOWN_Generated (1UL) /*!< Event generated */ - -/* Register: LPCOMP_EVENTS_UP */ -/* Description: Upward crossing */ - -/* Bit 0 : Upward crossing */ -#define LPCOMP_EVENTS_UP_EVENTS_UP_Pos (0UL) /*!< Position of EVENTS_UP field. */ -#define LPCOMP_EVENTS_UP_EVENTS_UP_Msk (0x1UL << LPCOMP_EVENTS_UP_EVENTS_UP_Pos) /*!< Bit mask of EVENTS_UP field. */ -#define LPCOMP_EVENTS_UP_EVENTS_UP_NotGenerated (0UL) /*!< Event not generated */ -#define LPCOMP_EVENTS_UP_EVENTS_UP_Generated (1UL) /*!< Event generated */ - -/* Register: LPCOMP_EVENTS_CROSS */ -/* Description: Downward or upward crossing */ - -/* Bit 0 : Downward or upward crossing */ -#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos (0UL) /*!< Position of EVENTS_CROSS field. */ -#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Msk (0x1UL << LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Pos) /*!< Bit mask of EVENTS_CROSS field. */ -#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_NotGenerated (0UL) /*!< Event not generated */ -#define LPCOMP_EVENTS_CROSS_EVENTS_CROSS_Generated (1UL) /*!< Event generated */ - /* Register: LPCOMP_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 4 : Shortcut between event CROSS and task STOP */ +/* Bit 4 : Shortcut between CROSS event and STOP task */ #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event UP and task STOP */ +/* Bit 3 : Shortcut between UP event and STOP task */ #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event DOWN and task STOP */ +/* Bit 2 : Shortcut between DOWN event and STOP task */ #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event READY and task STOP */ +/* Bit 1 : Shortcut between READY event and STOP task */ #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event READY and task SAMPLE */ +/* Bit 0 : Shortcut between READY event and SAMPLE task */ #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ @@ -2569,28 +1930,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 3 : Write '1' to enable interrupt for event CROSS */ +/* Bit 3 : Write '1' to Enable interrupt for CROSS event */ #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event UP */ +/* Bit 2 : Write '1' to Enable interrupt for UP event */ #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event DOWN */ +/* Bit 1 : Write '1' to Enable interrupt for DOWN event */ #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event READY */ +/* Bit 0 : Write '1' to Enable interrupt for READY event */ #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2600,28 +1961,28 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: LPCOMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 3 : Write '1' to disable interrupt for event CROSS */ +/* Bit 3 : Write '1' to Disable interrupt for CROSS event */ #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event UP */ +/* Bit 2 : Write '1' to Disable interrupt for UP event */ #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event DOWN */ +/* Bit 1 : Write '1' to Disable interrupt for DOWN event */ #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event READY */ +/* Bit 0 : Write '1' to Disable interrupt for READY event */ #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -2709,119 +2070,83 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Comparator hysteresis enable */ #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ -#define LPCOMP_HYST_HYST_Disabled (0UL) /*!< Comparator hysteresis disabled */ -#define LPCOMP_HYST_HYST_Enabled (1UL) /*!< Comparator hysteresis enabled */ +#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ +#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ /* Peripheral: MWU */ /* Description: Memory Watch Unit */ -/* Register: MWU_EVENTS_REGION_WA */ -/* Description: Description cluster: Write access to region n detected */ - -/* Bit 0 : Write access to region n detected */ -#define MWU_EVENTS_REGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ -#define MWU_EVENTS_REGION_WA_WA_Msk (0x1UL << MWU_EVENTS_REGION_WA_WA_Pos) /*!< Bit mask of WA field. */ -#define MWU_EVENTS_REGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ -#define MWU_EVENTS_REGION_WA_WA_Generated (1UL) /*!< Event generated */ - -/* Register: MWU_EVENTS_REGION_RA */ -/* Description: Description cluster: Read access to region n detected */ - -/* Bit 0 : Read access to region n detected */ -#define MWU_EVENTS_REGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ -#define MWU_EVENTS_REGION_RA_RA_Msk (0x1UL << MWU_EVENTS_REGION_RA_RA_Pos) /*!< Bit mask of RA field. */ -#define MWU_EVENTS_REGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ -#define MWU_EVENTS_REGION_RA_RA_Generated (1UL) /*!< Event generated */ - -/* Register: MWU_EVENTS_PREGION_WA */ -/* Description: Description cluster: Write access to peripheral region n detected */ - -/* Bit 0 : Write access to peripheral region n detected */ -#define MWU_EVENTS_PREGION_WA_WA_Pos (0UL) /*!< Position of WA field. */ -#define MWU_EVENTS_PREGION_WA_WA_Msk (0x1UL << MWU_EVENTS_PREGION_WA_WA_Pos) /*!< Bit mask of WA field. */ -#define MWU_EVENTS_PREGION_WA_WA_NotGenerated (0UL) /*!< Event not generated */ -#define MWU_EVENTS_PREGION_WA_WA_Generated (1UL) /*!< Event generated */ - -/* Register: MWU_EVENTS_PREGION_RA */ -/* Description: Description cluster: Read access to peripheral region n detected */ - -/* Bit 0 : Read access to peripheral region n detected */ -#define MWU_EVENTS_PREGION_RA_RA_Pos (0UL) /*!< Position of RA field. */ -#define MWU_EVENTS_PREGION_RA_RA_Msk (0x1UL << MWU_EVENTS_PREGION_RA_RA_Pos) /*!< Bit mask of RA field. */ -#define MWU_EVENTS_PREGION_RA_RA_NotGenerated (0UL) /*!< Event not generated */ -#define MWU_EVENTS_PREGION_RA_RA_Generated (1UL) /*!< Event generated */ - /* Register: MWU_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ +/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ +/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ +/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ +/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event REGION3RA */ +/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event REGION3WA */ +/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event REGION2RA */ +/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event REGION2WA */ +/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event REGION1RA */ +/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event REGION1WA */ +/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event REGION0RA */ +/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event REGION0WA */ +/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ @@ -2830,84 +2155,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ +/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ +/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ +/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ +/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ +/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ +/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ +/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ +/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ +/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ +/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ +/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ +/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -2917,84 +2242,84 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: MWU_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ +/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ +/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ +/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ +/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ +/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ +/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ +/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ +/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ +/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ +/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ +/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ +/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3002,161 +2327,161 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_NMIEN */ -/* Description: Enable or disable interrupt */ +/* Description: Enable or disable non-maskable interrupt */ -/* Bit 27 : Enable or disable interrupt for event PREGION1RA */ +/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 26 : Enable or disable interrupt for event PREGION1WA */ +/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for event PREGION0RA */ +/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 24 : Enable or disable interrupt for event PREGION0WA */ +/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event REGION3RA */ +/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event REGION3WA */ +/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event REGION2RA */ +/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event REGION2WA */ +/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event REGION1RA */ +/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event REGION1WA */ +/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event REGION0RA */ +/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event REGION0WA */ +/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ /* Register: MWU_NMIENSET */ -/* Description: Enable interrupt */ +/* Description: Enable non-maskable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for event PREGION1RA */ +/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ -/* Bit 26 : Write '1' to enable interrupt for event PREGION1WA */ +/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for event PREGION0RA */ +/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ -/* Bit 24 : Write '1' to enable interrupt for event PREGION0WA */ +/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event REGION3RA */ +/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event REGION3WA */ +/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event REGION2RA */ +/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event REGION2WA */ +/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event REGION1RA */ +/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event REGION1WA */ +/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event REGION0RA */ +/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event REGION0WA */ +/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3164,86 +2489,86 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ /* Register: MWU_NMIENCLR */ -/* Description: Disable interrupt */ +/* Description: Disable non-maskable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for event PREGION1RA */ +/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 26 : Write '1' to disable interrupt for event PREGION1WA */ +/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for event PREGION0RA */ +/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 24 : Write '1' to disable interrupt for event PREGION0WA */ +/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event REGION3RA */ +/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event REGION3WA */ +/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event REGION2RA */ +/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event REGION2WA */ +/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event REGION1RA */ +/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event REGION1WA */ +/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event REGION0RA */ +/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event REGION0WA */ +/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ @@ -3251,390 +2576,390 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ /* Register: MWU_PERREGION_SUBSTATWA */ -/* Description: Description cluster: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ -/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ -/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ /* Register: MWU_PERREGION_SUBSTATRA */ -/* Description: Description cluster: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching */ +/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ -/* Bit 31 : Subregion 31 in region n (write '1' to clear) */ +/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 30 : Subregion 30 in region n (write '1' to clear) */ +/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 29 : Subregion 29 in region n (write '1' to clear) */ +/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 28 : Subregion 28 in region n (write '1' to clear) */ +/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 27 : Subregion 27 in region n (write '1' to clear) */ +/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 26 : Subregion 26 in region n (write '1' to clear) */ +/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 25 : Subregion 25 in region n (write '1' to clear) */ +/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 24 : Subregion 24 in region n (write '1' to clear) */ +/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 23 : Subregion 23 in region n (write '1' to clear) */ +/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 22 : Subregion 22 in region n (write '1' to clear) */ +/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 21 : Subregion 21 in region n (write '1' to clear) */ +/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 20 : Subregion 20 in region n (write '1' to clear) */ +/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 19 : Subregion 19 in region n (write '1' to clear) */ +/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 18 : Subregion 18 in region n (write '1' to clear) */ +/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 17 : Subregion 17 in region n (write '1' to clear) */ +/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 16 : Subregion 16 in region n (write '1' to clear) */ +/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 15 : Subregion 15 in region n (write '1' to clear) */ +/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 14 : Subregion 14 in region n (write '1' to clear) */ +/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 13 : Subregion 13 in region n (write '1' to clear) */ +/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 12 : Subregion 12 in region n (write '1' to clear) */ +/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 11 : Subregion 11 in region n (write '1' to clear) */ +/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 10 : Subregion 10 in region n (write '1' to clear) */ +/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 9 : Subregion 9 in region n (write '1' to clear) */ +/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 8 : Subregion 8 in region n (write '1' to clear) */ +/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 7 : Subregion 7 in region n (write '1' to clear) */ +/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 6 : Subregion 6 in region n (write '1' to clear) */ +/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 5 : Subregion 5 in region n (write '1' to clear) */ +/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 4 : Subregion 4 in region n (write '1' to clear) */ +/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 3 : Subregion 3 in region n (write '1' to clear) */ +/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 2 : Subregion 2 in region n (write '1' to clear) */ +/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 1 : Subregion 1 in region n (write '1' to clear) */ +/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ -/* Bit 0 : Subregion 0 in region n (write '1' to clear) */ +/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ @@ -3890,35 +3215,35 @@ POSSIBILITY OF SUCH DAMAGE. #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ /* Register: MWU_REGION_START */ -/* Description: Description cluster: Start address for region n */ +/* Description: Description cluster[0]: Start address for region 0 */ /* Bits 31..0 : Start address for region */ #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_REGION_END */ -/* Description: Description cluster: End address of region n */ +/* Description: Description cluster[0]: End address of region 0 */ /* Bits 31..0 : End address of region. */ #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_START */ -/* Description: Description cluster: Reserved for future use */ +/* Description: Description cluster[0]: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ /* Register: MWU_PREGION_END */ -/* Description: Description cluster: Reserved for future use */ +/* Description: Description cluster[0]: Reserved for future use */ /* Bits 31..0 : Reserved for future use */ #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ /* Register: MWU_PREGION_SUBS */ -/* Description: Description cluster: Subregions of region n */ +/* Description: Description cluster[0]: Subregions of region 0 */ /* Bit 31 : Include or exclude subregion 31 in region */ #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ @@ -4116,213 +3441,22 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: NFCT */ /* Description: NFC-A compatible radio */ -/* Register: NFCT_TASKS_ACTIVATE */ -/* Description: Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ - -/* Bit 0 : Activate NFCT peripheral for incoming and outgoing frames, change state to activated */ -#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ -#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ -#define NFCT_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_TASKS_DISABLE */ -/* Description: Disable NFCT peripheral */ - -/* Bit 0 : Disable NFCT peripheral */ -#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ -#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << NFCT_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ -#define NFCT_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_TASKS_SENSE */ -/* Description: Enable NFC sense field mode, change state to sense mode */ - -/* Bit 0 : Enable NFC sense field mode, change state to sense mode */ -#define NFCT_TASKS_SENSE_TASKS_SENSE_Pos (0UL) /*!< Position of TASKS_SENSE field. */ -#define NFCT_TASKS_SENSE_TASKS_SENSE_Msk (0x1UL << NFCT_TASKS_SENSE_TASKS_SENSE_Pos) /*!< Bit mask of TASKS_SENSE field. */ -#define NFCT_TASKS_SENSE_TASKS_SENSE_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_TASKS_STARTTX */ -/* Description: Start transmission of an outgoing frame, change state to transmit */ - -/* Bit 0 : Start transmission of an outgoing frame, change state to transmit */ -#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ -#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << NFCT_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define NFCT_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_TASKS_ENABLERXDATA */ -/* Description: Initializes the EasyDMA for receive. */ - -/* Bit 0 : Initializes the EasyDMA for receive. */ -#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos (0UL) /*!< Position of TASKS_ENABLERXDATA field. */ -#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Msk (0x1UL << NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Pos) /*!< Bit mask of TASKS_ENABLERXDATA field. */ -#define NFCT_TASKS_ENABLERXDATA_TASKS_ENABLERXDATA_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_TASKS_GOIDLE */ -/* Description: Force state machine to IDLE state */ - -/* Bit 0 : Force state machine to IDLE state */ -#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos (0UL) /*!< Position of TASKS_GOIDLE field. */ -#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Msk (0x1UL << NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Pos) /*!< Bit mask of TASKS_GOIDLE field. */ -#define NFCT_TASKS_GOIDLE_TASKS_GOIDLE_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_TASKS_GOSLEEP */ -/* Description: Force state machine to SLEEP_A state */ - -/* Bit 0 : Force state machine to SLEEP_A state */ -#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos (0UL) /*!< Position of TASKS_GOSLEEP field. */ -#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Msk (0x1UL << NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Pos) /*!< Bit mask of TASKS_GOSLEEP field. */ -#define NFCT_TASKS_GOSLEEP_TASKS_GOSLEEP_Trigger (1UL) /*!< Trigger task */ - -/* Register: NFCT_EVENTS_READY */ -/* Description: The NFCT peripheral is ready to receive and send frames */ - -/* Bit 0 : The NFCT peripheral is ready to receive and send frames */ -#define NFCT_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ -#define NFCT_EVENTS_READY_EVENTS_READY_Msk (0x1UL << NFCT_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ -#define NFCT_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_FIELDDETECTED */ -/* Description: Remote NFC field detected */ - -/* Bit 0 : Remote NFC field detected */ -#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos (0UL) /*!< Position of EVENTS_FIELDDETECTED field. */ -#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Msk (0x1UL << NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Pos) /*!< Bit mask of EVENTS_FIELDDETECTED field. */ -#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_FIELDDETECTED_EVENTS_FIELDDETECTED_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_FIELDLOST */ -/* Description: Remote NFC field lost */ - -/* Bit 0 : Remote NFC field lost */ -#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos (0UL) /*!< Position of EVENTS_FIELDLOST field. */ -#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Msk (0x1UL << NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Pos) /*!< Bit mask of EVENTS_FIELDLOST field. */ -#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_FIELDLOST_EVENTS_FIELDLOST_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_TXFRAMESTART */ -/* Description: Marks the start of the first symbol of a transmitted frame */ - -/* Bit 0 : Marks the start of the first symbol of a transmitted frame */ -#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_TXFRAMESTART field. */ -#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Pos) /*!< Bit mask of EVENTS_TXFRAMESTART field. */ -#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_TXFRAMESTART_EVENTS_TXFRAMESTART_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_TXFRAMEEND */ -/* Description: Marks the end of the last transmitted on-air symbol of a frame */ - -/* Bit 0 : Marks the end of the last transmitted on-air symbol of a frame */ -#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_TXFRAMEEND field. */ -#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Pos) /*!< Bit mask of EVENTS_TXFRAMEEND field. */ -#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_TXFRAMEEND_EVENTS_TXFRAMEEND_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_RXFRAMESTART */ -/* Description: Marks the end of the first symbol of a received frame */ - -/* Bit 0 : Marks the end of the first symbol of a received frame */ -#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos (0UL) /*!< Position of EVENTS_RXFRAMESTART field. */ -#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Msk (0x1UL << NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Pos) /*!< Bit mask of EVENTS_RXFRAMESTART field. */ -#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_RXFRAMESTART_EVENTS_RXFRAMESTART_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_RXFRAMEEND */ -/* Description: Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ - -/* Bit 0 : Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer */ -#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos (0UL) /*!< Position of EVENTS_RXFRAMEEND field. */ -#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Msk (0x1UL << NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Pos) /*!< Bit mask of EVENTS_RXFRAMEEND field. */ -#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_RXFRAMEEND_EVENTS_RXFRAMEEND_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_ERROR */ -/* Description: NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ - -/* Bit 0 : NFC error reported. The ERRORSTATUS register contains details on the source of the error. */ -#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << NFCT_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define NFCT_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_RXERROR */ -/* Description: NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ - -/* Bit 0 : NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. */ -#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos (0UL) /*!< Position of EVENTS_RXERROR field. */ -#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Msk (0x1UL << NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Pos) /*!< Bit mask of EVENTS_RXERROR field. */ -#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_RXERROR_EVENTS_RXERROR_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_ENDRX */ -/* Description: RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ - -/* Bit 0 : RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */ -#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ -#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_ENDTX */ -/* Description: Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ - -/* Bit 0 : Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer */ -#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ -#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ -#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_AUTOCOLRESSTARTED */ -/* Description: Auto collision resolution process has started */ - -/* Bit 0 : Auto collision resolution process has started */ -#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos (0UL) /*!< Position of EVENTS_AUTOCOLRESSTARTED field. */ -#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of EVENTS_AUTOCOLRESSTARTED field. */ -#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_AUTOCOLRESSTARTED_EVENTS_AUTOCOLRESSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_COLLISION */ -/* Description: NFC auto collision resolution error reported. */ - -/* Bit 0 : NFC auto collision resolution error reported. */ -#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos (0UL) /*!< Position of EVENTS_COLLISION field. */ -#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Msk (0x1UL << NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Pos) /*!< Bit mask of EVENTS_COLLISION field. */ -#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_COLLISION_EVENTS_COLLISION_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_SELECTED */ -/* Description: NFC auto collision resolution successfully completed */ - -/* Bit 0 : NFC auto collision resolution successfully completed */ -#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos (0UL) /*!< Position of EVENTS_SELECTED field. */ -#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Msk (0x1UL << NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Pos) /*!< Bit mask of EVENTS_SELECTED field. */ -#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_SELECTED_EVENTS_SELECTED_Generated (1UL) /*!< Event generated */ - -/* Register: NFCT_EVENTS_STARTED */ -/* Description: EasyDMA is ready to receive or send frames. */ - -/* Bit 0 : EasyDMA is ready to receive or send frames. */ -#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ -#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << NFCT_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define NFCT_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define NFCT_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ - /* Register: NFCT_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 5 : Shortcut between event TXFRAMEEND and task ENABLERXDATA */ +/* Bit 5 : Shortcut between TXFRAMEEND event and ENABLERXDATA task */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos (5UL) /*!< Position of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Msk (0x1UL << NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Pos) /*!< Bit mask of TXFRAMEEND_ENABLERXDATA field. */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_TXFRAMEEND_ENABLERXDATA_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event FIELDLOST and task SENSE */ +/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event FIELDDETECTED and task ACTIVATE */ +/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ @@ -4331,91 +3465,91 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 20 : Enable or disable interrupt for event STARTED */ +/* Bit 20 : Enable or disable interrupt for STARTED event */ #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for event SELECTED */ +/* Bit 19 : Enable or disable interrupt for SELECTED event */ #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for event COLLISION */ +/* Bit 18 : Enable or disable interrupt for COLLISION event */ #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for event AUTOCOLRESSTARTED */ +/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for event ENDTX */ +/* Bit 12 : Enable or disable interrupt for ENDTX event */ #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for event ENDRX */ +/* Bit 11 : Enable or disable interrupt for ENDRX event */ #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for event RXERROR */ +/* Bit 10 : Enable or disable interrupt for RXERROR event */ #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event ERROR */ +/* Bit 7 : Enable or disable interrupt for ERROR event */ #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event RXFRAMEEND */ +/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event RXFRAMESTART */ +/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event TXFRAMEEND */ +/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event TXFRAMESTART */ +/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event FIELDLOST */ +/* Bit 2 : Enable or disable interrupt for FIELDLOST event */ #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event FIELDDETECTED */ +/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event READY */ +/* Bit 0 : Enable or disable interrupt for READY event */ #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -4424,105 +3558,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 20 : Write '1' to enable interrupt for event STARTED */ +/* Bit 20 : Write '1' to Enable interrupt for STARTED event */ #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event SELECTED */ +/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event COLLISION */ +/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for event AUTOCOLRESSTARTED */ +/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for event ENDTX */ +/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for event ENDRX */ +/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for event RXERROR */ +/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event ERROR */ +/* Bit 7 : Write '1' to Enable interrupt for ERROR event */ #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event RXFRAMEEND */ +/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event RXFRAMESTART */ +/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event TXFRAMEEND */ +/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event TXFRAMESTART */ +/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event FIELDLOST */ +/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event FIELDDETECTED */ +/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event READY */ +/* Bit 0 : Write '1' to Enable interrupt for READY event */ #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4532,105 +3666,105 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 20 : Write '1' to disable interrupt for event STARTED */ +/* Bit 20 : Write '1' to Disable interrupt for STARTED event */ #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event SELECTED */ +/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event COLLISION */ +/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for event AUTOCOLRESSTARTED */ +/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for event ENDTX */ +/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for event ENDRX */ +/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for event RXERROR */ +/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event ERROR */ +/* Bit 7 : Write '1' to Disable interrupt for ERROR event */ #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event RXFRAMEEND */ +/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event RXFRAMESTART */ +/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event TXFRAMEEND */ +/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event TXFRAMESTART */ +/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event FIELDLOST */ +/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event FIELDDETECTED */ +/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event READY */ +/* Bit 0 : Write '1' to Disable interrupt for READY event */ #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -4678,17 +3812,6 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_NFCTAGSTATE_NFCTAGSTATE_FrameDelay (5UL) /*!< FrameDelay */ #define NFCT_NFCTAGSTATE_NFCTAGSTATE_Transmit (6UL) /*!< Transmit */ -/* Register: NFCT_SLEEPSTATE */ -/* Description: Sleep state during automatic collision resolution */ - -/* Bit 0 : Reflects the sleep state during automatic collision resolution. Set to IDLE - by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a - GOSLEEP task. */ -#define NFCT_SLEEPSTATE_SLEEPSTATE_Pos (0UL) /*!< Position of SLEEPSTATE field. */ -#define NFCT_SLEEPSTATE_SLEEPSTATE_Msk (0x1UL << NFCT_SLEEPSTATE_SLEEPSTATE_Pos) /*!< Bit mask of SLEEPSTATE field. */ -#define NFCT_SLEEPSTATE_SLEEPSTATE_Idle (0UL) /*!< State is IDLE. */ -#define NFCT_SLEEPSTATE_SLEEPSTATE_SleepA (1UL) /*!< State is SLEEP_A. */ - /* Register: NFCT_FIELDPRESENT */ /* Description: Indicates the presence or not of a valid field */ @@ -4714,9 +3837,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: NFCT_FRAMEDELAYMAX */ /* Description: Maximum frame delay */ -/* Bits 19..0 : Maximum frame delay in number of 13.56 MHz clocks */ +/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ -#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ +#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ /* Register: NFCT_FRAMEDELAYMODE */ /* Description: Configuration register for the Frame Delay Timer */ @@ -4893,7 +4016,7 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ -/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ +/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ @@ -4939,15 +4062,6 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ -/* Register: NVMC_READYNEXT */ -/* Description: Ready flag */ - -/* Bit 0 : NVMC can accept a new write operation */ -#define NVMC_READYNEXT_READYNEXT_Pos (0UL) /*!< Position of READYNEXT field. */ -#define NVMC_READYNEXT_READYNEXT_Msk (0x1UL << NVMC_READYNEXT_READYNEXT_Pos) /*!< Bit mask of READYNEXT field. */ -#define NVMC_READYNEXT_READYNEXT_Busy (0UL) /*!< NVMC cannot accept any write operation */ -#define NVMC_READYNEXT_READYNEXT_Ready (1UL) /*!< NVMC is ready */ - /* Register: NVMC_CONFIG */ /* Description: Configuration register */ @@ -4955,20 +4069,20 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ -#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write enabled */ +#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ /* Register: NVMC_ERASEPAGE */ -/* Description: Register for erasing a page in code area */ +/* Description: Register for erasing a page in Code area */ -/* Bits 31..0 : Register for starting erase of a page in code area */ +/* Bits 31..0 : Register for starting erase of a page in Code area */ #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ /* Register: NVMC_ERASEPCR1 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ -/* Bits 31..0 : Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ @@ -4982,37 +4096,23 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ /* Register: NVMC_ERASEPCR0 */ -/* Description: Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. */ +/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ -/* Bits 31..0 : Register for starting erase of a page in code area. Equivalent to ERASEPAGE. */ +/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ /* Register: NVMC_ERASEUICR */ -/* Description: Register for erasing user information configuration registers */ +/* Description: Register for erasing User Information Configuration Registers */ -/* Bit 0 : Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ +/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. */ #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ -/* Register: NVMC_ERASEPAGEPARTIAL */ -/* Description: Register for partial erase of a page in code area */ - -/* Bits 31..0 : Register for starting partial erase of a page in code area */ -#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos (0UL) /*!< Position of ERASEPAGEPARTIAL field. */ -#define NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGEPARTIAL_ERASEPAGEPARTIAL_Pos) /*!< Bit mask of ERASEPAGEPARTIAL field. */ - -/* Register: NVMC_ERASEPAGEPARTIALCFG */ -/* Description: Register for partial erase configuration */ - -/* Bits 6..0 : Duration of the partial erase in milliseconds */ -#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos (0UL) /*!< Position of DURATION field. */ -#define NVMC_ERASEPAGEPARTIALCFG_DURATION_Msk (0x7FUL << NVMC_ERASEPAGEPARTIALCFG_DURATION_Pos) /*!< Bit mask of DURATION field. */ - /* Register: NVMC_ICACHECNF */ -/* Description: I-code cache configuration register. */ +/* Description: I-Code cache configuration register. */ /* Bit 8 : Cache profiling enable */ #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ @@ -5027,14 +4127,14 @@ POSSIBILITY OF SUCH DAMAGE. #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ /* Register: NVMC_IHIT */ -/* Description: I-code cache hit counter. */ +/* Description: I-Code cache hit counter. */ /* Bits 31..0 : Number of cache hits */ #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ /* Register: NVMC_IMISS */ -/* Description: I-code cache miss counter. */ +/* Description: I-Code cache miss counter. */ /* Bits 31..0 : Number of cache misses */ #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ @@ -6742,7 +5842,7 @@ POSSIBILITY OF SUCH DAMAGE. #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ /* Register: GPIO_PIN_CNF */ -/* Description: Description collection: Configuration of GPIO pins */ +/* Description: Description collection[0]: Configuration of GPIO pins */ /* Bits 17..16 : Pin sensing mechanism */ #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ @@ -6786,65 +5886,22 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: PDM */ /* Description: Pulse Density Modulation (Digital Microphone) Interface */ -/* Register: PDM_TASKS_START */ -/* Description: Starts continuous PDM transfer */ - -/* Bit 0 : Starts continuous PDM transfer */ -#define PDM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define PDM_TASKS_START_TASKS_START_Msk (0x1UL << PDM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define PDM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: PDM_TASKS_STOP */ -/* Description: Stops PDM transfer */ - -/* Bit 0 : Stops PDM transfer */ -#define PDM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define PDM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PDM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define PDM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: PDM_EVENTS_STARTED */ -/* Description: PDM transfer has started */ - -/* Bit 0 : PDM transfer has started */ -#define PDM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ -#define PDM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << PDM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define PDM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define PDM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ - -/* Register: PDM_EVENTS_STOPPED */ -/* Description: PDM transfer has finished */ - -/* Bit 0 : PDM transfer has finished */ -#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PDM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define PDM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: PDM_EVENTS_END */ -/* Description: The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ - -/* Bit 0 : The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM */ -#define PDM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ -#define PDM_EVENTS_END_EVENTS_END_Msk (0x1UL << PDM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define PDM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define PDM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ - /* Register: PDM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 2 : Enable or disable interrupt for event END */ +/* Bit 2 : Enable or disable interrupt for END event */ #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event STOPPED */ +/* Bit 1 : Enable or disable interrupt for STOPPED event */ #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event STARTED */ +/* Bit 0 : Enable or disable interrupt for STARTED event */ #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -6853,21 +5910,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for event END */ +/* Bit 2 : Write '1' to Enable interrupt for END event */ #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6877,21 +5934,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PDM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for event END */ +/* Bit 2 : Write '1' to Disable interrupt for END event */ #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -6942,17 +5999,17 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ +#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ /* Register: PDM_GAINR */ /* Description: Right output gain adjustment */ -/* Bits 6..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ +/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ -#define PDM_GAINR_GAINR_Msk (0x7FUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ +#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ -#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment */ +#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ /* Register: PDM_RATIO */ @@ -6973,9 +6030,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define PDM_PSEL_CLK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define PDM_PSEL_CLK_PORT_Msk (0x1UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ +#define PDM_PSEL_CLK_PORT_Msk (0x3UL << PDM_PSEL_CLK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -6990,9 +6047,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define PDM_PSEL_DIN_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define PDM_PSEL_DIN_PORT_Msk (0x1UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ +#define PDM_PSEL_DIN_PORT_Msk (0x3UL << PDM_PSEL_DIN_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -7016,115 +6073,45 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: POWER */ /* Description: Power control */ -/* Register: POWER_TASKS_CONSTLAT */ -/* Description: Enable Constant Latency mode */ - -/* Bit 0 : Enable Constant Latency mode */ -#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos (0UL) /*!< Position of TASKS_CONSTLAT field. */ -#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Msk (0x1UL << POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Pos) /*!< Bit mask of TASKS_CONSTLAT field. */ -#define POWER_TASKS_CONSTLAT_TASKS_CONSTLAT_Trigger (1UL) /*!< Trigger task */ - -/* Register: POWER_TASKS_LOWPWR */ -/* Description: Enable Low-power mode (variable latency) */ - -/* Bit 0 : Enable Low-power mode (variable latency) */ -#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos (0UL) /*!< Position of TASKS_LOWPWR field. */ -#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Msk (0x1UL << POWER_TASKS_LOWPWR_TASKS_LOWPWR_Pos) /*!< Bit mask of TASKS_LOWPWR field. */ -#define POWER_TASKS_LOWPWR_TASKS_LOWPWR_Trigger (1UL) /*!< Trigger task */ - -/* Register: POWER_EVENTS_POFWARN */ -/* Description: Power failure warning */ - -/* Bit 0 : Power failure warning */ -#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos (0UL) /*!< Position of EVENTS_POFWARN field. */ -#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Msk (0x1UL << POWER_EVENTS_POFWARN_EVENTS_POFWARN_Pos) /*!< Bit mask of EVENTS_POFWARN field. */ -#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_POFWARN_EVENTS_POFWARN_Generated (1UL) /*!< Event generated */ - -/* Register: POWER_EVENTS_SLEEPENTER */ -/* Description: CPU entered WFI/WFE sleep */ - -/* Bit 0 : CPU entered WFI/WFE sleep */ -#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos (0UL) /*!< Position of EVENTS_SLEEPENTER field. */ -#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Msk (0x1UL << POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Pos) /*!< Bit mask of EVENTS_SLEEPENTER field. */ -#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_SLEEPENTER_EVENTS_SLEEPENTER_Generated (1UL) /*!< Event generated */ - -/* Register: POWER_EVENTS_SLEEPEXIT */ -/* Description: CPU exited WFI/WFE sleep */ - -/* Bit 0 : CPU exited WFI/WFE sleep */ -#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos (0UL) /*!< Position of EVENTS_SLEEPEXIT field. */ -#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Msk (0x1UL << POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Pos) /*!< Bit mask of EVENTS_SLEEPEXIT field. */ -#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_SLEEPEXIT_EVENTS_SLEEPEXIT_Generated (1UL) /*!< Event generated */ - -/* Register: POWER_EVENTS_USBDETECTED */ -/* Description: Voltage supply detected on VBUS */ - -/* Bit 0 : Voltage supply detected on VBUS */ -#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos (0UL) /*!< Position of EVENTS_USBDETECTED field. */ -#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Msk (0x1UL << POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Pos) /*!< Bit mask of EVENTS_USBDETECTED field. */ -#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_USBDETECTED_EVENTS_USBDETECTED_Generated (1UL) /*!< Event generated */ - -/* Register: POWER_EVENTS_USBREMOVED */ -/* Description: Voltage supply removed from VBUS */ - -/* Bit 0 : Voltage supply removed from VBUS */ -#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos (0UL) /*!< Position of EVENTS_USBREMOVED field. */ -#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Msk (0x1UL << POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Pos) /*!< Bit mask of EVENTS_USBREMOVED field. */ -#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_USBREMOVED_EVENTS_USBREMOVED_Generated (1UL) /*!< Event generated */ - -/* Register: POWER_EVENTS_USBPWRRDY */ -/* Description: USB 3.3 V supply ready */ - -/* Bit 0 : USB 3.3 V supply ready */ -#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos (0UL) /*!< Position of EVENTS_USBPWRRDY field. */ -#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Msk (0x1UL << POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Pos) /*!< Bit mask of EVENTS_USBPWRRDY field. */ -#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_NotGenerated (0UL) /*!< Event not generated */ -#define POWER_EVENTS_USBPWRRDY_EVENTS_USBPWRRDY_Generated (1UL) /*!< Event generated */ - /* Register: POWER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 9 : Write '1' to enable interrupt for event USBPWRRDY */ +/* Bit 9 : Write '1' to Enable interrupt for USBPWRRDY event */ #define POWER_INTENSET_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Msk (0x1UL << POWER_INTENSET_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENSET_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBPWRRDY_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for event USBREMOVED */ +/* Bit 8 : Write '1' to Enable interrupt for USBREMOVED event */ #define POWER_INTENSET_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Msk (0x1UL << POWER_INTENSET_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENSET_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBREMOVED_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event USBDETECTED */ +/* Bit 7 : Write '1' to Enable interrupt for USBDETECTED event */ #define POWER_INTENSET_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Msk (0x1UL << POWER_INTENSET_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENSET_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_USBDETECTED_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event SLEEPEXIT */ +/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event SLEEPENTER */ +/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event POFWARN */ +/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -7134,42 +6121,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 9 : Write '1' to disable interrupt for event USBPWRRDY */ +/* Bit 9 : Write '1' to Disable interrupt for USBPWRRDY event */ #define POWER_INTENCLR_USBPWRRDY_Pos (9UL) /*!< Position of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Msk (0x1UL << POWER_INTENCLR_USBPWRRDY_Pos) /*!< Bit mask of USBPWRRDY field. */ #define POWER_INTENCLR_USBPWRRDY_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBPWRRDY_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBPWRRDY_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for event USBREMOVED */ +/* Bit 8 : Write '1' to Disable interrupt for USBREMOVED event */ #define POWER_INTENCLR_USBREMOVED_Pos (8UL) /*!< Position of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Msk (0x1UL << POWER_INTENCLR_USBREMOVED_Pos) /*!< Bit mask of USBREMOVED field. */ #define POWER_INTENCLR_USBREMOVED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBREMOVED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBREMOVED_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event USBDETECTED */ +/* Bit 7 : Write '1' to Disable interrupt for USBDETECTED event */ #define POWER_INTENCLR_USBDETECTED_Pos (7UL) /*!< Position of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Msk (0x1UL << POWER_INTENCLR_USBDETECTED_Pos) /*!< Bit mask of USBDETECTED field. */ #define POWER_INTENCLR_USBDETECTED_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_USBDETECTED_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_USBDETECTED_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event SLEEPEXIT */ +/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event SLEEPENTER */ +/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event POFWARN */ +/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ @@ -7179,7 +6166,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: POWER_RESETREAS */ /* Description: Reset reason */ -/* Bit 20 : Reset due to wake up from System OFF mode by VBUS rising into valid range */ +/* Bit 20 : Reset due to wake up from System OFF mode by Vbus rising into valid range */ #define POWER_RESETREAS_VBUS_Pos (20UL) /*!< Position of VBUS field. */ #define POWER_RESETREAS_VBUS_Msk (0x1UL << POWER_RESETREAS_VBUS_Pos) /*!< Bit mask of VBUS field. */ #define POWER_RESETREAS_VBUS_NotDetected (0UL) /*!< Not detected */ @@ -7234,7 +6221,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ /* Register: POWER_RAMSTATUS */ -/* Description: Deprecated register - RAM status register */ +/* Description: Deprecated register - RAM status register */ /* Bit 3 : RAM block 3 is on or off/powering up */ #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ @@ -7284,9 +6271,9 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ /* Register: POWER_POFCON */ -/* Description: Power-fail comparator configuration */ +/* Description: Power failure comparator configuration */ -/* Bits 11..8 : Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). */ +/* Bits 11..8 : Power failure comparator threshold setting for voltage supply on VDDH */ #define POWER_POFCON_THRESHOLDVDDH_Pos (8UL) /*!< Position of THRESHOLDVDDH field. */ #define POWER_POFCON_THRESHOLDVDDH_Msk (0xFUL << POWER_POFCON_THRESHOLDVDDH_Pos) /*!< Bit mask of THRESHOLDVDDH field. */ #define POWER_POFCON_THRESHOLDVDDH_V27 (0UL) /*!< Set threshold to 2.7 V */ @@ -7306,7 +6293,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_POFCON_THRESHOLDVDDH_V41 (14UL) /*!< Set threshold to 4.1 V */ #define POWER_POFCON_THRESHOLDVDDH_V42 (15UL) /*!< Set threshold to 4.2 V */ -/* Bits 4..1 : Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. */ +/* Bits 4..1 : Power failure comparator threshold setting */ #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ @@ -7322,7 +6309,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ -/* Bit 0 : Enable or disable power failure warning */ +/* Bit 0 : Enable or disable power failure comparator */ #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ @@ -7343,7 +6330,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ /* Register: POWER_DCDCEN */ -/* Description: Enable DC/DC converter for REG1 stage */ +/* Description: Enable DC/DC converter for REG1 stage. */ /* Bit 0 : Enable DC/DC converter for REG1 stage. */ #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ @@ -7352,7 +6339,7 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ /* Register: POWER_DCDCEN0 */ -/* Description: Enable DC/DC converter for REG0 stage */ +/* Description: Enable DC/DC converter for REG0 stage. */ /* Bit 0 : Enable DC/DC converter for REG0 stage. */ #define POWER_DCDCEN0_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ @@ -7370,202 +6357,202 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_MAINREGSTATUS_MAINREGSTATUS_High (1UL) /*!< High voltage mode. Voltage supplied on VDDH. */ /* Register: POWER_RAM_POWER */ -/* Description: Description cluster: RAMn power control register */ +/* Description: Description cluster[0]: RAM0 power control register */ -/* Bit 31 : Keep retention on RAM section S15 when RAM section is off */ +/* Bit 31 : Keep retention on RAM section S15 when RAM section is in OFF */ #define POWER_RAM_POWER_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ #define POWER_RAM_POWER_S15RETENTION_Msk (0x1UL << POWER_RAM_POWER_S15RETENTION_Pos) /*!< Bit mask of S15RETENTION field. */ #define POWER_RAM_POWER_S15RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S15RETENTION_On (1UL) /*!< On */ -/* Bit 30 : Keep retention on RAM section S14 when RAM section is off */ +/* Bit 30 : Keep retention on RAM section S14 when RAM section is in OFF */ #define POWER_RAM_POWER_S14RETENTION_Pos (30UL) /*!< Position of S14RETENTION field. */ #define POWER_RAM_POWER_S14RETENTION_Msk (0x1UL << POWER_RAM_POWER_S14RETENTION_Pos) /*!< Bit mask of S14RETENTION field. */ #define POWER_RAM_POWER_S14RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S14RETENTION_On (1UL) /*!< On */ -/* Bit 29 : Keep retention on RAM section S13 when RAM section is off */ +/* Bit 29 : Keep retention on RAM section S13 when RAM section is in OFF */ #define POWER_RAM_POWER_S13RETENTION_Pos (29UL) /*!< Position of S13RETENTION field. */ #define POWER_RAM_POWER_S13RETENTION_Msk (0x1UL << POWER_RAM_POWER_S13RETENTION_Pos) /*!< Bit mask of S13RETENTION field. */ #define POWER_RAM_POWER_S13RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S13RETENTION_On (1UL) /*!< On */ -/* Bit 28 : Keep retention on RAM section S12 when RAM section is off */ +/* Bit 28 : Keep retention on RAM section S12 when RAM section is in OFF */ #define POWER_RAM_POWER_S12RETENTION_Pos (28UL) /*!< Position of S12RETENTION field. */ #define POWER_RAM_POWER_S12RETENTION_Msk (0x1UL << POWER_RAM_POWER_S12RETENTION_Pos) /*!< Bit mask of S12RETENTION field. */ #define POWER_RAM_POWER_S12RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S12RETENTION_On (1UL) /*!< On */ -/* Bit 27 : Keep retention on RAM section S11 when RAM section is off */ +/* Bit 27 : Keep retention on RAM section S11 when RAM section is in OFF */ #define POWER_RAM_POWER_S11RETENTION_Pos (27UL) /*!< Position of S11RETENTION field. */ #define POWER_RAM_POWER_S11RETENTION_Msk (0x1UL << POWER_RAM_POWER_S11RETENTION_Pos) /*!< Bit mask of S11RETENTION field. */ #define POWER_RAM_POWER_S11RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S11RETENTION_On (1UL) /*!< On */ -/* Bit 26 : Keep retention on RAM section S10 when RAM section is off */ +/* Bit 26 : Keep retention on RAM section S10 when RAM section is in OFF */ #define POWER_RAM_POWER_S10RETENTION_Pos (26UL) /*!< Position of S10RETENTION field. */ #define POWER_RAM_POWER_S10RETENTION_Msk (0x1UL << POWER_RAM_POWER_S10RETENTION_Pos) /*!< Bit mask of S10RETENTION field. */ #define POWER_RAM_POWER_S10RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S10RETENTION_On (1UL) /*!< On */ -/* Bit 25 : Keep retention on RAM section S9 when RAM section is off */ +/* Bit 25 : Keep retention on RAM section S9 when RAM section is in OFF */ #define POWER_RAM_POWER_S9RETENTION_Pos (25UL) /*!< Position of S9RETENTION field. */ #define POWER_RAM_POWER_S9RETENTION_Msk (0x1UL << POWER_RAM_POWER_S9RETENTION_Pos) /*!< Bit mask of S9RETENTION field. */ #define POWER_RAM_POWER_S9RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S9RETENTION_On (1UL) /*!< On */ -/* Bit 24 : Keep retention on RAM section S8 when RAM section is off */ +/* Bit 24 : Keep retention on RAM section S8 when RAM section is in OFF */ #define POWER_RAM_POWER_S8RETENTION_Pos (24UL) /*!< Position of S8RETENTION field. */ #define POWER_RAM_POWER_S8RETENTION_Msk (0x1UL << POWER_RAM_POWER_S8RETENTION_Pos) /*!< Bit mask of S8RETENTION field. */ #define POWER_RAM_POWER_S8RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S8RETENTION_On (1UL) /*!< On */ -/* Bit 23 : Keep retention on RAM section S7 when RAM section is off */ +/* Bit 23 : Keep retention on RAM section S7 when RAM section is in OFF */ #define POWER_RAM_POWER_S7RETENTION_Pos (23UL) /*!< Position of S7RETENTION field. */ #define POWER_RAM_POWER_S7RETENTION_Msk (0x1UL << POWER_RAM_POWER_S7RETENTION_Pos) /*!< Bit mask of S7RETENTION field. */ #define POWER_RAM_POWER_S7RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S7RETENTION_On (1UL) /*!< On */ -/* Bit 22 : Keep retention on RAM section S6 when RAM section is off */ +/* Bit 22 : Keep retention on RAM section S6 when RAM section is in OFF */ #define POWER_RAM_POWER_S6RETENTION_Pos (22UL) /*!< Position of S6RETENTION field. */ #define POWER_RAM_POWER_S6RETENTION_Msk (0x1UL << POWER_RAM_POWER_S6RETENTION_Pos) /*!< Bit mask of S6RETENTION field. */ #define POWER_RAM_POWER_S6RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S6RETENTION_On (1UL) /*!< On */ -/* Bit 21 : Keep retention on RAM section S5 when RAM section is off */ +/* Bit 21 : Keep retention on RAM section S5 when RAM section is in OFF */ #define POWER_RAM_POWER_S5RETENTION_Pos (21UL) /*!< Position of S5RETENTION field. */ #define POWER_RAM_POWER_S5RETENTION_Msk (0x1UL << POWER_RAM_POWER_S5RETENTION_Pos) /*!< Bit mask of S5RETENTION field. */ #define POWER_RAM_POWER_S5RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S5RETENTION_On (1UL) /*!< On */ -/* Bit 20 : Keep retention on RAM section S4 when RAM section is off */ +/* Bit 20 : Keep retention on RAM section S4 when RAM section is in OFF */ #define POWER_RAM_POWER_S4RETENTION_Pos (20UL) /*!< Position of S4RETENTION field. */ #define POWER_RAM_POWER_S4RETENTION_Msk (0x1UL << POWER_RAM_POWER_S4RETENTION_Pos) /*!< Bit mask of S4RETENTION field. */ #define POWER_RAM_POWER_S4RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S4RETENTION_On (1UL) /*!< On */ -/* Bit 19 : Keep retention on RAM section S3 when RAM section is off */ +/* Bit 19 : Keep retention on RAM section S3 when RAM section is in OFF */ #define POWER_RAM_POWER_S3RETENTION_Pos (19UL) /*!< Position of S3RETENTION field. */ #define POWER_RAM_POWER_S3RETENTION_Msk (0x1UL << POWER_RAM_POWER_S3RETENTION_Pos) /*!< Bit mask of S3RETENTION field. */ #define POWER_RAM_POWER_S3RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S3RETENTION_On (1UL) /*!< On */ -/* Bit 18 : Keep retention on RAM section S2 when RAM section is off */ +/* Bit 18 : Keep retention on RAM section S2 when RAM section is in OFF */ #define POWER_RAM_POWER_S2RETENTION_Pos (18UL) /*!< Position of S2RETENTION field. */ #define POWER_RAM_POWER_S2RETENTION_Msk (0x1UL << POWER_RAM_POWER_S2RETENTION_Pos) /*!< Bit mask of S2RETENTION field. */ #define POWER_RAM_POWER_S2RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S2RETENTION_On (1UL) /*!< On */ -/* Bit 17 : Keep retention on RAM section S1 when RAM section is off */ +/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ -/* Bit 16 : Keep retention on RAM section S0 when RAM section is off */ +/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ -/* Bit 15 : Keep RAM section S15 on or off in System ON mode. */ +/* Bit 15 : Keep RAM section S15 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ #define POWER_RAM_POWER_S15POWER_Msk (0x1UL << POWER_RAM_POWER_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ #define POWER_RAM_POWER_S15POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S15POWER_On (1UL) /*!< On */ -/* Bit 14 : Keep RAM section S14 on or off in System ON mode. */ +/* Bit 14 : Keep RAM section S14 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ #define POWER_RAM_POWER_S14POWER_Msk (0x1UL << POWER_RAM_POWER_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ #define POWER_RAM_POWER_S14POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S14POWER_On (1UL) /*!< On */ -/* Bit 13 : Keep RAM section S13 on or off in System ON mode. */ +/* Bit 13 : Keep RAM section S13 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ #define POWER_RAM_POWER_S13POWER_Msk (0x1UL << POWER_RAM_POWER_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ #define POWER_RAM_POWER_S13POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S13POWER_On (1UL) /*!< On */ -/* Bit 12 : Keep RAM section S12 on or off in System ON mode. */ +/* Bit 12 : Keep RAM section S12 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ #define POWER_RAM_POWER_S12POWER_Msk (0x1UL << POWER_RAM_POWER_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ #define POWER_RAM_POWER_S12POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S12POWER_On (1UL) /*!< On */ -/* Bit 11 : Keep RAM section S11 on or off in System ON mode. */ +/* Bit 11 : Keep RAM section S11 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ #define POWER_RAM_POWER_S11POWER_Msk (0x1UL << POWER_RAM_POWER_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ #define POWER_RAM_POWER_S11POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S11POWER_On (1UL) /*!< On */ -/* Bit 10 : Keep RAM section S10 on or off in System ON mode. */ +/* Bit 10 : Keep RAM section S10 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ #define POWER_RAM_POWER_S10POWER_Msk (0x1UL << POWER_RAM_POWER_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ #define POWER_RAM_POWER_S10POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S10POWER_On (1UL) /*!< On */ -/* Bit 9 : Keep RAM section S9 on or off in System ON mode. */ +/* Bit 9 : Keep RAM section S9 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ #define POWER_RAM_POWER_S9POWER_Msk (0x1UL << POWER_RAM_POWER_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ #define POWER_RAM_POWER_S9POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S9POWER_On (1UL) /*!< On */ -/* Bit 8 : Keep RAM section S8 on or off in System ON mode. */ +/* Bit 8 : Keep RAM section S8 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ #define POWER_RAM_POWER_S8POWER_Msk (0x1UL << POWER_RAM_POWER_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ #define POWER_RAM_POWER_S8POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S8POWER_On (1UL) /*!< On */ -/* Bit 7 : Keep RAM section S7 on or off in System ON mode. */ +/* Bit 7 : Keep RAM section S7 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ #define POWER_RAM_POWER_S7POWER_Msk (0x1UL << POWER_RAM_POWER_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ #define POWER_RAM_POWER_S7POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S7POWER_On (1UL) /*!< On */ -/* Bit 6 : Keep RAM section S6 on or off in System ON mode. */ +/* Bit 6 : Keep RAM section S6 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ #define POWER_RAM_POWER_S6POWER_Msk (0x1UL << POWER_RAM_POWER_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ #define POWER_RAM_POWER_S6POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S6POWER_On (1UL) /*!< On */ -/* Bit 5 : Keep RAM section S5 on or off in System ON mode. */ +/* Bit 5 : Keep RAM section S5 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ #define POWER_RAM_POWER_S5POWER_Msk (0x1UL << POWER_RAM_POWER_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ #define POWER_RAM_POWER_S5POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S5POWER_On (1UL) /*!< On */ -/* Bit 4 : Keep RAM section S4 on or off in System ON mode. */ +/* Bit 4 : Keep RAM section S4 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ #define POWER_RAM_POWER_S4POWER_Msk (0x1UL << POWER_RAM_POWER_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ #define POWER_RAM_POWER_S4POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S4POWER_On (1UL) /*!< On */ -/* Bit 3 : Keep RAM section S3 on or off in System ON mode. */ +/* Bit 3 : Keep RAM section S3 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define POWER_RAM_POWER_S3POWER_Msk (0x1UL << POWER_RAM_POWER_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ #define POWER_RAM_POWER_S3POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S3POWER_On (1UL) /*!< On */ -/* Bit 2 : Keep RAM section S2 on or off in System ON mode. */ +/* Bit 2 : Keep RAM section S2 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define POWER_RAM_POWER_S2POWER_Msk (0x1UL << POWER_RAM_POWER_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ #define POWER_RAM_POWER_S2POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S2POWER_On (1UL) /*!< On */ -/* Bit 1 : Keep RAM section S1 on or off in System ON mode. */ +/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ -/* Bit 0 : Keep RAM section S0 on or off in System ON mode. */ +/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERSET */ -/* Description: Description cluster: RAMn power control set register */ +/* Description: Description cluster[0]: RAM0 power control set register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERSET_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7647,88 +6634,88 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ -/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ +/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ #define POWER_RAM_POWERSET_S15POWER_Msk (0x1UL << POWER_RAM_POWERSET_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ #define POWER_RAM_POWERSET_S15POWER_On (1UL) /*!< On */ -/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ +/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ #define POWER_RAM_POWERSET_S14POWER_Msk (0x1UL << POWER_RAM_POWERSET_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ #define POWER_RAM_POWERSET_S14POWER_On (1UL) /*!< On */ -/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ +/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ #define POWER_RAM_POWERSET_S13POWER_Msk (0x1UL << POWER_RAM_POWERSET_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ #define POWER_RAM_POWERSET_S13POWER_On (1UL) /*!< On */ -/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ +/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ #define POWER_RAM_POWERSET_S12POWER_Msk (0x1UL << POWER_RAM_POWERSET_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ #define POWER_RAM_POWERSET_S12POWER_On (1UL) /*!< On */ -/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ +/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ #define POWER_RAM_POWERSET_S11POWER_Msk (0x1UL << POWER_RAM_POWERSET_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ #define POWER_RAM_POWERSET_S11POWER_On (1UL) /*!< On */ -/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ +/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ #define POWER_RAM_POWERSET_S10POWER_Msk (0x1UL << POWER_RAM_POWERSET_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ #define POWER_RAM_POWERSET_S10POWER_On (1UL) /*!< On */ -/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ +/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ #define POWER_RAM_POWERSET_S9POWER_Msk (0x1UL << POWER_RAM_POWERSET_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ #define POWER_RAM_POWERSET_S9POWER_On (1UL) /*!< On */ -/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ +/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ #define POWER_RAM_POWERSET_S8POWER_Msk (0x1UL << POWER_RAM_POWERSET_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ #define POWER_RAM_POWERSET_S8POWER_On (1UL) /*!< On */ -/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ +/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ #define POWER_RAM_POWERSET_S7POWER_Msk (0x1UL << POWER_RAM_POWERSET_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ #define POWER_RAM_POWERSET_S7POWER_On (1UL) /*!< On */ -/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ +/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ #define POWER_RAM_POWERSET_S6POWER_Msk (0x1UL << POWER_RAM_POWERSET_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ #define POWER_RAM_POWERSET_S6POWER_On (1UL) /*!< On */ -/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ +/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ #define POWER_RAM_POWERSET_S5POWER_Msk (0x1UL << POWER_RAM_POWERSET_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ #define POWER_RAM_POWERSET_S5POWER_On (1UL) /*!< On */ -/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ +/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ #define POWER_RAM_POWERSET_S4POWER_Msk (0x1UL << POWER_RAM_POWERSET_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ #define POWER_RAM_POWERSET_S4POWER_On (1UL) /*!< On */ -/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ +/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define POWER_RAM_POWERSET_S3POWER_Msk (0x1UL << POWER_RAM_POWERSET_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ #define POWER_RAM_POWERSET_S3POWER_On (1UL) /*!< On */ -/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ +/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define POWER_RAM_POWERSET_S2POWER_Msk (0x1UL << POWER_RAM_POWERSET_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ #define POWER_RAM_POWERSET_S2POWER_On (1UL) /*!< On */ -/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ -/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ /* Register: POWER_RAM_POWERCLR */ -/* Description: Description cluster: RAMn power control clear register */ +/* Description: Description cluster[0]: RAM0 power control clear register */ /* Bit 31 : Keep retention on RAM section S15 when RAM section is switched off */ #define POWER_RAM_POWERCLR_S15RETENTION_Pos (31UL) /*!< Position of S15RETENTION field. */ @@ -7810,82 +6797,82 @@ POSSIBILITY OF SUCH DAMAGE. #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ -/* Bit 15 : Keep RAM section S15 of RAMn on or off in System ON mode */ +/* Bit 15 : Keep RAM section S15 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S15POWER_Pos (15UL) /*!< Position of S15POWER field. */ #define POWER_RAM_POWERCLR_S15POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S15POWER_Pos) /*!< Bit mask of S15POWER field. */ #define POWER_RAM_POWERCLR_S15POWER_Off (1UL) /*!< Off */ -/* Bit 14 : Keep RAM section S14 of RAMn on or off in System ON mode */ +/* Bit 14 : Keep RAM section S14 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S14POWER_Pos (14UL) /*!< Position of S14POWER field. */ #define POWER_RAM_POWERCLR_S14POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S14POWER_Pos) /*!< Bit mask of S14POWER field. */ #define POWER_RAM_POWERCLR_S14POWER_Off (1UL) /*!< Off */ -/* Bit 13 : Keep RAM section S13 of RAMn on or off in System ON mode */ +/* Bit 13 : Keep RAM section S13 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S13POWER_Pos (13UL) /*!< Position of S13POWER field. */ #define POWER_RAM_POWERCLR_S13POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S13POWER_Pos) /*!< Bit mask of S13POWER field. */ #define POWER_RAM_POWERCLR_S13POWER_Off (1UL) /*!< Off */ -/* Bit 12 : Keep RAM section S12 of RAMn on or off in System ON mode */ +/* Bit 12 : Keep RAM section S12 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S12POWER_Pos (12UL) /*!< Position of S12POWER field. */ #define POWER_RAM_POWERCLR_S12POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S12POWER_Pos) /*!< Bit mask of S12POWER field. */ #define POWER_RAM_POWERCLR_S12POWER_Off (1UL) /*!< Off */ -/* Bit 11 : Keep RAM section S11 of RAMn on or off in System ON mode */ +/* Bit 11 : Keep RAM section S11 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S11POWER_Pos (11UL) /*!< Position of S11POWER field. */ #define POWER_RAM_POWERCLR_S11POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S11POWER_Pos) /*!< Bit mask of S11POWER field. */ #define POWER_RAM_POWERCLR_S11POWER_Off (1UL) /*!< Off */ -/* Bit 10 : Keep RAM section S10 of RAMn on or off in System ON mode */ +/* Bit 10 : Keep RAM section S10 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S10POWER_Pos (10UL) /*!< Position of S10POWER field. */ #define POWER_RAM_POWERCLR_S10POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S10POWER_Pos) /*!< Bit mask of S10POWER field. */ #define POWER_RAM_POWERCLR_S10POWER_Off (1UL) /*!< Off */ -/* Bit 9 : Keep RAM section S9 of RAMn on or off in System ON mode */ +/* Bit 9 : Keep RAM section S9 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S9POWER_Pos (9UL) /*!< Position of S9POWER field. */ #define POWER_RAM_POWERCLR_S9POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S9POWER_Pos) /*!< Bit mask of S9POWER field. */ #define POWER_RAM_POWERCLR_S9POWER_Off (1UL) /*!< Off */ -/* Bit 8 : Keep RAM section S8 of RAMn on or off in System ON mode */ +/* Bit 8 : Keep RAM section S8 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S8POWER_Pos (8UL) /*!< Position of S8POWER field. */ #define POWER_RAM_POWERCLR_S8POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S8POWER_Pos) /*!< Bit mask of S8POWER field. */ #define POWER_RAM_POWERCLR_S8POWER_Off (1UL) /*!< Off */ -/* Bit 7 : Keep RAM section S7 of RAMn on or off in System ON mode */ +/* Bit 7 : Keep RAM section S7 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S7POWER_Pos (7UL) /*!< Position of S7POWER field. */ #define POWER_RAM_POWERCLR_S7POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S7POWER_Pos) /*!< Bit mask of S7POWER field. */ #define POWER_RAM_POWERCLR_S7POWER_Off (1UL) /*!< Off */ -/* Bit 6 : Keep RAM section S6 of RAMn on or off in System ON mode */ +/* Bit 6 : Keep RAM section S6 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S6POWER_Pos (6UL) /*!< Position of S6POWER field. */ #define POWER_RAM_POWERCLR_S6POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S6POWER_Pos) /*!< Bit mask of S6POWER field. */ #define POWER_RAM_POWERCLR_S6POWER_Off (1UL) /*!< Off */ -/* Bit 5 : Keep RAM section S5 of RAMn on or off in System ON mode */ +/* Bit 5 : Keep RAM section S5 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S5POWER_Pos (5UL) /*!< Position of S5POWER field. */ #define POWER_RAM_POWERCLR_S5POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S5POWER_Pos) /*!< Bit mask of S5POWER field. */ #define POWER_RAM_POWERCLR_S5POWER_Off (1UL) /*!< Off */ -/* Bit 4 : Keep RAM section S4 of RAMn on or off in System ON mode */ +/* Bit 4 : Keep RAM section S4 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S4POWER_Pos (4UL) /*!< Position of S4POWER field. */ #define POWER_RAM_POWERCLR_S4POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S4POWER_Pos) /*!< Bit mask of S4POWER field. */ #define POWER_RAM_POWERCLR_S4POWER_Off (1UL) /*!< Off */ -/* Bit 3 : Keep RAM section S3 of RAMn on or off in System ON mode */ +/* Bit 3 : Keep RAM section S3 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S3POWER_Pos (3UL) /*!< Position of S3POWER field. */ #define POWER_RAM_POWERCLR_S3POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S3POWER_Pos) /*!< Bit mask of S3POWER field. */ #define POWER_RAM_POWERCLR_S3POWER_Off (1UL) /*!< Off */ -/* Bit 2 : Keep RAM section S2 of RAMn on or off in System ON mode */ +/* Bit 2 : Keep RAM section S2 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S2POWER_Pos (2UL) /*!< Position of S2POWER field. */ #define POWER_RAM_POWERCLR_S2POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S2POWER_Pos) /*!< Bit mask of S2POWER field. */ #define POWER_RAM_POWERCLR_S2POWER_Off (1UL) /*!< Off */ -/* Bit 1 : Keep RAM section S1 of RAMn on or off in System ON mode */ +/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ -/* Bit 0 : Keep RAM section S0 of RAMn on or off in System ON mode */ +/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ @@ -7894,22 +6881,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: PPI */ /* Description: Programmable Peripheral Interconnect */ -/* Register: PPI_TASKS_CHG_EN */ -/* Description: Description cluster: Enable channel group n */ - -/* Bit 0 : Enable channel group n */ -#define PPI_TASKS_CHG_EN_EN_Pos (0UL) /*!< Position of EN field. */ -#define PPI_TASKS_CHG_EN_EN_Msk (0x1UL << PPI_TASKS_CHG_EN_EN_Pos) /*!< Bit mask of EN field. */ -#define PPI_TASKS_CHG_EN_EN_Trigger (1UL) /*!< Trigger task */ - -/* Register: PPI_TASKS_CHG_DIS */ -/* Description: Description cluster: Disable channel group n */ - -/* Bit 0 : Disable channel group n */ -#define PPI_TASKS_CHG_DIS_DIS_Pos (0UL) /*!< Position of DIS field. */ -#define PPI_TASKS_CHG_DIS_DIS_Msk (0x1UL << PPI_TASKS_CHG_DIS_DIS_Pos) /*!< Bit mask of DIS field. */ -#define PPI_TASKS_CHG_DIS_DIS_Trigger (1UL) /*!< Trigger task */ - /* Register: PPI_CHEN */ /* Description: Channel enable register */ @@ -8560,21 +7531,21 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ /* Register: PPI_CH_EEP */ -/* Description: Description cluster: Channel n event end-point */ +/* Description: Description cluster[0]: Channel 0 event end-point */ /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ /* Register: PPI_CH_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster[0]: Channel 0 task end-point */ /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ /* Register: PPI_CHG */ -/* Description: Description collection: Channel group n */ +/* Description: Description collection[0]: Channel group 0 */ /* Bit 31 : Include or exclude channel 31 */ #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ @@ -8769,7 +7740,7 @@ POSSIBILITY OF SUCH DAMAGE. #define PPI_CHG_CH0_Included (1UL) /*!< Include */ /* Register: PPI_FORK_TEP */ -/* Description: Description cluster: Channel n task end-point */ +/* Description: Description cluster[0]: Channel 0 task end-point */ /* Bits 31..0 : Pointer to task register */ #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ @@ -8777,105 +7748,36 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: PWM */ -/* Description: Pulse width modulation unit 0 */ - -/* Register: PWM_TASKS_STOP */ -/* Description: Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ - -/* Bit 0 : Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback */ -#define PWM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define PWM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << PWM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define PWM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: PWM_TASKS_SEQSTART */ -/* Description: Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ - -/* Bit 0 : Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. */ -#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos (0UL) /*!< Position of TASKS_SEQSTART field. */ -#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Msk (0x1UL << PWM_TASKS_SEQSTART_TASKS_SEQSTART_Pos) /*!< Bit mask of TASKS_SEQSTART field. */ -#define PWM_TASKS_SEQSTART_TASKS_SEQSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: PWM_TASKS_NEXTSTEP */ -/* Description: Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ - -/* Bit 0 : Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. */ -#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos (0UL) /*!< Position of TASKS_NEXTSTEP field. */ -#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Msk (0x1UL << PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Pos) /*!< Bit mask of TASKS_NEXTSTEP field. */ -#define PWM_TASKS_NEXTSTEP_TASKS_NEXTSTEP_Trigger (1UL) /*!< Trigger task */ - -/* Register: PWM_EVENTS_STOPPED */ -/* Description: Response to STOP task, emitted when PWM pulses are no longer generated */ - -/* Bit 0 : Response to STOP task, emitted when PWM pulses are no longer generated */ -#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << PWM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: PWM_EVENTS_SEQSTARTED */ -/* Description: Description collection: First PWM period started on sequence n */ - -/* Bit 0 : First PWM period started on sequence n */ -#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos (0UL) /*!< Position of EVENTS_SEQSTARTED field. */ -#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Msk (0x1UL << PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Pos) /*!< Bit mask of EVENTS_SEQSTARTED field. */ -#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_SEQSTARTED_EVENTS_SEQSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: PWM_EVENTS_SEQEND */ -/* Description: Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ - -/* Bit 0 : Emitted at end of every sequence n, when last value from RAM has been applied to wave counter */ -#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos (0UL) /*!< Position of EVENTS_SEQEND field. */ -#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Msk (0x1UL << PWM_EVENTS_SEQEND_EVENTS_SEQEND_Pos) /*!< Bit mask of EVENTS_SEQEND field. */ -#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_SEQEND_EVENTS_SEQEND_Generated (1UL) /*!< Event generated */ - -/* Register: PWM_EVENTS_PWMPERIODEND */ -/* Description: Emitted at the end of each PWM period */ - -/* Bit 0 : Emitted at the end of each PWM period */ -#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos (0UL) /*!< Position of EVENTS_PWMPERIODEND field. */ -#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Msk (0x1UL << PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Pos) /*!< Bit mask of EVENTS_PWMPERIODEND field. */ -#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_PWMPERIODEND_EVENTS_PWMPERIODEND_Generated (1UL) /*!< Event generated */ - -/* Register: PWM_EVENTS_LOOPSDONE */ -/* Description: Concatenated sequences have been played the amount of times defined in LOOP.CNT */ - -/* Bit 0 : Concatenated sequences have been played the amount of times defined in LOOP.CNT */ -#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos (0UL) /*!< Position of EVENTS_LOOPSDONE field. */ -#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Msk (0x1UL << PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Pos) /*!< Bit mask of EVENTS_LOOPSDONE field. */ -#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_NotGenerated (0UL) /*!< Event not generated */ -#define PWM_EVENTS_LOOPSDONE_EVENTS_LOOPSDONE_Generated (1UL) /*!< Event generated */ +/* Description: Pulse Width Modulation Unit 0 */ /* Register: PWM_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 4 : Shortcut between event LOOPSDONE and task STOP */ +/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event LOOPSDONE and task SEQSTART[1] */ +/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event LOOPSDONE and task SEQSTART[0] */ +/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event SEQEND[1] and task STOP */ +/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event SEQEND[0] and task STOP */ +/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -8884,43 +7786,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 7 : Enable or disable interrupt for event LOOPSDONE */ +/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event PWMPERIODEND */ +/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event SEQEND[1] */ +/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event SEQEND[0] */ +/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event SEQSTARTED[1] */ +/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event SEQSTARTED[0] */ +/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event STOPPED */ +/* Bit 1 : Enable or disable interrupt for STOPPED event */ #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -8929,49 +7831,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 7 : Write '1' to enable interrupt for event LOOPSDONE */ +/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event PWMPERIODEND */ +/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event SEQEND[1] */ +/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event SEQEND[0] */ +/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event SEQSTARTED[1] */ +/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event SEQSTARTED[0] */ +/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -8981,49 +7883,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 7 : Write '1' to disable interrupt for event LOOPSDONE */ +/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event PWMPERIODEND */ +/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event SEQEND[1] */ +/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event SEQEND[0] */ +/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event SEQSTARTED[1] */ +/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event SEQSTARTED[0] */ +/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -9042,33 +7944,33 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: PWM_MODE */ /* Description: Selects operating mode of the wave counter */ -/* Bit 0 : Selects up mode or up-and-down mode for the counter */ +/* Bit 0 : Selects up or up and down as wave counter mode */ #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ -#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter, edge-aligned PWM duty cycle */ -#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter, center-aligned PWM duty cycle */ +#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ +#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ /* Register: PWM_COUNTERTOP */ /* Description: Value up to which the pulse generator counter counts */ -/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. */ +/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ /* Register: PWM_PRESCALER */ /* Description: Configuration for PWM_CLK */ -/* Bits 2..0 : Prescaler of PWM_CLK */ +/* Bits 2..0 : Pre-scaler of PWM_CLK */ #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ -#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 (8 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 (4 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 (2 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 (1 MHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 (500 kHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 (250 kHz) */ -#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 (125 kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ +#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ /* Register: PWM_DECODER */ /* Description: Configuration of the decoder */ @@ -9079,54 +7981,54 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ -/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ -#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ /* Register: PWM_LOOP */ -/* Description: Number of playbacks of a loop */ +/* Description: Amount of playback of a loop */ -/* Bits 15..0 : Number of playbacks of pattern cycles */ +/* Bits 15..0 : Amount of playback of pattern cycles */ #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster: Beginning address in RAM of this sequence */ +/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ -/* Bits 31..0 : Beginning address in RAM of this sequence */ +/* Bits 31..0 : Beginning address in Data RAM of sequence A */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster: Number of values (duty cycles) in this sequence */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ -/* Bits 14..0 : Number of values (duty cycles) in this sequence */ +/* Bits 14..0 : Amount of values (duty cycles) in sequence A */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster: Number of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ -/* Bits 23..0 : Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ /* Register: PWM_SEQ_ENDDELAY */ -/* Description: Description cluster: Time added after the sequence */ +/* Description: Description cluster[0]: Time added after the sequence */ /* Bits 23..0 : Time added after the sequence in PWM periods */ #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: PWM_PSEL_OUT */ -/* Description: Description collection: Output pin select for PWM channel n */ +/* Description: Description collection[0]: Output pin select for PWM channel 0 */ /* Bit 31 : Connection */ #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -9134,9 +8036,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ -#define PWM_PSEL_OUT_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define PWM_PSEL_OUT_PORT_Msk (0x1UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ +/* Bits 9..8 : Port number */ +#define PWM_PSEL_OUT_PORT_Pos (8UL) /*!< Position of PORT field. */ +#define PWM_PSEL_OUT_PORT_Msk (0x3UL << PWM_PSEL_OUT_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9146,131 +8048,46 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: QDEC */ /* Description: Quadrature Decoder */ -/* Register: QDEC_TASKS_START */ -/* Description: Task starting the quadrature decoder */ - -/* Bit 0 : Task starting the quadrature decoder */ -#define QDEC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define QDEC_TASKS_START_TASKS_START_Msk (0x1UL << QDEC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define QDEC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: QDEC_TASKS_STOP */ -/* Description: Task stopping the quadrature decoder */ - -/* Bit 0 : Task stopping the quadrature decoder */ -#define QDEC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define QDEC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << QDEC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define QDEC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: QDEC_TASKS_READCLRACC */ -/* Description: Read and clear ACC and ACCDBL */ - -/* Bit 0 : Read and clear ACC and ACCDBL */ -#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos (0UL) /*!< Position of TASKS_READCLRACC field. */ -#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Msk (0x1UL << QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Pos) /*!< Bit mask of TASKS_READCLRACC field. */ -#define QDEC_TASKS_READCLRACC_TASKS_READCLRACC_Trigger (1UL) /*!< Trigger task */ - -/* Register: QDEC_TASKS_RDCLRACC */ -/* Description: Read and clear ACC */ - -/* Bit 0 : Read and clear ACC */ -#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos (0UL) /*!< Position of TASKS_RDCLRACC field. */ -#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Msk (0x1UL << QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Pos) /*!< Bit mask of TASKS_RDCLRACC field. */ -#define QDEC_TASKS_RDCLRACC_TASKS_RDCLRACC_Trigger (1UL) /*!< Trigger task */ - -/* Register: QDEC_TASKS_RDCLRDBL */ -/* Description: Read and clear ACCDBL */ - -/* Bit 0 : Read and clear ACCDBL */ -#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos (0UL) /*!< Position of TASKS_RDCLRDBL field. */ -#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Msk (0x1UL << QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Pos) /*!< Bit mask of TASKS_RDCLRDBL field. */ -#define QDEC_TASKS_RDCLRDBL_TASKS_RDCLRDBL_Trigger (1UL) /*!< Trigger task */ - -/* Register: QDEC_EVENTS_SAMPLERDY */ -/* Description: Event being generated for every new sample value written to the SAMPLE register */ - -/* Bit 0 : Event being generated for every new sample value written to the SAMPLE register */ -#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos (0UL) /*!< Position of EVENTS_SAMPLERDY field. */ -#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Msk (0x1UL << QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Pos) /*!< Bit mask of EVENTS_SAMPLERDY field. */ -#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_NotGenerated (0UL) /*!< Event not generated */ -#define QDEC_EVENTS_SAMPLERDY_EVENTS_SAMPLERDY_Generated (1UL) /*!< Event generated */ - -/* Register: QDEC_EVENTS_REPORTRDY */ -/* Description: Non-null report ready */ - -/* Bit 0 : Non-null report ready */ -#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos (0UL) /*!< Position of EVENTS_REPORTRDY field. */ -#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Msk (0x1UL << QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Pos) /*!< Bit mask of EVENTS_REPORTRDY field. */ -#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_NotGenerated (0UL) /*!< Event not generated */ -#define QDEC_EVENTS_REPORTRDY_EVENTS_REPORTRDY_Generated (1UL) /*!< Event generated */ - -/* Register: QDEC_EVENTS_ACCOF */ -/* Description: ACC or ACCDBL register overflow */ - -/* Bit 0 : ACC or ACCDBL register overflow */ -#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos (0UL) /*!< Position of EVENTS_ACCOF field. */ -#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Msk (0x1UL << QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Pos) /*!< Bit mask of EVENTS_ACCOF field. */ -#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_NotGenerated (0UL) /*!< Event not generated */ -#define QDEC_EVENTS_ACCOF_EVENTS_ACCOF_Generated (1UL) /*!< Event generated */ - -/* Register: QDEC_EVENTS_DBLRDY */ -/* Description: Double displacement(s) detected */ - -/* Bit 0 : Double displacement(s) detected */ -#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos (0UL) /*!< Position of EVENTS_DBLRDY field. */ -#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Msk (0x1UL << QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Pos) /*!< Bit mask of EVENTS_DBLRDY field. */ -#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_NotGenerated (0UL) /*!< Event not generated */ -#define QDEC_EVENTS_DBLRDY_EVENTS_DBLRDY_Generated (1UL) /*!< Event generated */ - -/* Register: QDEC_EVENTS_STOPPED */ -/* Description: QDEC has been stopped */ - -/* Bit 0 : QDEC has been stopped */ -#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define QDEC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - /* Register: QDEC_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 6 : Shortcut between event SAMPLERDY and task READCLRACC */ +/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between event DBLRDY and task STOP */ +/* Bit 5 : Shortcut between DBLRDY event and STOP task */ #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between event DBLRDY and task RDCLRDBL */ +/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event REPORTRDY and task STOP */ +/* Bit 3 : Shortcut between REPORTRDY event and STOP task */ #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event REPORTRDY and task RDCLRACC */ +/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event SAMPLERDY and task STOP */ +/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event REPORTRDY and task READCLRACC */ +/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ @@ -9279,35 +8096,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 4 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event DBLRDY */ +/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event ACCOF */ +/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event REPORTRDY */ +/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event SAMPLERDY */ +/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9317,35 +8134,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QDEC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 4 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event DBLRDY */ +/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event ACCOF */ +/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event REPORTRDY */ +/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event SAMPLERDY */ +/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ @@ -9434,9 +8251,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QDEC_PSEL_LED_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QDEC_PSEL_LED_PORT_Msk (0x1UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QDEC_PSEL_LED_PORT_Msk (0x3UL << QDEC_PSEL_LED_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9451,9 +8268,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QDEC_PSEL_A_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QDEC_PSEL_A_PORT_Msk (0x1UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QDEC_PSEL_A_PORT_Msk (0x3UL << QDEC_PSEL_A_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9468,9 +8285,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QDEC_PSEL_B_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QDEC_PSEL_B_PORT_Msk (0x1UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QDEC_PSEL_B_PORT_Msk (0x3UL << QDEC_PSEL_B_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9510,59 +8327,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: QSPI */ /* Description: External flash interface */ -/* Register: QSPI_TASKS_ACTIVATE */ -/* Description: Activate QSPI interface */ - -/* Bit 0 : Activate QSPI interface */ -#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos (0UL) /*!< Position of TASKS_ACTIVATE field. */ -#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Msk (0x1UL << QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Pos) /*!< Bit mask of TASKS_ACTIVATE field. */ -#define QSPI_TASKS_ACTIVATE_TASKS_ACTIVATE_Trigger (1UL) /*!< Trigger task */ - -/* Register: QSPI_TASKS_READSTART */ -/* Description: Start transfer from external flash memory to internal RAM */ - -/* Bit 0 : Start transfer from external flash memory to internal RAM */ -#define QSPI_TASKS_READSTART_TASKS_READSTART_Pos (0UL) /*!< Position of TASKS_READSTART field. */ -#define QSPI_TASKS_READSTART_TASKS_READSTART_Msk (0x1UL << QSPI_TASKS_READSTART_TASKS_READSTART_Pos) /*!< Bit mask of TASKS_READSTART field. */ -#define QSPI_TASKS_READSTART_TASKS_READSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: QSPI_TASKS_WRITESTART */ -/* Description: Start transfer from internal RAM to external flash memory */ - -/* Bit 0 : Start transfer from internal RAM to external flash memory */ -#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos (0UL) /*!< Position of TASKS_WRITESTART field. */ -#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Msk (0x1UL << QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Pos) /*!< Bit mask of TASKS_WRITESTART field. */ -#define QSPI_TASKS_WRITESTART_TASKS_WRITESTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: QSPI_TASKS_ERASESTART */ -/* Description: Start external flash memory erase operation */ - -/* Bit 0 : Start external flash memory erase operation */ -#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos (0UL) /*!< Position of TASKS_ERASESTART field. */ -#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Msk (0x1UL << QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Pos) /*!< Bit mask of TASKS_ERASESTART field. */ -#define QSPI_TASKS_ERASESTART_TASKS_ERASESTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: QSPI_TASKS_DEACTIVATE */ -/* Description: Deactivate QSPI interface */ - -/* Bit 0 : Deactivate QSPI interface */ -#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos (0UL) /*!< Position of TASKS_DEACTIVATE field. */ -#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Msk (0x1UL << QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Pos) /*!< Bit mask of TASKS_DEACTIVATE field. */ -#define QSPI_TASKS_DEACTIVATE_TASKS_DEACTIVATE_Trigger (1UL) /*!< Trigger task */ - -/* Register: QSPI_EVENTS_READY */ -/* Description: QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ - -/* Bit 0 : QSPI peripheral is ready. This event will be generated as a response to any QSPI task. */ -#define QSPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ -#define QSPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << QSPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ -#define QSPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ -#define QSPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ - /* Register: QSPI_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 0 : Enable or disable interrupt for event READY */ +/* Bit 0 : Enable or disable interrupt for READY event */ #define QSPI_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTEN_READY_Msk (0x1UL << QSPI_INTEN_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTEN_READY_Disabled (0UL) /*!< Disable */ @@ -9571,7 +8339,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for event READY */ +/* Bit 0 : Write '1' to Enable interrupt for READY event */ #define QSPI_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENSET_READY_Msk (0x1UL << QSPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9581,7 +8349,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for event READY */ +/* Bit 0 : Write '1' to Disable interrupt for READY event */ #define QSPI_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define QSPI_INTENCLR_READY_Msk (0x1UL << QSPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define QSPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -9614,9 +8382,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_READ_CNT */ /* Description: Read transfer length */ -/* Bits 17..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 20..0 : Read transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_READ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_READ_CNT_CNT_Msk (0x3FFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_READ_CNT_CNT_Msk (0x1FFFFFUL << QSPI_READ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_WRITE_DST */ /* Description: Flash destination address */ @@ -9635,9 +8403,9 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_WRITE_CNT */ /* Description: Write transfer length */ -/* Bits 17..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ +/* Bits 20..0 : Write transfer length in number of bytes. The length must be a multiple of 4 bytes. */ #define QSPI_WRITE_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ -#define QSPI_WRITE_CNT_CNT_Msk (0x3FFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ +#define QSPI_WRITE_CNT_CNT_Msk (0x1FFFFFUL << QSPI_WRITE_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ /* Register: QSPI_ERASE_PTR */ /* Description: Start address of flash block to be erased */ @@ -9665,9 +8433,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ #define QSPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QSPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QSPI_PSEL_SCK_PORT_Msk (0x1UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QSPI_PSEL_SCK_PORT_Msk (0x3UL << QSPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QSPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9682,9 +8450,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ #define QSPI_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QSPI_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QSPI_PSEL_CSN_PORT_Msk (0x1UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QSPI_PSEL_CSN_PORT_Msk (0x3UL << QSPI_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QSPI_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9699,9 +8467,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_IO0_CONNECT_Connected (0UL) /*!< Connect */ #define QSPI_PSEL_IO0_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QSPI_PSEL_IO0_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QSPI_PSEL_IO0_PORT_Msk (0x1UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QSPI_PSEL_IO0_PORT_Msk (0x3UL << QSPI_PSEL_IO0_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QSPI_PSEL_IO0_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9716,9 +8484,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_IO1_CONNECT_Connected (0UL) /*!< Connect */ #define QSPI_PSEL_IO1_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QSPI_PSEL_IO1_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QSPI_PSEL_IO1_PORT_Msk (0x1UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QSPI_PSEL_IO1_PORT_Msk (0x3UL << QSPI_PSEL_IO1_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QSPI_PSEL_IO1_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9733,9 +8501,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_IO2_CONNECT_Connected (0UL) /*!< Connect */ #define QSPI_PSEL_IO2_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QSPI_PSEL_IO2_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QSPI_PSEL_IO2_PORT_Msk (0x1UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QSPI_PSEL_IO2_PORT_Msk (0x3UL << QSPI_PSEL_IO2_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QSPI_PSEL_IO2_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9750,9 +8518,9 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PSEL_IO3_CONNECT_Connected (0UL) /*!< Connect */ #define QSPI_PSEL_IO3_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define QSPI_PSEL_IO3_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define QSPI_PSEL_IO3_PORT_Msk (0x1UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */ +#define QSPI_PSEL_IO3_PORT_Msk (0x3UL << QSPI_PSEL_IO3_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define QSPI_PSEL_IO3_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -9768,12 +8536,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_IFCONFIG0 */ /* Description: Interface configuration. */ -/* Bit 12 : Page size for commands PP, PP2O, PP4O and PP4IO. */ -#define QSPI_IFCONFIG0_PPSIZE_Pos (12UL) /*!< Position of PPSIZE field. */ -#define QSPI_IFCONFIG0_PPSIZE_Msk (0x1UL << QSPI_IFCONFIG0_PPSIZE_Pos) /*!< Bit mask of PPSIZE field. */ -#define QSPI_IFCONFIG0_PPSIZE_256Bytes (0UL) /*!< 256 bytes. */ -#define QSPI_IFCONFIG0_PPSIZE_512Bytes (1UL) /*!< 512 bytes. */ - /* Bit 7 : Enable deep power-down mode (DPM) feature. */ #define QSPI_IFCONFIG0_DPMENABLE_Pos (7UL) /*!< Position of DPMENABLE field. */ #define QSPI_IFCONFIG0_DPMENABLE_Msk (0x1UL << QSPI_IFCONFIG0_DPMENABLE_Pos) /*!< Bit mask of DPMENABLE field. */ @@ -9813,8 +8575,8 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 25 : Select SPI mode. */ #define QSPI_IFCONFIG1_SPIMODE_Pos (25UL) /*!< Position of SPIMODE field. */ #define QSPI_IFCONFIG1_SPIMODE_Msk (0x1UL << QSPI_IFCONFIG1_SPIMODE_Pos) /*!< Bit mask of SPIMODE field. */ -#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ -#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ +#define QSPI_IFCONFIG1_SPIMODE_MODE0 (0UL) /*!< Mode 0: Data are captured on the clock's rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). */ +#define QSPI_IFCONFIG1_SPIMODE_MODE3 (1UL) /*!< Mode 3: Data are captured on the clock's falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). */ /* Bit 24 : Enter/exit deep power-down mode (DPM) for external flash memory. */ #define QSPI_IFCONFIG1_DPMEN_Pos (24UL) /*!< Position of DPMEN field. */ @@ -9829,7 +8591,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_STATUS */ /* Description: Status register. */ -/* Bits 31..24 : Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */ +/* Bits 31..24 : Value of external flash devices Status Register. When the external flash has two bytes status register this field includes the value of the low byte. */ #define QSPI_STATUS_SREG_Pos (24UL) /*!< Position of SREG field. */ #define QSPI_STATUS_SREG_Msk (0xFFUL << QSPI_STATUS_SREG_Pos) /*!< Bit mask of SREG field. */ @@ -9894,17 +8656,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: QSPI_CINSTRCONF */ /* Description: Custom instruction configuration register. */ -/* Bit 17 : Stop (finalize) long frame transaction */ -#define QSPI_CINSTRCONF_LFSTOP_Pos (17UL) /*!< Position of LFSTOP field. */ -#define QSPI_CINSTRCONF_LFSTOP_Msk (0x1UL << QSPI_CINSTRCONF_LFSTOP_Pos) /*!< Bit mask of LFSTOP field. */ -#define QSPI_CINSTRCONF_LFSTOP_Stop (1UL) /*!< Stop */ - -/* Bit 16 : Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. */ -#define QSPI_CINSTRCONF_LFEN_Pos (16UL) /*!< Position of LFEN field. */ -#define QSPI_CINSTRCONF_LFEN_Msk (0x1UL << QSPI_CINSTRCONF_LFEN_Pos) /*!< Bit mask of LFEN field. */ -#define QSPI_CINSTRCONF_LFEN_Disable (0UL) /*!< Long frame mode disabled */ -#define QSPI_CINSTRCONF_LFEN_Enable (1UL) /*!< Long frame mode enabled */ - /* Bit 15 : Send WREN (write enable opcode 0x06) before instruction. */ #define QSPI_CINSTRCONF_WREN_Pos (15UL) /*!< Position of WREN field. */ #define QSPI_CINSTRCONF_WREN_Msk (0x1UL << QSPI_CINSTRCONF_WREN_Pos) /*!< Bit mask of WREN field. */ @@ -9989,431 +8740,108 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: RADIO */ -/* Description: 2.4 GHz radio */ - -/* Register: RADIO_TASKS_TXEN */ -/* Description: Enable RADIO in TX mode */ - -/* Bit 0 : Enable RADIO in TX mode */ -#define RADIO_TASKS_TXEN_TASKS_TXEN_Pos (0UL) /*!< Position of TASKS_TXEN field. */ -#define RADIO_TASKS_TXEN_TASKS_TXEN_Msk (0x1UL << RADIO_TASKS_TXEN_TASKS_TXEN_Pos) /*!< Bit mask of TASKS_TXEN field. */ -#define RADIO_TASKS_TXEN_TASKS_TXEN_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_RXEN */ -/* Description: Enable RADIO in RX mode */ - -/* Bit 0 : Enable RADIO in RX mode */ -#define RADIO_TASKS_RXEN_TASKS_RXEN_Pos (0UL) /*!< Position of TASKS_RXEN field. */ -#define RADIO_TASKS_RXEN_TASKS_RXEN_Msk (0x1UL << RADIO_TASKS_RXEN_TASKS_RXEN_Pos) /*!< Bit mask of TASKS_RXEN field. */ -#define RADIO_TASKS_RXEN_TASKS_RXEN_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_START */ -/* Description: Start RADIO */ - -/* Bit 0 : Start RADIO */ -#define RADIO_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define RADIO_TASKS_START_TASKS_START_Msk (0x1UL << RADIO_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define RADIO_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_STOP */ -/* Description: Stop RADIO */ - -/* Bit 0 : Stop RADIO */ -#define RADIO_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define RADIO_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RADIO_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define RADIO_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_DISABLE */ -/* Description: Disable RADIO */ - -/* Bit 0 : Disable RADIO */ -#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos (0UL) /*!< Position of TASKS_DISABLE field. */ -#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Msk (0x1UL << RADIO_TASKS_DISABLE_TASKS_DISABLE_Pos) /*!< Bit mask of TASKS_DISABLE field. */ -#define RADIO_TASKS_DISABLE_TASKS_DISABLE_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_RSSISTART */ -/* Description: Start the RSSI and take one single sample of the receive signal strength */ - -/* Bit 0 : Start the RSSI and take one single sample of the receive signal strength */ -#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos (0UL) /*!< Position of TASKS_RSSISTART field. */ -#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Msk (0x1UL << RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Pos) /*!< Bit mask of TASKS_RSSISTART field. */ -#define RADIO_TASKS_RSSISTART_TASKS_RSSISTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_RSSISTOP */ -/* Description: Stop the RSSI measurement */ - -/* Bit 0 : Stop the RSSI measurement */ -#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos (0UL) /*!< Position of TASKS_RSSISTOP field. */ -#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Msk (0x1UL << RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Pos) /*!< Bit mask of TASKS_RSSISTOP field. */ -#define RADIO_TASKS_RSSISTOP_TASKS_RSSISTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_BCSTART */ -/* Description: Start the bit counter */ - -/* Bit 0 : Start the bit counter */ -#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos (0UL) /*!< Position of TASKS_BCSTART field. */ -#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Msk (0x1UL << RADIO_TASKS_BCSTART_TASKS_BCSTART_Pos) /*!< Bit mask of TASKS_BCSTART field. */ -#define RADIO_TASKS_BCSTART_TASKS_BCSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_BCSTOP */ -/* Description: Stop the bit counter */ - -/* Bit 0 : Stop the bit counter */ -#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos (0UL) /*!< Position of TASKS_BCSTOP field. */ -#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Msk (0x1UL << RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Pos) /*!< Bit mask of TASKS_BCSTOP field. */ -#define RADIO_TASKS_BCSTOP_TASKS_BCSTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_EDSTART */ -/* Description: Start the energy detect measurement used in IEEE 802.15.4 mode */ - -/* Bit 0 : Start the energy detect measurement used in IEEE 802.15.4 mode */ -#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos (0UL) /*!< Position of TASKS_EDSTART field. */ -#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Msk (0x1UL << RADIO_TASKS_EDSTART_TASKS_EDSTART_Pos) /*!< Bit mask of TASKS_EDSTART field. */ -#define RADIO_TASKS_EDSTART_TASKS_EDSTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_EDSTOP */ -/* Description: Stop the energy detect measurement */ - -/* Bit 0 : Stop the energy detect measurement */ -#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos (0UL) /*!< Position of TASKS_EDSTOP field. */ -#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Msk (0x1UL << RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Pos) /*!< Bit mask of TASKS_EDSTOP field. */ -#define RADIO_TASKS_EDSTOP_TASKS_EDSTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_CCASTART */ -/* Description: Start the clear channel assessment used in IEEE 802.15.4 mode */ - -/* Bit 0 : Start the clear channel assessment used in IEEE 802.15.4 mode */ -#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos (0UL) /*!< Position of TASKS_CCASTART field. */ -#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Msk (0x1UL << RADIO_TASKS_CCASTART_TASKS_CCASTART_Pos) /*!< Bit mask of TASKS_CCASTART field. */ -#define RADIO_TASKS_CCASTART_TASKS_CCASTART_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_TASKS_CCASTOP */ -/* Description: Stop the clear channel assessment */ - -/* Bit 0 : Stop the clear channel assessment */ -#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos (0UL) /*!< Position of TASKS_CCASTOP field. */ -#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Msk (0x1UL << RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Pos) /*!< Bit mask of TASKS_CCASTOP field. */ -#define RADIO_TASKS_CCASTOP_TASKS_CCASTOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RADIO_EVENTS_READY */ -/* Description: RADIO has ramped up and is ready to be started */ - -/* Bit 0 : RADIO has ramped up and is ready to be started */ -#define RADIO_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ -#define RADIO_EVENTS_READY_EVENTS_READY_Msk (0x1UL << RADIO_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ -#define RADIO_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_ADDRESS */ -/* Description: Address sent or received */ - -/* Bit 0 : Address sent or received */ -#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos (0UL) /*!< Position of EVENTS_ADDRESS field. */ -#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Msk (0x1UL << RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Pos) /*!< Bit mask of EVENTS_ADDRESS field. */ -#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_ADDRESS_EVENTS_ADDRESS_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_PAYLOAD */ -/* Description: Packet payload sent or received */ - -/* Bit 0 : Packet payload sent or received */ -#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos (0UL) /*!< Position of EVENTS_PAYLOAD field. */ -#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Msk (0x1UL << RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Pos) /*!< Bit mask of EVENTS_PAYLOAD field. */ -#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_PAYLOAD_EVENTS_PAYLOAD_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_END */ -/* Description: Packet sent or received */ - -/* Bit 0 : Packet sent or received */ -#define RADIO_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ -#define RADIO_EVENTS_END_EVENTS_END_Msk (0x1UL << RADIO_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define RADIO_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_DISABLED */ -/* Description: RADIO has been disabled */ - -/* Bit 0 : RADIO has been disabled */ -#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos (0UL) /*!< Position of EVENTS_DISABLED field. */ -#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Msk (0x1UL << RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Pos) /*!< Bit mask of EVENTS_DISABLED field. */ -#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_DISABLED_EVENTS_DISABLED_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_DEVMATCH */ -/* Description: A device address match occurred on the last received packet */ - -/* Bit 0 : A device address match occurred on the last received packet */ -#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos (0UL) /*!< Position of EVENTS_DEVMATCH field. */ -#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Msk (0x1UL << RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Pos) /*!< Bit mask of EVENTS_DEVMATCH field. */ -#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_DEVMATCH_EVENTS_DEVMATCH_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_DEVMISS */ -/* Description: No device address match occurred on the last received packet */ - -/* Bit 0 : No device address match occurred on the last received packet */ -#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos (0UL) /*!< Position of EVENTS_DEVMISS field. */ -#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Msk (0x1UL << RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Pos) /*!< Bit mask of EVENTS_DEVMISS field. */ -#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_DEVMISS_EVENTS_DEVMISS_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_RSSIEND */ -/* Description: Sampling of receive signal strength complete */ - -/* Bit 0 : Sampling of receive signal strength complete */ -#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos (0UL) /*!< Position of EVENTS_RSSIEND field. */ -#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Msk (0x1UL << RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Pos) /*!< Bit mask of EVENTS_RSSIEND field. */ -#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_RSSIEND_EVENTS_RSSIEND_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_BCMATCH */ -/* Description: Bit counter reached bit count value */ - -/* Bit 0 : Bit counter reached bit count value */ -#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos (0UL) /*!< Position of EVENTS_BCMATCH field. */ -#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Msk (0x1UL << RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Pos) /*!< Bit mask of EVENTS_BCMATCH field. */ -#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_BCMATCH_EVENTS_BCMATCH_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_CRCOK */ -/* Description: Packet received with CRC ok */ - -/* Bit 0 : Packet received with CRC ok */ -#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos (0UL) /*!< Position of EVENTS_CRCOK field. */ -#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Msk (0x1UL << RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Pos) /*!< Bit mask of EVENTS_CRCOK field. */ -#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_CRCOK_EVENTS_CRCOK_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_CRCERROR */ -/* Description: Packet received with CRC error */ - -/* Bit 0 : Packet received with CRC error */ -#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos (0UL) /*!< Position of EVENTS_CRCERROR field. */ -#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Msk (0x1UL << RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Pos) /*!< Bit mask of EVENTS_CRCERROR field. */ -#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_CRCERROR_EVENTS_CRCERROR_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_FRAMESTART */ -/* Description: IEEE 802.15.4 length field received */ - -/* Bit 0 : IEEE 802.15.4 length field received */ -#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos (0UL) /*!< Position of EVENTS_FRAMESTART field. */ -#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Msk (0x1UL << RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Pos) /*!< Bit mask of EVENTS_FRAMESTART field. */ -#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_FRAMESTART_EVENTS_FRAMESTART_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_EDEND */ -/* Description: Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ - -/* Bit 0 : Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. */ -#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos (0UL) /*!< Position of EVENTS_EDEND field. */ -#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Msk (0x1UL << RADIO_EVENTS_EDEND_EVENTS_EDEND_Pos) /*!< Bit mask of EVENTS_EDEND field. */ -#define RADIO_EVENTS_EDEND_EVENTS_EDEND_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_EDEND_EVENTS_EDEND_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_EDSTOPPED */ -/* Description: The sampling of energy detection has stopped */ - -/* Bit 0 : The sampling of energy detection has stopped */ -#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos (0UL) /*!< Position of EVENTS_EDSTOPPED field. */ -#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Msk (0x1UL << RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Pos) /*!< Bit mask of EVENTS_EDSTOPPED field. */ -#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_EDSTOPPED_EVENTS_EDSTOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_CCAIDLE */ -/* Description: Wireless medium in idle - clear to send */ - -/* Bit 0 : Wireless medium in idle - clear to send */ -#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos (0UL) /*!< Position of EVENTS_CCAIDLE field. */ -#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Msk (0x1UL << RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Pos) /*!< Bit mask of EVENTS_CCAIDLE field. */ -#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_CCAIDLE_EVENTS_CCAIDLE_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_CCABUSY */ -/* Description: Wireless medium busy - do not send */ - -/* Bit 0 : Wireless medium busy - do not send */ -#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos (0UL) /*!< Position of EVENTS_CCABUSY field. */ -#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Msk (0x1UL << RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Pos) /*!< Bit mask of EVENTS_CCABUSY field. */ -#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_CCABUSY_EVENTS_CCABUSY_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_CCASTOPPED */ -/* Description: The CCA has stopped */ - -/* Bit 0 : The CCA has stopped */ -#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos (0UL) /*!< Position of EVENTS_CCASTOPPED field. */ -#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Msk (0x1UL << RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Pos) /*!< Bit mask of EVENTS_CCASTOPPED field. */ -#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_CCASTOPPED_EVENTS_CCASTOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_RATEBOOST */ -/* Description: Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ - -/* Bit 0 : Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. */ -#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos (0UL) /*!< Position of EVENTS_RATEBOOST field. */ -#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Msk (0x1UL << RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Pos) /*!< Bit mask of EVENTS_RATEBOOST field. */ -#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_RATEBOOST_EVENTS_RATEBOOST_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_TXREADY */ -/* Description: RADIO has ramped up and is ready to be started TX path */ - -/* Bit 0 : RADIO has ramped up and is ready to be started TX path */ -#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos (0UL) /*!< Position of EVENTS_TXREADY field. */ -#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Msk (0x1UL << RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Pos) /*!< Bit mask of EVENTS_TXREADY field. */ -#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_TXREADY_EVENTS_TXREADY_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_RXREADY */ -/* Description: RADIO has ramped up and is ready to be started RX path */ - -/* Bit 0 : RADIO has ramped up and is ready to be started RX path */ -#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos (0UL) /*!< Position of EVENTS_RXREADY field. */ -#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Msk (0x1UL << RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Pos) /*!< Bit mask of EVENTS_RXREADY field. */ -#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_RXREADY_EVENTS_RXREADY_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_MHRMATCH */ -/* Description: MAC header match found */ - -/* Bit 0 : MAC header match found */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos (0UL) /*!< Position of EVENTS_MHRMATCH field. */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Msk (0x1UL << RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Pos) /*!< Bit mask of EVENTS_MHRMATCH field. */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_MHRMATCH_EVENTS_MHRMATCH_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_SYNC */ -/* Description: Preamble indicator. */ - -/* Bit 0 : Preamble indicator. */ -#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos (0UL) /*!< Position of EVENTS_SYNC field. */ -#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Msk (0x1UL << RADIO_EVENTS_SYNC_EVENTS_SYNC_Pos) /*!< Bit mask of EVENTS_SYNC field. */ -#define RADIO_EVENTS_SYNC_EVENTS_SYNC_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_SYNC_EVENTS_SYNC_Generated (1UL) /*!< Event generated */ - -/* Register: RADIO_EVENTS_PHYEND */ -/* Description: Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ - -/* Bit 0 : Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air. */ -#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos (0UL) /*!< Position of EVENTS_PHYEND field. */ -#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Msk (0x1UL << RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Pos) /*!< Bit mask of EVENTS_PHYEND field. */ -#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_NotGenerated (0UL) /*!< Event not generated */ -#define RADIO_EVENTS_PHYEND_EVENTS_PHYEND_Generated (1UL) /*!< Event generated */ +/* Description: 2.4 GHz Radio */ /* Register: RADIO_SHORTS */ -/* Description: Shortcuts between local events and tasks */ - -/* Bit 21 : Shortcut between event PHYEND and task START */ -#define RADIO_SHORTS_PHYEND_START_Pos (21UL) /*!< Position of PHYEND_START field. */ -#define RADIO_SHORTS_PHYEND_START_Msk (0x1UL << RADIO_SHORTS_PHYEND_START_Pos) /*!< Bit mask of PHYEND_START field. */ -#define RADIO_SHORTS_PHYEND_START_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_PHYEND_START_Enabled (1UL) /*!< Enable shortcut */ +/* Description: Shortcut register */ -/* Bit 20 : Shortcut between event PHYEND and task DISABLE */ -#define RADIO_SHORTS_PHYEND_DISABLE_Pos (20UL) /*!< Position of PHYEND_DISABLE field. */ -#define RADIO_SHORTS_PHYEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_PHYEND_DISABLE_Pos) /*!< Bit mask of PHYEND_DISABLE field. */ -#define RADIO_SHORTS_PHYEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ -#define RADIO_SHORTS_PHYEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 19 : Shortcut between event RXREADY and task START */ +/* Bit 19 : Shortcut between RXREADY event and START task */ #define RADIO_SHORTS_RXREADY_START_Pos (19UL) /*!< Position of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Msk (0x1UL << RADIO_SHORTS_RXREADY_START_Pos) /*!< Bit mask of RXREADY_START field. */ #define RADIO_SHORTS_RXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 18 : Shortcut between event TXREADY and task START */ +/* Bit 18 : Shortcut between TXREADY event and START task */ #define RADIO_SHORTS_TXREADY_START_Pos (18UL) /*!< Position of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Msk (0x1UL << RADIO_SHORTS_TXREADY_START_Pos) /*!< Bit mask of TXREADY_START field. */ #define RADIO_SHORTS_TXREADY_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_TXREADY_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 17 : Shortcut between event CCAIDLE and task STOP */ +/* Bit 17 : Shortcut between CCAIDLE event and STOP task */ #define RADIO_SHORTS_CCAIDLE_STOP_Pos (17UL) /*!< Position of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_STOP_Pos) /*!< Bit mask of CCAIDLE_STOP field. */ #define RADIO_SHORTS_CCAIDLE_STOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 16 : Shortcut between event EDEND and task DISABLE */ +/* Bit 16 : Shortcut between EDEND event and DISABLE task */ #define RADIO_SHORTS_EDEND_DISABLE_Pos (16UL) /*!< Position of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Msk (0x1UL << RADIO_SHORTS_EDEND_DISABLE_Pos) /*!< Bit mask of EDEND_DISABLE field. */ #define RADIO_SHORTS_EDEND_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_EDEND_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 15 : Shortcut between event READY and task EDSTART */ +/* Bit 15 : Shortcut between READY event and EDSTART task */ #define RADIO_SHORTS_READY_EDSTART_Pos (15UL) /*!< Position of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Msk (0x1UL << RADIO_SHORTS_READY_EDSTART_Pos) /*!< Bit mask of READY_EDSTART field. */ #define RADIO_SHORTS_READY_EDSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_READY_EDSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 14 : Shortcut between event FRAMESTART and task BCSTART */ +/* Bit 14 : Shortcut between FRAMESTART event and BCSTART task */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Pos (14UL) /*!< Position of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Msk (0x1UL << RADIO_SHORTS_FRAMESTART_BCSTART_Pos) /*!< Bit mask of FRAMESTART_BCSTART field. */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_FRAMESTART_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between event CCABUSY and task DISABLE */ +/* Bit 13 : Shortcut between CCABUSY event and DISABLE task */ #define RADIO_SHORTS_CCABUSY_DISABLE_Pos (13UL) /*!< Position of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Msk (0x1UL << RADIO_SHORTS_CCABUSY_DISABLE_Pos) /*!< Bit mask of CCABUSY_DISABLE field. */ #define RADIO_SHORTS_CCABUSY_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCABUSY_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between event CCAIDLE and task TXEN */ +/* Bit 12 : Shortcut between CCAIDLE event and TXEN task */ #define RADIO_SHORTS_CCAIDLE_TXEN_Pos (12UL) /*!< Position of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Msk (0x1UL << RADIO_SHORTS_CCAIDLE_TXEN_Pos) /*!< Bit mask of CCAIDLE_TXEN field. */ #define RADIO_SHORTS_CCAIDLE_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_CCAIDLE_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between event RXREADY and task CCASTART */ +/* Bit 11 : Shortcut between RXREADY event and CCASTART task */ #define RADIO_SHORTS_RXREADY_CCASTART_Pos (11UL) /*!< Position of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Msk (0x1UL << RADIO_SHORTS_RXREADY_CCASTART_Pos) /*!< Bit mask of RXREADY_CCASTART field. */ #define RADIO_SHORTS_RXREADY_CCASTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_RXREADY_CCASTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between event DISABLED and task RSSISTOP */ +/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 6 : Shortcut between event ADDRESS and task BCSTART */ +/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between event END and task START */ +/* Bit 5 : Shortcut between END event and START task */ #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between event ADDRESS and task RSSISTART */ +/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event DISABLED and task RXEN */ +/* Bit 3 : Shortcut between DISABLED event and RXEN task */ #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event DISABLED and task TXEN */ +/* Bit 2 : Shortcut between DISABLED event and TXEN task */ #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event END and task DISABLE */ +/* Bit 1 : Shortcut between END event and DISABLE task */ #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event READY and task START */ +/* Bit 0 : Shortcut between READY event and START task */ #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ @@ -10422,161 +8850,147 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENSET */ /* Description: Enable interrupt */ -/* Bit 27 : Write '1' to enable interrupt for event PHYEND */ -#define RADIO_INTENSET_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ -#define RADIO_INTENSET_PHYEND_Msk (0x1UL << RADIO_INTENSET_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ -#define RADIO_INTENSET_PHYEND_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_PHYEND_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_PHYEND_Set (1UL) /*!< Enable */ - -/* Bit 26 : Write '1' to enable interrupt for event SYNC */ -#define RADIO_INTENSET_SYNC_Pos (26UL) /*!< Position of SYNC field. */ -#define RADIO_INTENSET_SYNC_Msk (0x1UL << RADIO_INTENSET_SYNC_Pos) /*!< Bit mask of SYNC field. */ -#define RADIO_INTENSET_SYNC_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENSET_SYNC_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENSET_SYNC_Set (1UL) /*!< Enable */ - -/* Bit 23 : Write '1' to enable interrupt for event MHRMATCH */ +/* Bit 23 : Write '1' to Enable interrupt for MHRMATCH event */ #define RADIO_INTENSET_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Msk (0x1UL << RADIO_INTENSET_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENSET_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_MHRMATCH_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for event RXREADY */ +/* Bit 22 : Write '1' to Enable interrupt for RXREADY event */ #define RADIO_INTENSET_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Msk (0x1UL << RADIO_INTENSET_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENSET_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RXREADY_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for event TXREADY */ +/* Bit 21 : Write '1' to Enable interrupt for TXREADY event */ #define RADIO_INTENSET_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Msk (0x1UL << RADIO_INTENSET_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENSET_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_TXREADY_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event RATEBOOST */ +/* Bit 20 : Write '1' to Enable interrupt for RATEBOOST event */ #define RADIO_INTENSET_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Msk (0x1UL << RADIO_INTENSET_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENSET_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RATEBOOST_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event CCASTOPPED */ +/* Bit 19 : Write '1' to Enable interrupt for CCASTOPPED event */ #define RADIO_INTENSET_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Msk (0x1UL << RADIO_INTENSET_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENSET_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCASTOPPED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event CCABUSY */ +/* Bit 18 : Write '1' to Enable interrupt for CCABUSY event */ #define RADIO_INTENSET_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Msk (0x1UL << RADIO_INTENSET_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENSET_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCABUSY_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for event CCAIDLE */ +/* Bit 17 : Write '1' to Enable interrupt for CCAIDLE event */ #define RADIO_INTENSET_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Msk (0x1UL << RADIO_INTENSET_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENSET_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CCAIDLE_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for event EDSTOPPED */ +/* Bit 16 : Write '1' to Enable interrupt for EDSTOPPED event */ #define RADIO_INTENSET_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Msk (0x1UL << RADIO_INTENSET_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENSET_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for event EDEND */ +/* Bit 15 : Write '1' to Enable interrupt for EDEND event */ #define RADIO_INTENSET_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENSET_EDEND_Msk (0x1UL << RADIO_INTENSET_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENSET_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_EDEND_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for event FRAMESTART */ +/* Bit 14 : Write '1' to Enable interrupt for FRAMESTART event */ #define RADIO_INTENSET_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Msk (0x1UL << RADIO_INTENSET_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENSET_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_FRAMESTART_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for event CRCERROR */ +/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for event CRCOK */ +/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for event BCMATCH */ +/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event RSSIEND */ +/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event DEVMISS */ +/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event DEVMATCH */ +/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event DISABLED */ +/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event END */ +/* Bit 3 : Write '1' to Enable interrupt for END event */ #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event PAYLOAD */ +/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event ADDRESS */ +/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event READY */ +/* Bit 0 : Write '1' to Enable interrupt for READY event */ #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10586,161 +9000,147 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 27 : Write '1' to disable interrupt for event PHYEND */ -#define RADIO_INTENCLR_PHYEND_Pos (27UL) /*!< Position of PHYEND field. */ -#define RADIO_INTENCLR_PHYEND_Msk (0x1UL << RADIO_INTENCLR_PHYEND_Pos) /*!< Bit mask of PHYEND field. */ -#define RADIO_INTENCLR_PHYEND_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_PHYEND_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_PHYEND_Clear (1UL) /*!< Disable */ - -/* Bit 26 : Write '1' to disable interrupt for event SYNC */ -#define RADIO_INTENCLR_SYNC_Pos (26UL) /*!< Position of SYNC field. */ -#define RADIO_INTENCLR_SYNC_Msk (0x1UL << RADIO_INTENCLR_SYNC_Pos) /*!< Bit mask of SYNC field. */ -#define RADIO_INTENCLR_SYNC_Disabled (0UL) /*!< Read: Disabled */ -#define RADIO_INTENCLR_SYNC_Enabled (1UL) /*!< Read: Enabled */ -#define RADIO_INTENCLR_SYNC_Clear (1UL) /*!< Disable */ - -/* Bit 23 : Write '1' to disable interrupt for event MHRMATCH */ +/* Bit 23 : Write '1' to Disable interrupt for MHRMATCH event */ #define RADIO_INTENCLR_MHRMATCH_Pos (23UL) /*!< Position of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Msk (0x1UL << RADIO_INTENCLR_MHRMATCH_Pos) /*!< Bit mask of MHRMATCH field. */ #define RADIO_INTENCLR_MHRMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_MHRMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_MHRMATCH_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for event RXREADY */ +/* Bit 22 : Write '1' to Disable interrupt for RXREADY event */ #define RADIO_INTENCLR_RXREADY_Pos (22UL) /*!< Position of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Msk (0x1UL << RADIO_INTENCLR_RXREADY_Pos) /*!< Bit mask of RXREADY field. */ #define RADIO_INTENCLR_RXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RXREADY_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for event TXREADY */ +/* Bit 21 : Write '1' to Disable interrupt for TXREADY event */ #define RADIO_INTENCLR_TXREADY_Pos (21UL) /*!< Position of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Msk (0x1UL << RADIO_INTENCLR_TXREADY_Pos) /*!< Bit mask of TXREADY field. */ #define RADIO_INTENCLR_TXREADY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_TXREADY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_TXREADY_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event RATEBOOST */ +/* Bit 20 : Write '1' to Disable interrupt for RATEBOOST event */ #define RADIO_INTENCLR_RATEBOOST_Pos (20UL) /*!< Position of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Msk (0x1UL << RADIO_INTENCLR_RATEBOOST_Pos) /*!< Bit mask of RATEBOOST field. */ #define RADIO_INTENCLR_RATEBOOST_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RATEBOOST_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RATEBOOST_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event CCASTOPPED */ +/* Bit 19 : Write '1' to Disable interrupt for CCASTOPPED event */ #define RADIO_INTENCLR_CCASTOPPED_Pos (19UL) /*!< Position of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Msk (0x1UL << RADIO_INTENCLR_CCASTOPPED_Pos) /*!< Bit mask of CCASTOPPED field. */ #define RADIO_INTENCLR_CCASTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCASTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCASTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event CCABUSY */ +/* Bit 18 : Write '1' to Disable interrupt for CCABUSY event */ #define RADIO_INTENCLR_CCABUSY_Pos (18UL) /*!< Position of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Msk (0x1UL << RADIO_INTENCLR_CCABUSY_Pos) /*!< Bit mask of CCABUSY field. */ #define RADIO_INTENCLR_CCABUSY_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCABUSY_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCABUSY_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for event CCAIDLE */ +/* Bit 17 : Write '1' to Disable interrupt for CCAIDLE event */ #define RADIO_INTENCLR_CCAIDLE_Pos (17UL) /*!< Position of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Msk (0x1UL << RADIO_INTENCLR_CCAIDLE_Pos) /*!< Bit mask of CCAIDLE field. */ #define RADIO_INTENCLR_CCAIDLE_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CCAIDLE_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CCAIDLE_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for event EDSTOPPED */ +/* Bit 16 : Write '1' to Disable interrupt for EDSTOPPED event */ #define RADIO_INTENCLR_EDSTOPPED_Pos (16UL) /*!< Position of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Msk (0x1UL << RADIO_INTENCLR_EDSTOPPED_Pos) /*!< Bit mask of EDSTOPPED field. */ #define RADIO_INTENCLR_EDSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for event EDEND */ +/* Bit 15 : Write '1' to Disable interrupt for EDEND event */ #define RADIO_INTENCLR_EDEND_Pos (15UL) /*!< Position of EDEND field. */ #define RADIO_INTENCLR_EDEND_Msk (0x1UL << RADIO_INTENCLR_EDEND_Pos) /*!< Bit mask of EDEND field. */ #define RADIO_INTENCLR_EDEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_EDEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_EDEND_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for event FRAMESTART */ +/* Bit 14 : Write '1' to Disable interrupt for FRAMESTART event */ #define RADIO_INTENCLR_FRAMESTART_Pos (14UL) /*!< Position of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Msk (0x1UL << RADIO_INTENCLR_FRAMESTART_Pos) /*!< Bit mask of FRAMESTART field. */ #define RADIO_INTENCLR_FRAMESTART_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_FRAMESTART_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_FRAMESTART_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for event CRCERROR */ +/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for event CRCOK */ +/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for event BCMATCH */ +/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event RSSIEND */ +/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event DEVMISS */ +/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event DEVMATCH */ +/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event DISABLED */ +/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event END */ +/* Bit 3 : Write '1' to Disable interrupt for END event */ #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event PAYLOAD */ +/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event ADDRESS */ +/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event READY */ +/* Bit 0 : Write '1' to Disable interrupt for READY event */ #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -10777,21 +9177,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ -/* Register: RADIO_PDUSTAT */ -/* Description: Payload status */ - -/* Bits 2..1 : Status on what rate packet is received with in Long Range */ -#define RADIO_PDUSTAT_CISTAT_Pos (1UL) /*!< Position of CISTAT field. */ -#define RADIO_PDUSTAT_CISTAT_Msk (0x3UL << RADIO_PDUSTAT_CISTAT_Pos) /*!< Bit mask of CISTAT field. */ -#define RADIO_PDUSTAT_CISTAT_LR125kbit (0UL) /*!< Frame is received at 125kbps */ -#define RADIO_PDUSTAT_CISTAT_LR500kbit (1UL) /*!< Frame is received at 500kbps */ - -/* Bit 0 : Status on payload length vs. PCNF1.MAXLEN */ -#define RADIO_PDUSTAT_PDUSTAT_Pos (0UL) /*!< Position of PDUSTAT field. */ -#define RADIO_PDUSTAT_PDUSTAT_Msk (0x1UL << RADIO_PDUSTAT_PDUSTAT_Pos) /*!< Bit mask of PDUSTAT field. */ -#define RADIO_PDUSTAT_PDUSTAT_LessThan (0UL) /*!< Payload less than PCNF1.MAXLEN */ -#define RADIO_PDUSTAT_PDUSTAT_GreaterThan (1UL) /*!< Payload greater than PCNF1.MAXLEN */ - /* Register: RADIO_PACKETPTR */ /* Description: Packet pointer */ @@ -10815,7 +9200,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_TXPOWER */ /* Description: Output power */ -/* Bits 7..0 : RADIO output power */ +/* Bits 7..0 : RADIO output power. */ #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ #define RADIO_TXPOWER_TXPOWER_0dBm (0x0UL) /*!< 0 dBm */ @@ -10826,8 +9211,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_Pos6dBm (0x6UL) /*!< +6 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos7dBm (0x7UL) /*!< +7 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos8dBm (0x8UL) /*!< +8 dBm */ +#define RADIO_TXPOWER_TXPOWER_Pos9dBm (0x9UL) /*!< +9 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xE2UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ @@ -10837,15 +9223,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ -/* Bits 3..0 : Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. */ +/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ -#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s BLE */ -#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s BLE */ -#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ -#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX */ +#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ +#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ +#define RADIO_MODE_MODE_Ble_LR125Kbit (5UL) /*!< Long range 125 kbit/s (TX Only - RX supports both) */ +#define RADIO_MODE_MODE_Ble_LR500Kbit (6UL) /*!< Long range 500 kbit/s (TX Only - RX supports both) */ #define RADIO_MODE_MODE_Ieee802154_250Kbit (15UL) /*!< IEEE 802.15.4-2006 250 kbit/s */ /* Register: RADIO_PCNF0 */ @@ -10867,9 +9254,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ #define RADIO_PCNF0_PLEN_32bitZero (2UL) /*!< 32-bit zero preamble - used for IEEE 802.15.4 */ -#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BLE long range */ +#define RADIO_PCNF0_PLEN_LongRange (3UL) /*!< Preamble - used for BTLE Long Range */ -/* Bits 23..22 : Length of code indicator - long range */ +/* Bits 23..22 : Length of Code Indicator - Long Range */ #define RADIO_PCNF0_CILEN_Pos (22UL) /*!< Position of CILEN field. */ #define RADIO_PCNF0_CILEN_Msk (0x3UL << RADIO_PCNF0_CILEN_Pos) /*!< Bit mask of CILEN field. */ @@ -10903,7 +9290,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ +#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ /* Bits 18..16 : Base address length in number of bytes */ @@ -11061,9 +9448,9 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ /* Register: RADIO_TIFS */ -/* Description: Interframe spacing in us */ +/* Description: Inter Frame Spacing in us */ -/* Bits 9..0 : Interframe spacing in us */ +/* Bits 9..0 : Inter Frame Spacing in us */ #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ #define RADIO_TIFS_TIFS_Msk (0x3FFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ @@ -11105,16 +9492,16 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ /* Register: RADIO_DAB */ -/* Description: Description collection: Device address base segment n */ +/* Description: Description collection[0]: Device address base segment 0 */ -/* Bits 31..0 : Device address base segment n */ +/* Bits 31..0 : Device address base segment 0 */ #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ /* Register: RADIO_DAP */ -/* Description: Description collection: Device address prefix n */ +/* Description: Description collection[0]: Device address prefix 0 */ -/* Bits 15..0 : Device address prefix n */ +/* Bits 15..0 : Device address prefix 0 */ #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ @@ -11201,20 +9588,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ -/* Register: RADIO_MHRMATCHCONF */ -/* Description: Search pattern configuration */ - -/* Bits 31..0 : Search pattern configuration */ -#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos (0UL) /*!< Position of MHRMATCHCONF field. */ -#define RADIO_MHRMATCHCONF_MHRMATCHCONF_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHCONF_MHRMATCHCONF_Pos) /*!< Bit mask of MHRMATCHCONF field. */ - -/* Register: RADIO_MHRMATCHMAS */ -/* Description: Pattern mask */ - -/* Bits 31..0 : Pattern mask */ -#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos (0UL) /*!< Position of MHRMATCHMAS field. */ -#define RADIO_MHRMATCHMAS_MHRMATCHMAS_Msk (0xFFFFFFFFUL << RADIO_MHRMATCHMAS_MHRMATCHMAS_Pos) /*!< Bit mask of MHRMATCHMAS field. */ - /* Register: RADIO_MODECNF0 */ /* Description: Radio mode configuration register 0 */ @@ -11228,53 +9601,53 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Radio ramp-up time */ #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ -#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51 */ -#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information */ +#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ +#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ /* Register: RADIO_SFD */ -/* Description: IEEE 802.15.4 start of frame delimiter */ +/* Description: IEEE 802.15.4 Start of Frame Delimiter */ -/* Bits 7..0 : IEEE 802.15.4 start of frame delimiter */ +/* Bits 7..0 : IEEE 802.15.4 Start of Frame Delimiter */ #define RADIO_SFD_SFD_Pos (0UL) /*!< Position of SFD field. */ #define RADIO_SFD_SFD_Msk (0xFFUL << RADIO_SFD_SFD_Pos) /*!< Bit mask of SFD field. */ /* Register: RADIO_EDCNT */ -/* Description: IEEE 802.15.4 energy detect loop count */ +/* Description: IEEE 802.15.4 Energy Detect Loop Count */ -/* Bits 20..0 : IEEE 802.15.4 energy detect loop count */ +/* Bits 20..0 : IEEE 802.15.4 Energy Detect Loop Count */ #define RADIO_EDCNT_EDCNT_Pos (0UL) /*!< Position of EDCNT field. */ #define RADIO_EDCNT_EDCNT_Msk (0x1FFFFFUL << RADIO_EDCNT_EDCNT_Pos) /*!< Bit mask of EDCNT field. */ /* Register: RADIO_EDSAMPLE */ -/* Description: IEEE 802.15.4 energy detect level */ +/* Description: IEEE 802.15.4 Energy Detect Level */ -/* Bits 7..0 : IEEE 802.15.4 energy detect level */ +/* Bits 7..0 : IEEE 802.15.4 Energy Detect Level */ #define RADIO_EDSAMPLE_EDLVL_Pos (0UL) /*!< Position of EDLVL field. */ #define RADIO_EDSAMPLE_EDLVL_Msk (0xFFUL << RADIO_EDSAMPLE_EDLVL_Pos) /*!< Bit mask of EDLVL field. */ /* Register: RADIO_CCACTRL */ -/* Description: IEEE 802.15.4 clear channel assessment control */ +/* Description: IEEE 802.15.4 Clear Channel Assessment Control */ /* Bits 31..24 : Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. */ #define RADIO_CCACTRL_CCACORRCNT_Pos (24UL) /*!< Position of CCACORRCNT field. */ #define RADIO_CCACTRL_CCACORRCNT_Msk (0xFFUL << RADIO_CCACTRL_CCACORRCNT_Pos) /*!< Bit mask of CCACORRCNT field. */ -/* Bits 23..16 : CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ +/* Bits 23..16 : CCA Correlator Busy Threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. */ #define RADIO_CCACTRL_CCACORRTHRES_Pos (16UL) /*!< Position of CCACORRTHRES field. */ #define RADIO_CCACTRL_CCACORRTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCACORRTHRES_Pos) /*!< Bit mask of CCACORRTHRES field. */ -/* Bits 15..8 : CCA energy busy threshold. Used in all the CCA modes except CarrierMode. */ +/* Bits 15..8 : CCA Energy Busy Threshold. Used in all the CCA modes except CarrierMode. */ #define RADIO_CCACTRL_CCAEDTHRES_Pos (8UL) /*!< Position of CCAEDTHRES field. */ #define RADIO_CCACTRL_CCAEDTHRES_Msk (0xFFUL << RADIO_CCACTRL_CCAEDTHRES_Pos) /*!< Bit mask of CCAEDTHRES field. */ -/* Bits 2..0 : CCA mode of operation */ +/* Bits 2..0 : CCA Mode Of Operation */ #define RADIO_CCACTRL_CCAMODE_Pos (0UL) /*!< Position of CCAMODE field. */ #define RADIO_CCACTRL_CCAMODE_Msk (0x7UL << RADIO_CCACTRL_CCAMODE_Pos) /*!< Bit mask of CCAMODE field. */ -#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy above threshold */ -#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier seen */ -#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy above threshold AND carrier seen */ -#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy above threshold OR carrier seen */ -#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ +#define RADIO_CCACTRL_CCAMODE_EdMode (0UL) /*!< Energy Above Threshold */ +#define RADIO_CCACTRL_CCAMODE_CarrierMode (1UL) /*!< Carrier Seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierAndEdMode (2UL) /*!< Energy Above Threshold AND Carrier Seen */ +#define RADIO_CCACTRL_CCAMODE_CarrierOrEdMode (3UL) /*!< Energy Above Threshold OR Carrier Seen */ +#define RADIO_CCACTRL_CCAMODE_EdModeTest1 (4UL) /*!< Energy Above Threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. */ /* Register: RADIO_POWER */ /* Description: Peripheral power control */ @@ -11289,35 +9662,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: RNG */ /* Description: Random Number Generator */ -/* Register: RNG_TASKS_START */ -/* Description: Task starting the random number generator */ - -/* Bit 0 : Task starting the random number generator */ -#define RNG_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define RNG_TASKS_START_TASKS_START_Msk (0x1UL << RNG_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define RNG_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: RNG_TASKS_STOP */ -/* Description: Task stopping the random number generator */ - -/* Bit 0 : Task stopping the random number generator */ -#define RNG_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define RNG_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RNG_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define RNG_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RNG_EVENTS_VALRDY */ -/* Description: Event being generated for every new random number written to the VALUE register */ - -/* Bit 0 : Event being generated for every new random number written to the VALUE register */ -#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos (0UL) /*!< Position of EVENTS_VALRDY field. */ -#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Msk (0x1UL << RNG_EVENTS_VALRDY_EVENTS_VALRDY_Pos) /*!< Bit mask of EVENTS_VALRDY field. */ -#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_NotGenerated (0UL) /*!< Event not generated */ -#define RNG_EVENTS_VALRDY_EVENTS_VALRDY_Generated (1UL) /*!< Event generated */ - /* Register: RNG_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 0 : Shortcut between event VALRDY and task STOP */ +/* Bit 0 : Shortcut between VALRDY event and STOP task */ #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ @@ -11326,7 +9674,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for event VALRDY */ +/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11336,7 +9684,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RNG_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for event VALRDY */ +/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ @@ -11363,104 +9711,45 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: RTC */ /* Description: Real time counter 0 */ -/* Register: RTC_TASKS_START */ -/* Description: Start RTC COUNTER */ - -/* Bit 0 : Start RTC COUNTER */ -#define RTC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define RTC_TASKS_START_TASKS_START_Msk (0x1UL << RTC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define RTC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: RTC_TASKS_STOP */ -/* Description: Stop RTC COUNTER */ - -/* Bit 0 : Stop RTC COUNTER */ -#define RTC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define RTC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << RTC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define RTC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: RTC_TASKS_CLEAR */ -/* Description: Clear RTC COUNTER */ - -/* Bit 0 : Clear RTC COUNTER */ -#define RTC_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ -#define RTC_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << RTC_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ -#define RTC_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ - -/* Register: RTC_TASKS_TRIGOVRFLW */ -/* Description: Set COUNTER to 0xFFFFF0 */ - -/* Bit 0 : Set COUNTER to 0xFFFFF0 */ -#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos (0UL) /*!< Position of TASKS_TRIGOVRFLW field. */ -#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Msk (0x1UL << RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Pos) /*!< Bit mask of TASKS_TRIGOVRFLW field. */ -#define RTC_TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Trigger (1UL) /*!< Trigger task */ - -/* Register: RTC_EVENTS_TICK */ -/* Description: Event on COUNTER increment */ - -/* Bit 0 : Event on COUNTER increment */ -#define RTC_EVENTS_TICK_EVENTS_TICK_Pos (0UL) /*!< Position of EVENTS_TICK field. */ -#define RTC_EVENTS_TICK_EVENTS_TICK_Msk (0x1UL << RTC_EVENTS_TICK_EVENTS_TICK_Pos) /*!< Bit mask of EVENTS_TICK field. */ -#define RTC_EVENTS_TICK_EVENTS_TICK_NotGenerated (0UL) /*!< Event not generated */ -#define RTC_EVENTS_TICK_EVENTS_TICK_Generated (1UL) /*!< Event generated */ - -/* Register: RTC_EVENTS_OVRFLW */ -/* Description: Event on COUNTER overflow */ - -/* Bit 0 : Event on COUNTER overflow */ -#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos (0UL) /*!< Position of EVENTS_OVRFLW field. */ -#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Msk (0x1UL << RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Pos) /*!< Bit mask of EVENTS_OVRFLW field. */ -#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_NotGenerated (0UL) /*!< Event not generated */ -#define RTC_EVENTS_OVRFLW_EVENTS_OVRFLW_Generated (1UL) /*!< Event generated */ - -/* Register: RTC_EVENTS_COMPARE */ -/* Description: Description collection: Compare event on CC[n] match */ - -/* Bit 0 : Compare event on CC[n] match */ -#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ -#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << RTC_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ -#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ -#define RTC_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ - /* Register: RTC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event OVRFLW */ +/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event TICK */ +/* Bit 0 : Write '1' to Enable interrupt for TICK event */ #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11470,42 +9759,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event OVRFLW */ +/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event TICK */ +/* Bit 0 : Write '1' to Disable interrupt for TICK event */ #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11515,81 +9804,81 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTEN */ /* Description: Enable or disable event routing */ -/* Bit 19 : Enable or disable event routing for event COMPARE[3] */ +/* Bit 19 : Enable or disable event routing for COMPARE[3] event */ #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable event routing for event COMPARE[2] */ +/* Bit 18 : Enable or disable event routing for COMPARE[2] event */ #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable event routing for event COMPARE[1] */ +/* Bit 17 : Enable or disable event routing for COMPARE[1] event */ #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable event routing for event COMPARE[0] */ +/* Bit 16 : Enable or disable event routing for COMPARE[0] event */ #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable event routing for event OVRFLW */ +/* Bit 1 : Enable or disable event routing for OVRFLW event */ #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable event routing for event TICK */ +/* Bit 0 : Enable or disable event routing for TICK event */ #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Disable */ +#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ /* Register: RTC_EVTENSET */ /* Description: Enable event routing */ -/* Bit 19 : Write '1' to enable event routing for event COMPARE[3] */ +/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable event routing for event COMPARE[2] */ +/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable event routing for event COMPARE[1] */ +/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable event routing for event COMPARE[0] */ +/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable event routing for event OVRFLW */ +/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable event routing for event TICK */ +/* Bit 0 : Write '1' to Enable event routing for TICK event */ #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11599,42 +9888,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: RTC_EVTENCLR */ /* Description: Disable event routing */ -/* Bit 19 : Write '1' to disable event routing for event COMPARE[3] */ +/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable event routing for event COMPARE[2] */ +/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable event routing for event COMPARE[1] */ +/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable event routing for event COMPARE[0] */ +/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable event routing for event OVRFLW */ +/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable event routing for event TICK */ +/* Bit 0 : Write '1' to Disable event routing for TICK event */ #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ @@ -11656,7 +9945,7 @@ POSSIBILITY OF SUCH DAMAGE. #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: RTC_CC */ -/* Description: Description collection: Compare register n */ +/* Description: Description collection[0]: Compare register 0 */ /* Bits 23..0 : Compare value */ #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ @@ -11664,242 +9953,138 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: SAADC */ -/* Description: Successive approximation register (SAR) analog-to-digital converter */ - -/* Register: SAADC_TASKS_START */ -/* Description: Starts the SAADC and prepares the result buffer in RAM */ - -/* Bit 0 : Starts the SAADC and prepares the result buffer in RAM */ -#define SAADC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define SAADC_TASKS_START_TASKS_START_Msk (0x1UL << SAADC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define SAADC_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: SAADC_TASKS_SAMPLE */ -/* Description: Takes one SAADC sample */ - -/* Bit 0 : Takes one SAADC sample */ -#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos (0UL) /*!< Position of TASKS_SAMPLE field. */ -#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Msk (0x1UL << SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Pos) /*!< Bit mask of TASKS_SAMPLE field. */ -#define SAADC_TASKS_SAMPLE_TASKS_SAMPLE_Trigger (1UL) /*!< Trigger task */ - -/* Register: SAADC_TASKS_STOP */ -/* Description: Stops the SAADC and terminates all on-going conversions */ - -/* Bit 0 : Stops the SAADC and terminates all on-going conversions */ -#define SAADC_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define SAADC_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SAADC_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define SAADC_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: SAADC_TASKS_CALIBRATEOFFSET */ -/* Description: Starts offset auto-calibration */ - -/* Bit 0 : Starts offset auto-calibration */ -#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos (0UL) /*!< Position of TASKS_CALIBRATEOFFSET field. */ -#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Msk (0x1UL << SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Pos) /*!< Bit mask of TASKS_CALIBRATEOFFSET field. */ -#define SAADC_TASKS_CALIBRATEOFFSET_TASKS_CALIBRATEOFFSET_Trigger (1UL) /*!< Trigger task */ - -/* Register: SAADC_EVENTS_STARTED */ -/* Description: The SAADC has started */ - -/* Bit 0 : The SAADC has started */ -#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ -#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SAADC_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define SAADC_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_END */ -/* Description: The SAADC has filled up the result buffer */ - -/* Bit 0 : The SAADC has filled up the result buffer */ -#define SAADC_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ -#define SAADC_EVENTS_END_EVENTS_END_Msk (0x1UL << SAADC_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define SAADC_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_DONE */ -/* Description: A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ - -/* Bit 0 : A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. */ -#define SAADC_EVENTS_DONE_EVENTS_DONE_Pos (0UL) /*!< Position of EVENTS_DONE field. */ -#define SAADC_EVENTS_DONE_EVENTS_DONE_Msk (0x1UL << SAADC_EVENTS_DONE_EVENTS_DONE_Pos) /*!< Bit mask of EVENTS_DONE field. */ -#define SAADC_EVENTS_DONE_EVENTS_DONE_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_DONE_EVENTS_DONE_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_RESULTDONE */ -/* Description: Result ready for transfer to RAM */ - -/* Bit 0 : Result ready for transfer to RAM */ -#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos (0UL) /*!< Position of EVENTS_RESULTDONE field. */ -#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Msk (0x1UL << SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Pos) /*!< Bit mask of EVENTS_RESULTDONE field. */ -#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_RESULTDONE_EVENTS_RESULTDONE_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_CALIBRATEDONE */ -/* Description: Calibration is complete */ - -/* Bit 0 : Calibration is complete */ -#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos (0UL) /*!< Position of EVENTS_CALIBRATEDONE field. */ -#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Msk (0x1UL << SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Pos) /*!< Bit mask of EVENTS_CALIBRATEDONE field. */ -#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_CALIBRATEDONE_EVENTS_CALIBRATEDONE_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_STOPPED */ -/* Description: The SAADC has stopped */ - -/* Bit 0 : The SAADC has stopped */ -#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_CH_LIMITH */ -/* Description: Description cluster: Last result is equal or above CH[n].LIMIT.HIGH */ - -/* Bit 0 : Last result is equal or above CH[n].LIMIT.HIGH */ -#define SAADC_EVENTS_CH_LIMITH_LIMITH_Pos (0UL) /*!< Position of LIMITH field. */ -#define SAADC_EVENTS_CH_LIMITH_LIMITH_Msk (0x1UL << SAADC_EVENTS_CH_LIMITH_LIMITH_Pos) /*!< Bit mask of LIMITH field. */ -#define SAADC_EVENTS_CH_LIMITH_LIMITH_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_CH_LIMITH_LIMITH_Generated (1UL) /*!< Event generated */ - -/* Register: SAADC_EVENTS_CH_LIMITL */ -/* Description: Description cluster: Last result is equal or below CH[n].LIMIT.LOW */ - -/* Bit 0 : Last result is equal or below CH[n].LIMIT.LOW */ -#define SAADC_EVENTS_CH_LIMITL_LIMITL_Pos (0UL) /*!< Position of LIMITL field. */ -#define SAADC_EVENTS_CH_LIMITL_LIMITL_Msk (0x1UL << SAADC_EVENTS_CH_LIMITL_LIMITL_Pos) /*!< Bit mask of LIMITL field. */ -#define SAADC_EVENTS_CH_LIMITL_LIMITL_NotGenerated (0UL) /*!< Event not generated */ -#define SAADC_EVENTS_CH_LIMITL_LIMITL_Generated (1UL) /*!< Event generated */ +/* Description: Analog to Digital Converter */ /* Register: SAADC_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 21 : Enable or disable interrupt for event CH7LIMITL */ +/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for event CH7LIMITH */ +/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for event CH6LIMITL */ +/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for event CH6LIMITH */ +/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for event CH5LIMITL */ +/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for event CH5LIMITH */ +/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for event CH4LIMITL */ +/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for event CH4LIMITH */ +/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for event CH3LIMITL */ +/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for event CH3LIMITH */ +/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for event CH2LIMITL */ +/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for event CH2LIMITH */ +/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for event CH1LIMITL */ +/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for event CH1LIMITH */ +/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event CH0LIMITL */ +/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event CH0LIMITH */ +/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event STOPPED */ +/* Bit 5 : Enable or disable interrupt for STOPPED event */ #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event CALIBRATEDONE */ +/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event RESULTDONE */ +/* Bit 3 : Enable or disable interrupt for RESULTDONE event */ #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event DONE */ +/* Bit 2 : Enable or disable interrupt for DONE event */ #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event END */ +/* Bit 1 : Enable or disable interrupt for END event */ #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event STARTED */ +/* Bit 0 : Enable or disable interrupt for STARTED event */ #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ @@ -11908,154 +10093,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for event CH7LIMITL */ +/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event CH7LIMITH */ +/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event CH6LIMITL */ +/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event CH6LIMITH */ +/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for event CH5LIMITL */ +/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for event CH5LIMITH */ +/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for event CH4LIMITL */ +/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for event CH4LIMITH */ +/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for event CH3LIMITL */ +/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for event CH3LIMITH */ +/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for event CH2LIMITL */ +/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for event CH2LIMITH */ +/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event CH1LIMITL */ +/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for event CH1LIMITH */ +/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event CH0LIMITL */ +/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event CH0LIMITH */ +/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event CALIBRATEDONE */ +/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event RESULTDONE */ +/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event DONE */ +/* Bit 2 : Write '1' to Enable interrupt for DONE event */ #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event END */ +/* Bit 1 : Write '1' to Enable interrupt for END event */ #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event STARTED */ +/* Bit 0 : Write '1' to Enable interrupt for STARTED event */ #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -12065,154 +10250,154 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SAADC_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for event CH7LIMITL */ +/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event CH7LIMITH */ +/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event CH6LIMITL */ +/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event CH6LIMITH */ +/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for event CH5LIMITL */ +/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for event CH5LIMITH */ +/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for event CH4LIMITL */ +/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for event CH4LIMITH */ +/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for event CH3LIMITL */ +/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for event CH3LIMITH */ +/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for event CH2LIMITL */ +/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for event CH2LIMITH */ +/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event CH1LIMITL */ +/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for event CH1LIMITH */ +/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event CH0LIMITL */ +/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event CH0LIMITH */ +/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event CALIBRATEDONE */ +/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event RESULTDONE */ +/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event DONE */ +/* Bit 2 : Write '1' to Disable interrupt for DONE event */ #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event END */ +/* Bit 1 : Write '1' to Disable interrupt for END event */ #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event STARTED */ +/* Bit 0 : Write '1' to Disable interrupt for STARTED event */ #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ @@ -12225,20 +10410,20 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Status */ #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define SAADC_STATUS_STATUS_Ready (0UL) /*!< SAADC is ready. No on-going conversions. */ -#define SAADC_STATUS_STATUS_Busy (1UL) /*!< SAADC is busy. Conversion in progress. */ +#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ +#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ /* Register: SAADC_ENABLE */ -/* Description: Enable or disable SAADC */ +/* Description: Enable or disable ADC */ -/* Bit 0 : Enable or disable SAADC */ +/* Bit 0 : Enable or disable ADC */ #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SAADC */ -#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SAADC */ +#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ +#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ /* Register: SAADC_CH_PSELP */ -/* Description: Description cluster: Input positive pin selection for CH[n] */ +/* Description: Description cluster[0]: Input positive pin selection for CH[0] */ /* Bits 4..0 : Analog positive input channel */ #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ @@ -12253,10 +10438,10 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ -#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ +#define SAADC_CH_PSELP_PSELP_VDDHDIV5 (0x11UL) /*!< VDDH/5 */ /* Register: SAADC_CH_PSELN */ -/* Description: Description cluster: Input negative pin selection for CH[n] */ +/* Description: Description cluster[0]: Input negative pin selection for CH[0] */ /* Bits 4..0 : Analog negative input, enables differential channel */ #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ @@ -12271,10 +10456,10 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ -#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x0DUL) /*!< VDDH/5 */ +#define SAADC_CH_PSELN_PSELN_VDDHDIV5 (0x11UL) /*!< VDDH/5 */ /* Register: SAADC_CH_CONFIG */ -/* Description: Description cluster: Input configuration for CH[n] */ +/* Description: Description cluster[0]: Input configuration for CH[0] */ /* Bit 24 : Enable burst mode */ #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ @@ -12285,10 +10470,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 20 : Enable differential mode */ #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND */ +#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ -/* Bits 18..16 : Acquisition time, the time the SAADC uses to sample the input voltage */ +/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ @@ -12333,7 +10518,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ /* Register: SAADC_CH_LIMIT */ -/* Description: Description cluster: High/low limits for event monitoring of a channel */ +/* Description: Description cluster[0]: High/low limits for event monitoring a channel */ /* Bits 31..16 : High level limit */ #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ @@ -12349,13 +10534,13 @@ POSSIBILITY OF SUCH DAMAGE. /* Bits 2..0 : Set the resolution */ #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ -#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bits */ -#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bits */ -#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bits */ -#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bits */ +#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ +#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ +#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ +#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ /* Register: SAADC_OVERSAMPLE */ -/* Description: Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ +/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ /* Bits 3..0 : Oversample control */ #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ @@ -12391,16 +10576,16 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: SAADC_RESULT_MAXCNT */ -/* Description: Maximum number of 16-bit samples to be written to output RAM buffer */ +/* Description: Maximum number of buffer words to transfer */ -/* Bits 14..0 : Maximum number of 16-bit samples to be written to output RAM buffer */ +/* Bits 14..0 : Maximum number of buffer words to transfer */ #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: SAADC_RESULT_AMOUNT */ -/* Description: Number of 16-bit samples written to output RAM buffer since the previous START task */ +/* Description: Number of buffer words transferred since last START */ -/* Bits 14..0 : Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. */ +/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ @@ -12408,19 +10593,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: SPI */ /* Description: Serial Peripheral Interface 0 */ -/* Register: SPI_EVENTS_READY */ -/* Description: TXD byte sent and RXD byte received */ - -/* Bit 0 : TXD byte sent and RXD byte received */ -#define SPI_EVENTS_READY_EVENTS_READY_Pos (0UL) /*!< Position of EVENTS_READY field. */ -#define SPI_EVENTS_READY_EVENTS_READY_Msk (0x1UL << SPI_EVENTS_READY_EVENTS_READY_Pos) /*!< Bit mask of EVENTS_READY field. */ -#define SPI_EVENTS_READY_EVENTS_READY_NotGenerated (0UL) /*!< Event not generated */ -#define SPI_EVENTS_READY_EVENTS_READY_Generated (1UL) /*!< Event generated */ - /* Register: SPI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 2 : Write '1' to enable interrupt for event READY */ +/* Bit 2 : Write '1' to Enable interrupt for READY event */ #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12430,7 +10606,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 2 : Write '1' to disable interrupt for event READY */ +/* Bit 2 : Write '1' to Disable interrupt for READY event */ #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ @@ -12455,9 +10631,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPI_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ #define SPI_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPI_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPI_PSEL_SCK_PORT_Msk (0x1UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPI_PSEL_SCK_PORT_Msk (0x3UL << SPI_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPI_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12472,9 +10648,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPI_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ #define SPI_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPI_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPI_PSEL_MOSI_PORT_Msk (0x1UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPI_PSEL_MOSI_PORT_Msk (0x3UL << SPI_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPI_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12489,9 +10665,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPI_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ #define SPI_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPI_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPI_PSEL_MISO_PORT_Msk (0x1UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPI_PSEL_MISO_PORT_Msk (0x3UL << SPI_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPI_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12550,87 +10726,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: SPIM */ /* Description: Serial Peripheral Interface Master with EasyDMA 0 */ -/* Register: SPIM_TASKS_START */ -/* Description: Start SPI transaction */ - -/* Bit 0 : Start SPI transaction */ -#define SPIM_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define SPIM_TASKS_START_TASKS_START_Msk (0x1UL << SPIM_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define SPIM_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: SPIM_TASKS_STOP */ -/* Description: Stop SPI transaction */ - -/* Bit 0 : Stop SPI transaction */ -#define SPIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define SPIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << SPIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define SPIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: SPIM_TASKS_SUSPEND */ -/* Description: Suspend SPI transaction */ - -/* Bit 0 : Suspend SPI transaction */ -#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ -#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define SPIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ - -/* Register: SPIM_TASKS_RESUME */ -/* Description: Resume SPI transaction */ - -/* Bit 0 : Resume SPI transaction */ -#define SPIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ -#define SPIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << SPIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define SPIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ - -/* Register: SPIM_EVENTS_STOPPED */ -/* Description: SPI transaction has stopped */ - -/* Bit 0 : SPI transaction has stopped */ -#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: SPIM_EVENTS_ENDRX */ -/* Description: End of RXD buffer reached */ - -/* Bit 0 : End of RXD buffer reached */ -#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ -#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ - -/* Register: SPIM_EVENTS_END */ -/* Description: End of RXD buffer and TXD buffer reached */ - -/* Bit 0 : End of RXD buffer and TXD buffer reached */ -#define SPIM_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ -#define SPIM_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIM_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define SPIM_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ - -/* Register: SPIM_EVENTS_ENDTX */ -/* Description: End of TXD buffer reached */ - -/* Bit 0 : End of TXD buffer reached */ -#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ -#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ -#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ - -/* Register: SPIM_EVENTS_STARTED */ -/* Description: Transaction started */ - -/* Bit 0 : Transaction started */ -#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ -#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << SPIM_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define SPIM_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define SPIM_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ - /* Register: SPIM_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 17 : Shortcut between event END and task START */ +/* Bit 17 : Shortcut between END event and START task */ #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ @@ -12639,35 +10738,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 19 : Write '1' to enable interrupt for event STARTED */ +/* Bit 19 : Write '1' to Enable interrupt for STARTED event */ #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event END */ +/* Bit 6 : Write '1' to Enable interrupt for END event */ #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12677,35 +10776,35 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 19 : Write '1' to disable interrupt for event STARTED */ +/* Bit 19 : Write '1' to Disable interrupt for STARTED event */ #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event END */ +/* Bit 6 : Write '1' to Disable interrupt for END event */ #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -12745,9 +10844,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIM_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIM_PSEL_SCK_PORT_Msk (0x1UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIM_PSEL_SCK_PORT_Msk (0x3UL << SPIM_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12762,9 +10861,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIM_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIM_PSEL_MOSI_PORT_Msk (0x1UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIM_PSEL_MOSI_PORT_Msk (0x3UL << SPIM_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12779,9 +10878,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIM_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIM_PSEL_MISO_PORT_Msk (0x1UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIM_PSEL_MISO_PORT_Msk (0x3UL << SPIM_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12796,9 +10895,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ #define SPIM_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIM_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIM_PSEL_CSN_PORT_Msk (0x1UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIM_PSEL_CSN_PORT_Msk (0x3UL << SPIM_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIM_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -12915,39 +11014,6 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_IFTIMING_CSNDUR_CSNDUR_Pos (0UL) /*!< Position of CSNDUR field. */ #define SPIM_IFTIMING_CSNDUR_CSNDUR_Msk (0xFFUL << SPIM_IFTIMING_CSNDUR_CSNDUR_Pos) /*!< Bit mask of CSNDUR field. */ -/* Register: SPIM_CSNPOL */ -/* Description: Polarity of CSN output */ - -/* Bit 0 : Polarity of CSN output */ -#define SPIM_CSNPOL_CSNPOL_Pos (0UL) /*!< Position of CSNPOL field. */ -#define SPIM_CSNPOL_CSNPOL_Msk (0x1UL << SPIM_CSNPOL_CSNPOL_Pos) /*!< Bit mask of CSNPOL field. */ -#define SPIM_CSNPOL_CSNPOL_LOW (0UL) /*!< Active low (idle state high) */ -#define SPIM_CSNPOL_CSNPOL_HIGH (1UL) /*!< Active high (idle state low) */ - -/* Register: SPIM_PSELDCX */ -/* Description: Pin select for DCX signal */ - -/* Bit 31 : Connection */ -#define SPIM_PSELDCX_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ -#define SPIM_PSELDCX_CONNECT_Msk (0x1UL << SPIM_PSELDCX_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ -#define SPIM_PSELDCX_CONNECT_Connected (0UL) /*!< Connect */ -#define SPIM_PSELDCX_CONNECT_Disconnected (1UL) /*!< Disconnect */ - -/* Bit 5 : Port number */ -#define SPIM_PSELDCX_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIM_PSELDCX_PORT_Msk (0x1UL << SPIM_PSELDCX_PORT_Pos) /*!< Bit mask of PORT field. */ - -/* Bits 4..0 : Pin number */ -#define SPIM_PSELDCX_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define SPIM_PSELDCX_PIN_Msk (0x1FUL << SPIM_PSELDCX_PIN_Pos) /*!< Bit mask of PIN field. */ - -/* Register: SPIM_DCXCNT */ -/* Description: DCX configuration */ - -/* Bits 3..0 : This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. */ -#define SPIM_DCXCNT_DCXCNT_Pos (0UL) /*!< Position of DCXCNT field. */ -#define SPIM_DCXCNT_DCXCNT_Msk (0xFUL << SPIM_DCXCNT_DCXCNT_Pos) /*!< Bit mask of DCXCNT field. */ - /* Register: SPIM_ORC */ /* Description: Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT */ @@ -12959,53 +11025,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: SPIS */ /* Description: SPI Slave 0 */ -/* Register: SPIS_TASKS_ACQUIRE */ -/* Description: Acquire SPI semaphore */ - -/* Bit 0 : Acquire SPI semaphore */ -#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos (0UL) /*!< Position of TASKS_ACQUIRE field. */ -#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Msk (0x1UL << SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Pos) /*!< Bit mask of TASKS_ACQUIRE field. */ -#define SPIS_TASKS_ACQUIRE_TASKS_ACQUIRE_Trigger (1UL) /*!< Trigger task */ - -/* Register: SPIS_TASKS_RELEASE */ -/* Description: Release SPI semaphore, enabling the SPI slave to acquire it */ - -/* Bit 0 : Release SPI semaphore, enabling the SPI slave to acquire it */ -#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos (0UL) /*!< Position of TASKS_RELEASE field. */ -#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Msk (0x1UL << SPIS_TASKS_RELEASE_TASKS_RELEASE_Pos) /*!< Bit mask of TASKS_RELEASE field. */ -#define SPIS_TASKS_RELEASE_TASKS_RELEASE_Trigger (1UL) /*!< Trigger task */ - -/* Register: SPIS_EVENTS_END */ -/* Description: Granted transaction completed */ - -/* Bit 0 : Granted transaction completed */ -#define SPIS_EVENTS_END_EVENTS_END_Pos (0UL) /*!< Position of EVENTS_END field. */ -#define SPIS_EVENTS_END_EVENTS_END_Msk (0x1UL << SPIS_EVENTS_END_EVENTS_END_Pos) /*!< Bit mask of EVENTS_END field. */ -#define SPIS_EVENTS_END_EVENTS_END_NotGenerated (0UL) /*!< Event not generated */ -#define SPIS_EVENTS_END_EVENTS_END_Generated (1UL) /*!< Event generated */ - -/* Register: SPIS_EVENTS_ENDRX */ -/* Description: End of RXD buffer reached */ - -/* Bit 0 : End of RXD buffer reached */ -#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ -#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define SPIS_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ - -/* Register: SPIS_EVENTS_ACQUIRED */ -/* Description: Semaphore acquired */ - -/* Bit 0 : Semaphore acquired */ -#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos (0UL) /*!< Position of EVENTS_ACQUIRED field. */ -#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Msk (0x1UL << SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Pos) /*!< Bit mask of EVENTS_ACQUIRED field. */ -#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_NotGenerated (0UL) /*!< Event not generated */ -#define SPIS_EVENTS_ACQUIRED_EVENTS_ACQUIRED_Generated (1UL) /*!< Event generated */ - /* Register: SPIS_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 2 : Shortcut between event END and task ACQUIRE */ +/* Bit 2 : Shortcut between END event and ACQUIRE task */ #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ @@ -13014,21 +11037,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 10 : Write '1' to enable interrupt for event ACQUIRED */ +/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event END */ +/* Bit 1 : Write '1' to Enable interrupt for END event */ #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ @@ -13038,21 +11061,21 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 10 : Write '1' to disable interrupt for event ACQUIRED */ +/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event END */ +/* Bit 1 : Write '1' to Disable interrupt for END event */ #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ @@ -13105,9 +11128,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIS_PSEL_SCK_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIS_PSEL_SCK_PORT_Msk (0x1UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIS_PSEL_SCK_PORT_Msk (0x3UL << SPIS_PSEL_SCK_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -13122,9 +11145,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIS_PSEL_MISO_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIS_PSEL_MISO_PORT_Msk (0x1UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIS_PSEL_MISO_PORT_Msk (0x3UL << SPIS_PSEL_MISO_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -13139,9 +11162,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIS_PSEL_MOSI_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIS_PSEL_MOSI_PORT_Msk (0x1UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIS_PSEL_MOSI_PORT_Msk (0x3UL << SPIS_PSEL_MOSI_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -13156,9 +11179,9 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define SPIS_PSEL_CSN_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define SPIS_PSEL_CSN_PORT_Msk (0x1UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ +#define SPIS_PSEL_CSN_PORT_Msk (0x3UL << SPIS_PSEL_CSN_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -13174,25 +11197,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_RXD_MAXCNT */ /* Description: Maximum number of bytes in receive buffer */ -/* Bits 15..0 : Maximum number of bytes in receive buffer */ +/* Bits 7..0 : Maximum number of bytes in receive buffer */ #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: SPIS_RXD_AMOUNT */ /* Description: Number of bytes received in last granted transaction */ -/* Bits 15..0 : Number of bytes received in the last granted transaction */ +/* Bits 7..0 : Number of bytes received in the last granted transaction */ #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIS_RXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 1..0 : List type */ -#define SPIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define SPIS_RXD_LIST_LIST_Msk (0x3UL << SPIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: SPIS_TXD_PTR */ /* Description: TXD data pointer */ @@ -13204,25 +11218,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: SPIS_TXD_MAXCNT */ /* Description: Maximum number of bytes in transmit buffer */ -/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: SPIS_TXD_AMOUNT */ /* Description: Number of bytes transmitted in last granted transaction */ -/* Bits 15..0 : Number of bytes transmitted in last granted transaction */ +/* Bits 7..0 : Number of bytes transmitted in last granted transaction */ #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIS_TXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 1..0 : List type */ -#define SPIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define SPIS_TXD_LIST_LIST_Msk (0x3UL << SPIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define SPIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define SPIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: SPIS_CONFIG */ /* Description: Configuration register */ @@ -13263,35 +11268,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: TEMP */ /* Description: Temperature Sensor */ -/* Register: TEMP_TASKS_START */ -/* Description: Start temperature measurement */ - -/* Bit 0 : Start temperature measurement */ -#define TEMP_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define TEMP_TASKS_START_TASKS_START_Msk (0x1UL << TEMP_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define TEMP_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: TEMP_TASKS_STOP */ -/* Description: Stop temperature measurement */ - -/* Bit 0 : Stop temperature measurement */ -#define TEMP_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define TEMP_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TEMP_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TEMP_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: TEMP_EVENTS_DATARDY */ -/* Description: Temperature measurement complete, data ready */ - -/* Bit 0 : Temperature measurement complete, data ready */ -#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos (0UL) /*!< Position of EVENTS_DATARDY field. */ -#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Msk (0x1UL << TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Pos) /*!< Bit mask of EVENTS_DATARDY field. */ -#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_NotGenerated (0UL) /*!< Event not generated */ -#define TEMP_EVENTS_DATARDY_EVENTS_DATARDY_Generated (1UL) /*!< Event generated */ - /* Register: TEMP_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for event DATARDY */ +/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -13301,7 +11281,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TEMP_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for event DATARDY */ +/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ @@ -13438,133 +11418,76 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: TIMER */ /* Description: Timer/Counter 0 */ -/* Register: TIMER_TASKS_START */ -/* Description: Start Timer */ - -/* Bit 0 : Start Timer */ -#define TIMER_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define TIMER_TASKS_START_TASKS_START_Msk (0x1UL << TIMER_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define TIMER_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: TIMER_TASKS_STOP */ -/* Description: Stop Timer */ - -/* Bit 0 : Stop Timer */ -#define TIMER_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define TIMER_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TIMER_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TIMER_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: TIMER_TASKS_COUNT */ -/* Description: Increment Timer (Counter mode only) */ - -/* Bit 0 : Increment Timer (Counter mode only) */ -#define TIMER_TASKS_COUNT_TASKS_COUNT_Pos (0UL) /*!< Position of TASKS_COUNT field. */ -#define TIMER_TASKS_COUNT_TASKS_COUNT_Msk (0x1UL << TIMER_TASKS_COUNT_TASKS_COUNT_Pos) /*!< Bit mask of TASKS_COUNT field. */ -#define TIMER_TASKS_COUNT_TASKS_COUNT_Trigger (1UL) /*!< Trigger task */ - -/* Register: TIMER_TASKS_CLEAR */ -/* Description: Clear time */ - -/* Bit 0 : Clear time */ -#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos (0UL) /*!< Position of TASKS_CLEAR field. */ -#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Msk (0x1UL << TIMER_TASKS_CLEAR_TASKS_CLEAR_Pos) /*!< Bit mask of TASKS_CLEAR field. */ -#define TIMER_TASKS_CLEAR_TASKS_CLEAR_Trigger (1UL) /*!< Trigger task */ - -/* Register: TIMER_TASKS_SHUTDOWN */ -/* Description: Deprecated register - Shut down timer */ - -/* Bit 0 : Deprecated field - Shut down timer */ -#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos (0UL) /*!< Position of TASKS_SHUTDOWN field. */ -#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Msk (0x1UL << TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Pos) /*!< Bit mask of TASKS_SHUTDOWN field. */ -#define TIMER_TASKS_SHUTDOWN_TASKS_SHUTDOWN_Trigger (1UL) /*!< Trigger task */ - -/* Register: TIMER_TASKS_CAPTURE */ -/* Description: Description collection: Capture Timer value to CC[n] register */ - -/* Bit 0 : Capture Timer value to CC[n] register */ -#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos (0UL) /*!< Position of TASKS_CAPTURE field. */ -#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Msk (0x1UL << TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Pos) /*!< Bit mask of TASKS_CAPTURE field. */ -#define TIMER_TASKS_CAPTURE_TASKS_CAPTURE_Trigger (1UL) /*!< Trigger task */ - -/* Register: TIMER_EVENTS_COMPARE */ -/* Description: Description collection: Compare event on CC[n] match */ - -/* Bit 0 : Compare event on CC[n] match */ -#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos (0UL) /*!< Position of EVENTS_COMPARE field. */ -#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Msk (0x1UL << TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Pos) /*!< Bit mask of EVENTS_COMPARE field. */ -#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_NotGenerated (0UL) /*!< Event not generated */ -#define TIMER_EVENTS_COMPARE_EVENTS_COMPARE_Generated (1UL) /*!< Event generated */ - /* Register: TIMER_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 13 : Shortcut between event COMPARE[5] and task STOP */ +/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 12 : Shortcut between event COMPARE[4] and task STOP */ +/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between event COMPARE[3] and task STOP */ +/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 10 : Shortcut between event COMPARE[2] and task STOP */ +/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between event COMPARE[1] and task STOP */ +/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between event COMPARE[0] and task STOP */ +/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between event COMPARE[5] and task CLEAR */ +/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 4 : Shortcut between event COMPARE[4] and task CLEAR */ +/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event COMPARE[3] and task CLEAR */ +/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event COMPARE[2] and task CLEAR */ +/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event COMPARE[1] and task CLEAR */ +/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event COMPARE[0] and task CLEAR */ +/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ @@ -13573,42 +11496,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENSET */ /* Description: Enable interrupt */ -/* Bit 21 : Write '1' to enable interrupt for event COMPARE[5] */ +/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event COMPARE[4] */ +/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event COMPARE[3] */ +/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event COMPARE[2] */ +/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for event COMPARE[1] */ +/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for event COMPARE[0] */ +/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ @@ -13618,48 +11541,57 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TIMER_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 21 : Write '1' to disable interrupt for event COMPARE[5] */ +/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event COMPARE[4] */ +/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event COMPARE[3] */ +/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event COMPARE[2] */ +/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for event COMPARE[1] */ +/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for event COMPARE[0] */ +/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ +/* Register: TIMER_STATUS */ +/* Description: Timer status */ + +/* Bit 0 : Timer status */ +#define TIMER_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ +#define TIMER_STATUS_STATUS_Msk (0x1UL << TIMER_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ +#define TIMER_STATUS_STATUS_Stopped (0UL) /*!< Timer is stopped */ +#define TIMER_STATUS_STATUS_Started (1UL) /*!< Timer is started */ + /* Register: TIMER_MODE */ /* Description: Timer mode selection */ @@ -13689,7 +11621,7 @@ POSSIBILITY OF SUCH DAMAGE. #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ /* Register: TIMER_CC */ -/* Description: Description collection: Capture/Compare register n */ +/* Description: Description collection[0]: Capture/Compare register 0 */ /* Bits 31..0 : Capture/Compare value */ #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ @@ -13699,110 +11631,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: TWI */ /* Description: I2C compatible Two-Wire Interface 0 */ -/* Register: TWI_TASKS_STARTRX */ -/* Description: Start TWI receive sequence */ - -/* Bit 0 : Start TWI receive sequence */ -#define TWI_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ -#define TWI_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWI_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ -#define TWI_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWI_TASKS_STARTTX */ -/* Description: Start TWI transmit sequence */ - -/* Bit 0 : Start TWI transmit sequence */ -#define TWI_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ -#define TWI_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWI_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define TWI_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWI_TASKS_STOP */ -/* Description: Stop TWI transaction */ - -/* Bit 0 : Stop TWI transaction */ -#define TWI_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define TWI_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWI_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TWI_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWI_TASKS_SUSPEND */ -/* Description: Suspend TWI transaction */ - -/* Bit 0 : Suspend TWI transaction */ -#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ -#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWI_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define TWI_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWI_TASKS_RESUME */ -/* Description: Resume TWI transaction */ - -/* Bit 0 : Resume TWI transaction */ -#define TWI_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ -#define TWI_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWI_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define TWI_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWI_EVENTS_STOPPED */ -/* Description: TWI stopped */ - -/* Bit 0 : TWI stopped */ -#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWI_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define TWI_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: TWI_EVENTS_RXDREADY */ -/* Description: TWI RXD byte received */ - -/* Bit 0 : TWI RXD byte received */ -#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos (0UL) /*!< Position of EVENTS_RXDREADY field. */ -#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Msk (0x1UL << TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Pos) /*!< Bit mask of EVENTS_RXDREADY field. */ -#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_NotGenerated (0UL) /*!< Event not generated */ -#define TWI_EVENTS_RXDREADY_EVENTS_RXDREADY_Generated (1UL) /*!< Event generated */ - -/* Register: TWI_EVENTS_TXDSENT */ -/* Description: TWI TXD byte sent */ - -/* Bit 0 : TWI TXD byte sent */ -#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos (0UL) /*!< Position of EVENTS_TXDSENT field. */ -#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Msk (0x1UL << TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Pos) /*!< Bit mask of EVENTS_TXDSENT field. */ -#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_NotGenerated (0UL) /*!< Event not generated */ -#define TWI_EVENTS_TXDSENT_EVENTS_TXDSENT_Generated (1UL) /*!< Event generated */ - -/* Register: TWI_EVENTS_ERROR */ -/* Description: TWI error */ - -/* Bit 0 : TWI error */ -#define TWI_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define TWI_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWI_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define TWI_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define TWI_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - -/* Register: TWI_EVENTS_BB */ -/* Description: TWI byte boundary, generated before each byte that is sent or received */ - -/* Bit 0 : TWI byte boundary, generated before each byte that is sent or received */ -#define TWI_EVENTS_BB_EVENTS_BB_Pos (0UL) /*!< Position of EVENTS_BB field. */ -#define TWI_EVENTS_BB_EVENTS_BB_Msk (0x1UL << TWI_EVENTS_BB_EVENTS_BB_Pos) /*!< Bit mask of EVENTS_BB field. */ -#define TWI_EVENTS_BB_EVENTS_BB_NotGenerated (0UL) /*!< Event not generated */ -#define TWI_EVENTS_BB_EVENTS_BB_Generated (1UL) /*!< Event generated */ - -/* Register: TWI_EVENTS_SUSPENDED */ -/* Description: TWI entered the suspended state */ - -/* Bit 0 : TWI entered the suspended state */ -#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ -#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ -#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ -#define TWI_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ - /* Register: TWI_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 1 : Shortcut between event BB and task STOP */ +/* Bit 1 : Shortcut between BB event and STOP task */ #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event BB and task SUSPEND */ +/* Bit 0 : Shortcut between BB event and SUSPEND task */ #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -13811,42 +11649,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENSET */ /* Description: Enable interrupt */ -/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for event BB */ +/* Bit 14 : Write '1' to Enable interrupt for BB event */ #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event TXDSENT */ +/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event RXDREADY */ +/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13856,42 +11694,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWI_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for event BB */ +/* Bit 14 : Write '1' to Disable interrupt for BB event */ #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event TXDSENT */ +/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event RXDREADY */ +/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -13937,9 +11775,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWI_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ #define TWI_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define TWI_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define TWI_PSEL_SCL_PORT_Msk (0x1UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ +#define TWI_PSEL_SCL_PORT_Msk (0x3UL << TWI_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define TWI_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -13954,9 +11792,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWI_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ #define TWI_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define TWI_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define TWI_PSEL_SDA_PORT_Msk (0x1UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ +#define TWI_PSEL_SDA_PORT_Msk (0x3UL << TWI_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define TWI_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -13997,143 +11835,34 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: TWIM */ /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ -/* Register: TWIM_TASKS_STARTRX */ -/* Description: Start TWI receive sequence */ - -/* Bit 0 : Start TWI receive sequence */ -#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ -#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << TWIM_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ -#define TWIM_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIM_TASKS_STARTTX */ -/* Description: Start TWI transmit sequence */ - -/* Bit 0 : Start TWI transmit sequence */ -#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ -#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << TWIM_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define TWIM_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIM_TASKS_STOP */ -/* Description: Stop TWI transaction. Must be issued while the TWI master is not suspended. */ - -/* Bit 0 : Stop TWI transaction. Must be issued while the TWI master is not suspended. */ -#define TWIM_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define TWIM_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIM_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TWIM_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIM_TASKS_SUSPEND */ -/* Description: Suspend TWI transaction */ - -/* Bit 0 : Suspend TWI transaction */ -#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ -#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define TWIM_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIM_TASKS_RESUME */ -/* Description: Resume TWI transaction */ - -/* Bit 0 : Resume TWI transaction */ -#define TWIM_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ -#define TWIM_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIM_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define TWIM_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIM_EVENTS_STOPPED */ -/* Description: TWI stopped */ - -/* Bit 0 : TWI stopped */ -#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIM_EVENTS_ERROR */ -/* Description: TWI error */ - -/* Bit 0 : TWI error */ -#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIM_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define TWIM_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - -/* Register: TWIM_EVENTS_SUSPENDED */ -/* Description: Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ - -/* Bit 0 : Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. */ -#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos (0UL) /*!< Position of EVENTS_SUSPENDED field. */ -#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Msk (0x1UL << TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Pos) /*!< Bit mask of EVENTS_SUSPENDED field. */ -#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_SUSPENDED_EVENTS_SUSPENDED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIM_EVENTS_RXSTARTED */ -/* Description: Receive sequence started */ - -/* Bit 0 : Receive sequence started */ -#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ -#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ -#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIM_EVENTS_TXSTARTED */ -/* Description: Transmit sequence started */ - -/* Bit 0 : Transmit sequence started */ -#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ -#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ -#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIM_EVENTS_LASTRX */ -/* Description: Byte boundary, starting to receive the last byte */ - -/* Bit 0 : Byte boundary, starting to receive the last byte */ -#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos (0UL) /*!< Position of EVENTS_LASTRX field. */ -#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Msk (0x1UL << TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Pos) /*!< Bit mask of EVENTS_LASTRX field. */ -#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_LASTRX_EVENTS_LASTRX_Generated (1UL) /*!< Event generated */ - -/* Register: TWIM_EVENTS_LASTTX */ -/* Description: Byte boundary, starting to transmit the last byte */ - -/* Bit 0 : Byte boundary, starting to transmit the last byte */ -#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos (0UL) /*!< Position of EVENTS_LASTTX field. */ -#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Msk (0x1UL << TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Pos) /*!< Bit mask of EVENTS_LASTTX field. */ -#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_NotGenerated (0UL) /*!< Event not generated */ -#define TWIM_EVENTS_LASTTX_EVENTS_LASTTX_Generated (1UL) /*!< Event generated */ - /* Register: TWIM_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 12 : Shortcut between event LASTRX and task STOP */ +/* Bit 12 : Shortcut between LASTRX event and STOP task */ #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 11 : Shortcut between event LASTRX and task SUSPEND */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Pos (11UL) /*!< Position of LASTRX_SUSPEND field. */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTRX_SUSPEND_Pos) /*!< Bit mask of LASTRX_SUSPEND field. */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ -#define TWIM_SHORTS_LASTRX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ - -/* Bit 10 : Shortcut between event LASTRX and task STARTTX */ +/* Bit 10 : Shortcut between LASTRX event and STARTTX task */ #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 9 : Shortcut between event LASTTX and task STOP */ +/* Bit 9 : Shortcut between LASTTX event and STOP task */ #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 8 : Shortcut between event LASTTX and task SUSPEND */ +/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 7 : Shortcut between event LASTTX and task STARTRX */ +/* Bit 7 : Shortcut between LASTTX event and STARTRX task */ #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14142,43 +11871,43 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for event LASTTX */ +/* Bit 24 : Enable or disable interrupt for LASTTX event */ #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for event LASTRX */ +/* Bit 23 : Enable or disable interrupt for LASTRX event */ #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for event SUSPENDED */ +/* Bit 18 : Enable or disable interrupt for SUSPENDED event */ #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for event ERROR */ +/* Bit 9 : Enable or disable interrupt for ERROR event */ #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event STOPPED */ +/* Bit 1 : Enable or disable interrupt for STOPPED event */ #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -14187,49 +11916,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for event LASTTX */ +/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for event LASTRX */ +/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event SUSPENDED */ +/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14239,49 +11968,49 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for event LASTTX */ +/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for event LASTRX */ +/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event SUSPENDED */ +/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14327,9 +12056,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define TWIM_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define TWIM_PSEL_SCL_PORT_Msk (0x1UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ +#define TWIM_PSEL_SCL_PORT_Msk (0x3UL << TWIM_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -14344,9 +12073,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define TWIM_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define TWIM_PSEL_SDA_PORT_Msk (0x1UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ +#define TWIM_PSEL_SDA_PORT_Msk (0x3UL << TWIM_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -14372,16 +12101,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_RXD_MAXCNT */ /* Description: Maximum number of bytes in receive buffer */ -/* Bits 15..0 : Maximum number of bytes in receive buffer */ +/* Bits 7..0 : Maximum number of bytes in receive buffer */ #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: TWIM_RXD_AMOUNT */ /* Description: Number of bytes transferred in the last transaction */ -/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: TWIM_RXD_LIST */ /* Description: EasyDMA list type */ @@ -14402,16 +12131,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIM_TXD_MAXCNT */ /* Description: Maximum number of bytes in transmit buffer */ -/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +/* Bits 7..0 : Maximum number of bytes in transmit buffer */ #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: TWIM_TXD_AMOUNT */ /* Description: Number of bytes transferred in the last transaction */ -/* Bits 15..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ +/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: TWIM_TXD_LIST */ /* Description: EasyDMA list type */ @@ -14433,110 +12162,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: TWIS */ /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ -/* Register: TWIS_TASKS_STOP */ -/* Description: Stop TWI transaction */ - -/* Bit 0 : Stop TWI transaction */ -#define TWIS_TASKS_STOP_TASKS_STOP_Pos (0UL) /*!< Position of TASKS_STOP field. */ -#define TWIS_TASKS_STOP_TASKS_STOP_Msk (0x1UL << TWIS_TASKS_STOP_TASKS_STOP_Pos) /*!< Bit mask of TASKS_STOP field. */ -#define TWIS_TASKS_STOP_TASKS_STOP_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIS_TASKS_SUSPEND */ -/* Description: Suspend TWI transaction */ - -/* Bit 0 : Suspend TWI transaction */ -#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ -#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define TWIS_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIS_TASKS_RESUME */ -/* Description: Resume TWI transaction */ - -/* Bit 0 : Resume TWI transaction */ -#define TWIS_TASKS_RESUME_TASKS_RESUME_Pos (0UL) /*!< Position of TASKS_RESUME field. */ -#define TWIS_TASKS_RESUME_TASKS_RESUME_Msk (0x1UL << TWIS_TASKS_RESUME_TASKS_RESUME_Pos) /*!< Bit mask of TASKS_RESUME field. */ -#define TWIS_TASKS_RESUME_TASKS_RESUME_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIS_TASKS_PREPARERX */ -/* Description: Prepare the TWI slave to respond to a write command */ - -/* Bit 0 : Prepare the TWI slave to respond to a write command */ -#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos (0UL) /*!< Position of TASKS_PREPARERX field. */ -#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Msk (0x1UL << TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Pos) /*!< Bit mask of TASKS_PREPARERX field. */ -#define TWIS_TASKS_PREPARERX_TASKS_PREPARERX_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIS_TASKS_PREPARETX */ -/* Description: Prepare the TWI slave to respond to a read command */ - -/* Bit 0 : Prepare the TWI slave to respond to a read command */ -#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos (0UL) /*!< Position of TASKS_PREPARETX field. */ -#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Msk (0x1UL << TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Pos) /*!< Bit mask of TASKS_PREPARETX field. */ -#define TWIS_TASKS_PREPARETX_TASKS_PREPARETX_Trigger (1UL) /*!< Trigger task */ - -/* Register: TWIS_EVENTS_STOPPED */ -/* Description: TWI stopped */ - -/* Bit 0 : TWI stopped */ -#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos (0UL) /*!< Position of EVENTS_STOPPED field. */ -#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Msk (0x1UL << TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Pos) /*!< Bit mask of EVENTS_STOPPED field. */ -#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_STOPPED_EVENTS_STOPPED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIS_EVENTS_ERROR */ -/* Description: TWI error */ - -/* Bit 0 : TWI error */ -#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << TWIS_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define TWIS_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - -/* Register: TWIS_EVENTS_RXSTARTED */ -/* Description: Receive sequence started */ - -/* Bit 0 : Receive sequence started */ -#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ -#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ -#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIS_EVENTS_TXSTARTED */ -/* Description: Transmit sequence started */ - -/* Bit 0 : Transmit sequence started */ -#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ -#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ -#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: TWIS_EVENTS_WRITE */ -/* Description: Write command received */ - -/* Bit 0 : Write command received */ -#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos (0UL) /*!< Position of EVENTS_WRITE field. */ -#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Msk (0x1UL << TWIS_EVENTS_WRITE_EVENTS_WRITE_Pos) /*!< Bit mask of EVENTS_WRITE field. */ -#define TWIS_EVENTS_WRITE_EVENTS_WRITE_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_WRITE_EVENTS_WRITE_Generated (1UL) /*!< Event generated */ - -/* Register: TWIS_EVENTS_READ */ -/* Description: Read command received */ - -/* Bit 0 : Read command received */ -#define TWIS_EVENTS_READ_EVENTS_READ_Pos (0UL) /*!< Position of EVENTS_READ field. */ -#define TWIS_EVENTS_READ_EVENTS_READ_Msk (0x1UL << TWIS_EVENTS_READ_EVENTS_READ_Pos) /*!< Bit mask of EVENTS_READ field. */ -#define TWIS_EVENTS_READ_EVENTS_READ_NotGenerated (0UL) /*!< Event not generated */ -#define TWIS_EVENTS_READ_EVENTS_READ_Generated (1UL) /*!< Event generated */ - /* Register: TWIS_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 14 : Shortcut between event READ and task SUSPEND */ +/* Bit 14 : Shortcut between READ event and SUSPEND task */ #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 13 : Shortcut between event WRITE and task SUSPEND */ +/* Bit 13 : Shortcut between WRITE event and SUSPEND task */ #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ @@ -14545,37 +12180,37 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 26 : Enable or disable interrupt for event READ */ +/* Bit 26 : Enable or disable interrupt for READ event */ #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ -/* Bit 25 : Enable or disable interrupt for event WRITE */ +/* Bit 25 : Enable or disable interrupt for WRITE event */ #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for event ERROR */ +/* Bit 9 : Enable or disable interrupt for ERROR event */ #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event STOPPED */ +/* Bit 1 : Enable or disable interrupt for STOPPED event */ #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ @@ -14584,42 +12219,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENSET */ /* Description: Enable interrupt */ -/* Bit 26 : Write '1' to enable interrupt for event READ */ +/* Bit 26 : Write '1' to Enable interrupt for READ event */ #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ -/* Bit 25 : Write '1' to enable interrupt for event WRITE */ +/* Bit 25 : Write '1' to Enable interrupt for WRITE event */ #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14629,42 +12264,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 26 : Write '1' to disable interrupt for event READ */ +/* Bit 26 : Write '1' to Disable interrupt for READ event */ #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ -/* Bit 25 : Write '1' to disable interrupt for event WRITE */ +/* Bit 25 : Write '1' to Disable interrupt for WRITE event */ #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STOPPED */ +/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ @@ -14717,9 +12352,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define TWIS_PSEL_SCL_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define TWIS_PSEL_SCL_PORT_Msk (0x1UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ +#define TWIS_PSEL_SCL_PORT_Msk (0x3UL << TWIS_PSEL_SCL_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -14734,9 +12369,9 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define TWIS_PSEL_SDA_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define TWIS_PSEL_SDA_PORT_Msk (0x1UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ +#define TWIS_PSEL_SDA_PORT_Msk (0x3UL << TWIS_PSEL_SDA_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -14752,25 +12387,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_RXD_MAXCNT */ /* Description: Maximum number of bytes in RXD buffer */ -/* Bits 15..0 : Maximum number of bytes in RXD buffer */ +/* Bits 7..0 : Maximum number of bytes in RXD buffer */ #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: TWIS_RXD_AMOUNT */ /* Description: Number of bytes transferred in the last RXD transaction */ -/* Bits 15..0 : Number of bytes transferred in the last RXD transaction */ +/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: TWIS_RXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 1..0 : List type */ -#define TWIS_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define TWIS_RXD_LIST_LIST_Msk (0x3UL << TWIS_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIS_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIS_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: TWIS_TXD_PTR */ /* Description: TXD Data pointer */ @@ -14782,28 +12408,19 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: TWIS_TXD_MAXCNT */ /* Description: Maximum number of bytes in TXD buffer */ -/* Bits 15..0 : Maximum number of bytes in TXD buffer */ +/* Bits 7..0 : Maximum number of bytes in TXD buffer */ #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: TWIS_TXD_AMOUNT */ /* Description: Number of bytes transferred in the last TXD transaction */ -/* Bits 15..0 : Number of bytes transferred in the last TXD transaction */ +/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: TWIS_TXD_LIST */ -/* Description: EasyDMA list type */ - -/* Bits 1..0 : List type */ -#define TWIS_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ -#define TWIS_TXD_LIST_LIST_Msk (0x3UL << TWIS_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ -#define TWIS_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ -#define TWIS_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ +#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: TWIS_ADDRESS */ -/* Description: Description collection: TWI slave address n */ +/* Description: Description collection[0]: TWI slave address 0 */ /* Bits 6..0 : TWI slave address */ #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ @@ -14835,110 +12452,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: UART */ /* Description: Universal Asynchronous Receiver/Transmitter */ -/* Register: UART_TASKS_STARTRX */ -/* Description: Start UART receiver */ - -/* Bit 0 : Start UART receiver */ -#define UART_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ -#define UART_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UART_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ -#define UART_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UART_TASKS_STOPRX */ -/* Description: Stop UART receiver */ - -/* Bit 0 : Stop UART receiver */ -#define UART_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ -#define UART_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UART_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ -#define UART_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UART_TASKS_STARTTX */ -/* Description: Start UART transmitter */ - -/* Bit 0 : Start UART transmitter */ -#define UART_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ -#define UART_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UART_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define UART_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UART_TASKS_STOPTX */ -/* Description: Stop UART transmitter */ - -/* Bit 0 : Stop UART transmitter */ -#define UART_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ -#define UART_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UART_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ -#define UART_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UART_TASKS_SUSPEND */ -/* Description: Suspend UART */ - -/* Bit 0 : Suspend UART */ -#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos (0UL) /*!< Position of TASKS_SUSPEND field. */ -#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Msk (0x1UL << UART_TASKS_SUSPEND_TASKS_SUSPEND_Pos) /*!< Bit mask of TASKS_SUSPEND field. */ -#define UART_TASKS_SUSPEND_TASKS_SUSPEND_Trigger (1UL) /*!< Trigger task */ - -/* Register: UART_EVENTS_CTS */ -/* Description: CTS is activated (set low). Clear To Send. */ - -/* Bit 0 : CTS is activated (set low). Clear To Send. */ -#define UART_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ -#define UART_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UART_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ -#define UART_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ -#define UART_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ - -/* Register: UART_EVENTS_NCTS */ -/* Description: CTS is deactivated (set high). Not Clear To Send. */ - -/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ -#define UART_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ -#define UART_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UART_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ -#define UART_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ -#define UART_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ - -/* Register: UART_EVENTS_RXDRDY */ -/* Description: Data received in RXD */ - -/* Bit 0 : Data received in RXD */ -#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ -#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ -#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ -#define UART_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ - -/* Register: UART_EVENTS_TXDRDY */ -/* Description: Data sent from TXD */ - -/* Bit 0 : Data sent from TXD */ -#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ -#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ -#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ -#define UART_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ - -/* Register: UART_EVENTS_ERROR */ -/* Description: Error detected */ - -/* Bit 0 : Error detected */ -#define UART_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define UART_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UART_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define UART_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define UART_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - -/* Register: UART_EVENTS_RXTO */ -/* Description: Receiver timeout */ - -/* Bit 0 : Receiver timeout */ -#define UART_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ -#define UART_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UART_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ -#define UART_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ -#define UART_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ - /* Register: UART_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 4 : Shortcut between event NCTS and task STOPRX */ +/* Bit 4 : Shortcut between NCTS event and STOPRX task */ #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event CTS and task STARTRX */ +/* Bit 3 : Shortcut between CTS event and STARTRX task */ #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -14947,42 +12470,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENSET */ /* Description: Enable interrupt */ -/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event CTS */ +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -14992,42 +12515,42 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event CTS */ +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15079,9 +12602,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UART_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ #define UART_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UART_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UART_PSEL_RTS_PORT_Msk (0x1UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UART_PSEL_RTS_PORT_Msk (0x3UL << UART_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UART_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15096,9 +12619,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UART_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ #define UART_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UART_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UART_PSEL_TXD_PORT_Msk (0x1UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UART_PSEL_TXD_PORT_Msk (0x3UL << UART_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UART_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15113,9 +12636,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UART_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ #define UART_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UART_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UART_PSEL_CTS_PORT_Msk (0x1UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UART_PSEL_CTS_PORT_Msk (0x3UL << UART_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UART_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15130,9 +12653,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UART_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ #define UART_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UART_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UART_PSEL_RXD_PORT_Msk (0x1UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UART_PSEL_RXD_PORT_Msk (0x3UL << UART_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UART_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15180,12 +12703,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_CONFIG */ /* Description: Configuration of parity and hardware flow control */ -/* Bit 4 : Stop bits */ -#define UART_CONFIG_STOP_Pos (4UL) /*!< Position of STOP field. */ -#define UART_CONFIG_STOP_Msk (0x1UL << UART_CONFIG_STOP_Pos) /*!< Bit mask of STOP field. */ -#define UART_CONFIG_STOP_One (0UL) /*!< One stop bit */ -#define UART_CONFIG_STOP_Two (1UL) /*!< Two stop bits */ - /* Bits 3..1 : Parity */ #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ @@ -15202,155 +12719,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: UARTE */ /* Description: UART with EasyDMA 0 */ -/* Register: UARTE_TASKS_STARTRX */ -/* Description: Start UART receiver */ - -/* Bit 0 : Start UART receiver */ -#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos (0UL) /*!< Position of TASKS_STARTRX field. */ -#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Msk (0x1UL << UARTE_TASKS_STARTRX_TASKS_STARTRX_Pos) /*!< Bit mask of TASKS_STARTRX field. */ -#define UARTE_TASKS_STARTRX_TASKS_STARTRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UARTE_TASKS_STOPRX */ -/* Description: Stop UART receiver */ - -/* Bit 0 : Stop UART receiver */ -#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos (0UL) /*!< Position of TASKS_STOPRX field. */ -#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Msk (0x1UL << UARTE_TASKS_STOPRX_TASKS_STOPRX_Pos) /*!< Bit mask of TASKS_STOPRX field. */ -#define UARTE_TASKS_STOPRX_TASKS_STOPRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UARTE_TASKS_STARTTX */ -/* Description: Start UART transmitter */ - -/* Bit 0 : Start UART transmitter */ -#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos (0UL) /*!< Position of TASKS_STARTTX field. */ -#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Msk (0x1UL << UARTE_TASKS_STARTTX_TASKS_STARTTX_Pos) /*!< Bit mask of TASKS_STARTTX field. */ -#define UARTE_TASKS_STARTTX_TASKS_STARTTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UARTE_TASKS_STOPTX */ -/* Description: Stop UART transmitter */ - -/* Bit 0 : Stop UART transmitter */ -#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos (0UL) /*!< Position of TASKS_STOPTX field. */ -#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Msk (0x1UL << UARTE_TASKS_STOPTX_TASKS_STOPTX_Pos) /*!< Bit mask of TASKS_STOPTX field. */ -#define UARTE_TASKS_STOPTX_TASKS_STOPTX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UARTE_TASKS_FLUSHRX */ -/* Description: Flush RX FIFO into RX buffer */ - -/* Bit 0 : Flush RX FIFO into RX buffer */ -#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos (0UL) /*!< Position of TASKS_FLUSHRX field. */ -#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Msk (0x1UL << UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Pos) /*!< Bit mask of TASKS_FLUSHRX field. */ -#define UARTE_TASKS_FLUSHRX_TASKS_FLUSHRX_Trigger (1UL) /*!< Trigger task */ - -/* Register: UARTE_EVENTS_CTS */ -/* Description: CTS is activated (set low). Clear To Send. */ - -/* Bit 0 : CTS is activated (set low). Clear To Send. */ -#define UARTE_EVENTS_CTS_EVENTS_CTS_Pos (0UL) /*!< Position of EVENTS_CTS field. */ -#define UARTE_EVENTS_CTS_EVENTS_CTS_Msk (0x1UL << UARTE_EVENTS_CTS_EVENTS_CTS_Pos) /*!< Bit mask of EVENTS_CTS field. */ -#define UARTE_EVENTS_CTS_EVENTS_CTS_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_CTS_EVENTS_CTS_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_NCTS */ -/* Description: CTS is deactivated (set high). Not Clear To Send. */ - -/* Bit 0 : CTS is deactivated (set high). Not Clear To Send. */ -#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos (0UL) /*!< Position of EVENTS_NCTS field. */ -#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Msk (0x1UL << UARTE_EVENTS_NCTS_EVENTS_NCTS_Pos) /*!< Bit mask of EVENTS_NCTS field. */ -#define UARTE_EVENTS_NCTS_EVENTS_NCTS_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_NCTS_EVENTS_NCTS_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_RXDRDY */ -/* Description: Data received in RXD (but potentially not yet transferred to Data RAM) */ - -/* Bit 0 : Data received in RXD (but potentially not yet transferred to Data RAM) */ -#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos (0UL) /*!< Position of EVENTS_RXDRDY field. */ -#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Msk (0x1UL << UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Pos) /*!< Bit mask of EVENTS_RXDRDY field. */ -#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_RXDRDY_EVENTS_RXDRDY_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_ENDRX */ -/* Description: Receive buffer is filled up */ - -/* Bit 0 : Receive buffer is filled up */ -#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos (0UL) /*!< Position of EVENTS_ENDRX field. */ -#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Msk (0x1UL << UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Pos) /*!< Bit mask of EVENTS_ENDRX field. */ -#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_ENDRX_EVENTS_ENDRX_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_TXDRDY */ -/* Description: Data sent from TXD */ - -/* Bit 0 : Data sent from TXD */ -#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos (0UL) /*!< Position of EVENTS_TXDRDY field. */ -#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Msk (0x1UL << UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Pos) /*!< Bit mask of EVENTS_TXDRDY field. */ -#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_TXDRDY_EVENTS_TXDRDY_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_ENDTX */ -/* Description: Last TX byte transmitted */ - -/* Bit 0 : Last TX byte transmitted */ -#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos (0UL) /*!< Position of EVENTS_ENDTX field. */ -#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Msk (0x1UL << UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Pos) /*!< Bit mask of EVENTS_ENDTX field. */ -#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_ENDTX_EVENTS_ENDTX_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_ERROR */ -/* Description: Error detected */ - -/* Bit 0 : Error detected */ -#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos (0UL) /*!< Position of EVENTS_ERROR field. */ -#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Msk (0x1UL << UARTE_EVENTS_ERROR_EVENTS_ERROR_Pos) /*!< Bit mask of EVENTS_ERROR field. */ -#define UARTE_EVENTS_ERROR_EVENTS_ERROR_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_ERROR_EVENTS_ERROR_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_RXTO */ -/* Description: Receiver timeout */ - -/* Bit 0 : Receiver timeout */ -#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos (0UL) /*!< Position of EVENTS_RXTO field. */ -#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Msk (0x1UL << UARTE_EVENTS_RXTO_EVENTS_RXTO_Pos) /*!< Bit mask of EVENTS_RXTO field. */ -#define UARTE_EVENTS_RXTO_EVENTS_RXTO_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_RXTO_EVENTS_RXTO_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_RXSTARTED */ -/* Description: UART receiver has started */ - -/* Bit 0 : UART receiver has started */ -#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos (0UL) /*!< Position of EVENTS_RXSTARTED field. */ -#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Msk (0x1UL << UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Pos) /*!< Bit mask of EVENTS_RXSTARTED field. */ -#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_RXSTARTED_EVENTS_RXSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_TXSTARTED */ -/* Description: UART transmitter has started */ - -/* Bit 0 : UART transmitter has started */ -#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos (0UL) /*!< Position of EVENTS_TXSTARTED field. */ -#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Msk (0x1UL << UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Pos) /*!< Bit mask of EVENTS_TXSTARTED field. */ -#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_TXSTARTED_EVENTS_TXSTARTED_Generated (1UL) /*!< Event generated */ - -/* Register: UARTE_EVENTS_TXSTOPPED */ -/* Description: Transmitter stopped */ - -/* Bit 0 : Transmitter stopped */ -#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos (0UL) /*!< Position of EVENTS_TXSTOPPED field. */ -#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Msk (0x1UL << UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Pos) /*!< Bit mask of EVENTS_TXSTOPPED field. */ -#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_NotGenerated (0UL) /*!< Event not generated */ -#define UARTE_EVENTS_TXSTOPPED_EVENTS_TXSTOPPED_Generated (1UL) /*!< Event generated */ - /* Register: UARTE_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 6 : Shortcut between event ENDRX and task STOPRX */ +/* Bit 6 : Shortcut between ENDRX event and STOPRX task */ #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 5 : Shortcut between event ENDRX and task STARTRX */ +/* Bit 5 : Shortcut between ENDRX event and STARTRX task */ #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ @@ -15359,67 +12737,67 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 22 : Enable or disable interrupt for event TXSTOPPED */ +/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for event TXSTARTED */ +/* Bit 20 : Enable or disable interrupt for TXSTARTED event */ #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for event RXSTARTED */ +/* Bit 19 : Enable or disable interrupt for RXSTARTED event */ #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for event RXTO */ +/* Bit 17 : Enable or disable interrupt for RXTO event */ #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for event ERROR */ +/* Bit 9 : Enable or disable interrupt for ERROR event */ #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for event ENDTX */ +/* Bit 8 : Enable or disable interrupt for ENDTX event */ #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event TXDRDY */ +/* Bit 7 : Enable or disable interrupt for TXDRDY event */ #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event ENDRX */ +/* Bit 4 : Enable or disable interrupt for ENDRX event */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event RXDRDY */ +/* Bit 2 : Enable or disable interrupt for RXDRDY event */ #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event NCTS */ +/* Bit 1 : Enable or disable interrupt for NCTS event */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event CTS */ +/* Bit 0 : Enable or disable interrupt for CTS event */ #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ @@ -15428,77 +12806,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENSET */ /* Description: Enable interrupt */ -/* Bit 22 : Write '1' to enable interrupt for event TXSTOPPED */ +/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event TXSTARTED */ +/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event RXSTARTED */ +/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for event RXTO */ +/* Bit 17 : Write '1' to Enable interrupt for RXTO event */ #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Enable interrupt for ERROR event */ #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for event ENDTX */ +/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event TXDRDY */ +/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event ENDRX */ +/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event RXDRDY */ +/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event NCTS */ +/* Bit 1 : Write '1' to Enable interrupt for NCTS event */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event CTS */ +/* Bit 0 : Write '1' to Enable interrupt for CTS event */ #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15508,77 +12886,77 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 22 : Write '1' to disable interrupt for event TXSTOPPED */ +/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event TXSTARTED */ +/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event RXSTARTED */ +/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for event RXTO */ +/* Bit 17 : Write '1' to Disable interrupt for RXTO event */ #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event ERROR */ +/* Bit 9 : Write '1' to Disable interrupt for ERROR event */ #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for event ENDTX */ +/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event TXDRDY */ +/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event ENDRX */ +/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event RXDRDY */ +/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event NCTS */ +/* Bit 1 : Write '1' to Disable interrupt for NCTS event */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event CTS */ +/* Bit 0 : Write '1' to Disable interrupt for CTS event */ #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ @@ -15630,9 +13008,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UARTE_PSEL_RTS_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UARTE_PSEL_RTS_PORT_Msk (0x1UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UARTE_PSEL_RTS_PORT_Msk (0x3UL << UARTE_PSEL_RTS_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15647,9 +13025,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UARTE_PSEL_TXD_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UARTE_PSEL_TXD_PORT_Msk (0x1UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UARTE_PSEL_TXD_PORT_Msk (0x3UL << UARTE_PSEL_TXD_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15664,9 +13042,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UARTE_PSEL_CTS_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UARTE_PSEL_CTS_PORT_Msk (0x1UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UARTE_PSEL_CTS_PORT_Msk (0x3UL << UARTE_PSEL_CTS_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15681,9 +13059,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number */ +/* Bits 6..5 : Port number */ #define UARTE_PSEL_RXD_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UARTE_PSEL_RXD_PORT_Msk (0x1UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UARTE_PSEL_RXD_PORT_Msk (0x3UL << UARTE_PSEL_RXD_PORT_Pos) /*!< Bit mask of PORT field. */ /* Bits 4..0 : Pin number */ #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ @@ -15724,16 +13102,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_RXD_MAXCNT */ /* Description: Maximum number of bytes in receive buffer */ -/* Bits 15..0 : Maximum number of bytes in receive buffer */ +/* Bits 9..0 : Maximum number of bytes in receive buffer */ #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: UARTE_RXD_AMOUNT */ /* Description: Number of bytes transferred in the last transaction */ -/* Bits 15..0 : Number of bytes transferred in the last transaction */ +/* Bits 9..0 : Number of bytes transferred in the last transaction */ #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: UARTE_TXD_PTR */ /* Description: Data pointer */ @@ -15745,16 +13123,16 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UARTE_TXD_MAXCNT */ /* Description: Maximum number of bytes in transmit buffer */ -/* Bits 15..0 : Maximum number of bytes in transmit buffer */ +/* Bits 9..0 : Maximum number of bytes in transmit buffer */ #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ +#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0x3FFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: UARTE_TXD_AMOUNT */ /* Description: Number of bytes transferred in the last transaction */ -/* Bits 15..0 : Number of bytes transferred in the last transaction */ +/* Bits 9..0 : Number of bytes transferred in the last transaction */ #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ +#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0x3FFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: UARTE_CONFIG */ /* Description: Configuration of parity and hardware flow control */ @@ -15779,31 +13157,31 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: UICR */ -/* Description: User information configuration registers */ +/* Description: User Information Configuration Registers */ /* Register: UICR_NRFFW */ -/* Description: Description collection: Reserved for Nordic firmware design */ +/* Description: Description collection[0]: Reserved for Nordic firmware design */ /* Bits 31..0 : Reserved for Nordic firmware design */ #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ /* Register: UICR_NRFHW */ -/* Description: Description collection: Reserved for Nordic hardware design */ +/* Description: Description collection[0]: Reserved for Nordic hardware design */ /* Bits 31..0 : Reserved for Nordic hardware design */ #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ /* Register: UICR_CUSTOMER */ -/* Description: Description collection: Reserved for customer */ +/* Description: Description collection[0]: Reserved for customer */ /* Bits 31..0 : Reserved for customer */ #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ /* Register: UICR_PSELRESET */ -/* Description: Description collection: Mapping of the nRESET function (see POWER chapter for details) */ +/* Description: Description collection[0]: Mapping of the nRESET function */ /* Bit 31 : Connection */ #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ @@ -15811,18 +13189,18 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bit 5 : Port number onto which nRESET is exposed */ +/* Bits 6..5 : Port number onto which nRESET is exposed */ #define UICR_PSELRESET_PORT_Pos (5UL) /*!< Position of PORT field. */ -#define UICR_PSELRESET_PORT_Msk (0x1UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ +#define UICR_PSELRESET_PORT_Msk (0x3UL << UICR_PSELRESET_PORT_Pos) /*!< Bit mask of PORT field. */ -/* Bits 4..0 : GPIO pin number onto which nRESET is exposed */ +/* Bits 4..0 : Pin number of PORT onto which nRESET is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ /* Description: Access port protection */ -/* Bits 7..0 : Enable or disable access port protection. */ +/* Bits 7..0 : Enable or disable Access Port protection. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ @@ -15837,23 +13215,17 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ -/* Register: UICR_DEBUGCTRL */ -/* Description: Processor debug control */ - -/* Bits 15..8 : Configure CPU flash patch and breakpoint (FPB) unit behavior */ -#define UICR_DEBUGCTRL_CPUFPBEN_Pos (8UL) /*!< Position of CPUFPBEN field. */ -#define UICR_DEBUGCTRL_CPUFPBEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUFPBEN_Pos) /*!< Bit mask of CPUFPBEN field. */ -#define UICR_DEBUGCTRL_CPUFPBEN_Disabled (0x00UL) /*!< Disable CPU FPB unit. Writes into the FPB registers will be ignored. */ -#define UICR_DEBUGCTRL_CPUFPBEN_Enabled (0xFFUL) /*!< Enable CPU FPB unit (default behavior) */ +/* Register: UICR_EXTSUPPLY */ +/* Description: Enable external circuitry to be supplied from VDD pin. Applicable in 'High voltage mode' only. */ -/* Bits 7..0 : Configure CPU non-intrusive debug features */ -#define UICR_DEBUGCTRL_CPUNIDEN_Pos (0UL) /*!< Position of CPUNIDEN field. */ -#define UICR_DEBUGCTRL_CPUNIDEN_Msk (0xFFUL << UICR_DEBUGCTRL_CPUNIDEN_Pos) /*!< Bit mask of CPUNIDEN field. */ -#define UICR_DEBUGCTRL_CPUNIDEN_Disabled (0x00UL) /*!< Disable CPU ITM and ETM functionality */ -#define UICR_DEBUGCTRL_CPUNIDEN_Enabled (0xFFUL) /*!< Enable CPU ITM and ETM functionality (default behavior) */ +/* Bit 0 : Enable external circuitry to be supplied from VDD pin (output of REG0 stage). */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Pos (0UL) /*!< Position of EXTSUPPLY field. */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Msk (0x1UL << UICR_EXTSUPPLY_EXTSUPPLY_Pos) /*!< Bit mask of EXTSUPPLY field. */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Disabled (0UL) /*!< No current can be drawn from the VDD pin. */ +#define UICR_EXTSUPPLY_EXTSUPPLY_Enabled (1UL) /*!< It is allowed to supply external circuitry from the VDD pin. */ /* Register: UICR_REGOUT0 */ -/* Description: GPIO reference voltage / external output supply voltage in high voltage mode */ +/* Description: GPIO reference voltage / external output supply voltage in 'High voltage mode'. */ /* Bits 2..0 : Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. */ #define UICR_REGOUT0_VOUT_Pos (0UL) /*!< Position of VOUT field. */ @@ -15868,207 +13240,36 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: USBD */ -/* Description: Universal serial bus device */ - -/* Register: USBD_TASKS_STARTEPIN */ -/* Description: Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ - -/* Bit 0 : Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host */ -#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos (0UL) /*!< Position of TASKS_STARTEPIN field. */ -#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Msk (0x1UL << USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Pos) /*!< Bit mask of TASKS_STARTEPIN field. */ -#define USBD_TASKS_STARTEPIN_TASKS_STARTEPIN_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_STARTISOIN */ -/* Description: Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ - -/* Bit 0 : Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint */ -#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos (0UL) /*!< Position of TASKS_STARTISOIN field. */ -#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Msk (0x1UL << USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Pos) /*!< Bit mask of TASKS_STARTISOIN field. */ -#define USBD_TASKS_STARTISOIN_TASKS_STARTISOIN_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_STARTEPOUT */ -/* Description: Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ - -/* Bit 0 : Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host */ -#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos (0UL) /*!< Position of TASKS_STARTEPOUT field. */ -#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Msk (0x1UL << USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Pos) /*!< Bit mask of TASKS_STARTEPOUT field. */ -#define USBD_TASKS_STARTEPOUT_TASKS_STARTEPOUT_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_STARTISOOUT */ -/* Description: Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ - -/* Bit 0 : Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint */ -#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos (0UL) /*!< Position of TASKS_STARTISOOUT field. */ -#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Msk (0x1UL << USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Pos) /*!< Bit mask of TASKS_STARTISOOUT field. */ -#define USBD_TASKS_STARTISOOUT_TASKS_STARTISOOUT_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_EP0RCVOUT */ -/* Description: Allows OUT data stage on control endpoint 0 */ - -/* Bit 0 : Allows OUT data stage on control endpoint 0 */ -#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos (0UL) /*!< Position of TASKS_EP0RCVOUT field. */ -#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Msk (0x1UL << USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Pos) /*!< Bit mask of TASKS_EP0RCVOUT field. */ -#define USBD_TASKS_EP0RCVOUT_TASKS_EP0RCVOUT_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_EP0STATUS */ -/* Description: Allows status stage on control endpoint 0 */ - -/* Bit 0 : Allows status stage on control endpoint 0 */ -#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos (0UL) /*!< Position of TASKS_EP0STATUS field. */ -#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Msk (0x1UL << USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Pos) /*!< Bit mask of TASKS_EP0STATUS field. */ -#define USBD_TASKS_EP0STATUS_TASKS_EP0STATUS_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_EP0STALL */ -/* Description: Stalls data and status stage on control endpoint 0 */ - -/* Bit 0 : Stalls data and status stage on control endpoint 0 */ -#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos (0UL) /*!< Position of TASKS_EP0STALL field. */ -#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Msk (0x1UL << USBD_TASKS_EP0STALL_TASKS_EP0STALL_Pos) /*!< Bit mask of TASKS_EP0STALL field. */ -#define USBD_TASKS_EP0STALL_TASKS_EP0STALL_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_DPDMDRIVE */ -/* Description: Forces D+ and D- lines into the state defined in the DPDMVALUE register */ - -/* Bit 0 : Forces D+ and D- lines into the state defined in the DPDMVALUE register */ -#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos (0UL) /*!< Position of TASKS_DPDMDRIVE field. */ -#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Msk (0x1UL << USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Pos) /*!< Bit mask of TASKS_DPDMDRIVE field. */ -#define USBD_TASKS_DPDMDRIVE_TASKS_DPDMDRIVE_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_TASKS_DPDMNODRIVE */ -/* Description: Stops forcing D+ and D- lines into any state (USB engine takes control) */ - -/* Bit 0 : Stops forcing D+ and D- lines into any state (USB engine takes control) */ -#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos (0UL) /*!< Position of TASKS_DPDMNODRIVE field. */ -#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Msk (0x1UL << USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Pos) /*!< Bit mask of TASKS_DPDMNODRIVE field. */ -#define USBD_TASKS_DPDMNODRIVE_TASKS_DPDMNODRIVE_Trigger (1UL) /*!< Trigger task */ - -/* Register: USBD_EVENTS_USBRESET */ -/* Description: Signals that a USB reset condition has been detected on USB lines */ - -/* Bit 0 : Signals that a USB reset condition has been detected on USB lines */ -#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos (0UL) /*!< Position of EVENTS_USBRESET field. */ -#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Msk (0x1UL << USBD_EVENTS_USBRESET_EVENTS_USBRESET_Pos) /*!< Bit mask of EVENTS_USBRESET field. */ -#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_USBRESET_EVENTS_USBRESET_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_STARTED */ -/* Description: Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ - -/* Bit 0 : Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register */ -#define USBD_EVENTS_STARTED_EVENTS_STARTED_Pos (0UL) /*!< Position of EVENTS_STARTED field. */ -#define USBD_EVENTS_STARTED_EVENTS_STARTED_Msk (0x1UL << USBD_EVENTS_STARTED_EVENTS_STARTED_Pos) /*!< Bit mask of EVENTS_STARTED field. */ -#define USBD_EVENTS_STARTED_EVENTS_STARTED_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_STARTED_EVENTS_STARTED_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_ENDEPIN */ -/* Description: Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - -/* Bit 0 : The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ -#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos (0UL) /*!< Position of EVENTS_ENDEPIN field. */ -#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Msk (0x1UL << USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Pos) /*!< Bit mask of EVENTS_ENDEPIN field. */ -#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_ENDEPIN_EVENTS_ENDEPIN_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_EP0DATADONE */ -/* Description: An acknowledged data transfer has taken place on the control endpoint */ - -/* Bit 0 : An acknowledged data transfer has taken place on the control endpoint */ -#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos (0UL) /*!< Position of EVENTS_EP0DATADONE field. */ -#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Msk (0x1UL << USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Pos) /*!< Bit mask of EVENTS_EP0DATADONE field. */ -#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_EP0DATADONE_EVENTS_EP0DATADONE_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_ENDISOIN */ -/* Description: The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ - -/* Bit 0 : The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. */ -#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos (0UL) /*!< Position of EVENTS_ENDISOIN field. */ -#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Msk (0x1UL << USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Pos) /*!< Bit mask of EVENTS_ENDISOIN field. */ -#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_ENDISOIN_EVENTS_ENDISOIN_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_ENDEPOUT */ -/* Description: Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ - -/* Bit 0 : The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. */ -#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos (0UL) /*!< Position of EVENTS_ENDEPOUT field. */ -#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Msk (0x1UL << USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Pos) /*!< Bit mask of EVENTS_ENDEPOUT field. */ -#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_ENDEPOUT_EVENTS_ENDEPOUT_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_ENDISOOUT */ -/* Description: The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ - -/* Bit 0 : The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. */ -#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos (0UL) /*!< Position of EVENTS_ENDISOOUT field. */ -#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Msk (0x1UL << USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Pos) /*!< Bit mask of EVENTS_ENDISOOUT field. */ -#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_ENDISOOUT_EVENTS_ENDISOOUT_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_SOF */ -/* Description: Signals that a SOF (start of frame) condition has been detected on USB lines */ - -/* Bit 0 : Signals that a SOF (start of frame) condition has been detected on USB lines */ -#define USBD_EVENTS_SOF_EVENTS_SOF_Pos (0UL) /*!< Position of EVENTS_SOF field. */ -#define USBD_EVENTS_SOF_EVENTS_SOF_Msk (0x1UL << USBD_EVENTS_SOF_EVENTS_SOF_Pos) /*!< Bit mask of EVENTS_SOF field. */ -#define USBD_EVENTS_SOF_EVENTS_SOF_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_SOF_EVENTS_SOF_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_USBEVENT */ -/* Description: An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ - -/* Bit 0 : An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. */ -#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos (0UL) /*!< Position of EVENTS_USBEVENT field. */ -#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Msk (0x1UL << USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Pos) /*!< Bit mask of EVENTS_USBEVENT field. */ -#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_USBEVENT_EVENTS_USBEVENT_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_EP0SETUP */ -/* Description: A valid SETUP token has been received (and acknowledged) on the control endpoint */ - -/* Bit 0 : A valid SETUP token has been received (and acknowledged) on the control endpoint */ -#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos (0UL) /*!< Position of EVENTS_EP0SETUP field. */ -#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Msk (0x1UL << USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Pos) /*!< Bit mask of EVENTS_EP0SETUP field. */ -#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_EP0SETUP_EVENTS_EP0SETUP_Generated (1UL) /*!< Event generated */ - -/* Register: USBD_EVENTS_EPDATA */ -/* Description: A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ - -/* Bit 0 : A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register */ -#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos (0UL) /*!< Position of EVENTS_EPDATA field. */ -#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Msk (0x1UL << USBD_EVENTS_EPDATA_EVENTS_EPDATA_Pos) /*!< Bit mask of EVENTS_EPDATA field. */ -#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_NotGenerated (0UL) /*!< Event not generated */ -#define USBD_EVENTS_EPDATA_EVENTS_EPDATA_Generated (1UL) /*!< Event generated */ +/* Description: Universal Serial Bus device */ /* Register: USBD_SHORTS */ -/* Description: Shortcuts between local events and tasks */ +/* Description: Shortcut register */ -/* Bit 4 : Shortcut between event ENDEPOUT[0] and task EP0RCVOUT */ +/* Bit 4 : Shortcut between ENDEPOUT[0] event and EP0RCVOUT task */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos (4UL) /*!< Position of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Pos) /*!< Bit mask of ENDEPOUT0_EP0RCVOUT field. */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0RCVOUT_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 3 : Shortcut between event ENDEPOUT[0] and task EP0STATUS */ +/* Bit 3 : Shortcut between ENDEPOUT[0] event and EP0STATUS task */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos (3UL) /*!< Position of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Msk (0x1UL << USBD_SHORTS_ENDEPOUT0_EP0STATUS_Pos) /*!< Bit mask of ENDEPOUT0_EP0STATUS field. */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_ENDEPOUT0_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 2 : Shortcut between event EP0DATADONE and task EP0STATUS */ +/* Bit 2 : Shortcut between EP0DATADONE event and EP0STATUS task */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos (2UL) /*!< Position of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_EP0STATUS_Pos) /*!< Bit mask of EP0DATADONE_EP0STATUS field. */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_EP0STATUS_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 1 : Shortcut between event EP0DATADONE and task STARTEPOUT[0] */ +/* Bit 1 : Shortcut between EP0DATADONE event and STARTEPOUT[0] task */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos (1UL) /*!< Position of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPOUT0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Disabled (0UL) /*!< Disable shortcut */ #define USBD_SHORTS_EP0DATADONE_STARTEPOUT0_Enabled (1UL) /*!< Enable shortcut */ -/* Bit 0 : Shortcut between event EP0DATADONE and task STARTEPIN[0] */ +/* Bit 0 : Shortcut between EP0DATADONE event and STARTEPIN[0] task */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos (0UL) /*!< Position of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Msk (0x1UL << USBD_SHORTS_EP0DATADONE_STARTEPIN0_Pos) /*!< Bit mask of EP0DATADONE_STARTEPIN0 field. */ #define USBD_SHORTS_EP0DATADONE_STARTEPIN0_Disabled (0UL) /*!< Disable shortcut */ @@ -16077,151 +13278,157 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTEN */ /* Description: Enable or disable interrupt */ -/* Bit 24 : Enable or disable interrupt for event EPDATA */ +/* Bit 25 : Enable or disable interrupt for ACCESSFAULT event */ +#define USBD_INTEN_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */ +#define USBD_INTEN_ACCESSFAULT_Msk (0x1UL << USBD_INTEN_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */ +#define USBD_INTEN_ACCESSFAULT_Disabled (0UL) /*!< Disable */ +#define USBD_INTEN_ACCESSFAULT_Enabled (1UL) /*!< Enable */ + +/* Bit 24 : Enable or disable interrupt for EPDATA event */ #define USBD_INTEN_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTEN_EPDATA_Msk (0x1UL << USBD_INTEN_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTEN_EPDATA_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EPDATA_Enabled (1UL) /*!< Enable */ -/* Bit 23 : Enable or disable interrupt for event EP0SETUP */ +/* Bit 23 : Enable or disable interrupt for EP0SETUP event */ #define USBD_INTEN_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Msk (0x1UL << USBD_INTEN_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTEN_EP0SETUP_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0SETUP_Enabled (1UL) /*!< Enable */ -/* Bit 22 : Enable or disable interrupt for event USBEVENT */ +/* Bit 22 : Enable or disable interrupt for USBEVENT event */ #define USBD_INTEN_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Msk (0x1UL << USBD_INTEN_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTEN_USBEVENT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_USBEVENT_Enabled (1UL) /*!< Enable */ -/* Bit 21 : Enable or disable interrupt for event SOF */ +/* Bit 21 : Enable or disable interrupt for SOF event */ #define USBD_INTEN_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTEN_SOF_Msk (0x1UL << USBD_INTEN_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTEN_SOF_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_SOF_Enabled (1UL) /*!< Enable */ -/* Bit 20 : Enable or disable interrupt for event ENDISOOUT */ +/* Bit 20 : Enable or disable interrupt for ENDISOOUT event */ #define USBD_INTEN_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Msk (0x1UL << USBD_INTEN_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTEN_ENDISOOUT_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOOUT_Enabled (1UL) /*!< Enable */ -/* Bit 19 : Enable or disable interrupt for event ENDEPOUT[7] */ +/* Bit 19 : Enable or disable interrupt for ENDEPOUT[7] event */ #define USBD_INTEN_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Msk (0x1UL << USBD_INTEN_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTEN_ENDEPOUT7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT7_Enabled (1UL) /*!< Enable */ -/* Bit 18 : Enable or disable interrupt for event ENDEPOUT[6] */ +/* Bit 18 : Enable or disable interrupt for ENDEPOUT[6] event */ #define USBD_INTEN_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Msk (0x1UL << USBD_INTEN_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTEN_ENDEPOUT6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT6_Enabled (1UL) /*!< Enable */ -/* Bit 17 : Enable or disable interrupt for event ENDEPOUT[5] */ +/* Bit 17 : Enable or disable interrupt for ENDEPOUT[5] event */ #define USBD_INTEN_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Msk (0x1UL << USBD_INTEN_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTEN_ENDEPOUT5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT5_Enabled (1UL) /*!< Enable */ -/* Bit 16 : Enable or disable interrupt for event ENDEPOUT[4] */ +/* Bit 16 : Enable or disable interrupt for ENDEPOUT[4] event */ #define USBD_INTEN_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Msk (0x1UL << USBD_INTEN_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTEN_ENDEPOUT4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT4_Enabled (1UL) /*!< Enable */ -/* Bit 15 : Enable or disable interrupt for event ENDEPOUT[3] */ +/* Bit 15 : Enable or disable interrupt for ENDEPOUT[3] event */ #define USBD_INTEN_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Msk (0x1UL << USBD_INTEN_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTEN_ENDEPOUT3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT3_Enabled (1UL) /*!< Enable */ -/* Bit 14 : Enable or disable interrupt for event ENDEPOUT[2] */ +/* Bit 14 : Enable or disable interrupt for ENDEPOUT[2] event */ #define USBD_INTEN_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Msk (0x1UL << USBD_INTEN_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTEN_ENDEPOUT2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT2_Enabled (1UL) /*!< Enable */ -/* Bit 13 : Enable or disable interrupt for event ENDEPOUT[1] */ +/* Bit 13 : Enable or disable interrupt for ENDEPOUT[1] event */ #define USBD_INTEN_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Msk (0x1UL << USBD_INTEN_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTEN_ENDEPOUT1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT1_Enabled (1UL) /*!< Enable */ -/* Bit 12 : Enable or disable interrupt for event ENDEPOUT[0] */ +/* Bit 12 : Enable or disable interrupt for ENDEPOUT[0] event */ #define USBD_INTEN_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Msk (0x1UL << USBD_INTEN_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTEN_ENDEPOUT0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPOUT0_Enabled (1UL) /*!< Enable */ -/* Bit 11 : Enable or disable interrupt for event ENDISOIN */ +/* Bit 11 : Enable or disable interrupt for ENDISOIN event */ #define USBD_INTEN_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Msk (0x1UL << USBD_INTEN_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTEN_ENDISOIN_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDISOIN_Enabled (1UL) /*!< Enable */ -/* Bit 10 : Enable or disable interrupt for event EP0DATADONE */ +/* Bit 10 : Enable or disable interrupt for EP0DATADONE event */ #define USBD_INTEN_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Msk (0x1UL << USBD_INTEN_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTEN_EP0DATADONE_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_EP0DATADONE_Enabled (1UL) /*!< Enable */ -/* Bit 9 : Enable or disable interrupt for event ENDEPIN[7] */ +/* Bit 9 : Enable or disable interrupt for ENDEPIN[7] event */ #define USBD_INTEN_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Msk (0x1UL << USBD_INTEN_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTEN_ENDEPIN7_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN7_Enabled (1UL) /*!< Enable */ -/* Bit 8 : Enable or disable interrupt for event ENDEPIN[6] */ +/* Bit 8 : Enable or disable interrupt for ENDEPIN[6] event */ #define USBD_INTEN_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Msk (0x1UL << USBD_INTEN_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTEN_ENDEPIN6_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN6_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for event ENDEPIN[5] */ +/* Bit 7 : Enable or disable interrupt for ENDEPIN[5] event */ #define USBD_INTEN_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Msk (0x1UL << USBD_INTEN_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTEN_ENDEPIN5_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN5_Enabled (1UL) /*!< Enable */ -/* Bit 6 : Enable or disable interrupt for event ENDEPIN[4] */ +/* Bit 6 : Enable or disable interrupt for ENDEPIN[4] event */ #define USBD_INTEN_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Msk (0x1UL << USBD_INTEN_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTEN_ENDEPIN4_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN4_Enabled (1UL) /*!< Enable */ -/* Bit 5 : Enable or disable interrupt for event ENDEPIN[3] */ +/* Bit 5 : Enable or disable interrupt for ENDEPIN[3] event */ #define USBD_INTEN_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Msk (0x1UL << USBD_INTEN_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTEN_ENDEPIN3_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN3_Enabled (1UL) /*!< Enable */ -/* Bit 4 : Enable or disable interrupt for event ENDEPIN[2] */ +/* Bit 4 : Enable or disable interrupt for ENDEPIN[2] event */ #define USBD_INTEN_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Msk (0x1UL << USBD_INTEN_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTEN_ENDEPIN2_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN2_Enabled (1UL) /*!< Enable */ -/* Bit 3 : Enable or disable interrupt for event ENDEPIN[1] */ +/* Bit 3 : Enable or disable interrupt for ENDEPIN[1] event */ #define USBD_INTEN_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Msk (0x1UL << USBD_INTEN_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTEN_ENDEPIN1_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN1_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for event ENDEPIN[0] */ +/* Bit 2 : Enable or disable interrupt for ENDEPIN[0] event */ #define USBD_INTEN_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Msk (0x1UL << USBD_INTEN_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTEN_ENDEPIN0_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_ENDEPIN0_Enabled (1UL) /*!< Enable */ -/* Bit 1 : Enable or disable interrupt for event STARTED */ +/* Bit 1 : Enable or disable interrupt for STARTED event */ #define USBD_INTEN_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTEN_STARTED_Msk (0x1UL << USBD_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTEN_STARTED_Disabled (0UL) /*!< Disable */ #define USBD_INTEN_STARTED_Enabled (1UL) /*!< Enable */ -/* Bit 0 : Enable or disable interrupt for event USBRESET */ +/* Bit 0 : Enable or disable interrupt for USBRESET event */ #define USBD_INTEN_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTEN_USBRESET_Msk (0x1UL << USBD_INTEN_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTEN_USBRESET_Disabled (0UL) /*!< Disable */ @@ -16230,175 +13437,182 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENSET */ /* Description: Enable interrupt */ -/* Bit 24 : Write '1' to enable interrupt for event EPDATA */ +/* Bit 25 : Write '1' to Enable interrupt for ACCESSFAULT event */ +#define USBD_INTENSET_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */ +#define USBD_INTENSET_ACCESSFAULT_Msk (0x1UL << USBD_INTENSET_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */ +#define USBD_INTENSET_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENSET_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENSET_ACCESSFAULT_Set (1UL) /*!< Enable */ + +/* Bit 24 : Write '1' to Enable interrupt for EPDATA event */ #define USBD_INTENSET_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENSET_EPDATA_Msk (0x1UL << USBD_INTENSET_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENSET_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EPDATA_Set (1UL) /*!< Enable */ -/* Bit 23 : Write '1' to enable interrupt for event EP0SETUP */ +/* Bit 23 : Write '1' to Enable interrupt for EP0SETUP event */ #define USBD_INTENSET_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Msk (0x1UL << USBD_INTENSET_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENSET_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0SETUP_Set (1UL) /*!< Enable */ -/* Bit 22 : Write '1' to enable interrupt for event USBEVENT */ +/* Bit 22 : Write '1' to Enable interrupt for USBEVENT event */ #define USBD_INTENSET_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Msk (0x1UL << USBD_INTENSET_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENSET_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_USBEVENT_Set (1UL) /*!< Enable */ -/* Bit 21 : Write '1' to enable interrupt for event SOF */ +/* Bit 21 : Write '1' to Enable interrupt for SOF event */ #define USBD_INTENSET_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENSET_SOF_Msk (0x1UL << USBD_INTENSET_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENSET_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_SOF_Set (1UL) /*!< Enable */ -/* Bit 20 : Write '1' to enable interrupt for event ENDISOOUT */ +/* Bit 20 : Write '1' to Enable interrupt for ENDISOOUT event */ #define USBD_INTENSET_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Msk (0x1UL << USBD_INTENSET_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENSET_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOOUT_Set (1UL) /*!< Enable */ -/* Bit 19 : Write '1' to enable interrupt for event ENDEPOUT[7] */ +/* Bit 19 : Write '1' to Enable interrupt for ENDEPOUT[7] event */ #define USBD_INTENSET_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Msk (0x1UL << USBD_INTENSET_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENSET_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT7_Set (1UL) /*!< Enable */ -/* Bit 18 : Write '1' to enable interrupt for event ENDEPOUT[6] */ +/* Bit 18 : Write '1' to Enable interrupt for ENDEPOUT[6] event */ #define USBD_INTENSET_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Msk (0x1UL << USBD_INTENSET_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENSET_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT6_Set (1UL) /*!< Enable */ -/* Bit 17 : Write '1' to enable interrupt for event ENDEPOUT[5] */ +/* Bit 17 : Write '1' to Enable interrupt for ENDEPOUT[5] event */ #define USBD_INTENSET_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Msk (0x1UL << USBD_INTENSET_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENSET_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT5_Set (1UL) /*!< Enable */ -/* Bit 16 : Write '1' to enable interrupt for event ENDEPOUT[4] */ +/* Bit 16 : Write '1' to Enable interrupt for ENDEPOUT[4] event */ #define USBD_INTENSET_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Msk (0x1UL << USBD_INTENSET_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENSET_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT4_Set (1UL) /*!< Enable */ -/* Bit 15 : Write '1' to enable interrupt for event ENDEPOUT[3] */ +/* Bit 15 : Write '1' to Enable interrupt for ENDEPOUT[3] event */ #define USBD_INTENSET_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Msk (0x1UL << USBD_INTENSET_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENSET_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT3_Set (1UL) /*!< Enable */ -/* Bit 14 : Write '1' to enable interrupt for event ENDEPOUT[2] */ +/* Bit 14 : Write '1' to Enable interrupt for ENDEPOUT[2] event */ #define USBD_INTENSET_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Msk (0x1UL << USBD_INTENSET_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENSET_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT2_Set (1UL) /*!< Enable */ -/* Bit 13 : Write '1' to enable interrupt for event ENDEPOUT[1] */ +/* Bit 13 : Write '1' to Enable interrupt for ENDEPOUT[1] event */ #define USBD_INTENSET_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Msk (0x1UL << USBD_INTENSET_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENSET_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT1_Set (1UL) /*!< Enable */ -/* Bit 12 : Write '1' to enable interrupt for event ENDEPOUT[0] */ +/* Bit 12 : Write '1' to Enable interrupt for ENDEPOUT[0] event */ #define USBD_INTENSET_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Msk (0x1UL << USBD_INTENSET_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENSET_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPOUT0_Set (1UL) /*!< Enable */ -/* Bit 11 : Write '1' to enable interrupt for event ENDISOIN */ +/* Bit 11 : Write '1' to Enable interrupt for ENDISOIN event */ #define USBD_INTENSET_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Msk (0x1UL << USBD_INTENSET_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENSET_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDISOIN_Set (1UL) /*!< Enable */ -/* Bit 10 : Write '1' to enable interrupt for event EP0DATADONE */ +/* Bit 10 : Write '1' to Enable interrupt for EP0DATADONE event */ #define USBD_INTENSET_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Msk (0x1UL << USBD_INTENSET_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENSET_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_EP0DATADONE_Set (1UL) /*!< Enable */ -/* Bit 9 : Write '1' to enable interrupt for event ENDEPIN[7] */ +/* Bit 9 : Write '1' to Enable interrupt for ENDEPIN[7] event */ #define USBD_INTENSET_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Msk (0x1UL << USBD_INTENSET_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENSET_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN7_Set (1UL) /*!< Enable */ -/* Bit 8 : Write '1' to enable interrupt for event ENDEPIN[6] */ +/* Bit 8 : Write '1' to Enable interrupt for ENDEPIN[6] event */ #define USBD_INTENSET_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Msk (0x1UL << USBD_INTENSET_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENSET_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN6_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to enable interrupt for event ENDEPIN[5] */ +/* Bit 7 : Write '1' to Enable interrupt for ENDEPIN[5] event */ #define USBD_INTENSET_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Msk (0x1UL << USBD_INTENSET_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENSET_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN5_Set (1UL) /*!< Enable */ -/* Bit 6 : Write '1' to enable interrupt for event ENDEPIN[4] */ +/* Bit 6 : Write '1' to Enable interrupt for ENDEPIN[4] event */ #define USBD_INTENSET_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Msk (0x1UL << USBD_INTENSET_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENSET_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN4_Set (1UL) /*!< Enable */ -/* Bit 5 : Write '1' to enable interrupt for event ENDEPIN[3] */ +/* Bit 5 : Write '1' to Enable interrupt for ENDEPIN[3] event */ #define USBD_INTENSET_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Msk (0x1UL << USBD_INTENSET_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENSET_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN3_Set (1UL) /*!< Enable */ -/* Bit 4 : Write '1' to enable interrupt for event ENDEPIN[2] */ +/* Bit 4 : Write '1' to Enable interrupt for ENDEPIN[2] event */ #define USBD_INTENSET_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Msk (0x1UL << USBD_INTENSET_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENSET_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN2_Set (1UL) /*!< Enable */ -/* Bit 3 : Write '1' to enable interrupt for event ENDEPIN[1] */ +/* Bit 3 : Write '1' to Enable interrupt for ENDEPIN[1] event */ #define USBD_INTENSET_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Msk (0x1UL << USBD_INTENSET_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENSET_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN1_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to enable interrupt for event ENDEPIN[0] */ +/* Bit 2 : Write '1' to Enable interrupt for ENDEPIN[0] event */ #define USBD_INTENSET_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Msk (0x1UL << USBD_INTENSET_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENSET_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_ENDEPIN0_Set (1UL) /*!< Enable */ -/* Bit 1 : Write '1' to enable interrupt for event STARTED */ +/* Bit 1 : Write '1' to Enable interrupt for STARTED event */ #define USBD_INTENSET_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENSET_STARTED_Msk (0x1UL << USBD_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENSET_STARTED_Set (1UL) /*!< Enable */ -/* Bit 0 : Write '1' to enable interrupt for event USBRESET */ +/* Bit 0 : Write '1' to Enable interrupt for USBRESET event */ #define USBD_INTENSET_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENSET_USBRESET_Msk (0x1UL << USBD_INTENSET_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENSET_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -16408,175 +13622,182 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 24 : Write '1' to disable interrupt for event EPDATA */ +/* Bit 25 : Write '1' to Disable interrupt for ACCESSFAULT event */ +#define USBD_INTENCLR_ACCESSFAULT_Pos (25UL) /*!< Position of ACCESSFAULT field. */ +#define USBD_INTENCLR_ACCESSFAULT_Msk (0x1UL << USBD_INTENCLR_ACCESSFAULT_Pos) /*!< Bit mask of ACCESSFAULT field. */ +#define USBD_INTENCLR_ACCESSFAULT_Disabled (0UL) /*!< Read: Disabled */ +#define USBD_INTENCLR_ACCESSFAULT_Enabled (1UL) /*!< Read: Enabled */ +#define USBD_INTENCLR_ACCESSFAULT_Clear (1UL) /*!< Disable */ + +/* Bit 24 : Write '1' to Disable interrupt for EPDATA event */ #define USBD_INTENCLR_EPDATA_Pos (24UL) /*!< Position of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Msk (0x1UL << USBD_INTENCLR_EPDATA_Pos) /*!< Bit mask of EPDATA field. */ #define USBD_INTENCLR_EPDATA_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EPDATA_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EPDATA_Clear (1UL) /*!< Disable */ -/* Bit 23 : Write '1' to disable interrupt for event EP0SETUP */ +/* Bit 23 : Write '1' to Disable interrupt for EP0SETUP event */ #define USBD_INTENCLR_EP0SETUP_Pos (23UL) /*!< Position of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Msk (0x1UL << USBD_INTENCLR_EP0SETUP_Pos) /*!< Bit mask of EP0SETUP field. */ #define USBD_INTENCLR_EP0SETUP_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0SETUP_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0SETUP_Clear (1UL) /*!< Disable */ -/* Bit 22 : Write '1' to disable interrupt for event USBEVENT */ +/* Bit 22 : Write '1' to Disable interrupt for USBEVENT event */ #define USBD_INTENCLR_USBEVENT_Pos (22UL) /*!< Position of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Msk (0x1UL << USBD_INTENCLR_USBEVENT_Pos) /*!< Bit mask of USBEVENT field. */ #define USBD_INTENCLR_USBEVENT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_USBEVENT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_USBEVENT_Clear (1UL) /*!< Disable */ -/* Bit 21 : Write '1' to disable interrupt for event SOF */ +/* Bit 21 : Write '1' to Disable interrupt for SOF event */ #define USBD_INTENCLR_SOF_Pos (21UL) /*!< Position of SOF field. */ #define USBD_INTENCLR_SOF_Msk (0x1UL << USBD_INTENCLR_SOF_Pos) /*!< Bit mask of SOF field. */ #define USBD_INTENCLR_SOF_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_SOF_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_SOF_Clear (1UL) /*!< Disable */ -/* Bit 20 : Write '1' to disable interrupt for event ENDISOOUT */ +/* Bit 20 : Write '1' to Disable interrupt for ENDISOOUT event */ #define USBD_INTENCLR_ENDISOOUT_Pos (20UL) /*!< Position of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Msk (0x1UL << USBD_INTENCLR_ENDISOOUT_Pos) /*!< Bit mask of ENDISOOUT field. */ #define USBD_INTENCLR_ENDISOOUT_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOOUT_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOOUT_Clear (1UL) /*!< Disable */ -/* Bit 19 : Write '1' to disable interrupt for event ENDEPOUT[7] */ +/* Bit 19 : Write '1' to Disable interrupt for ENDEPOUT[7] event */ #define USBD_INTENCLR_ENDEPOUT7_Pos (19UL) /*!< Position of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT7_Pos) /*!< Bit mask of ENDEPOUT7 field. */ #define USBD_INTENCLR_ENDEPOUT7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT7_Clear (1UL) /*!< Disable */ -/* Bit 18 : Write '1' to disable interrupt for event ENDEPOUT[6] */ +/* Bit 18 : Write '1' to Disable interrupt for ENDEPOUT[6] event */ #define USBD_INTENCLR_ENDEPOUT6_Pos (18UL) /*!< Position of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT6_Pos) /*!< Bit mask of ENDEPOUT6 field. */ #define USBD_INTENCLR_ENDEPOUT6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT6_Clear (1UL) /*!< Disable */ -/* Bit 17 : Write '1' to disable interrupt for event ENDEPOUT[5] */ +/* Bit 17 : Write '1' to Disable interrupt for ENDEPOUT[5] event */ #define USBD_INTENCLR_ENDEPOUT5_Pos (17UL) /*!< Position of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT5_Pos) /*!< Bit mask of ENDEPOUT5 field. */ #define USBD_INTENCLR_ENDEPOUT5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT5_Clear (1UL) /*!< Disable */ -/* Bit 16 : Write '1' to disable interrupt for event ENDEPOUT[4] */ +/* Bit 16 : Write '1' to Disable interrupt for ENDEPOUT[4] event */ #define USBD_INTENCLR_ENDEPOUT4_Pos (16UL) /*!< Position of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT4_Pos) /*!< Bit mask of ENDEPOUT4 field. */ #define USBD_INTENCLR_ENDEPOUT4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT4_Clear (1UL) /*!< Disable */ -/* Bit 15 : Write '1' to disable interrupt for event ENDEPOUT[3] */ +/* Bit 15 : Write '1' to Disable interrupt for ENDEPOUT[3] event */ #define USBD_INTENCLR_ENDEPOUT3_Pos (15UL) /*!< Position of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT3_Pos) /*!< Bit mask of ENDEPOUT3 field. */ #define USBD_INTENCLR_ENDEPOUT3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT3_Clear (1UL) /*!< Disable */ -/* Bit 14 : Write '1' to disable interrupt for event ENDEPOUT[2] */ +/* Bit 14 : Write '1' to Disable interrupt for ENDEPOUT[2] event */ #define USBD_INTENCLR_ENDEPOUT2_Pos (14UL) /*!< Position of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT2_Pos) /*!< Bit mask of ENDEPOUT2 field. */ #define USBD_INTENCLR_ENDEPOUT2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT2_Clear (1UL) /*!< Disable */ -/* Bit 13 : Write '1' to disable interrupt for event ENDEPOUT[1] */ +/* Bit 13 : Write '1' to Disable interrupt for ENDEPOUT[1] event */ #define USBD_INTENCLR_ENDEPOUT1_Pos (13UL) /*!< Position of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT1_Pos) /*!< Bit mask of ENDEPOUT1 field. */ #define USBD_INTENCLR_ENDEPOUT1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT1_Clear (1UL) /*!< Disable */ -/* Bit 12 : Write '1' to disable interrupt for event ENDEPOUT[0] */ +/* Bit 12 : Write '1' to Disable interrupt for ENDEPOUT[0] event */ #define USBD_INTENCLR_ENDEPOUT0_Pos (12UL) /*!< Position of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Msk (0x1UL << USBD_INTENCLR_ENDEPOUT0_Pos) /*!< Bit mask of ENDEPOUT0 field. */ #define USBD_INTENCLR_ENDEPOUT0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPOUT0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPOUT0_Clear (1UL) /*!< Disable */ -/* Bit 11 : Write '1' to disable interrupt for event ENDISOIN */ +/* Bit 11 : Write '1' to Disable interrupt for ENDISOIN event */ #define USBD_INTENCLR_ENDISOIN_Pos (11UL) /*!< Position of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Msk (0x1UL << USBD_INTENCLR_ENDISOIN_Pos) /*!< Bit mask of ENDISOIN field. */ #define USBD_INTENCLR_ENDISOIN_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDISOIN_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDISOIN_Clear (1UL) /*!< Disable */ -/* Bit 10 : Write '1' to disable interrupt for event EP0DATADONE */ +/* Bit 10 : Write '1' to Disable interrupt for EP0DATADONE event */ #define USBD_INTENCLR_EP0DATADONE_Pos (10UL) /*!< Position of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Msk (0x1UL << USBD_INTENCLR_EP0DATADONE_Pos) /*!< Bit mask of EP0DATADONE field. */ #define USBD_INTENCLR_EP0DATADONE_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_EP0DATADONE_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_EP0DATADONE_Clear (1UL) /*!< Disable */ -/* Bit 9 : Write '1' to disable interrupt for event ENDEPIN[7] */ +/* Bit 9 : Write '1' to Disable interrupt for ENDEPIN[7] event */ #define USBD_INTENCLR_ENDEPIN7_Pos (9UL) /*!< Position of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Msk (0x1UL << USBD_INTENCLR_ENDEPIN7_Pos) /*!< Bit mask of ENDEPIN7 field. */ #define USBD_INTENCLR_ENDEPIN7_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN7_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN7_Clear (1UL) /*!< Disable */ -/* Bit 8 : Write '1' to disable interrupt for event ENDEPIN[6] */ +/* Bit 8 : Write '1' to Disable interrupt for ENDEPIN[6] event */ #define USBD_INTENCLR_ENDEPIN6_Pos (8UL) /*!< Position of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Msk (0x1UL << USBD_INTENCLR_ENDEPIN6_Pos) /*!< Bit mask of ENDEPIN6 field. */ #define USBD_INTENCLR_ENDEPIN6_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN6_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN6_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to disable interrupt for event ENDEPIN[5] */ +/* Bit 7 : Write '1' to Disable interrupt for ENDEPIN[5] event */ #define USBD_INTENCLR_ENDEPIN5_Pos (7UL) /*!< Position of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Msk (0x1UL << USBD_INTENCLR_ENDEPIN5_Pos) /*!< Bit mask of ENDEPIN5 field. */ #define USBD_INTENCLR_ENDEPIN5_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN5_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN5_Clear (1UL) /*!< Disable */ -/* Bit 6 : Write '1' to disable interrupt for event ENDEPIN[4] */ +/* Bit 6 : Write '1' to Disable interrupt for ENDEPIN[4] event */ #define USBD_INTENCLR_ENDEPIN4_Pos (6UL) /*!< Position of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Msk (0x1UL << USBD_INTENCLR_ENDEPIN4_Pos) /*!< Bit mask of ENDEPIN4 field. */ #define USBD_INTENCLR_ENDEPIN4_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN4_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN4_Clear (1UL) /*!< Disable */ -/* Bit 5 : Write '1' to disable interrupt for event ENDEPIN[3] */ +/* Bit 5 : Write '1' to Disable interrupt for ENDEPIN[3] event */ #define USBD_INTENCLR_ENDEPIN3_Pos (5UL) /*!< Position of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Msk (0x1UL << USBD_INTENCLR_ENDEPIN3_Pos) /*!< Bit mask of ENDEPIN3 field. */ #define USBD_INTENCLR_ENDEPIN3_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN3_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN3_Clear (1UL) /*!< Disable */ -/* Bit 4 : Write '1' to disable interrupt for event ENDEPIN[2] */ +/* Bit 4 : Write '1' to Disable interrupt for ENDEPIN[2] event */ #define USBD_INTENCLR_ENDEPIN2_Pos (4UL) /*!< Position of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Msk (0x1UL << USBD_INTENCLR_ENDEPIN2_Pos) /*!< Bit mask of ENDEPIN2 field. */ #define USBD_INTENCLR_ENDEPIN2_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN2_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN2_Clear (1UL) /*!< Disable */ -/* Bit 3 : Write '1' to disable interrupt for event ENDEPIN[1] */ +/* Bit 3 : Write '1' to Disable interrupt for ENDEPIN[1] event */ #define USBD_INTENCLR_ENDEPIN1_Pos (3UL) /*!< Position of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Msk (0x1UL << USBD_INTENCLR_ENDEPIN1_Pos) /*!< Bit mask of ENDEPIN1 field. */ #define USBD_INTENCLR_ENDEPIN1_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN1_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN1_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to disable interrupt for event ENDEPIN[0] */ +/* Bit 2 : Write '1' to Disable interrupt for ENDEPIN[0] event */ #define USBD_INTENCLR_ENDEPIN0_Pos (2UL) /*!< Position of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Msk (0x1UL << USBD_INTENCLR_ENDEPIN0_Pos) /*!< Bit mask of ENDEPIN0 field. */ #define USBD_INTENCLR_ENDEPIN0_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_ENDEPIN0_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_ENDEPIN0_Clear (1UL) /*!< Disable */ -/* Bit 1 : Write '1' to disable interrupt for event STARTED */ +/* Bit 1 : Write '1' to Disable interrupt for STARTED event */ #define USBD_INTENCLR_STARTED_Pos (1UL) /*!< Position of STARTED field. */ #define USBD_INTENCLR_STARTED_Msk (0x1UL << USBD_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ #define USBD_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ #define USBD_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ #define USBD_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ -/* Bit 0 : Write '1' to disable interrupt for event USBRESET */ +/* Bit 0 : Write '1' to Disable interrupt for USBRESET event */ #define USBD_INTENCLR_USBRESET_Pos (0UL) /*!< Position of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Msk (0x1UL << USBD_INTENCLR_USBRESET_Pos) /*!< Bit mask of USBRESET field. */ #define USBD_INTENCLR_USBRESET_Disabled (0UL) /*!< Read: Disabled */ @@ -16584,27 +13805,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_INTENCLR_USBRESET_Clear (1UL) /*!< Disable */ /* Register: USBD_EVENTCAUSE */ -/* Description: Details on what caused the USBEVENT event */ +/* Description: Details on event that caused the USBEVENT event */ -/* Bit 11 : USB device is ready for normal operation. Write '1' to clear. */ +/* Bit 11 : Wrapper has re-initialized SFRs to the proper values. MAC is ready for normal operation. Write '1' to clear. */ #define USBD_EVENTCAUSE_READY_Pos (11UL) /*!< Position of READY field. */ #define USBD_EVENTCAUSE_READY_Msk (0x1UL << USBD_EVENTCAUSE_READY_Pos) /*!< Bit mask of READY field. */ #define USBD_EVENTCAUSE_READY_NotDetected (0UL) /*!< USBEVENT was not issued due to USBD peripheral ready */ #define USBD_EVENTCAUSE_READY_Ready (1UL) /*!< USBD peripheral is ready */ -/* Bit 10 : USB MAC has been woken up and operational. Write '1' to clear. */ -#define USBD_EVENTCAUSE_USBWUALLOWED_Pos (10UL) /*!< Position of USBWUALLOWED field. */ -#define USBD_EVENTCAUSE_USBWUALLOWED_Msk (0x1UL << USBD_EVENTCAUSE_USBWUALLOWED_Pos) /*!< Bit mask of USBWUALLOWED field. */ -#define USBD_EVENTCAUSE_USBWUALLOWED_NotAllowed (0UL) /*!< Wake up not allowed */ -#define USBD_EVENTCAUSE_USBWUALLOWED_Allowed (1UL) /*!< Wake up allowed */ - -/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. */ +/* Bit 9 : Signals that a RESUME condition (K state or activity restart) has been detected on the USB lines. Write '1' to clear. */ #define USBD_EVENTCAUSE_RESUME_Pos (9UL) /*!< Position of RESUME field. */ #define USBD_EVENTCAUSE_RESUME_Msk (0x1UL << USBD_EVENTCAUSE_RESUME_Pos) /*!< Bit mask of RESUME field. */ #define USBD_EVENTCAUSE_RESUME_NotDetected (0UL) /*!< Resume not detected */ #define USBD_EVENTCAUSE_RESUME_Detected (1UL) /*!< Resume detected */ -/* Bit 8 : Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. */ +/* Bit 8 : Signals that the USB lines have been seen idle long enough for the device to enter suspend. Write '1' to clear. */ #define USBD_EVENTCAUSE_SUSPEND_Pos (8UL) /*!< Position of SUSPEND field. */ #define USBD_EVENTCAUSE_SUSPEND_Msk (0x1UL << USBD_EVENTCAUSE_SUSPEND_Pos) /*!< Bit mask of SUSPEND field. */ #define USBD_EVENTCAUSE_SUSPEND_NotDetected (0UL) /*!< Suspend not detected */ @@ -16616,8 +13831,23 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_EVENTCAUSE_ISOOUTCRC_NotDetected (0UL) /*!< No error detected */ #define USBD_EVENTCAUSE_ISOOUTCRC_Detected (1UL) /*!< Error detected */ +/* Register: USBD_BUSSTATE */ +/* Description: Provides the logic state of the D+ and D- lines */ + +/* Bit 1 : State of the D+ line */ +#define USBD_BUSSTATE_DP_Pos (1UL) /*!< Position of DP field. */ +#define USBD_BUSSTATE_DP_Msk (0x1UL << USBD_BUSSTATE_DP_Pos) /*!< Bit mask of DP field. */ +#define USBD_BUSSTATE_DP_Low (0UL) /*!< Low */ +#define USBD_BUSSTATE_DP_High (1UL) /*!< High */ + +/* Bit 0 : State of the D- line */ +#define USBD_BUSSTATE_DM_Pos (0UL) /*!< Position of DM field. */ +#define USBD_BUSSTATE_DM_Msk (0x1UL << USBD_BUSSTATE_DM_Pos) /*!< Bit mask of DM field. */ +#define USBD_BUSSTATE_DM_Low (0UL) /*!< Low */ +#define USBD_BUSSTATE_DM_High (1UL) /*!< High */ + /* Register: USBD_HALTED_EPIN */ -/* Description: Description collection: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection[0]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPIN_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16626,7 +13856,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_HALTED_EPIN_GETSTATUS_Halted (1UL) /*!< Endpoint is halted */ /* Register: USBD_HALTED_EPOUT */ -/* Description: Description collection: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ +/* Description: Description collection[0]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ /* Bits 15..0 : OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. */ #define USBD_HALTED_EPOUT_GETSTATUS_Pos (0UL) /*!< Position of GETSTATUS field. */ @@ -16637,109 +13867,109 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPSTATUS */ /* Description: Provides information on which endpoint's EasyDMA registers have been captured */ -/* Bit 24 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 24 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT8_Pos (24UL) /*!< Position of EPOUT8 field. */ #define USBD_EPSTATUS_EPOUT8_Msk (0x1UL << USBD_EPSTATUS_EPOUT8_Pos) /*!< Bit mask of EPOUT8 field. */ #define USBD_EPSTATUS_EPOUT8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 23 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 23 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT7_Pos (23UL) /*!< Position of EPOUT7 field. */ #define USBD_EPSTATUS_EPOUT7_Msk (0x1UL << USBD_EPSTATUS_EPOUT7_Pos) /*!< Bit mask of EPOUT7 field. */ #define USBD_EPSTATUS_EPOUT7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 22 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 22 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT6_Pos (22UL) /*!< Position of EPOUT6 field. */ #define USBD_EPSTATUS_EPOUT6_Msk (0x1UL << USBD_EPSTATUS_EPOUT6_Pos) /*!< Bit mask of EPOUT6 field. */ #define USBD_EPSTATUS_EPOUT6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 21 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 21 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT5_Pos (21UL) /*!< Position of EPOUT5 field. */ #define USBD_EPSTATUS_EPOUT5_Msk (0x1UL << USBD_EPSTATUS_EPOUT5_Pos) /*!< Bit mask of EPOUT5 field. */ #define USBD_EPSTATUS_EPOUT5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 20 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 20 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT4_Pos (20UL) /*!< Position of EPOUT4 field. */ #define USBD_EPSTATUS_EPOUT4_Msk (0x1UL << USBD_EPSTATUS_EPOUT4_Pos) /*!< Bit mask of EPOUT4 field. */ #define USBD_EPSTATUS_EPOUT4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 19 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 19 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT3_Pos (19UL) /*!< Position of EPOUT3 field. */ #define USBD_EPSTATUS_EPOUT3_Msk (0x1UL << USBD_EPSTATUS_EPOUT3_Pos) /*!< Bit mask of EPOUT3 field. */ #define USBD_EPSTATUS_EPOUT3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 18 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 18 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT2_Pos (18UL) /*!< Position of EPOUT2 field. */ #define USBD_EPSTATUS_EPOUT2_Msk (0x1UL << USBD_EPSTATUS_EPOUT2_Pos) /*!< Bit mask of EPOUT2 field. */ #define USBD_EPSTATUS_EPOUT2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 17 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 17 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT1_Pos (17UL) /*!< Position of EPOUT1 field. */ #define USBD_EPSTATUS_EPOUT1_Msk (0x1UL << USBD_EPSTATUS_EPOUT1_Pos) /*!< Bit mask of EPOUT1 field. */ #define USBD_EPSTATUS_EPOUT1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 16 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 16 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPOUT0_Pos (16UL) /*!< Position of EPOUT0 field. */ #define USBD_EPSTATUS_EPOUT0_Msk (0x1UL << USBD_EPSTATUS_EPOUT0_Pos) /*!< Bit mask of EPOUT0 field. */ #define USBD_EPSTATUS_EPOUT0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPOUT0_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 8 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 8 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN8_Pos (8UL) /*!< Position of EPIN8 field. */ #define USBD_EPSTATUS_EPIN8_Msk (0x1UL << USBD_EPSTATUS_EPIN8_Pos) /*!< Bit mask of EPIN8 field. */ #define USBD_EPSTATUS_EPIN8_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN8_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 7 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 7 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN7_Pos (7UL) /*!< Position of EPIN7 field. */ #define USBD_EPSTATUS_EPIN7_Msk (0x1UL << USBD_EPSTATUS_EPIN7_Pos) /*!< Bit mask of EPIN7 field. */ #define USBD_EPSTATUS_EPIN7_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN7_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 6 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 6 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN6_Pos (6UL) /*!< Position of EPIN6 field. */ #define USBD_EPSTATUS_EPIN6_Msk (0x1UL << USBD_EPSTATUS_EPIN6_Pos) /*!< Bit mask of EPIN6 field. */ #define USBD_EPSTATUS_EPIN6_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN6_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 5 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 5 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN5_Pos (5UL) /*!< Position of EPIN5 field. */ #define USBD_EPSTATUS_EPIN5_Msk (0x1UL << USBD_EPSTATUS_EPIN5_Pos) /*!< Bit mask of EPIN5 field. */ #define USBD_EPSTATUS_EPIN5_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN5_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 4 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 4 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN4_Pos (4UL) /*!< Position of EPIN4 field. */ #define USBD_EPSTATUS_EPIN4_Msk (0x1UL << USBD_EPSTATUS_EPIN4_Pos) /*!< Bit mask of EPIN4 field. */ #define USBD_EPSTATUS_EPIN4_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN4_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 3 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 3 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN3_Pos (3UL) /*!< Position of EPIN3 field. */ #define USBD_EPSTATUS_EPIN3_Msk (0x1UL << USBD_EPSTATUS_EPIN3_Pos) /*!< Bit mask of EPIN3 field. */ #define USBD_EPSTATUS_EPIN3_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN3_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 2 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 2 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN2_Pos (2UL) /*!< Position of EPIN2 field. */ #define USBD_EPSTATUS_EPIN2_Msk (0x1UL << USBD_EPSTATUS_EPIN2_Pos) /*!< Bit mask of EPIN2 field. */ #define USBD_EPSTATUS_EPIN2_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN2_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 1 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 1 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN1_Pos (1UL) /*!< Position of EPIN1 field. */ #define USBD_EPSTATUS_EPIN1_Msk (0x1UL << USBD_EPSTATUS_EPIN1_Pos) /*!< Bit mask of EPIN1 field. */ #define USBD_EPSTATUS_EPIN1_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ #define USBD_EPSTATUS_EPIN1_DataDone (1UL) /*!< EasyDMA registers have been captured for this endpoint */ -/* Bit 0 : Captured state of endpoint's EasyDMA registers. Write '1' to clear. */ +/* Bit 0 : Endpoint's EasyDMA registers captured state. Write '1' to clear. */ #define USBD_EPSTATUS_EPIN0_Pos (0UL) /*!< Position of EPIN0 field. */ #define USBD_EPSTATUS_EPIN0_Msk (0x1UL << USBD_EPSTATUS_EPIN0_Pos) /*!< Bit mask of EPIN0 field. */ #define USBD_EPSTATUS_EPIN0_NoData (0UL) /*!< EasyDMA registers have not been captured for this endpoint */ @@ -16866,7 +14096,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_BREQUEST */ /* Description: SETUP data, byte 1, bRequest */ -/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. */ +/* Bits 7..0 : SETUP data, byte 1, bRequest. Values provides for standard requests only, user must implement Class and Vendor values. */ #define USBD_BREQUEST_BREQUEST_Pos (0UL) /*!< Position of BREQUEST field. */ #define USBD_BREQUEST_BREQUEST_Msk (0xFFUL << USBD_BREQUEST_BREQUEST_Pos) /*!< Bit mask of BREQUEST field. */ #define USBD_BREQUEST_BREQUEST_STD_GET_STATUS (0UL) /*!< Standard request GET_STATUS */ @@ -16924,14 +14154,14 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_WLENGTHH_WLENGTHH_Msk (0xFFUL << USBD_WLENGTHH_WLENGTHH_Pos) /*!< Bit mask of WLENGTHH field. */ /* Register: USBD_SIZE_EPOUT */ -/* Description: Description collection: Number of bytes received last in the data stage of this OUT endpoint */ +/* Description: Description collection[0]: Amount of bytes received last in the data stage of this OUT endpoint */ -/* Bits 6..0 : Number of bytes received last in the data stage of this OUT endpoint */ +/* Bits 6..0 : Amount of bytes received last in the data stage of this OUT endpoint */ #define USBD_SIZE_EPOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define USBD_SIZE_EPOUT_SIZE_Msk (0x7FUL << USBD_SIZE_EPOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ /* Register: USBD_SIZE_ISOOUT */ -/* Description: Number of bytes received last on this ISO OUT data endpoint */ +/* Description: Amount of bytes received last on this iso OUT data endpoint */ /* Bit 16 : Zero-length data packet received */ #define USBD_SIZE_ISOOUT_ZERO_Pos (16UL) /*!< Position of ZERO field. */ @@ -16939,7 +14169,7 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_SIZE_ISOOUT_ZERO_Normal (0UL) /*!< No zero-length data received, use value in SIZE */ #define USBD_SIZE_ISOOUT_ZERO_ZeroData (1UL) /*!< Zero-length data received, ignore value in SIZE */ -/* Bits 9..0 : Number of bytes received last on this ISO OUT data endpoint */ +/* Bits 9..0 : Amount of bytes received last on this iso OUT data endpoint */ #define USBD_SIZE_ISOOUT_SIZE_Pos (0UL) /*!< Position of SIZE field. */ #define USBD_SIZE_ISOOUT_SIZE_Msk (0x3FFUL << USBD_SIZE_ISOOUT_SIZE_Pos) /*!< Bit mask of SIZE field. */ @@ -16962,17 +14192,17 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_USBPULLUP_CONNECT_Enabled (1UL) /*!< Pull-up is connected to D+ */ /* Register: USBD_DPDMVALUE */ -/* Description: State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ +/* Description: State at which the DPDMDRIVE task will force D+ and D-. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). */ -/* Bits 4..0 : State D+ and D- lines will be forced into by the DPDMDRIVE task */ +/* Bits 4..0 : State at which the DPDMDRIVE task will force D+ and D- */ #define USBD_DPDMVALUE_STATE_Pos (0UL) /*!< Position of STATE field. */ #define USBD_DPDMVALUE_STATE_Msk (0x1FUL << USBD_DPDMVALUE_STATE_Pos) /*!< Bit mask of STATE field. */ -#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) */ +#define USBD_DPDMVALUE_STATE_Resume (1UL) /*!< D+ forced low, D- forced high (K state) for a timing pre-set in hardware (50 us or 5 ms, depending on bus state) */ #define USBD_DPDMVALUE_STATE_J (2UL) /*!< D+ forced high, D- forced low (J state) */ #define USBD_DPDMVALUE_STATE_K (4UL) /*!< D+ forced low, D- forced high (K state) */ /* Register: USBD_DTOGGLE */ -/* Description: Data toggle control and status */ +/* Description: Data toggle control and status. */ /* Bits 9..8 : Data toggle value */ #define USBD_DTOGGLE_VALUE_Pos (8UL) /*!< Position of VALUE field. */ @@ -16994,11 +14224,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPINEN */ /* Description: Endpoint IN enable */ -/* Bit 8 : Enable ISO IN endpoint */ +/* Bit 8 : Enable iso IN endpoint */ #define USBD_EPINEN_ISOIN_Pos (8UL) /*!< Position of ISOIN field. */ #define USBD_EPINEN_ISOIN_Msk (0x1UL << USBD_EPINEN_ISOIN_Pos) /*!< Bit mask of ISOIN field. */ -#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable ISO IN endpoint 8 */ -#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable ISO IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Disable (0UL) /*!< Disable iso IN endpoint 8 */ +#define USBD_EPINEN_ISOIN_Enable (1UL) /*!< Enable iso IN endpoint 8 */ /* Bit 7 : Enable IN endpoint 7 */ #define USBD_EPINEN_IN7_Pos (7UL) /*!< Position of IN7 field. */ @@ -17051,11 +14281,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: USBD_EPOUTEN */ /* Description: Endpoint OUT enable */ -/* Bit 8 : Enable ISO OUT endpoint 8 */ +/* Bit 8 : Enable iso OUT endpoint 8 */ #define USBD_EPOUTEN_ISOOUT_Pos (8UL) /*!< Position of ISOOUT field. */ #define USBD_EPOUTEN_ISOOUT_Msk (0x1UL << USBD_EPOUTEN_ISOOUT_Pos) /*!< Bit mask of ISOOUT field. */ -#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable ISO OUT endpoint 8 */ -#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable ISO OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Disable (0UL) /*!< Disable iso OUT endpoint 8 */ +#define USBD_EPOUTEN_ISOOUT_Enable (1UL) /*!< Enable iso OUT endpoint 8 */ /* Bit 7 : Enable OUT endpoint 7 */ #define USBD_EPOUTEN_OUT7_Pos (7UL) /*!< Position of OUT7 field. */ @@ -17140,15 +14370,6 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_FRAMECNTR_FRAMECNTR_Pos (0UL) /*!< Position of FRAMECNTR field. */ #define USBD_FRAMECNTR_FRAMECNTR_Msk (0x7FFUL << USBD_FRAMECNTR_FRAMECNTR_Pos) /*!< Bit mask of FRAMECNTR field. */ -/* Register: USBD_LOWPOWER */ -/* Description: Controls USBD peripheral low power mode during USB suspend */ - -/* Bit 0 : Controls USBD peripheral low-power mode during USB suspend */ -#define USBD_LOWPOWER_LOWPOWER_Pos (0UL) /*!< Position of LOWPOWER field. */ -#define USBD_LOWPOWER_LOWPOWER_Msk (0x1UL << USBD_LOWPOWER_LOWPOWER_Pos) /*!< Bit mask of LOWPOWER field. */ -#define USBD_LOWPOWER_LOWPOWER_ForceNormal (0UL) /*!< Software must write this value to exit low power mode and before performing a remote wake-up */ -#define USBD_LOWPOWER_LOWPOWER_LowPower (1UL) /*!< Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral */ - /* Register: USBD_ISOINCONFIG */ /* Description: Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent */ @@ -17159,21 +14380,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOINCONFIG_RESPONSE_ZeroData (1UL) /*!< Endpoint responds with a zero-length data packet in that case */ /* Register: USBD_EPIN_PTR */ -/* Description: Description cluster: Data pointer */ +/* Description: Description cluster[0]: Data pointer */ /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPIN_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPIN_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPIN_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPIN_MAXCNT */ -/* Description: Description cluster: Maximum number of bytes to transfer */ +/* Description: Description cluster[0]: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPIN_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPIN_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPIN_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPIN_AMOUNT */ -/* Description: Description cluster: Number of bytes transferred in the last transaction */ +/* Description: Description cluster[0]: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPIN_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -17201,21 +14422,21 @@ POSSIBILITY OF SUCH DAMAGE. #define USBD_ISOIN_AMOUNT_AMOUNT_Msk (0x3FFUL << USBD_ISOIN_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ /* Register: USBD_EPOUT_PTR */ -/* Description: Description cluster: Data pointer */ +/* Description: Description cluster[0]: Data pointer */ /* Bits 31..0 : Data pointer. Accepts any address in Data RAM. */ #define USBD_EPOUT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define USBD_EPOUT_PTR_PTR_Msk (0xFFFFFFFFUL << USBD_EPOUT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: USBD_EPOUT_MAXCNT */ -/* Description: Description cluster: Maximum number of bytes to transfer */ +/* Description: Description cluster[0]: Maximum number of bytes to transfer */ /* Bits 6..0 : Maximum number of bytes to transfer */ #define USBD_EPOUT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ #define USBD_EPOUT_MAXCNT_MAXCNT_Msk (0x7FUL << USBD_EPOUT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ /* Register: USBD_EPOUT_AMOUNT */ -/* Description: Description cluster: Number of bytes transferred in the last transaction */ +/* Description: Description cluster[0]: Number of bytes transferred in the last transaction */ /* Bits 6..0 : Number of bytes transferred in the last transaction */ #define USBD_EPOUT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ @@ -17246,27 +14467,10 @@ POSSIBILITY OF SUCH DAMAGE. /* Peripheral: WDT */ /* Description: Watchdog Timer */ -/* Register: WDT_TASKS_START */ -/* Description: Start the watchdog */ - -/* Bit 0 : Start the watchdog */ -#define WDT_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ -#define WDT_TASKS_START_TASKS_START_Msk (0x1UL << WDT_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ -#define WDT_TASKS_START_TASKS_START_Trigger (1UL) /*!< Trigger task */ - -/* Register: WDT_EVENTS_TIMEOUT */ -/* Description: Watchdog timeout */ - -/* Bit 0 : Watchdog timeout */ -#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos (0UL) /*!< Position of EVENTS_TIMEOUT field. */ -#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Msk (0x1UL << WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Pos) /*!< Bit mask of EVENTS_TIMEOUT field. */ -#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_NotGenerated (0UL) /*!< Event not generated */ -#define WDT_EVENTS_TIMEOUT_EVENTS_TIMEOUT_Generated (1UL) /*!< Event generated */ - /* Register: WDT_INTENSET */ /* Description: Enable interrupt */ -/* Bit 0 : Write '1' to enable interrupt for event TIMEOUT */ +/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -17276,7 +14480,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: WDT_INTENCLR */ /* Description: Disable interrupt */ -/* Bit 0 : Write '1' to disable interrupt for event TIMEOUT */ +/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ @@ -17417,7 +14621,7 @@ POSSIBILITY OF SUCH DAMAGE. #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ /* Register: WDT_RR */ -/* Description: Description collection: Reload request n */ +/* Description: Description collection[0]: Reload request 0 */ /* Bits 31..0 : Reload request register */ #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ diff --git a/cores/nRF5/SDK/components/device/nrf52840_peripherals.h b/cores/nRF5/SDK/components/device/nrf52840_peripherals.h index 4c2c60f7..4bab1694 100644 --- a/cores/nRF5/SDK/components/device/nrf52840_peripherals.h +++ b/cores/nRF5/SDK/components/device/nrf52840_peripherals.h @@ -1,59 +1,37 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef _NRF52840_PERIPHERALS_H #define _NRF52840_PERIPHERALS_H -/* Clock Peripheral */ -#define CLOCK_PRESENT -#define CLOCK_COUNT 1 - -/* Power Peripheral */ -#define POWER_PRESENT -#define POWER_COUNT 1 - -#define POWER_FEATURE_RAM_REGISTERS_PRESENT -#define POWER_FEATURE_RAM_REGISTERS_COUNT 9 - -#define POWER_FEATURE_VDDH_PRESENT -#define POWER_FEATURE_VDDH_DCDC_PRESENT - -/* Non-Volatile Memory Controller */ -#define NVMC_PRESENT -#define NVMC_COUNT 1 - -#define NVMC_FEATURE_CACHE_PRESENT - /* Floating Point Unit */ #define FPU_PRESENT #define FPU_COUNT 1 @@ -77,9 +55,6 @@ POSSIBILITY OF SUCH DAMAGE. #define P0_PIN_NUM 32 #define P1_PIN_NUM 16 -#define P0_FEATURE_PINS_PRESENT 0xFFFFFFFFUL -#define P1_FEATURE_PINS_PRESENT 0x0000FFFFUL - /* ACL */ #define ACL_PRESENT @@ -89,11 +64,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_PRESENT #define RADIO_COUNT 1 -#define RADIO_EASYDMA_MAXCNT_SIZE 8 -#define RADIO_FEATURE_IEEE_802_15_4_PRESENT - -#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos8dBm - /* Accelerated Address Resolver */ #define AAR_PRESENT #define AAR_COUNT 1 @@ -112,14 +82,11 @@ POSSIBILITY OF SUCH DAMAGE. #define NFCT_PRESENT #define NFCT_COUNT 1 -#define NFCT_EASYDMA_MAXCNT_SIZE 9 - /* Peripheral to Peripheral Interconnect */ #define PPI_PRESENT #define PPI_COUNT 1 #define PPI_CH_NUM 20 -#define PPI_FIXED_CH_NUM 12 #define PPI_GROUP_NUM 6 #define PPI_FEATURE_FORKS_PRESENT @@ -188,29 +155,10 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM2_FEATURE_HARDWARE_CSN_PRESENT 0 #define SPIM3_FEATURE_HARDWARE_CSN_PRESENT 1 -#define SPIM0_FEATURE_DCX_PRESENT 0 -#define SPIM1_FEATURE_DCX_PRESENT 0 -#define SPIM2_FEATURE_DCX_PRESENT 0 -#define SPIM3_FEATURE_DCX_PRESENT 1 - -#define SPIM0_FEATURE_RXDELAY_PRESENT 0 -#define SPIM1_FEATURE_RXDELAY_PRESENT 0 -#define SPIM2_FEATURE_RXDELAY_PRESENT 0 -#define SPIM3_FEATURE_RXDELAY_PRESENT 1 - -#define SPIM0_EASYDMA_MAXCNT_SIZE 16 -#define SPIM1_EASYDMA_MAXCNT_SIZE 16 -#define SPIM2_EASYDMA_MAXCNT_SIZE 16 -#define SPIM3_EASYDMA_MAXCNT_SIZE 16 - /* Serial Peripheral Interface Slave with DMA*/ #define SPIS_PRESENT #define SPIS_COUNT 3 -#define SPIS0_EASYDMA_MAXCNT_SIZE 16 -#define SPIS1_EASYDMA_MAXCNT_SIZE 16 -#define SPIS2_EASYDMA_MAXCNT_SIZE 16 - /* Two Wire Interface Master */ #define TWI_PRESENT #define TWI_COUNT 2 @@ -219,16 +167,10 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_PRESENT #define TWIM_COUNT 2 -#define TWIM0_EASYDMA_MAXCNT_SIZE 16 -#define TWIM1_EASYDMA_MAXCNT_SIZE 16 - /* Two Wire Interface Slave with DMA */ #define TWIS_PRESENT #define TWIS_COUNT 2 -#define TWIS0_EASYDMA_MAXCNT_SIZE 16 -#define TWIS1_EASYDMA_MAXCNT_SIZE 16 - /* Universal Asynchronous Receiver-Transmitter */ #define UART_PRESENT #define UART_COUNT 1 @@ -237,9 +179,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PRESENT #define UARTE_COUNT 2 -#define UARTE0_EASYDMA_MAXCNT_SIZE 16 -#define UARTE1_EASYDMA_MAXCNT_SIZE 16 - /* Quadrature Decoder */ #define QDEC_PRESENT #define QDEC_COUNT 1 @@ -248,10 +187,6 @@ POSSIBILITY OF SUCH DAMAGE. #define SAADC_PRESENT #define SAADC_COUNT 1 -#define SAADC_EASYDMA_MAXCNT_SIZE 15 - -#define SAADC_CH_NUM 8 - /* GPIO Tasks and Events */ #define GPIOTE_PRESENT #define GPIOTE_COUNT 1 @@ -282,29 +217,18 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM2_CH_NUM 4 #define PWM3_CH_NUM 4 -#define PWM0_EASYDMA_MAXCNT_SIZE 15 -#define PWM1_EASYDMA_MAXCNT_SIZE 15 -#define PWM2_EASYDMA_MAXCNT_SIZE 15 -#define PWM3_EASYDMA_MAXCNT_SIZE 15 - /* Pulse Density Modulator */ #define PDM_PRESENT #define PDM_COUNT 1 -#define PDM_EASYDMA_MAXCNT_SIZE 15 - /* Inter-IC Sound Interface */ #define I2S_PRESENT #define I2S_COUNT 1 -#define I2S_EASYDMA_MAXCNT_SIZE 14 - /* Universal Serial Bus Device */ #define USBD_PRESENT #define USBD_COUNT 1 -#define USBD_EASYDMA_MAXCNT_SIZE 7 - /* ARM TrustZone Cryptocell 310 */ #define CRYPTOCELL_PRESENT #define CRYPTOCELL_COUNT 1 @@ -313,6 +237,4 @@ POSSIBILITY OF SUCH DAMAGE. #define QSPI_PRESENT #define QSPI_COUNT 1 -#define QSPI_EASYDMA_MAXCNT_SIZE 20 - #endif // _NRF52840_PERIPHERALS_H diff --git a/cores/nRF5/SDK/components/device/nrf52_bitfields.h b/cores/nRF5/SDK/components/device/nrf52_bitfields.h index b27fad13..ae959d4a 100755 --- a/cores/nRF5/SDK/components/device/nrf52_bitfields.h +++ b/cores/nRF5/SDK/components/device/nrf52_bitfields.h @@ -1,35 +1,32 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef __NRF52_BITS_H #define __NRF52_BITS_H @@ -131,6 +128,2292 @@ POSSIBILITY OF SUCH DAMAGE. #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ +/* Peripheral: AMLI */ +/* Description: AHB Multi-Layer Interface */ + +/* Register: AMLI_RAMPRI_CPU0 */ +/* Description: AHB bus master priority register for CPU0 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SPIS1 */ +/* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_RADIO */ +/* Description: AHB bus master priority register for RADIO */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_ECB */ +/* Description: AHB bus master priority register for ECB */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_CCM */ +/* Description: AHB bus master priority register for CCM */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_AAR */ +/* Description: AHB bus master priority register for AAR */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SAADC */ +/* Description: AHB bus master priority register for SAADC */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_UARTE */ +/* Description: AHB bus master priority register for UARTE */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SERIAL0 */ +/* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_SERIAL2 */ +/* Description: AHB bus master priority register for SPIM2 and SPIS2 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_NFCT */ +/* Description: AHB bus master priority register for NFCT */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_I2S */ +/* Description: AHB bus master priority register for I2S */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_PDM */ +/* Description: AHB bus master priority register for PDM */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */ + +/* Register: AMLI_RAMPRI_PWM */ +/* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */ + +/* Bits 31..28 : Priority register for RAM AHB slave 7 */ +#define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ +#define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ +#define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 27..24 : Priority register for RAM AHB slave 6 */ +#define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ +#define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ +#define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 23..20 : Priority register for RAM AHB slave 5 */ +#define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ +#define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ +#define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 19..16 : Priority register for RAM AHB slave 4 */ +#define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ +#define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ +#define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 15..12 : Priority register for RAM AHB slave 3 */ +#define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ +#define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ +#define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 11..8 : Priority register for RAM AHB slave 2 */ +#define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ +#define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ +#define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 7..4 : Priority register for RAM AHB slave 1 */ +#define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ +#define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ +#define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */ + +/* Bits 3..0 : Priority register for RAM AHB slave 0 */ +#define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ +#define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ +#define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */ +#define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */ + + /* Peripheral: BPROT */ /* Description: Block Protect */ @@ -1179,18 +3462,6 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: CLOCK_LFCLKSRC */ /* Description: Clock source for the LFCLK */ -/* Bit 17 : Enable or disable external source for LFCLK */ -#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */ -#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */ -#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */ -#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */ - -/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */ -#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */ -#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */ -#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */ -#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */ - /* Bits 1..0 : Clock source */ #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ @@ -1199,7 +3470,7 @@ POSSIBILITY OF SUCH DAMAGE. #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ /* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval */ +/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */ /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ @@ -1383,7 +3654,7 @@ POSSIBILITY OF SUCH DAMAGE. #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ /* Register: COMP_REFSEL */ -/* Description: Reference source select for single-ended mode */ +/* Description: Reference source select */ /* Bits 2..0 : Reference select */ #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ @@ -1397,17 +3668,11 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_EXTREFSEL */ /* Description: External reference select */ -/* Bits 2..0 : External analog reference select */ +/* Bit 0 : External analog reference select */ #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ +#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */ -#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */ /* Register: COMP_TH */ /* Description: Threshold configuration for hysteresis unit */ @@ -1423,18 +3688,18 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: COMP_MODE */ /* Description: Mode configuration */ -/* Bit 8 : Main operation modes */ +/* Bit 8 : Main operation mode */ #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ -#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */ +#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ -/* Bits 1..0 : Speed and power modes */ +/* Bits 1..0 : Speed and power mode */ #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ -#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */ +#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ -#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */ +#define COMP_MODE_SP_High (2UL) /*!< High speed mode */ /* Register: COMP_HYST */ /* Description: Comparator hysteresis enable */ @@ -1906,10 +4171,8 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ -#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */ #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ -#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */ #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_PACKAGE */ @@ -1920,8 +4183,6 @@ POSSIBILITY OF SUCH DAMAGE. #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ -#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */ -#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */ #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ /* Register: FICR_INFO_RAM */ @@ -2693,7 +4954,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ +#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ /* Register: LPCOMP_ENABLE */ @@ -4834,193 +7095,193 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_OUT */ /* Description: Write GPIO port */ -/* Bit 31 : Pin 31 */ +/* Bit 31 : P0.31 pin */ #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ -/* Bit 30 : Pin 30 */ +/* Bit 30 : P0.30 pin */ #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ -/* Bit 29 : Pin 29 */ +/* Bit 29 : P0.29 pin */ #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ -/* Bit 28 : Pin 28 */ +/* Bit 28 : P0.28 pin */ #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ -/* Bit 27 : Pin 27 */ +/* Bit 27 : P0.27 pin */ #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ -/* Bit 26 : Pin 26 */ +/* Bit 26 : P0.26 pin */ #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ -/* Bit 25 : Pin 25 */ +/* Bit 25 : P0.25 pin */ #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ -/* Bit 24 : Pin 24 */ +/* Bit 24 : P0.24 pin */ #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ -/* Bit 23 : Pin 23 */ +/* Bit 23 : P0.23 pin */ #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ -/* Bit 22 : Pin 22 */ +/* Bit 22 : P0.22 pin */ #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ -/* Bit 21 : Pin 21 */ +/* Bit 21 : P0.21 pin */ #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ -/* Bit 20 : Pin 20 */ +/* Bit 20 : P0.20 pin */ #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ -/* Bit 19 : Pin 19 */ +/* Bit 19 : P0.19 pin */ #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ -/* Bit 18 : Pin 18 */ +/* Bit 18 : P0.18 pin */ #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ -/* Bit 17 : Pin 17 */ +/* Bit 17 : P0.17 pin */ #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ -/* Bit 16 : Pin 16 */ +/* Bit 16 : P0.16 pin */ #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ -/* Bit 15 : Pin 15 */ +/* Bit 15 : P0.15 pin */ #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ -/* Bit 14 : Pin 14 */ +/* Bit 14 : P0.14 pin */ #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ -/* Bit 13 : Pin 13 */ +/* Bit 13 : P0.13 pin */ #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ -/* Bit 12 : Pin 12 */ +/* Bit 12 : P0.12 pin */ #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ -/* Bit 11 : Pin 11 */ +/* Bit 11 : P0.11 pin */ #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ -/* Bit 10 : Pin 10 */ +/* Bit 10 : P0.10 pin */ #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ -/* Bit 9 : Pin 9 */ +/* Bit 9 : P0.9 pin */ #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ -/* Bit 8 : Pin 8 */ +/* Bit 8 : P0.8 pin */ #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ -/* Bit 7 : Pin 7 */ +/* Bit 7 : P0.7 pin */ #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ -/* Bit 6 : Pin 6 */ +/* Bit 6 : P0.6 pin */ #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ -/* Bit 5 : Pin 5 */ +/* Bit 5 : P0.5 pin */ #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ -/* Bit 4 : Pin 4 */ +/* Bit 4 : P0.4 pin */ #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ -/* Bit 3 : Pin 3 */ +/* Bit 3 : P0.3 pin */ #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ -/* Bit 2 : Pin 2 */ +/* Bit 2 : P0.2 pin */ #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ -/* Bit 1 : Pin 1 */ +/* Bit 1 : P0.1 pin */ #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ -/* Bit 0 : Pin 0 */ +/* Bit 0 : P0.0 pin */ #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ @@ -5029,224 +7290,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_OUTSET */ /* Description: Set individual bits in GPIO port */ -/* Bit 31 : Pin 31 */ +/* Bit 31 : P0.31 pin */ #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 30 : Pin 30 */ +/* Bit 30 : P0.30 pin */ #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 29 : Pin 29 */ +/* Bit 29 : P0.29 pin */ #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 28 : Pin 28 */ +/* Bit 28 : P0.28 pin */ #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 27 : Pin 27 */ +/* Bit 27 : P0.27 pin */ #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 26 : Pin 26 */ +/* Bit 26 : P0.26 pin */ #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 25 : Pin 25 */ +/* Bit 25 : P0.25 pin */ #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 24 : Pin 24 */ +/* Bit 24 : P0.24 pin */ #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 23 : Pin 23 */ +/* Bit 23 : P0.23 pin */ #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 22 : Pin 22 */ +/* Bit 22 : P0.22 pin */ #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 21 : Pin 21 */ +/* Bit 21 : P0.21 pin */ #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 20 : Pin 20 */ +/* Bit 20 : P0.20 pin */ #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 19 : Pin 19 */ +/* Bit 19 : P0.19 pin */ #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 18 : Pin 18 */ +/* Bit 18 : P0.18 pin */ #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 17 : Pin 17 */ +/* Bit 17 : P0.17 pin */ #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 16 : Pin 16 */ +/* Bit 16 : P0.16 pin */ #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 15 : Pin 15 */ +/* Bit 15 : P0.15 pin */ #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 14 : Pin 14 */ +/* Bit 14 : P0.14 pin */ #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 13 : Pin 13 */ +/* Bit 13 : P0.13 pin */ #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 12 : Pin 12 */ +/* Bit 12 : P0.12 pin */ #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 11 : Pin 11 */ +/* Bit 11 : P0.11 pin */ #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 10 : Pin 10 */ +/* Bit 10 : P0.10 pin */ #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 9 : Pin 9 */ +/* Bit 9 : P0.9 pin */ #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 8 : Pin 8 */ +/* Bit 8 : P0.8 pin */ #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 7 : Pin 7 */ +/* Bit 7 : P0.7 pin */ #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 6 : Pin 6 */ +/* Bit 6 : P0.6 pin */ #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 5 : Pin 5 */ +/* Bit 5 : P0.5 pin */ #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 4 : Pin 4 */ +/* Bit 4 : P0.4 pin */ #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 3 : Pin 3 */ +/* Bit 3 : P0.3 pin */ #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 2 : Pin 2 */ +/* Bit 2 : P0.2 pin */ #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 1 : Pin 1 */ +/* Bit 1 : P0.1 pin */ #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ -/* Bit 0 : Pin 0 */ +/* Bit 0 : P0.0 pin */ #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ @@ -5256,224 +7517,224 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_OUTCLR */ /* Description: Clear individual bits in GPIO port */ -/* Bit 31 : Pin 31 */ +/* Bit 31 : P0.31 pin */ #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 30 : Pin 30 */ +/* Bit 30 : P0.30 pin */ #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 29 : Pin 29 */ +/* Bit 29 : P0.29 pin */ #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 28 : Pin 28 */ +/* Bit 28 : P0.28 pin */ #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 27 : Pin 27 */ +/* Bit 27 : P0.27 pin */ #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 26 : Pin 26 */ +/* Bit 26 : P0.26 pin */ #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 25 : Pin 25 */ +/* Bit 25 : P0.25 pin */ #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 24 : Pin 24 */ +/* Bit 24 : P0.24 pin */ #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 23 : Pin 23 */ +/* Bit 23 : P0.23 pin */ #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 22 : Pin 22 */ +/* Bit 22 : P0.22 pin */ #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 21 : Pin 21 */ +/* Bit 21 : P0.21 pin */ #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 20 : Pin 20 */ +/* Bit 20 : P0.20 pin */ #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 19 : Pin 19 */ +/* Bit 19 : P0.19 pin */ #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 18 : Pin 18 */ +/* Bit 18 : P0.18 pin */ #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 17 : Pin 17 */ +/* Bit 17 : P0.17 pin */ #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 16 : Pin 16 */ +/* Bit 16 : P0.16 pin */ #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 15 : Pin 15 */ +/* Bit 15 : P0.15 pin */ #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 14 : Pin 14 */ +/* Bit 14 : P0.14 pin */ #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 13 : Pin 13 */ +/* Bit 13 : P0.13 pin */ #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 12 : Pin 12 */ +/* Bit 12 : P0.12 pin */ #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 11 : Pin 11 */ +/* Bit 11 : P0.11 pin */ #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 10 : Pin 10 */ +/* Bit 10 : P0.10 pin */ #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 9 : Pin 9 */ +/* Bit 9 : P0.9 pin */ #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 8 : Pin 8 */ +/* Bit 8 : P0.8 pin */ #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 7 : Pin 7 */ +/* Bit 7 : P0.7 pin */ #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 6 : Pin 6 */ +/* Bit 6 : P0.6 pin */ #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 5 : Pin 5 */ +/* Bit 5 : P0.5 pin */ #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 4 : Pin 4 */ +/* Bit 4 : P0.4 pin */ #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 3 : Pin 3 */ +/* Bit 3 : P0.3 pin */ #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 2 : Pin 2 */ +/* Bit 2 : P0.2 pin */ #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 1 : Pin 1 */ +/* Bit 1 : P0.1 pin */ #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ -/* Bit 0 : Pin 0 */ +/* Bit 0 : P0.0 pin */ #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ @@ -5483,193 +7744,193 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_IN */ /* Description: Read GPIO port */ -/* Bit 31 : Pin 31 */ +/* Bit 31 : P0.31 pin */ #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ -/* Bit 30 : Pin 30 */ +/* Bit 30 : P0.30 pin */ #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ -/* Bit 29 : Pin 29 */ +/* Bit 29 : P0.29 pin */ #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ -/* Bit 28 : Pin 28 */ +/* Bit 28 : P0.28 pin */ #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ -/* Bit 27 : Pin 27 */ +/* Bit 27 : P0.27 pin */ #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ -/* Bit 26 : Pin 26 */ +/* Bit 26 : P0.26 pin */ #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ -/* Bit 25 : Pin 25 */ +/* Bit 25 : P0.25 pin */ #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ -/* Bit 24 : Pin 24 */ +/* Bit 24 : P0.24 pin */ #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ -/* Bit 23 : Pin 23 */ +/* Bit 23 : P0.23 pin */ #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ -/* Bit 22 : Pin 22 */ +/* Bit 22 : P0.22 pin */ #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ -/* Bit 21 : Pin 21 */ +/* Bit 21 : P0.21 pin */ #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ -/* Bit 20 : Pin 20 */ +/* Bit 20 : P0.20 pin */ #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ -/* Bit 19 : Pin 19 */ +/* Bit 19 : P0.19 pin */ #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ -/* Bit 18 : Pin 18 */ +/* Bit 18 : P0.18 pin */ #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ -/* Bit 17 : Pin 17 */ +/* Bit 17 : P0.17 pin */ #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ -/* Bit 16 : Pin 16 */ +/* Bit 16 : P0.16 pin */ #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ -/* Bit 15 : Pin 15 */ +/* Bit 15 : P0.15 pin */ #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ -/* Bit 14 : Pin 14 */ +/* Bit 14 : P0.14 pin */ #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ -/* Bit 13 : Pin 13 */ +/* Bit 13 : P0.13 pin */ #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ -/* Bit 12 : Pin 12 */ +/* Bit 12 : P0.12 pin */ #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ -/* Bit 11 : Pin 11 */ +/* Bit 11 : P0.11 pin */ #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ -/* Bit 10 : Pin 10 */ +/* Bit 10 : P0.10 pin */ #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ -/* Bit 9 : Pin 9 */ +/* Bit 9 : P0.9 pin */ #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ -/* Bit 8 : Pin 8 */ +/* Bit 8 : P0.8 pin */ #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ -/* Bit 7 : Pin 7 */ +/* Bit 7 : P0.7 pin */ #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ -/* Bit 6 : Pin 6 */ +/* Bit 6 : P0.6 pin */ #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ -/* Bit 5 : Pin 5 */ +/* Bit 5 : P0.5 pin */ #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ -/* Bit 4 : Pin 4 */ +/* Bit 4 : P0.4 pin */ #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ -/* Bit 3 : Pin 3 */ +/* Bit 3 : P0.3 pin */ #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ -/* Bit 2 : Pin 2 */ +/* Bit 2 : P0.2 pin */ #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ -/* Bit 1 : Pin 1 */ +/* Bit 1 : P0.1 pin */ #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ -/* Bit 0 : Pin 0 */ +/* Bit 0 : P0.0 pin */ #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ @@ -5678,193 +7939,193 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: GPIO_DIR */ /* Description: Direction of GPIO pins */ -/* Bit 31 : Pin 31 */ +/* Bit 31 : P0.31 pin */ #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ -/* Bit 30 : Pin 30 */ +/* Bit 30 : P0.30 pin */ #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ -/* Bit 29 : Pin 29 */ +/* Bit 29 : P0.29 pin */ #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ -/* Bit 28 : Pin 28 */ +/* Bit 28 : P0.28 pin */ #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ -/* Bit 27 : Pin 27 */ +/* Bit 27 : P0.27 pin */ #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ -/* Bit 26 : Pin 26 */ +/* Bit 26 : P0.26 pin */ #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ -/* Bit 25 : Pin 25 */ +/* Bit 25 : P0.25 pin */ #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ -/* Bit 24 : Pin 24 */ +/* Bit 24 : P0.24 pin */ #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ -/* Bit 23 : Pin 23 */ +/* Bit 23 : P0.23 pin */ #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ -/* Bit 22 : Pin 22 */ +/* Bit 22 : P0.22 pin */ #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ -/* Bit 21 : Pin 21 */ +/* Bit 21 : P0.21 pin */ #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ -/* Bit 20 : Pin 20 */ +/* Bit 20 : P0.20 pin */ #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ -/* Bit 19 : Pin 19 */ +/* Bit 19 : P0.19 pin */ #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ -/* Bit 18 : Pin 18 */ +/* Bit 18 : P0.18 pin */ #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ -/* Bit 17 : Pin 17 */ +/* Bit 17 : P0.17 pin */ #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ -/* Bit 16 : Pin 16 */ +/* Bit 16 : P0.16 pin */ #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ -/* Bit 15 : Pin 15 */ +/* Bit 15 : P0.15 pin */ #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ -/* Bit 14 : Pin 14 */ +/* Bit 14 : P0.14 pin */ #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ -/* Bit 13 : Pin 13 */ +/* Bit 13 : P0.13 pin */ #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ -/* Bit 12 : Pin 12 */ +/* Bit 12 : P0.12 pin */ #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ -/* Bit 11 : Pin 11 */ +/* Bit 11 : P0.11 pin */ #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ -/* Bit 10 : Pin 10 */ +/* Bit 10 : P0.10 pin */ #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ -/* Bit 9 : Pin 9 */ +/* Bit 9 : P0.9 pin */ #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ -/* Bit 8 : Pin 8 */ +/* Bit 8 : P0.8 pin */ #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ -/* Bit 7 : Pin 7 */ +/* Bit 7 : P0.7 pin */ #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ -/* Bit 6 : Pin 6 */ +/* Bit 6 : P0.6 pin */ #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ -/* Bit 5 : Pin 5 */ +/* Bit 5 : P0.5 pin */ #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ -/* Bit 4 : Pin 4 */ +/* Bit 4 : P0.4 pin */ #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ -/* Bit 3 : Pin 3 */ +/* Bit 3 : P0.3 pin */ #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ -/* Bit 2 : Pin 2 */ +/* Bit 2 : P0.2 pin */ #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ -/* Bit 1 : Pin 1 */ +/* Bit 1 : P0.1 pin */ #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ -/* Bit 0 : Pin 0 */ +/* Bit 0 : P0.0 pin */ #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ @@ -8153,9 +10414,9 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ -/* Bits 1..0 : How a sequence is read from RAM and spread to the compare register */ +/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ -#define PWM_DECODER_LOAD_Msk (0x3UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ +#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ @@ -8170,24 +10431,24 @@ POSSIBILITY OF SUCH DAMAGE. #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ /* Register: PWM_SEQ_PTR */ -/* Description: Description cluster[0]: Beginning address in Data RAM of this sequence */ +/* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ -/* Bits 31..0 : Beginning address in Data RAM of this sequence */ +/* Bits 31..0 : Beginning address in Data RAM of sequence A */ #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ /* Register: PWM_SEQ_CNT */ -/* Description: Description cluster[0]: Amount of values (duty cycles) in this sequence */ +/* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ -/* Bits 14..0 : Amount of values (duty cycles) in this sequence */ +/* Bits 14..0 : Amount of values (duty cycles) in sequence A */ #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ /* Register: PWM_SEQ_REFRESH */ -/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded into compare register */ +/* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ -/* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */ +/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ @@ -8753,13 +11014,13 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ +#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xFFUL) /*!< Deprecated enumerator - -40 dBm */ /* Register: RADIO_MODE */ /* Description: Data rate and modulation */ @@ -8771,7 +11032,6 @@ POSSIBILITY OF SUCH DAMAGE. #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ -#define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */ /* Register: RADIO_PCNF0 */ /* Description: Packet configuration register 0 */ @@ -10307,7 +12567,7 @@ POSSIBILITY OF SUCH DAMAGE. #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: SPIM_FREQUENCY */ -/* Description: SPI frequency. Accuracy depends on the HFCLK source selected. */ +/* Description: SPI frequency */ /* Bits 31..0 : SPI master data rate */ #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ @@ -11106,21 +13366,18 @@ POSSIBILITY OF SUCH DAMAGE. #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ -#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 1 : NACK received after sending the address (write '1' to clear) */ #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ -#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ -#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ @@ -11379,12 +13636,6 @@ POSSIBILITY OF SUCH DAMAGE. #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ -/* Bit 0 : Overrun error */ -#define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */ -#define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */ - /* Register: TWIM_ENABLE */ /* Description: Enable TWIM */ @@ -11973,7 +14224,7 @@ POSSIBILITY OF SUCH DAMAGE. /* Register: UART_BAUDRATE */ /* Description: Baud rate */ -/* Bits 31..0 : Baud rate */ +/* Bits 31..0 : Baud-rate */ #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ @@ -11983,9 +14234,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ -#define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ -#define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ @@ -12068,24 +14317,12 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ -/* Bit 7 : Enable or disable interrupt for TXDRDY event */ -#define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */ - /* Bit 4 : Enable or disable interrupt for ENDRX event */ #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ -/* Bit 2 : Enable or disable interrupt for RXDRDY event */ -#define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */ -#define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */ - /* Bit 1 : Enable or disable interrupt for NCTS event */ #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -12143,13 +14380,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ -/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ -#define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ - /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ @@ -12157,13 +14387,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ -/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ -#define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ - /* Bit 1 : Write '1' to Enable interrupt for NCTS event */ #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -12223,13 +14446,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ -/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ -#define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ - /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ @@ -12237,13 +14453,6 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ -/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ -#define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ -#define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ -#define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ - /* Bit 1 : Write '1' to Disable interrupt for NCTS event */ #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ @@ -12347,9 +14556,9 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UARTE_BAUDRATE */ -/* Description: Baud rate. Accuracy depends on the HFCLK source selected. */ +/* Description: Baud rate */ -/* Bits 31..0 : Baud rate */ +/* Bits 31..0 : Baud-rate */ #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ @@ -12359,9 +14568,7 @@ POSSIBILITY OF SUCH DAMAGE. #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */ #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ -#define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */ #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ @@ -12462,14 +14669,14 @@ POSSIBILITY OF SUCH DAMAGE. #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ -/* Bits 5..0 : GPIO number P0.n onto which Reset is exposed */ +/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */ #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ -#define UICR_PSELRESET_PIN_Msk (0x3FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ +#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ /* Register: UICR_APPROTECT */ /* Description: Access Port protection */ -/* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */ +/* Bits 7..0 : Enable or disable Access Port protection. */ #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ diff --git a/cores/nRF5/SDK/components/device/nrf52_name_change.h b/cores/nRF5/SDK/components/device/nrf52_name_change.h index f7940954..952d4599 100755 --- a/cores/nRF5/SDK/components/device/nrf52_name_change.h +++ b/cores/nRF5/SDK/components/device/nrf52_name_change.h @@ -1,34 +1,32 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef NRF52_NAME_CHANGE_H #define NRF52_NAME_CHANGE_H diff --git a/cores/nRF5/SDK/components/device/nrf52_to_nrf52840.h b/cores/nRF5/SDK/components/device/nrf52_to_nrf52840.h index a32c8018..15008a93 100644 --- a/cores/nRF5/SDK/components/device/nrf52_to_nrf52840.h +++ b/cores/nRF5/SDK/components/device/nrf52_to_nrf52840.h @@ -1,35 +1,33 @@ -/* - -Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - -3. Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from this - software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - -*/ - +/* Copyright (c) 2016, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + #ifndef NRF52_TO_NRF52840_H #define NRF52_TO_NRF52840_H @@ -44,106 +42,44 @@ POSSIBILITY OF SUCH DAMAGE. /* UART */ /* The registers PSELRTS, PSELTXD, PSELCTS, PSELRXD were restructured into a struct. */ -#ifndef PSELRTS - #define PSELRTS PSEL.RTS -#endif -#ifndef PSELTXD - #define PSELTXD PSEL.TXD -#endif -#ifndef PSELCTS - #define PSELCTS PSEL.CTS -#endif -#ifndef PSELRXD - #define PSELRXD PSEL.RXD -#endif +#define PSELRTS PSEL.RTS +#define PSELTXD PSEL.TXD +#define PSELCTS PSEL.CTS +#define PSELRXD PSEL.RXD /* TWI */ /* The registers PSELSCL, PSELSDA were restructured into a struct. */ -#ifndef PSELSCL - #define PSELSCL PSEL.SCL -#endif -#ifndef PSELSDA - #define PSELSDA PSEL.SDA -#endif - - -/* LPCOMP */ -/* The hysteresis control enumerated values has changed name for nRF52840 devices. */ -#ifndef LPCOMP_HYST_HYST_NoHyst - #define LPCOMP_HYST_HYST_NoHyst LPCOMP_HYST_HYST_Disabled -#endif -#ifndef LPCOMP_HYST_HYST_Hyst50mV - #define LPCOMP_HYST_HYST_Hyst50mV LPCOMP_HYST_HYST_Enabled -#endif +#define PSELSCL PSEL.SCL +#define PSELSDA PSEL.SDA /* From nrf52_name_change.h. Several macros changed in different versions of nRF52 headers. By defining the following, any code written for any version of nRF52 headers will still compile. */ /* I2S */ /* Several enumerations changed case. Adding old macros to keep compilation compatibility. */ -#ifndef I2S_ENABLE_ENABLE_DISABLE - #define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled -#endif -#ifndef I2S_ENABLE_ENABLE_ENABLE - #define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled -#endif -#ifndef I2S_CONFIG_MODE_MODE_MASTER - #define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master -#endif -#ifndef I2S_CONFIG_MODE_MODE_SLAVE - #define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave -#endif -#ifndef I2S_CONFIG_RXEN_RXEN_DISABLE - #define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled -#endif -#ifndef I2S_CONFIG_RXEN_RXEN_ENABLE - #define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled -#endif -#ifndef I2S_CONFIG_TXEN_TXEN_DISABLE - #define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled -#endif -#ifndef I2S_CONFIG_TXEN_TXEN_ENABLE - #define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled -#endif -#ifndef I2S_CONFIG_MCKEN_MCKEN_DISABLE - #define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled -#endif -#ifndef I2S_CONFIG_MCKEN_MCKEN_ENABLE - #define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled -#endif -#ifndef I2S_CONFIG_SWIDTH_SWIDTH_8BIT - #define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit -#endif -#ifndef I2S_CONFIG_SWIDTH_SWIDTH_16BIT - #define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit -#endif -#ifndef I2S_CONFIG_SWIDTH_SWIDTH_24BIT - #define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit -#endif -#ifndef I2S_CONFIG_ALIGN_ALIGN_LEFT - #define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left -#endif -#ifndef I2S_CONFIG_ALIGN_ALIGN_RIGHT - #define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right -#endif -#ifndef I2S_CONFIG_FORMAT_FORMAT_ALIGNED - #define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned -#endif -#ifndef I2S_CONFIG_CHANNELS_CHANNELS_STEREO - #define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo -#endif -#ifndef I2S_CONFIG_CHANNELS_CHANNELS_LEFT - #define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left -#endif -#ifndef I2S_CONFIG_CHANNELS_CHANNELS_RIGHT - #define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right -#endif +#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled +#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled +#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master +#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave +#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled +#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled +#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled +#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled +#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled +#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled +#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit +#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit +#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left +#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right +#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned +#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo +#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left +#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right /* LPCOMP */ /* Corrected typo in RESULT register. */ -#ifndef LPCOMP_RESULT_RESULT_Bellow - #define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below -#endif +#define LPCOMP_RESULT_RESULT_Bellow LPCOMP_RESULT_RESULT_Below /*lint --flb "Leave library region" */ diff --git a/cores/nRF5/SDK/components/drivers_nrf/delay/nrf_delay.h b/cores/nRF5/SDK/components/drivers_nrf/delay/nrf_delay.h index 120fb2e4..f8f5f3fc 100644 --- a/cores/nRF5/SDK/components/drivers_nrf/delay/nrf_delay.h +++ b/cores/nRF5/SDK/components/drivers_nrf/delay/nrf_delay.h @@ -61,7 +61,7 @@ loop NOP NOP NOP -#if defined(NRF52_SERIES) +#ifdef NRF52 NOP NOP NOP @@ -130,7 +130,7 @@ __ASM ( " NOP\n\t" " NOP\n\t" " NOP\n\t" -#if defined(NRF52_SERIES) +#ifdef NRF52 " NOP\n\t" " NOP\n\t" " NOP\n\t" @@ -213,7 +213,7 @@ __ASM volatile ( " NOP\n" " NOP\n" " NOP\n" -#if defined(NRF52_SERIES) +#ifdef NRF52 " NOP\n" " NOP\n" " NOP\n" diff --git a/cores/nRF5/SDK/components/softdevice/s132/hex/s132_nrf52_2.0.1_license-agreement.txt b/cores/nRF5/SDK/components/softdevice/s132/hex/s132_nrf52_2.0.1_license-agreement.txt new file mode 100644 index 00000000..9ce142f2 --- /dev/null +++ b/cores/nRF5/SDK/components/softdevice/s132/hex/s132_nrf52_2.0.1_license-agreement.txt @@ -0,0 +1,96 @@ +S110/S120/S130/S132 license agreement + + +NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT + +License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120, S130 and S132 Bluetooth SoftDevice software packages +("SoftDevice"). + +You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before +downloading, installing and/or using any software or content in the SoftDevice provided herewith. + +YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS +OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF +THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS. + +IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE +INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE. + +1. Grant of License +Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license +("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated +in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this +agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit. + +2. Title +Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and +other intellectual property rights in and to the SoftDevice. + +3. No Modifications or Reverse Engineering +Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code +parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code. + +4. Distribution Restrictions +Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party. +Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein. +Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee +necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making +such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice. + +5. No Other Rights +Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be +contrary to this Agreement. + +6. Fees +Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to +comply with the Agreement. + +7. DISCLAIMER OF WARRANTY +THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS +LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR +THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE +IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE +REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE. +LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEEÂ’S +INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT. + + +8. No Support +Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how, +bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice. + +9. Limitation of Liability +In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of +procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any +special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract, +tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers, +licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or +limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliatesÂ’ liability shall be limited to +USD 50. + +10. Breach of Contract +Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably +attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both +direct and indirect costs for Nordic and its licensors. + +11. Indemnity +Licensee undertakes to indemnify, hold harmless and defend Nordic and its directors, officers, affiliates, shareholders, licensors, employees and +agents from and against any claims or lawsuits, including attorney's fees, that arise or result of the LicenseeÂ’s execution of the License and which +is not due to causes for which Nordic is responsible. + +12. Governing Law +This Agreement shall be construed according to the laws of Norway, and hereby submits to the exclusive jurisdiction of the Oslo tingrett. + +13. Assignment +Licensee shall not assign this Agreement or any rights or obligations hereunder without the prior written consent of Nordic. + +14. Termination +Without prejudice to any other rights, Nordic may cancel this Agreement if Licensee does not abide by the terms and conditions of this +Agreement. Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any +other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology. + +15. Third party beneficiaries +NordicÂ’s licensors are intended third party beneficiaries under this Agreement. + + diff --git a/cores/nRF5/SDK/components/softdevice/s132/hex/s132_nrf52_2.0.1_softdevice.hex b/cores/nRF5/SDK/components/softdevice/s132/hex/s132_nrf52_2.0.1_softdevice.hex new file mode 100644 index 00000000..3b41f758 --- /dev/null +++ b/cores/nRF5/SDK/components/softdevice/s132/hex/s132_nrf52_2.0.1_softdevice.hex @@ -0,0 +1,6919 @@ +:020000040000FA +:1000000000040020E508000079050000C508000094 +:10001000830500008D05000097050000000000002A +:1000200000000000000000000000000009090000BE +:10003000A105000000000000AB050000B5050000B0 +:10004000BF050000C9050000D3050000DD05000064 +:10005000E7050000F1050000FB05000005060000B3 +:100060000F06000019060000230600002D06000000 +:1000700037060000410600004B0600005506000050 +:100080005F06000069060000730600007D060000A0 +:1000900087060000910600009B060000A5060000F0 +:1000A000AF060000B9060000C3060000CD06000040 +:1000B000D7060000E1060000EB060000F506000090 +:1000C000FF06000009070000130700001D070000DD +:1000D00027070000310700003B070000450700002C +:1000E0004F07000059070000630700006D0700007C +:1000F00077070000810700008B07000095070000CC +:100100009F0700001FB500F003F88DE80F001FBD2A +:1001100000F0DEBB1FB56FF00100009040100390AF +:10012000029001904FF010208069000B420900F00E +:100130001F045DF822300120A04083434DF8223097 +:10014000684600F044F91FBDF0B54FF6FF734FF459 +:10015000B4751A466E1E11E0A94201D3344600E080 +:100160000C46091B30F8027B641E3B441A44F9D14B +:100170009CB204EB134394B204EB12420029EBD17E +:1001800098B200EB134002EB124140EA0140F0BD8F +:10019000DD4992B00446D1E90001CDE91001FF220A +:1001A0004021684600F03AFB94E80F008DE80F000C +:1001B000684610A902E004C841F8042D8842FAD12B +:1001C00010216846FFF7C0FF1090AA208DF8440068 +:1001D000FFF7A0FF00F0F2F84FF01024A069102202 +:1001E0006946803000F001F9A069082210A900F0EA +:1001F000FCF800F0D7F84FF080510A6949690068AF +:100200004A43824201D8102070470020704710B541 +:10021000D0E900214FF0805002EB8103026944696C +:100220006243934209D84FF01022536903EB8103D4 +:100230000169406941438B4201D9092010BD5069D1 +:10024000401C01D0002010BD0F2010BD70B501680A +:100250000446AE4D4FF01020062951D2DFE801F0E0 +:10026000320318283B1DD4E90265646829463046EC +:1002700000F0CDF82A462146304600F0B6F8AA0034 +:100280002146304600F09EFA002800D0032070BDC1 +:1002900000F050FB4FF4805007E0201DFFF7ABFF4C +:1002A0000028F4D100F046FB60682860002070BD93 +:1002B000241D94E80700920000F084FA0028F6D08C +:1002C0000E2070BD8069401C12D0201DFFF79FFFDB +:1002D0000028F6D109E08069401C09D0201DFFF7F5 +:1002E0008AFF0028EDD1606820B12046FFF750FF5B +:1002F000042070BDFFF70EFF00F060F800F052F828 +:10030000072070BD10B50C46182802D001200860E7 +:1003100010BD2068FFF79AFF206010BD4FF0102439 +:10032000A069401C05D0A569A66980353079AA2846 +:1003300008D06069401C2DD060690068401C29D03D +:1003400060692CE010212846FFF7FEFE31688142EB +:100350001CD1A16901F18002C03105E030B108CAA9 +:1003600051F8040D984201D1012000E000208A429A +:10037000F4D158B1286810B1042803D0FEE728460C +:1003800000F057F861496868086008E000F016F866 +:1003900000F008F84FF480500168491C01D000F0CB +:1003A000A3FAFEE7BFF34F8F59480168594A01F499 +:1003B000E06111430160BFF34F8FFEE74FF0102063 +:1003C0008169491C02D0806900F0ADB87047524A7B +:1003D00001681160121D416811604F4A8168103236 +:1003E0001160111DC068086070472DE9F041174683 +:1003F0000D460646002406E03046296800F0A6F8BF +:10040000641C2D1D361DBC42F6D3BDE8F08170B5CD +:100410000C4605464FF4806608E0284600F083F855 +:10042000B44205D3A4F5806405F58055002CF4D1C1 +:1004300070BD4168044609B1012500E000254FF078 +:1004400010267069A268920000F0BCF9C8B120467D +:1004500000F01AF89DB17669A56864684FF4002031 +:1004600084420AD2854208D229463046FFF7CFFFA0 +:100470002A4621463046FFF7B8FFFFF79FFFFFF7F8 +:1004800091FFFFF747FEF8E72DE9FF414FF01024F9 +:10049000616980680D0B01EB800000F6FF70010BB5 +:1004A00000200090019002900246039068460123CC +:1004B0000BE0560902F01F0C50F8267003FA0CFCF2 +:1004C00047EA0C0740F82670521CAA42F1D30AE012 +:1004D0004A0901F01F0650F8225003FA06F6354388 +:1004E00040F82250491C8029F2D3A169090B4A091E +:1004F00001F01F0150F822408B409C4340F82240FD +:10050000FFF765FFBDE8FF815809000000000020EB +:100510000CED00E00400FA050006004014480168F4 +:100520000029FCD07047134A0221116010490B6862 +:10053000002BFCD00F4B1B1D186008680028FCD056 +:100540000020106008680028FCD07047094B10B5E7 +:1005500001221A60064A1468002CFCD00160106861 +:100560000028FCD00020186010680028FCD010BDC6 +:1005700000E4014004E5014008208F49096809585A +:10058000084710208C4909680958084714208A49EF +:100590000968095808471820874909680958084711 +:1005A0003020854909680958084738208249096878 +:1005B000095808473C2080490968095808474020E5 +:1005C0007D4909680958084744207B49096809584A +:1005D0000847482078490968095808474C20764957 +:1005E000096809580847502073490968095808479D +:1005F0005420714909680958084758206E4909680C +:10060000095808475C206C49096809580847602068 +:100610006949096809580847642067490968095801 +:100620000847682064490968095808476C206249EE +:1006300009680958084770205F4909680958084740 +:1006400074205D4909680958084778205A490968A3 +:10065000095808477C2058490968095808478020EC +:1006600055490968095808478420534909680958B9 +:100670000847882050490968095808478C204E4986 +:1006800009680958084790204B49096809580847E4 +:10069000942049490968095808479820464909683B +:1006A000095808479C204449096809580847A02070 +:1006B0004149096809580847A4203F490968095871 +:1006C0000847A8203C49096809580847AC203A491E +:1006D000096809580847B020374909680958084788 +:1006E000B4203549096809580847B82032490968D3 +:1006F00009580847BC203049096809580847C020F4 +:100700002D49096809580847C4202B490968095828 +:100710000847C8202849096809580847CC202649B5 +:10072000096809580847D02023490968095808472B +:10073000D4202149096809580847D8201E4909686A +:1007400009580847DC201C49096809580847E02077 +:100750001949096809580847E420174909680958E0 +:100760000847E8201449096809580847EC2012494D +:10077000096809580847F0200F49096809580847CF +:10078000F4200D49096809580847F8200A49096802 +:1007900009580847FC2008490968095808475FF4C8 +:1007A0008070054909680958084700000348044952 +:1007B000024A034B70470000000000206809000057 +:1007C0006809000040EA010310B59B070FD1042A15 +:1007D0000DD310C808C9121F9C42F8D020BA19BA0C +:1007E000884201D9012010BD4FF0FF3010BD1AB171 +:1007F000D30703D0521C07E0002010BD10F8013BC6 +:1008000011F8014B1B1B07D110F8013B11F8014BEC +:100810001B1B01D1921EF1D1184610BD02F0FF033F +:1008200043EA032242EA024200F005B870477047EB +:1008300070474FF000020429C0F0128010F0030C42 +:1008400000F01B80CCF1040CBCF1020F18BF00F8C3 +:10085000012BA8BF20F8022BA1EB0C0100F00DB872 +:100860005FEAC17C24BF00F8012B00F8012B48BFD0 +:1008700000F8012B70474FF0000200B51346944674 +:100880009646203922BFA0E80C50A0E80C50B1F1E8 +:100890002001BFF4F7AF090728BFA0E80C5048BFFC +:1008A0000CC05DF804EB890028BF40F8042B08BF9A +:1008B000704748BF20F8022B11F0804F18BF00F896 +:1008C000012B7047014B1B68DB68184700000020B4 +:1008D00009480A497047FFF7FBFFFFF713FC00BD0B +:1008E00020BFFDE7064B1847064A1060016881F3F8 +:1008F0000888406800470000680900006809000097 +:100900001D030000000000201EF0040F0CBFEFF3D9 +:100910000881EFF30981886902380078182803D12B +:1009200000E00000074A1047074A12682C3212689C +:100930001047000000B5054B1B68054A9B589847B7 +:1009400000BD000005030000000000205409000065 +:1009500004000000001000000000000000FFFFFF86 +:040960000090D00330 +:101000008811002091B001005D960000E1AF010061 +:101010005D9600005D9600005D96000000000000F7 +:10102000000000000000000000000000EDB0010022 +:101030005D960000000000005D9600005D960000D7 +:1010400055B101005BB101005D9600005D960000A6 +:101050005D9600005D9600005D9600005D960000C4 +:1010600061B101005D9600005D96000067B101006E +:101070005D9600006DB1010073B1010079B101000E +:101080005D9600005D9600005D9600005D96000094 +:101090005D9600005D9600005D9600005D96000084 +:1010A0007FB1010085B101005D9600005D960000F2 +:1010B0005D9600005D9600005D9600005D96000064 +:1010C0008BB101005D9600005D9600005D9600000A +:1010D0005D9600005D9600005D9600005D96000044 +:1010E0005D9600005D9600005D9600005D96000034 +:1010F0005D9600005D9600005D9600005D96000024 +:101100005D9600005D96000000F002F819F09DFF6A +:101110000AA090E8000C82448344AAF10107DA4552 +:1011200001D119F092FFAFF2090EBAE80F0013F0E7 +:10113000010F18BFFB1A43F00103184748A501002F +:1011400068A501000A4410F8014B14F00F0508BF10 +:1011500010F8015B240908BF10F8014B6D1E05D083 +:1011600010F8013B6D1E01F8013BF9D1641E03D05C +:10117000641E01F8015BFBD19142E4D3704700008B +:101180000023002400250026103A28BF78C1FBD890 +:10119000520728BF30C148BF0B6070471FB500F031 +:1011A0003DF88DE80F001FBD1EF0040F0CBFEFF3DC +:1011B0000880EFF30980014A10470000AF94000057 +:1011C0008269034981614FF00100104470470000BB +:1011D000D511000001B41EB400B510F075F901B4CA +:1011E0000198864601BC01B01EBD0000F0B4404627 +:1011F000494652465B460FB402A0013001B506488D +:10120000004700BF01BC86460FBC80468946924617 +:101210009B46F0BC704700000911000019F012BF96 +:1012200070B51C4C054608202070A01C00F065F825 +:101230005920A08029462046BDE8704006F069BBD1 +:1012400010B506F071FB13490020891E087010BD0F +:1012500070B50C460F49891E097829B1A0F16001CB +:10126000532906D3012011E0602802D043F2010087 +:101270000CE020CC084E94E80E0006EB8000A0F5B0 +:101280008050241FD0F8806E2846B047206070BD83 +:10129000012070470A000020D0B1010010B50446BB +:1012A0000021012000F03FF80021182000F03BF859 +:1012B00000210B2000F037F80421192000F033F84A +:1012C00004210D2000F02FF804210E2000F02BF84F +:1012D00004210F2000F027F80421C84300F023F870 +:1012E0000721162000F01FF80721152000F01BF839 +:1012F0002046FFF795FF002010BD88210180704730 +:10130000FFF79EBF10487047104A10B514680F4B86 +:101310000F4A08331A60FFF79BFF0C48001D04605A +:1013200010BD704770474907090E002806DA00F023 +:101330000F0000F1E02080F8141D704700F1E0205C +:1013400080F800147047000003F9004310050240C4 +:101350000100000130B5FB4D044610280AD0112CC5 +:1013600006D02846122C817806D0132C08D0FFDF37 +:10137000AC7030BDFFDFFBE71129F9D0FFDFF7E7E5 +:101380001129F5D0FFDFF3E770B50EF02CF9044614 +:101390000FF062FE201AC4B206200CF0EBFA0546EC +:1013A00006200CF0EFFA2E1A07200CF0E3FA05469F +:1013B00007200CF0E7FAE349281A32188878122837 +:1013C0000DD000231A4413280BD0002002440878C3 +:1013D000022808D000201044201AC0B270BD01239A +:1013E000F0E70120F2E70120F5E7D64810B5C17813 +:1013F00094B0A9B15FF017018DF800104168CDF8E5 +:1014000002100089ADF8060009A968460AF0C3F881 +:101410000446112801D004B1FFDF14B0204610BDEE +:101420003221E9E702210CF0FABA2DE9F04194B03B +:101430001D4690460E460746FFF7F4FF04000BD00A +:101440002078222804D3A07FC0F34010A84206D100 +:10145000082014B0BDE8F08143F20200F9E737201C +:101460008DF80000ADF802703DB101208DF8040048 +:101470008DF805608DF8068002E000208DF80400EC +:1014800009A968460AF087F8A07F65F34510A077A0 +:101490000020DEE730B50446A1F120000D460A2801 +:1014A0004AD2DFE800F005070C1C2328353A3F44F8 +:1014B000FFDF42E0207820283FD1FFDF3DE0A14858 +:1014C0000178032939D08078132836D02078242851 +:1014D00033D0252831D023282FD0FFDF2DE02078EE +:1014E00022282AD0232828D8FFDF26E020782228A7 +:1014F00023D0FFDF21E0207822281ED024281CD012 +:1015000026281AD0272818D0292816D0FFDF14E063 +:101510002078252811D0FFDF0FE0207825280CD077 +:10152000FFDF0AE02078252807D0FFDF05E02078DC +:10153000282802D0FFDF00E0FFDF257030BD30B586 +:101540000B8840F67B444FF6FF72022801D093428D +:1015500004D09D1FA54224D2022802D04D88954276 +:1015600003D04D88AD1FA5421BD24C88A34218D88A +:101570008B88B3F5FA7F14D2022802D0C888904233 +:1015800005D0C88840F677450A38A84209D2C888ED +:10159000904208D0944206D05B1C6343B3EB800FAB +:1015A00001DB072030BD002030BD70B5044610F0CF +:1015B000F3F960BB207930B1082802D8217B0829D3 +:1015C00005D9072070BD217B0029FAD0F6E718B1B4 +:1015D000206810F0E1F9D0B9207B18B1A06810F0B4 +:1015E000DBF9A0B9002507E0206850F8250010F0CD +:1015F000D3F960B96D1CEDB22079A842F4D800256A +:1016000009E0A06850F8250010F0C6F908B11020D4 +:1016100070BD6D1CEDB2207BA842F2D8002070BDD9 +:1016200010B5028943F6FD73111F994212D2418908 +:1016300004290FD3B1F5804F0CD891420AD8017814 +:10164000890705D5406818B1FFF7AFFF002800D122 +:10165000002010BD072010BDF0B50024059D10B17D +:10166000A94203D851E009B90020F0BD0920F0BD1E +:10167000055D8DB107197E78112E3FD00FDC0A2E43 +:101680003CD2DFE806F03B1624242A2A2C2C3333E4 +:10169000025D72BB641CE4B28C42F9D3E4E71D2EF8 +:1016A0002CDAA6F11206042E28D2DFE806F027274E +:1016B0001018022DDAD1BD781D70072D01D26D07EB +:1016C00001D40A20F0BD157845F0010515E0EE4380 +:1016D000F60707E0012D07D010E00620F0BD2E0729 +:1016E000A6F18056002EF5D06046F0BD1578AE0705 +:1016F00001D50B20F0BD45F002051570055D641C99 +:101700002C44E4B28C4202D9B0E74FF4485C8C42DE +:10171000AED3A9E710B504784CB1012243F20223FD +:10172000012C07D0022C0FD0032C17D112E000227D +:101730000A7015E00A7082790324B4EB921F0DD170 +:101740000EE00000A80100200A708479B2EB941F1B +:1017500004D105E00A708279920901D0184610BDC3 +:1017600050F8012F41F8012F80888880002010BD9B +:1017700008B538B1FEA06B4600680090487903EBCD +:10178000901000781070086842F8010F88889080E7 +:1017900008BD30B50C46097895B0222902D2082040 +:1017A00015B030BD28218DF80010ADF80200132AC5 +:1017B00003D03B2A01D00720F2E78DF8042009A9C5 +:1017C000684609F0E8FE050003D121212046FFF715 +:1017D00061FE2846E4E700B595B023218DF800109E +:1017E000ADF802001088ADF804005088ADF806008E +:1017F000D088ADF80A009088ADF808000020ADF858 +:101800000C00ADF80E0009A9684609F0C4FE15B039 +:1018100000BD70B50E46050003D00021092010F070 +:1018200078F8D44C0120022EE0701CD0032E00D09A +:10183000FFDF0621201D0FF061FD607A20F0C0005F +:1018400084F80900FFF7D1FD608A00280AD0002D36 +:1018500008D083000122002109200FF0BDFF0928D4 +:1018600000D0FFDF70BD0321E01D0FF047FD607A5F +:1018700020F0C00040F040006072E01C02F03BFC31 +:10188000E0E72DE9FF410220BA4E8DF80400002761 +:10189000F08AADF80600B84655E001A80CF029F82A +:1018A000050006D0F08AB0B3A6F81680ADF8068021 +:1018B00047E0039C2078212843D0A07F01072BD547 +:1018C00004F123000090A28EBDF80800214604F127 +:1018D000360301F02BFD050003D011282AD0FFDFCD +:1018E00028E0A07F20F00800A077E07F810861F366 +:1018F0000000C10861F34100E07794F8210000F096 +:101900001F0084F820002078282824D1292120468F +:10191000FFF7C0FD1FE01CE0400712D5BDF808002E +:10192000214604F10E02FFF756FF050004D01128EE +:1019300000D0FFDF00250EE0A07F20F00400A0779C +:1019400009E07F1CFFB202200CF014F8401CB842E2 +:10195000A3D8052D07D0BDF80600F082052D04D0D0 +:10196000284604B076E5A6F816800020F9E72DE9B0 +:10197000F047040000D1FFDF20787E4E20F00F00FA +:10198000801C20F0F0007030207060680178091F22 +:1019900011290BD2DFE801F0F1090A4FF00A0CF02F +:1019A000F0360A0A0A0AF174F100FFDFBDE8F08799 +:1019B00087883846FFF736FD050000D1FFDF6078E5 +:1019C000212140F008006070307D40F00400307547 +:1019D0002846FFF75FFD384606F0E7FC384603F07F +:1019E00023FC384604F03DFC394602200FF091FFFD +:1019F000A87F20F01000A877FFF743FF0028D5D07C +:101A0000FFDFD3E785882846FFF70CFD00B9FFDF2D +:101A100060688078012800D0FFDF606881792846FF +:101A200006F027FF0028C1D0617841F008016170FD +:101A30006168C880BAE786883046FFF7F3FC050086 +:101A400000D1FFDF6078314640F0080060706068C8 +:101A5000C088288160680089688160684089A881A1 +:101A600002200FF056FF0020A875A87F00F00300A9 +:101A700002289BD1FFF705FF002897D0FFDF95E7ED +:101A800080783C2803D0002502280AD000E00125F8 +:101A9000002720B13C2802D0022800D0FFDF17B178 +:101AA0007EE00127F5E7607840F008006070307D47 +:101AB00040F008003075EDBB606802218788384629 +:101AC0000BF0A4FF0546032138460BF09FFF82462A +:101AD000052138460BF09AFF8146042138460BF069 +:101AE00095FF804605B9FFDFBAF1000F00D1FFDF97 +:101AF000B9F1000F00D1FFDFB8F1000F00D1FFDF17 +:101B000022212846FFF7C6FC60688079012837D07B +:101B10004FF00208A87F68F30100A8776068C08AC8 +:101B200028816068008B68816068408BA88160684C +:101B3000C07900E027E0E87560688168A961808964 +:101B4000A8836068807B6870606850F80F1FC5F8D4 +:101B500002108088E880A87F00F00301384606F074 +:101B600016FCB8F1010F0ED0B8F1020F18D005E045 +:101B70000302FF01A80100201FE023E0FFDF15E7BB +:101B80004FF00108C6E73078032800D0FFDF0021BE +:101B900008460FF0BEFEBDE8F047012000F087BF09 +:101BA000B078132800D0FFDF002107200FF0B1FE2E +:101BB000BDE8F0471120FFF7CDBB2046BDE8F04758 +:101BC00001F08CBE607840F008006070EEE62DE910 +:101BD000F0470546007800270009DFF894A69146F3 +:101BE0000C463E46012871D0BC464FF6FF710228D4 +:101BF0006DD0072809D00A286AD0FFDFA9F8006055 +:101C00000CB1278066800020D0E6686804F10802E5 +:101C100003780D2B40D006DC042B7DD0072B44D05D +:101C20000A2B7AD106E0122B46D0132B51D0142B5D +:101C3000F7D1C0E011270926002C6FD0B0F804803E +:101C4000A4F804806868807920729AF814104046DD +:101C500021F004018AF8141004210BF0F2FE052192 +:101C600040460BF0EEFE002140460BF0EAFE01215B +:101C700040460BF0E6FE032140460BF0E2FE022157 +:101C800040460BF0DEFE062140460BF0DAFE07214F +:101C900040460BF0D6FEB1E701270926002CCCD038 +:101CA0008088A080686880790EE0122710268088DE +:101CB000214600F01EFFA1E71C270926002CBCD0FE +:101CC0004088A08068680079207297E78AE0B3E0D6 +:101CD00082E081783C2938D010272026002CACD017 +:101CE0008088A0806868C08A60836868C08A208312 +:101CF0006868008BA0836868408BE0836868417FD8 +:101D0000E07D61F30000E0756968497F490861F38F +:101D10004700E075696802E022E05CE08BE0C8798A +:101D20000831FFF725FD696804F10F0201F10F008A +:101D30008B7B01461846FFF71BFD6868807910B160 +:101D40000120A07507E00220FBE71B270926002CD5 +:101D500071D084F808C09AF8141021F008018CE0C2 +:101D60001D273026002C66D0A1806868411D0079AF +:101D7000FFF7FEFC686890F82B00E0736868C07895 +:101D80000428207C14D020F00100207469681F22F0 +:101D9000C97861F3420020746968C97A61F3C700A9 +:101DA0002074696804F111000C3119F04DF825E731 +:101DB00040F00100E9E720271026E4B3A18068681D +:101DC00004F10902407A20726968CB1C88781946B0 +:101DD000FFF7CEFC12E74A4621462846BDE8F04709 +:101DE00001F001BF287E012803D0022813D0FFDFB5 +:101DF00004E71F271026F4B16888A080688B208133 +:101E0000A88B6081E88BA081288CE0819AF814105F +:101E100021F0200131E012271026688800F069FEC9 +:101E20004CB1687800F007000328C0D19AF814106C +:101E300021F0020121E027E0287E062822D2DFE8F7 +:101E400000F0040F0F030303C5E71B270926DCB1CD +:101E5000A18084F808C09AF8141021F001010CE068 +:101E60001B27092684B1A180287E012808D00320E1 +:101E700020729AF8141021F010018AF81410BDE6AF +:101E80000220F5E7FFDFB9E6A9F80060BBE610B570 +:101E9000F74894B08078132802D0082014B010BD01 +:101EA00022208DF8000009A9684609F074FB044659 +:101EB000002107200FF02DFD2046EFE700B5EC488C +:101EC00095B08078122801D00820A0E41E208DF85B +:101ED000000000208DF802008DF8030009A9684673 +:101EE00009F059FB0028F0D1002107200FF011FD67 +:101EF0001120FFF72FFA002089E400B5DC4895B0E7 +:101F00000078022803D0032801D008207FE41B209A +:101F10008DF8000000208DF8020009A9684609F03C +:101F20003AFB0028F2D1002108460FF0F2FC012014 +:101F300000F0BDFD00206AE42DE9F0410027CC4C03 +:101F40000A287CD2DFE800F0057B1C7B7B7B7B448E +:101F50003B6AFFF7D2FF002831D105F021FC0028B1 +:101F60002DD0017821F00F01891C21F0F0012031E2 +:101F70000170077605F0F2FB207D40F001001DE0C6 +:101F80008EB23046FFF74EFA050000D1FFDF287809 +:101F9000212814D005F004FC98B1017821F00F013C +:101FA000891C21F0F0011031017002210176468078 +:101FB000AF7505F0D3FB207D40F002002075BDE831 +:101FC000F08129463046BDE8F0411322FFF7E1BB1E +:101FD000A578122D03D0132D04D0FFDFEFE7FFF714 +:101FE0006DFF01E0FFF753FF0028E8D105F0D8FBB3 +:101FF0000028E4D0017821F00F01891C21F0F001C4 +:1020000020310170122D07D00221017605F0A6FBC8 +:10201000207D40F01000D1E70121F6E7607A012130 +:10202000B1EB901F02D1022104E008E0800900D04A +:10203000FFDF0321BDE8F0410020FFF7EABBFFDF2F +:10204000BDE72DE9F04114460D00074600D1FFDF42 +:102050002878012803D0022821D0FFDFAFE73846D7 +:10206000FFF7E0F9060000D1FFDF0220B07520780D +:1020700020F00F00801C20F0F000103020706078FD +:1020800040F0080060702868A0616868E0612889F5 +:1020900020847748017D41F0200101758FE73846A3 +:1020A000FFF7C0F9060000D1FFDF69884FF6FF7027 +:1020B000814209D1AA88824206D131463846BDE81C +:1020C000F0411322FFF765BB814201D1A88898B186 +:1020D000207820F00F00801C20F0F00010302070DD +:1020E000607840F0080060702868A0616868E0616E +:1020F00028892084002006E0782300223946022027 +:102100000FF06AFB0120B07559E730B5054695B070 +:102110000C4608460FF040FC78BB00200121203D12 +:10212000062D5FD2DFE805F0032540444A57002121 +:1021300008200FF0C7FB10B1112015B030BD2420CE +:102140008DF80000D4F80200CDF80200A0798DF8D7 +:10215000060009A9684609F01EFA05002CD10823DB +:102160000022114618460FF037FB082824D0FFDF65 +:1021700022E060680FF052FC08B11020DDE73C203F +:102180008DF800002088ADF802006088ADF80400EA +:1021900009A9684609F0FFF905000DD1606858B13A +:1021A000BDF82810018007E0206801F0E2FF02E09E +:1021B000204600F0B1FC05462846BEE73D220BE074 +:1021C0008DF8021002E000BF8DF8020009A96846F0 +:1021D00009F0E1F9EFE734228DF800202278D207E8 +:1021E000F2D0EDE70720A8E730B5054695B00C46DC +:1021F00008460FF0F5FB70BB203D052D35D2DFE81A +:1022000005F00323232523002088FFF70BF920B1D5 +:102210000078222804D208208FE743F202008CE7DE +:1022200025208DF800002088ADF8020009A9684635 +:1022300009F0B1F9002880D1DDF82A10C4F80210A5 +:102240009DF82E10A17178E7062076E7206838B156 +:102250000FF0E4FB08B110206FE7206801F07DFF6C +:102260000348408AA080002067E7072065E7000058 +:10227000A8010020FE487047FD4810B518210A3813 +:1022800018F059FE012000F012FC1120FFF762F84F +:10229000F74C00200A3C211D60744FF4617060828D +:1022A000E01C05F045FBD4F80300C4F80A00B4F8BC +:1022B0000700E081607A2074FFF797F800B1FFDF34 +:1022C00000F09CFCBDE8104001F0C2BA10B50C460D +:1022D0003E21204618F02FFEA07F20F00300A077BB +:1022E000202020700020A07584F8220010BD7047C7 +:1022F0002DE9FC4105460E4608460FF04DFB10B196 +:102300001020BDE8FC81DA4C0A3C15B1012D38D112 +:102310002CE0D4F803000090B4F80700ADF80400F6 +:102320008046677A8DF80670E11C3046FFF7F2F9B7 +:102330000028E6D1FFF759F830B10099C4F803102E +:10234000A4F807806772DCE7307808B1012808D16B +:10235000D4F80300C4F80A00B4F80700E081607AFA +:102360002074002109200FF0D4FA0FE0317841B138 +:10237000012906D0022906D0032904D043F2022005 +:10238000BFE70720BDE70120FFF743FA657400208F +:10239000B7E710B504460FF023FB08B1102010BDBD +:1023A000B34922460A39C878091DFFF7E1F9002030 +:1023B00010BD2DE9F0419AB0054600208DF85C0073 +:1023C0008DF858008DF828008DF860001E461446E0 +:1023D000884628460FF02BFB18B920460FF027FB44 +:1023E00010B110201AB0EAE555EA040018D01F27F2 +:1023F0000AAB17AA414628460097FFF72DF9002897 +:10240000F0D118AB16AA314620460097FFF724F901 +:102410000028E7D19DF85800C00703D00A20E1E763 +:102420000720DFE701AF7DB11A208DF804008DF899 +:10243000068042462946F81C18F006FD0BA901A8A3 +:1024400009F0A9F80028CDD17CB120208DF8040036 +:102450008DF8066032462146F81C18F0F5FC0BA9F1 +:1024600001A809F098F80028BCD181499DF82800FE +:102470000A3948700020B5E770B506460A200C46B8 +:10248000087015461146204609F085F830B9382104 +:1024900021702046294609F07EF820B1082801D194 +:1024A00043F2032070BD2A462146304600F05BFB14 +:1024B0000446082800D1FFDF204670BD2DE9F04119 +:1024C0006CA196B00446D1E90001CDE914010027C2 +:1024D00020460FF061FA30B92078012806D16068F3 +:1024E0000FF05AFA10B1102016B068E5604D0A3DA1 +:1024F0002878012801D00820F6E707200BF042FADF +:1025000018B9207848B1012807D0FEF73DFF30B157 +:10251000287D10F00C0F09D103E01220E4E713200E +:10252000E2E7C10702D1A846800701D51120DBE709 +:10253000208A43F6E172A0F120019142217807D36D +:10254000012942D1002840D1618A00293DD10FE004 +:10255000022901D0032901D1A02836D3012907D0AF +:1025600098F80110C90703D0618A71B3B4292CD837 +:10257000217831B1012908D0022904D0032924D1BE +:1025800015E0002516E0022514E008B9608A60B164 +:1025900004256068007868B101280AD0022808D0B4 +:1025A000032806D043F202209EE70125F1E7032528 +:1025B00000E00127207A30B1012807D0022807D097 +:1025C00003286AD106E0002605E066E0012602E065 +:1025D000022600E003260DB1022D13D196B1E0686A +:1025E00018B1FEF7E2FF002886D198F801008007B5 +:1025F00002D043F2012077E7022D03D1022E4CD006 +:10260000032E4AD018208DF82C00208AADF82E0019 +:10261000208AADF830008DF8325098F80310002071 +:102620004FF0010811B1012968D102E08DF83300A3 +:1026300001E08DF833808DF834702178012925D0A0 +:10264000CDF83500ADF839008DF83C60207DC0F341 +:102650004002014662F35F01C0F3800041EA80005E +:1026600014A9085C8DF83B00B8B169460BA805E0D9 +:10267000B2010020070605040302010008F08BFFE9 +:10268000002891D15DB1022D09D011E0606850F8A9 +:10269000011FCDF835108088D4E7072024E73EB12C +:1026A000E06828B16A460BA9FFF7E6FE0028A2D130 +:1026B0001B208DF82C008DF82E8069460BA808F0A1 +:1026C0006AFF002897D19DF801001B2816D1052D1F +:1026D00009D2DFE805F0030305050300032000E04D +:1026E000022000F0E4F9012D0AD0608A40B10022F6 +:1026F0008300114610460FF06FF808B10320F3E68F +:102700000020F1E62DE9FC4107460D460326084668 +:102710000FF08DF9002863D13846FEF783FE0400E0 +:1027200004D02078222804D20820EAE543F20200EF +:10273000E7E5A07F00F0030C2DB129466046FEF7C7 +:10274000FEFE0600F1D1F948BCF1010F05D0BCF145 +:10275000020F17D0FFDF3046D3E5A27D2946012ABC +:1027600002D0007D800701D51120CAE529B968464D +:1027700000F0FDFA0028D8D16946384605F0F6FF8A +:102780000646E8E7A17D022914D1007D800611D418 +:1027900025B1A07F40070BD4002100E0012138467D +:1027A00006F02FF80600D6D1A075002DD3D002E098 +:1027B0001126D0E7A5B12A4621463846FFF70BF887 +:1027C00006461128C7D1A07F4107C4D4296844F820 +:1027D0000E1F6968616040F0040020740026BAE7AB +:1027E00010208EE570B50C460546FEF71BFE010075 +:1027F00005D022462846BDE87040FEF7CABF43F226 +:10280000020070BD00B595B031218DF800108DF833 +:10281000020009A9684608F0BEFE15B000BD0123FC +:10282000FEF703BE00231A461946FEF7FEBD70B53B +:1028300094B004460FF0B0F810B1102014B070BD81 +:102840002046FEF7EDFE0028F8D1B84DA8781128F3 +:1028500001D00820F2E7FEF797FD20B1287DC006E1 +:1028600003D51120EAE71320E8E71D208DF80000CA +:10287000207800F001008DF802002089ADF80400F6 +:102880006089ADF806002078C0F340008DF809009B +:10289000E8780025012618B1012804D00320CDE7EF +:1028A0008DF8085001E08DF8086009A9684608F025 +:1028B00072FE0028C2D12078800707D5606828B151 +:1028C00009AA6946FFF7D8FD0028B7D11E208DF868 +:1028D00000008DF802608DF8035009A9684608F0E1 +:1028E0005AFE0028AAD1A08900F0F5F80400A5D16D +:1028F0001220FEF72FFD2046A0E7F0B595B0154653 +:102900000C4607460FF093F838B920460FF044F80C +:1029100018B928460FF040F810B1102015B0F0BDDE +:10292000824E307D10F0180F01D1400701D51120E3 +:10293000F4E72046FEF774FE0028EFD12078C0F3BC +:102940004001394302D0800702D50FB10720E5E7E7 +:1029500029460220FEF7F3FD0028DFD1B0781128C8 +:1029600003D0122801D00820D8E706200BF00AF87F +:1029700018B1B078122802D005E01220CEE7FFF798 +:102980009DFA0028CAD1FEF7FFFC022801D21320CD +:10299000C4E72078800707D5606828B109AA69468E +:1029A000FFF76AFD0028B9D121208DF800002089A9 +:1029B000ADF802006089ADF8040020784FF0010105 +:1029C000C0F340008DF80600207882074FF0000029 +:1029D00015D43A7842B1012A09D0022A07D0032A35 +:1029E00005D043F2022099E78DF8070001E08DF849 +:1029F000071057F8012F0292BA88ADF80C20F27830 +:102A00001AB1012A04D0032088E78DF80E0001E0F6 +:102A10008DF80E102988ADF810106988ADF81210E5 +:102A2000A988ADF81410E988ADF81800ADF81610B3 +:102A3000ADF81A0009A9684608F0ADFD002886D156 +:102A4000A08900F048F804008ED11320FEF782FC24 +:102A5000204663E730B5054695B00C4608460EF0B3 +:102A6000BFFF10B1102015B030BD2846FEF7DAFCCC +:102A700038B10178222902D3807F800604D408204F +:102A8000F1E743F20200EEE713208DF80000ADF805 +:102A9000025009A9684608F07EFD0028E3D19DF99F +:102AA0002A107F2901D02170DDE70520DBE730B552 +:102AB0001E4D040008D0012C04D0022C06D0032C9B +:102AC00004D0FFDF2C7030BDFFDFFBE72878012842 +:102AD000F8D0FFDFF6E710B548B1830000221146B9 +:102AE00007200EF079FE072801D0032010BD00203A +:102AF00010BD70B50C0006460DD0FEF793FC050026 +:102B000000D1FFDFA680288920812889608168891B +:102B1000A081A889E08170BD10B50446006840B16D +:102B20000EF085FF20B1102010BD0000A80100208C +:102B3000206801F005FBA0882F4C6082607C012892 +:102B40000FD1002109200EF0BDFE00B10120617AF5 +:102B50000122B2EB911F01D1022100E00321FEF717 +:102B600058FE0020E0E72DE9F047002592460C468C +:102B70000646A8464FF001090B2721E0306850F8BF +:102B80002500007820B1012805D00720BDE8F08796 +:102B900084F8028001E084F80290306850F8250043 +:102BA00050F8011FC4F803108088A4F807002770AC +:102BB0005146204608F0EFFC0028E7D16D1CEDB22D +:102BC0003079A842DAD8002539270FE0B068102202 +:102BD00050F82510A01C18F037F9277051462046F0 +:102BE00008F0D9FC0028D1D16D1CEDB2307BA84291 +:102BF000ECD80020CAE70000A8010020E848002126 +:102C00000160818070472DE9FF41804692B01C46EB +:102C10000E4618460EF0C0FE18B1102016B0BDE8E2 +:102C2000F08121460120FEF78AFC0028F6D101251B +:102C30008DF842504FF4C050ADF84000002210A96A +:102C4000284603F0ACFD0028E8D18DF842504FF43F +:102C50002850ADF8400000271C216846099718F05D +:102C60008CF99DF82400ADF8346020F00F00401C72 +:102C700020F0F00010308DF824009DF82500ADF80C +:102C8000367020F0FF008DF825009DF8260007AA79 +:102C900020F00600801C40F001008DF826009DF811 +:102CA00000000BA940F002008DF800001F20ADF8D5 +:102CB000380009A80C9010A80B90CDF83C8068460D +:102CC00003F070FB0028A9D1B54EBDF81C0007AA7F +:102CD00030808DF8425042F60120ADF840009DF85A +:102CE00026000BA920F00600801C20F001008DF8C2 +:102CF00026000220ADF83400ADF8380014A80F907B +:102D0000684603F04FFB002888D1BDF81C00708096 +:102D1000311D204600F0ECF880E73EB5044608205F +:102D2000ADF8000020460EF037FE08B110203EBD81 +:102D300021460120FEF703FC0028F8D12088ADF8D9 +:102D400004006088ADF80600A088ADF80800E088AF +:102D5000ADF80A00924801AB6A468088002103F072 +:102D60000BFFBDF800100829E1D003203EBD1FB5C0 +:102D70000446002002900820ADF80800CDF80CD0E1 +:102D800020460EF009FE10B1102004B010BD84489A +:102D900002AA81884FF6FF7004F07DF80028F4D174 +:102DA000BDF80810082901D00320EEE7BDF8001097 +:102DB0002180BDF802106180BDF80410A180BDF82B +:102DC0000610E180E1E701B582B00220ADF8000015 +:102DD000734802AB6A464088002103F0CDFEBDF87F +:102DE0000010022900D003200EBD1CB50021009167 +:102DF0000221ADF8001001900EF0F2FD08B1102094 +:102E00001CBD67486A4641884FF6FF7004F043F8DE +:102E1000BDF800100229F3D003201CBDFEB5074603 +:102E200014460E4608460EF0B7FD08B11020FEBD50 +:102E30001F2C01D90C20FEBD38460EF0ADFD584DBB +:102E400018BB288801A903F023F80028F3D13878AB +:102E50008DF80500288801A903F06FFE0028EAD14B +:102E600000909DF800009DF8051040F002008DF8DC +:102E70000000090703D040F008008DF80000288802 +:102E8000694603F0FDFD0028D5D1ADF8084028883B +:102E9000334602AA002103F06FFEBDF80810A142DC +:102EA000C9D00320FEBD7CB50546002000900190EE +:102EB0000888ADF800000C46284601950EF0AEFDDE +:102EC00018B920460EF08CFD08B110207CBD15B15C +:102ED000BDF8000050B132486A4601884FF6FF70D5 +:102EE00003F0D9FFBDF8001021807CBD0C207CBD13 +:102EF00030B593B0044600200D460090142101A87F +:102F000018F03BF81C2108A818F037F89DF80000CD +:102F1000CDF808D020F00F00401C20F0F000103059 +:102F20008DF800009DF8010006AA20F0FF008DF842 +:102F300001009DF8200001A940F002008DF820005A +:102F400001208DF8460042F60420ADF8440011A897 +:102F500001902088ADF83C006088ADF83E00A08864 +:102F6000ADF84000E088ADF842009DF8020020F086 +:102F70000600801C20F001008DF802000820ADF84A +:102F80000C00ADF810000FA8059008A803F00AFA8D +:102F9000002803D1BDF818002880002013B030BDF0 +:102FA00010000020094810B504680A490848086064 +:102FB0000DF07AFB0848046010BD08490020086045 +:102FC0004FF0E0210220C1F8800270471005024056 +:102FD000010000011805024014050240FC1F0040DA +:102FE00070B50C46054606F0B1FE21462846BDE800 +:102FF000704007F08EBE704770477047704770474B +:1030000010FFFFFFDBE5B15100C001008800FFFFAA +:1030100010B504460EF0C0FC08B1102010BD207899 +:10302000C0F30210042807D86078072804D3A178D9 +:10303000102901D8814201D2072010BDE078410754 +:1030400006D421794A0703D4000701D4080701D523 +:10305000062010BD002010BD10B513785C08C37F9A +:1030600064F30003C3771478A40864F34103C377BF +:103070001078C309887863F34100887013781C09BD +:103080004B7864F347134B701378DB0863F300004D +:1030900088705078487110BD10B5C4780B7864F30F +:1030A00000030B70C478640864F341030B70C478A8 +:1030B000A40864F382030B70C478E40864F3C303C8 +:1030C0000B700379117863F30001117003795B08C9 +:1030D00063F34101117003799B0863F3820111705E +:1030E0000079C00860F3C301117010BD70B51446BB +:1030F0000D46064604F054FB80B10178142221F0FD +:103100000F01891C21F0F001A03100F8181B2146A5 +:1031100017F0DFFEBDE8704004F020BB29463046C2 +:10312000BDE870401322FEF734BB70B514460E465E +:10313000054604F035FB70B1017821F00F01891CC0 +:1031400021F0F00120310170458021688161BDE8E6 +:10315000704004F003BB31462846BDE8704013229E +:10316000FEF717BB10B5FE4C94F8300000280CD1C8 +:1031700004F120014FF6FF72A1F110000CF0A9F844 +:1031800000B1FFDF012084F8300010BD2DE9F047C9 +:10319000064608A8894690E830041F469046142148 +:1031A000284617F0EAFE0021CAF80010B8F1000F17 +:1031B00003D0B9F1000F03D114E03878C00711D063 +:1031C00020680EF00DFCE8BBB8F1000F07D12068B5 +:1031D000123028602068143068602068A860216878 +:1031E000CAF800103878800727D560680EF016FC02 +:1031F00040BBB9F1000F2CD0FFF73CF80168C6F8CE +:10320000B4118188A6F8B811807986F8BA01FFF761 +:10321000A9FFDFF84C8308F12008C5F80C8062682C +:103220005AB196F8B40106F2B5111032FEF7A0FAC1 +:1032300010224146606817F007FE3878400712D523 +:10324000A06800E002E00EF0CBFB50B11020BDE81A +:10325000F08760680028F9D0E8606068C6F8B001BF +:10326000EBE7A06828610020F1E730B50546087853 +:103270000C4620F00F00401C20F0F00110312170AE +:103280000020607095F8220030B104280FD0052886 +:1032900011D0062814D0FFDF20780121B1EB101FD8 +:1032A00004D295F8200000F01F00607030BD21F0BE +:1032B000F000203002E021F0F00030302070EBE729 +:1032C00021F0F0004030F9E710B510B190F8A940B6 +:1032D00044B1A34890F8354000205CB1086010600C +:1032E000186010BD00F1A8040C6000F1D001F830A6 +:1032F0001160F5E79A4C34340C60F0E700B58BB000 +:103300000823CDE902128DF8013001919449002380 +:1033100064310591099301468DF8103068460BF031 +:10332000B0FF002800D0FFDF0BB000BD30B595B076 +:103330000C462C2518998DF80050ADF80200B3B159 +:103340001868019058680290ADF80C2010220DF119 +:103350000E0017F079FD09A9684608F01CF900284D +:1033600003D1A17F41F01001A17715B030BD00203D +:103370000190E8E72DE9F0470646008A8AB080B25E +:103380000D468146FEF74EF80446754F3078283FCB +:10339000DFF8CC814FF0000A122873D2DFE800F08A +:1033A00072E9350936777E98A8F3E7E6E5E4DF5B56 +:1033B000DFDFA07F00F00300012806D0002148468F +:1033C0000AF02DFB050003D101E00121F7E7FFDF43 +:1033D00098F85C10090602D5D8F860000BE00321CC +:1033E00005F121000DF08AFFD5F821005D49B0FB01 +:1033F000F1F201FB1200C5F8210070686866B06840 +:10340000A8662078252800D0FFDFECE0A07F00F040 +:103410000300012806D0002148460AF000FB060000 +:1034200003D101E00121F7E7FFDF7078810702D5C2 +:103430002178252904D040F0010070700AB006E719 +:103440000220287096F82000287106F121003136FC +:10345000C5E90206F2E7A07F00F00300012806D0CC +:10346000002148460AF0DBFA040003D101E0012103 +:10347000F7E7FFDF6078C10605D5142028704134D6 +:103480006C60DBE7E2E140F008006070D6E73448AA +:10349000082128380DF032FF032016E02A208DF88D +:1034A000000010220DF10200716817F0CDFC10220F +:1034B0000DF11200B16817F0C7FC294968462C3994 +:1034C00008F069F800B1FFDF042028706F60B5E7ED +:1034D000E07FC00600D5FFDFB0680090B388062209 +:1034E0000321484604F0C1FF0028A7D0FFDFA5E76D +:1034F00004B9FFDF716821B1102204F1230017F035 +:10350000A3FC28212046FDF7C5FFA07F00F00300A3 +:1035100002280ED104F12300002300901A46214610 +:103520004846FFF703FF112807D029212046FDF761 +:10353000B1FF307A84F8200080E7A07F000700D533 +:10354000FFDF14F81E0F40F008002070A4F816A04A +:10355000C4F818A0C4F81CA0617808460AE034E05A +:103560005C02002040420F006CE19AE090E062E0D3 +:1035700009E03FE061F38200410861F3C30060703D +:10358000307AE0705AE7A07F00F00300012806D0EF +:10359000002148460AF043FA040003D101E001216A +:1035A000F7E7FFDF022104F175000DF0A7FE1120FF +:1035B000287004F5DA706860B4F875002882FD4858 +:1035C0006C346C61C5E9028038E7A07F00F003002D +:1035D000012805D0002148460AF021FA18B901E077 +:1035E0000121F8E7FFDF0AB0324621464846BDE830 +:1035F000F0477BE504B9FFDF207821289CD930799A +:10360000012802D002280AD103E0E07F40F0100038 +:10361000E07798F85C1041F0010188F85C103246C0 +:1036200021464846FFF762FD0AB02046BDE8F04754 +:103630002321FDF72FBF327901230321484604F0EF +:10364000B9FD98B1122005F8040B327925F8042B46 +:10365000281DA91E0095CDE901100023032148462D +:1036600004F025FE00288DD0FFDFE7E6A07F00F004 +:103670000300012806D0002148460AF0D0F90400D2 +:1036800003D101E00121F7E7FFDF30792070D5E6B3 +:103690000321484605F085F9002895D113202870AC +:1036A000CCE6A07F00F00300012806D000214846A8 +:1036B0000AF0B5F9050003D101E00121F7E7FFDFCA +:1036C00095F8740000F00300012878D1A07F00F085 +:1036D0000307E07FC0F3400616B1012F04D02BE0B2 +:1036E00095F89000C0072AD0D5F8AC0118B395F82A +:1036F0007320017C62F387010174E27FD5F8AC018D +:1037000062F341010174D5F8AC0166F30001017464 +:10371000AEB1D5F8AC01102204F12301783517F0D1 +:1037200093FB287E40F001002876287820F00100E5 +:1037300005F8780900E016B1022F04D02CE095F8C6 +:103740007800C00726D0D5F8A80118B395F87320E3 +:10375000017C62F387010174E27FD5F8A80162F36E +:1037600041010174D5F8A80166F3000101748EB11E +:10377000D5F8A801102204F12301783517F064FB75 +:10378000287840F0010005F8180B287820F0010097 +:1037900005F89009022F51D05FF0000000EB4000C7 +:1037A00005EBC00090F87800800708D5D5F8B02167 +:1037B00095F86C0005F16D011032FDF7D9FF052079 +:1037C00060F3070815F8740F00F0030060F30F288A +:1037D000287960F31748287F60F31F687548AC3874 +:1037E000027822F00F02921C22F0F00220320270C6 +:1037F000427822F00702D21C4270A0F80290C0F872 +:10380000188004F035F92078252805D0212807D024 +:10381000FFDF2078222803D922212046FDF73AFE37 +:10382000A07F00F0030001280AD0002148460AF0DA +:1038300008F900283FF40EAEFFDFFFE50120ADE7F9 +:103840000121F3E7716881F801A0F7E5FFDFF5E5F5 +:1038500070B5584C0025103C14F85C0F20F0800027 +:10386000207065600BF0D7FC5249A1F1100004F004 +:1038700091F804F82C5C072060724E487C3020617F +:103880005030A0611030E06170BD70B50D46FDF79D +:10389000C9FD040000D1FFDF4FF4DE71284617F0A8 +:1038A0006CFB44485430686104F123002861A07F18 +:1038B00000F00300012809D05FF0020105F59070C7 +:1038C0000BF0AAFC002800D0FFDF70BD0121F5E756 +:1038D0000A46014602F590700BF0BCBC70B5054677 +:1038E00040689AB0017808290DD00B2903D00C2923 +:1038F00036D101218171686886883046FDF792FDD6 +:10390000040035D133E046883046FDF78BFD0400D6 +:1039100000D1FFDF2078212822D0282822D1686812 +:1039200002210C3001F09EF9E0B168680821001D09 +:1039300001F098F9B0B12D208DF80000ADF80260CB +:10394000102204F1230101A817F07EFA09A96846A4 +:1039500007F021FE00B1FFDF29212046FDF79AFD87 +:103960001AB070BD687840F008006870F8E7FFDFB3 +:10397000A07F00F00301022902D120F01000A077FF +:10398000207821280AD06868817909B1807898B1B7 +:10399000A07F00F0030002285BD0FFDFA07F00F0D3 +:1039A00003000228DCD1FDF76CFF0028D8D0FFDF30 +:1039B000D6E700006C020020687840F008006870CC +:1039C000E07FC10720D0800701D5062000E0052058 +:1039D00084F822002078292818D02428DED1314606 +:1039E00006200DF096FF22212046FDF753FDA07F13 +:1039F00000F0030001282AD0002130460AF021F807 +:103A00000028CBD0FFDFC9E70420E1E7A07F00F06A +:103A10000300012806D0002130460AF000F8050016 +:103A200003D101E00121F7E7FFDF25212046FDF763 +:103A300031FD10208DF8500014A905F590700BF0A1 +:103A400000FC0228AAD00028A8D0FFDFA6E70121A9 +:103A5000D3E7687840F0080068709FE72DE9F047E9 +:103A60008CB01D46904689460646DDF850A0FDF70D +:103A7000D9FC040052D0207822284FD323284DD0DF +:103A8000E07FC0064AD4A07F00F00300012806D0E2 +:103A90000021304609F0C3FF070002D00BE00121EE +:103AA000F7E7A07F00F00300012804D10121304690 +:103AB00009F0ACFF074601AB02AA03A93846FFF79D +:103AC00003FC039800B9FFDF4FB1039807F5907727 +:103AD00087612078222806D0242804D007E00399A3 +:103AE0000020886103E025212046FDF7D3FC0398E0 +:103AF0000C2141704662A0F80480C0F80890A0F83C +:103B000006A0C560029901610199416104A90BF009 +:103B1000B8FB022802D0002800D0FFDF0CB0BDE8BF +:103B2000F08730B589B00546FDF77CFC0178222985 +:103B300033D9807F00F00300012806D000212846F9 +:103B400009F06DFF040003D101E00121F7E7FFDF79 +:103B5000227801230321284604F02CFB00281CD0E6 +:103B600012208DF80C00227806A8811F05ABCDE944 +:103B700000310290ADF8102000230321284604F004 +:103B800096FB00B1FFDF03A904F590700BF059FB21 +:103B9000022802D0002800D0FFDF09B030BD10B5E8 +:103BA00086B00446FDF73EFC0178222919D9807FB2 +:103BB00000F00300012806D00021204609F02FFF65 +:103BC000040003D101E00121F7E7FFDF13208DF8A6 +:103BD0000000694604F590700BF033FB002800D01C +:103BE000FFDF06B010BD2DE9F05F05460C4600274B +:103BF0000078904601093E46BB4604F1080A0229B6 +:103C00007ED0072902D00A2909D141E068680178ED +:103C1000082905D00B292BD00C2929D0FFDFC5E1BD +:103C200014271C26002C6CD04088A080FDF7FAFBDE +:103C30005FEA000900D1FFDF99F81700524609F149 +:103C40001801FDF795FD68688089208269684868D9 +:103C5000C4F812008868C4F81600A07E20F00600A0 +:103C600040F00100A07699F81E0040F040014DE0C0 +:103C70001A270A26002CD6D08088A080FDF7D2FB18 +:103C8000050000D1FFDF51462846FFF7EEFA8DE12F +:103C90000CB1288DA080287E0E287CD006DC01285F +:103CA0007AD0022808D0032804D135E0102874D037 +:103CB000112873D0FFDF79E11E270926002CB2D02E +:103CC000A088FDF7AFFB5FEA000900D1FFDF287F86 +:103CD00000F003000128207A1BD020F001002072A0 +:103CE000297F890861F341002072297FC90861F3A7 +:103CF00082002072297F090961F3C300207201E06C +:103D000049E116E199F81E0040F0800189F81E1083 +:103D10004CE140F00100E2E713270D26002CAAD069 +:103D2000A088FDF77FFB8146807F00F0030001281B +:103D300006D00021A08809F072FE050003D101E041 +:103D40000121F7E7FFDF99F81E0000F00302012AC6 +:103D500059D0A86E817801F003010129217A54D04D +:103D600021F00101217283789B0863F341012172E4 +:103D70008378DB0863F38201217283781B0963F384 +:103D8000C3012172037863F306112172437863F350 +:103D9000C711217203E060E0A6E08EE09EE084F8A7 +:103DA00009B0C178A172012A32D04279E17A62F376 +:103DB0000001E1724279520862F34101E1724279F5 +:103DC000920862F38201E1724279D20862F3C30180 +:103DD000E1720279217B62F30001217302795208BA +:103DE00062F3410121730279920862F38201217327 +:103DF0000079C00860F3C301217399F800002328FB +:103E00005AD9262168E0686EA4E741F00101A9E7CC +:103E10000279E17A62F30001E1720279520862F3F9 +:103E20004101E1720279920862F38201E172027942 +:103E3000D20862F3C301E1724279217B62F300018F +:103E400021734279520862F3410121734279920849 +:103E500062F3820121734079CBE718271026002CEA +:103E600067D0A088FDF7DEFA8246807F00F003006D +:103E7000012807D00021A08809F0D1FD5FEA0009E0 +:103E800003D101E00121F6E7FFDFE869A06099F8BE +:103E9000010040F0040189F8011099F80200800740 +:103EA00008D5012020739AF8000023287ED9272105 +:103EB000504663E084F80CB078E015270F26C4B3B1 +:103EC000A088FDF7AFFA814606225146E86907F05F +:103ED000C8FB0120A073AEE048464FE01627092634 +:103EE0003CB3287F207261E0287FFE4902280CD075 +:103EF00019270E26ECB101280DD003281AD004286A +:103F00001BD0052819D0FFDF23E01B270926BCB3EF +:103F10000120207205E001202072607A20F0030069 +:103F2000607211F85C0F4208520062F306000870DC +:103F30000FE02BE00220207207E0697F052801F0E6 +:103F40000F0141F0800121721BD0607A20F0030044 +:103F50006072A088FDF766FA05460078212825D012 +:103F6000232800D0FFDFA87F00F00300012810D035 +:103F70000021A08809F065FD22212846FDF78AFA74 +:103F800014E0607A20F00300401CE1E7A8F800602C +:103F900011E00121EDE70CB16888A080287E03289C +:103FA0002BD004280AD005284BD0FFDFA8F80060EA +:103FB0000CB1278066800020BDE8F09F15270F26F2 +:103FC000002CE3D0A088FDF72DFA807F00F00300DD +:103FD000012806D00021A08809F021FD050003D1A9 +:103FE00001E00121F7E7FFDFD5F821000622514665 +:103FF00007F037FB84F80EB0D8E717270926002C06 +:10400000C4D0A088FDF70EFA8146807F00F003003F +:10401000012806D00021A08809F001FD050003D188 +:1040200001E00121F7E7FFDFA878800701D5022032 +:1040300000E00120207299F800002328B6D927213A +:104040004AE719270E26002CA0D0A088FDF7EAF930 +:104050005FEA000900D1FFDFC4F808B0A4F80CB093 +:1040600084F808B0A07A40F00300A07299F81F10FD +:1040700061F38200A07299F81F1001EA510161F307 +:10408000C300A072687E00F0030001288ED1607A20 +:1040900040F00400607299F81E0000F0030001284F +:1040A00014D0E97E607B61F300006073AA7E217BFF +:1040B00062F300012173EA7E520862F341006073EB +:1040C000A87E400860F3410121736FE7E87E217B01 +:1040D00060F300012173AA7E607B62F300006073CD +:1040E000EA7E520862F341012173A97E490861F317 +:1040F000410060735AE730B504468079012591B0DC +:10410000B5EB901F00D0FFDFFFF72CF84FF6FF70E4 +:10411000099074488DF8015020300190201D0290C4 +:10412000601C0B900AA968460BF0ABF800B1FFDFEA +:104130000B980188A4F801108078E07011B030BDB0 +:1041400010B5684C30B10146102204F1200016F081 +:104150007BFE012084F8300010BD10B50446FFF747 +:1041600001F8604920461022BDE81040203116F0C9 +:104170006BBE70B55B4C06004FF0000514D00DF01F +:104180000BFC08B110250DE00621304607F050FA6F +:10419000411C06D0206614F85C0F40F080002070AF +:1041A00000E00725284670BD14F85C0F20F0800061 +:1041B000F5E72DE9F041804688B00D460027084616 +:1041C0000DF035FCA8B94046FDF72CF9040003D0EA +:1041D0002078222815D104E043F2020008B0BDE89F +:1041E000F08145B9A07F010603D500F00300022845 +:1041F00001D01020F2E7A07FC10601D4010702D54B +:104200000DB10820EAE7374991F85C10C90701D0E1 +:104210001120E3E7E17FC90601D50D20DEE700F0BC +:104220000300022805D125B12846FEF7F1FE07005C +:10423000D4D1A07F00F00300012806D00021404621 +:1042400009F0EDFB060002D00CE00121F7E7A07FAA +:1042500000F0030001280BD00021404609F0D6FBF6 +:10426000060007D0A07F00F00300022804D009E078 +:104270000121F2E70420B1E725B12A463146204664 +:10428000FEF7EAFE07AB1A4669463046FFF71CF810 +:10429000009800B9FFDF00990D20487006F5907076 +:1042A000C1F82480486100200881A07F00F003004D +:1042B00001282BD0F5B302200871301D8861707879 +:1042C00040090877B078C0F340004877287800F0BC +:1042D0000102887F62F301008877E27F62F3820047 +:1042E000887701E05C020020E27F520862F3C3009D +:1042F0008877B27862F304108877A878C87701F1DC +:10430000210228462031FEF7C7FE22E00120087175 +:10431000287800F00102087E62F3010008762A780E +:10432000520862F3820008762A78920862F3C3008A +:10433000087600E009E02A78D20862F304100876D3 +:1043400024212046FDF7A6F80BE003200871052084 +:10435000087625212046FDF79DF8A07F20F08000FB +:10436000A07701A900980AF08CFF022801D000B1C3 +:10437000FFDF384632E72DE9FF4FF94A0D4699B085 +:104380009A4607CA14AB002783E807001998FDF77F +:1043900049F8060006D03078262806D008201DB03F +:1043A000BDE8F08F43F20200F9E7B07F00F00309A7 +:1043B000B9F1010F03D0B9F1020F07D008E03DB900 +:1043C0001B98FEF725FE0028E9D101E01B9878BB79 +:1043D000B07F00F00300012806D00021199809F0F1 +:1043E0001EFB040003D101E00121F7E7FFDF852D6B +:1043F00025D007DCD5B1812D1BD0822D1BD0832D7C +:1044000008D11AE0862D1CD0882D1CD0892D1CD0F7 +:104410008A2D1CD00F2020710F281AD001208DF872 +:104420003400201D0E902079A8B158E10020F2E759 +:104430000FE00120EFE70220EDE70320EBE7052086 +:10444000E9E70620E7E70820E5E70920E3E70A2097 +:10445000E1E70720A3E7B9F1010F17D0D4E919501C +:1044600080460220019001200090A87898F8021060 +:10447000C0F3C000C1F3C00108405FEA000B5DD08B +:1044800050460DF089FA00286CD12DE0D4E9198549 +:104490000120019002200090214630461B9AFEF731 +:1044A000DBFD1B98007800F00101A87861F30100A2 +:1044B000A870F17F61F38200A870F17F490861F371 +:1044C000C300A870A17861F30410A8706078400957 +:1044D0002870A078C0F3400068701B988078E8705E +:1044E000002068712871C0E7DAF80C000DF054FA6A +:1044F000C0BBDAF81C000DF04FFA98BBDAF80C00DC +:10450000A060DAF81C00E06098F80100A17800F0E3 +:10451000010041EA4000A07098F80210C0B2C1F357 +:104520000011891E0840A070002084F82000009926 +:1045300006F1170002290BD001210AE098F80110BA +:10454000A07801F00101FD2242EA41010840E2E7C2 +:10455000002104EB810188610199701C022902D0BD +:10456000012101E028E0002104EB81018861A878A5 +:1045700000F00300012849D198F8020000F0030080 +:10458000012843D1B9F1010F04D12A1D691D1B98DF +:10459000FEF782FD297998F8040001408DF82C106F +:1045A000687998F8052010408DF8300001432DD02F +:1045B00050460DF0F1F908B11020F0E60AF11000B4 +:1045C00004F5D47104F17C020490B9F1020F3CD0DF +:1045D0000090CDE9012100210BAB5A462046FEF7A1 +:1045E000D5FD0028E9D104F5D67104F19402B9F1A2 +:1045F000010F30D004980090CDE9012100210CABCF +:104600005A462046FEF7C2FD0028D6D1A078800782 +:1046100040D4A87898F80210C0F38000C1F380015C +:10462000084337D0297898F8000014AAB9F1010F8F +:1046300017D032F810204B00DA4012F0030718D0E0 +:10464000012F1ED0022F12D11DE0CDF800A0CDE920 +:1046500001210121C0E7CDF800A0CDE90121012110 +:10466000CDE732F811204300DA4002F00307032FB0 +:1046700007D0BBF1000F0DD0012906D0042904D0CA +:1046800008E00227F5E70127F3E7012801D0042815 +:1046900000D10427F07F40F001006BF34100F07778 +:1046A000A07881074FF003000CD5A071BBF1000F7B +:1046B00015D100BF8DF85C0017AA31461998FEF796 +:1046C00034FD0CE00221022F18D0012F18D0042F46 +:1046D00022D00020A071F07F20F00100F07725218A +:1046E0003046FCF7D7FE0DA904F590700AF0A9FD3D +:1046F00010B1022800D0FFDF002050E6A171D9E7F9 +:10470000A1710D2104F1240016F037FC607840F00F +:10471000020060700420CDE70120A071DFE72DE9E1 +:10472000F04387B0914688460446FCF77BFE0700BD +:1047300006D03878272806D0082007B0BDE8F083D7 +:1047400043F20200F9E7B87F00F00300012809D026 +:104750000021204609F063F9040006D104E00000BE +:104760001CB301000121F4E7FFDFA679012E08D078 +:10477000B8F1000F0FD048460DF00EF9B8B1102077 +:10478000DBE7B9F1000F25D1B8F1000F09D0B8F17E +:10479000010F1FD120E0022E05D0032E05D0FFDF30 +:1047A00028E00C2526E0012524E0022522E0B8F1CE +:1047B000020F03D0B8F1010F0AD00BE0032E09D18C +:1047C00000251022494604F1210016F03DFB11E0BE +:1047D000022E01D00720B0E70025102104F12100AE +:1047E00016F0A9FB5FEA090004D0062106F020FFBD +:1047F000C4F821006078252140F00200607038463E +:10480000FCF748FE6078C10713D020F0010060700B +:1048100002208DF8000004F1210002908DF8045070 +:104820006946FF300AF00DFD022804D018B1FFDF01 +:1048300001E084F8205000207FE730B587B00D46B6 +:104840000446FCF7EFFD88B1807F00F003000128EB +:104850000FD00021204609F0E2F804000ED02846CF +:104860000DF09AF838B1102007B030BD43F20200C5 +:10487000FAE70121EEE76078400701D40820F3E76A +:10488000294604F141002022054616F0DDFA607841 +:1048900040F01000607001070FD520F00800607034 +:1048A00014208DF80000694604F5907001950AF017 +:1048B000C8FC022801D000B1FFDF0020D4E770B5AA +:1048C00094B00D460646FCF7ADFD18B101782729D6 +:1048D00044D103E043F2020014B070BD807F00F0C9 +:1048E0000300012806D00021304609F098F80400A2 +:1048F00003D101E00121F7E7FFDFA07902282DD1E4 +:10490000A078C0072AD0002302220321304603F0FA +:1049100051FC28B30D208DF80D0007A80222811F3D +:10492000ADF8142006ABCDE900310C9604F5907477 +:104930000290089400230321304603F0B8FC00B134 +:10494000FFDF04208DF810008DF824500DA903A876 +:104950000AF097FC00B1FFDF0020BDE70820BBE7AD +:104960001120B9E770B5064686B014460D460846D4 +:104970000DF012F818B920460DF032F810B11020E1 +:1049800006B070BDA6F57F40FF380DD03046FCF76D +:1049900049FD30B14378811C22461846FCF7E8FEF9 +:1049A00007E043F20200EBE72046FDF7F2FC0028A7 +:1049B000E6D11021E01D0CF0A1FCE21D294668465D +:1049C000FEF79CFC102204F11700019916F03CFA46 +:1049D0000020D5E72DE9F041044690B01546884601 +:1049E000002708460DF023F818B928460DF01FF8E7 +:1049F00018B1102010B0BDE8F0812046FCF712FD80 +:104A0000060003D03078272818D102E043F20200D4 +:104A1000F0E7B07F00F00300012806D00021204617 +:104A200008F0FDFF040003D101E00121F7E7FFDFFB +:104A30006078400702D5A078800701D40820D9E724 +:104A4000B07F00F00300012818D0D4E919014078A4 +:104A500000B1B5B1487810B1B8F1000F11D0C5B1AF +:104A6000EA1D02A8E168FEF749FC102205F11700D3 +:104A7000039916F0BDF930B104270AE0D4E9191002 +:104A8000E5E70720B6E71022E91D04F1310016F032 +:104A9000DBF9B8F1000F06D0102208F1070104F18C +:104AA000210016F0D1F96078252140F002006070F5 +:104AB0003046FCF7EFFC6078C10715D020F001000C +:104AC000607002208DF8200004F121000A9010305F +:104AD0000B908DF8247008A9EF300AF0B2FB022881 +:104AE00004D018B1FFDF01E084F82070002081E7D6 +:104AF000F8B515460E460746FCF794FC040004D0B2 +:104B00002078222804D00820F8BD43F20200F8BD26 +:104B1000A07F00F00300022802D043F20500F8BD98 +:104B200030460CF039FF18B928460CF035FF08B1B3 +:104B30001020F8BD00953288B31C21463846FEF798 +:104B4000F5FB112814D00028F3D1297C4A08E17F15 +:104B500062F30001E1772A7C62F34101E177297C6D +:104B6000890884F82010A17F21F08001A177F8BD89 +:104B7000A17F0907FBD4D6F80200C4F83600D6F8A6 +:104B80000600C4F83A003088A0861022294604F1B5 +:104B9000230016F059F9287C4108E07F61F3820078 +:104BA000E077297C61F3C300E077287C800884F8F3 +:104BB0002100A07F40F00800A0770020D3E770B567 +:104BC00094B00D4606460BB1072085E6FCF72AFC9B +:104BD000040007D02078222802D3A07F400604D406 +:104BE000082079E643F2020076E6C5B12D208DF863 +:104BF0000000ADF802601022294601A816F024F941 +:104C0000287C4108E07F61F30000E077297C61F3B4 +:104C10004100E077287C800884F8200004E02E2002 +:104C20008DF80000ADF8026009A9684606F0B3FCF3 +:104C3000A17F21F04001A1774EE670B50D46FCF74B +:104C4000F1FB040005D028460CF0CAFE20B110206C +:104C500070BD43F2020070BD29462046FEF705FBF9 +:104C6000002070BD05E000BF10F8012B0AB1002044 +:104C70007047491E89B2F7D20120704770B50D46C2 +:104C8000007804991446042803D0052832D0FFDFA9 +:104C900070BDA88B0E2200EB400002EB4000188094 +:104CA00033200880002CF3D0A88BA081002613E0CD +:104CB000A87F012814D006EBC60005EB400106EBE7 +:104CC000460204EB4202088CD081102022311032BF +:104CD0000AF078FB761CB6B2A089B042E8D870BD65 +:104CE00005EB860106EB460204EB4202088CD081FC +:104CF0000220EBE7A88B102200EBC00002EB400083 +:104D0000188034200880A87F012808D0022806D007 +:104D1000FFDF002CE3D0A88BA081002613E0A07356 +:104D2000F7E7A87F012812D006EBC60005EB40018B +:104D300004EB40000A8C028210221230223116F05D +:104D400083F8761CB6B2A089B042EAD870BD05EBF4 +:104D5000860106EBC602088C04EB42022231108267 +:104D6000022012320AF02EFBEBE72DE9F041057824 +:104D70000E20DDF818C001F1200402F10E074FF0FB +:104D80000008022D06D0032D2DD0062D6AD0FFDF9E +:104D9000BDE8F081CD8B05EB850600EB4600188061 +:104DA0003120ACF80000002AF2D0087F9581801FE6 +:104DB000C6B214E061682088388031F8020BF880B0 +:104DC00031F8020B3881BA1C30460AF0FBFA06B102 +:104DD00018B187F80480A7F8028008340A376D1EDE +:104DE000ADB2E7D2D4E7CD8B05EB850600EB4600EC +:104DF00018803220ACF80000002AC9D0087F9581C5 +:104E0000401FC6B22AE06168228811F8010BFA80BF +:104E10003A79430860F3000263F34102830863F3C5 +:104E20008202C30863F3C302030963F30412430954 +:104E300063F34512830963F386123A71C0097871EE +:104E400031F8020B38813A4630460AF0BBFA18B105 +:104E500087F80280A7F8008008340A376D1EADB2CB +:104E6000D1D295E7087FCD8B801E86B206F108006F +:104E70006843103018803520ACF80000002A87D035 +:104E8000958102F11007D68107EBC5080BE0208859 +:104E90003880C7F8048032464046616815F0D4FF78 +:104EA0000834B04408376D1EADB2F0D270E72DE97A +:104EB000F0471D46089E0C4681462AB1607E00F5EB +:104EC0008070D080E08B108199F800000E274FF0A1 +:104ED00000084FF0100A0C287ED2DFE800F096069A +:104EE000152129313F4E636B6B6B207F914608285B +:104EF00002D0032800D0FFDF2F8030200BE000BF5E +:104F0000A9F80C80BDE8F087207F9146042800D0E6 +:104F1000FFDF2F8031203080B9F1000FF0D1F1E7B1 +:104F2000207F9146042800D0FFDF2F803220F2E757 +:104F3000207F9146022800D0FFDF2F803320EAE750 +:104F4000207F1746022800D0FFDF3420A5F800A0FC +:104F50003080002FD6D0A7F80C80D3E7207F1746EB +:104F6000042800D0FFDF3520A5F800A03080002FF6 +:104F7000C8D04046A7F80C8012E0207F17460528CD +:104F800002D0062800D0FFDF122028803620308093 +:104F9000002FB7D0E08BB881A7F81080B9F80200D5 +:104FA000F881AFE7207F9146072800D0FFDF2F80F0 +:104FB0003720B0E74FF0140018804FF0380017008A +:104FC00030809FD0E08BB881A7F8128099F800005C +:104FD000092807D00A2800E017E009D00B280DD0D7 +:104FE000FFDF8FE7207F0C2800D0FFDF01200AE0E1 +:104FF000207F0D2800D0FFDF042004E0207F0E2852 +:1050000000D0FFDF0520B8737CE7FFDF7AE770B5DB +:105010000C460546FCF706FA20B10078222804D297 +:10502000082070BD43F2020070BD0521284608F03B +:10503000F6FC206008B1002070BD032070BDFFB5F4 +:1050400085B007461720ADF80C00089814460D46A9 +:10505000022628B908A93846FFF7D9FF00283ED113 +:105060005DB10023BDF80C203146384603F0A2F8AC +:10507000B8B308980078A0BB05E02078092822D0B2 +:105080000F282FD0FFDF002004A9CDE90010034630 +:105090000290BDF80C203146384603F008F900288C +:1050A0001DD1089803A9801DC4E901072046049A70 +:1050B00004F007FB60B3072828D2DFE800F01E1CCD +:1050C00027272520220007260023BDF80C20314683 +:1050D000384603F06FF80028D5D143F2040009B038 +:1050E000F0BD08E00023BDF80C203146384603F03F +:1050F00061F80028C7D11120F1E70020EFE7082070 +:10510000EDE743F20300EAE70720E8E70320E6E7DC +:1051100004980090BDF80C3004223146384603F064 +:10512000A4F90028DBD1002DD9D008990D70D6E75D +:1051300010B588B01C46AAB104238DF8003013883E +:10514000ADF80C305288ADF80E208A788DF8122018 +:105150000988ADF8101000236A462146FFF76FFF5B +:1051600008B010BD1020FBE72DE9F041074600789C +:105170000C46122839D2DFE800F0383434141036E7 +:1051800009090909090909090909090904B9FFDF18 +:10519000607840F00800607028E0002CF8D1FFDF54 +:1051A000F6E7B888052186B2304608F038FC054697 +:1051B00004B1FFDF05B9FFDF3146A81D04F07AFA1C +:1051C00002F0EEFA040007D0607840F0080060704A +:1051D000668002F0C3FA0AE013213046FDF702FBB5 +:1051E00016E0FFDF02E0FFDF00E0FFDF84B1607860 +:1051F00000070DD52078582220F00F00C01C20F0A9 +:10520000F00090302070394604F1180015F061FE6E +:105210000020BDE500200870881D04F048BA0A4649 +:105220000146901D04F04CBA70B50546052108F002 +:10523000F6FB040000D1FFDF2946A01DBDE8704049 +:1052400004F038BA2DE9FE4F4FF00009ADF8089090 +:10525000ADF8049047880C4605469346052138462C +:1052600008F0DDFB060000D1FFDF24B1A780A4F821 +:105270000690A4F80890297E04F112003827C91E70 +:105280004FF001084FF0360A00900F2970D2DFE886 +:1052900001F0F9FA6F6108AD6A70812CB6C9E59525 +:1052A00095003078012800D0FFDFA88B0E2101EB9C +:1052B000C001ADF804103021ADF80810002C13D057 +:1052C000A08100200DE004EBC00132790A747288DD +:1052D000CA8105EB8002401CD38B4B82128C8A82E0 +:1052E00080B2A1898142EED8E8E03078012800D070 +:1052F000FFDFE88B0E2101EBC001ADF80410302177 +:10530000ADF80810297F091FC9B20091002CEBD01D +:10531000A08100271AE000BF05EBC70A04EBC7080D +:1053200008F10E02DAF8241000980AF04BF818B1D0 +:1053300088F81090A8F80E90BAF82010A8F812106B +:10534000BAF822107F1CA8F81410BFB2A089B84286 +:10535000E2D8B3E002A8009001AB224629463046CD +:10536000FFF78CFCAAE03078072806D0FFDF04E0C6 +:10537000A3E03078072800D0FFDFE88BADF808A065 +:105380001230ADF80400002C38D0A98BA1817188AF +:10539000E18123E03078082800D0FFDFA88B00F1FE +:1053A0000E01ADF804103721ADF80810002C25D0FF +:1053B000A081AA8B04F10E00296A4CE0E88B123020 +:1053C00080B23921ADF80400ADF80810F4B3A98B10 +:1053D000A181287E102807D00221A173E98B2182A8 +:1053E000EA8B296A009836E00121F6E702A80090CE +:1053F00001AB224629463046FFF7B7FC5EE0307825 +:10540000092800D0FFDF1420ADF80400ADF80870C3 +:105410001CB3A98BA181A4F81290A4F8109084F871 +:105420000E804BE030780A2800D0FFDF288CADF8E2 +:1054300008701430ADF804007CB10421A173A98B6D +:10544000A181E98B2182298C618200E032E02A8CE3 +:1054500004F11400696A15F0F7FC2FE030780B288E +:1054600000D0FFDF1420ADF80400ADF8087004B3DD +:105470000521A173A4F80C90A4F81090A4F8129040 +:105480001CE000E008E002A8009001AB224629469B +:105490003046FFF70CFD11E00D203A21ADF8040075 +:1054A000ADF8081034B1A4F80680A4F8089084F888 +:1054B0000C9003E0ABF8000014E0FFDFBDF804003F +:1054C000ABF8000074B1BDF808002080BDF80400FE +:1054D0006080287E032805D0102803D0112801D031 +:1054E00086F800900020BDE8FE8F2DE9F84356882D +:1054F0000F46804615460521304608F090FA040014 +:1055000000D1FFDFA41D33462A46394640460094A9 +:1055100004F054FABDE8F8832DE9F0438DB00D4650 +:105520001446814607A9FFF772FD002814D14FF6F3 +:10553000FF7601274FF420588CB103208DF800002E +:105540001020ADF8140008A802460690204605A9D0 +:1055500009F057FF78B107200DB0BDE8F0830820AF +:10556000ADF80C508DF812708DF80000ADF80E609B +:10557000ADF810800CE00798A17801712188418076 +:105580008DF81270ADF80C50ADF81080ADF80E60CB +:105590006A4601214846079BFFF751FDDCE708B545 +:1055A00001228DF8022042F60202ADF800200A46E0 +:1055B00002236946FFF7BCFD08BD08B501228DF83E +:1055C000022042F60302ADF800200A460323694692 +:1055D000FFF7AEFD08BD00B587B079B102228DF8A6 +:1055E00000200A88ADF80C204988ADF80E10002381 +:1055F0006A460421FFF723FD07B000BD1020FBE73A +:1056000009B1062394E50720704770B588B00D46B0 +:105610001446064607A9FFF7FAFC00280ED17CB114 +:105620000620ADF80C508DF80000ADF80E40079B39 +:105630006A4607215C803046FFF701FD08B070BD67 +:1056400005208DF80000ADF80C50F0E700B587B0EC +:1056500059B107238DF80030ADF80C2004910023D8 +:105660006A460821FFF7EBFCC6E71020C4E770B5D7 +:10567000002488B0172391B10A78062A20D2DFE8E7 +:1056800002F01F04041503171523DB1E9DB2CB88FF +:105690000BB18E681EB1AB4203D90C20CEE71020AF +:1056A000CCE7042A04D08B8853B901E00620C5E773 +:1056B000012A13D0022A05D0042A1CD0052A2AD098 +:1056C0000720BBE709228DF800204A88ADF80C209E +:1056D000CA88ADF80E208968049123E00C228DF869 +:1056E00000204A88ADF80C20CA88ADF80E208968E1 +:1056F0000924049116E00D228DF800204A88ADF8A7 +:105700000C208A88ADF80E20CA88ADF81020896870 +:105710000A24059106E00E228DF8002049788DF8C4 +:105720000C100B2400236A462146FFF788FC85E70E +:1057300000B587B00F228DF80020ADF80C100023C3 +:105740006A461946FFF77BFC56E700B587B071B192 +:1057500002228DF800200A88ADF80C204988ADF8A7 +:105760000E1000236A460521FFF769FC44E710206C +:1057700042E7000018B1817801293CD101E01020F6 +:105780007047018842F60213C81A4FF4807299429A +:1057900033D01CDC42F60103A1EB030099422CD06C +:1057A0000CDCF9B1B1F5C05F27D06FF4C050081818 +:1057B00023D0A0F57060FF381DD11EE001281CD059 +:1057C00002281AD0FF2818D0904214D115E0904238 +:1057D00013D008DC012810D002280ED0FE280CD0EF +:1057E000FF2808D109E0A0F58070013805D0012814 +:1057F00003D0022801D0002070470F2070470B28EB +:1058000026D008DC1BD2DFE800F01C2025251A2555 +:10581000292325271E0011281CD008DC0C2817D0AE +:105820000D281DD00F2815D0102808D110E082288F +:1058300009D0842810D0852810D0872812D00320C2 +:105840007047002070470520704743F203007047FF +:10585000072070470F2070470420704706207047CC +:105860000C2070474FF45050704707280DD2DFE8E6 +:1058700000F00406040C0C080A00002070471120F8 +:105880007047072070470820704703207047007852 +:1058900010F00F0204D0012A05D0022A0CD110E02A +:1058A000000909D10AE00009012807D0022805D023 +:1058B000032803D0042801D0072070470870002077 +:1058C00070470620704705282AD2DFE800F003075A +:1058D0000F171F00087820F0FF001EE0087820F066 +:1058E0000F00401C20F0F000103016E0087820F087 +:1058F0000F00401C20F0F00020300EE0087820F06F +:105900000F00401C20F0F000303006E0087820F056 +:105910000F00401C20F0F00040300870002070475D +:105920000720704738B50C46050041D06946FFF79F +:10593000AEFF002819D19DF80010607861F30200D5 +:1059400060706946681CFFF7A2FF00280DD19DF822 +:105950000010607861F3C5006070A978C1F341015F +:10596000012903D0022905D0072038BD217821F074 +:10597000200102E0217841F020012170410704D08C +:10598000A978C90861F386106070607810F0380F4C +:1059900007D0A978090961F3C710607010F0380FBB +:1059A00002D16078400603D5207840F04000207096 +:1059B000002038BD70B50446002008801546606898 +:1059C000FFF7B0FF002816D12089A189884211D89D +:1059D00060688078C0070AD0B1F5007F0AD840F22D +:1059E0000120B1FBF0F200FB1210288007E0B1F5B6 +:1059F000FF7F01D90C2070BD01F201212980002018 +:105A000070BD10B50478137864F300031370047844 +:105A1000640864F3410313700478A40864F38203F8 +:105A200013700478E40864F3C30313700478240942 +:105A300064F3041313700478640964F3451313705A +:105A40000078800960F38613137031B10878C107BC +:105A500001D1800701D5012000E0002060F3C713C9 +:105A6000137010BD4278530702D002F0070306E01E +:105A700012F0380F02D0C2F3C20300E001234A78CB +:105A800063F302024A70407810F0380F02D0C0F37E +:105A9000C20005E0430702D000F0070000E001204B +:105AA00060F3C5024A7070472DE9F04792B00D00CF +:105AB000804613D0B8F1000F14D01221284615F0FB +:105AC0003AFA03AAFF21012005F0C3FB0024264671 +:105AD00037464FF420596FF4205A6DE0102012B071 +:105AE000BDE8F0870720FAE79DF8160001280AD1E3 +:105AF000BDF8140048450BD010EB0A000AD001286D +:105B00000CD002280CD0042C0ED0052C0FD10DE0A7 +:105B1000012400E00224BDF8126008E0032406E03E +:105B20000424BDF8127002E0052400E00624BDF84C +:105B30001210414540D12C7486B34FF007090DF186 +:105B400034080EAACDF80090CDE9012810230022D8 +:105B5000FF21304605F019FCF0B9BDF834002A46A3 +:105B6000C0B20EA909F02EFCB0B9AE81B7B108AE33 +:105B7000CDF80090CDE9016813230022FF213846BB +:105B800005F003FC40B9BDF83400F11CC01EC0B2E2 +:105B90002A1D09F017FC10B10320A0E70AE0BDF8A8 +:105BA0002100E881062C05D19DF81600A872BDF8E9 +:105BB00014002881002092E703A805F052FB00287A +:105BC00092D0FFF71CFE8AE72DE9F0438BB00E461A +:105BD000DDE9129805461C461746142103A815F066 +:105BE000CCF901208DF810008DF80C008DF8118093 +:105BF000ADF8147064B1A178C90709D08DF816000A +:105C0000E088ADF81A00A088ADF81800A0680790E9 +:105C100001F0C6FD040025D06580002009A9CDE96A +:105C200000101722034601460290ADF820202846B6 +:105C300002F03DFB002812D108368DE8700008AA5A +:105C4000494603A8099B04F032FE06466078000727 +:105C500001D501F083FD5EB13046FFF706FE0BB0C3 +:105C6000BDE8F08313212846FCF7BCFD0320F6E7CE +:105C700009980090BDF8203004220021284602F047 +:105C8000F4FBECE770B506468AB000200D4605909F +:105C900007240490069003A900940790CDE9010120 +:105CA000024610232946304605F06FFB68B904A967 +:105CB000009108A8CDE90140BDF80C30002229462A +:105CC000304605F071F9002801D0FFF798FD0AB0C1 +:105CD00070BD05F02CB82DE9FC470546002700787B +:105CE0000C46B846B9460C2873D2DFE800F0B80677 +:105CF0000D2FCE5F5F7F96B49AA504B1FFDF288990 +:105D000080B201F0BFFEABE0A888042180B28146DA +:105D100007F085FE064604B1FFDF06B9FFDF4946FE +:105D200006F1080004F02CFA01F03AFD040008D056 +:105D3000607840F008006070A4F8029001F00EFD59 +:105D40008FE013214846FCF74DFD9EE004B9FFDFCC +:105D50006088042107F063FE060000D1FFDFA6F88B +:105D60000090002029791EE005EBC0029268D3B2B2 +:105D70005FEA037C07D5DB0605D505EBC10030F8EB +:105D8000020C308007E0120A52060AD5307105EB8A +:105D9000C000C08870806078022740F00800607002 +:105DA0005EE0401CC0B28142DED859E0E888ADF820 +:105DB000000004B9FFDF9DF80100000604D5287833 +:105DC000062807D005282AD0607840F008006070C7 +:105DD00046E044E06088042107F021FE060000D17F +:105DE000FFDF86F80490A888708018E004B9FFDF10 +:105DF0006088042107F013FE060000D1FFDF06F1E2 +:105E0000080004F0E8FF90F0010F02D1E8790006E5 +:105E100026D560880227F080D6E704B9FFDF022785 +:105E2000D2E704B9FFDF022761880122204601F092 +:105E30006DFE4FF00108C7E7A88986B204B1FFDF05 +:105E4000686800902889ADF8040001226946304650 +:105E500001F077FE04E0002CB6D1FFDFB4E7FFDFEE +:105E60009CB16078000710D5B8F1000F0DD12078F3 +:105E7000582220F00F00001D20F0F000803020702C +:105E8000294604F1180015F024F83846BDE8FC87CF +:105E90003EB50C0008D06B4601AA002105F0E2FADD +:105EA00020B1FFF7ACFC3EBD10203EBD002020809D +:105EB000A0709DF8050002A900F00700FFF703FDA0 +:105EC00050B99DF8080020709DF8050002A9C0F3A4 +:105ED000C200FFF7F8FC08B103203EBD9DF80800A2 +:105EE00060709DF80500C109A07861F30410A070EE +:105EF0009DF80510890961F3C300A0709DF8041096 +:105F0000890601D5022100E0012161F342009DF8DC +:105F1000001061F30000A07000203EBD70B5144673 +:105F200006460D4651EA040005D075B108460BF04F +:105F300075FD78B901E0072070BD2946304605F0AF +:105F4000ECFA10B1BDE8704059E454B120460BF0B2 +:105F500065FD08B1102070BD21463046BDE8704097 +:105F600096E7002070BD2DE9FE4F05460C46007EE9 +:105F70000A31009104F108010027029190460C318A +:105F8000821E3E46BB464FF0010A0191082A7CD290 +:105F9000DFE802F0F7047B32327EBCF86888042127 +:105FA00007F03DFD5FEA000900D1FFDFB9F800000E +:105FB00010B152270726ECE051271026002C7CD088 +:105FC0006888A08084F806A099F80400002205EBF8 +:105FD000C0000099C08BFFF7A1FF00286ED199F88F +:105FE000040005EBC000C08B208199F8040005EB8C +:105FF000C000408CE081E6E0B5F82290062822D16E +:10600000E87F00061FD5512709F1140086B2002C45 +:10601000D5D0A88B00220099FFF780FF002873D10C +:106020006888A0800220A071A88B208184F80EA02F +:10603000288C2082A4F812904A46696ADDF8040090 +:1060400014F002FFBFE0502709F1120086B2002CC5 +:1060500033D0A88B00220299FFF760FF002853D1AC +:106060006888A080A88BE080287E06280ED00220B9 +:106070002073288CE081E87F4A46C0096073A4F849 +:10608000109004F11200696ADAE79BE00120EFE763 +:106090006888042107F0C3FCB5F822A05FEA000974 +:1060A00000D1FFDF09F1080004F095FE90F0010F28 +:1060B00002D1E87F000626D501E076E024E00AF16F +:1060C0001400512786B2002C70D06888A080A88B5D +:1060D00000220099FFF722FF002815D10220A071AD +:1060E000A88B20810420A073288C2082A4F812A001 +:1060F0005246696A019814F0A7FE89F804B0A98B8A +:10610000A9F802105FE00320BDE8FE8F6888FBF766 +:1061100089F982466888042107F081FC8146BAF13A +:10612000000F00D1FFDFB9F1000F00D1FFDFB9F898 +:106130000600A0F57F41FF3902D05127142601E067 +:10614000502712268CB36888A080502F06D00220DA +:10615000A071287F029901F016F934E0287FA11D73 +:1061600001F011F99AF82210CDE9001BB9F80220CC +:10617000688800234946FFF727FD0028C4D122E0A4 +:1061800000E016E0FE49A88BC988814205D154275A +:10619000062654B16888A08015E05327082624B14C +:1061A0006888A080A88BE0800DE0FFE7A8F8006079 +:1061B0000EE055270726002CF8D0A88BA08084F885 +:1061C00006B000E0FFDFA8F800600CB12780668011 +:1061D000002099E7EA4900200870704730B587B081 +:1061E0000C4607F0E5FB0546FF2800D1FFDF002045 +:1061F0002080207160804FF6FF70E080294604F116 +:10620000080003F0AFFF02AA2946012005F021F89B +:106210001AE000BF9DF80B00000715D5BDF80E0071 +:106220002946FFF72FFD9DF80B00FF2340F01000DB +:106230008DF80B00BDF80B00ADF80400BDF80E00A2 +:106240002946019A05F037F902A805F00AF8002856 +:10625000E0D007B030BD0A46014602F1080003F065 +:1062600095BF70B50546042107F0D9FB040000D1A5 +:10627000FFDF294604F10800BDE8704003F080BF4D +:106280002DE9F0418AB00D468046FBF7CBF80600B9 +:1062900006D03078222806D208200AB0BDE8F08166 +:1062A00043F20200F9E70421404607F0B8FB074635 +:1062B0000DB1A88878B101208DF8140002208DF866 +:1062C000180000248DF819403DB1A888ADF82000D1 +:1062D0002868079004E00920DFE7ADF82040079424 +:1062E00001F05EFA050026D0A5F8028004A8CDE9E9 +:1062F000000417220023ADF80C20194640460294F2 +:1063000001F0D5FF0028C8D107F108000095CDE9BC +:10631000018096F8221003AA05A8049B04F0C7FA8E +:1063200004466878000701D501F018FA4CB1204600 +:10633000FFF79BFAB1E713214046FCF753FA03201D +:10634000ABE704980090BDF80C30042200214046D1 +:1063500002F08BF84FF6FF71F9809EE72DE9FF5FA1 +:1063600083460E9E9846914677888A463846FBF7C4 +:1063700059F805460421384607F051FB044605B993 +:10638000FFDF04B9FFDF0834CDE90274CDE90086F0 +:1063900095F822104B465246584603F027FF04B0AA +:1063A000BDE8F09F2DE9F04F99B004464FF000088A +:1063B0007348ADF84C80ADF82480ADF84880A0F863 +:1063C0000480ADF80C80ADF81080ADF81880ADF801 +:1063D0001480007816460D464746012809D0022849 +:1063E00007D0032805D0042803D0082019B0BDE841 +:1063F000F08F20460BF0D0FAD0BB28460BF0CCFA39 +:10640000B0BB60680BF013FB90BB606848B160895B +:106410002189884202D8B1F5007F01D90C20E5E737 +:10642000804608AA04A92846FFF7C4FA0028DDD14F +:1064300068688078C0F34100022808D19DF81100F7 +:1064400010F0380F03D028690BF0E8FA80B903A9DF +:106450002069FFF767FA0028C8D1206950B1607839 +:1064600080079DF80D0000F0380002D5E8B301E088 +:1064700011E0D0BB9DF80C0080060ED59DF80D00F4 +:1064800010F0380F03D060680BF0C8FA18B96068D4 +:106490000BF0CDFA08B11020A8E705A96069FFF755 +:1064A00041FA0028A2D1606940B19DF8150000F0C2 +:1064B000070101293BD110F0380F38D006A9A06997 +:1064C000FFF730FA002891D19DF8140080062ED4F1 +:1064D0009DF8180080062AD4A06950B19DF81900D3 +:1064E00000F00701012922D100E020E010F0380F70 +:1064F0001DD0E06818B10078C8B11C2817D20CAACA +:10650000611C2046FFF77DFA0120B94660F30F2792 +:10651000BA4607468DF8460042F60300ADF844003F +:106520000DF1330215A9286808F06BFF08B10720A8 +:106530005CE79DF8540014A9CDF80090C01CCDE98B +:10654000019100F0FF0B00230BF20122514611A82C +:1065500004F0C7FDE8BBBDF850000B9008492A893C +:106560002869091D0092CDE901016B89BDF8202041 +:106570002868049904F0B5FD01007CD1207801E081 +:1065800058030020C1064FF0020A01D480062BD523 +:10659000ADF81C90606950B905A904A8FFF762FA2C +:1065A0009DF8150020F00700401C8DF815009DF89F +:1065B00014008DF8467040F0C8008DF8140042F6C3 +:1065C0000210ADF8440009A907AA0023CDF800A0E5 +:1065D00000E01CE0CDE9012140F2032211A8059959 +:1065E00004F07FFD010046D1F8484D464FF0070901 +:1065F0008088ADF831000CA9CDE900195B46002276 +:106600000295FF21BDF8500004F0CEFC10B1FFF759 +:10661000F6F8EBE69DF83000000625D52946012066 +:1066200060F30F218DF846704FF42450ADF844000C +:10663000ADF8285062789DF82800002362F300002E +:106640008DF828006278520862F341008DF8280026 +:106650000AAACDF800A0CDE9012540F2032211A835 +:1066600004F03FFD010006D1606850B3206970B9A5 +:1066700003A904A800E07DE0FFF7F4F96078800743 +:1066800005D49DF80D0020F038008DF80D008DF830 +:10669000467042F60110ADF84400208940F2012115 +:1066A000B0FBF1F201FB1202606812ABCDF8008082 +:1066B000CDE90103002311A8039904F012FD0100A4 +:1066C00058D12078C00729D0ADF81C50A06950B926 +:1066D00006A904A8FFF7C6F99DF8190020F00700E5 +:1066E000401C8DF819009DF818008DF8467040F098 +:1066F00040008DF8180042F60310ADF8440013A9CD +:1067000007AACDF800A0CDE90121002340F2032221 +:1067100011A8069904F0E5FC01002BD1E06868B3EC +:106720002946012060F30F218DF8467042F60410CF +:10673000ADF84400E068002302788DF858204078D6 +:106740008DF85900E06816AA4088ADF85A00E06854 +:1067500000798DF85C00E068C088ADF85D00CDF888 +:106760000090CDE901254FF4027211A804F0B9FCA4 +:10677000010003D00B9800F019FE37E6934803217F +:10678000017056B180883080BDF848007080BDF837 +:106790002400B080BDF84C00F080002026E670B5E3 +:1067A00001258AB016460B46012802D0022816D1D0 +:1067B00004E08DF80E504FF4205003E08DF80E5099 +:1067C00042F60100ADF80C0063B10024601C60F3D8 +:1067D0000F2404AA08A9184608F013FE20B10720C8 +:1067E0000AB070BD1020FBE704A99DF8202077486F +:1067F000CDE90021801C02900023214603A802F26B +:10680000012204F06EFC10B1FEF7F9FFE8E76F48D3 +:106810000EB14188318005700020E1E770B594B079 +:10682000044601268DF83E6041F60100ADF83C00BB +:1068300012AA0FA93046FFF7B2FF002848D12078EE +:10684000624CC0074FF0000544D01C2102A814F090 +:1068500094FB9DF808008DF83E6040F020008DF814 +:10686000080042F60520ADF83C000E959DF83A0070 +:10687000119520F00600801C8DF83A009DF8380034 +:106880006A4620F0FF008DF838009DF8390009A90C +:1068900020F0FF008DF839000420ADF82C00ADF891 +:1068A00030000EA80A9011A80D900FA80990ADF81D +:1068B0002E5002A8FFF776FD002809D1BDF8000090 +:1068C000E080BDF804002081401C6081257000201C +:1068D00014B070BDE5802581BDF84800F4E72DE9CE +:1068E000F74F8B46394900269EB00A78012A04D01A +:1068F000022A02D0082021B079E54A88824201D0DC +:106900000620F8E789465A4501D10720F3E701211F +:106910004FF000088DF86610ADF8401042464FF673 +:10692000FF71531C63F30F220492ADF84210ADF8CF +:106930004A10FF2042F6020A8DF86A801AAA8DF8E2 +:106940004800ADF864A0ADF868801192CDF84C8095 +:1069500010A804F0ADFC0024254627460BAA072109 +:1069600010A804F0A8FC78B1822857D184B37DB375 +:10697000ADF85C409DF85600ADF85E508DF80C8087 +:1069800017AC01285ED065E09DF832000FB30128F6 +:1069900053D1BDF8301051451DD116AA07A90720C3 +:1069A0008DE80700BDF82E0010230022FF2104F01F +:1069B000ECFC98BBBDF85800042801D0062847D14C +:1069C000BDF81C10594538D10F2094E7580300201A +:1069D00036E0012831D1BDF83000B0F5205F03D09A +:1069E00042F60101884228D1B9F80210BDF82E0004 +:1069F000814201D1012700E0002704B17DB1584553 +:106A00001BD116AB07AA07218DE80E000446102300 +:106A10000022FF2104F0B9FC00B902E02DE0354668 +:106A20000BE0BDF85800022801D0102810D1C0B2E8 +:106A300015AA07A908F0C6FC50B9BDF82E608DE76D +:106A4000052058E703A915A8221D08F0DAFC08B1B3 +:106A5000032050E79DF80C000023001DC2B22098CF +:106A60008DF80C200092CDE9014019A8049904F09A +:106A700038FB10B9022289F80020FEF7C0FE3AE781 +:106A800010B50B46401E86B084B203AA00211846FA +:106A9000FEF7B7FF04AA072103A88DE8070001232A +:106AA0000022FF21204604F07FFA0446BDF81000C2 +:106AB000012800D0FFDF2046FEF7A1FE06B010BD82 +:106AC000F0B5FC4F044687B038780E46032804D052 +:106AD000042802D0082007B0F0BD04AA03A920466C +:106AE000FEF768FF0500F6D160688078C0F34100CA +:106AF00002280AD19DF80D0010F0380F05D020694A +:106B00000AF08CFF08B11020E5E7208905AA216969 +:106B10008DE807006389BDF810202068039904F010 +:106B2000E0FA10B1FEF76BFED5E716B1BDF8140020 +:106B30003080042038702846CDE738B50C00054673 +:106B400009D000236A46FF2104F08CFC28B100BF65 +:106B5000FEF755FE38BD102038BD69462046FEF7C9 +:106B6000E1FE0028F8D1A078FF2100F001032846BB +:106B7000009A04F0A0FCEBE77FB5144603AA0725B2 +:106B80000292CDE900350A462388FF2104F00CFA71 +:106B9000BDF80C102180FEF732FE04B070BD2DE967 +:106BA000F04192B04FF000050C000746ADF81050D0 +:106BB00019D0E06828B1A068A8B10188ADF810101C +:106BC00005803846FAF72EFC88B1007822286AD36F +:106BD000384606F0EDFE80460421384606F01FFFD9 +:106BE000060008D106E0102012B0BDE8F08143F2A3 +:106BF0000200F9E7FFDFA078012803D0022801D0C6 +:106C00000720F1E7208838B1401C80B206AA41462F +:106C100004F01FFB38BB02E043F20300E4E706A8E0 +:106C200004F01FFB9DF822204FF45051012A09D196 +:106C3000BDF82020A2F52453023B03D1822801D0C5 +:106C400088B901E00846CFE7E06898B1072204A9B7 +:106C5000CDE900020291A2882088BDF81030FF2102 +:106C600004F0A2F910B1FEF7CAFDBDE7A168BDF8B6 +:106C7000100008809DF81B00C00602D543F20140B9 +:106C8000B2E70A9818B1BDF82400022801D0032009 +:106C9000AAE717220A98ADF80C20A17800780129FC +:106CA00003D0800710D408209EE7C007FBD0002344 +:106CB0000721384601F07EFA18B14FF0070802208C +:106CC00005E043F204008FE74FF0010803208DF840 +:106CD00030002088ADF834000BA8CDE90005002372 +:106CE0000295BDF80C204146384601F0E0FA002834 +:106CF00087D1CDE900570836029603AA07210CA8D0 +:106D00000B9B03F0D4FD10B1FEF7AFFD6CE70B98C1 +:106D10000090BDF80C3004224146384601F0A5FB36 +:106D200062E770B5064615460C460846FEF722FD9A +:106D3000002805D12A4621463046BDE870402EE5A0 +:106D400070BDCCE570B51E4614460D0009D044B1A7 +:106D5000616831B138B157494988814203D0072071 +:106D600070BD102070BD2068FEF704FD0028F9D129 +:106D7000324621462846BDE87040FFF713BB70B588 +:106D800015460C0006D038B14A498988814203D0A3 +:106D9000072070BD102070BD2068FEF7EBFC0028B6 +:106DA000F9D129462046BDE8704089E670B5054610 +:106DB00086B00E46144610460AF012FEF0BB60681C +:106DC0000AF035FED0BBA5F57F40FF3803D028463A +:106DD000FAF728FBA0B1284606F0EAFD0546304642 +:106DE0006946FEF761FE00280CD19DF810100F20B7 +:106DF000082936D2DFE801F008060606060A0A0866 +:106E000043F2020006B070BD0320FBE79DF80210BC +:106E1000012908D1BDF80010B1F5C05FF2D06FF4C0 +:106E2000C052D142EED09DF80610012905D1BDF81F +:106E30000410A1F528510529E4D900E022E09DF8CD +:106E40000A1001290ED1BDF80810B1F5245FD9D080 +:106E5000A1F524510239D5D00129D3D0022901D17D +:106E6000D0E7FFDF606878B9002305AA29463046DD +:106E700004F0F8FA10B1FEF7C2FCC3E79DF8140065 +:106E8000800601D41020BDE7618822463046636841 +:106E9000FFF772FEB6E72DE9F043074685B0894655 +:106EA000144610460AF09CFD30B1102005B0BDE834 +:106EB000F083000058030020384606F079FD4FF6B5 +:106EC000FF760546B74201D0FF2D0AD001460023C8 +:106ED00004AA484604F0C6FA30B100BFFEF78FFCA2 +:106EE000E4E743F20200E1E79DF81000C00602D596 +:106EF00043F20140DAE74FF0070803A90027CDF875 +:106F00000080CDE90171628833462946484604F085 +:106F10003CFA060012D160680AF062FD58B9606858 +:106F2000CDF80080CDE901072388628829464846CC +:106F300004F02BFA0646BDF80C0020803046CDE761 +:106F400039B1FD4B0A881B899A4202D843F20300EB +:106F5000704724E610B586B0F74C0423ADF8143022 +:106F6000E3883BB124898C4201D2914204D943F297 +:106F70000300A3E50620A1E5ADF810100021009163 +:106F80000191ADF8003002218DF8021005A902919F +:106F900004A90391ADF812206946FFF700FE8DE5C4 +:106FA0002DE9FC4781460F4608460AF0F5FCD0BBA8 +:106FB0004846FAF737FA5FEA000811D098F800005F +:106FC000222832D3002317221946484601F0F2F84E +:106FD00050B10421484606F022FD060007D105E025 +:106FE00043F20200BDE8FC871120FBE7FFDF06F15A +:106FF000080003F0E1F805463878012803D002289C +:1070000004D00720EEE7A8070FD502E015F0340FF3 +:107010000BD0B8793C1DC00709D0E08838B1A06812 +:107020000AF0BAFC18B11020DCE70820DAE73A7859 +:107030002088002128B3A0F201130721112B18D2B8 +:107040000CD2DFE803F00B090D0B1D0B121D100B0A +:107050000B1D1D1D1D0B1D00022A11D10846C1E785 +:10706000012AFBD00CE0EA0600E0AA06002AF5DAC5 +:1070700006E0A0F5C0721F2A02D97D3A022AEDD897 +:10708000C1B298F82200CDE900017288234631464A +:107090004846FEF799FDA5E72DE9FF4F89B01E464A +:1070A00015460C464FF000080F460998FAF7BAF952 +:1070B00030B10078222806D208200DB0BDE8F08F4C +:1070C00043F20200F9E7B00801D00720F5E7032EEC +:1070D00000D10026099806F06BFC83464FF6FF7A34 +:1070E000CCB1022D6AD320460AF0A1FC30B904EBE2 +:1070F0000509A9F101000AF09AFC08B11020DCE7AB +:10710000AD1EAAB22146504604F0BCFA39F8021C62 +:10711000884253D1ADB28848B10702D50189491CD4 +:1071200000E001211FFA81F9F10701D0068900E092 +:10713000564603AA5946484604F08BF84FF0070A12 +:107140000BE07888102839D808F1040108441FFAA8 +:1071500080F8A84532D804EB08078FB33988494531 +:10716000EFD34DE09DF80F100A0749D54CB304EB5F +:10717000080908F10402B9F8023097B2102B1DD8A3 +:10718000DA19AA421AD8B9F80020904216D1C806D6 +:1071900018D5E119CDE9001A08AA0292B9F8000041 +:1071A0000022594603F000FF10B1FEF728FB84E7E8 +:1071B000B9F80200BDF82010884203D00B207CE70C +:1071C0001EE005E0B9F8020038441FFA80F806E036 +:1071D000C90604D55946FEF755FD00288FD19DF804 +:1071E0000F00FF2320F010008DF80F00BDF80F00F6 +:1071F000ADF80000BDF812005946009A04F05BF9A2 +:1072000003A804F02EF818B9BDF81200B042A9D9AD +:107210000421099806F003FC040000D1FFDF228856 +:107220005AB10025CDE900A52B4621460998FEF765 +:10723000CBFC0028BBD125803FE700203DE72DE9AE +:10724000F04F89B01E4617000D464FF000041BD0CA +:10725000B10802D0072009B030E7032E00D1002684 +:1072600006F0A6FB8046FF2805D07DB128460AF02F +:10727000D5FB48B902E043F20200ECE73988681E0A +:1072800008440AF0CBFB08B11020E4E72A49B00714 +:1072900001D5488900E00120F2074FF6FF7902D0BE +:1072A0004989491E00E049468EB204AA414603F0CE +:1072B000D0FF4FF0070A0DF10C0B33E09DF81310CF +:1072C00009072FD50023CDE900A3CDF808B04B4620 +:1072D0000022414604F059F8E8B9F5B1BDF80C10A8 +:1072E0003A8821442819091D8A4231D3BDF8162055 +:1072F00020F8022BBDF80C2020F8022BCDE900A0CD +:10730000CDF808B0BDF81600BDF80C30002241469B +:1073100004F03BF808B103209DE7BDF80C002044C1 +:10732000001D84B204A803F09CFF38B1822809D064 +:10733000FEF765FA8FE7000058030020BDF816003D +:10734000B042BBD934B175B13988A01C814203D297 +:107350000C2080E705207EE722462946484604F0B7 +:1073600091F929190880A41C3C80002073E710B50E +:1073700004460AF035FB08B1102010BD11484089C1 +:107380002080002010BD70B50C4605460E21204619 +:1073900013F0D1FD002020802DB1012D01D0FFDFA1 +:1073A00070BD062000E00520A07170BD10B50C4630 +:1073B00003F01EFF00B1FFDF2046BDE81040FEF7DE +:1073C0001EBA0000580300204FF0E0224FF40041A5 +:1073D0000020C2F8801120490870204990020860FE +:1073E000704730B51C4D04462878A04218BF002CC9 +:1073F00002D0002818BFFFDF2878A04208BF30BDA8 +:107400002C701749154A0020ECB1164DDFF858C012 +:10741000131F012C0DD0022C1CBFFFDF30BD0860F4 +:1074200003200860CCF800504FF400001060186092 +:1074300030BD086002200860CCF800504FF040706A +:107440001060186030BD086008604FF06070106018 +:1074500030BD00B5FFDF00BD1600002008F501407B +:1074600000F500406403002014F5004010B5044608 +:10747000007894B0022805D0012803D043F205001B +:1074800014B010BDA07828B1032803D8607808B1E3 +:10749000032801D90720F3E73F208DF8000020786A +:1074A000022801D0012000E000208DF80200607861 +:1074B00000F095FDC01D8DF80300A078012800D1D3 +:1074C000022000F08CFD8DF80400607800F087FD4C +:1074D0008DF80500A07800F082FD8DF80600207878 +:1074E000012804D19DF80300401C8DF8030009A970 +:1074F000684604F050F800B1FFDF0020C0E72DE936 +:10750000FF4F8DB0FA49DDE91AB90600D1E9020151 +:107510000396CDE90901507A117A9A460844154636 +:10752000C7B20DD00024F01D20F00700B04200D0FB +:10753000FFDF28880399401C1FFA80F814B107E088 +:107540000124F0E708F0FF0007F0E2FE00B1FFDFE2 +:1075500003993A4601EB0810C01C20F00301D5F84E +:10756000108003913CB9002008701FFA88F003F0E6 +:10757000E2FC00B1FFDF0399234601EB0800039012 +:10758000A87A297A3A460844C1B203A800F071FDEE +:107590000398C01C20F003000390697A00912B7AB5 +:1075A000AA7A04B1002001A906F015F900B1FFDFA5 +:1075B000BDF804100398CDE900B90844C01C20F0C0 +:1075C00003001C99CDE902103A4604B1002053464D +:1075D00005A906F08BFA00B1FFDFBDF8141003987F +:1075E0000844C01D20F007000E99821B03900A601A +:1075F000002C35D1C04ABF491160111D401E0860E2 +:1076000001232C220BA9BD4806F066F800F0F1FC1E +:1076100000211E22084602F043F8FAF72DFE00F082 +:107620008FFEFEF7D7FD09AB00220521B4A0FBF7C2 +:10763000EAFA00B1FFDF05F10C00FFF7EFF800B147 +:10764000FFDF4FF47F71B04813F097FCAE48012183 +:1076500080F8F913022180F8FA13062180F8FB1351 +:1076600011B0BDE8F08F10B5A74CA078092800D361 +:10767000FFDF2078C0EBC00004EB001010F8041FFF +:1076800021F0FF010170417821F00701C91C21F0B0 +:10769000180141700121E17010BD2DE9F04105464E +:1076A0000C4600270078052190463E46B1EB101F9E +:1076B00000D0FFDF287E58B1012810D0FFDF00BFC7 +:1076C000A8F800600CB1278066800020BDE8F0813A +:1076D000022709267CB1A88BA080A87F09E0032798 +:1076E000142644B16888A080286AE060A88C2082B3 +:1076F000287F2072E4E7A8F80060E6E700B501788B +:1077000095B001F001018DF80210417801F00101FE +:107710008DF803100178C1F340018DF80410417811 +:10772000C1F340018DF80510017889088DF8061025 +:10773000417889088DF8071081788DF80810C17894 +:107740008DF8091000798DF80A003E208DF80000B0 +:1077500009A9684603F01FFF15B000BD70B56A4C5B +:10776000E07800281BD020780025C0EBC00004EB97 +:107770000010407900F00700011991F8F803401E4D +:1077800081F8F8032078401CC0B22070092800D18D +:107790002570A078401CA07009F09FFCE57070BDBA +:1077A000594890F8FB03002800D05CE770472DE9AA +:1077B000F043554D9BB00026D5F8F40368B1FFF7B0 +:1077C000EFFF002875D07022D5F8F41313F081FB79 +:1077D000FFF7C4FFC5F8F463EEE795F8F903002856 +:1077E00067D0FFF740FF0446444805F0A6FF6060FD +:1077F00000B9FFDF606803F019FF88B12046FAF78F +:10780000B6F86078010706D520F00700401C6070CC +:10781000FFF7A4FFD0E73948616805F097FFCBE791 +:107820003648616805F092FF01A800F05BFC002873 +:107830006CD10321BDF8040006F0F1F88046BDF8D4 +:10784000040006F052FA0746B8F1000F00D1FFDF3E +:10785000D8F8040010B10078FF2857D0FFF703FFD5 +:1078600004463846211D05F0A0FE00B9FFDFD4F81C +:10787000049089F80060BDF804006080204600F0A4 +:1078800046FE384605F0BDFE00B9FFDF3B208DF80F +:107890001000BDF80400ADF8120004A805F040FB8C +:1078A0000EA804F02CF96078010703D4C00607D4B1 +:1078B00009E02BE020F00700801C6070FFF74EFF0E +:1078C000C8F8049078E7D8F8040038B10178491C6A +:1078D00011F0FF0101709DD1FFDF6DE7002211461D +:1078E000384600F07AFB002894D1FFDF64E70000FF +:1078F00028B301000000002000060240B407002069 +:107900006E52463578000000B80300201BB0BDE879 +:10791000F08310B5FC4CA0600868E060AFF2711015 +:1079200001F021FE607010BDF7490020087070471B +:1079300030B505464FF080500C46D0F8A41095B0F5 +:10794000491C05D1D0F8A810C9430904090C08D076 +:1079500050F8A01F01F00101297041682160806882 +:107960000EE02B208DF8000009A9684603F013FEF5 +:1079700000B1FFDF012028700A982060BDF82C00BC +:10798000A0802878002803D0607940F0C0006071A2 +:1079900015B030BDF0B54FF080540746D4F88000E4 +:1079A00095B00D462B26401C0BD1D4F88400401C0A +:1079B00007D1D4F88800401C03D1D4F88C00401CB7 +:1079C0000BD0D4F880003860D4F884007860D4F804 +:1079D0008800B860D4F88C0016E08DF82C606946F9 +:1079E0000BA803F0D8FD00B1FFDF019838600298C2 +:1079F00078608DF82C6069460BA803F0CCFD00B1CF +:107A0000FFDF0198B8600298F860D4F89000401C3D +:107A10000BD1D4F89400401C07D1D4F89800401C36 +:107A200003D1D4F89C00401C08D054F8900F286073 +:107A300060686860A068A860E06816E08DF8006083 +:107A400009A9684603F0A7FD00B1FFDF0A98286086 +:107A50000B9868608DF8006009A9684603F09BFDEB +:107A600000B1FFDF0A98A8600B98E86015B0F0BD80 +:107A700030B5A64C0546D4F8F40300B1FFDFC4F8D6 +:107A8000F45330BD3EB50546032105F0C8FF04465A +:107A9000284606F02AF9054604B9FFDF606818B1E8 +:107AA0000078FF2800D1FFDF01AA6946284600F0D0 +:107AB00094FA60B9FFDF0AE0002202A9284600F02C +:107AC0008CFA00B9FFDF9DF8080000B1FFDF9DF8D8 +:107AD0000000411E8DF80010EED2606801998842C6 +:107AE00001D100206060894C94F8FA03022800D389 +:107AF000FFDF94F8FA03401CC0B284F8FA030128AF +:107B000003D18148407801F04DFD3EBD70B504467B +:107B1000A1F57F4016460D46FF3800D1FFDF012E4C +:107B200001D0FFDF70BD207820F00F00401D20F055 +:107B3000F0005030207000202076A5830120A0772F +:107B400070BD70B515460C460646FFF729FE90B18C +:107B5000017821F00F01491D21F0F0015031017031 +:107B600046800121017621680162A1888184057720 +:107B7000BDE87040F2E53046BDE870401321FAF7E9 +:107B800031BE70B505460C46084609F029FF08B11C +:107B9000102070BD2846F9F745FC28B1284600F0B2 +:107BA000F3FE2070002070BD43F2020070BD2DE98D +:107BB000F04F87B00546002005905348894601786C +:107BC00011B1082007B04CE54F48514941602846A3 +:107BD00009F006FF002868D1484609F001FF002897 +:107BE00063D16F7A2B7AF818FF2870D82888FE287E +:107BF0006DD800B90A202880296909B94FF4B0610D +:107C000029616A68B2B15478907804EB4404204446 +:107C10001478167904EB440400EB44005479D278CC +:107C200004EB440406EB4606344402EB420204EB48 +:107C3000420406E007EB470003EB430200EB42047B +:107C40002046C7EBC7021044C3EBC30210441844DC +:107C500086B206EBC60000EB400A04EBC40000EB62 +:107C600040000090D82901D20920ABE7A87AB84299 +:107C70002DD84FF01208082F0DD8012B0BD807F084 +:107C8000B2FC074609F0E8F93A1A297A687A521ED6 +:107C90000B189A4201DA404694E76F68834688469B +:107CA000BFB1384609F0C3FE08B110208AE7B978A1 +:107CB0007878014438780A180BEB0800904206D116 +:107CC00079793A791144FA781144884201D0072031 +:107CD00078E700981FFA8AF387B20097CDE901642C +:107CE0002A4603A90020FFF70AFCDFF81C8003994D +:107CF000D9F80020D8F80400014491420AD90420A0 +:107D0000C9F800105EE7000018000020B80300204A +:107D1000881200200097CDE901641FFA8AF32A46F1 +:107D200004A9FFF7ECFBDDE90301884200D0FFDF87 +:107D30000498D8F804100844C8F80400C9F80000F2 +:107D4000FF49012088F80000087005983AE72DE9FE +:107D5000F04707460C46084609F042FE40B938464F +:107D600009F05CFE20B9F81C20F00300B84202D0F4 +:107D70001020BDE8F087F3484FF00008817899B1F2 +:107D800041788246C1EBC10100EB0115B4F80090C7 +:107D900015F8040F234600F00F000022294600F0DA +:107DA000F0F9060004D013E0A4F800800520E0E715 +:107DB00097B12188494501D90C260DE02878234642 +:107DC00000F00F003A46294600F0DBF9060005D026 +:107DD0000C2E01D0A4F800803046CAE79AF80100C2 +:107DE0005446401CC0B28AF80100092801D184F829 +:107DF0000180A078401EA070687800F0070101297A +:107E00000BD0022903D0032918D0FFDFE4E7C00616 +:107E1000E2D46888FFF736FEDEE7CB48696805F0F4 +:107E200095FC94F8F903401CC0B284F8F9030128CA +:107E3000D2D1C648407801F0B5FBCDE794F8FB03FA +:107E4000401C8AF8FB03C7E770B50D46044609F0ED +:107E5000A3FD18B9284609F0C3FD08B1102070BD74 +:107E600029462046BDE8704007F089BA70B504463F +:107E700015460E46084609F08FFD18B9284609F048 +:107E8000AFFD08B1102070BD022C03D0102C01D022 +:107E9000092070BD2A463146204607F093FA002893 +:107EA000F7D0052070BD70B514460D46064609F0A2 +:107EB00073FD38B9284609F093FD18B9204609F03A +:107EC000ADFD08B1102070BD22462946304607F0AE +:107ED00098FA0028F7D0072070BD10B594B004467A +:107EE00009F07EFD10B1102014B010BD0F208DF8E8 +:107EF000000009A9684603F04EFB0028F4D19DF864 +:107F00002C002070BDF82E006080BDF83000A080ED +:107F10000020E9E770B505460C46084609F07EFDED +:107F200020B93CB1206809F05BFD08B1102070BD9C +:107F3000A08828B121462846BDE87040FEF7A0B9C8 +:107F4000092070BD70B504460D46084609F024FDB1 +:107F500030B9601E1E2814D8284609F01DFD08B14E +:107F6000102070BD022C01D9072070BD04B9FFDFBD +:107F7000774800EB840050F8041C2846BDE87040A8 +:107F80000847A4F120001F28EED829462046BDE866 +:107F90007040FAF7BAB870B504460D46084609F0C5 +:107FA0001FFD30B9601E1E280DD8284609F0F4FCCC +:107FB00008B1102070BD012C01D0022C01D1062087 +:107FC00070BD072070BDA4F120001F28F9D82946F4 +:107FD0002046BDE87040FAF707B905F089B90328D3 +:107FE00003D0022803D001207047062070470320E9 +:107FF000704710B594B003F0BFFA544841788068D8 +:1080000003F0B0FC514801240C300178012916D14D +:1080100030218DF80010C0788DF8020010B10128D1 +:1080200003D005E08DF8024002E000208DF8020048 +:10803000684604F075FF10B109A803F060FD022046 +:108040008DF824008DF825008DF8260009A8FFF78B +:108050000DFA00B1FFDF8DF8244003208DF82500D4 +:108060008DF8260009A8FFF701FA002800D0FFDFED +:108070003AE72DE9F0410646022012B101EB420039 +:10808000401DC7B23068C01C20F0030232601BBB29 +:108090002C483B460A21283809F06FFB002408E0F1 +:1080A0000A2C11D2DFE804F005070509090B0B05BE +:1080B0000505284804E0284802E0284800E0284850 +:1080C00009F07AFB054600E0FFDFA54200D0FFDFA4 +:1080D000641CE4B20A2CE3D3306800EB0710306074 +:1080E000BDE8F0812DE9F04395B081463A208DF846 +:1080F0002C0069460BA803F04EFA00B1FFDF43F2F3 +:10810000040600246D46DFF83C8032E02F19B87D6C +:10811000C10706D0400704D405EB4400C08800F036 +:1081200024FC98F8FA0310B3B87D80071FD505EB3F +:108130004400C08800F0B1F9C8B105EB440011E07B +:1081400008000020B8030020B40700201800002019 +:1081500028B30100391F0000B3830000E12F0000A5 +:10816000C9F00000C188A9F80010002605E0641CD1 +:10817000E4B29DF80400A042C8D815B03046BDE86E +:10818000F0832DE9F041044600201880601E1D4652 +:1081900016460F46052800D3FFDF05482A4600EBA8 +:1081A0008400314650F8043C3846BDE8F041184799 +:1081B00038B301002DE9F0478A4698461546064631 +:1081C000032105F02CFC0446304605F0A0FD0C35DB +:1081D000AFB2002581462E4604B9FFDFB9F1000F8A +:1081E00000D1FFDF04EB8A000189B94200D30125E9 +:1081F000218CB94202D2BAF1060F00D3012638EA27 +:10820000050104D0817A41F0020181720BE038EA65 +:10821000060108D0817A41F00401817214F8220F1E +:1082200040F00400207005EA0600BDE8F0872DE963 +:10823000F0478246DDE90854174605F10C009946DF +:108240000E461FFA80F800232A4639465046FFF7AB +:10825000B1FF60B1B07800061BD424F8045C24F8A8 +:10826000029C504605F053FD040008D106E0072F9C +:1082700001D01120D9E743F20400D6E7FFDF2D1D1E +:108280002046A9B204F037FF00B9FFDF504603F0E3 +:10829000D5FA06EB8700062F0289A2EB08010181BF +:1082A00003D2318CA1EB080030840020BDE72DE91A +:1082B000F04385B01E46DDE90D5491460F46DDF8CA +:1082C000308005F024FD60B309F10402694692B2E2 +:1082D00004F0ABFE50B300980770BDF80800042806 +:1082E00000D2FFDF002701983A46394607808770A1 +:1082F000019803F065FB1EB1BDF80800001F308037 +:10830000B8F1000F03D00198C01DC8F8000015B1E6 +:10831000BDF8100028808CB1288870B103982060C7 +:108320000CE043F2020005B0BDE8F083072F01D056 +:108330001120F8E743F20400F5E727600020F2E798 +:108340000020FF49024600BF21F81020401C0828E9 +:10835000FAD3704770B50C46897821F0FF01A170FF +:10836000217821F00F0121700121617000216160ED +:1083700005F0CDFC050000D1FFDF284604F053FED8 +:10838000F53820852046BDE8704000F0A4BB70B5EC +:108390000D46032105F043FB040000D1FFDFA07868 +:1083A00065F30600A07070BD70470146012009F01A +:1083B000B0BA3EB58DB20321284605F030FB04006B +:1083C00000D1FFDF2078002220F00F002070022073 +:1083D0008DF800004FF6FF70ADF80200ADF8040014 +:1083E00069462846F9F72DFE3EBD2DE9F0470546C2 +:1083F0000C4600784FF00009012192464F46B1EB40 +:10840000101F00D0FFDF287E032809D0FFDF00BF48 +:10841000AAF8007014B1A4F800906780002004E767 +:10842000AE8B4FF0700906F10A0087B2D4B16888AC +:10843000A080688B2081E680A889A968001F80B28F +:108440008046024604F10A00C91D12F0FDFC4645B3 +:10845000DED904EB0800A6EB08020A30296912F005 +:10846000F3FCD5E7AAF80070D8E72DE9FC410F46E8 +:108470001C46164680460321089D05F0D0FA0100EF +:1084800008D033463A464046CDE90045FFF7CFFED7 +:10849000BDE8FC8143F20200FAE770B50546A0F59D +:1084A0007F4086B0FF3811D0284605F01EFC04003E +:1084B00000D1FFDF2046694605F077F800B9FFDFFD +:1084C000019CB4F80500E41C052802D0012006B088 +:1084D00070BD2E460321284605F0A1FA050000D103 +:1084E000FFDF2079122807D120880C2804D1A87832 +:1084F00000F07F00022806D0002306220421304627 +:10850000FFF758FEE3E7002306220521F7E72DE9F0 +:10851000F04F84688389818A34F8032F0B4465887F +:108520001B1F87B0934222D14FF0010B4FF0000880 +:10853000042D1FD0052D78D0062D6FD0402D16D3D9 +:1085400004461646284600F0BAFA08280FD02078CC +:1085500020F00F00401C20F0F000103020700320AD +:1085600020766583A683607840F00800607007B0CD +:10857000BDE8F08F04F10409164604460246494658 +:108580003046FCF7B2FFC0B20828F0D1ADF80C803D +:10859000CDF8108047466088032105F040FA0500B9 +:1085A00000D1FFDF67482989008881420DD304A8E4 +:1085B000CDE900071722ADF80C2002970023608850 +:1085C0001946FFF774FE00B1FFDF009403AA494685 +:1085D0003046049BFDF7C2FEC0B205281AD2DFE880 +:1085E00000F0041903150300C1E7BDF80C000028D2 +:1085F000BDD004990423CDE90001608800222946FA +:10860000FFF715FE0028B2D0FFDFB0E7607840F03A +:108610001000ABE7FFDFAAE707E0FFE7009103697F +:108620004088211DFBF71AFAA1E707461646408845 +:10863000032105F0F4F9050000D1FFDF8DF80C806F +:10864000A878C146400600D1FFDF042E8FD32179E0 +:1086500041F30000401C06D16A7863799A4286D1C2 +:108660002A78120783D04FF00208142939DA4FF61E +:10867000FF7A012933D0122902D0132931D11CE00D +:108680000C2E2ED1A97801F07F01012929D028785C +:1086900020F00F00401C2870607968708DF80CB0D5 +:1086A0002089ADF80E006089ADF81000A089ADF802 +:1086B0001200E089ADF8140016E0062E11D12878DA +:1086C00020F00F0028707988012009F022F98DF838 +:1086D0000C80ADF80EA02089ADF8100004E0062E45 +:1086E00008D09DF80C10A9B178883A4603A9F9F78B +:1086F000A8FC3CE7287820F00F002870798801203A +:1087000009F007F98DF80C802089ADF80E00ADF85E +:1087100010A0E9E7002887D07E8806A8CDE90009E7 +:108720002F464D460023062204213046CDF80890FE +:10873000FFF7BDFD00B1FFDF069880F800B003E051 +:10874000E407002050B3010061794170A0F8028075 +:1087500085800621CDE900100523042239463046E4 +:10876000FFF765FD0028C4D0FFDF00E77FB50D46A9 +:108770000646032105F053F904003DD0207800F0AF +:108780000F0001283BD0002003A9CDE900100346CB +:1087900002900C2205213046FFF789FD002829D1DF +:1087A000039812210523017061781A46891C4170D3 +:1087B00008214180298881806988C180A988018138 +:1087C000E98841810C21CDE9001021463046FFF7B0 +:1087D0002EFD00B1FFDFF02300223146012008F01A +:1087E000FBFF207820F00F00401C20706078801C78 +:1087F0006070002004B070BD43F20200FAE711205F +:10880000F8E77FB50D460646032105F008F9040098 +:1088100006D0207800F00F00012804D00820E9E7F6 +:1088200043F20200E6E7002003A9CDE90010034669 +:108830000290062205213046FFF739FD0028D9D1E4 +:108840000398132105230170617841700221418052 +:1088500085800621CDE900101A4621463046FFF7F3 +:10886000E6FC00B1FFDF207820F00F002070002030 +:10887000C0E72DE9F84F0E468146032105F0CFF8F9 +:108880000546484605F043FA80464FF0000B05B90F +:10889000FFDFB8F1000F59D1FFDF57E040466946CE +:1088A000002204F025FD9DF800408246082C00D3EC +:1088B000FFDF05EB84070AF108003989062C014423 +:1088C000398102D2298C08442884072C03D10BF16A +:1088D000010000F0FF0BB87AC10710D0072C03D0BD +:1088E000874A32F8141000E0298D3A898A4206D36B +:1088F00020F00100B8724846032C2DD0FFDFB87A73 +:10890000810706D520F00200B8724846032C26D015 +:10891000FFDF062C1AD800BF95F82200410715D5B5 +:1089200020F0040085F822005FF0000405EB8400CD +:10893000817A4A0706D521F0040181724846032C4A +:1089400010D0FFDF641CE4B2062CEFD3761EF6B223 +:10895000A4D25846BDE8F88FFBF721F9CFE7FBF723 +:10896000E0F8D9E7FBF7DDF8ECE710B5032105F0F7 +:1089700056F8040000D1FFDF204600F0ACF8A078E4 +:1089800040F08000A07010BD10B5032105F047F83D +:10899000040000D1FFDF208D2321B0FBF1F0C0B235 +:1089A00010BD70B50D46032105F039F8040000D163 +:1089B000FFDF062D00D9FFDF072D03D0504830F828 +:1089C000150000E0208D04EB85010A89824205D262 +:1089D0008A7A012042F001028A7270BD002070BDC7 +:1089E00010B50446402801D2072010BD00F067F8FA +:1089F000082802D04FF4445010BD0021414802E045 +:108A0000491C082903D230F81120002AF8D108297E +:108A100003D020F81140002010BD042010BD10B577 +:108A2000402801D2072010BD00F049F8082805D0E1 +:108A3000344A002122F81010084610BD052010BD50 +:108A400070B588B015460C00064606D02DB160887A +:108A5000402804D2072008B070BD1020FBE7218811 +:108A600049B300F02CF8082827D003AA06A905A8C6 +:108A70008DE80700228804AB07213046FFF717FC7A +:108A80000028E8D1BDF810202946059812F0DCF93D +:108A90002088BDF81010884204D9421A294403984E +:108AA00012F0D2F905980090238862880721304699 +:108AB000FFF7DBFCCFE70C20CDE70520CBE7014635 +:108AC0000020104A02E0401C082803D232F810307F +:108AD0008B42F8D1704710B504462021083012F0BF +:108AE0004CFA0748002100BF30F8112004EB810345 +:108AF000491C1A810629F7D9208DA08410BD0000D9 +:108B000050B30100E407002030B44FF0E02001230F +:108B10004FF4006C0021C0F880C11D02C0F88051E4 +:108B20001C06C0F88041E54A82F80014D21E82F883 +:108B30000014E34A82F80014E24A53609360C2F8DA +:108B40004011C2F84411C2F84811C0F880C2C0F800 +:108B50008052C0F88042C0F800C1C0F800411360E4 +:108B600030BC704770B401204FF0E023C6024FF0D4 +:108B7000000CC3F880610402C3F880410506C3F805 +:108B80008051D04A50609060CF4801680029FCD1E4 +:108B9000C2F840C1C2F844C1C2F848C1C3F88062FB +:108BA000C3F88042C3F8805270BC70474FF0E02099 +:108BB0004FF40061C0F88012C910C0F880127047ED +:108BC000002804BFC1487047012804BFC04870474F +:108BD000022804BFBF48704700B5FFDF002000BD7A +:108BE00008B5B849002298B101282FD002281CBF2F +:108BF000FFDF08BD4FF48020C1F80803C1F8480327 +:108C0000B5480260C1F84821B2480068009008BD2C +:108C10004FF48030C1F80803C1F84803AF4B1A6025 +:108C2000C1F84021AE4BC1031960AE49C1F8080339 +:108C30004FF0E0230012C3F88001AB480260C1F896 +:108C40004021C1F80022A948027008BD4FF400304D +:108C5000C1F80803C1F84803A5480260C1F84421DF +:108C60009B480068009008BD70B5DFF858C2042624 +:108C70000024012558B1012840D002281CBFFFDF85 +:108C800070BD9C4A4FF48020012B3CD144E0881EEB +:108C900020F07F414FF48030CCF80803CCF84041FD +:108CA000CCF84403CCF84015012B14BF002101215E +:108CB0008E4B59708B490D61DFF83CC2CCF80040F7 +:108CC0008E4C4FF0020CC4F800C0DFF834C2CCF870 +:108CD0000060DFF814C23D32CCF80020C1F8005229 +:108CE0004FF0E02C8A15CCF88022C1F80403CCF8B0 +:108CF00000210804834908601D7070BD824A4FF44A +:108D00000030012B08D0CCF80803C2F84041CCF861 +:108D10004403C2F8401570BDC2F84041CCF80403CA +:108D2000CCF84403C2F8401570BD6748006870472E +:108D300070B576480568774975480860614CD4F885 +:108D40004001002601280AD1D4F8080310F4803F1E +:108D500005D04FF48030C4F80803C4F84061D4F85B +:108D6000440101280DD1D4F8080310F4003F08D0C5 +:108D70004FF40030C4F80803C4F84461012007F040 +:108D8000BCFBD4F8480101280DD1D4F8080310F435 +:108D9000802F08D04FF48020C4F80803C4F848613D +:108DA000022007F0AAFB5C48056070BD574810B56B +:108DB00004685849564808604C490878002808BF9C +:108DC00003201AD0464A4FF000401060454AC00BBD +:108DD000C2F8080303124FF0E02C0020CCF88031D9 +:108DE000414B1860C2F84001C2F8000208704A788E +:108DF000002A1CBF4870002001D007F07EFB4648C7 +:108E0000046010BD4FF0E0214FF08070C1F8000207 +:108E100070474FF0E0214FF08070C1F8800270473A +:108E20004FF0E0214FF40010C1F8000270474FF0FE +:108E3000E0214FF40010C1F8800270472949012059 +:108E400008614FF0E0210002C1F880027047410A3A +:108E500043F609525143C0F3080010FB02F000F53D +:108E6000807001EB50207047430B48F2376C03FBD6 +:108E70000CF31B0C4FEA432CC1F800C0DFF89CC078 +:108E800003FB0C0326484CF2F72C5843400D10FB13 +:108E90000CFC0CEB432303F580735B1213700A6820 +:108EA000104408607047194810B5046819491848FB +:108EB000086007F00FFC1848046010BD0BE000E0EC +:108EC00018E000E000B0004004B5004040810040E0 +:108ED00044B1004048B1004048B5004040B50040B2 +:108EE00008F5014000800040408500402800002037 +:108EF00044B5004008B000400485004008850040AB +:108F00001085004004F5014004B000401005024007 +:108F1000010000011805024014050240F7C2FFFFDE +:108F20006F0C010010B5EFF3108000F0010472B671 +:108F3000EC484178491C41704078012801D108F083 +:108F4000EBF8002C00D162B610BD70B5E54CE078AE +:108F500048B90125E570FFF7E5FF08F0E5F820B115 +:108F6000002008F0C1F8002070BD4FF0804065710E +:108F7000C0F80453F7E770B5EFF3108000F0010577 +:108F800072B6D84C607800B9FFDF6078401E607020 +:108F9000607808B908F0C4F8002D00D162B670BD41 +:108FA000D04810B5C17821B100214171C170FFF7DF +:108FB000E2FF002010BD10B5044608F0B5F8C9491D +:108FC000C978084000D001202060002010BD2DE9A4 +:108FD000F05FDFF810934278817889F80620002549 +:108FE00089F80710064689F8085000782F4620B106 +:108FF00001280FD002280FD0FFDF08F0A2F898B1A7 +:1090000008F0A6F8A8420FD1284608F0A5F80028D5 +:10901000FAD047E00125F0E7FFF784FF08F084F875 +:109020000028FBD00225E8E701208407E060C4F8AF +:109030000471AD490D600107D1F84412AA4AC1F389 +:10904000423124321160A8494FF0020B34310860DC +:10905000C4F804B3A060DFF894A2DAF80010C943A2 +:1090600041F3001101F10108DAF8001041F010019C +:10907000CAF8001000E020BFD4F804010028FAD09C +:10908000284608F069F80028FAD0B8F1000F05D199 +:10909000DAF8001021F01001CAF80010C4F808B383 +:1090A000C4F8047199F807004C4670B1307860B983 +:1090B00008F03AF8064608F025FA6FF0004116B1BC +:1090C000C4E9031001E0C4E9030115B12771BDE84B +:1090D000F09F01202071BDE8F05F00F0E1B810B50D +:1090E000040000D1FFDF4FF080414FF0FF30C1F8A6 +:1090F00008030022C1F80021C1F80421C1F80C21A5 +:10910000C1F8102108F016F828B176490120C8707E +:109110004878401C48702046BDE8104057E72DE9CC +:10912000F0410125AF077D616E4CE079F0B1012877 +:1091300003D0217A401E814218DA07F0F5FF064677 +:1091400008F0E0F9E179012902D9217A491C21725C +:109150000EB1216900E0E168411A022902DA11F139 +:10916000020F0EDC0EB1206100E0E060FFF7DAFED6 +:1091700007F0DAFF10B13D61A57000E02570002016 +:109180002072BDE8F0812DE9F05F5948D0F800B0B9 +:10919000574A5849083211608406D4F8080110B1C2 +:1091A0004FF0010801E04FF00008D4F8000100B1D1 +:1091B00001208146D4F8040108B1012600E0002610 +:1091C000D4F80C0100B101208246D4F8100108B196 +:1091D000012700E0002748EA090126EA010020EA09 +:1091E0000A00B84300D0FFDF0025B8F1000F04D01B +:1091F000C4F80851012007F077FFDFF8E880B9F1E3 +:10920000000F13D0C4F8005198F8050020B188F879 +:109210000550002007F068FF98F8000030B107F013 +:1092200083FF18B1012088F8020020610EB1C4F854 +:109230000451BAF1000F0AD0C4F80C5198F802009A +:10924000464600B9FFDFB5703570FFF794FE37B1C1 +:10925000C4F8105198F8040008B1FFF760FF2449E2 +:10926000091DC1F800B032E770B51E4DE87808B9A5 +:1092700007F056FF01208407A061A87858B100BF0D +:10928000D4F80C0120B9002007F066FF0028F7D1C0 +:109290000020C4F80C014FF0FF30C4F8080370BD83 +:1092A0002DE9F0411926B507C5F808630124AC6122 +:1092B0000020C5F80001C5F80C01C5F8100107F041 +:1092C00033FF084F10B1BC702C6100E03C70FFF719 +:1092D00029FE0549B87920310860C5F804636C613E +:1092E0004FE700002C0000201805004010ED00E0C2 +:1092F000100502400100000110B50D2000F06FF8CC +:10930000C4B26FF0040000F06AF8C0B2844200D02A +:10931000FFDF3A490120086010BD70B50D2000F054 +:1093200048F8374C0020C4F800010125C4F8045364 +:109330000D2000F049F825604FF0E0216014C1F8DD +:10934000000170BD10B50D2000F033F82C4801214C +:1093500041600021C0F80011BDE810400D2000F070 +:1093600033B8284810B504682649274808310860F2 +:109370002349D1F80001012804D0FFDF2148001D56 +:10938000046010BD1D48001D00680022C0B2C1F875 +:10939000002107F0D2FFF1E710B51948D0F800110D +:1093A0000029FBD0FFF7DDFFBDE810400D2000F0E5 +:1093B0000BB800F01F02012191404009800000F12C +:1093C000E020C0F88011704700F01F020121914099 +:1093D0004009800000F1E020C0F8801270470028AA +:1093E00006DA00F00F0000F1E02090F8140D03E021 +:1093F00000F1E02090F800044009704704D50040D7 +:1094000000D00040100502400100000110B52020EE +:1094100000F075F8202000F07DF84449202081F804 +:109420000004434900060860091D42480860F7F738 +:1094300069FF3F49C83108603F48D0F8041341F044 +:109440000101C0F80413D0F8041341F08071C0F892 +:109450000413364901201C39C1F8000110BD10B5B4 +:10946000202000F04CF8324800210160001D01600E +:109470002F4A481EE83A10602F4AC2F808032C4BC6 +:10948000C8331960C2F80001C2F860012B490860B6 +:10949000BDE81040202000F03DB825492848EC39AF +:1094A0000860704722492648E8390860704770B55F +:1094B0001F4A8069E83A224911601F49D1F80061CA +:1094C0000023204D1D4A5C1E1EB1A84206D3002178 +:1094D0000FE0D1F8606186B1A84209D2C1F800312D +:1094E000C1F860311460BDE87040202000F012B86F +:1094F0001168BDE8704011F072BDFFDF70BD00F073 +:109500001F02012191404009800000F1E020C0F8D5 +:109510008011704700F01F02012191404009800036 +:1095200000F1E020C0F880127047000020E000E069 +:1095300000060240841200200000024000040240A5 +:109540000100000100C001004FF0E0214FF0007069 +:10955000C1F88001C1F88002384B802283F80024D2 +:10956000C1F80001704700B502460420344903E009 +:1095700001EBC0031B792BB1401EC0B2F8D2FFDF54 +:10958000FF2000BD41F8302001EBC00100224A71EC +:109590008A7101220A7100BD294A002102EBC00034 +:1095A0000171704710B50446042800D3FFDF24483A +:1095B00000EBC4042079012800D0FFDF6079A17995 +:1095C000401CC0B2814200D060714FF0E0214FF0EA +:1095D0000070C1F8000210BD2DE9F041194805687E +:1095E00018491948083108601448042690F8000406 +:1095F000134F4009154C042818D0FFDF16E02178DE +:1096000007EBC1000279012A08D1427983799A4295 +:1096100004D04279827157F8310080472078401C8D +:10962000C0B22070042801D300202070761EF6B24C +:10963000E5D20448001D0560BDE8F08119E000E0B6 +:10964000F407002010050240010000014000002046 +:109650000F4A12680D498A420CD118470C4A126809 +:109660000A4B9A4206D101B507F020FFFFF715FF1C +:10967000BDE80140074909680958084706480749F5 +:10968000054A064B7047000000000000BEBAFECA43 +:10969000980000200400002088110020881100207C +:1096A000F84B586019721A80C90011F066BC00218D +:1096B000018070474FF6FF720280032008F029B93D +:1096C00070472DE9F04F0E46017804464FF0010A2D +:1096D0000AFA01F047F2FF1100EA01086168154635 +:1096E00097B00888A0F57F42FF3A06D0B8F1000F86 +:1096F00007D047F2FE12104203D0012017B0BDE898 +:10970000F08F40EA080008804FF00009A5B185F805 +:10971000009023780027052003220221DFF864B39C +:10972000102B75D2DFE803F0740D131C2F4A515A29 +:1097300031A5A175A9F1F0EF20780B28E9D004201C +:10974000DCE72970A089A5F8010032801DE1042121 +:109750002970A189A5F80110E189A5F8031082E01C +:1097600006202870A089A5F80100E089A5F803006B +:10977000208AA5F80500A28AE81DA16911F064FB02 +:10978000A08AC01D6FE0082129702178082901D125 +:1097900010212970A189A5F80110E189A5F803100D +:1097A00030806A1D694604F1100005F02AFE002889 +:1097B0007ED130889DF80010084454E00A202870BB +:1097C000A089A5F801003280AAE00C212970A189A6 +:1097D000A5F80110E189A5F80310B7E0A2890AEB0A +:1097E000420081B23088884262D3052960D30E20BE +:1097F0002870002008E0236905EB400C33F8103096 +:10980000401CACF8013080B29042F4D33180BCE00F +:10981000CAE09BF809005A46002873D0401E5072D7 +:10982000227BDBF80400236900EBC205AA882868C4 +:10983000D3F800C00244A2F1080042F808CC5A68EC +:1098400042608DF800108DF8019028680290A88879 +:10985000ADF8040000216846FBF786FCA5F80490EB +:10986000002E01D0484630808FE0287840F08001FB +:109870002970287840F040012970287820F03F00B6 +:1098800012302870A189A5F80110E289E81C21692D +:1098900011F0DAFAE089C01C3080287841063FD503 +:1098A000000672D58DF800A08DF80190308800E098 +:1098B00026E0001DADF804000295E189E81C08448B +:1098C0000390001D04909BF808008DF814000021FF +:1098D0006846FBF749FC074630880C303080022F81 +:1098E00001D007B363E09DF81420DBF804109BF867 +:1098F0000830584601EBC2019A4201D28A882AB147 +:10990000042754E030E02BE022E00DE0427A521CC4 +:109910008BF809200D6030888880A6F8009046E01A +:109920006168A089888030E0287820F03F001630F8 +:109930002870A089A5F80100E089A5F80300228A13 +:10994000681D616911F080FA208A401D3080E7E7C8 +:10995000287820F03F0018302870207B687055E789 +:1099600060680188090401D4052720E0C088A18926 +:10997000884201D006271AE01E202870A6F800A011 +:109980006068018821F400410180B8F1000F0ED019 +:10999000BBF80000002283000320A16807F01CFF31 +:1099A00061682078887007E0A6F800900327606857 +:1099B000018821EA0801018038469FE62DE9FF4F22 +:1099C00097B00C46249E70B117280CD83288A2F5A7 +:1099D0007F43FF3B07D02278530601D4120604D5FB +:1099E00008201BB08BE60720FBE74FF000098DF83D +:1099F00000908DF801902278831E02F03F0CA0F1B8 +:109A0000010A611C4D461FFA8AF702AABCF1200F19 +:109A100079D2DFE80CF089107861786C78AA78CD7B +:109A200078F778FC78F478F378F2787878F178F051 +:109A300078EF78EE7889052876D104208DF800003B +:109A4000B0788DF804006088ADF8060020798DF8B4 +:109A50000100607800F03F000C282BD00ADCA0F158 +:109A60000200092860D2DFE800F0145F175F1C5F76 +:109A70001F5F2200122826D006DC0E281DD01028D9 +:109A8000DAD11DE01408002016281FD01828D3D1E1 +:109A90001FE03078800701E030784007002843DA83 +:109AA00037E130780007F9E73078C006F6E730781C +:109AB0008006F3E730784006F0E730780006EDE7FF +:109AC0003088C005EAE73088C004E7E730888004C2 +:109AD000E4E730884004E1E73178890724D503289A +:109AE000AAD105208DF80000B4F80100D2E0317849 +:109AF0004907F3D5062817D3617898B2012903D016 +:109B0000022999D102E01FE1022700E01027062177 +:109B10008DF8001061788DF80610ADF80490A11C46 +:109B2000904607F102091BE097E000BF31F8022BD5 +:109B3000A0F1020AA8F800208B463A4608F102007C +:109B400011F082F908EB070202F10208BDF80420C7 +:109B5000AAEB0700521C0BEB070180B2ADF8042002 +:109B60008145E3D9002878D1D3E03078000774D557 +:109B700007208DF800001FFA8AF1ADF80490601CF0 +:109B80000DF106020FE000BF30F8023B22F8023B65 +:109B900030F8023B22F8023B091FBDF8043089B2BD +:109BA0005B1CADF804300429EED2002955D1B0E099 +:109BB0003178C90651D502284FD308208DF800000E +:109BC000ADF8069061789BB28DF80410A01C0CE0F3 +:109BD000078822F8047B871C80C25B1ABDF80670D8 +:109BE00008447F1C9BB2ADF806709942F0D9A3BB24 +:109BF0008FE070E075E065E04FE042E01DE012E0CC +:109C000005E0FFE73078800627D5092003E03078AB +:109C1000400622D50A208DF80000B088ADF8040077 +:109C2000ADF8067007E03078000616D50B208DF8E9 +:109C30000000ADF8047002916BE03188C9050CD5C5 +:109C400002287FD30C208DF8000099B2ADF8069061 +:109C500063788DF80430A01C10E073E0078822F8C8 +:109C6000027B478822F8027B071D80C2C91ABDF813 +:109C7000067018447F1C89B2ADF806708B42EDD98E +:109C800093E73188C9045DD501285BD10D208DF89B +:109C90000000B088ADF804003BE03188890451D55C +:109CA00005284FD30E218DF80010B188ADF80410AF +:109CB000B4F80310401FADF80800601DADF80610A1 +:109CC000039026E0318849043CD501283AD10F2081 +:109CD0008DF800001DE03188090433D4B4F8011078 +:109CE000F18003282ED3217801F03F011B2925D0D4 +:109CF00011218DF80010318841F40041A6F80010C0 +:109D0000B4F80110ADF80410C01EADF80600E01C58 +:109D10000290207800F03F001B2809D01D2807D0B2 +:109D200003201A9907F0F5FD308800F400403080D8 +:109D300068461999FBF718FA284652E610218DF863 +:109D40000010DDE70725F7E70825F5E700B597B030 +:109D5000032806D18DF80000019100216846FBF729 +:109D600003FA17B000BD00002DE9FF4F8DB09346F8 +:109D7000DDE91A56DDF8749004464FF0000A082A0F +:109D800006D0E06901F02CF858B110203070BCE02A +:109D90002888092140F01000288089F80010022747 +:109DA00017E0E16901208871E2694FF42051918048 +:109DB000E1698872E06942F601010181E1690020F0 +:109DC0008873288840F020002880112089F800003E +:109DD0000427307809900A20307004F1180009F146 +:109DE000020802250B9001F063FA002066E000BF34 +:109DF000BBF1100F06D1022D04D0A8EB0A00BDF86C +:109E00000C204280BDF80E001099884203D9F64913 +:109E1000097A0E9104E003D1099909B131701FE06C +:109E2000A8F800001C980088A0EB0500A0EB070034 +:109E300083B2C7F1FF00984200D203460E980AAAE7 +:109E400008EB07018DE8070094F82010BDF80E001C +:109E5000002201F09AFA307030B1C0B2832858D095 +:109E6000BDF80E0020833DE0089828B1DE48006868 +:109E700000790A282BD335E0BDF82800C11901F07C +:109E8000FF0A022D0ED099F80110514503D1BDF8FB +:109E90001820824208D0D4488A46006801780329F5 +:109EA00008D021E089F801A0CF4800680178042992 +:109EB00006D008E000790A2816D20120089006E0B2 +:109EC000BDF80E10818005EB0A00D04485B203AACC +:109ED0000E990B9801F0EFF920B91C980088401BEF +:109EE000B84285DA022D0BD0BBF1100F04D1A8EBDC +:109EF0000A01BDF80C0048801C98058000203070D5 +:109F0000B94800680078032803D0002011B0BDE8EC +:109F1000F08F0220FAE72DE9F0410546406B134629 +:109F2000002758B3491F8EB2698FA1F57F42FF3ACF +:109F300005D0421892881144891D8CB200E000249B +:109F4000A1192A8F0831914216D82044B3F8011084 +:109F500020F8021BB3F8031020F8021B324620F849 +:109F6000026B591D10F070FF6C87696B0020214453 +:109F7000B61D3144088002E0092700E083273846F7 +:109F8000BDE8F08110B50B88048F9C420CD9446B5E +:109F9000E018048844B1848824F40044A41D2344B8 +:109FA0000B801060002010BD822010BD2DE9F0470D +:109FB00088B00025904689468246ADF810500727A4 +:109FC00045E0039806888088000440D4A8F8006023 +:109FD00005A80097CDE901504FF4007300224946CF +:109FE000304601F0D2F9040038D1BDF81000ADF8C8 +:109FF0001800039804888188B44214D10A0412D44A +:10A00000CDE9005721F40041029541F48043428894 +:10A010004946204600F0C8FF04000BD10398818810 +:10A0200041F40041818003AA06A95046FFF7AAFF28 +:10A030000400DED0CDE9005703980295BDF8143036 +:10A0400000880022494600F0AFFF822C06D103AA07 +:10A0500004A95046FFF796FF0400B2D0ADF81050A7 +:10A0600004E00398818821F40041818003AA04A9B7 +:10A070005046FFF787FF0028F3D0822C03D02046FC +:10A0800008B0BDE8F0870020FAE730B50446406B21 +:10A0900097B0002570B10B208DF80000208FADF82F +:10A0A0000800606B0391019000216846FBF713FEE6 +:10A0B0008DF800504FF6FF7065636087258717B0F5 +:10A0C00030BD2DE9F041044686B00E46616B00209C +:10A0D0000C9D174600292AD0012B28D12A4631464B +:10A0E0002046FFF763FF002821D1002F1FD0A04694 +:10A0F00034460026ADF8106007270EE0039800886C +:10A10000288003980296811DCDE900178388428834 +:10A110000088214600F048FF30B903AA04A9404650 +:10A12000FFF730FF0028E9D0822800D1002006B0D8 +:10A1300026E72DE9F0411546DDE906644A1D37881A +:10A1400092B2974201D206201AE73280172204F811 +:10A15000012B0A46208065801946201D10F074FEF0 +:10A1600000200DE700220280C262831D0263C361EA +:10A1700042634FF6FF734387028780F820107047D1 +:10A180004FF6FF720280042007F0C3BB30B597B0D2 +:10A190000D460446FFF779FF208E48B101208DF867 +:10A1A0000000E06ACDE9010500216846FBF793FD58 +:10A1B0000020E062206382E70146002009880A0748 +:10A1C00000D5012011F0F00F01D040F00200CA05C7 +:10A1D00001D540F004008A0501D540F01000490582 +:10A1E00001D540F020007047200800202DE9FF4FE6 +:10A1F000A7B01F46349E299D379C5FEA000817D000 +:10A200002878410610D400F03F011E290AD0218889 +:10A2100011F4FE6F0CD13A88172A09D3A1F57F42B9 +:10A22000FF3A05D0010606D500F03F00122802D003 +:10A2300004202BB06BE6FE4928984FF00009087205 +:10A240008DF810908DF834900DAA0A60359A4A6006 +:10A25000ADF81490ADF890902878032200F03F03F9 +:10A260008646711C04F1180CCB464FF0040AA8F185 +:10A270000500CDF898C01F2B7DD2DFE803F07C7C71 +:10A28000107C1C7C867CEF7CEE7CED7CEC7CEF7C97 +:10A29000EB7C7C7CEA7CE97C7C7C7C7CE800B8F113 +:10A2A000030F02D08DF810A0EFE232701720A6F84D +:10A2B00001003A80BEE2B8F1050FF3D1B5F8010014 +:10A2C0002083ADF81400B5F80310618300287DD019 +:10A2D00088427BD884F808B0A4F806B04FF6FF7027 +:10A2E0006084269800F0E4FF05203070B01C0090D8 +:10A2F0004FF0020A08AA2899269800F0DCFF0028EF +:10A300007ED19DF82600012803D002207070102015 +:10A3100002E00120707002208346002201A909A8F2 +:10A3200005F06FF830BB9DF80400834522D13A88D0 +:10A33000801CA2EB0A0181421CDB0098BDF82210B0 +:10A340000AF1020A0180009909A8891C0A460091B5 +:10A3500001A905F056F89DF80400009908AA0144E7 +:10A3600050441FFA80FA00912899269800F0A3FF24 +:10A370000028D2D000E069E2BAF1020F40D0A7F87D +:10A3800000A057E28DF8100054E2B8F1070F89D30E +:10A39000B5F801002083ADF81400B5F8031061830F +:10A3A000A0B1884212D84FF0010A84F808A0B5F88D +:10A3B0000500E08000202073E06900F011FD90B9F5 +:10A3C000E16981F806A04FF4205100E078E0E269ED +:10A3D00042F601009180E16981F80AA0E1690881F3 +:10A3E000E16900208873A8F107006084E81D6062BD +:10A3F000269800F05DFF0720307006F1010A00E0AA +:10A400006FE000204FF0010BADF8220018E000BF14 +:10A41000BBF1010F0CD0E069807901281FD03AF818 +:10A42000021C00BF0BF102002AF8021B1FFA80FB7E +:10A43000BDF822100BF102002AF8021B1FFA80FB64 +:10A4400008AA2899269800F036FF58B10FE0DAE103 +:10A450006BE10AE1AEE0D2E17BE05AE01EE0BDF83C +:10A460002010DFE73988A1EB0B000428D0DABBF11C +:10A47000010F36D0E069807901280CD0BDF820109A +:10A48000A1F57F40FF3806D03AF8021CAAF8001068 +:10A490000BF10200B1E1BDF82010F7E7B8F1070FAA +:10A4A00003D0B8F1150F7FF4FDAEB5F8011021838C +:10A4B000ADF81410B5F80320628309B1914201D9B7 +:10A4C00001205FE701212172A4F806B084F80CB0E6 +:10A4D000B8F1050F07D0C0B2691DE26904F072FF40 +:10A4E00008B10A204EE74FF6FF70608404A824A943 +:10A4F000CDE90010CDE902762878002300F03F0274 +:10A5000020462899FFF730FC8146208BADF81400D7 +:10A5100090E1B8F1030FC6D14020ADF89000B5F836 +:10A5200001002083ADF81400289ACDE900210AAB80 +:10A53000029339880022491E8BB294F8201000F053 +:10A5400024FF8DF8100058BB0B203070BDF8280098 +:10A550002EE0B8F1050FA6D18020ADF89000B5F837 +:10A5600001002083B5F803206284ADF81400B2F531 +:10A57000007F01D9072005E742F47C426284289BD2 +:10A58000CDE900310DF12C0CCDF808C03988491EF9 +:10A590008BB294F8201000F0F8FE8DF8100018B17E +:10A5A0008328B5D10220BEE00D203070BDF82C000C +:10A5B000401C22E14FEADE1000EB400002EB80007D +:10A5C000404505D95FEA4E607FF56CAE584614E110 +:10A5D000B5F801C0ADF814C02978490608D50521A1 +:10A5E0008DF834102978090605D58DF834B031E19D +:10A5F00006218DF83410E91C289BA8EB000ACDE950 +:10A600000013CDF808B009911FFA8AF394F82010CE +:10A610000022604600F0C8FC8DF810008DF834B0C0 +:10A620002978490610D52088C00509D5208B01E07E +:10A6300020080020BDF81410884201D1C4F824B0CD +:10A6400058468DF810B0D8E0832801D14FF00209A8 +:10A650004FF48070ADF89000BDF814002083A4F88A +:10A6600022A0099860621320C5E0B8F1050FFFF43D +:10A6700019AEB5F801C0ADF814C0218F41B3A1F5F2 +:10A680007F42FE3A24D007218DF83410289A6B1DA2 +:10A69000CDE9003280B2CDF808B040F40043DA468C +:10A6A000B5F8032094F82010604600F07DFC4FF4CC +:10A6B00000718DF810008DF834A0ADF8901083284B +:10A6C00010D0E8B1218FA1F57F40FE3807D0DCE043 +:10A6D0000A218DF834104FF6FE712187D6E7A4F8D1 +:10A6E00038A0A7E02A4641462046FFF714FC8DF823 +:10A6F000100008B1832848D1BDF81400208351E729 +:10A700002A4641462046FFF706FC8DF81000E0BBC4 +:10A71000618F606BCDE9007643185A88998833F8C9 +:10A72000060BFFF706FD814684E095F801A0B8F11D +:10A73000020F7CD15FEA0A0002D0BAF1010F76D194 +:10A7400008208DF8340005A800908DF838A094F802 +:10A750002010534600222046FFF7B3FC8DF8390045 +:10A760008DF83AB050B9BAF1010F12D0BAF1000F1A +:10A7700004D1218FA1F57F40FF380AD0208F40B14E +:10A780008DF834B04FF4806000E053E0ADF89000F5 +:10A790000DE00DA83599FBF79EFA81464FF48060D5 +:10A7A0008DF834B0ADF89000B9F1020F06D0FD4835 +:10A7B0000068807928B18DF8100043E0A4F818A053 +:10A7C00038E0B9F1000F03D081208DF8100043E08C +:10A7D00005A8009094F82010534601222046FFF768 +:10A7E00070FC8DF8100020463699FFF74EFC9DF85E +:10A7F0001000F8B919203070012038801AE00620C6 +:10A800008DF8100041E02078000723D5B8F1010F42 +:10A8100020D109208DF83400A088ADF8380004203C +:10A82000369907F076F80820ADF8900000E011E0C6 +:10A83000A7F800B09DF8340020B10DA83599FBF7BA +:10A840004AFA8146B9F1000F1CD005E05FEA4E607C +:10A850007FF528AD4FF004092088BDF8901008431B +:10A860002080BDF8900080050AD5218FA1F57F409A +:10A87000FE3805D12998E062A4F830804FF0030932 +:10A880004846D6E49DF8100058B101203070287871 +:10A890007070BDF8140070809DF8100030710520B4 +:10A8A00038802088BDF8901088432080E8E72DE9A3 +:10A8B000FF4F0178A5B080464FF0010B0BFA01F075 +:10A8C0004FF60901349C0840ADF86C0021884FF028 +:10A8D0000009A1F57F42FF3A02D028B1080703D54D +:10A8E000012029B0BDE8F08F289F4FF0000A04A88E +:10A8F00087F800A02799269A55460988ADF87C105C +:10A90000A8498DF868A00A728DF810A008603298E6 +:10A91000486098F80000012830D0022809D00328A8 +:10A9200076D1387820F03F001D303870B8F8040038 +:10A93000A08098F80000022804D1387820F03F0069 +:10A940001B30387021AAF91C07208DE80700BDF8DC +:10A950007C0094F82010C01E83B2B8F804000022D6 +:10A9600000F013FD0028DBD1B8F80400A7F80100BF +:10A97000BDF88400C01CADF87C005FE198F80510BC +:10A980008DF8681098F804004FF40079012802D07F +:10A990000228C5D133E1208808F1080600F4FE60E2 +:10A9A000ADF86C0010F0F00F1BD010F0C00F05D008 +:10A9B0003088228B904201D005257DE189B9B0789D +:10A9C000C0070ED0B2680720CDE90020CDF808A05E +:10A9D000F388B28894F82010308800F0E5FA002857 +:10A9E0006FD12899BDF86C00491C802845D006DC41 +:10A9F00010280ED020280CD0402891D122E0B0F5AC +:10AA0000807F5FD048457DD0B0F5806F88D1CBE0A6 +:10AA100029E1C00601D5082000E01020814604206D +:10AA2000ADF814A01BAA8DF8100000921FA81AA957 +:10AA30000397CDE9011033884A4607212046FFF7E6 +:10AA400093F992E09DF868004FF00A09002894D12C +:10AA500021AA07208DE80700BDF87C0094F820109B +:10AA6000401E83B2208B002200F08FFC8DF868001E +:10AA70000B203870BDF8840019E09DF868004FF095 +:10AA80000C0900281CD123AA07208DE80700BDF877 +:10AA90007C00628C401E83B294F82010208B00F062 +:10AAA00074FC8DF868000D203870BDF88C00401CD7 +:10AAB000ADF87C0004208DF81000208BADF8140058 +:10AAC000BCE057E03188208B814253D19DF868105B +:10AAD0004FF01209002918D1616A81B1B178C90714 +:10AAE00048D0B3680722CDE90032CDF808A0F3883A +:10AAF000B28894F8201000F057FA8DF868001320FF +:10AB0000387000E002E0ADF87CB097E0B6F800C025 +:10AB1000208B84452ED19DF868004FF0160900283F +:10AB2000606B08D0E0B34FF6FF7000215646ADF8D9 +:10AB300008A0019027E060B1B178C9071AD1618FF0 +:10AB400043181FA8CDE900075A88998833F8060BE7 +:10AB500009E0B078C0070DD01FA8CDE90007B28882 +:10AB6000F1886046B368FFF7E4FA050066D0062D69 +:10AB70007AD03FE005253DE0019021AA02A92046B8 +:10AB8000FFF700FA0146628FBDF80800824201D04B +:10AB90000029F1D0608F616B0844068001986087BE +:10ABA0004CE00000200800209DF868004FF01809D4 +:10ABB00040B1208BC8B13088208320463399FFF7FD +:10ABC00064FA3BE004F118000090237E94F8201012 +:10ABD00001222046FFF775FA8DF868000028ECD1B5 +:10ABE00019203870ADF87CB0E7E705252046339989 +:10ABF000FFF74BFA9DF81000032857D05CE020883F +:10AC000000F40070ADF86C0048452CD1208FA0F501 +:10AC10007F41FE397FF4D0AED8F808004FF0160916 +:10AC200048B16063B8F80C1021874FF6FF71618757 +:10AC3000A0F800A002E04FF6FF702087BDF86C007E +:10AC400030F4FE6116D0782300220420339906F0F8 +:10AC5000C3FD98F80000A0702088BDF86C10084370 +:10AC600020800AE000E006252088BDF86C108843AB +:10AC7000208021E02188814321809DF8100028B1A7 +:10AC80005F48416804A8FBF726F805469DF8680070 +:10AC900090B187F8019087F800B0208B78809DF8FC +:10ACA000680038710520ADF87C0005E05448416823 +:10ACB00004A8FBF710F80546208810F4FE6F22D197 +:10ACC000208E00B32799289B01AD0988ADF87C1030 +:10ACD000DDE93212009385E816001FABE26A26997F +:10ACE000FFF784FA054603280DD08DF810B0E06A0E +:10ACF000059033980690002104A8FAF7ECFF00B104 +:10AD00000546A4F830A02798BDF87C10018028469D +:10AD1000E7E500B597B0042807D102208DF80000C0 +:10AD2000019100216846FAF7D6FF17B000BD70B553 +:10AD3000334C037800222168012B02D0022B44D12E +:10AD400029E00B780BB1042B03D10A71226803218F +:10AD500011702168062582880B7905EBC303CA525E +:10AD6000216808230A250A7903EBC2021144C2882C +:10AD70000A80216802890B7905EBC303CA52418915 +:10AD800020680C23027903EBC2028152206801790A +:10AD9000491C01711DE00A7482888A802168C2887A +:10ADA000CA80226801891181226841895181C16864 +:10ADB0002068C1606168FAF78EFF0146022806D05C +:10ADC0002068007C002801D119B1812070BD83204A +:10ADD00070BD002070BD406B002800D0012070477E +:10ADE0008178012909D10088B0F5205F03D042F6AF +:10ADF0000101884201D10020704706207047000001 +:10AE00002008002010B58B7883B102789A4205D1D2 +:10AE10000B885BB102E08B79091D4BB18B789A42AC +:10AE2000F9D1B0F801300C88A342F4D1002010BD54 +:10AE3000812010BD07282BD012B1012A2CD103E0AC +:10AE4000497801F0070102E04978C1F3C201052900 +:10AE500022D2DFE801F0031D081017000AB1032019 +:10AE6000704702207047042812D0052810D0062809 +:10AE70000ED058B10EE005280AD0062808D00228C6 +:10AE800008D003E0062803D0032803D0052070472C +:10AE9000002070470F2070478120704710B513883D +:10AEA0000B800B781C061FD5FE4CA47A844204D874 +:10AEB00043F010000870002010BD94682478C4404E +:10AEC00064F304130B701378D17803F0030341EAA1 +:10AED000032140F20123B1FBF3F403FB1411926848 +:10AEE00000FB0120401C10BD906810BD37B5BDF8B7 +:10AEF000041011809DF8045029061BD5E94901234F +:10AF00009468897A814209D8FE280FD1E80602D5D3 +:10AF10008B405B1E00E00023237007E02178834014 +:10AF20009943C5F30013834019432170107820F032 +:10AF3000100010703EBD2DE9F0410746C81C0E46BA +:10AF400020F00300B04202D08620BDE8F081082A3C +:10AF500001D90E20F9E7D34D002034462E60AF8092 +:10AF60002881AA72E8801AE0E988491CE9808106F4 +:10AF700014D4E17800F0030041EA002040F20121FE +:10AF8000B0FBF1F201FB1201206800F0E3FA29891D +:10AF9000084480B22881381A3044A0600C342078EC +:10AFA0004107E1D40020D0E72DE9FF4F85B01546D9 +:10AFB000DDE912B68046994623F4404700F0BAFA1C +:10AFC00004000BD0207800060AD5B648817A06988E +:10AFD000814205D8872009B0BDE8F08F0120FAE74B +:10AFE000224669460698FFF759FF824600208DF8F1 +:10AFF0000400072E18D0012221463046FFF71AFF21 +:10B000000028E8D1207840060ED502208DF80400F3 +:10B01000ADF80880BDF80000ADF80C50ADF80A009E +:10B02000ADF80E70CDF810B05FEA094004D50027E6 +:10B030003D46B84601260CE02178E07801F0030196 +:10B0400040EA012040F20121B0FBF1F2804601FB11 +:10B0500012865FEA494009D5B04507D1A178207929 +:10B0600001F0030140EA0120A84201D3B54201D911 +:10B070000720B0E778191FFA80F9B14501D90D20F2 +:10B08000A9E79DF8040020B101A8FAF722FE0028E4 +:10B09000A1D1B04507D1A0784FEA192161F3010091 +:10B0A000A07084F80490149800B10780BBF1000FE1 +:10B0B00015D00AEB05003A4659460FF0C5FE224668 +:10B0C00069460698FFF7EAFE9DF80000224620F048 +:10B0D00010008DF8000000990698FFF707FF002088 +:10B0E00079E72DE9FF4FDFF8BC9182461746B9F8A2 +:10B0F0000610D9F8000001EB410100EB810440F299 +:10B100000120B2FBF0F183B000FB11764D46DDF873 +:10B1100044803146049800F01DFA29682A898B463C +:10B12000611A0C3101441144AB8889B28B4202D8B8 +:10B13000842007B050E70499CDB2290603D5A906AB +:10B1400001D58520F5E7B9F806C00CF1010C1FFA0E +:10B150008CFCA9F806C0129909B1A1F800C0A90693 +:10B1600002D5C4F8088007E0104480B2A9F80800AE +:10B17000191A01EB0B00A0602246FE200499FFF78C +:10B18000B5FEE77026712078390A61F30100320AB2 +:10B19000A17840F0040062F30101A17020709AF8D8 +:10B1A00002006071BAF80000E080002626732806CD +:10B1B00002D599F80A7000E00127A80601D54FF0E2 +:10B1C00000084D4600244FF007090DE0CDF800803F +:10B1D000CDE90196E8882146109B069AFFF7E4FE28 +:10B1E0000028A6D1641CE4B2BC42EFD30020A0E743 +:10B1F0002DE9F047804600F09DF9070005D00026B4 +:10B200004446284D40F2012916E00120BDE8F087B0 +:10B21000204600F08FF90278C17802F0030241EA7B +:10B220000222B2FBF9F309FB1321006800F092F946 +:10B230003044641C86B2A4B2E988601E8142E7DC17 +:10B24000A8F10100E8802889801B2881002038703F +:10B25000DCE720B1401E1080917000207047012073 +:10B26000704710B50F4904460088CA88904201D340 +:10B27000822010BD096800EB400001EB800250798C +:10B28000A072D08820819178107901F0030140EA02 +:10B290000120A081A078E11CFFF700FE206120883A +:10B2A000401C01E02C0800202080E080002010BD20 +:10B2B0000121018270472DE9FC474FF6FF780546D2 +:10B2C000A2F80080406817468A4680788DF8020010 +:10B2D00068680088ADF8000000208DF80600288A14 +:10B2E0002C88A04200D304462C822DE0288A401CE2 +:10B2F0002882701D6968FFF785FD18BB39884145B4 +:10B3000001D1601E38806888A04222D3B17830799C +:10B3100001F0030140EA01296946701DFFF772FD43 +:10B3200080B96989414519D0002231465046FFF75E +:10B3300081FD38B96A894A4504D1E968B0680FF0DF +:10B3400057FD58B1641CA4B2204600F0F3F8060083 +:10B35000CCD1641E2C828220BDE8FC877C80707971 +:10B36000B871F088B8803178F07801F0030140EAD4 +:10B3700001207881A7F80C90287A324607F108015D +:10B38000FFF78CFD38610020E6E72DE9F04F85B02E +:10B390001D4690460F468346DDF838A0DDF8409004 +:10B3A00000F0C8F8040009D02078000608D57148DC +:10B3B000807AB84204D8872005B00DE60120FBE76B +:10B3C000C8F30906224669463846FFF767FD074677 +:10B3D0005046BAF1070F1AD000222146FFF72AFD86 +:10B3E0000028E9D12078400611D501208DF804000D +:10B3F000ADF808B0BDF80000ADF80A00ADF80C607B +:10B40000ADF80E5001A8FAF764FC0028D4D12178D9 +:10B41000E07801F0030140EA0121A278207902F0EE +:10B42000030240EA0220464507D0B1F5007F04D967 +:10B43000691E814201DD0B20BEE7864201D907204B +:10B44000BAE7801B82B2AA4200D92A46B9F1000F9E +:10B4500001D0A9F800200F9810B1B9190FF0F4FC31 +:10B460000020A9E72DE9F0411D4617460E4600F0E1 +:10B4700061F8040008D02078000607D53D48807A9E +:10B48000B04203D8872060E501205EE522463946B8 +:10B490003046FFF703FD65B12178E07801F0030144 +:10B4A00040EA0120B0F5007F01D8012000E0002033 +:10B4B0002870002049E52DE9F0411D4617460E464B +:10B4C00000F038F8040008D02078000607D5294895 +:10B4D000807AB04203D8872037E5012035E522463F +:10B4E00039463046FFF702FDFF2D14D02178E07871 +:10B4F00001F0030240EA022040F20122B0FBF2F325 +:10B5000002FB130015B900F2012080B2E070000ABE +:10B5100060F301012170002017E510B50C4600F022 +:10B5200009F828B1C18821804079A070002010BDA1 +:10B53000012010BD0F49CA88824209D340B1096871 +:10B5400000EB40006FF00B0202EB800008447047F4 +:10B5500000207047C0B2820609D4000605D5054810 +:10B56000807A4843401C80B27047084670470020EC +:10B57000704700002C08002010B506F089FB05F08C +:10B5800024FEFBF721FF0EF057FB06F081FABDE821 +:10B59000104006F00DBB10B50C4601F0C1FC80B3A5 +:10B5A000204600F0ACFA68B322780E2A09D00F2AA0 +:10B5B00007D0022A05D0032A03D0102A2ED0FFDF9D +:10B5C0001DE0A0781E282BD00FDC0C2824D008DC2E +:10B5D000092825D2DFE800F013241724241E1E1AA0 +:10B5E0001C0012281CD1072010BD302818DDA0F146 +:10B5F0003A00032814D2DFE800F011130B000020FA +:10B6000010BD11E00EE043F20200F9E70420F7E775 +:10B610000D20F5E70F20F3E70820F1E71120EFE711 +:10B620000320EDE7FFDFEAE7FFDFE8E700F067BAB6 +:10B6300070B50346002002466FF02F050EE09C5CBB +:10B64000A4F130060A2E02D34FF0FF3070BD00EB9C +:10B65000800005EB4000521C2044D2B28A42EED357 +:10B6600070BD30B50A240AE0B0FBF4F304FB13000C +:10B670008D18303005F8010C521E1846D2B2002A3F +:10B68000F2D130BD30B500234FF6FF7510E0040A4B +:10B6900044EA002084B2C85C6040C0F303146040F8 +:10B6A00005EA00344440E0B25B1C84EA40109BB2DF +:10B6B0009342ECD330BD000010B509F0D8FB04284C +:10B6C00003D009F0D4FB052802D108F0D2F950B913 +:10B6D00009F05AFC032803D009F05CFC032804D1CC +:10B6E00007F0ACFA08B1012010BD002010BD70B504 +:10B6F0000C460546062102F092F9606008B1002070 +:10B7000006E00721284602F08AF9606018B101209E +:10B710002070002070BD022070BD2DE9FC470C4652 +:10B7200006466946FFF7E3FF00287DD19DF800003B +:10B7300058B107F0E5F9B0427ED0002221463046EC +:10B740000BF0F1FC002874D116E007F040FFB04286 +:10B7500072D00022214630460BF0D8F8002868D17C +:10B76000019D95F89800303518B9687E08B1012020 +:10B7700000E00020804603E0019D95F849803035C7 +:10B780004FF0010A95F82D004FF00009A0B195F88F +:10B790002E00800710D584F8019084F800A084F86A +:10B7A0000290A68095F82F10A171298E2181698EB3 +:10B7B000618185F82D903CE0304602F0A8FA070040 +:10B7C00000D1FFDF384601F049FD10F0FF0008D03E +:10B7D00084F801900D212170A680E08084F802A0F9 +:10B7E00027E0304602F081FA070000D1FFDFB8F110 +:10B7F000000F21D0384601F0BCFDA8B19DF8000033 +:10B8000038B90198D0F8BC004188B14201D180F824 +:10B810000090304607F0D9F884F801900A21217091 +:10B8200084F80290A68000E006E0A97EA17185F868 +:10B8300019900120BDE8FC870020FBE71CB5694694 +:10B84000FFF755FF00B1FFDF684601F0B1FBFD498E +:10B8500000208968A1F89A001CBD2DE9FC4104462E +:10B860000E46062002F086F80546072002F082F810 +:10B870002844C7B20025A8463E4417E02088401C53 +:10B8800080B22080B04202D34046A4F8008080B24B +:10B89000B84204D3B04202D20020BDE8FC81694620 +:10B8A000FFF725FF0028F8D06D1CEDB2AE42E5D8B9 +:10B8B0004FF6FF7020801220EFE738B54FF6FF708B +:10B8C000ADF800000DE00621BDF8000002F0B9F867 +:10B8D00004460721BDF8000002F0B3F80CB100B136 +:10B8E000FFDF00216846FFF7B8FF0028EBD038BD26 +:10B8F0002DE9F041D4A0D64C06790025076884F8DC +:10B90000425001F04EFB84F8435004202087102061 +:10B9100060874FF6FF70A4F80A0184F80C51A4F870 +:10B920000E0184F8315004F8EE5BC94804F8C05C9D +:10B9300004F8BA5C8030A57340F87D7FC449067175 +:10B94000FD31481E0BF08DF80A202075032060752C +:10B95000A075E0750E20207606206076A076E07651 +:10B96000BDE8F0812DE9F041B64C0D4660602170D4 +:10B9700007F013F8FFF7A1FFFFF7BAFF207809F0EF +:10B980001CF8B349C431A1F181000F46064607F007 +:10B990003FFF60680BF030F820780CF0D1FB2846B0 +:10B9A00009F0B9FE3946304607F0E6F860680BF05A +:10B9B00045FC01F0F6FAA649002081F84300CFE7E4 +:10B9C00010B501240AB1002010BD21B1012903D016 +:10B9D0000024204610BD02210DF09EFBF9E72DE961 +:10B9E000F047040000D1FFDF994D002695F83100A3 +:10B9F00058B166701020207095F83200A07095F84C +:10BA00003300E07085F831606AE0287840B12C227C +:10BA1000A91C20460FF018FA0E2020702E705FE04F +:10BA200095F82E0060B10120E07095F82F00A0700D +:10BA300095F8300060700F20207085F82E604FE080 +:10BA4000844802218246FFF708FF00B1FFDFB5F806 +:10BA50000E91062001F08EFF0746072001F08AFFB5 +:10BA60003844C7B2781C00F0FF0800BFB5F80E01DB +:10BA7000B84213D10021204607F05CFD58BB95F871 +:10BA8000340080B36670132020701C21A01C0FF0BE +:10BA900052FA0220A07085F8346021E040451BD1A5 +:10BAA0000021204606F0FEFFE8B12078132817D1C8 +:10BAB000A0783C2814D1A088072101F0B0FF050030 +:10BAC00000D1FFDF288806F080FFA088072101F061 +:10BAD000B8FF00B1FFDF03E02146FFF71EFE10B103 +:10BAE0000120BDE8F087FFE702215046FFF7B5FED1 +:10BAF00018B9B5F80E114945B8D10020F1E76EE745 +:10BB000010B508F0C8FE00B1FFDF0AF073FF00B106 +:10BB1000FFDF07F033FE09F0E7FD00B1FFDF0BF0B8 +:10BB20008BFB00B1FFDF06F0F5FF00B1FFDF0CF08B +:10BB300001FB00B1FFDFFFF7C0FEFFF7D9FE06F003 +:10BB400015FF02F0C1F801F02CFA4148002180F8FD +:10BB500043100171012141710222C270017010BDB8 +:10BB600010B53B4C207828B10A21BDE810400E20CA +:10BB700001F0E4B9FFF7A0FD08B10C2002E001F0EC +:10BB800010FA00202071012060710A21E1702070FC +:10BB900010BD70B52E4C0546207828B1BDE8704028 +:10BBA00039210E2001F0CAB9FFF786FD08B10C203B +:10BBB00012E094F8430008280DD204EB0010102284 +:10BBC0002946443001F0C7F994F84300401C84F83A +:10BBD0004300002000E0072020710120607139211E +:10BBE000E170207070BD70B5194C0546207828B101 +:10BBF000BDE870400B210E2001F0A0B9287818B1E3 +:10BC0000012801D0122016E094F8C400082823D29D +:10BC1000FFF752FD08B10C200DE00E482B7894F888 +:10BC2000C4106A1C463806F018F994F8C400401C89 +:10BC300084F8C40000202071012060710B21E170A4 +:10BC4000207070BD44000020FFFFFFFF1F000000B8 +:10BC500038080020460900200720ECE710B5FE4C0C +:10BC6000207828B13821BDE810400E2001F066B9D7 +:10BC7000FFF722FD08B10C2002E0002084F8430009 +:10BC80002071012060713821E170207010BDF248F0 +:10BC9000017819B10F210E2001F050B90021017176 +:10BCA0000E2181700F21C170FF2181714FF6FF714C +:10BCB0000181EA4949680A7882728A8882814988C2 +:10BCC000C1810121417101707047E3490A781AB1BD +:10BCD0003B210E2001F032B90088A1F80A010120B1 +:10BCE00081F80C0100220A7148713B22CA70087069 +:10BCF000704710B5D84C207828B12B21BDE81040F2 +:10BD00000E2001F01BB90821A01D05F0F7FA002054 +:10BD10002071012060712B21E170207010BD70B581 +:10BD2000CD4C217829B1BDE8704031210E2001F0C1 +:10BD300005B990F90000042814D098B1011D11D064 +:10BD400010F1080F0ED010F10C0F0BD010F1100FE6 +:10BD500008D010F1140F05D010F1280F02D01220D6 +:10BD6000207103E0002506F0B9F825713120E0705C +:10BD700001206071207064E730B5B74D04468DB086 +:10BD8000287828B12A210E2001F0D8F80DB030BD56 +:10BD900010222146684601F0DEF8102204F110015D +:10BDA00004A801F0D8F868460DF0E0FF10222C46F8 +:10BDB000A81D08A901F0CFF8002020710E20A07066 +:10BDC0002A20E070012060712070DFE72DE9FF413B +:10BDD000A14C207828B13A210E2001F0AFF8BDE83F +:10BDE000FF814FF0000884F80680B4F80A01ADF82E +:10BDF000040002A9FFF77BFC20B1002101A8FFF796 +:10BE00002CFDE8BBBDF80400ADF8000002A980B22B +:10BE1000FFF76DFC00B1FFDFBDF8000001F077FF18 +:10BE2000050000D1FFDF2846039F01F0A9FA80F04A +:10BE3000010697F84950BDF8000001F056FF0700D1 +:10BE400000D1FFDF384601F094FA80F0010255EA94 +:10BE5000020019D0A179BDF8000004EB410108816E +:10BE60007D49A3791831585C65F300005854A379D3 +:10BE700062F341005854A27966F38200505400E006 +:10BE80000DE0A079401CA07100216846FFF7E5FC99 +:10BE900028B9BDF80000BDF804108842B6D10120D1 +:10BEA00084F8048060713A21E170207097E770B5E2 +:10BEB000694C0546207828B1BDE8704034210E2039 +:10BEC00001F03CB808F0D3FF052804D0284608F05C +:10BED00061FD002000E00C20207101206071342100 +:10BEE000E1702070ADE65C48017819B10E2108467A +:10BEF00001F024B85949CA68C0F80620098A41816E +:10BF000000210171012141710E22C2700170704740 +:10BF100070B5514C0646251D207828B1BDE870400B +:10BF200032210E2001F00AB83146002006F00CFF45 +:10BF3000287058B900213246084607F051FD287094 +:10BF400020B946483168C160B18801820120607122 +:10BF50003221E170207074E670B53F4C05462078C0 +:10BF600028B1BDE8704030210E2000F0E7BF08F096 +:10BF7000C4FD10B909F05CFE68B1287809F02CFC0A +:10BF8000287807F0A5FD0020207101206071302184 +:10BF9000E170207055E60C20F6E72DE9F0412E4CBB +:10BFA0000646251D207828B1BDE8F04117210E2056 +:10BFB00000F0C4BF3146012006F0C6FE28700127FC +:10BFC00068B932460121002007F00AFD287030B917 +:10BFD0003068E063B088A4F8400084F8427067716C +:10BFE0001720E0702770BBE438B51B4D0446287855 +:10BFF00028B1BDE8384030210E2000F09FBF2279E3 +:10C0000061798A4215D0A079E379984211D01F2A2C +:10C010000FD81F290DD8002211460EF055F940B94E +:10C020000022E07911460EF04FF910B9207A072866 +:10C0300001D912201BE04FF6FF70ADF8000008F0A8 +:10C04000A3FFD8B908F0A6FFC0B908F010FFA8B93F +:10C050000021684604E00000380800204400002069 +:10C06000FFF7FBFB50B1204605F030FE00202871A1 +:10C07000012068713E21E970287038BD0C20F6E778 +:10C080002DE9FC47FE4C054694F82E0028B12821E6 +:10C090000F2000F053FFBDE8FC87282084F8300013 +:10C0A000012184F82E10A8784FF000091A2825D015 +:10C0B0000EDC162831D2DFE800F03030303030218D +:10C0C000303030303030303030303030302121219D +:10C0D0002A2822D00BDCA0F11E000C281DD2DFE89C +:10C0E00000F01C1C1C1C1C1C1C1C1C1C1C0D3A38AD +:10C0F000042812D2DFE800F0110211022888B0F5FE +:10C10000706F0AD21F20884684F82F00288869465D +:10C11000FFF7EDFA18B1022019E0122017E09DF8A0 +:10C120000000019F002806D007F1CE07019E05D12F +:10C1300006F1B50604E007F1B407F7E706F1CF060C +:10C14000684600F023FF08B1387818B10C2084F855 +:10C150002F00A0E787F80080A878307084F82F902F +:10C16000684600F025FF96E77CB5C54C054620786B +:10C1700020B125210E2000F0E1FE7CBD2888694613 +:10C18000FFF7B5FA002168B102202071BC48816038 +:10C190000173E1800E20A0702520E0700120607105 +:10C1A00020707CBD019A104612F1300282F83610E0 +:10C1B0008368A360037B237392F83630002BF5D19C +:10C1C0002888E080E6E72DE9FC41AD4C064694F86E +:10C1D0002E0028B110210F2000F0B0FEBDE8FC8138 +:10C1E0001F2084F82F00102084F83000012784F8E5 +:10C1F0002E7030886946FFF77AFA70B9684600F009 +:10C20000C5FE50B1019D9DF8000030350028019811 +:10C2100005D0E230017841B904E0022006E0D0F810 +:10C22000BC00F7E795F82D1019B13A2084F82F00DB +:10C23000D4E795F82E1089070CD1042101709DF8E0 +:10C24000000020B901993088D1F8BC1048806846B8 +:10C2500000F0AEFE002084F82F0085F82D70BDE7B9 +:10C260002DE9F047864D0646287828B1BDE8F0470D +:10C270001D210E2000F062BE4FF01F0985F80490CA +:10C28000012068711D21E970287008F0F0FD0C276D +:10C2900004284ED005284CD0B0791224012800D0B3 +:10C2A000E8B9307808B1012819D1F07908B101282E +:10C2B00015D1708843F6FD71021F30248A420ED2D8 +:10C2C000B288121F8A420AD22887B0886887B0795C +:10C2D0004FF000084446012803D050B111E02C7102 +:10C2E0000CE495F8420020B3654A3C32012108462F +:10C2F00002E0644A0021012007F072FB040000D034 +:10C30000FFDFF079012800D010B907F091FB044657 +:10C3100014B185F80490E3E73078012801D018B112 +:10C3200009E00021022001E00021012007F095FB37 +:10C3300008B12F71D4E785F80480D1E770B5504C6F +:10C34000217829B1BDE870401E210E2000F0F6BD15 +:10C350001F212171012161711E22E270217002787A +:10C360001221012A00D01AB9407818B1012801D051 +:10C37000217166E400260C25012A08D008F077FD1B +:10C38000052802D008F034FA30B1257159E4618FE4 +:10C39000208F08F0BFFBF7E7267152E42DE9FE4F2E +:10C3A0000546AFF25C71D1E90001354E01908A4635 +:10C3B00096F82E0030B103B02121BDE8F04F0F20D8 +:10C3C00000F0BCBD1F2086F82F00212086F8300029 +:10C3D0004FF0010886F82E80298843F6FD730A1F66 +:10C3E00030209A427ED26A88141F9C42FAD28A4236 +:10C3F00078D8EA8940F67B43911F9942F2D2298A84 +:10C400008C1F9C42EED28A42F2D86A8AB2F5FA7F39 +:10C41000E8D2AA8A40F67744A2F10A03A342E1D205 +:10C42000B2EBD10F5ED9E98A2A8B9142E0D8297903 +:10C43000122011B1012955D102E069790029F9D101 +:10C44000297B09B10129F6D108F011FD4FF00C0943 +:10C4500005286ED008F00BFD0428FAD096F83400B9 +:10C46000002866D107F0B3F8A0F57F41FF39F8D175 +:10C47000062102A801F0A4FA040050D0032103E031 +:10C4800038080020500000200CF034FB96F803011F +:10C4900000901B2296F802312088114601F070FBB3 +:10C4A00004283ED000B1FFDF208806F08DFA04F1A9 +:10C4B0000D07B4F800B00421384604F01FFF5946B8 +:10C4C00038460CF00CFCFDA03F1D006800900321D5 +:10C4D000684604F09EFE002069460A5C3A54401CFF +:10C4E000C0B200E06FE00328F7D3288A6080688A32 +:10C4F000A080A88AE08096F8051196F8040108F05B +:10C50000C8FA0146204608F0F0FA002784F8367091 +:10C5100084F83770687968B101280FD10CE00920E0 +:10C5200051E02088062101F08CFA00B1FFDF0720DE +:10C5300049E071E0677601E084F81980D5F80600DB +:10C54000C4F81A006889E0830198A06084F80CA000 +:10C5500084F8C4808DF800700121684604F059FE0B +:10C560009DF8000000F00701C0F3C1021144C0F3C0 +:10C57000401008448DF80000401D2076092801D2A3 +:10C5800008302076002120460CF0B4FA287B18B140 +:10C59000012805D0FFDF24E00021C94A012005E081 +:10C5A00096F8420098B10121C64A084607F018FAE9 +:10C5B000B8B1208806F009FA2088062101F041FA76 +:10C5C00000B1FFDF1F2086F82F00BDE8FE8F208816 +:10C5D00006F0FBF92088062101F033FAE0B1FFDF15 +:10C5E0001AE02879012800D010B907F021FA50B9D3 +:10C5F0002146032007F031FA28B96A8829882046A5 +:10C6000008F005FA58B1208806F0DFF920880621E5 +:10C6100001F017FA00B1FFDF86F82F90D5E784F814 +:10C62000B87086F82F70D0E738B5A64C3C3C20781F +:10C6300020B122210E2000F081FC38BD1F20207186 +:10C64000012565712220E070257008F010FC052896 +:10C6500002D00C20207138BD00202071684608F0FF +:10C6600090FA0028F7D10098008806F0AEF90098FB +:10C670000621008801F0E5F900B1FFDF904884F859 +:10C6800034500C380078FCF78DFF38BD2DE9F041AF +:10C690008C4D04463C3D95F82E0028B1BDE8F04194 +:10C6A00023210F2000F04ABC1F2085F82F002320F3 +:10C6B00085F83000012085F82E00618840F67B4324 +:10C6C0008A1F30209A4251D2A288961F9E424DD294 +:10C6D00091424BD8E188B1F5FA7F47D2218940F6E3 +:10C6E0007746A1F10A03B34240D2B1EBD20F3DD954 +:10C6F0006189A289914239D84FF00008208806212B +:10C7000001F08DF906004FF0020707D000F030FC71 +:10C7100020B1D6F8BC00017839B902E085F82F7055 +:10C7200061E4D6F8D010097809B13A201EE005215D +:10C730008171D6F8BC004146A0F80880D6F8BC202C +:10C74000A0885081D6F8BC20E0889081D6F8BC2023 +:10C750002089D081D6F8BC00028943899A4204D846 +:10C760008279082A01D89A4203D3122085F82F0033 +:10C7700039E422884280D6F8BC00077085F82F1073 +:10C7800031E42DE9FE434F4C06463C3C207830B165 +:10C7900003B02421BDE8F0430E2000F0CFBB0125FB +:10C7A00065712420E070257030460CF0BAFA08B1AB +:10C7B000002000E01220207100282DD1414884F88B +:10C7C000FC504430316840F87D1F317901714FF0E1 +:10C7D000000884F8FC806946062001F0ACF800B13E +:10C7E000FFDF684601F085F8A0B9BDF8047000BF0E +:10C7F000BDF80400062101F012F9060000D1FFDFA8 +:10C8000086F8C450684601F074F818B9BDF8040001 +:10C81000B842EDD184F80480BDE8FE8370B5294D9F +:10C8200006463C3D95F82E0028B1BDE87040262113 +:10C830000F2000F083BB1F2085F82F00262085F8ED +:10C840003000012085F82E003088062101F0E7F83D +:10C85000040007D000F08CFB20B1D4F8BC000178B4 +:10C8600031B901E002200CE0D4F8D010097809B108 +:10C870003A2006E005210170D4F8BC1030884880C9 +:10C88000002085F82F0074E50E483C38017819B176 +:10C8900006210E2000F052BB002101710E22827091 +:10C8A0000622C270C0F80610C0F80A10817941F063 +:10C8B0000101817101214171017070471122330022 +:10C8C000500000207408002070B5F84E054696F818 +:10C8D0002E0028B1BDE870402C210F2000F02EBBA7 +:10C8E0001F2086F82F002C2086F83000012086F8C3 +:10C8F0002E002888062101F092F8040007D000F0ED +:10C9000037FB20B1D4F8BC00017831B901E0022036 +:10C9100020E0D4F8D010097809B13A201AE094F850 +:10C920006410D1B1D5F802104160D5F806108160CD +:10C9300054F8BC0F698910228181206805F10C012F +:10C940000E300EF081FA21680320087021682888D3 +:10C950004880002086F82F000BE50C20FAE770B520 +:10C96000D24E04460C25307828B1BDE8704018211D +:10C970000E2000F0E3BA08F007FB032852D008F0BD +:10C9800009FB03284ED0607908B1012829D1A0798C +:10C9900008B1012825D1A07B28B1012803D00228A5 +:10C9A00001D003281DD1607BD8B1C00819D162889D +:10C9B0004FF48040824202D82188814203D92079F5 +:10C9C00001280ED118E0207930B1012814D00228B6 +:10C9D00005D0032805D102E0202A0BD30CE0A029C2 +:10C9E0000AD22079042805D12088202802D3618822 +:10C9F000884201D9122515E0207986F83600607941 +:10CA000010B1012804D00DE0A94A0021204606E01B +:10CA100096F8420030B1A54A01213C32204606F08A +:10CA200014F905460120357170711821F1703070CC +:10CA30009FE410B59D4C217829B11A21BDE8104022 +:10CA40000E2000F07BBA01781F2902D91220207134 +:10CA500006E0002121710278411C104606F0A6F97B +:10CA6000012060711A21E170207010BD10B58F4C4B +:10CA7000217829B12021BDE810400E2000F05EBAD7 +:10CA800001781F2902D91220207106E000212171AE +:10CA90000278411C104606F078F9012060712021CF +:10CAA000E170207010BD2DE9FC41804C217829B146 +:10CAB000BDE8FC411B210E2000F040BA0127677140 +:10CAC0000C21217100780026012803D000286AD0AB +:10CAD00012205CE006F083F800287ED094F836003F +:10CAE000A0B1012812D0042810D008F053FA002871 +:10CAF00073D108F049FA18B108F046FA02286CD14F +:10CB0000002008F06CFEE0B3FFDF4AE008F03CFADA +:10CB1000002862D108F03EFA00285ED105F0F0FF4F +:10CB2000A0F57F41FF3958D1072101A800F048FF47 +:10CB30005F4905460C398860280000D1FFDF0321DA +:10CB400028460BF025FF284606F0FAF994F809115B +:10CB500094F8080108F021FA0146284608F049FA3D +:10CB600094F8070100901B2294F80631288811469A +:10CB700001F006F868B1042800D0FFDF28880721FB +:10CB800000E00EE000F05DFF00B1FFDF0720207144 +:10CB900023E0288805F018FF284608F020FE00B1A1 +:10CBA000FFDF267119E008F0EFF9032803D008F041 +:10CBB000F1F9032811D108F0EAF90546002008F040 +:10CBC0001FFD50B9267145B1288805F0FEFE288862 +:10CBD000072100F036FF00B1FFDF1B20E070277057 +:10CBE000BDE8FC812DE9F041304C0646207828B1A3 +:10CBF000BDE8F0412D210E2000F0A0B930880721BA +:10CC000000F00DFF05004FF0010720D095F8D1008E +:10CC100040B995F83C000F2801D0102802D195F8B2 +:10CC2000040150B10C2020710E20A0702D20E07066 +:10CC30003088E0806771277072E51022B11C05F121 +:10CC4000D2000EF001F985F8D1700020EBE7022048 +:10CC5000E9E770B5154C0546207828B1BDE870406D +:10CC60002E210E2000F06AB92888072100F0D7FE97 +:10CC7000022178B190F8D1202AB990F83C200F2AEF +:10CC800004D0102A02D00C20207104E080F8D110CA +:10CC90000020F9E721710E20A0702E20E070288876 +:10CCA000E080012060712070EDE500003808002070 +:10CCB000500000207CB5C54C0546207820B13721B6 +:10CCC0000E2000F03BF97CBD28886946FEF70FFD79 +:10CCD00038B102202071012060713721E17020708D +:10CCE0007CBD01987F22014680F8382080F83920E9 +:10CCF000002280F83A20A87801F8280FE8784870D8 +:10CD0000287988702271E6E71CB5B04C217821B1F2 +:10CD100013210E2000F012F91CBD00886946FEF7B1 +:10CD2000E6FC08B1022005E0019890F828100129DE +:10CD300002D00C20207106E0382100222271095C0B +:10CD400021720088E080012060711321E1700E21C2 +:10CD5000A17020701CBD2DE9F0419C4C0546207847 +:10CD600028B1BDE8F04135210E2000F0E7B8A878E1 +:10CD700008B1012803D1A888B0F5FA7F01D91220A3 +:10CD800020712888072100F04AFE0126A0B1002763 +:10CD900080F8C870A988A0F8CA1080F8A460A978A3 +:10CDA000012900D0002180F8C81090F8A50008B132 +:10CDB00008F014FE277101E0022020716671352011 +:10CDC000E0702670ACE42DE9F041804C05462078F7 +:10CDD00028B1BDE8F0413C210E2000F0AFB8288812 +:10CDE000072100F01CFE012358B382886D88C68895 +:10CDF000418803EB4207BD4217D342F210777E43CE +:10CE0000BF107943B6FBF1F1491E89B24FF4FA76AF +:10CE1000B14200D931468D4200D22946491C521CEC +:10CE2000B1FBF2F15143491E8AB290F8F01001B9FA +:10CE30000284E2800020207163713C20E070237046 +:10CE40006EE40220F7E770B5604C0546207828B103 +:10CE5000BDE8704033210E2000F070B808F094F85F +:10CE600008B10C2017E0297889B10A290FD01429BC +:10CE70000DD01E290BD0282909D0322907D04B29E3 +:10CE800005D0642903D0FF2901D0122003E02846F1 +:10CE900008F047FD00202071012060713321E1700E +:10CEA0002070F0E449490A781AB13F210E2000F0C1 +:10CEB00045B800220A710278454B4AB1012A0CD0CC +:10CEC00012200871012048713F22CA700870F4E4F2 +:10CED000D0F80100C3F80200F4E7D0F80100C3F86D +:10CEE0000600EFE770B5394C0546207828B1BDE85B +:10CEF00070403D210E2000F021B808F045F810B92F +:10CF000008F048F808B10C2003E0287805F05EFF2F +:10CF100000202071012060713D21E1702070B2E499 +:10CF200010B50178402907D22A4A52F8211019B1C8 +:10CF3000801C8847012010BD002010BD234A92F8B4 +:10CF40003130002B06D182F8320082F833100120F4 +:10CF500082F83100B1E430B5134606E0CC18D51A9A +:10CF600014F8014C5B1E4455DBB2002BF6D130BDEA +:10CF700090F8491041B990F8981029B190F89800AC +:10CF8000042801D0012098E4002096E4017840684C +:10CF900021B190F8490010B100208EE4E8E70120AB +:10CFA0008BE40A480021C0F8F81080F8C41084E42B +:10CFB0000178012909D1406890F8A510002904D012 +:10CFC000002180F8A51008F009BD76E4380800209B +:10CFD0003809002060B301003D3070470844C01D8F +:10CFE000424301F13D00104480B2704770B51C46C9 +:10CFF0000546A018049BC01D00FB03F204F13D0090 +:10D00000104486B2B14238BFFFDF1C2128460DF024 +:10D0100092FFA6F11C0080B22C752880B0F5004F5D +:10D0200088BFFFDF70BD008870472DE9F04F0E46C6 +:10D030008188044600F11C0AC088154620F400428D +:10D0400021F40043002721F4004820F400499A42CB +:10D0500008D100F4004001F4004188421CBF0020C8 +:10D06000BDE8F08FC14517D9207DA9EB0801091A49 +:10D07000C91F8D4227DCC11D0AEB08000144C91EEF +:10D0800071603581F7603782011D3160058047800E +:10D090000120A074BDE8F08F2088217DA0EB08005E +:10D0A000401AB0F1070B0ED4BBF11B0FB8BFFFDF66 +:10D0B0005D45D4BF28461FFA8BF0291A0A04120CCA +:10D0C00018BF4A4503DDA7740020BDE8F08F217D1D +:10D0D000CB1D0AEB08010B44DB1E7360308104F1A9 +:10D0E0001C03F36032820B1D336008804A800120EC +:10D0F000A074BDE8F08F2DE9F041044600F11C0258 +:10D10000808820F40043A07C002808BFBDE8F0819F +:10D11000D0180288438813448B423CBF0020BDE8EE +:10D12000F081002791429CBF0180478013D9891A62 +:10D130000D042D0C45800ED0A088261D20F4004043 +:10D14000854288BFFFDF30884FF4004121EA0000AC +:10D150002843308008E0217D0088CB1D184481B22F +:10D160002288201D00F09AFAA7740120BDE8F08102 +:10D1700030B4B0F802C08488034600F11C052CF4DA +:10D1800000402844A44503D10020D88130BC70471A +:10D19000B3F80AC00488A44509D34088ACEB040C5A +:10D1A000A0EB0C0084B20CEB0500C01E06E0A4EB63 +:10D1B0000C041D7DA4B2AC446044001DB1F800C055 +:10D1C000A44588BF0C80B3F80AC0BCF1000F0CBFA7 +:10D1D0004FF0010C4FF0000C82F800C00988D98193 +:10D1E00030BC70472DE9F041044600F11C01408835 +:10D1F00020F400404518E089002808BFBDE8F08110 +:10D200006189084480B2608129886A88114481421A +:10D2100038BFFFDF28886D88628941190027914255 +:10D2200018D175B16088A61C20F40040A84238BF10 +:10D23000FFDF30884FF4004121EA000028433080AE +:10D2400007E0217D2288CB1D184481B2A01C00F08C +:10D2500025FA6781E7810120BDE8F0812DE9F047DB +:10D260000189B0F802800027044600F11C0A4145FC +:10D2700018BF4FF4004938D021F400400AEB0001F8 +:10D280004E886EB1208904F1080520F40040B042B8 +:10D2900038BFFFDF288829EA0000304328801FE0DC +:10D2A000207D2389C21D088823F40045104421886D +:10D2B000284480B204F1080C88420AD2091A89B2C3 +:10D2C0001B3291422CBF03F4004129EA030004D22F +:10D2D00004E0401A80B229EA03010843ACF80000D8 +:10D2E000781C218987B24145C6D13846BDE8F08710 +:10D2F0002DE9F047B0F806800B46044600F11C010A +:10D30000B0F80890408828F4004C01EB0C058045EB +:10D3100004BF0020BDE8F087002A1CBF281D106054 +:10D3200023B1227D291D18460DF08EFD2F886D88B2 +:10D3300085B1E81987B2E088A61D20F40040A84214 +:10D3400038BFFFDF30884FF4004121EA0000284356 +:10D35000308007E0207D2288C31DD81981B2A01D2E +:10D3600000F09CF9C84504BFE08820813846BDE83C +:10D37000F0874188808881420CBF012000207047DF +:10D380004188C08888420CBF01200020704730B41B +:10D390004488828800F11C0324F4004C22F40041EC +:10D3A000634494421BD04289C48915191C885A8849 +:10D3B000A3189D4216D312B18A4210D212E0037D07 +:10D3C0000CF1070C1A196244008892B2801A80B2DC +:10D3D0002233984201D211B104E08A4202D130BC1A +:10D3E0000020704730BC012070472DE9F007858888 +:10D3F000C48800F11C06024625F4004C24F40049C0 +:10D4000025F4004A002024F4004306EB0C074FF0FB +:10D410000108D1450AD104F4004405F40045AC42AA +:10D4200004D01082BDE8F00700207047634506D99C +:10D43000147DA3EB0C031B1BDD1F002305E01488E8 +:10D44000157DA4EB0C04641BE51F002DE9DB94891A +:10D450005CB13C887F8847B1DB1BD0748B42E0DB3A +:10D4600090893044001BC01E12E02D1BD0748D42E9 +:10D4700006DB107D9389C01D60443344184406E0E8 +:10D480008B42CEDB82F8138090893044001BC01E93 +:10D490001182BDE8F00770472DE9F05F044600F106 +:10D4A0001C088088924620F4004B208A894608EBAD +:10D4B0000B0608B1484502D20020BDE8F09FA089C4 +:10D4C000002804BF00273D4605D0378875887919A4 +:10D4D000884218BFFFDFE07C50EA050101D078B335 +:10D4E00038E0A08950B1217D4044C91D5944084409 +:10D4F000B4F8151020F8031DE17D8170A18907EBB8 +:10D5000009004944A181308000257580207DBAF151 +:10D51000000F09D0C31D30882288184481B2201D15 +:10D5200000F0BCF8A5813AE0A189C01D58444144EF +:10D53000084430F8031DA4F815108078E0752EE03B +:10D54000FFE7A089B4F815104044C01B20F8031D64 +:10D55000E17D817005EB090085B2A089BAF1000F69 +:10D560004844A0813780758010D0A088261D20F403 +:10D570000040A84238BFFFDF30884FF4004121EA65 +:10D580000000284330800020A08108E0A0894044AA +:10D59000C01B30F8031DA4F815108078E07500203A +:10D5A0002082A0740120BDE8F09F10B4B0F802C042 +:10D5B000848800F11C022CF400431344A44504D0D9 +:10D5C000B0F80AC0BCF1000F02D010BC00207047B8 +:10D5D00003F1040CC1F800C0007D00F1070C0CEB56 +:10D5E0000300C01E486018880881CA605B880B82EF +:10D5F00020B9D01E48600B810020088210BC012099 +:10D60000704770B5044600F11C018288408820F400 +:10D6100000431944904205D06289002A04BFE28980 +:10D62000002A01D0002070BD0A884D8885B1A61C53 +:10D6300020F40040A84238BFFFDF30884FF400419B +:10D6400021EA0000284330800020E081012070BDE5 +:10D65000207DC31D981881B22288A01C00F01EF8FE +:10D66000F2E700218181C17401828174704782894F +:10D67000002A04BF00207047828800F11C0322F4B6 +:10D6800000421A44B2F800C0BCF1000F1DBF037D78 +:10D69000121D1A44DA1E4A608089704710B4B0F82F +:10D6A00000C02CF40044214489B24FF4004491425C +:10D6B0000AD2521A92B21B339A422CBF0CF4004287 +:10D6C00024EA0C0104D204E0891A89B224EA0C028B +:10D6D0001143018010BC70472DE9F04188464FF698 +:10D6E000FC7102F103021E46040002EA010509D0A2 +:10D6F0000027E01C20F00300A04200D0FFDF201D27 +:10D7000001210CE00127F4E7024628442FB9B14279 +:10D7100001D2034600E000231360491CC9B2B142A4 +:10D72000F2D9011BC8F80010002F04D10EB1201D42 +:10D7300000E000202060BDE8F08102460020116872 +:10D74000002902D0084609681160704702680A6023 +:10D75000016070474FF6FC73C91C1940101A001F76 +:10D7600090FBF1F0C0B270474FF6FC73C91C194032 +:10D77000001D01FB02007047F8B5D24D04460E466D +:10D78000A878A04200D8FFDF05EB8607B86A50F8FA +:10D79000240000B1FFDFB868FFF7CFFF05000DD010 +:10D7A000B86A062E40F824500AD0082E00D3FFDFB6 +:10D7B000C548294650F82620204690472846F8BDFF +:10D7C000C048C24B7A30A0F12E0200902946204674 +:10D7D00009F087F8F2E72DE9F84F8046DDF8289048 +:10D7E0001E4603EB090093468A46C4B25FEA080767 +:10D7F00007D00025FF2800D9FFDFBAF1000F03D1C1 +:10D8000001E00125F6E7FFDF08F1030020F0030146 +:10D81000414500D0FFDFCB4500D9FFDF65B9A94AFC +:10D8200000204C324FF6FF7110705180A74A1070E3 +:10D83000A44A7A3210705180A24880F800B0467035 +:10D840008470C4700471447180F80690DFF878B277 +:10D85000C67100260BF1400B8146FF1C27F0030028 +:10D860000746002D02D109EB860188603BF816209F +:10D8700019F8063001D04FF000006946FFF72CFF81 +:10D880000098761CF6B20744082EE6D3FF1C27F05A +:10D8900003002346064675B1002002226946FFF7C1 +:10D8A0001BFF00983118002003464E46C91C21F08A +:10D8B00003021DB110E0C9F84800EEE706EB80074F +:10D8C0000021BA6206E000BFD7F828C04CF821302A +:10D8D000491CC9B2A142F7D3401CC0B202EB84017B +:10D8E0000828E3D3A1EB0800AAF800000020BDE857 +:10D8F000F88F10B5044604F073F808B1102010BD7D +:10D900002078704A618802EB800092780EE0836A8A +:10D9100053F8213043B14A1C6280A180806A50F8DC +:10D920002100A060002010BD491C89B28A42EED8B7 +:10D930006180052010BD70B505460C46084604F010 +:10D940004FF808B1102070BD082D01D3072070BD1D +:10D9500025700020608070BD0EB56946FFF7EBFFB3 +:10D9600000B1FFDF6846FFF7C4FF08B100200EBD1D +:10D9700001200EBD10B50446082800D3FFDF514832 +:10D98000005D10BD3EB5054600246946FFF7D3FF94 +:10D9900018B1FFDF01E0641CE4B26846FFF7A9FF9D +:10D9A0000028F8D02846FFF7E5FF001BC0B23EBDB7 +:10D9B00044498978814201D9C0B27047FF2070473D +:10D9C0002DE9F0410C460546062901D0072C10D15F +:10D9D0003C4FB86CFFF7B1FE02004FF6FF7604D063 +:10D9E0000221B86CFFF7B6FE00E030462880B04256 +:10D9F00002D10020BDE8F0812146FFF7BDFE040002 +:10DA000002D1288800F050F82046F3E7A0F57F42C5 +:10DA1000FF3A01D0082901D300207047ACE6A0F5F9 +:10DA20007F42FF3A0BD0082909D2264A93788342D5 +:10DA300005D902EB8101896A51F820007047002066 +:10DA400070472DE9F04104460D46A4F57F4143F2AD +:10DA50000200FF39CED0082D01D30720CAE71949AB +:10DA60004FF000088A78A242C4D901EB850721460D +:10DA7000BA6A52F82460002EBCD0134A08462032FD +:10DA8000314652F825209047B96A062D41F8248086 +:10DA900001D0072D02D1204600F006F83146B868C3 +:10DAA000FFF754FE0020A5E710B5064CC2B20221D4 +:10DAB000A06CFFF759FE0146A06CBDE81040FFF7CF +:10DAC00045BE00004809002060B401005600002057 +:10DAD0000146A048002200680260037A00EB830040 +:10DAE00040F80C2F8180114600F025B92DE9F05F38 +:10DAF0009846DDF830B0DDF828A0154689460400C8 +:10DB00004FF0000625D00027E01C20F00300A042C3 +:10DB100000D0FFDF7DB30120FFF75EFA00FB056256 +:10DB20000AEBCB00104486B20120FFF755FA00FB48 +:10DB300005620B9908EBC100104405EB450100EBB1 +:10DB40004100143000EB850000EB850086B217B170 +:10DB500011E00127D8E7A6EB85000C3887B27D4895 +:10DB6000A9000460257204F10C0060600DF005FA54 +:10DB70003846FFF7ADFFA9F800600020BDE8F09F30 +:10DB80002DE9FF4F734C814681B020689A468B4641 +:10DB900000B9FFDF2068027A4A4503D9426852F88B +:10DBA000291021B143F2020005B0BDE8F08F0068F2 +:10DBB00000B9FFDF01210E9A0398FFF70FFAC61C88 +:10DBC0004FF6FC752E40584601215246FFF706FAE3 +:10DBD000C01C00EA050808EB0600001D85B25D4880 +:10DBE00000270068046801E027460446206838B131 +:10DBF000A188A942F8D13946204600F0A4F813E0E4 +:10DC000005F10800A18880B2814229D33946204617 +:10DC100000F099F8A0880022411B60190260818001 +:10DC2000394600F088F8A580A08860802680251DF0 +:10DC30000E9F0123039A314628460097FFF7D6F935 +:10DC40002088414628445A460123CDF800A0FFF71A +:10DC5000CDF9404800684168002041F82940A3E719 +:10DC60000420A1E770B53B4C0546206800B9FFDFF2 +:10DC70002068017AA94210D9426852F8250060B1A3 +:10DC80004188002342F8253003608180194600F066 +:10DC900052F8216800200A7A08E043F2020070BDC1 +:10DCA0004B6853F820306BB9401CC0B28242F7D8A1 +:10DCB000002002E08A88104480B209680029F9D166 +:10DCC000FFF706FF002070BD70B5224D28680028C0 +:10DCD0000AD0002404E02046FFF7C4FF641CE4B22D +:10DCE0002868007AA042F6D870BD70B5194E054676 +:10DCF0000024306800B9FFDF3068017AA94204D9F6 +:10DD0000406850F8250000B1041D204670BD70B574 +:10DD1000104E05460024306800B9FFDF3068017AF4 +:10DD2000A94206D9406850F8251011B131F8040B0A +:10DD30004418204670BD19B10A6802600860704737 +:10DD400004490968F8E7006809B1086070470149AB +:10DD50000968FAE75C00002070B5044600780E46BA +:10DD600001281AD0072802D00C281AD115E0A06883 +:10DD7000216905780B2D0CD0052003F0CAFD052D77 +:10DD80000FD0782300220520D4F8101003F024FDD2 +:10DD900007E0782300220620F8E70520216903F038 +:10DDA000B8FD31462046BDE8704001F0BBB910B562 +:10DDB00000F13902C3799478411D64F003042340D3 +:10DDC000C371DB070DD04B79547923404B710B792C +:10DDD000127913400B718278C9788A4200D9817018 +:10DDE00010BD00224A710A71F5E74178012900D07F +:10DDF0000C21017070472DE9F74F86B000208C6927 +:10DE00008DF800000878012617460D464FF0070BE5 +:10DE10004FF011094FF00A0A2A2878D2DFE810F0F3 +:10DE20002A00140357036C03A603B503D103FE03B2 +:10DE300015043F0468048704A004DD04EE04110502 +:10DE4000190539055E058905AD05D605F305FD05FE +:10DE50001F063006420674069606E8061F072D07C1 +:10DE6000580778078C079D07D6070E083A08F6076B +:10DE7000FA07000814B120781D2829D0D5F80880A9 +:10DE80005FEA080043D001208DF80000686A049022 +:10DE900003208DF804008DF805A0286A0290A88858 +:10DEA0000028EFD098F8001091B10F2910D27DD240 +:10DEB000DFE801F07C144BDCFEFDFCFBFAF9F8080E +:10DEC0009EF7F600022822D124B120780C2801D038 +:10DED000002675E302208DF80000B1E10620696A92 +:10DEE00003F017FDA8880728EDD1204601F015F9A9 +:10DEF000022809D0204601F010F9032808D920464D +:10DF000001F00BF9072803D20120207005E010E290 +:10DF1000002CB7D020780128D5D198F80400C11F73 +:10DF20000A2902D385F81CA08DE2A070D8F8001051 +:10DF3000A163B8F80410A18798F8060084F83E00A1 +:10DF4000012028700320207046E00728BBD1002C58 +:10DF500098D020780D28B6D198F8031094F83B207B +:10DF6000C1F3C000C2F3C002104201D00E2000E095 +:10DF70000F20890707D198F805100142D2D198F8EF +:10DF800006100142CED194F83D2098F8051020EA01 +:10DF900002021142C6D194F83E2098F80610904330 +:10DFA0000142BFD198F80400C11F00E049E20A29EC +:10DFB000B8D2617F814201D90620C9E3D8F80010A8 +:10DFC0006160B8F80410218198F80600A072012061 +:10DFD00028700E20207003208DF80000686A0490DD +:10DFE00004F139000190601D029017300390DBE0CE +:10DFF000B5F806B041288FD1204601F08EF80428EC +:10E0000002D1E078C00704D1204601F086F80F283D +:10E010009CD1CBF14006324608F10101606A0CF058 +:10E0200013FF606A5A463044E9680CF00DFF0E2079 +:10E030008DF80000686A0490606A019000216846CB +:10E04000FFF78AFE2078042808D0A07F48B1012875 +:10E0500007D0032808D0102020709CE005202070F5 +:10E060000FE284F8009033E71220F5E71128C2D1BF +:10E07000204601F052F8042802D1E078C00719D0F8 +:10E08000204601F04AF8062805D1E078C00711D1F2 +:10E09000A07F02280ED0204601F03FF8112808E0AA +:10E0A000B3E083E09BE172E152E10AE1E9E0CFE015 +:10E0B00017E0A0D1102208F1010104F148000CF092 +:10E0C000C3FE6078012809D012202070E078C007D4 +:10E0D00065D0A07F90B301285DD060E084F800B0E7 +:10E0E00059E0112887D1204601F017F8082804D0FC +:10E0F000204601F012F813288AD12869D0B1686946 +:10E10000C0B104F17800102208F1010106460CF0BC +:10E110009BFE2078082812D014202070E078C007D9 +:10E120000FD0A07F022818D06178022912D00328CE +:10E1300031D034E000208DF80000FAE02BE0092017 +:10E14000EBE70B202870296902204870206CC1E998 +:10E1500001069AE208B1012879D10B2028702969BB +:10E1600008204870606A4860206AC1E9020680E2BF +:10E17000206CE2780068C2F34402521ED04000F0E6 +:10E18000010040F0800000E000200874E06A48616F +:10E1900084E20646F0E3042028700520F0E185F8CB +:10E1A00000A08DF800A0BFE33946FFE31128C4D1D9 +:10E1B000204600F0B2FF0A2802D1E078C00704D15F +:10E1C000204600F0AAFF1528B7D1102208F101015E +:10E1D00004F148000CF038FE20780A2810D01620F0 +:10E1E000207012202870296904F1580081F801A0DC +:10E1F0004860203088601038C860206C0861B5E342 +:10E200000B202070E7E22870D9E1022895D1204642 +:10E2100000F083FF042804D3204600F07EFF082886 +:10E2200009D3204600F079FF0E2886D3204600F05F +:10E2300074FF12287DD2A07F0228B8D18DF80090FB +:10E24000686A049098F801008DF80400FEE36DE21E +:10E250000228ACD1204600F060FF002869D020469B +:10E2600000F05BFF0128F9D0204600F056FF0C2893 +:10E27000F4D005208DF8040098F801008DF8050011 +:10E280005BE71128FCD1002CFAD020781728F7D1B1 +:10E290006178E06A022912D05FF0000101EB4101D0 +:10E2A000182606EBC1011022405808F101010CF0BC +:10E2B000CBFD0520696A00F023FF267008E60121E6 +:10E2C000ECE70B28DCD1002CDAD020781828D7D145 +:10E2D0006178E06A02292DD05FF0000101EB410175 +:10E2E000102202EBC1014158B8F8010008806078A3 +:10E2F000E16A022821D0002000EB4002142000EB4C +:10E30000C2000958404650F8032F0A604068486030 +:10E310000520696A00F0F4FE6078022810D04FF002 +:10E3200000002044407A20F001010CD14FF00100A0 +:10E330000BE0D9E14FF00101D0E74FF00100DBE73E +:10E340004FF00100EDE74FF000002044417285E3FB +:10E35000112895D1002C93D02078192890D161787C +:10E36000E06A022911D0002101EB41011C2202EBDD +:10E37000C1011022405808F101010CF065FD052093 +:10E38000696A00F0BDFE1A20EEE00121ECE70828E2 +:10E3900098D1002C98D020781A2893D1E16A98F867 +:10E3A00001000870E16AD8F8022041F8012FB8F89E +:10E3B000060088800520696A00F0A2FE60780228C5 +:10E3C00007D04FF000002044407A20F002002CD00B +:10E3D00034E04FF00100F6E7214448723EE3112893 +:10E3E000B7D1002CB7D020781B28B2D16178E06A71 +:10E3F00002291DD05FF0000101EB4101202202EB58 +:10E40000C1011022405808F101010CF01DFD05204A +:10E41000696A00F075FE607802280CD04FF00000A9 +:10E420002044407A20F0040008D14FF00101D3E7E6 +:10E430004FF00101E0E74FF00100F1E74FF000017C +:10E44000CAE785F81CB0F8E33878012886D11C2289 +:10E4500004F11C0079680CF03CFDE079C10894F8E7 +:10E460003B0001EAD001E07861F30000E070217F19 +:10E4700009B1297738E1217803290AD0C0073FF490 +:10E48000ECAD032028708DF800A0686A049041204C +:10E49000ABE3607FA17888423FF68EAD02262671FD +:10E4A000E179204621F0E001E171617A21F0F0018B +:10E4B0006172A17A21F0F001A172FFF778FC2E7051 +:10E4C0008DF800A0686A04908DF804B06CE6387886 +:10E4D0001228CFD18DF800B0696A04919168029139 +:10E4E000ADF804B008466168016021898180A17A95 +:10E4F000817104202070A9E23878B7F806801228CC +:10E50000B8D18DF800B0686A0490381D01AB07C817 +:10E5100083E807004120ADF8040008460C2100F80C +:10E52000011BC8F140021646216A0CF08DFC206ADE +:10E5300042468119F8680CF087FC00216846FFF715 +:10E540000BFCE07820F03E00801CE070207805286D +:10E5500001D00F2008E0A07F00283FF4BFAD0128C4 +:10E56000FBD0032870D108202070B1E4387803284C +:10E57000AFD178680168A1664068E0660520287020 +:10E580008DF80000686A04900EE638780328A0D160 +:10E5900078680168216740686067206C68B9A07F6F +:10E5A00028B1012803D0062028700420E8E785F868 +:10E5B00000B0FD482064606401E085F800B00326E7 +:10E5C000EFE33878022884D13879E0BBA07F0228B5 +:10E5D0000BD00328F1D1607801280BD0A07994F8F2 +:10E5E0003A1001280AD0F0480BE0B86800287BD028 +:10E5F000206411E0A17994F83A00F2E7B8680028A5 +:10E60000F5D02064E078C00701D0012901D0E648A8 +:10E6100002E0F8680028EAD06064CEE78DF800A038 +:10E62000696A0491E1785046C90709D061780229E6 +:10E6300003D1A17F29B1012903D0A17F032900D0F3 +:10E640000820287047E102E1C0E0387812288FD115 +:10E65000B868286209202870E0782969C0070DD0C1 +:10E6600008204870206A4860606A886004F1680089 +:10E67000C860A07F02287FF487AD79E5022048704A +:10E68000206C486004F16800886004F13800C860BC +:10E69000201D0861206B4861606B88612DE2E17884 +:10E6A0003878C90701D0072100E00B2188428AD1C0 +:10E6B0002078072819D084F8009000BF8DF800B0AA +:10E6C000686A0490286A0290ADF80490032100F86B +:10E6D000011B516810220CF0B7FB00216846FFF7C0 +:10E6E0003BFB00202862BEE44AE208202070E5E7F8 +:10E6F00038781228ABD18DF800B0686A0490906821 +:10E700000290ADF80490042100F8011B102204F1DE +:10E7100068010CF099FB00216846FFF71DFB20788B +:10E72000092801D013201FE784F800A016E0E17843 +:10E730003878C90701D0072100E00B21884286D133 +:10E74000102204F1480079680CF052FB10B104204B +:10E750002877AFE3207809283FF4BFAC0C2052E5BE +:10E76000E078C10737D0A17F012902D002291BD050 +:10E770002EE00D20287029690B2048706078012850 +:10E7800009D0206A4860606A886004F16800C86047 +:10E7900010300861FAE4606A4860206A886004F119 +:10E7A0007800C8601038F4E7C0F3440114290FD290 +:10E7B0004FF0006101EBB0104FEAB060E07060789C +:10E7C000012803D01020207004205FE10620CBE652 +:10E7D0006078012887D00E2015E538780A2889D17D +:10E7E00085F800A010208DF80000686A0490506839 +:10E7F000019000216846FFF7AFFAE9E7E078C0072B +:10E800000AD0A07F012803D10F20287004203FE107 +:10E81000102028700F203BE1152028702969032063 +:10E820004870206C48606078012805D004F17800B9 +:10E8300088601038C86060E104F1680088601030BA +:10E84000F8E738780228CAD138790028E0D028774C +:10E850002EE338781428FBD185F800902969092027 +:10E86000487078684860607801280DD004F168002D +:10E8700088601030C860206B0861606B486104F1EB +:10E8800058008861A06A22E004F17800886010389E +:10E89000F0E738780828DBD16078012801D0132010 +:10E8A00041E2A178A06A0844C1F110010CF043FBD9 +:10E8B00012202870296904F1580081F801A04860ED +:10E8C000203088601038C860206C086147E0C8615B +:10E8D000E06A086211E18DF80490DDE038780928DB +:10E8E000B6D1102204F1480079680CF081FA08B121 +:10E8F0000B202DE720780B2812D02046FFF757FA7F +:10E90000A178A06A0844C1F110010CF014FB162094 +:10E91000287008208DF80000686A049000206DE0DF +:10E92000132028708DF800A0686A04908DF8049078 +:10E930003AE4387812288BD1B868286214202870FD +:10E94000296904F1580081F801A0486010308860FE +:10E950001030C860606C08616078012806D004F14E +:10E9600039004861206B8861606BB0E7601D4861C9 +:10E97000606B8861206BAAE789E2387809288AD120 +:10E980008DF800B0686A0490286A0290ADF804908F +:10E990000D2100F8011B102279680CF055FA0021B6 +:10E9A0006846FFF7D9F902E07EB5010075E0002066 +:10E9B00028626178012901D01520D5E5162129703A +:10E9C00008218DF80010696A049117E038780C2846 +:10E9D00086D1162028706078022802D12046FFF7E1 +:10E9E000E6F9A17878680844C1F110010CF0A3FAA7 +:10E9F00008208DF80000686A049078680190A0787B +:10EA00008DF8080062E53878102894D1E079C007C5 +:10EA100079D01720287009203AE0387811288AD157 +:10EA20001422391D04F11C000CF053FAE16A208D08 +:10EA3000A1F80900E16AA078C871E179E26A01F001 +:10EA400003011172E16A627A0A7300E049E2E16A45 +:10EA5000A07A81F824006078012876D0B4E160784B +:10EA6000022801D0012000E000202044407AC007A5 +:10EA700004D0E078C00701D1192054E11E206EE6D1 +:10EA8000387812287CD1B86828621A2028700520AE +:10EA90008DF80000686A049011466846FFF75CF93B +:10EAA000FFF777BB387803286AD16078E16A0228DB +:10EAB00001D0012000E0002000EB4002142000EB18 +:10EAC000C20289587A6813680B6052684A601B2139 +:10EAD0002970D5E9041206234B70636A4B6066788F +:10EAE000E36A022E01D0012600E0002606EB46066E +:10EAF00000EBC6001858C1E90202686A486206982D +:10EB000000F027FBCCE788E138780F2838D160780F +:10EB1000E26A022801D0012000E0002000EB400062 +:10EB2000102101EBC00002231058093279680AF065 +:10EB300077FC1C202870296905204870206A4860ED +:10EB4000E06A09308860FA4874E65BE138780E289C +:10EB500016D16178E06A022901D0012100E000218C +:10EB600001EB4101182606EBC101A27840587968F3 +:10EB70000CF06AF96178E06A022902D0012101E013 +:10EB8000B8E0002101EB410106EBC1014158A0783A +:10EB90000A18C0F1100110460CF0CDF98DF800B044 +:10EBA000686A0490286A0290ADF80490062101700A +:10EBB0006278E16A022A01D0012200E0002202EB21 +:10EBC000420206EBC202401C895810220CF03CF9AC +:10EBD00000216846FFF7C0F8002028621D20287039 +:10EBE0008DF800A0686A04900B208DF804006DE495 +:10EBF000387812287ED18DF800B0686A0490906849 +:10EC000002900B20ADF80400029880F800B0627802 +:10EC1000E16A022A01D0012200E0002202EB420256 +:10EC2000102303EBC20289580988A0F8011061780B +:10EC3000E26A022902D0012101E03BE1002101EB5F +:10EC40004103142101EBC30151580A6840F8032F16 +:10EC50004968416000216846FFF77EF80EE760785A +:10EC6000022801D0012000E000202044407A8007E3 +:10EC700001D51F2057E0212071E53878122839D1BD +:10EC80008DF800B0686A0490B8680290ADF80490FE +:10EC9000082606706278E16A022A01D0012200E0AB +:10ECA000002202EB42021C2303EBC202401C8958E3 +:10ECB00010220CF0C9F800216846FFF74DF820201B +:10ECC00028708DF800A0686A04908DF804605BE4F9 +:10ECD000387812280ED18DF800B0686A04909068D8 +:10ECE00002900820ADF80400029809210170E16942 +:10ECF000097800E093E04170E16951F8012FC0F814 +:10ED000002208988C18000216846FFF725F8B2E714 +:10ED10006078022801D0012100E000212144497AD5 +:10ED2000490706D5222028708DF800A0686A049053 +:10ED3000D1E5012848D067E0387812286FD1B8684B +:10ED4000286223202870296905204870206A4860BD +:10ED5000E06A0930886077486CE538780E285ED123 +:10ED60006178E06A022901D0012100E0002101EB75 +:10ED70004101202606EBC1014058516810220CF0D9 +:10ED800063F88DF800B0686A0490286A0290ADF8C4 +:10ED9000049080F800A06278E16A022A02D0012281 +:10EDA00001E0A4E0002202EB420206EBC202401C9A +:10EDB000895810220CF048F800216846FEF7CCFF75 +:10EDC000002028626078B4E72420C8E46078022834 +:10EDD0000BD000202044407AC10702D0E178C90757 +:10EDE00005D0810705D519209DE40120F2E7172001 +:10EDF00099E4400701D51B2095E41C202070607821 +:10EE0000012801D01820AAE42720A8E4282028708F +:10EE10000B203DE6387813284AD129209FE40CE0E6 +:10EE20002078012844D00C2842D02046FEF7DDFF90 +:10EE30000C208DF80000686A049039E038784FF0B3 +:10EE40002608122805D013201070032685F80080AC +:10EE50004DE08DF800B0686A0490B8680290022016 +:10EE6000ADF80400029805210170297F417000214E +:10EE70006846FEF771FF0B208DF80000686A049069 +:10EE800039466846FEF768FF064685F80080012E81 +:10EE90000ED02CE001208DF80000686A0490042058 +:10EEA0008DF80400287F8DF805000020287712E0F7 +:10EEB000287F80B11D202070252028708DF800A0AB +:10EEC000686A049002208DF8040039466846FEF70F +:10EED00043FF06460BE00CB1FE2020709DF80000B9 +:10EEE00028B100216846FEF737FFFEF7F1BF09B0F1 +:10EEF0003046BDE8F08F2DE9F04F0C4601274E69F2 +:10EF0000097885B09046BA464FF00209072021B132 +:10EF100001294FD0022920D1C9E0217901290BD044 +:10EF2000022916D0032911D0042916D11CE00000B3 +:10EF300076B50100B0B40100707801280CD106202C +:10EF4000616A02F0BFFC002807D11AE01D20307072 +:10EF500017E07178022901D0052796E031780C2955 +:10EF600027D18DF804000EE03078011F042902D368 +:10EF70000E3803281DD2B07F02281AD1208902281A +:10EF800017D38DF8049084F800A020899DF8041010 +:10EF9000884203D20A208DF800003FE01221083495 +:10EFA00088F8001094E80E00C8E901120327C8F899 +:10EFB0000C306AE098F80010122966D18DF8000034 +:10EFC000616A0491D8F80850029521794FF00B0B33 +:10EFD000012906D0022929D0032911D0042954D1AE +:10EFE0005AE0ADF8049085F800B0207E4F4600F05E +:10EFF0001F00687000216846FEF7AEFE377043E0E0 +:10F00000ADF8049005202870207E68704E460021DF +:10F010006846FEF7A1FE26708DF800B0606A049085 +:10F0200041466846FEF798FE07462EE0ADF804001C +:10F0300085F800A0207F6870607F00F00100A87054 +:10F04000A07F00F01F00E870E17F2971C0071FD08A +:10F0500094F8200000F00F00687194F8210000F08F +:10F060000F00A87100216846FEF776FE2868B0639D +:10F07000A888B087A87986F83E00A06940787077A4 +:10F080002879B0700D2030700027384605B030E781 +:10F090000020A8716871E5E7ADF804900E20287093 +:10F0A000207E687000216846FEF756FEECE7FE20E1 +:10F0B00030708DF800A0606A049004208DF8040080 +:10F0C000207E8DF80500EDE700B50023012285B014 +:10F0D00005280FD006280BD102208DF800200491BE +:10F0E0008DF804008DF8053000216846FEF734FEE7 +:10F0F00005B000BD8DF8002004918DF80420F1E7E3 +:10F1000070B50C46054602F004FC21462846BDE8D1 +:10F1100070407823002202F05FBB08B1007870478E +:10F120000C20704770B50C0005784FF000010CD032 +:10F1300021702146F4F71EF973482178405D88421A +:10F1400001D1032070BD022070BDF4F713F9002037 +:10F1500070BD027B032A05D000220A704B780C2B6D +:10F1600002D003E0042070470A770A62027B930012 +:10F17000521C0273C15003207047F0B585B00F4692 +:10F1800005460124287B05EB800050F8046C70785C +:10F19000411E0D290AD25C493A46123101EB80002A +:10F1A000314650F8043C2846984704460CB1012CDF +:10F1B00011D1287B401E10F0FF00287301D00324DA +:10F1C000E0E70D208DF80000706A049000210196A0 +:10F1D0006846FFF7A7FF032CD4D005B02046F0BD4A +:10F1E00070B515460A46044629461046FFF7C5FF86 +:10F1F000064674B12078FE280BD1207E30B1002065 +:10F200002870294604F10C00FFF7B7FF2046FEF7EF +:10F21000ECFD304670BD704770B50D460446882140 +:10F220000BF0ABFE012D03D0022D03D0052070BDE5 +:10F23000012000E0022060702046FEF7D6FD00208D +:10F2400070BD28B1027E1AB10A4600F10C01C7E771 +:10F250000120704730B5044687B00D46062002F005 +:10F2600058FB2946052002F054FB2078FE2806D0E2 +:10F2700000208DF8000069462046FFF7E2FF07B046 +:10F2800030BD7FB50E4600218DF80C1041780C2959 +:10F2900003D00D2903D0002405E0846900E044690F +:10F2A0000CB1217E91B16D4601462846FFF751FF12 +:10F2B000032809D1324629462046FFF791FF9DF8E1 +:10F2C0000C10002900D0042004B070BD04F10C051E +:10F2D000EAE710B590B00C4607900B480521801E58 +:10F2E00008900A488DF8191009900F92694606A8EF +:10F2F000FFF7C7FF002805D11022204601990BF027 +:10F30000A3FD002010B010BDB6B4010076B5010019 +:10F3100070B50D46040011D085B1210128460BF0CF +:10F320000AFE10224E4928460BF08EFD4C48012162 +:10F330000838018044804560002070BD012070BD08 +:10F3400070B5474E00240546083E10E07068AA7B61 +:10F3500000EB0410817B914208D1C17BEA7B914292 +:10F3600004D10C2229460BF043FD30B1641C3088D7 +:10F370008442EBDB4FF0FF3070BD204670BD70B5AE +:10F380000D46060006D02DB1FFF7DAFF002803DB9B +:10F39000401C14E0102070BD314C083C208862886D +:10F3A000411C914201D9042070BD6168102201EB1B +:10F3B000001031460BF048FD2088401C208028704A +:10F3C000002070BD70B514460D0018D0BCB10021EE +:10F3D000A170022802D0102811D105E0288870B150 +:10F3E0000121A170108008E02846FFF7A9FF00283E +:10F3F00005DB401CA070A8892080002070BD012082 +:10F4000070BD70B5054614460E000BD0002030705C +:10F41000A878012808D005D91149A1F108010A8866 +:10F4200090420AD9012070BD24B128782070288824 +:10F43000000A5070022008700FE064B14968102281 +:10F4400001EB0011204610390BF0FEFC28782073E8 +:10F450002888000A607310203070002070BD000002 +:10F46000680000202DE9F041FE4C207EE17D8842BD +:10F4700008BFBDE8F0810126FB4D0027E07D215C3F +:10F4800001EB810205EB8200037C052B10D0037C8D +:10F49000062B1BD0037C072B27D0437C012B18BFE6 +:10F4A000FFDF30D0207EE17D8842E7D1BDE8F081EA +:10F4B0000674E07D16281ABFE07D401C0020E07530 +:10F4C000481CC0B255F8222002210CE00674E07DF1 +:10F4D00016281ABFE07D401C0020E075481C55F836 +:10F4E0002220C0B203219047DCE70674E07D162895 +:10F4F0001ABFE07D401C0020E075481CC0B255F8E2 +:10F5000022200821EFE74774E07D16280EBF002077 +:10F51000E07D401CE075481CC0B255F82220072150 +:10F52000E1E770B5D14E00240C2086F82900A6F53D +:10F530003B70254680F8CD4180F8CC4100F5F47051 +:10F540000476C47506F12C000AF0C8FDA6F58E708D +:10F55000057586F82B50601EB06086F8255086F839 +:10F56000225086F8235086F8245086F82150C0484F +:10F5700005704570A6F1E80004EB840100EB810101 +:10F580000D74611CCCB20B2CF6D30120F9F728FBCB +:10F590000020F9F725FB012086F82600F9F7D4FFB3 +:10F5A000B448F9F7E0FFB44C2070B448F9F7DBFF3A +:10F5B0006070BDE87040F9F7A7BA10B5F9F7D2FA54 +:10F5C000AD4C2078F9F7E8FF6078F9F7E5FFA74C34 +:10F5D00094F82800002808BF10BDF9F7CCFC0020E3 +:10F5E00084F8280010BD0B20704770B5F9F79DFB1B +:10F5F0009E4C054694F8260000281CBFFFDF70BD16 +:10F6000094F82B00002808BFFFDF6FF07F4260698D +:10F610000026291AB1F5800F24BF431BB3F5800FD4 +:10F620000DD38A4203D2101A2844411C07E09A42A3 +:10F6300028BFFFDF05D2511B0844401C414200296E +:10F6400000DBFFDF012584F8265084F82B6094F856 +:10F6500029100420844A01EB810102EB8101087426 +:10F66000A068B0F1FF3F04D0A81EA0600120F9F708 +:10F67000B7FA0020F9F7B4FAF9F798FA0AF0C0FEE1 +:10F68000F9F7DCFB7E48066006604FF0E0214FF49E +:10F690000040C1F88002F3F790FC7548007802281A +:10F6A00004D0032805D194F8230010B184F8225027 +:10F6B00001E084F82260BDE87040F9F7A3BB03467F +:10F6C00069490B2000EB800201EB820212F8042C46 +:10F6D00022B1401E10F0FF00F4D1704700EB800211 +:10F6E00001EB8201012241F8143C01F8042C70471F +:10F6F000012804D0032808BF002926D000E021B348 +:10F700005A4B4FF0000C83F821C0594A00289070E2 +:10F7100014BF022882F803C00BD0072915D2DFE8F6 +:10F7200001F01404060C0E1012001B2000E03A2019 +:10F73000D070012083F8210070475820F8E7772027 +:10F74000F6E79620F4E7B520F2E700207047484836 +:10F7500010B54078F9F77BFB80B210BD421E10B5A2 +:10F76000414900EB800001EB80040A2A02D814F81A +:10F77000040C00B9FFDF14F8040C012818BFFFDFE8 +:10F78000002004F8040C10BD70B53E4C94F8CD0177 +:10F7900094F8CC1188420CBF01250025F9F7C5FA71 +:10F7A000F9F755FB94F8CD1194F8CC2191420CBF98 +:10F7B00001210021A942E9D170BD2DE9F05F804609 +:10F7C0004B1E1746DCB2284804EB840200EB82058E +:10F7D0002E1D287CDFF88C9007282DD199F8170072 +:10F7E000002299F818C0844524D000BF19F800C041 +:10F7F000A44508BF012200D04AB116280CBF4FF023 +:10F80000000C00F1010C19F80CC009F800C0162812 +:10F810000CBF0020401CC0B299F818C08445E5D147 +:10F8200042B199F818204846002A0EBF1622027EDF +:10F83000521E0276012028740A2B10D80A4801EBC8 +:10F84000810100EB810010F8040C40B1287C0128F4 +:10F8500006D0287C012802D0B87A012816D0FFDF14 +:10F86000B87A11E0BC0B0020D80B0020C00C00209F +:10F870007A000020851601007800002065F4000061 +:10F8800000F50040D409002001284AD1FE49287C17 +:10F89000022816D099F8180016284AD099F81800AE +:10F8A00099F81710401C884200D1FFDF01206874CE +:10F8B00099F8180009F8004099F8180016283DD06A +:10F8C0003EE0DFF8C8C39CF829000246A04207D0FA +:10F8D000024600EB820001EB8000807CA042F7D161 +:10F8E0009CF8293083420CD19CF8292002EB82023B +:10F8F00001EB8202927C8CF8292001228CF82A20CC +:10F9000009E000EB800301EB830302EB820201EBD1 +:10F9100082029B7C937400EB800001EB80000C2240 +:10F920008274387A062825D2DFE800F012211E1BE7 +:10F93000181599F817000028B8D1B6E7002002E0A2 +:10F9400099F81800401C89F818000020BDE8F09FC5 +:10F950004FF0000A11E04FF0B40A0EE04FF0730AC6 +:10F960000BE04FF0320A08E04FF00A0A05E04FF0D2 +:10F97000060A02E0FFDF4FF0000A3868A0EB0A0039 +:10F980003060397A00290CBF04210221401A20F08E +:10F990007F423260D7E90001084420F07F40706068 +:10F9A000B87A022818BF387B7ED1387A00280CBF7D +:10F9B0000420022000EB0A037868591D00EB010BBC +:10F9C000B3484078504503D9B04991F8231011B19C +:10F9D0000BF1060003E0A0EB0A005844801DAB4980 +:10F9E00091F829C0BCF10C0F24D08E4691F8291053 +:10F9F00001EB810CA44901EB8C0CDCF804C06245DE +:10FA000018D0DFF890C29EF8292002EB820201EBA9 +:10FA100082014A688968A2EB080222F07F42A1EBCA +:10FA2000080121F07F41904298BFB2F5800F49D282 +:10FA30008C4547D34044A0EB0B0020F07F41316060 +:10FA40001944F86821F07F410A1A6FF07F43B2F53C +:10FA5000800F24BFA0EB010CBCF5800F0DD39342A7 +:10FA600003D2181A0844421C07E0634528BFFFDF91 +:10FA70001FD2591A0844401C4242002A19DD0520B1 +:10FA8000287499F8180016282DD099F8180099F8BC +:10FA90001710401C884200D1FFDF99F8180009F8C0 +:10FAA000004099F8180000E00BE016287FF448AFFA +:10FAB00044E73068ABF10501084420F07F407060F6 +:10FAC000002030727068401D20F07F407060787AAE +:10FAD000B072387A0627707203280DD260B101F037 +:10FAE00023FB28B108E099F817000028D5D1D3E707 +:10FAF000CAF138074FF0320A65480178012918BF6A +:10FB000003290AD14078504507D9604991F823105C +:10FB1000002904BFA0EB0A0007445E4B3068A0EB4D +:10FB20000802706822F07F41A0EB080020F07F4CB3 +:10FB30008F4298BFB1F5800F1CD263451AD3534949 +:10FB400091F829300C2B32D091F829704FF00C0B22 +:10FB50004FEA0B0A4C4907EB870301EB8303D3F809 +:10FB600008C0ACEB080C944531D8BB469F7C0C2FE9 +:10FB7000F0D199E00520287499F81800162811D0C2 +:10FB800099F8180099F81710401C884200D1FFDF3F +:10FB900099F8180009F8004099F8180016287FF421 +:10FBA000CFAECBE699F817000028F1D1EFE702209D +:10FBB000287491F829000C2818BF91F82900A8741E +:10FBC00081F82940012081F82A00BDE8F09F0C2F20 +:10FBD0001CBFBA46002267D00AEB8A0301EB8303FD +:10FBE000D3F804C0ACEB080C844528D29A7B96F875 +:10FBF0000AC094451CD30520287499F818001628CB +:10FC000011D099F8180099F81710401C884200D1BB +:10FC1000FFDF99F8180009F8004099F81800162835 +:10FC20007FF48EAE8AE699F817000028F1D1EFE74D +:10FC300093F812A00122BAF10C0FCDD103E0002AF3 +:10FC400008BFBA4630D03E460F4806EB860200EBAE +:10FC50008208062188F8101099F81800162836D066 +:10FC600099F8180099F81710401C884200D1FFDF5E +:10FC700099F8180009F8006099F8180016280CBFC8 +:10FC8000002099F8180007E0D80B0020C00C0020D5 +:10FC90007A000020FFFF3F0018BF401C89F81800C1 +:10FCA00098F81260B245CFD10220FE4E287406F1BA +:10FCB000E80090F82910B9420ED185F812A080F81A +:10FCC0002940012180F82A100120BDE8F09F99F811 +:10FCD00017000028CCD1CAE70C2F0BD0BBF10C0FBA +:10FCE00008BFFFDF0BEB8B0006EB8000847485F808 +:10FCF00012A0E9E7BBF10C0F08BFFFDF0BEB8B0095 +:10FD000006EB800084740C20A874DDE730B50D4646 +:10FD1000E54A44190021101A71EB010038BFFFDFDA +:10FD2000E2488542C8BFFFDFE1488542B8BFFFDF38 +:10FD3000E0488442A8BFE04804DA002CAABF20466D +:10FD4000DC4830BD201830BD401E70B5C0B200EB9D +:10FD50008001D44800EB8104607B062810D2DFE8E4 +:10FD600000F0030D0B090705002033E0B4200BE081 +:10FD7000732009E0322007E00A2005E0062003E0B6 +:10FD8000FFDF617B002029B3022108446168084439 +:10FD900020F07F40F9F75BF894F90C50C24A4419FF +:10FDA0000021101A71EB010038BFFFDFBF48854208 +:10FDB000C8BFFFDFBE488542B8BFFFDFBD488442F1 +:10FDC000A8BFBD4804DA002CAABF2046B94870BDC0 +:10FDD000201870BD0421D8E72DE9F04F0646B7483A +:10FDE00085B00068C005C00D11D0103840B20028A1 +:10FDF000B8BF00F00F0000F1E020B4BF90F8140D80 +:10FE000090F80004400908BF4FF0010A01D04FF0FC +:10FE1000000A3078002817BF01283079002005B08B +:10FE200018BFBDE8F08F062810D2DFE800F0030D00 +:10FE30000B090705002015E0B4200BE0732009E052 +:10FE4000322007E00A2005E0062003E0FFDF3179D9 +:10FE5000002039B15FF0020100EB0109BAF1000F97 +:10FE600006D101E00421F7E79549002081F8270039 +:10FE70006C4602AA2146B068F8F7F6FF9DF9082003 +:10FE8000F068211D10440122C01C1F28B8BF019238 +:10FE900008DB03AAF8F7E8FF9DF80C0010B1019801 +:10FEA000401C0190DDE900100844401D20F07F4017 +:10FEB0000190A1EB090020F07F40009070798DF84F +:10FEC0000A0000980390F8F730FF0099019B091A87 +:10FED000181A7C4A21F07F4120F07F40B1F5800F55 +:10FEE00010D282420ED3764890F82950009CAB463F +:10FEF000191B21F07F486FF07F41091BA0F1E80733 +:10FF0000049101E0002080E00C2D26D005EB850057 +:10FF100007EB80026FF07F435068011BB1F5800F43 +:10FF200010D3A4EB000CBCF5800F0BD38B4203D293 +:10FF300004990844411C05E063450DD2181A204479 +:10FF4000401C4142002908DA5D48AB46957C90F898 +:10FF500027000028D8D04CE0FFDF5D4525D00BEB13 +:10FF60008B0007EB80036FF07F429968081BB0F5A8 +:10FF7000800F12D3A4EB010CBCF5800F0DD382428D +:10FF800003D204980844401C07E0624528BFFFDF05 +:10FF90000BD2521A1019401C4042002805DD9DF872 +:10FFA0000A009A7B904228BF0C460C2D1CBF9DF87E +:10FFB0000A10434A14D000BF05EB850007EB800010 +:10FFC00043681B1B23F07F43434509D2837B99423F +:10FFD00028BF8468857C92F8270050B90C2DEBD19E +:10FFE0000098A04205D004EB080020F07F40009468 +:10FFF000019000990398814206D001EB090020F09E +:020000040001F9 +:100000007F40F8F724FFB06001202D4991F82710B8 +:10001000002904BF05B0BDE8F08FBAF1000F3FF42E +:1000200023AF05B0BDE8F08F2DE9F04F814687B0D2 +:100030000C4625480AF05AF8244901274FF00008D9 +:1000400001EB090500287DD0A1F5887898F8140007 +:10005000002818BFFFDF2078012800F0238200BFAE +:1000600088F810902078022808BFFFDF184E20790A +:1000700006F10C023072607970723146A068F8F7B0 +:10008000F3FE96F90C000F2804DD1F38307330683A +:10009000401C306096F90C00E168351D0844C01C16 +:1000A0001F2817E0D80B0020FF7F841E0020A10727 +:1000B00000E05EF80080841E00807BE104ED00E03B +:1000C000C00C0020FFFF3F00EC0C0020B40C00200F +:1000D000A40B0020B8BF2F6009DB6A462946F8F759 +:1000E000C3FE9DF8000010B12868401C28602078ED +:1000F000B07288F81470F64D95F8CD0195F8CC11D2 +:10010000884204BF07B0BDE8F08FF24890F829405C +:100110000C2C00F0CF81F8F708FEEF4904EB8402C5 +:1001200001EB82010A7C042A19BF0A7C032A07B06A +:10013000BDE8F08FE94B4A688968121A22F07F42C5 +:10014000081A00E01BE020F07F40062A3CBF07B001 +:10015000BDE8F08FB2F5800F24BF07B0BDE8F08F87 +:1001600083423CBF07B0BDE8F08F95F8CD0195F80C +:10017000CC11884240F0A78107B0BDE8F08FD44E83 +:1001800096F8CD01162855D096F8CD0196F8CC11E9 +:10019000401C884200D1FFDF207801284FD0CC4896 +:1001A00090F8CD1101EB810100EB810080F81090F7 +:1001B000207802284BD0C64890F8CD1101EB810180 +:1001C00000EB8105207928726079687205F10C02D4 +:1001D0002946A068F8F748FE95F90C000F2804DDC1 +:1001E0001F3828732868401C286095F90C00E168C6 +:1001F0002E1D0844C01C1F28B8BF376009DB6A46A3 +:100200003146F8F731FE9DF8000010B13068401C0F +:1002100030602078A872AE4991F8CD0116280EBF43 +:10022000002091F8CD01401C81F8CD01AC4809F0C7 +:1002300073FF60E796F8CC010028ADD1ABE715F865 +:10024000010C002818BFFFDF05F8017CA7E7A548CF +:100250000068C005C00D0FD0103840B20028B8BFEC +:1002600000F00F0000F1E020ACBF90F8000490F81F +:10027000140D400908BFFFDF954890F8CD1101AA81 +:1002800001EB810100EB8106E068CDF800808DF87C +:1002900004806946F8F7E8FD9DF904000F28CCBFFB +:1002A000012000200099351D084401900220B07201 +:1002B0002079307260797072A068C01C1F28B8BFA6 +:1002C0002F6009DB6A462946F8F7CEFD9DF800004D +:1002D00010B12868401C2860307A062810D2DFE868 +:1002E00000F0030D0B09070500200BE0B42009E026 +:1002F000732007E0322005E00A2003E0062001E039 +:10030000FFDF0020217900290CBF042102210844CD +:1003100002907168401D08440199009001440298C0 +:10032000081A05906B4C002084F82700F8F7FDFCB4 +:10033000804630600198404420F07F40F06094F89F +:1003400029000C287ED0204690F8291001EB81026C +:10035000A0F1E80101EB82025468009A274622448A +:1003600022F07F42039296F809B090F82950121BB0 +:1003700022F07F4A6FF07F42121BA94604920C2D97 +:1003800027D0554805EB850100EB81036FF07F42D4 +:100390005868011BB1F5800F24BFA4EB000CBCF51D +:1003A000800F0BD38A4203D204990844411C05E014 +:1003B00062450DD2111A0819401C4142002908DA81 +:1003C0004448A9469D7C90F827000028D7D04DE0EE +:1003D000FFDF4D4525D0404809EB890100EB810145 +:1003E0006FF07F438868021B8146B2F5800F24BFFF +:1003F000A4EB000CBCF5800F0DD3934203D2049AFA +:100400001044421C07E0634528BFFFDF09D21A1AD7 +:100410001019401C4242002A03DD887B834528BF17 +:100420004C460C2D1CBF2B4BA3F1E80116D000BF8E +:1004300005EB850001EB80025068001B20F07F4037 +:10044000504500E026E009D2907B834528BF9468A0 +:10045000957C93F8270048B90C2DE9D1A74205D027 +:1004600004EB0A0020F07F4027460390039AA7EB95 +:10047000080121F07F41A2EB0802059822F07F429B +:10048000B1F5800F06D2904204D30298384420F090 +:100490007F4030600F4890F8270000287FF442AF7B +:1004A000B9E600BF15F8010C002818BFFFDF05F8FA +:1004B000017CD5E595F8CD0195F8CC11884204BFB3 +:1004C00007B0BDE8F08F07B0BDE8F04FF8F79ABC71 +:1004D000D4090020C00C0020D80B0020FFFF3F00F3 +:1004E000EC0C002004ED00E00020F8F769BB0120CF +:1004F000F8F766BBFD48007870472DE9F0410546E6 +:1005000002282DD0FA4C94F829000C2808BFFFDFF0 +:10051000002784F82670012684F82B6094F82910AF +:100520000320DFF8D08301EB810108EB810108741F +:10053000F8F76FFCD5B1012D39D0032D1CBFFFDFBB +:10054000BDE8F08194F8290094F82910401CC0B24D +:1005500001EB810158F82120BDE8F0410521104749 +:10056000E2480078BDE8F041F9F71CB8207F002888 +:1005700018BFFFDF84F8256000202760F8F730FB04 +:10058000A168B1F1FF3F04D0012300221846F8F71B +:100590006BFB94F8290094F82910401CC0B201EBC1 +:1005A000810158F82120BDE8F041012110470120C8 +:1005B000F8F716FB94F8250000281CBFA068B0F1DE +:1005C000FF3F0DD094F8290094F82910401CC0B2C8 +:1005D00001EB810158F82120BDE8F04106211047C8 +:1005E000207F012815D002281FD0032833D00428EB +:1005F0001CBFFFDFBDE8F08194F820106068012384 +:10060000411A00221846F8F72FFB94F82800B8BBCF +:1006100037E094F8240028B184F82470F8F700FC3F +:1006200084F823602777BDE8F08194F8280018B992 +:10063000F8F778FC84F8286094F8290094F82910D9 +:10064000401CC0B201EB810158F8212000219047E5 +:100650002777BDE8F081217B60680123411A0022E1 +:100660001846F8F701FB94F8240028B184F82470A8 +:10067000F8F7D6FB84F8236002202077BDE8F081EC +:1006800003E0F8F74FFC84F8286094F8290094F808 +:100690002910401CC0B201EB810158F82120002133 +:1006A00090472677BDE8F08110B5914C94F8290069 +:1006B0000C2808BFFFDF94F8290094F82910401C8B +:1006C000C0B28C4A01EB810152F82120BDE81040F4 +:1006D000042110472DE9F05FF8F727FB844C814691 +:1006E0004FF00C0B94F829000026A4F1E8084FF015 +:1006F000010A0C282CD094F82910204601EB810126 +:1007000008EB8101097C042922D090F8291001EB23 +:10071000810108EB8101097C032908BFBDE8F09F36 +:10072000754922696069A2EB090222F07F42A0EBC1 +:10073000090020F07F40062A38BFBDE8F09FB2F5DF +:10074000800F28BFBDE8F09F814238BFBDE8F09F11 +:10075000A068B0F1FF3F18BFFFDF84F8256094F870 +:100760002900664F0C2806D194F8210018B1F878BA +:100770007870B87838705E4890F829000C281ED040 +:100780005B4890F8291001EB810108EB8101097C9D +:10079000042914D190F829B090F8291001EB8101B7 +:1007A00008EB810181F810A090F8291001EB81017C +:1007B00008EB8101897C80F8291080F82AA0504C30 +:1007C00094F8CD0194F8CC1104F2DF2588424ED084 +:1007D00094F8CC0100EB800004EB8000007C405DCD +:1007E000012894F8CC0100EB800004EB800004D0D9 +:1007F000007C405D022878D018E0807A01280DD076 +:1008000094F8CC11022001EB810104EB8101097CF9 +:10081000485594F8CC01162820D01BE094F8CC0160 +:1008200000EB800004EB8000007C465594F8CC017E +:1008300000EB800004EB800294F8CC0100EB800018 +:1008400004EB8000017C4846FEF7B7FF94F8CC012A +:10085000162803D094F8CC01401C00E0002084F856 +:10086000CC0194F8CD0194F8CC118842B0D1254C3C +:10087000207D70B1207C415D012966D0405D022859 +:100880006BD0207D28B1217C1E4A4846FEF795FF9B +:100890002675BBF10C0F06D00BEB8B0008EB80002C +:1008A000017C012961D0124C94F829000C2800F039 +:1008B000388194F82A00002800F0428184F82A60E8 +:1008C00094F8290000EB800008EB8003A4F53B704E +:1008D000D3E90112DB68C0F80433C0E9BF12607EBF +:1008E00000280CBF042502250EE01CE07800002043 +:1008F000C00C0020D80B0020FFFF3F007A00002032 +:10090000D4090020A40B002094F82900C34600EB72 +:10091000800108EB8100407B06284DD2DFE800F023 +:10092000404A4846444294F8CC0100EB800004EB76 +:100930008000807A012818BFFFDF94F8CC0100EB1B +:10094000800004EB8000867268E7A17A01291DBF50 +:10095000022141552675465593E7A07A012818BF14 +:10096000FFDFA672207C46558BE707210174FE4C01 +:10097000207E162810D0207EE17D401C884200D1C8 +:10098000FFDF207E04F800B0207E16280EBF002076 +:10099000207E401C207686E7E07D0028F1D1EFE73D +:1009A00000200BE0B42009E0732007E0322005E0CE +:1009B0000A2003E0062001E0FFDF00202073617EB3 +:1009C000022918BF012911D121690144A1EB0902B3 +:1009D00022F07F42382A09D903206076A1F1320043 +:1009E00020F07F4020613220207309E0322807D2B6 +:1009F00094F8280058B9F8F795FA84F828A006E08A +:100A000094F8280018B1F8F7B6FA84F828607978D5 +:100A100084F8201038780622012818BF032806D150 +:100A200084F824A0207B814284BF081A821D94F898 +:100A30002230002B18BF921C94F82400002808BF15 +:100A4000002B6AD0D4F810806069A8EB0908DFF8A1 +:100A50001CC328F07F48A0EB090020F07F404245EE +:100A600098BFB8F5800F41D284453FD3207B8842A0 +:100A700015D22369A1EB0002A3EB020222F07F4210 +:100A80001144294421F07F412261616000280CBF9C +:100A900001200320207710F0FF0F36D114E00AD98F +:100AA000226900291044284420F07F4060600CBF78 +:100AB00002200420EEE7002B08BFFFDF2069284456 +:100AC00020F07F40606026770120F8F789F800BFAA +:100AD00094F82900012300EB80010BEB8100616891 +:100AE00090F90C200020F8F7BFF829E084F8246082 +:100AF00084F82260207B0028E0D021690844284443 +:100B000020F07F4060600220207720690123411996 +:100B100000221846F8F7A8F8DAE7207B0028ECD185 +:100B2000CCE70120F8F75CF80020F8F759F8F8F75F +:100B30003DF894F8280018B1F8F71DFA84F82860F9 +:100B400094F8220028B1F8F76BF984F8236084F850 +:100B5000226094F8210018B1F8787870B87838706D +:100B600094F8240030B184F823603878002808BF56 +:100B700084F824607C48017EC07D814203D07C489B +:100B80004078F8F70FFD84F827A0BDE8F09F70B516 +:100B9000784C054682B094F829000C2808BFFFDF86 +:100BA00094F8290000EB8000734E06EB8000007C77 +:100BB000032818BFFFDFA068B0F1FF3F18BFFFDFB9 +:100BC00094F82900002100EB800006EB800001AAC8 +:100BD00090F90C0000918DF8041028446946F8F74C +:100BE00043F99DF904000F28CCBF01200020009993 +:100BF00008446168084420F07F41A16094F8250012 +:100C0000002804BF02B070BD012302B00022BDE87D +:100C100070401846F8F728B8584A0B1A02F1010C30 +:100C2000B3EB9C0F3CBF1846704710B5441AB4EBA9 +:100C30009C0F3CBF184610BD9A4203D2101A0844BC +:100C4000401C10BD94429EBFFFDF002010BD511A12 +:100C50000844401C404210BD0123002201460220EE +:100C6000F8F702B80220F7F7BBBFF8F75EB8F0B5A7 +:100C7000404C054683B094F82B00002808BFFFDFE6 +:100C8000642D50D33E490020491B80414BD33D4841 +:100C900090F8CD1190F8CC01814244D13A48007DC2 +:100CA000002840D194F82900334F00EB800007EB77 +:100CB0008006206801AA28446946F8F7D5F89DF90E +:100CC0000400002802DD0098401C0090B2680099E2 +:100CD00073685018C01A20F07F40B0F5800F22D200 +:100CE000B07C0C2809D000EB800007EB8000406846 +:100CF000801A20F07F40884215D3A068B0F1FF3FF2 +:100D000005D00120F7F76CFF4FF0FF30A06020689E +:100D100028442060B0680099084420F07F4060615A +:100D200003B00120F0BD03B00020F0BD2DE9F0417B +:100D30000646401EC5B2104805EB850100EB810454 +:100D4000207C002808BFFFDF0E4A92F8CC1192F8F1 +:100D5000CD01814221D000BF01EB810302EB83036F +:100D60001B7CB34220D011E0BC0B0020FFFF3F00F2 +:100D700078000020C00C0020D80B0020FF7F841ECC +:100D8000FF1FA107D4090020A40B002016290CBFC7 +:100D90000021491CC9B28142DED13A48017D0029B7 +:100DA00062D0007CB0425FD10020BDE8F081217CA0 +:100DB00005291FBF217C0629217C07292CD12774F6 +:100DC000C27D0023017E914218BF014624D000BF9E +:100DD00011F80280A84508BF012300D04BB1162AA4 +:100DE0000CBF4FF0000802F1010811F8088001F86B +:100DF0000280162A0CBF0022521CD2B291F8188031 +:100E00009045E5D143B10A7E002A08BF81F818C099 +:100E100002D00A7E521E0A76617C21B36674C27DBE +:100E20000021037E934224D0835CAB4208BF0121A2 +:100E300000D029B1162A0CBF0023531CC35C835475 +:100E4000162A0CBF0022521CD2B2037E9342EBD171 +:100E500049B1027E0146002A08BF81F818C008D0B7 +:100E60000A7E521E0A7604E00127074800264FF04A +:100E7000160C217C012904BF617C002997D1012037 +:100E8000BDE8F081A40B0020BC0B0020F0B5734A34 +:100E9000D2F80032724D002401212E7856B9714EDD +:100EA0003460704F03263F1D3E606E4F04260C37A2 +:100EB0003E602970C2F80042D1601160694C48342C +:100EC000D16425688542FBD35160D160C2F80032FD +:100ED000F0BD2DE9F041044680074FF000054FF0CA +:100EE000010604D560480560066024F00204E004B1 +:100EF0004FF0FF3705D55D484660C0F8087324F40D +:100F00008054600003D55A48056024F08044E00511 +:100F10000FD55248C0F80052C0F8087351490D600F +:100F2000091D0D604F4A04210C321160066124F442 +:100F30008074A00409D54F484660C0F80052C0F83C +:100F400008734D48056024F40054C4F38030C4F3A2 +:100F5000C031884200D0FFDF14F4404F14D047481E +:100F60004660C0F8087346488660C0F80052C0F872 +:100F7000087344490D600A1D16608660C0F8087346 +:100F80000D60166024F4404420050AD53E484660B2 +:100F90008660C0F80873C0F848733C48056024F4C4 +:100FA000006409F007FA3A48044200D0FFDFBDE8C8 +:100FB000F08170B5202500224FEA020320FA02F1E9 +:100FC000C90719D051B201F01F060124B4404E09DF +:100FD000B60006F1E026C6F88041C6F88042002936 +:100FE00006DA01F00F0101F1E02181F8143D03E080 +:100FF00001F1E02181F80034521CAA42DED370BD19 +:1010000070B5174C0D466060FFF763FF6068FFF72F +:10101000D0FF2846F8F763F808F00EFE00F0D5F888 +:1010200009F0C8F909F016F9F8F78EFABDE8704032 +:1010300008F0B0BE10B50A4C6068FFF74AFF606860 +:10104000FFF7B7FF09F0B6F9F8F70EF90020606076 +:1010500010BD034840687047022070470080004080 +:101060008000002004850040FC1F004000C00040BC +:1010700004E5014000D0004004D5004000E00040FD +:1010800000F0004000F5004000B0004008B500400E +:10109000FEFF0FFC70B51F490A68BAB100231D4658 +:1010A00001244A68521C4A60092A00D34D600E7917 +:1010B00004FA06F20E6816420AD072B60B68934321 +:1010C0000B6062B649680160002070BD052070BDEC +:1010D0005B1C092BE5D3FFDFF8E74FF0E0214FF46D +:1010E0008000C1F800027047EFF3108111F0010F8A +:1010F00072B64FF0010202FA00F20648036842EAB3 +:101100000302026000D162B6E7E7024800210160F5 +:101110004160704788000020012081070860704707 +:10112000012081074860704712480068C00700D05E +:10113000012070470F48001F0068C00700D0012041 +:1011400070470C4808300068C00700D00120704785 +:10115000084810300068704706490C310A68D2030D +:1011600006D5096801F00301814201D101207047D1 +:10117000002070470C040040C84911F8210F49783D +:10118000884201D3401A02E0C1F121010844C0B2F3 +:101190007047C249233111F8210F4978884201D3A1 +:1011A000401A02E0C1F121010844C0B27047BB49B6 +:1011B000463111F8210F4978884201D3401A02E0E4 +:1011C000C1F121010844C0B27047B54910B5802073 +:1011D00081F80004B1490020233101F8210F487043 +:1011E000AE4901F8210F4870AC49463101F8210F92 +:1011F0004870AC4808F072FFAA48401C08F06EFF27 +:10120000F8F77AF8BDE8104000F03DB920207047AB +:10121000B2E770B50C4605460026FFF7ADFF014664 +:101220009E48A14212D30022641EE4B20DD390F86E +:101230002210435C491CC9B205F8013B80F822101A +:101240002129F1D180F82220EEE7012600F01BF9D8 +:10125000304670BD202070479BE770B50C460546B0 +:101260000026FFF796FF01468C482330A14212D397 +:101270000022641EE4B20DD390F82210435C491C96 +:10128000C9B205F8013B80F822102129F1D180F87C +:101290002220EEE7012600F0F6F8304670BD20214E +:1012A00001700020704710B50446FFF780FF2070E2 +:1012B000002010BD70B50C460546FFF778FF0146CB +:1012C00076484630A14213D30022641EE4B20DD307 +:1012D00090F82210435C491CC9B205F8013B80F824 +:1012E00022102129F1D180F82220EEE7002401E02C +:1012F00042F2070400F0C7F8204670BD70B50C46F6 +:101300000546212900D9FFDF67480068103840B240 +:1013100000F0A0F8C6B20D2000F09CF8C0B28642E2 +:1013200004D2FFDF02E000BFF8F736F82146284676 +:10133000FFF76FFF0028F7D070BD2DE9F047DFF809 +:101340006481564CA8F101080746233498F8000040 +:10135000DFF84891002604F1230A38B994F82210E6 +:1013600094F82100212200F084F890B14D4699F8BC +:10137000221099F82100212200F07BF8B8B15546DF +:101380009AF822109AF82100212200F072F848B34E +:1013900035E094F82100275494F82100401CC0B295 +:1013A00084F8210021282AD184F8216027E095F8CB +:1013B00021002F5495F82100401CC0B285F821006F +:1013C000212801D185F8216098F800004746B0B186 +:1013D00095F8221095F82100212200F04AF870B10A +:1013E0003E700CE095F821002F5495F82100401C28 +:1013F000C0B285F82100212801D185F8216094F838 +:10140000221094F82100212200F033F800281FD088 +:1014100099F8221099F82100212200F02AF80028DA +:1014200016D09AF822109AF82100212200F021F813 +:1014300000280DD0F7F786FF1A4808F057FEB0F5E0 +:10144000005F00D0FFDFBDE8F047164808F064BE3B +:10145000BDE8F087002806DA00F00F0000F1E02078 +:1014600090F8140D03E000F1E02090F8000440092A +:101470007047401C884204D0904200D109B100203E +:1014800070470120704710B5064808F02FFE00286D +:1014900003D1BDE81040F7F740BF10BDF00C0020AD +:1014A0000DE000E09100002004ED00E01349087811 +:1014B0004A78401CC0B2904205D0114B01221A60FC +:1014C000BFF34F8F0870704770B54FF0E0250B4C9D +:1014D000F7F7E8FF20BF40BF20BF60782178617038 +:1014E000D5F8001229B9D5F8041211B92178814232 +:1014F000EED0F7F7D2FF002070BD0000930000206F +:10150000180502402DE9F041012528034FF0E021A4 +:101510000026C1F880011E4CC4F800610C2000F0C8 +:101520002CF81C4801680268C94341F3001142F0DD +:1015300010020260C4F804532560491C00E020BF7B +:10154000D4F80021002AFAD019B9016821F010015D +:101550000160114807686560C4F80853C4F8006169 +:101560000C2000F00AF83846BDE8F08110B50446BA +:10157000FFF7C8FF2060002010BD00F01F0201210E +:1015800091404009800000F1E020C0F880127047CF +:1015900000C0004010ED00E008C500402DE9F04714 +:1015A000F84C0646FF21606800EB061211702178A6 +:1015B000FF2916D04FF0080909EB011109EB0617B6 +:1015C0004158C059491E21F07F4100F0DDF918B1A2 +:1015D00094F80080454614E06168207801EB06111C +:1015E00008702670BDE8F087626809EB0510D159D4 +:1015F000105800F0C9F930B96068A84600EB08102F +:101600000578FF2DF0D1606800EB061100EB0810A3 +:101610000D700670E6E7F0B5DA4B044600200125B0 +:101620005A680C261B7A0BE005EB0017D75DA74222 +:1016300004D106EB0017D7598F4204D0401CC0B22A +:101640008342F1D8FF20F0BD70B5FFF70EFBCD4C03 +:10165000014608252278606805EB0212805800F0E8 +:1016600093F9012808D92178606805EB01114058E9 +:10167000BDE87040FFF7F0BAFEF73CFFBDE87040F0 +:10168000F7F790BF2DE9F041BE4C2578FFF7EDFA52 +:101690000146FF2D6FD04FF00808626808EB051671 +:1016A000905900F071F90228606801D980595EE014 +:1016B00000EB051109782170022101EB0511425C54 +:1016C0005AB1521E4254815901F5000121F07F4167 +:1016D00081512846FFF762FF34E00423012203EB27 +:1016E000051302EB051250F803C0875CBCF1000F34 +:1016F00010D0BCF5806F10D9CCF3090250F806C0A9 +:101700000CEB423C2CF07F4C40F806C0C3589A1AB0 +:10171000920A09E0FF2181540AE0825902EB4C321F +:1017200022F07F428251002242542846FFF736FFC2 +:101730000C21606801EB05114158E06850F8272042 +:10174000384690472078FF2815D0FFF78EFA0146DB +:101750002278606808EB02124546805800F014F9C0 +:10176000012891D92178606805EB01114058BDE846 +:10177000F041FFF771BABDE8F081F0B51D4614469F +:101780000E460746FF2B00D3FFDFA00700D0FFDF88 +:101790007C48FF210022C760446005720674017016 +:1017A00042701046012204E002EB0013401CE15499 +:1017B000C0B2A842F8D3F0BD70B5724C0646657849 +:1017C000207C854200D3FFDFE06840F82560607828 +:1017D000401C6070284670BD2DE9FF5F1D468B469A +:1017E0000746FF24FFF741FADFF89891064699F87B +:1017F0000100B84200D8FFDF00214FF001084FF090 +:101800000C0A99F80820D9F804000EE008EB01133F +:10181000C35CFF2B27D0BB4205D10AEB011350F864 +:1018200003C0DC4521D0491CC9B28A42EED8FF2C46 +:101830001BD008EB04110AEB0412475440F802B025 +:101840000421029B0022012B01EB041111D0425014 +:101850004FF4806808234FF0020C454519D9A905BB +:10186000890D08D008E00C46DDE7FF2004B0BDE894 +:10187000F09F4550ECE7414606EB413203EB041381 +:1018800022F07F42C250691A0CEB0412890A81547B +:101890000BE005B9012506EB453103EB041321F0FC +:1018A0007F41C1500CEB0411425499F8005020467E +:1018B000FFF774FE99F80000A84201D0FFF7C4FEBC +:1018C0003846D3E770B50C460546FFF7CEF9064615 +:1018D00021462846FFF79FFE0446FF2817D0294DD2 +:1018E000082101EB041168684058314600F04CF8BB +:1018F00000F58050400B02216A6801EB0411515C35 +:1019000009B100EB8120002800D1012070BD00202A +:1019100070BD2DE9F0410F468046FFF77CFEFF28A1 +:101920001BD0184E357871682A462C4605E0844253 +:1019300006D0254601EB05131C78FF2CF7D10CE0EF +:10194000FF2C0AD0A5420CD101EB021000783070B8 +:10195000FF2804D0FFF778FE03E000200BE7FFF735 +:1019600081F939464046FFF7ADFFFF220123716838 +:1019700003EB0413CA5401EB041201EB05111278B6 +:101980000A70F8E65C0D0020401A20F07F40B0F5A8 +:10199000000F00D90020704770B50446A0F5000084 +:1019A0002C4EB0F1786F02D23444A4F500042A48DA +:1019B000844201D2012500E0002500F041F830B159 +:1019C000B4420BD32548006804E0284370BDB442FC +:1019D00004D32348844201D20120F6E70020F4E733 +:1019E00010B50446A0F50000B0F1786F03D2194895 +:1019F0000444A4F5000400F023F84FF0804130B116 +:101A00001648006804E08C4204D2012003E0144828 +:101A10008442F8D2002080F0010010BD10B520B142 +:101A2000FFF7DEFF08B1012010BD002010BD10B58A +:101A300020B1FFF7B1FF08B1012010BD002010BD9B +:101A4000084809490068884201D1012070470020F8 +:101A5000704700000000002000C001001C000020B2 +:101A60000800002098000020BEBAFECA0548064AB9 +:101A70000168914201D10021016004490120086000 +:101A80007047000098000020BEBAFECA40E5014041 +:101A9000404800210170417010218170704770B57D +:101AA000054616460C460220F5F79BFC39490120F5 +:101AB00008703949F01E086038480560001F04604E +:101AC00070BD10B50220F5F78CFC3249012008707A +:101AD00033480021C0F80011C0F80411C0F8081103 +:101AE00030494FF40000086010BD2A480178C9B1A0 +:101AF0002D4A4FF4000111602949D1F8003100222C +:101B0000002B1CBFD1F80431002B02D0D1F80811F2 +:101B100011B14270102103E001214170234909688D +:101B2000817002700020F5F75CBC1A48017800292A +:101B300004BF407870471A48D0F80011002904BF4C +:101B400002207047D0F8001100291CBFD0F8041102 +:101B5000002905D0D0F80801002804BF01207047F3 +:101B6000002070470B480178002904BF8078704737 +:101B70000B48D0F8001100291CBFD0F8041100292F +:101B800002D0D0F8080108B110207047074800685B +:101B9000C0B270479C00002010F5004008F50040DE +:101BA00000F0004004F5014008F5014000F4004059 +:101BB0003148002101704170704770B506461446E7 +:101BC0000D460120F5F70DFC2B49012008702B482C +:101BD0000660001D0460001D056070BD2DE9F04128 +:101BE00004460120F5F7FDFB234901200870244934 +:101BF0000C60244D0026C5F8046123494FF040775E +:101C00000F60A1F1040844B1012C18BFFFDFC5F833 +:101C10000062C8F80070BDE8F081C5F800024FF01E +:101C20008070C8F80000BDE8F0811348017879B1F0 +:101C3000154A4FF0407111601249D1F8042100217A +:101C4000002A08BF417002D0104A12684270017029 +:101C50000020F5F7C6BB08480178002904BF40788A +:101C600070470848D0F80401002808BF70470748AB +:101C70000068C0B2704700009F00002008F50040D7 +:101C800004F5004000F0004008F5014000F4004079 +:101C900070B5FE4C002501266570257025626572C1 +:101CA000A572E67284F82950256304F13C00A5630F +:101CB00008F014FA002818BFFFDF84F82450F44815 +:101CC00009F07CFAF3480660657770BD30B4EF49DF +:101CD0000268DFF8C8C34A6142688A61007A0877FF +:101CE0000A7DED4BACF1040401204AB10A7E00FAF2 +:101CF00002F21A608D7D002D0CBF2260CCF800200E +:101D00004A7D002A04BF30BC70474A7E904018606C +:101D1000C97D00290CBF2060CCF8000030BC7047A2 +:101D2000DF4900B50A1D40B101281CBFFFDF00BD1F +:101D3000DC480860DC48106000BDDC480860DC4816 +:101D4000F9E7F0B502264FF0E02701240025C7F897 +:101D50008061D8490D600C60D7490A6822F077028B +:101D600042F0880242F000420A60CD490A1DD0B11B +:101D7000012818BFFFDF1AD0D04940F25B6008602D +:101D8000091F40F203100860081F0460CC490320BB +:101D90000860CC4996200860BC4C94F9240010F0EF +:101DA000030F09D033E0C1480860C14802E0BD48D4 +:101DB0000860BD481060DFE780100A300C2826D28A +:101DC000DFE800F021252525251D1915110D0A062E +:101DD000BD49042008601BE0BB48056018E0BA4913 +:101DE000FC20086014E0B849F820086010E0B6490B +:101DF000F42008600CE0B449F020086008E0B24923 +:101E0000EC20086004E0B049D820086000E0FFDF63 +:101E1000607F002814BF4FF4C020AC48AC49086074 +:101E2000AD49AC480860091FAC480860C7F880623B +:101E3000AB491020C1F80403F0BD944A0368C2F80E +:101E400002308088D08011727047904890F8290045 +:101E500070478E4A517010707047F0B50D460446B9 +:101E600004EB4501908808841078D2F8011001270E +:101E700040EA012044F8250005F1080007FA00F6C1 +:101E8000002B04BF206BB04304D0012B18BFFFDF31 +:101E9000206B304307FA05F108432063F0BD30B5ED +:101EA0000D460446082988BFFFDF0022002D11D906 +:101EB00054F82210900000F1804000F58050C0F8E6 +:101EC000001604EB4201098CC0F82016501CC2B267 +:101ED0009542EDD8206B8349086030BD10B50446AB +:101EE00010F0030F2BD1A0100A300C2827D2DFE806 +:101EF00000F022262626261E1A16120E0A067249FF +:101F0000042008601CE070490020086018E06E4959 +:101F1000FC20086014E06C49F820086010E06A4971 +:101F2000F42008600CE06849F020086008E0664989 +:101F3000EC20086004E06449D820086000E0FFDF7E +:101F4000524880F8244010BD504890F83400704743 +:101F5000654AC178116000686449000208607047F2 +:101F6000252808BF02210ED0262808BF1A210AD032 +:101F7000272808BF502106D00A2894BF0422062231 +:101F800002EB4001C9B25A4A11605A4908607047D1 +:101F90003E49086270473D498A7A012A49D0022A9F +:101FA00018BF70474B7D002B08BF7047DFF848C152 +:101FB000012A42D0CA7D4B7E002A18BF01227D3003 +:101FC000CCF80000DFF834C10020CCF84C01180236 +:101FD00082F0010240EA025040F00312087F8300C1 +:101FE00003F1804303F5C043C3F81025444A02EBD4 +:101FF0008002887EC30003F1804303F5F833C3F801 +:102000001425DFF800C1C3F810C5C97ECB0003F169 +:10201000804303F5F833C3F81425304AC3F810257C +:10202000012202FA00F002FA01F108433649086081 +:1020300070470B7D002BB9D170478A7D0B7E002A3B +:1020400018BF01227E30BBE72DE9F84F00280CBFF6 +:10205000012002200D4C224D0322A072C5F800225F +:10206000627F002A14BF4FF4C022184A264F3A60FC +:102070004FF00108002976D0012973D002291CBF36 +:10208000FFDFBDE8F88F206A00283FE0700D0020D8 +:10209000840D0020A0050040180500500C050050DC +:1020A00014150040050103001F0003020601020091 +:1020B00025000302FC1F00403C170040381500407B +:1020C00010150040441500400C15004000000404A9 +:1020D00008F5014040800040A4F501401011004087 +:1020E0000010004040160040241500401C15004020 +:1020F00008150040541500404C8500400080004009 +:10210000006000404C81004004F5014008BFFFDF43 +:10211000216A206B0844FB490860FC49FA480860C2 +:10212000A17AFB4801290EBF0560FA490160A06B46 +:1021300040F40020A063D5F800924FF0100AC5F8D3 +:1021400008A30026C5F80062F3484FF4802BC0F8BE +:1021500000B0FF208DF80000C5F81061C5F81080B0 +:102160003DE000E01CE0012813D0C5F804800228FF +:1021700018BFBDE8F88F607D002808BFBDE8F88F64 +:10218000E648C0F84C80E6480068BDE8F84F0A30E1 +:1021900001E7C5F80080207D0028F1D1BDE8F88F67 +:1021A000E0490128896B07D0022818BFFFDF09D05A +:1021B000BDE8F84F0A20EEE641F48010A0634FF42A +:1021C000801004E041F40010A0634FF40010386068 +:1021D000EEE700BF9DF80000401E8DF800009DF85E +:1021E000000018B1D5F810010028F3D09DF80000C8 +:1021F000002808BFFFDFC5F80C61C5F81061C5F8FD +:102200000461C5F81461C5F81861C5F82861C648AD +:1022100000680090C5F80092C7F800B0C5F804A3A4 +:102220004FF400203860216A206BBDE8F84F084465 +:102230000A30B0E62DE9F847BC4CD4F8000220F093 +:102240000309D4F804034FF0100AC0F30018C4F8CF +:1022500008A30026C4F80062B24D687F002814BFAE +:102260004FF4C020B248AC490860A87A0127012881 +:1022700002D0022803D014E0287D10B911E0687D57 +:1022800078B1A87EEA7E07FA00F007FA02F210435E +:102290000860287F800000F1804000F5C040C0F851 +:1022A0001065FF208DF80000C4F81061276104E07C +:1022B0009DF80000401E8DF800009DF8000018B148 +:1022C000D4F810010028F3D09DF80000002808BFC2 +:1022D000FFDFC4F81061C4F828616E72AE72EF724D +:1022E000C4F80092B8F1000F18BFC4F804A3BDE809 +:1022F000F88700688F4920F07F40086070474FF0F2 +:10230000E0200221C0F88011C0F8801270474FF021 +:10231000E0210220C1F8000170478749087070472A +:1023200010B5864807F0E2FE002818BFFFDF10BD99 +:10233000824807F0F1BE82490860704730B5794C99 +:102340000546206BA84228BFFFDF012020732561CE +:10235000607F40B1A81C20617448D0F8001241F0A1 +:102360004001C0F800126D490020C1F844017549D0 +:1023700020690860A06B744940F48000A0634FF4AA +:102380008000086030BD674802210173CA210161E5 +:10239000417F41B1CC2101616449D1F8002242F072 +:1023A0004002C1F800225D4A0021C2F844110269CE +:1023B000016B1144634A1160816B41F480018163B8 +:1023C00061494FF480000860704756490120487702 +:1023D0005E49022008605F495D480860091F5E4849 +:1023E000086070474F490020487770474A494FF4CA +:1023F000800008604B48816B21F4800181630021DB +:1024000001737047454801214160C1600021C0F857 +:1024100044114C480160434801637047414800B58E +:10242000407F002818BFFFDF4020484908603F4830 +:10243000D0F8001241F04001C0F8001200BD394848 +:1024400000B5407F002818BFFFDF3848D0F80012E1 +:1024500021F04001C0F800123C490020086000BD96 +:102460003248D0F8001221F01001C0F8001201210A +:10247000816170472D480021C0F81C11D0F800126E +:1024800041F01001C0F800127047284981B0D1F81E +:102490001C21012A1EBF002001B070472F4A12687C +:1024A00002F07F02524202700020C1F81C012C4849 +:1024B00000680090012001B0704730B50C0005465F +:1024C00008BFFFDF14F0010F1CBF012CFFDF002D40 +:1024D0000CBF01200220134901284872CC72134915 +:1024E00004BFD1F8000240F0040007D0022807BF63 +:1024F000D1F8000240F00800FFDF30BDC1F8000253 +:1025000030BD00004885004048810040A8F50140EA +:10251000ACF501400410004008F501400080004087 +:102520004C850040700D0020181100400010004044 +:10253000000004043C150040A1000020AC0D002068 +:10254000041500404485004004F50140601500403A +:10255000448000409CF5014028110040481500408F +:102560001C11004070B5EB4C0022E17A11F0020F13 +:1025700018BF10F0040F16D111F0100F1CBF94F803 +:102580003530002B02D094F8363063B111F0080FCB +:102590001CBF94F82830002B05D111F0040F03D094 +:1025A00094F8291001B90122657ADB4900234FF024 +:1025B000010C35B100F00200104314D0BDE87040AA +:1025C00038E6607F002814BF4FF4C020D348D44AB7 +:1025D0001060D1F8000220F00300C1F80002A372DD +:1025E00084F80BC070BD012D14D0022D18BFFFDF81 +:1025F0001CD0A07A01280CBFCA48CB484FF47A718E +:1026000000F2E730B0FBF1F0216BBDE87040081A32 +:102610008C30C0E4D1F8000220F00400C1F80002C0 +:10262000637284F80BC084F80AC0E2E7D1F80002B4 +:1026300020F00800C1F80002637284F80BC0022089 +:10264000A072D6E72DE9F84FB84FD7F84C21B14C1E +:10265000B3494FF00108A07A0026CAB1012802D080 +:10266000022803D014E0227D12B911E0627D7AB114 +:10267000A27EE37E08FA02F208FA03F31A430A6024 +:10268000227F920002F1804202F5C042C2F810653A +:10269000A26B0A60A663217B19B1D7F84411012906 +:1026A00000D000219C4DD5F81021012A0CBF4022FA +:1026B0000022012805BFD5F80C31012B002320236F +:1026C0001A43012805BFD5F80431012B002310233C +:1026D0001343974A022804BFD2F800C0BCF1010F8F +:1026E00007D1D5F80CC1BCF1010F08BF4FF0080CA1 +:1026F00001D04FF0000C4CEA0303022804BF12681B +:10270000002A05D1D5F80C21012A08BF042200D0E7 +:1027100000221A43022803D1002918BF022100D148 +:1027200000211143022804BFD5F80401012805D176 +:10273000D7F84401012818BF012000D1002040EA49 +:1027400001097C48016811F0FF0F03D0D5F814117E +:10275000012900D0002184F83410006810F0FF0F28 +:1027600003D0D5F81801012800D0002084F83500E6 +:102770007148006818B1FFF7D8F9012800D000208F +:1027800084F83600C5F80C61C5F81061C5F804611D +:10279000C5F81461C5F81861C5F828616748006874 +:1027A0000090C7F84461664800684D46DFF8949190 +:1027B0000090D9F80000E062617F00291CBF801EF4 +:1027C000E062614800682063A07ADFF880A10228F7 +:1027D0000CD1607850B1DAF80010097808402178FF +:1027E00031EA000008BF84F8288001D084F828600E +:1027F000DFF85C8115F0010F16D098F80010554AEB +:102800004908E06A52F821108847012198F8002011 +:10281000514B5208206B53F82220904798F8000043 +:1028200010F0010F0BD01FE015F0200F18BF022190 +:10283000ECD115F0020F18BF0021E7D1EEE7DAF86E +:102840000000062200F10901A01C08F0D1FA40B9ED +:10285000207ADAF800100978B0EBD11F08BF012008 +:1028600000D0002084F829002846FFF77BFE15F0F1 +:10287000020F05D0394898F8001050F82100804721 +:1028800015F00C0F07D0364898F8001050F82110BA +:10289000C5F3C000884715F0200F05D0314898F8DF +:1028A000001050F82100804798F80000022805D158 +:1028B00005F06E00402806D101F00EF998F80000EE +:1028C000042828BFFFDFA07A022818BFBDE8F88FD0 +:1028D000207B002808BFBDE8F88FC7F844610228B4 +:1028E00014D0012818BFFFDF216B2069884298BFF0 +:1028F000FFDF2069C9F80000A06B1B4940F480008D +:10290000A0634FF480000860BDE8F88F2169206B58 +:102910000844EFE7700D00200010004000000404A0 +:1029200008F50140F0FE0100B0F801000080004011 +:10293000001400404016004060150040181100408F +:10294000448100404485004040850040041500401B +:10295000A1000020FCB4010004B501000CB5010089 +:102960001CB501002CB5010004F5014010B54A4822 +:1029700006F0CFFB0021484806F000FC0121464844 +:1029800006F0CAFB4549002081F822004FF6FF708F +:10299000888443490880488010BD10B53E4806F041 +:1029A000B8FB00213C4806F0E9FB01213A4806F05B +:1029B000B3FB3A49002081F822004FF6FF7088846B +:1029C00037490880488010BD704734498A8C82425C +:1029D00018BF7047002081F822004FF6FF708884EE +:1029E00070472D49016070472D49088070472B4979 +:1029F0008A8CA2F57F43FF3B03D00021016008468B +:102A0000704791F822202549012A1ABF0160012050 +:102A100000207047214901F1220091F82220012A6B +:102A200004BF00207047012202701D48008888847E +:102A3000104670471A49488070471849184B8A8CCD +:102A40005B889A4206D191F82220002A1EBF0160BD +:102A500001207047002070471048114A818C52882D +:102A6000914209D14FF6FF71818410F8221F19B1EC +:102A70000021017001207047002070470748084A74 +:102A8000818C5288914205D190F8220000281CBF09 +:102A90000020704701207047D60D0020B00D0020A7 +:102AA000A200002070B5FF4E044696F88400002571 +:102AB000012807D096F8660001281CBF002070BDD1 +:102AC000E1B90EE0D1B9657014202070D6F8850008 +:102AD000C4F80200D6F88900C4F8060086F88450CD +:102AE0000CE06570132020701C2206F16801A01C08 +:102AF00008F0AAF90120A07186F86650012070BD87 +:102B0000E84890F86610002914BFB0F86A004FF644 +:102B1000FF70704770B5E4480178002918BF0C2693 +:102B200001D0304670BDDF4C0026354684F8546035 +:102B300084F8556084F8566084F8576084F85860CB +:102B400084F8596084F84D6084F82D6084F86460DE +:102B50007F21817094F85A0028B1FFF770FCFEF7CE +:102B6000C4FF84F85A5084F86650D04806F07EF9C5 +:102B7000CF4806F07BF9D4E770B5CB4A0025157035 +:102B8000C84CC4E91701107800281CBFFFDF70BDD6 +:102B900084F8545084F8555084F8565084F85750AF +:102BA00084F8585084F8595084F84D5084F82D50CA +:102BB00084F864507F20907094F85A0028B1FFF791 +:102BC0003EFCFEF792FF84F85A5084F86650B748EE +:102BD00006F04CF9BDE87040B54806F047B9B14879 +:102BE00090F854007047AF4900B591F84F0091F844 +:102BF0004E10C0F38002C0F340031A4400F00100FD +:102C00001044052910D2DFE801F00B070B0309007F +:102C1000A84931F8100000BDA74800BDA74900E051 +:102C2000A74931F8100000BDFFDF002000BD9D481E +:102C300040F27121B0F8500048437047994890F82D +:102C40006500002818BF0120704770B5954C437B84 +:102C5000002584F84F30037984F84E30012B0EBFE5 +:102C6000A4F85050B0F800C0A4F850C090F80EC0BE +:102C700084F865C021701168C4F801109188A4F827 +:102C8000051081796173D0F80710C4F80710B0F807 +:102C90000B00A4F80B0094F84D000126002818BF83 +:102CA00084F8556094F82D00002818BF84F8566009 +:102CB000052B2CD2DFE803F00308212608000021B1 +:102CC0007A4806F0D6F823E00121784806F0D1F8DA +:102CD000E11D764806F0FEF8607B20B1012818BFA0 +:102CE000FFDF05D014E00021704806F007F90FE07F +:102CF00001216E4806F002F90AE006216B4806F051 +:102D0000B8F805E00221694806F0B3F800E0FFDFFB +:102D100084F8575084F85850611C644806F0CCF889 +:102D20002178624806F0DDF80421614806F0A1F838 +:102D3000611C5F4806F0C0F821785D4806F0D1F8C4 +:102D400084F85460002070BD564A012382F8583040 +:102D500092F866C0BCF1000F1CBF3A20704710B457 +:102D600014784FF0000C844218BF82F858C009D183 +:102D700082F857C00868C2F801008888A2F80500E8 +:102D800082F8573010BC0020704770B5454C05469E +:102D9000002084F856002A4604F10E0008F054F88A +:102DA00084F82D50012084F8560070BD10B53D4CBC +:102DB000002284F8552084F84D00024604F12E00CC +:102DC00008F042F8012084F8550010BD354981F81B +:102DD0006400704770B5344E3078A0BB314C94F825 +:102DE000540080B3FFF79CFA002584F8525084F811 +:102DF000535075702846FFF790FA0020FEF7A1FFA8 +:102E00003048FFF7A5F83048FFF773FAFFF7BBFA31 +:102E100094F84F0010F0010F04D094F8521011F004 +:102E2000010F13D010F0020F04D094F8521011F0DB +:102E3000020F18D010F0040F2CD094F8520010F0AC +:102E4000040F1BD026E0FFE70C2070BD2520FFF704 +:102E500087F80020FEF764FF94F8520040F001006C +:102E600084F8520016E02620FFF77AF80020FEF7DB +:102E700057FF94F8520040F0020009E02720FFF7C6 +:102E80006FF80020FEF74CFF94F8520040F0040069 +:102E900084F85200FFF73BFA01210020FFF7D4F835 +:102EA0000F2113E0F80D0020A8000020880E00205C +:102EB000B00E00204CB501009189130054B50100FB +:102EC00044B501003FB501003CB501000520FEF707 +:102ED000C0FF2178601CFEF7B0FF94F84E00012877 +:102EE0001EBF042894F85500002808D094F84D20FF +:102EF00004F12E01FE4806F01CF884F8555094F8B1 +:102F0000560040B194F82D2004F10E01F94806F066 +:102F10003CF884F85650206E017819B110F8041B63 +:102F2000FEF7BDFFE06D017831B1F34A401CFEF7BA +:102F3000B6FD012084F85A00FFF7FAF9002070BDB1 +:102F4000EE494860704770B5ED4C05003BD0204617 +:102F500094F84F1090F8520011F0010F02D010F0C9 +:102F6000010F0CD011F0020F02D010F0020F11D09F +:102F700011F0040F27D010F0040F18D023E0252003 +:102F8000FEF7EEFF0020FEF7CBFE94F8520040F073 +:102F9000010009E02620FEF7E3FF0020FEF7C0FE57 +:102FA00094F8520040F0020084F852000BE0272011 +:102FB000FEF7D6FF0020FEF7B3FE94F8520040F073 +:102FC000040084F8520094F8530040B194F84E0085 +:102FD000012808BFFFDFBDE8704000F054BA1DB102 +:102FE00002210020FFF730F894F85700002558B16F +:102FF000611CBF4805F060FF611CBE4805F05CFF26 +:1030000084F8575084F85850B948FFF794F994F869 +:103010004E00052809D2DFE800F00303030903008E +:1030200001210846FFF749FA00E0FFDF94F84F005E +:1030300094F8521030EA01014FF0010002D0AF497C +:10304000087070BD94F84E10012914BF84F8530025 +:1030500084F85250F3E710B5FFF762F9A7480078FB +:1030600040B9A74890F8540020B10020FFF76BFF4B +:10307000002010BDFFF7C6F9FFF7B8F9FFF7DAF83F +:10308000FFF73DF9FFF754F90C2010BD9B490120D3 +:10309000487070479A4981F85900704770B500250B +:1030A00002F075FC68B14FF49670FEF771FF934E15 +:1030B0003078012809D0022801D003282ED0FFDF64 +:1030C00070BDBDE8704000F0DEB98D4C94F84E0044 +:1030D000032823D094F85A0018B1FEF7F2FCFFF74A +:1030E0009DF98848FFF727F994F84E00012818BF8A +:1030F00004280AD094F86500012814BF032810257D +:1031000045F00E010020FFF7D8F994F8640001287B +:1031100008BFFFF7AFF90220307070BDBDE8704006 +:10312000012010E770B5764C744D94F864000128C6 +:1031300020D000BF94F85A0018B1FFF780F9FEF7CD +:10314000D4FC02F024FCF8B12878022818BFFFDF75 +:1031500094F84E00012804BF4FF41970FEF718FFD1 +:103160000120FFF7F0FE287800281EBF28780128EC +:10317000FFDF70BD6448FFF788F9002804BF7F2097 +:10318000A870FFF76DF9D5E7BDE8704000F07BB996 +:103190002DE9F05F82460027FEF7D6FE574D8146A7 +:1031A000B8462878022818BFFFDF554C4FF07F0B38 +:1031B00094F86400012825D0524805F079FE0646AF +:1031C000BAF1000F6FD04F4805F06FFF00286AD0AA +:1031D000FEF73BFE002866D094F85A00002818BF7E +:1031E0004FF028081ED000BFA8F1010000F0FF0832 +:1031F000FEF79BFC02280FD0012808BF4FF0010802 +:1032000010D00DE04048FFF740F9002808BF85F8CE +:1032100002B0FFF725F9CFE7B8F1000FE4D1FFDFE7 +:103220004FF0000837484FF0010A062E3BD2DFE886 +:1032300006F083838303833B94F84E10012918BF63 +:10324000042979D059EA080105D194F865100029BC +:1032500018BF022970D194F86410012904BF94F8B2 +:103260008410002905D02348FFF765F80320287053 +:1032700063E084F884A0007804F18C06C0F3801029 +:1032800084F88500D4F8E300C4F88600B4F8E700B9 +:10329000A4F88A00A8787F2808BFFFDFA8783070DC +:1032A00085F802B0DFE747E0C178E27991421BD1AF +:1032B0000179227A914217D14179627A914213D1F0 +:1032C0008179A27A91420FD1C179E27A91420BD1F0 +:1032D000017A227B914207D10178627BC1F3801190 +:1032E000914208BF012200D0002294F84E100DE058 +:1032F000880E0020B00E0020DB0E0020A800002069 +:10330000F80D0020D80E0020AA000020012918BFC7 +:10331000042900D14AB979B959EA080105D194F8CC +:103320006510002918BF012906D194F8581019B961 +:1033300094F85910A346C9B1012794F85A0018B15E +:10334000FFF77DF8FEF7D1FB002F1CBF0120FFF730 +:10335000FAFD287800281ABF28780128BDE8F09FD8 +:103360002878032818BFFFDFBDE8F09F06466A688B +:10337000DBF8EF10C2F80D1000786B49C0F3801035 +:103380005076DBF8E300C2F81A00BBF8E700D08300 +:10339000BBF8F300A2F811009BF8F500D074B07DE3 +:1033A0001075B6F81700D082B6F819005080B6F83C +:1033B0001B009080B6F81D00D08002F1080007F0D5 +:1033C00002FF96F8240000F01F016868017696F865 +:1033D0002410490980F8CC109BF86600002818BF1B +:1033E000FFDF00268BF8686068680188ABF86A1018 +:1033F000417E8BF86D10D0F81A10CBF86E10C18B8F +:10340000ABF872109BF800108BF87410DBF8011009 +:10341000CBF87510BBF80510ABF879104188ABF804 +:103420007C108188ABF87E10C188ABF8801090F8D2 +:10343000CC008BF882009BF88300B8F1000F04BF2A +:1034400020F001008BF883000BD040F001008BF8D6 +:103450008300FEF787FB9BF8831060F347018BF82E +:1034600083108BF866A02E70FEF7CCFFFEF7BEFF30 +:10347000FEF7E0FEFEF743FFFEF75AFF0120696802 +:1034800002F064FB59E770B5FEF7BCFFFEF7AEFF34 +:10349000FEF7D0FEFEF733FF244C002694F85A00C6 +:1034A00028B1FEF7CCFFFEF720FB84F85A60204DD0 +:1034B0002E70FEF73DFF94F84E004FF000010128FA +:1034C00004D0BDE87040002002F040BB022002F0B2 +:1034D0003DFB94F86600002818BFFFDF68780028DD +:1034E00008BF70BD607B84F86D00207884F874009C +:1034F000D4F80700C4F86E00B4F80B00A4F872000A +:10350000D4F80100C4F87500B4F80500A4F87900F7 +:103510003C2084F8680068680088A4F86A000120EC +:1035200084F866006E7070BDF70E0020F80D002064 +:10353000A80000202DE9F041FF4F044600207A78D2 +:10354000FE4D4FF00108064612B1012A08D00DE0E9 +:1035500095F8492052B1002908BF87F8018004E09E +:10356000AA7F1AB1002908BF7E7001207A782B2328 +:1035700012FB03F22A44937F184312D021BB02F1BD +:103580001F012A22A01C07F05FFC66700420207037 +:1035900084F8028078782B2110FB01F0284486778C +:1035A00012E0287801281CBF0020BDE8F08159B93D +:1035B0006670132020701C22A91CA01C07F044FC7C +:1035C000A6712E7085F89F600120BDE8F081DB4870 +:1035D0000178002914BF80884FF6FF7070472DE9ED +:1035E000F041D64C0546A07F002818BFBDE8F08109 +:1035F000284605F05DFC00210126072834D2DFE8CB +:1036000000F004070C3333330E0084F8201009E077 +:1036100084F8206084F828100BE0032000E00220EA +:1036200084F8200004F12901284605F098FC84F86C +:103630002800284605F05EFC84F8210004F12201F0 +:10364000284605F040FCBC4D04F1480728787F2847 +:1036500008BFFFDF287838707F202870A677BDE884 +:10366000F041032001F025BB84F82810BDE8F0816B +:1036700010B5002001F0AEFAB04CA0B1FEF747FE45 +:1036800000210120FEF7E0FC04F1B800FEF753FE34 +:10369000D4F8A800FEF752FE94F88400032818BF5F +:1036A00002281FD022E0FEF7ADFEFEF79FFEFEF7D8 +:1036B000C1FDFEF724FE94F8A10030B1FEF7BFFE75 +:1036C000FEF713FA002084F8A100012084F8AC0072 +:1036D000022084F8A300FEF72BFEBDE81040002076 +:1036E00001F0E7BA01210020FEF7E7FEFEF7C2FE77 +:1036F00094F8A10018B1FEF7E4F9FEF78FFE03205D +:1037000084F8A30010BD8D490028B1F8AE202CD05C +:10371000FF2A0BD24FF6FF7000EA4200A1F8AE007C +:10372000FF2888BFFF2001D9A1F8AE008248426877 +:10373000012A12BF002A0D224260D243C2EBC2030B +:1037400003EB021291F8AD30DB4303EB830CCCEBBF +:1037500083131A444260900CB1F8AE20B0FBF2F330 +:1037600002FB130081F8AD007047012ADED9500832 +:10377000A1F8AE0008BF0120D8D1D5E770B56F4CD5 +:1037800094F8A300022819BF94F8A3000128002090 +:1037900005461CBF0C2070BD2B2101FB00418D771D +:1037A000401CC0B20228F7D3257094F8A10028B1BC +:1037B000FEF745FEFEF799F984F8A15084F89D5074 +:1037C00084F89E5084F89F5084F8A050012084F81B +:1037D0007E0084F8845084F8A25084F87B0084F83A +:1037E0007C0084F87D00606FA16FE26FD4F88030B8 +:1037F000C4F88800C4F88C10C4F89020C4F8943041 +:10380000D4F88400C4F8980084F89C50002070BD5F +:103810004A4A10B5002382F8A330C2E92C010120E6 +:1038200082F8A300FFF7AAFF002818BFFFDF10BD32 +:103830002DE9F047414C81460C2794F8A30001285C +:103840001FBF94F8A30002280C20BDE8F087FEF704 +:1038500067FD0020FEF775FA94F89C004FF0010810 +:10386000002844D0D4F88800D4F88C10D4F89020E4 +:10387000D4F894306067A167E267C4F88030D4F868 +:103880009800C4F88400002684F89D6084F89E6047 +:1038900094F87B00002801BF94F87C00002894F87D +:1038A0007D0000281ABF94F8A000002884F89C60CE +:1038B00023D094F88400032802D0022805D008E021 +:1038C00005211F4800F0F5FC03E003211C4800F02F +:1038D000F0FC94F87A1004F17400FEF7AEFA0027B9 +:1038E00084F89C6094F8A300012815D10FE094F8A7 +:1038F000A300022808BF0027F4D094F8A3000228F0 +:1039000002BF84F8A3800C20BDE8F08704E084F8AF +:10391000AC80022084F8A300D4F8B400017819B177 +:1039200010F8041BFEF7BBFAD4F8B000017879B1A7 +:10393000044A401C08E00000B0000020000F0020F6 +:10394000E00F0020BB0F0020FEF7A9F884F8A1804B +:10395000FD48C4F8A890FEF7CCFCFEF7E9FC384619 +:10396000BDE8F08770B5FEF7DBFCF84C94F8A300D7 +:10397000022803D0FEF7DCFC0C2070BD012084F887 +:10398000AD00A4F8AE000220FEF7C7FCF048FEF739 +:10399000DFFAF04B002004F17B0200BF94F8A21084 +:1039A000491CA3FB015C4FEA5C0CACEB8C0C614442 +:1039B000C9B284F8A210895C012907D0401CC0B2AA +:1039C0000328EBD3FFF754FE002070BD94F8A2004B +:1039D000E149085CFEF7C4FA0020FEF7A1F9F1E71F +:1039E000DA4B10B44FF0010C83F89EC093F89F405F +:1039F000002C1EBF3A2010BC7047002418B993F861 +:103A00008E0088420FD183F88E1083F89D40106895 +:103A1000C3F888009088A3F88C0083F89DC083F8D1 +:103A2000A0C083F89CC083F89E4010BC0020704763 +:103A30000300C6494FF000004FF0010208BF81F8B3 +:103A4000922005D0012B16BF122081F892007047FA +:103A500081F89C2081F899307047BC4A032808BF40 +:103A6000C2F8941082F89800012082F89C0000208F +:103A70007047B64890F89C1029B190F8990000283A +:103A800008BF704704E090F88500002808BF704721 +:103A90000120704710B5FEF7B5FCFEF7A7FCFEF756 +:103AA000C9FBFEF72CFCA94C94F8A10030B1FEF73D +:103AB000C6FCFEF71AF8002084F8A100012084F863 +:103AC000AC00022084F8A300FEF732FC002010BDF9 +:103AD0009E4981F8A400704710B5FEF793FCFEF7ED +:103AE00085FCFEF7A7FBFEF70AFC984C94F8A100B2 +:103AF00030B1FEF7A4FCFDF7F8FF002084F8A10028 +:103B0000012084F8AC00022084F8A300FEF710FC2A +:103B1000BDE81040002001F0CCB82DE9F05F002690 +:103B2000DFF83882894C7F2780B104F1B80005F0B6 +:103B30008CFA20B904F1B80005F0A7FA30B194F876 +:103B4000840003280DD194F89E0050B194F8A3008E +:103B5000052828BFBDE8F09FDFE800F0BABABAF543 +:103B6000F40094F8A3007E4D4FF0010A052880F080 +:103B70006082DFE800F0FBFBFB03FA00784805F009 +:103B800097F97649887094F87E0030B9FEF7DCF931 +:103B9000002808BF4FF0000801D04FF0010894F84A +:103BA000A100002818BF4FF0280915D0A9F1010085 +:103BB00000F0FF09FDF7B9FF8346022803D1B9F1F0 +:103BC000000FF3D1FFDFB8F1000F14D1BBF1010FEB +:103BD00018BF4FF000080ED0DFF880914FF0020BB5 +:103BE00099F80200072880F08281DFE800F073F77F +:103BF00007F6F6F625004FF00108EDE794F8A1006E +:103C000018B1FEF71CFCFDF770FF5448FEF73DFCB1 +:103C1000002808BF89F80070FEF722FCB8F1000FF9 +:103C200000F05F8194F88400012818BF022840F05A +:103C30005881FEF7FFFAEBE094F8A10018B1FEF707 +:103C4000FEFBFDF752FF4548FEF71FFC002808BFAA +:103C500089F80070FEF704FCB8F1000F00F0418114 +:103C600094F88400022803D001287DD000F039B9EF +:103C70003B48FFF7B4FC012000F0ACFF58B13949D4 +:103C8000A1F1280005F043F93648FEF754FB94F8FB +:103C90009D00A0B190E0FEF7B5FBFEF7A7FBFEF795 +:103CA000C9FAFEF72CFB94F8A100002870D000BFE1 +:103CB000FEF7C5FBFDF719FF84F8A1609DE0012127 +:103CC0000846FEF7FAFBFEF75EFB052084F8A3002A +:103CD000BDE8F09F94F8A10018B1FEF7B0FBFDF726 +:103CE00004FF1E48FEF7D1FB002808BF89F80070CA +:103CF000FEF7B6FBB8F1000F71D094F884000228EB +:103D000047D0012830D003281CBFFFDFBDE8F09F5B +:103D1000E978D4F88000827E914231D12979C27E3F +:103D200091422DD16979027F914229D1A979427FAF +:103D3000914225D1E979827F914221D1297AC27FAE +:103D4000914214E08EE177E15CB50100000F0020A4 +:103D500062B50100ABAAAAAA5FB50100B0000020BD +:103D6000B80F0020E00F002052E0CFE061E107D162 +:103D70002978427EC1F38011914208BF012100D011 +:103D8000002194F88520012A48D0002927D0A0E0FE +:103D900033E0FE48FFF723FC012000F01BFFF8B1E1 +:103DA000FB49A1F1280005F0B2F8F948FEF7C3FA83 +:103DB00094F89D00002882D0D4F888006067B4F899 +:103DC0008C00A4F8780004F17401F14805F074F84F +:103DD00084F89D6084F89E6071E788E02CE07FE0C5 +:103DE000FEF710FBFEF702FBFEF724FAFEF787FA58 +:103DF00094F8A10000287FF45BAF84F8ACA084F8AD +:103E0000A3B0FEF795FABDE8F05F002000F051BFC7 +:103E1000DE48FFF7E4FBBDE8F05F29E4F1BB00BF3B +:103E200000F11A01D94805F04EF8D84805F062F8BB +:103E3000D4F8801048764CE094F8A10018B1FEF751 +:103E4000FEFAFDF752FED348FEF71FFB002808BF1D +:103E500089F80070FEF704FBB8F1000F41D0FDF7C0 +:103E6000F4FFE8B394F88400032808D0C748FFF7AC +:103E7000B6FBFEF7DFF9BDE8F05FFFF7F9BBD4F85A +:103E80008000E978827E91421DD12979C27E9142DB +:103E900019D16979027F914215D100E019E0A97921 +:103EA000427F91420FD1E979827F91420BD1297AE9 +:103EB000C27F914207D12978427EC1F3801191429D +:103EC00008BF012100D0002194F88520012A04D0E8 +:103ED00031B1BDE8F05F00F091B90029F9D19FE759 +:103EE000FFE7FEF7A7F9BDE8F05FFFF7C1BB94F865 +:103EF000A10018B1FEF7A3FAFDF7F7FDA548FEF7FC +:103F0000C4FA002808BF89F80070A3E09F4804F0B5 +:103F1000CFFF88F802009E48E978427A91421CD18E +:103F20002979827A914218D16979C27A914214D161 +:103F3000A979027B914210D1E979427B91420CD15F +:103F4000297A827B914208D129780078C1F38011C7 +:103F5000B1EBD01F08BF012500D00025FEF76AF99C +:103F600098F8020004284ED1EDB38A48FEF78DFA86 +:103F7000002808BF88F80070FEF772FA94F8AC00C9 +:103F800000281CBF0020FFF7BEFB84F8ACA07F4DCB +:103F900094F8490040BB042084F84B00284604F004 +:103FA000A9FF002808BF84F84C6003D0012808BF8F +:103FB00084F84CA004F14D01284604F084FF04F17C +:103FC0005401284604F0F7FF84F853001F2884BFEB +:103FD0001F2084F8530004F1730598F800007F282F +:103FE00008BFFFDF01E00EE009E098F8000028704C +:103FF00088F8007084F849A0042000F05AFEBDE85B +:10400000F05FFFF735BB6348FEF73FFA002808BFB3 +:1040100088F80070FEF724FA94F8AC00002804BF7A +:104020000120FFF770FB84F8AC60BDE8F05FFFF79C +:104030001FBBFFDFBDE8F09F94F8A10018B1FEF7A9 +:10404000FEF9FDF752FD5348FEF71FFA002808BF9E +:1040500088F80070FEF704FAFEF7ECF8BDE8F05FB0 +:10406000FFF706BB4B48FEF710FA002808BF88F898 +:104070000070FEF7F5F994F8AC00002804BF0120A9 +:10408000FFF741FB84F8AC60FEF7D4F8BDE8F05FC1 +:10409000FFF7EEBA70B5404C94F8A30007285ED243 +:1040A000DFE800F05D5D5D5D5D040D003748FEF703 +:1040B00042F9FEF7DFF9042084F8A30070BDFEF793 +:1040C000A1F9FEF793F9FEF7B5F8FEF718F9012507 +:1040D00084F8AC50022084F8A300FEF729F9207878 +:1040E000002818BFFFDF0020A070D4F880000188EE +:1040F000A180417EE171D0F81A10A160C18BA1812D +:104100004188E18281882183C088608394F8A4007B +:10411000207794F87A00A073606FC4F80F00B4F8A9 +:104120007800A4F8130094F8A10018B1FDF7FDFC85 +:10413000012809D0607F20F0010060772570BDE87C +:104140007040022000F0B5BD607F40F00100607754 +:10415000FDF708FD617F60F347016177EEE7FFDF60 +:1041600070BD70B50C4C94F8A3000025052828BF3D +:1041700070BDDFE800F04242422403000548FEF72C +:1041800084F910B903497F20087007E0B80F0020B8 +:10419000E00F0020B0000020000F0020FEF760F9C3 +:1041A00094F8AC00002804BF0120FFF7ACFA84F8B3 +:1041B000AC50FEF73FF8BDE87040FFF759BAFEF784 +:1041C00021F9FEF713F9FEF735F8FEF798F894F8A1 +:1041D000A10028B1FEF733F9FDF787FC84F8A15060 +:1041E000012084F8AC00022084F8A300FEF7A0F8B8 +:1041F000BDE87040002000F05CBD70BD70B50220CD +:1042000000F0E8FC0025604C0126A0B3012000F07E +:1042100050FD04F1E001A1F1280004F078FED4F88B +:104220008000C18A04F1E00004F0F1FED4F88000BF +:10423000017D04F1E00004F0EEFE04F1E000FEF781 +:104240007AF894F89D0080B1D4F888006067B4F8DB +:104250008C00A4F8780004F1740104F1E00004F08B +:104260002BFE84F89D5084F89E5084F89F600620B1 +:1042700084F8A30070BDFFE7FEF7C4F8FEF7B6F8B8 +:10428000FDF7D8FFFEF73BF894F8A10028B1FEF740 +:10429000D6F8FDF72AFC84F8A15084F8AC6002201F +:1042A00084F8A300FEF744F8BDE87040002000F059 +:1042B00000BD70B5344C0546032952D0052918BFFE +:1042C00070BD04F0D3FD0521284604F0D2FD94F81A +:1042D0007A10284604F005FE04F17401284604F023 +:1042E000EBFDD4F8800000F10D01284604F079FEC2 +:1042F000D4F8800000F11101284604F076FED4F8CD +:104300008000017D284604F086FED4F88000C18A32 +:10431000284604F07CFED4F880004188284604F04A +:104320006AFED4F880008188284604F068FED4F83C +:104330008000C188284604F066FED4F8800000F1B1 +:104340000801284604F07EFED4F88000017E28464D +:1043500004F063FE94F8A4102846BDE8704004F011 +:1043600066BE04F083FD0321284604F082FD94F824 +:104370007A10284604F0B5FD04F174012846BDE822 +:10438000704004F099BD0000000F00202DE9F047B7 +:10439000744E054684B096F800040C46DFF8C8A1B8 +:1043A00040099AF800144909884218BFFFDF96F8BF +:1043B000000440096D4991F800144909884218BF6A +:1043C000FFDFDFF8AC816E1E08F13809002709EB2A +:1043D0004505092C80F0C280DFE804F005323C3C42 +:1043E00037C0C0C070000B2EA8BFFFDF35F8020C2D +:1043F0000621F9F714FB040008BFFFDF0B2EA8BF4E +:10440000FFDF35F8020C2188884218BFFFDF94F8DF +:104410009800002808BFFFDFC8F8047088F8017012 +:10442000C8F80C70606AB0F5717F88BFA0F23737AA +:104430002046C8F8087004B0BDE8F04702F0CDB9D6 +:1044400004B0BDE8F04702F024BA04B0BDE8F0477C +:10445000FEF7F8B89AF8140D4649400991F800148F +:104460004909884218BFFFDF0B2EA8BFFFDF35F8D0 +:10447000020C0621F9F7D3FA040008BFFFDF0B2E68 +:10448000A8BFFFDF35F8020C2188884218BFFFDF84 +:10449000204602F0B4FA002818BFFFDF00222146B0 +:1044A000684600F0E7FC94F8A2006946FBF7BCFD03 +:1044B000208E401C208604B0BDE8F0870B2EA8BFDC +:1044C000FFDF35F8020C0621F9F7A9FA040008BF4E +:1044D000FFDF0B2EA8BFFFDF35F8020C21888842D2 +:1044E00018BFFFDF94F89800042818BFFFDF84F896 +:1044F000987094F8A2504FF6FF76681E0B28A8BF5C +:10450000FFDF09EB450020F8026C94F8A200FBF7EE +:1045100025F984F8A270D4F8A800002804BFD4F8C4 +:10452000A400C8F8100008D0D4E92B121144826905 +:1045300011448161D4E92901C860D4F8A40000289D +:1045400019BFD4F8A8100161D4F8A80087610A48FF +:10455000007804B0BDE8F047F5F724B8FFDF04B0F9 +:10456000BDE8F08701E000E00BE000E018E000E0CB +:104570000810002019E000E0B80000202DE9F04705 +:10458000FD4E07460024F08B401C80B2F083327849 +:10459000A046002A08BFFFDF09D0F74B042AA3F189 +:1045A00014095D6813D0052A18BFFFDF44D02146E7 +:1045B0003069FBF7ABFB306187F80080012139716E +:1045C000B860B06800F22710F860BDE8F0870A28EC +:1045D0002CBF02200320787100297BD0D6F810A0D0 +:1045E000D9F8104034B3A146E468002CFBD1B9F1EE +:1045F000000F1FD099F80000002808BFFFDFD9F88E +:104600001410D9F8040001445046FCF705FB0028BB +:1046100007DA291A4A1E92FBF5F202FB0504294625 +:1046200004E090FBF5F202FB150429468C4288BF9A +:10463000FFDFBCE74446BAE702207871002953D077 +:10464000D6F818A0BAF1000F08BFFFDF0025DAF88E +:10465000AC20D9F810402846691E5CB1A069904290 +:1046600028BF814284BF014625462046E468002CCD +:10467000F4D105B905460AF19804CAF8A850002DEE +:1046800004BFC4F80C80C9F8104005D0E868EC609D +:10469000E060002818BF0461D4F81090C4F81880B6 +:1046A000B9F1000F0ED0D9F8180048B1D4F814A011 +:1046B000504538BFFFDFD9F81800A0EB0A00A06111 +:1046C000C9F81880002D08BFC6F8208009D02878C6 +:1046D000002800E008E008BFFFDF69696868084457 +:1046E000306240F6B83462E72C4660E72DE9F041CD +:1046F000A24C804684B094F800040E46A04F4109B5 +:1047000097F800044009814218BFFFDF94F80004C5 +:1047100040099C4991F800144909884218BFFFDFFD +:1047200000250122092E944C5ED2DFE806F0051B1D +:104730003636315D5D184C00627322736078002854 +:104740001CBF04B0BDE8F0818F484560C56025738B +:10475000A068CD38FFF76CF8002818BFFFDF04B061 +:10476000BDE8F081607850B1207B002808BFFFF7DA +:1047700091F9657304B0BDE8F041FAF736BFA27352 +:10478000FFF7F0F8002818BFFFDF04B0BDE8F081A4 +:1047900004B0BDE8F041FDF755BF97F8140D7B4913 +:1047A000400991F800144909884218BFFFDF01222F +:1047B00000216846FFF7E2FE69464046FBF734FCFD +:1047C00004B0BDE8F0812078052818BFFFDF207F06 +:1047D000002808BFFFDF25772570207DFAF7BEFF90 +:1047E000257504B0BDE8F081FFDF04B0BDE8F081BD +:1047F0002DE9F041604C84B00025207804281FBFCB +:10480000207805280C2004B018BFBDE8F0810127EE +:104810006770607B002690B172B6607B00281CBF79 +:10482000A07B002805D0FFF735F96673A673FAF769 +:10483000DCFE62B6207DFCF779FAD0B913E094F87B +:10484000148003208DF804008DF80500FAF79CFF12 +:1048500002904FF0FF3003908DF80070694640469B +:10486000FBF7E2FBE6E720BF207DFCF75FFA0028BC +:10487000F9D0207F28B126772078052818BFFFDFE0 +:104880000C2566702670207DFAF768FF267504B047 +:104890002846BDE8F0812DE9F047374884B000781C +:1048A000002818BFFFF7A4FF0120374E307069467B +:1048B0000620F9F740F8002818BFFFDF00254FF663 +:1048C000FF7718E0029800281CBF90F89810002984 +:1048D00011D00088B84218BFDFF8B48045D0062157 +:1048E000F9F79DF8040008BFFFDF94F8A200FCF779 +:1048F0001DFA68B905E06846F8F7FBFF0028E1D02B +:1049000033E020BF94F8A200FCF710FA0028F8D09A +:1049100084F8985094F8A2904FF6FF7AA9F101001C +:104920000B28A8BFFFDF08EB490020F802AC94F881 +:10493000A200FAF713FF84F8A25069460620F8F7A0 +:10494000FAFF002818BFFFDF0AE0029800281CBF0A +:1049500090F89810002903D00088B842BFD104E035 +:104960006846F8F7C6FF0028EFD03570356104B00F +:104970000020BDE8F08700001C10002001E000E0EE +:104980000BE000E018E000E00810002019E000E073 +:104990004010002010B50078FE4C60B101280CBF1B +:1049A00040F6C410FFDF06D0A06841F66A018842D5 +:1049B00028BFFFDF10BDA060F6E710B5F54C00235F +:1049C0002070F54803704370037703734373837358 +:1049D0008361037524304FF6FF7101800522418009 +:1049E00020F8041F521EFAD1180008BFA36005D09A +:1049F000002B0EBFFFDF40F6C410A060A06841F698 +:104A00006A01884228BFFFDFBDE8104043E770B568 +:104A1000E14C0E4684B02178154600291EBF0C20BB +:104A200004B070BD416A01F29731C0F8AC10A061CA +:104A300090F89800002818BFFFDF40F2712006FBB5 +:104A400000F168430A30C4E90110A1F53D718842C4 +:104A500088BF0846A060D1490020C86005212170A8 +:104A600060702077E083CE48FAF729FE2075002891 +:104A700008BFFFDFFAF788FE2061002201216846A7 +:104A8000FFF77CFD207D6946FBF7CEFA04B00020DD +:104A900070BD884234BF012200220244D2B281425A +:104AA00034BF012000200844C1B28A4234BF084606 +:104AB0001046831AA0EB010C114401EBC1026344C0 +:104AC00002EB411103EB83031B0100EB400203EBFC +:104AD000C10102EB001201EBC201C0EBC00202EB0C +:104AE000401001EB8000983870474FF44B72B1F5DD +:104AF0004B7F38BF114641627047A74800780028B5 +:104B00001CBF0020704710B50620F8F725FF80F085 +:104B1000010010BD10B5A04C84B02278002A1EBF41 +:104B20000C2004B010BD40F27122424340F27120CB +:104B300048430A30C4E90120A2F53D71884298BF7C +:104B400001460020A160607004212170E083944838 +:104B5000FAF7B5FD2075002808BFFFDFFAF714FE4D +:104B600040F6B831FBF7D2F82061002201216846F7 +:104B7000FFF704FD207D6946FBF756FA04B00020DC +:104B800010BD70B5844CA1690160FFF731FE0023B0 +:104B900008B1A36170BDA169D1F8A8205AB1D1E9CB +:104BA0002BC5AC449569AC44C2F818C0D1E9292C96 +:104BB000CCF80C2005E0DFF8E4C1D1F8A420CCF853 +:104BC0001020D1F8A420D1F8A810002A14BF116138 +:104BD0008B61DEE7714910B54968002801F198043E +:104BE00008BF04F5BC7409D0012808BF04F531746E +:104BF00004D0022814BFFFDF04F5B0746648806853 +:104C0000A0428CBF0120002010BD6448D0E90112F1 +:104C1000914204D20078002804BF01207047002090 +:104C2000704730B55B4D85B0042221B3012908BF20 +:104C300003211CD0022908BF80F8982023D0032923 +:104C40001EBFFFDF05B030BD418840F2E242514354 +:104C5000544A1160D0F8BC100A89C2828A79027560 +:104C60004A8942808A898280C989C180022180F86C +:104C7000981005B030BD044648480078002818BF99 +:104C800084F8982007D0FAF7B0FC287805B0BDE882 +:104C90003040F4F787BC01222146684600F0EAF86C +:104CA00094F8A2006946FBF7BFF9208E401C2086CD +:104CB000E9E72DE9F041374F0025374C397884B0CA +:104CC000052880F0C080DFE800F003146FB8B8005A +:104CD000E5830846F4F766FC6078002875D1002269 +:104CE00011466846FFF74AFC207D6946FBF79CF9B0 +:104CF0006BE0DFF8A880206940F2E243D8F80410A6 +:104D00000844A16900F251604A88983102FB03F51A +:104D1000D8F810208A4208BF002614D0216AFBF779 +:104D20007BFF002807DA291A4A1E92FBF5F202FBE4 +:104D30000506294604E090FBF5F202FB150629461C +:104D40008E4288BFFFDFB868864208D2A06940F271 +:104D500071224188C1824A4306EB420605E040F2D7 +:104D6000E240B6FBF0F0A169C882A0690521017597 +:104D7000C08A6FF41C71484306EB400040F6354191 +:104D8000C8F80C00B0EB410F28BFFFDF04B0BDE84E +:104D9000F0811AE0B80000201C100020081000204C +:104DA000ED460100BC000020E5830846F4F7FAFB5D +:104DB00001202077A0692169C0F89C1080F89850E4 +:104DC0002178052918BFFFDF04D0FAF70EFC6573C0 +:104DD000A573DBE7002808BFFFDFA06990F8980003 +:104DE000002818BFFFDFA06990F8A200002818BFB4 +:104DF000FFDF6048FAF763FCA169064681F8A2006C +:104E00000F88401E0B28A8BFFFDF5B4800EB460061 +:104E100020F8027CA06990F8A200002808BFFFDFFC +:104E200001226846A16900F025F8A069694690F85A +:104E3000A200FBF7F9F8A561C7E704B00846BDE892 +:104E4000F041F4F7AFBBFFDFA0E7704700B54B4A76 +:104E500059B1012908BF401E07D002291CBFFFDF3E +:104E600000BD5178491C5170C01F506000BD4448BE +:104E7000007870472DE9F05F06460C46488840F2FE +:104E8000E24141439046E08A40F2E24200FB02FAEE +:104E900094F898200025394F4FF0030B4FF001098B +:104EA00052B13846012A40682DD0022A16D0032A72 +:104EB00018BFFFDF27D036E0B8F1000F08BFFFDFD3 +:104EC0007868002808BFFFDF7868F968C01D0844CB +:104ED0000AF25D41451884F8989023E0A8F1010199 +:104EE000084308BFFFDF2748B8F1000F006800EB58 +:104EF0000A0505D0786800F20F30A84288BFFFDFAE +:104F000084F898B00EE00D46B8F1000F0AD018B939 +:104F10007878002818BFFFDF786800F20F30A842C9 +:104F200088BFFFDF05B9FFDF2946D4F89C00FAF7F8 +:104F3000EDFEC4F89C000020307086F80490D4F890 +:104F40009C00B060204601F090FD002818BF86F854 +:104F5000059005D0606A00F5E570F060BDE8F09F4F +:104F600094F89800012806BF0220707186F805B0F9 +:104F7000F0E700008D4301004010002008100020E1 +:104F80001C100020BC000020FE48C07E7047FE4878 +:104F900040687047FD48C07E7047884234BF012298 +:104FA00000220244D2B2814234BF012000200844D2 +:104FB000C1B28A4234BF08461046831AA0EB010CE6 +:104FC000114401EBC102634402EB411103EB830383 +:104FD0001B0100EB400203EBC10102EB001201EBED +:104FE000C201C0EBC00202EB401001EB80009C3814 +:104FF00070474FF44A72B1F54A7F38BF114641629B +:1050000070472DE9FF4FDF4E83B08846706A3468E1 +:105010005FEA03090568D4F804B0306A0190298E6C +:105020000598A0EB010080B2009019BF04F1380789 +:1050300004F1480A371D05F1A80A032038710398C6 +:10504000002832D0012800F0DF8002287DD003281C +:1050500018BFFFDF00F00C81B9F1000F1EBF3879D7 +:105060000328FFDFA16A7069FAF750FEB860D4E93F +:10507000081081428EBFCAF800000846CAF8001026 +:10508000696A084400F24F10F860B5F89810059866 +:10509000081A00B2002840F349810398022818BF7B +:1050A000032040F0448100F041B9306A002808BF75 +:1050B000FFDFE98A40F27120484340F2E24101EB10 +:1050C00040010020B8F1000F06D0B14808FB01F103 +:1050D000B1FBF0F000F10100A061698840F2E2420A +:1050E00001FB02F24FF0000106D0A94908FB02F2D1 +:1050F000B2FBF1F101F10101E161316A40F271238A +:1051000001F10101A162EA8A02FB03F2C0EB420253 +:1051100002F237421144A1622A7D40F2E24312FBBF +:1051200003F202EB400000F2151020626062306A68 +:10513000A1EB00009749A0F1010009188CD2B0F54D +:10514000387F98BFFFDF5CE0FFE7E98A40F2712219 +:10515000E068514300EB41010020B8F1000F06D098 +:105160008B4808FB01F1B1FBF0F000F10100A061F8 +:10517000688840F2E24100FB01F14FF0000006D0E8 +:10518000834808FB01F1B1FBF0F000F10100E061A0 +:10519000306A002808BFFFDFB5F8AE00E98A0028B2 +:1051A00040F27122E06801FB02F100EB4100A169CD +:1051B000A0EB010003D13168D33849680844A062EC +:1051C0002269A168A06901FB0200297D40F2E24248 +:1051D00011FB02F101EB400000F21310206269881C +:1051E0005210E0695143C0EB4100A0F54770606286 +:1051F000A06A316A401AA0F5AA7167484018BFF446 +:105200002BAF0120387127E7B5F8AE00002808BFA2 +:10521000FFDF306A002808BFFFDF698840F2712293 +:10522000E0695143C0EB4101A162B5F8AE3022699B +:10523000D4F818C0D4F808809B1A08FB02C203FBFC +:1052400000202A7D40F2E24312FB03F202EB400011 +:1052500000F213102062A1F547706062306A081AEC +:10526000A0F5AA714C484018BFF4F6AEC9E700BFDC +:10527000B9F1000F1CBF94F83400002803D007B028 +:105280000220BDE8F08F698840F27122E069514345 +:10529000C0EB410100984843A062B5F8AE0030B3BE +:1052A000BBF1000F18BFFFDFB5F8AE100098002269 +:1052B0000844E169484302EB400000F21310206209 +:1052C000688840F271225043C1EB4000A0F547705E +:1052D000606232484068B0B1A26A01990120511A57 +:1052E000A1F5AA722C49891838BF3871B4E6BBF110 +:1052F000000F1ABF01980028FFDFABF1D301A06AAD +:105300000844A062D0E7FAF73FFA726901461046F6 +:10531000FBF782FCA16A081AA0F24F111E48401840 +:105320003EBF012007B0BDE8F08F95E60020787100 +:105330001098C8B1B5F8C01000290CBF0020B5F80E +:10534000C200A5F8C20095F8C420401C5043884212 +:105350000AD27879401E002806DD01207871B5F860 +:10536000C200401CA5F8C20087F80090B9F1000FF8 +:105370001CBF94F83400002881D189F0010084F822 +:1053800035000DE058100020DC00002080100020C7 +:1053900040420F00DBF7FFFFF4F8FFFFCC000020D6 +:1053A000307FF27E3946B37E9A4202D0FAF73CFE55 +:1053B00004E00020F076B0763060706207B0002024 +:1053C000BDE8F08F70B5FA4D0929D5E900326FD2EA +:1053D000DFE801F0055B737B6F8E8E588A0000203A +:1053E0001062D17E04294ED2DFE801F04D4D024516 +:1053F000516A0C681168087011684860106890F86C +:10540000350040B9FAF7C0F969680968096CFBF71B +:1054100003FC002818DC686801684A8E218E8A42E5 +:1054200006D1B4F89C20511AA4F89E10228605E0FB +:10543000511AA4F89E100168498E21860268C1683D +:105440001164C168416111E068680168098E228EAB +:10545000891AA4F89E100168098E218601680A6CD9 +:10546000C2600A6C4261886CC4F8A8002046BDE89E +:10547000704002F026BAD0685061FDF7ABFC0028FE +:1054800018BFFFDF70BDFFDF70BDD07E04280DD2D6 +:10549000DFE800F00C0C0206BDE8704002F0E1BA53 +:1054A000FDF7D9FD002818BFFFDF70BDFFDF70BD1D +:1054B0001EE0BDE87040FDF7C5B8D87E02280FD0C9 +:1054C000D87E032818BFFFDF06E0D87E022807D069 +:1054D000D87E032818BFFFDFBDE8704000F0B5BBE1 +:1054E000BDE8704000F0FCBBBDE87040FAF736B98B +:1054F000FFDF70BD2DE9F047AD4D0024AD4E824673 +:105500000F464FF0010809294ED2DFE801F0053BB4 +:1055100046463B4D4D4646006868DFF898920028A5 +:1055200018BFFFDF39465046C5F80490FFF74AFF21 +:10553000F07E022818BFBDE8F08768680568406AF9 +:105540000768FAF704F97A8840F27123E9695A4347 +:10555000C1EB4201AB39B72898BFB72000F54A70BC +:10556000081A796AA0F20130B1F5717F88BFA1F500 +:105570007174844238BF2046E862306880F8348015 +:10558000BDE8F0875046FFF71DFFF07E022804BFFC +:10559000306880F83480BDE8F08750462E60FFF711 +:1055A00011FF2C60BDE8F087FFDFBDE8F0872DE933 +:1055B000F0417F4C07460D4609291ED2DFE801F075 +:1055C00005101414101D1D14140060687A4E002874 +:1055D00018BFFFDF294638466660BDE8F041F1E6B6 +:1055E0003846BDE8F041EDE6734820603846FFF7E5 +:1055F000E9FE00202060BDE8F081FFDFBDE8F0811A +:10560000F0B56C4985B00026CA7E694C032A03D0E8 +:105610002831CA7E032A64D10025216000B3012805 +:1056200006BF03208876FFDF0AD02068002E0560C1 +:105630004562256055D06148456005B00020F0BD49 +:105640002068C17E29B1C17E827E914208BF20BF01 +:10565000F6D0C17E00290CBF012600268576E4E73E +:105660000026032708468F76C97E032904D0C07E12 +:10567000002808BF012631E00120FDF70BFD20685E +:10568000007F002808BFFFDF2068067F8DF80470C8 +:105690008DF80570FAF778F802904FF4FA700390DD +:1056A00001208DF8000069463046FAF7BDFC2068FD +:1056B000007FFBF73BFB30B920BF2068007FFBF782 +:1056C00035FB0028F8D02068007FFAF747F82068FB +:1056D0000577C57685760560012645622068857662 +:1056E000A3E705B00C20F0BD10B5324800F076FB02 +:1056F000314800F073FB3249002008752F4948708B +:105700002C49486101F12802506188769076284939 +:105710004860086010BD2DE9F0412A4C064694F817 +:105720000004294D400995F800144909884218BF22 +:10573000FFDF94F800044009244991F80014490956 +:10574000884218BFFFDF95F8140D4009204991F8F1 +:1057500000144909884218BFFFDF1E48154D002478 +:105760000670EC76AC7605F12806F476B476103047 +:105770000121017104606C6274622C6000F1080701 +:10578000346028467C6000F029FB05F1280000F019 +:1057900025FB05F1500004757C706C617461AC767A +:1057A000B476A7F1100044600460BDE8F081000009 +:1057B000CC0000205810002080100020DC000020C9 +:1057C000A810002001E000E00BE000E018E000E09D +:1057D00019E000E0C4000020F849087170472DE985 +:1057E000F843F7490546CA7EF64C01F12800002A25 +:1057F00004BFC27E002A73D0C97E022907BFC17EC2 +:1058000000290C20BDE8F8832060EF48F9F757FF26 +:1058100021680877ED4845602168086014384862BF +:10582000ADB1012105F1C400FBF768FD0620F8F7D2 +:10583000A1F806460720F8F79DF895F8C410304403 +:10584000B1FBF0F200FB1210401C85F8C400206888 +:10585000007F002808BFFFDFF9F779FFDC4909184E +:1058600038BF40F2F65000F26B1087B22068032672 +:10587000C676FDF7B8F921680861FDF7D8F94FF051 +:105880000108002558B3FDF7D2F921684A6A106073 +:105890000868012180F800806846FBF7BAFC9DF893 +:1058A000000042F210710002B0FBF1F201FB12089D +:1058B000F9F76AFF07EB0801FAF728FA2168C860D0 +:1058C0002268167256721571107FD37E111D92F8E0 +:1058D0001AC0634518D0FAF7A7FB19E000E006E00C +:1058E000BC482160F9F7EBFE2168087792E7F9F7E9 +:1058F0004BFF3946FAF70AFA2168C8600868057054 +:10590000086880F80180DBE7D576957615605562EA +:10591000206805830020FDF7BDFB00202560BDE861 +:10592000F8837047F8B5A64EF17E19B906F1280143 +:10593000C97E09B10C20F8BD0221F1769F4FA64D1A +:1059400077623560002438602C750094A3493A7959 +:1059500090F8CC00234631F8122031F810001044A2 +:1059600081B222462046FFF74CFB002818BFFFDF1C +:105970002C610120AC6028756C862C8685F8364039 +:105980003868018E491E018634830020F8BD8D4899 +:1059900010B540680124817E032908BF002409D086 +:1059A0000168497831B1006A8D49884284BF00247A +:1059B000FDF76CFB204610BD8248406801680A78FC +:1059C000521C0A70016A0068C26A914204D8007DC4 +:1059D00001281CBF01207047002070472DE9F843C3 +:1059E000784C774800262060416A00680D6880F88E +:1059F000346095F8A610002904BF007D032850D11B +:105A0000F9F7C2FE2268526901461046FBF704F915 +:105A1000002846DD216840F271274A6A13680A6847 +:105A20005B88D2F81CC07B43CCEB4303B0FBF3F0A4 +:105A30002B8E401C184410860A68B5F89C00118E05 +:105A4000401A00B200282CDD012082F83600B5F89B +:105A50004E00B5F84C10DFF88481401A298E401EA4 +:105A6000084487B216E0496A097938F8111000969F +:105A7000028E95F8CC30007D38F81330194489B285 +:105A80000123FFF7BEFA60B101280DD0022818BF2C +:105A9000FFDF06D021680868028EBA1A12B2002A07 +:105AA000E1DA2660BDE8F88320680068018E491CB1 +:105AB0000186EFE770B5434E00240628756843D28F +:105AC000DFE800F01820030E240D002000F0C3F9D9 +:105AD000EC76AC762C606C62706888B1746070BDD6 +:105AE000404835680078F3F75DFDEC76AC762C60C5 +:105AF0006C6270BD012000F0AEF970680028EDD135 +:105B0000FFDFEBE729680320087570BD686A296824 +:105B10000068CA698A60418840F2E24251432A68BB +:105B2000D160B0F8E810C18290F8E6100175B0F8C5 +:105B3000EA104180B0F8EC108180B0F8EE10C1801E +:105B400029680220087570BDFFDF70BD70B51D4D5E +:105B5000002470B1012812D002281CBFFFDF70BDE5 +:105B600000F0D5F96868C47684760460446220B990 +:105B70003BE000F0CCF96868B0B36C6070BD686859 +:105B800001684C70C4768476104E04604462002133 +:105B9000706802F0FDFE706880F8E24080F8E34033 +:105BA000FFF7C0FE002818BFFFDFF9F71EFD0D4804 +:105BB0006C600078F3F7F6FC6C6070BDD4000020D8 +:105BC00058100020CC000020AF550100DC00002060 +:105BD0000AFAFFFFF5540100A810002066B5010085 +:105BE000CF821300C4000020FFE7FFDFC5E7E749CD +:105BF0004968CA7E022A18BF70470A681378002BCA +:105C000018BF704750600968CA6A10442838C862D3 +:105C10007047DE4A00B5526841B1012908BF401EF5 +:105C200004D0022916BFFFDFC01F00BD106200BDF7 +:105C3000D748C07E00281CBF0020704710B5072041 +:105C4000F7F78AFE80F0010010BD38B5CF4C206810 +:105C500001684978012932D001216846FBF7D9FA59 +:105C60009DF8000042F210710002B0FBF1F201FB5E +:105C700012012068426AC06812681144FAF746F8B7 +:105C80002168C860C249226803208A4205D0118B6E +:105C90000A2924BF0221517203D2118B491C11839E +:105CA0005072107200231371107F92F81BC0111DE7 +:105CB000947EA4450FD0BDE83840FAF7B5B9C06866 +:105CC0004FF47A71FAF722F82168C860FCF78BFF6D +:105CD00021680861D6E7D37693761360536238BDA6 +:105CE0002DE9F843A94E3068416A04680D6894F8BC +:105CF000351031B1618E2A8E914202BF407A002860 +:105D0000FFDFF9F741FD3268526901461046FAF7A4 +:105D100083FF33684FF000090028596A096808BFFB +:105D200048460AD01A68498840F2712CD26901FBB2 +:105D30000CF1C2EB4101B0FBF1F02A8E618E02EB57 +:105D4000000C6145AEBF481C401C1044608694F8AE +:105D5000360030B9608EB5F89C10884204BF401CF4 +:105D60006086188B8B4F401C1883B5F84E00B5F831 +:105D70004C10401A298E401E08441FFA80F818E083 +:105D80003068406A007937F81000CDF8009095F837 +:105D9000CC1037F81110084481B2207D0023FFF7A2 +:105DA00030F9002808BFBDE8F883012818BFFFDFDD +:105DB00010D0628EA8EB020000B20028E0DA0820C2 +:105DC00085F84A00012085F849002846BDE8F843D7 +:105DD00001F037BA608E401C6086EAE72DE9F04793 +:105DE000DFF8B481694C05464FF01F090027EE7EAD +:105DF000042E23D2DFE806F02922021D454518BFF4 +:105E0000FFDF02202560A8762168C87E28B1C87E01 +:105E10008A7E904208BF20BFF6D0C87E8F760028C9 +:105E20001CBF4FF00C0927600CD10F604F62276038 +:105E30000BE00120FFF7E4FB814600E0FFDFB9F152 +:105E4000000F02D0E87EB042D1D1E87E002818BF12 +:105E5000FFDFBDE8F087F8B54C4D002601286A68E1 +:105E6000516A0C6844D108794A4B33F81010106815 +:105E700090F814C00127BCF1030F06D0027D022A5E +:105E800012D0007D012823D032E0066110688660C0 +:105E9000009794F8CC00B4F89C2033F8100000234D +:105EA000084481B203201EE0B4F8AE2002610097DE +:105EB00094F8CC00B4F89C2033F810000023084478 +:105EC00081B20220FFF79DF8696809680F750CE040 +:105ED000009794F8CC00B4F89C2033F8100000230D +:105EE000084481B20120FFF78CF8002818BFFFDFBB +:105EF000F9F77BFB29480078F3F754FB68680683C1 +:105F00000268218E5186006880F83660F8BD38B589 +:105F10001E4C00200546616809684A78002A18BFAF +:105F20004D702AD1097861B101216846FBF795F9D6 +:105F30009DF8000042F210710002B0FBF1F201FB8B +:105F400012006268516A09680144D068F9F7DEFE00 +:105F50006268D060157103205072107FD37E111DCE +:105F600092F81AC0634502D0FAF75EF803E0D576DE +:105F700095761560556260680583F9F736FB07482A +:105F80000078BDE83840F3F70DBB0000CC000020DE +:105F90008010002066B5010058100020C4000020C9 +:105FA00010B584B004466846FCF721FD002808BF00 +:105FB000FFDF009803F0ADF80321009803F0C3F869 +:105FC0000098017821F010010170214603F01EF9BC +:105FD0000D2C7CD2DFE804F03122075CABABAC15B2 +:105FE0009AABACAC8100FE48806890F8B510009880 +:105FF00003F08BF9FCF70EFD00281CBF04B010BDA8 +:1060000081E0F748806890F89110009803F0CDF98E +:10601000FCF700FD002808BFFFDFA6E0F04880681D +:10602000D0F8C000411C009803F060F9FCF7F2FCC6 +:1060300000281CBF04B010BD65E0E94CA068D0F892 +:10604000BC008179009803F025F9A068D0F8BC0065 +:106050000189009803F017F9A068D0F8BC004189C5 +:10606000009803F0FBF8A068D0F8BC008189009884 +:1060700003F0FBF8A068D0F8BC00C189009803F0D9 +:10608000FBF8FCF7C7FC00281CBF04B010BD3AE0C9 +:10609000D34CA068D0F8BC00011D009803F039F97A +:1060A000A068D0F8BC0000F10C01009803F03BF9A7 +:1060B000A068D0F8BC0000F11E01009803F039F987 +:1060C000A06800F18801009803F041F900E02EE09B +:1060D000FCF7A0FC00283CD145E0C14C6069017888 +:1060E000009803F04CF960698188009803F049F941 +:1060F00060694188009803F048F9FCF78BFC0028A0 +:106100001CBF04B010BDFFDF04B010BD0020029022 +:1061100003909DF8080002A940F001008DF80800E6 +:10612000009803F044F9FCF775FC90B91BE0FFDF21 +:10613000FCF770FC002808BFFFDF0C2C04BF04B084 +:1061400010BD072C11D0012C19BF002C022C04B05B +:1061500010BD0021A2488068A0F85210012180F8EB +:10616000561004B010BDFFDFF3E79D490020896899 +:10617000A1F8580004B010BD2DE9F843984D04462D +:106180004FF000066878084368702846A988806840 +:1061900011F0200F18BFA0F84C6004D1B0F84C20CB +:1061A000521CA0F84C2011F0600F4FF0010707D0EF +:1061B00090F83E1021B980F83E700121FEF731FDC4 +:1061C0004FF00808002C40F018826878002840F052 +:1061D0001681287910F0040F0DD0A86890F83B00C4 +:1061E000052808BFFFDFA86890F83D10022904BF0A +:1061F0002F7080F83D60287910F0020F00F0CD80FC +:106200006878002840F0C980E868C0780D2880F0E0 +:10621000C380DFE800F04333076FC1C1851823C195 +:1062200052649000A8680023012190F83D2030308E +:1062300002F0D3FD00283FD1A868032180F83D106B +:1062400080F856608DE0A8680023194690F83C203D +:10625000303002F0C2FD00287ED19EE0A868002305 +:10626000194690F83B20303002F0B7FD002808BFF7 +:10627000FFDF0920A96881F83B008EE0A8680023B1 +:10628000194690F83B20303002F0A7FD002808BFE7 +:10629000FFDF0720A96881F83B007EE0A8680023A3 +:1062A000194690F83B20303002F097FD002808BFD7 +:1062B000FFDFA86880F83B806FE0A86800231946DC +:1062C00090F83B20303002F088FD002808BFFFDF47 +:1062D000A8680A2180F85B7080F83B105DE0A86830 +:1062E00090F83B000D2818BFFFDFA8680C2180F84C +:1062F0005C7012E0A8680023194690F83B2030300B +:1063000002F06BFD28B9A86890F85C00002808BF6F +:10631000FFDFA8680E2180F85B7080F83B103CE03E +:10632000A86890F83B00132818BFFFDF1520A96864 +:1063300081F83B0031E0A868D0F8BC1003884A8897 +:106340009A4204BF097804290ED0A8680023194690 +:1063500090F83C20303000E002E002F03EFDE0B179 +:10636000A86880F85A6018E090F83B20002319468E +:10637000303002F032FD002808BFFFDFA86890F837 +:106380005E1011F0020F0FBF80F83B7080F856606E +:10639000D0F8BC000670D8E7FFDF287910F0080FAE +:1063A0000AD0687840B9A86890F83D10032903D155 +:1063B0000221297080F83D6000F0E2FBA87810F01F +:1063C000080F19D0A8680023052190F83B20303031 +:1063D00002F003FD70B185F80180A86802E00000BA +:1063E000E4000020D0F8D01008780B2808BF002067 +:1063F000087001E002F039F8A86800F046FB684632 +:10640000FCF7F5FA002800F0F8806878002840F0E2 +:10641000F480A8680023012190F83D20303002F07C +:10642000DCFC002840F0E980A86890F8B41000294E +:1064300018BF022026D190F83B200C2A0ED00D2A3E +:1064400008BF0B201ED0132A08BF06201AD0002335 +:106450000421303002F0C1FCB8B1CEE0FAF7FCFE06 +:106460000C284DD3A8680821D0F8BC001E30FAF7DC +:10647000F4FE28B1A86804218830FAF7EEFE00B9CE +:10648000FFDF0320FFF78CFDB7E0A86890F83C1011 +:10649000012927D0052920D0D0F8BC100A7882B372 +:1064A00049880288914261D190F83B200023194627 +:1064B000303002F092FC20B3A868D0F8BC10097804 +:1064C000022908BF002026D003291BD004293AD076 +:1064D000052908BF08201ED048E00720FFF760FD0F +:1064E000A8680BE00C20FFF75BFDA868A0F85860D7 +:1064F00090F85E1041F0010180F85E1080F83C6079 +:106500007BE033E090F83F1041B190F84000002864 +:1065100008BFFFDF0A20FFF743FD27E0FAF79CFEE4 +:106520000C2823D3A8680821D0F8BC001E30FAF745 +:1065300094FE28B1A86804218830FAF78EFE00B9CD +:10654000FFDF0320E7E790F85E0010F0030F0DD1A6 +:106550000C20FFF725FDA868A0F8526080F856705F +:1065600090F85E1041F0010180F85E106846FCF77B +:106570003EFAE0B3A8680023194690F83B2030307B +:1065800002F02BFC98B3A86890F8C41079B3A969FD +:10659000097861BB018E0A292FD900F10801052273 +:1065A000E86904F025FC0028A86808BF80F8C460EA +:1065B00023D0D0F8C000017851B1411C0522E86910 +:1065C00004F016FC98B9A868D0F8C000007830B97B +:1065D000A868E969D0F8C000401C04F0F4FDA86880 +:1065E000D0F8C0000178491C0170012000E004E0EF +:1065F000FFF7D6FCA86880F8C460A868A14600F13F +:10660000300490F8B40030B9627B002301212046A9 +:1066100002F0E3FB10B1208C401C20843D21B9F135 +:10662000000F18D12878022808BF16200ED00128A4 +:1066300004BFA86890F8B60008D06878B0B110F030 +:10664000140F1CBF1E20A07602D005E0A07603E048 +:1066500010F0080F02D0A17667763AE010F0030F31 +:1066600008BFFFDF2A20A076677632E094F8260084 +:1066700028B1608C411C6184A18C884213D294F8AB +:106680002A0028B1208D411C2185A18C88420AD284 +:10669000208CE18B884203D3AA6892F8B42012B907 +:1066A000A28C904203D32220A076677611E0A07BD3 +:1066B0000028A08B05D0884228BF84F81A80CBD24E +:1066C00005E0062803D33E20A076677601E0607ED1 +:1066D00040B1E6722673A673A868BDE8F8430221AC +:1066E000FEF79FBAA868BDE8F8430021FEF799BA03 +:1066F000FE494A788B781A430ED101280AD00879CE +:1067000010F0040F04D0886890F83D00022803D0F0 +:1067100001207047FEF779BA0020704770B5F34C3E +:1067200005460E46A0882843A08015F0020F04D02D +:1067300015F0010F18BFFFDFE66015F0010F18BF5D +:10674000266115F0020F13D0304602F085FD0628B1 +:1067500002D00B2830D00BE0A06890F83B10132932 +:1067600006D10021C0E91C115FF0010180F8401042 +:1067700015F0800F1CBF0820A07015F4806F08BFB3 +:1067800070BDA168088E89880844801D85B2304696 +:1067900002F062FD012817D0304602F05DFD0028AE +:1067A00018BF70BDA0682946D0F8BC00858030466F +:1067B000BDE8704002F072BDA06890F83B100D2952 +:1067C00008BF0021D4D1D1E7A0682946A0F8C6505F +:1067D0003046BDE8704002F091BDF8B5C34C0026CC +:1067E0000546A060A6806670A67026700088FCF73B +:1067F000FBF8A0680088FCF71DF9B5F8A000A168B7 +:10680000401C82B201F1300002F00DFA002818BFDE +:10681000FFDFA5F8A060A06890F8561031B1B0F87D +:106820005210B0F85420914228BFF8BD90F85A1089 +:1068300031B1B0F85810B0F85420914228BFF8BDDB +:10684000B0F85020B0F84E108A4228BFF8BD90F83A +:106850003E20B0F84C00CAB1884228BFF8BDA44819 +:106860000090A44BA44A2946304601F076FCA0686B +:106870000023052190F83B20303002F0AEFA0028CA +:1068800008BFF8BDBDE8F84001F063BC0628E6D3B8 +:10689000F8BD9648806890F8561029B1B0F85210AB +:1068A000B0F85420914219D290F85A1029B1B0F89A +:1068B0005810B0F85420914210D2B0F85020B0F8DF +:1068C0004E108A420AD290F83E20B0F84C001AB11D +:1068D000884203D201F09BBD0628FBD3002001466D +:1068E0004AE42DE9F0410C4607461D461646D821DC +:1068F0002046DDF8188004F040FB2780C4F8D080E3 +:10690000C4E92F65BDE8F081F7F7ACB970B50C4666 +:1069100015460621F7F783F8002808BF70BDD0F8A8 +:10692000D0100A780021072A1ED00C2A2FD00B2A5B +:106930003BD0062A49D090F8C820002A04BF002086 +:1069400070BD61701222227090F8C82052B100BF51 +:1069500080F8C810D0F8CA20C4F8022090F8C820E7 +:10696000002AF5D1012070BD002DFBD161700722F6 +:106970002270D0F8D0205368C4F802309368C4F86D +:10698000063092896281D0F8D0000170EAE7002DCC +:10699000E8D161700C222270D0F8D0205268C4F87F +:1069A0000220D0F8D0000170DCE7002DDAD1617050 +:1069B0000B222270D0F8D0205368C4F8023012891C +:1069C000E280D0F8D0000170CCE7002DCAD1617010 +:1069D00006222270D0F8D0205368D2F808C0D268BE +:1069E000C4F80230C4F806C0C4F80A20D0F8D000B9 +:1069F0000170B7E7002070473C494861704710B507 +:106A00000446B0F8A000401CA4F8A000B4F84C0064 +:106A1000401CA4F84C0094F8560020B1B4F8520081 +:106A2000401CA4F8520094F85A0020B1B4F8580061 +:106A3000401CA4F8580094F8B40040B994F83D20E4 +:106A40000023012104F1300002F0C7F920B1B4F8AD +:106A50005000401CA4F85000204600F016F800201A +:106A600010BD224AC2E906017047B0F84C1090F8F8 +:106A70003E20091D2AB1B0F84E00814203D3012007 +:106A800070470629FBD20020704770B5044690F885 +:106A90003B000025072821D1208EB4F8C610401CE9 +:106AA000884218BF70BDD4F8C000411C04F1080032 +:106AB00004F089FB0221204602F01CF884F83B50C8 +:106AC000012084F86600D4F8C0000078002808BFD0 +:106AD000FFDFD4F8C0000178491E017094F83B0034 +:106AE000082818BF70BD208E08E00000E4000020D8 +:106AF00079610100F16601001D670100D4F8BC1046 +:106B0000401C8988884218BF70BDD4F8D000017835 +:106B1000002918BFFFDF1ED12188C180D4F8BC0036 +:106B2000D4F8D01040890881D4F8BC00D4F8D01033 +:106B300080894881D4F8BC00D4F8D010C0898881FD +:106B4000D4F8D0000571D4F8D01007200870D4F81C +:106B5000D010208848800121204601F0CBFF03217E +:106B60002046FEF75EF8D4F8BC00218840888842B1 +:106B700018BFFFDFD4F8BC00057084F83B5070BD2F +:106B8000F0B5FF4C8DB0207910F0010F04BF0DB0AF +:106B9000F0BD206900230521C578A06890F83B204E +:106BA000303002F01AF9002818BF022D0CD00B2D3E +:106BB00018BF042D08D0052D1CBF062D0D2D03D0A8 +:106BC000607840F008006070607800281CBF0DB04D +:106BD000F0BD2069C078801E0C2880F0D881DFE8E5 +:106BE00000F006FD2B4BD2FCFDFBFD21FA96A068C0 +:106BF0000023012190F83D20303002F0EEF800280B +:106C000040F0E381206902F082FBA16881F8B600C0 +:106C1000022081F83D00002081F85A0081F85600DA +:106C200000F0D3B9A06890F83B100A2929D10021BF +:106C300080F83F100D2166E0A06890F83B100E2907 +:106C40001FD1D0F8BC1000884988814218BFFFDFEF +:106C5000A068D0F8BC0000F12601206902F084FB96 +:106C6000A06800F18C01206902F086FBA168112068 +:106C700081F83B0000F0A9B9A66896F83B001128FE +:106C800003D00220607000F0A0B9D6F8BC10102527 +:106C900001F10E0C00210DF1FF3208206B1A634444 +:106CA000401E13F8017C577013F8023C02F8023FB3 +:106CB00001F10201F2D1D6F8BC10102601F11E0339 +:106CC000002108220DF10F00A6EB010C9C44891C49 +:106CD0001CF8015C45701CF802CC00F802CF521E73 +:106CE000F2D1684603F042F808ADA06895E80E10AE +:106CF00000F1780585E80E100021C0E91A11012184 +:106D000080F83F10132180F83B1000F05EB9A168B5 +:106D100091F83B00112812BF0E2891F85C00002862 +:106D2000AFD1206902F03FFBA168002581F89000F7 +:106D300081F85B5081F85650D1F8BC000988408832 +:106D4000884218BFFFDFA068D0F8BC100D70D0F8E3 +:106D5000D0100A78002A18BFFFDF40F014810288A3 +:106D6000CA80D0F8D02090F890101171D0F8D010CF +:106D70000D72D0F8D0200B2111700188D0F8D0000E +:106D8000418000F000B9A06890F83B10152918BFA9 +:106D9000022040F00981002580F85B5080F85650B1 +:106DA000D0F8BC1000884988814218BFFFDFA06876 +:106DB000D0F8BC100D70D0F8D0100A78002A18BF97 +:106DC000FFDF40F0E08090F85C20A2B180F85C50DA +:106DD0000288CA8003E020E08BE089E0D7E0D0F8A9 +:106DE000D0100D71D0F8D0200C2111700188D0F88E +:106DF000D0004180C7E00288CA80D0F8D0100D7161 +:106E0000D0F8D02001211172D0F8D0200B211170C0 +:106E10000188D0F8D0004180B5E0A0680023194671 +:106E200090F83C20303001F0D8FF48B9A06800232A +:106E3000072190F83B20303001F0CFFF00287DD0B3 +:106E40006078002854D1A06890F85E0010F0020F1E +:106E500017D1206902F09DFAA16881F85F002069CE +:106E600002F099FAA168A1F86000206902F096FA90 +:106E7000A168A1F8620091F85E0040F0020081F87C +:106E80005E00A06890F85E1011F0010F15D190F827 +:106E90003C2000231946303001F09FFF002808BF36 +:106EA000FFDF0121A068042280F83C1080F8B820A0 +:106EB00080F85A100021A0F85810A06890F83B10F4 +:106EC000012904D1002180F83B1080F85610D0F839 +:106ED000BC2003885188994204BF1178042974D1D9 +:106EE0000021117090F83B20002A08BF80F856104E +:106EF0006BE0A0680023062190F83B20303001F0C1 +:106F00006CFFD8B1607800285FD16946206902F033 +:106F10005DFA9DF8000010F001008DF8000014BF2C +:106F200001200020A168002581F86400A06880F895 +:106F30005650D0F8BC100088498800E033E0814208 +:106F400018BFFFDFA068D0F8BC100D70D0F8D010CB +:106F50000A78002A18BFFFDF15D10288CA80D0F84E +:106F6000D0100D71DDE90013D0F8D0209160D3600E +:106F7000D0F8D020062111700188D0F8D00001E0AF +:106F8000E40000204180A06880F83B501DE0A0682C +:106F90000023194690F83C20303001F01EFF10B15C +:106FA000607818B111E0012060700EE0206902F0F5 +:106FB00053F9A16881F89100052081F83C00002078 +:106FC000A1F85800012081F85A00A068D0E91C12ED +:106FD000491C42F10002C0E91C120DB0F0BD0000D6 +:106FE00030B585B004466846FBF701FD002808BFB0 +:106FF000FFDF009802F08DF80321009802F0A3F85B +:107000000098017821F010010170214602F0FEF88D +:10701000A01E0C2851D2DFE800F006501E51511678 +:1070200050425051312CFD48C06890F8651021B194 +:107030000621009802F069F940E090F8CF1000981E +:1070400002F063F93AE0F548C06890F891100098B2 +:1070500002F0ABF932E0F14DE86800F1B8010098B8 +:1070600002F07DF9E86800F18C01009802F081F9E6 +:1070700024E00621009802F094F91FE0E74DA8688B +:107080000178009802F07BF9A8688188009802F0E6 +:1070900078F9A8684188009802F077F90EE000209E +:1070A000029003909DF8080002A940F001008DF8BD +:1070B0000800009802F085F900E0FFDFFBF7AAFC6A +:1070C000002808BFFFDF0C2C04BF05B030BD072C23 +:1070D0000DD0022C04BF05B030BD0021CF48C068E0 +:1070E000A0F85810012180F85A1005B030BDCB49E6 +:1070F0000020C968A1F8580005B030BD70B50C4635 +:1071000005464FF49071204603F037FF258000209C +:1071100084F8F00084F8FC0084F8040184F812017B +:1071200070BDF6F79FBD70B50C4615460721F6F702 +:1071300076FC002808BF70BD90F8F0200021DAB17D +:10714000002D77D161700722227090F8F0208AB16B +:10715000018480F8F010D0F8F220C4F80220D0F8B2 +:10716000F620C4F80620B0F8FA20628190F8F020EA +:10717000002AEDD1A1705DE090F8FC2002B3002D53 +:1071800058D190F8FC200B2A0CD00C2A18BFFFDF36 +:1071900050D161700C22227090F8FE20A2700288FB +:1071A000A2800AE061700B22227090F8FE20A2708B +:1071B0000288A28090F80221A27180F8FC1039E0C8 +:1071C00090F804218AB17DB961700822227002888A +:1071D0006280D0F80821D0F80C316260A360B0F86A +:1071E0001021A28180F8041124E090F812214AB104 +:1071F00005BB617011222270B0F81421628080F802 +:10720000121117E090F81621002A04BF002070BD6B +:1072100085B961701222227090F8162152B100BF18 +:1072200080F81611D0F81821C4F8022090F8162121 +:10723000002AF5D1012070BD002070477749886091 +:107240007047002180F83B1080F83C1080F83E1019 +:1072500090F8A60010B10220FEF72CBC0320FEF728 +:1072600029BC2DE9F04F6D4C07468DB0E0680D4606 +:107270000088F6F74CFD5FEA000B08BFFFDF60787F +:1072800028436070A088E16810F0200F4FF00005DF +:107290001CBFA1F84C5081F8AC5004D1B1F84C207F +:1072A000521CA1F84C2010F0600F4FF002084FF074 +:1072B000010613D0E06890F83E1011B1032907D001 +:1072C0000CE080F83E6000210120FEF7F3FB05E0B2 +:1072D00080F83E8000210120FEF7ECFBE06890F88A +:1072E0003E10012905D1A18811F4807F18BF80F8D4 +:1072F0003E80002F40F09B81A18811F4007F18BFD1 +:10730000A0F8C05004D1B0F8C010491CA0F8C010BB +:1073100000F0A9FB0CA8FBF76AFB002800F0E8804E +:107320006078002840F0E480E0680123194690F876 +:107330003D20303001F051FD002849D1D4F80CC077 +:107340009CF8CE0038B1ACF850508CF86550022053 +:10735000FFF746FECCE09CF83C200B2A08BF0B2030 +:107360001AD00ADC012A7BD0052A08BF072013D0D7 +:10737000092A08BF09200FD005E00F2A0FD0102AD4 +:1073800020D0162A7CD0012304210CF1300001F01A +:1073900024FD00281CD187E0FFF722FEA8E0F9F7C2 +:1073A0005BFF0C2814D3E0680821B830F9F755FFCB +:1073B00028B1E06804218C30F9F74FFF00B9FFDFF6 +:1073C0000420E9E79CF8D100012802D0022849D026 +:1073D0008EE09CF8FC00002841D100220CF1D2097B +:1073E0004FF0100808210DF1FF3000BFA8EB020399 +:1073F0004B44491E13F801AC80F801A013F8023C7D +:1074000000F8023F02F10202F0D10CF1B0080020B6 +:107410004FF0100C0DF10F01082201E004010020D3 +:10742000ACEB00034344801C13F8019C81F80190ED +:1074300013F8023C01F8023F521EEED1684602F0FA +:1074400095FC0DF12008E06898E80E10783080E88F +:107450000E100520FFF7C4FDE06880F8D15047E02A +:1074600015E00DE09CF85C0000281ABF8CF8656000 +:1074700002200D20FFF7B4FDE06880F8D15037E01E +:107480000620FFF7ADFDE06880F85A5030E00C2090 +:10749000FFF7A6FDE068A0F8585090F85E1041F0A4 +:1074A000010180F85E1023E0E06890F83B2090F83E +:1074B000E210E9B101230021303001F08EFCB8B1B7 +:1074C000E06890F8E210042904BF90F85E0010F024 +:1074D000030F0DD10C20FFF783FDE068A0F8525098 +:1074E00080F8566090F85E1041F0010180F85E105F +:1074F00000F0B1FF0028E06818BFA0F8A05004D148 +:10750000B0F8A010491CA0F8A01000F0A7FF40B1EF +:10751000E16891F8AC0002289CBF401C81F8AC00E7 +:1075200004D8E06890F8AC00022806D9E068A0F81A +:10753000A050A0F8A25080F8AC50E06801230021D0 +:1075400090F83C20303001F048FC20B9E06890F819 +:107550003C00072856D1E0680123002190F83B2029 +:10756000303001F03AFCE8B3E0680123002190F8E4 +:107570003D20303001F031FCA0B3E06890F83E10BF +:10758000022904BF90F8AC0000283BD15846F5F71B +:10759000F0FE38B3FBF772FA20B3E168B1F89A0055 +:1075A00001282FD981F8A560B1F84E20B1F84C0020 +:1075B000931E9842AFBF0120101A401E80B2B1F84E +:1075C000A020E3889A422FBF01229A1A521C92B23D +:1075D000904288BF1046012808BF81F8A55091F855 +:1075E000C82000E00EE08AB1B1F8A220B1F8CA10BC +:1075F0008A422FBF0121891A491C89B2884288BF5B +:10760000084603E0E168012081F8A550E1680A8E90 +:10761000104480B2A1F89C0091F83E30002B18BFB6 +:10762000012B2CD0022B1CBF032BFFDF09D0A0881D +:10763000C0F340200028E06818BFA0F8AE5031D158 +:1076400029E091F83D30032B1CD091F83C20082A0A +:1076500015D0B1F84C30B1F84EC0002203F1020849 +:10766000C4450BD3ACEB0302921E1204120C1FBFD5 +:10767000521E92B2002A521E18BF92B21044A1F8B4 +:107680009800D4E7B1F84C30032BF8D3B1F84E0092 +:107690001044401CF3E7B0F8AE10B0F89E2011443F +:1076A000A0F8AE10E06890F8CE1039B990F83D20FF +:1076B00001231946303001F090FB38B1E068B0F892 +:1076C0005010B0F89E201144A0F850103D212FB169 +:1076D000E06880F84A1080F8496069E02078022864 +:1076E00010D001281AD0607800B310F0140F14BF26 +:1076F0001E2110F0080FEBD110F0030F08BFFFDFC1 +:107700002A21E5E7E06890F86510002914BF0621FA +:10771000162180F84A1080F8496049E0E06890F846 +:10772000D01080F84A1080F8496041E0E06890F895 +:10773000561041B1B0F852104A1CA0F85220B0F8CF +:107740005420914214D290F85A1041B1B0F8581018 +:107750004A1CA0F85820B0F85420914208D2B0F842 +:107760005020B0F84E108A4208D390F8CE202AB1AB +:10777000222180F84A1080F8496019E090F83E20F4 +:107780004AB1B0F84C208A420FD3082180F84A1041 +:1077900080F849600CE0B0F84C10062905D33E2172 +:1077A00080F84A1080F8496002E090F8490088B1FA +:1077B000E06880F83B5080F83C5080F83E5090F8EC +:1077C000A6004FF00001002814BF02200320FEF79E +:1077D00071F903E000210846FEF76CF9E06880F8D3 +:1077E000A6500DB0BDE8F08FFE494A788B781A4359 +:1077F0000DD150B1087910F0080F04D0C86890F886 +:107800003D00032803D001207047FEF7D5B80020C3 +:1078100070472DE9F041F34C05460E46A0882843F9 +:10782000A08015F0020F04D015F0010F18BFFFDF84 +:10783000266115F0010F4FF000084FF001071CD032 +:107840003046666101F008FD062802D00B280BD0F7 +:1078500013E0E06890F83C1012290ED10021C0E935 +:107860001A1180F83F7008E0E06890F83C100C298D +:1078700004BF80F83F8080F85C7015F0020F19D0CB +:10788000206901F0E9FC052802D00B280BD011E09B +:10789000E06890F83C1010290CD10021C0E91C11BF +:1078A00080F8407006E0E06890F83C100B2908BFB3 +:1078B00080F8408015F0800F1CBF0820A070BDE844 +:1078C000F0812DE9F043C74C83B0012721690025E1 +:1078D0000191A5806570A5702570E06067F30708C9 +:1078E000064680F8A6700088F6F711FA5FEA0009EC +:1078F00008BFFFDFE0680088FBF776F8E0680088E3 +:10790000FBF798F8E068B0F89A00D0B101A8FBF74F +:107910006EF8B0B1E06890F8CE1091B190F83D20CB +:1079200001231946303001F058FA50B9E068A0F848 +:10793000505080F865500220FFF752FBE06880F855 +:10794000A550E26892F8F00028B9108C918888421E +:1079500088BFE08001D89088E080B2F89E00B2F83D +:10796000A010401E80B2014489B2A2F8A01092F883 +:10797000A430002B1CBFA2F8A25082F8A45004D15E +:10798000B2F8A2300344A2F8A230B2F84C3003445B +:10799000A2F84C30B2F89A30012B9CBF5B1CA2F8C5 +:1079A0009A30002818BF82F8AC5092F8A500002841 +:1079B0001CBFE08881420FD24846F5F7DAFC58B187 +:1079C000E06890F8C81039B1B0F8A210B0F8CA0059 +:1079D000814228BF00F045FDE06880F8A55090F88E +:1079E0003C10062918BF072916D1018EB0F8E420F3 +:1079F000891A09B200290FDB00F1E601083003F013 +:107A0000E2FB0221E06800F0C3FFE06880F8E35089 +:107A100080F83C5080F86670E16801F13000B1F800 +:107A20009E2001F000F9E06890F8C810002918BF06 +:107A3000A0F8A2506C4800906C4B6D4A314640460D +:107A400000F08BFBE0680123052190F83C203030EA +:107A500001F0C3F9002818BF00F07BFB03B0BDE8BC +:107A6000F08300F0D4BC2DE9F0415E4C4FF00207EA +:107A70004FF00005207910F0080F13D0607888B916 +:107A8000E06890F83C10142905D180F85B5080F82C +:107A90005A5080F83C5090F83D10032904BF2770DD +:107AA00080F83D5000F044F9A1884FF0010611F034 +:107AB000040F14D0607890B9E06890F83C20062A52 +:107AC00008BF80F8E36003D0082A08BF80F8E3709D +:107AD00090F83D20022A04BF267080F83D5011F036 +:107AE000020F4FF003073FD0607800283CD1206997 +:107AF000C078801E0C287DD2DFE800F006B7374240 +:107B00005819B723B72A8C4DE0680123194690F81D +:107B10003D20303001F061F9002825D1E06880F87F +:107B20003D7080F8565000BF80F85A509EE0E068E3 +:107B300090F83C00052818BFFFDFE06880F83C5053 +:107B4000F2E7E06890F83C00092818BFFFDF6FE01B +:107B5000E06890F83C000B2818BFFFDFE0680C21BC +:107B600080F85B6080F83C1080E0E06890F83C00B2 +:107B70000F2818BFFFDFE068102180F85B60F1E795 +:107B8000E06890F83C00102818BFFFDF1220E16881 +:107B900081F83C006AE0E06890F83C00102818BFCB +:107BA000FFDF1420E16881F83C005FE0E06890F8B6 +:107BB0003C00162818BFFFDFE06880F85B5080F8B3 +:107BC0005A5090F8FC00002818BFFFDFE06890F8DA +:107BD0005C1091B180F85C500188A0F8001180F829 +:107BE000FE5008E00401002063720100E977010003 +:107BF0001378010039E00C2107E00188A0F800119A +:107C000080F8FE5080F802610B2180F8FC1080F8AB +:107C10003C502BE0E06890F8E21004290ED0E068B8 +:107C20000123072190F83C20303001F0D6F8E8B16C +:107C3000E06880F85A5080F83C5017E090F83B20FC +:107C400001230021303001F0C8F8002808BFFFDF11 +:107C5000E06890F85E1011F0020F0EBF80F83B60F4 +:107C600080F8565080F8E250D9E7FFDF207910F015 +:107C7000100F09D0607838B9E06890F83C100629F8 +:107C800004BF072180F83C10A07810F0080F10D036 +:107C9000E0680123052190F83C20303001F09DF888 +:107CA00028B108206070E06880F8FC5001E000F026 +:107CB000DCFBE06890F83C10082918BFBDE8F081B3 +:107CC000018EB0F8E420491C914206BF617800297A +:107CD000BDE8F081B0F8EA104288914209D1B0F8CD +:107CE000EC2083889A4204D1B0F8EE20C3889A42EF +:107CF0000ED00288A0F8F420A0F8F610B0F8EC102E +:107D0000A0F8F810B0F8EE10A0F8FA1080F8F060C3 +:107D1000012100F03DFE00210420FDF7CBFEE068CC +:107D200080F8E35080F83C5080F83E70BDE8F08168 +:107D300030B5FF4C83B0207910F0010F04BF03B0C1 +:107D400030BD606901230521C578E06890F83C20CA +:107D5000303001F042F8002818BF022D0BD00A2D58 +:107D600018BF0B2D07D0032D18BF062D03D0607848 +:107D700040F008006070607800281CBF03B030BD80 +:107D80006069C0780D2880F0AB81DFE800F0462202 +:107D900007C8FEFEFDDBFCFEA3C0FB00E06801237C +:107DA000194690F83D20303001F017F8002840F0D7 +:107DB000B481606901F0ABFAE16881F8D00002207B +:107DC00081F83D00002081F85A0081F8560000F04B +:107DD000A4B9E0680123002190F83C20303000F085 +:107DE000FCFF002875D06078002840F0968160691B +:107DF00001F088FAE168A1F8E4000A8E801A00B266 +:107E000047F6FE728242A8BF00285ADDE63160695B +:107E100001F06FFA0620E1683FE0E06801230021ED +:107E200090F83C20303000F0D8FF00285FD0607818 +:107E3000002840F07281606901F037FA88B3606908 +:107E400001F030FAE168A1F8E4000A8E801A00B26D +:107E500047F6FE728242A8BF002832DD606901F059 +:107E60001BFAE16881F8E600606901F010FAE16848 +:107E7000A1F8E800606901F0F5F9E168A1F8EA000D +:107E8000606901F0F6F9E168A1F8EC00606901F0C1 +:107E9000F7F9E168A1F8EE00082081F83C0000F055 +:107EA0003CB9FFE7E0680123002190F83C20303026 +:107EB00000F093FF68B16078002800F01F8100F0A7 +:107EC0002CB9282081F84A00012081F8490000F0EF +:107ED00024B90CE0E0680123002190F83C20303008 +:107EE00000F07BFF18B1607828B100F016B90120CE +:107EF000607000F012B9E0680021A0F8581001216C +:107F000080F85A100B2180F83C1000F006B9E068A8 +:107F100090F83C100C2908BF0D214CD143E0E068DB +:107F20000123002190F83C20303000F056FF20B9AA +:107F3000E06890F85C0000287ED06078002801D1CD +:107F400001E06070E9E0E06800210125A0F8581028 +:107F500080F85A5000F1B001606901F0F1F9E06871 +:107F600000F18801606901F0F6F9E06890F8040119 +:107F7000002818BFFFDFE0680188A0F8061100F5AF +:107F8000847103E01EE087E010E0A9E0606901F081 +:107F9000C5F9E06800F58871606901F0C7F9E0682B +:107FA00080F804510F2180F83C10B6E0E06890F8AA +:107FB0003C10122901D00220C3E7002180F85A109A +:107FC0001621F0E7E0680123002190F83C203030D2 +:107FD00000F003FF48B9E0680123072190F83B2037 +:107FE000303000F0FAFE002826D06078002852D108 +:107FF000E06890F85E0010F0020F17D1606901F0A0 +:10800000C8F9E16881F85F00606901F0C4F9E168CE +:10801000A1F86000606901F0C1F9E168A1F86200AF +:1080200091F85E0040F0020081F85E00E06890F890 +:108030005E1011F0010F00E05EE015D190F83C20D9 +:1080400001230021303000F0C8FE002808BFFFDF08 +:108050000121E068042280F83C1080F8E32080F8D9 +:108060005A100021A0F85810E06890F83B10012940 +:1080700004D1002180F83B1080F8561090F8E210EF +:1080800004294AD1002180F8E21090F83B20002A10 +:1080900008BF80F8561040E0E0680123002190F806 +:1080A0003C20303000F099FE30B3607818BB694650 +:1080B000606901F081F99DF8000010F001008DF871 +:1080C000000014BF01200020E16881F86400E0682E +:1080D0000021A0F85810012180F85A10092162E708 +:1080E000E0680123002190F83C20303000F075FE5C +:1080F00010B1607810B110E0012022E7606901F052 +:10810000ABF8E16881F89100052081F83C0000207F +:10811000A1F85800012081F85A00E068D0E91C213C +:10812000521C41F10001C0E91C2103B030BD000028 +:1081300004010020F9480078002818BF0C2070477F +:1081400030B5F64C05462078002818BFFFDF657271 +:1081500030BDF2490120087270472DE9F047EF4C1D +:108160008146DDF8208020781E4617460D4628B946 +:10817000002F1CBF002EB8F1000F00D1FFDFC4F8A4 +:108180001C80C4E90C95C4E9057600202072E071DA +:108190002071E0706071A071E14EA0706081307854 +:1081A0004FF0010805F130072888F5F7B0FDA0620F +:1081B0002888F5F79AFDE062FAF7B2F80120F9F79E +:1081C000C0FDFAF702F905F11100FAF792F805F18E +:1081D0000D00F9F7BDFE307800280CBF0320012008 +:1081E000FAF79BF8387EF9F7BBFE0120F9F798FD06 +:1081F000FAF78DF8397CCB48002914BFCA49CB491E +:10820000016030784FF0010170B10120F9F71CFFD7 +:108210007068D0F8A800FAF791F800BF84F80080E1 +:10822000BDE8F047FAF784B80020F9F70DFFF5E74D +:108230002DE9F047DFF8E89282B048460026406812 +:10824000012700F130041B20ADF8000060794FF0E9 +:108250000208A9F1300570B301285AD002285CD079 +:10826000032818BFFFDF62D0286A0823017821F0B5 +:1082700008010170A27903EAC202114321F004014E +:108280000170E279042303EA8202114321F0100114 +:10829000017094F805A0A86AF5F779F80646FAF790 +:1082A000EDFBBAF1020F49D0BAF1010F49D0BAF192 +:1082B000030F49D04BE0FFE79D48FAF7BEFB40B102 +:1082C000296AAF706A694FF480609047032060713B +:1082D000CAE701AA6946A86AF4F74AFF286210B102 +:1082E00094F82B1021B19248FAF77BFB6771BBE73A +:1082F0009DF8041021B906808670012100F023FF4B +:10830000BDF80000C1B2286A01F065F884F8058064 +:10831000AAE78748FAF765FBA6E701AA6946A86AB3 +:10832000F4F726FF2862002808BFFFDF9CE780489B +:10833000FAF783FB002808BFFFDF95E7B04306D1BB +:1083400003E0B04303D100E00EB1012100E00021C1 +:10835000286A027842EA01110170E17B00291CBF02 +:108360006179012926D004F14801724891E80E1084 +:1083700000F1480686E80E10A16DC0F86110E16DAD +:10838000C0F865102230F9F7D6FF99F800000028F0 +:108390000CBF0121002168480176D4E90E12C0E922 +:1083A0000412A0F126012A6AF9F707FC0020F9F768 +:1083B00015FC03E0F9F7BFFFF9F737FC99F8000067 +:1083C00028B1286A007810F0100F05D00CE00121C8 +:1083D0000846FAF772F80AE05848007810F0100FD3 +:1083E00004BF2879002802D0A8780028EFD0687947 +:1083F000002804BF6F71F9F7C6FF286A0188A981B8 +:108400008078A87385F8008002B0BDE8F087434803 +:1084100010B50078012818BFFFDFF9F781FF404849 +:108420000178446811B9FFF703FF01E000F0BCF9DF +:1084300094F82800012818BF10BDBDE81040FAF7D5 +:1084400019B8364810B50078032818BFFFDFBDE81B +:10845000104000F0F4B93148407970472F48007956 +:1084600070472E490120887170472DE9F0412C4852 +:108470002A4D012601784068002700F13004686A1F +:10848000417801F01F08E96A02F0AAF868B10128F2 +:1084900021D0022834D003281CBFFFDFBDE8F081C3 +:1084A000E86ABDE8F041F5F7DCB801224146E86A28 +:1084B000F4F7F2FFD4E91010491C40F10000C4E9C0 +:1084C0001010E079012814BFE671E771687ABDE801 +:1084D000F041F1F767B800224146E86AF4F7DCFFA3 +:1084E000D4E91001401C41F10001C4E91001E07918 +:1084F000012802D1E771BDE8F081E671BDE8F081A5 +:10850000E86AF5F7AEF8D4E91010491C40F1000014 +:10851000C4E91010E0790128EFD1EBE71C0100203D +:108520004C010020181500401F0003021B0003022D +:108530003C010020F8100020401100202B010020F9 +:108540002DE9F041F04F4FF000083846A7F1300414 +:108550004068012600F130052078022818BFFFDFAF +:10856000A87850B185F80280A6706269414604205F +:1085700090473878002818BF2E71206A03210078B0 +:1085800031EA000004BFE878002805D1EE70216AC6 +:10859000A6706269022090470121002000F072F964 +:1085A00018B1BDE8F04100F04AB9BDE8F04100F073 +:1085B000FBB82DE9F05FD44E82463046A6F1300577 +:1085C00040684FF0000800F130092878012703289F +:1085D00018BFFFDF6889BAF1000F40F400706881AE +:1085E00004BF40F04000688100F0CE80F9F733FB13 +:1085F00098B999F8100080B1686A417811F01F0F9E +:108600000BD0007899F80710C0F3C000884204D15D +:10861000EF70BDE8F05F00F012B9686A0188A5F854 +:108620000F1080786874688940F02000688185F8B0 +:108630000480706800F1300B044690F8280001288F +:1086400013D1F9F70DFF5946204600F09BFB60B1AE +:108650003078002870680CBFC83000F58B70218816 +:1086600041809BF8081001710770686A99F806103C +:108670000078C0F38000884233D0706800F1300485 +:1086800090F8350048B3022844D000BF84F8058034 +:10869000307838B12079414620B12171AF706A69D4 +:1086A00010209047E07890B184F80380FAF7D4F96D +:1086B000002808BFFFDF0820AF706A6900219047DB +:1086C000D4E90E10491C40F10000C4E90E10A07955 +:1086D00001280CBF84F80680A771688940F4807077 +:1086E0006881686A99F807300178C1F3C0029A423C +:1086F0004AD1726801F0030102F13004012918BF68 +:1087000002292ED003291CBFE87940F0040012D0C2 +:10871000E87139E0A86AF4F765FD002808BFFFDFBB +:10872000D4E90E10491C40F10000C4E90E10687A2B +:10873000F0F738FFAAE700F02AFD70B1A770696A68 +:10874000AF706A6938469047E079012803D100BFCD +:1087500084F8078018E0E77116E0E87940F010002F +:10876000D6E7407810F01F0F17D0697861B900F094 +:108770001F001B28F1D8287A20B180206A690021C7 +:10878000904701E0FFF771FE5146012000F07AF8B2 +:1087900038B1BDE8F05F00F052B8E0790128DAD1D5 +:1087A000D6E7BDE8F05F43E570B5584C1B21E06AA1 +:1087B000F4F71BFE002101226062002811BF6170E6 +:1087C000627053486062504E3078706800F1300536 +:1087D00090F8400038B305F148014D4891E80E107B +:1087E00000F1480E8EE80E10A96DC0F86110E96D19 +:1087F000C0F865102230F9F79EFD307800280CBFD4 +:108800000120002080F0010142480176D5E91012D4 +:10881000C0E90412A0F12602616AF9F7CEF901203D +:10882000F9F7DCF904E0606AF9F785FDF9F7FDF97D +:1088300001210020F9F741FE0320207070BD70B5C2 +:10884000314900254C68F9F7DDFDF9F7CFFDF9F75F +:10885000F1FCF9F754FDF9F7E8F9F9F7C3FDF9F779 +:1088600067FD94F82800012808BFF9F7F9FD274CA7 +:108870000021626960899047E269E179E078904778 +:10888000257070BD70B5214C0546002908BF012D2B +:1088900005D12079401CC0B22071012831D8A169CE +:1088A0002846884700282CD0A1791B4841B1012DCA +:1088B00001BF417811F01F0F017811F0100F20D087 +:1088C000E179F1B910490978002918BF002102D0D7 +:1088D000294304D013E0012D18BF0121F8D10F491D +:1088E000097811F0100F04BF007810F0100F08D0B5 +:1088F000A07830B9607810B111F0100F01D00020CD +:1089000070BD012070BD00004C0100201C01002042 +:10891000F8100020401100202B0100202801002029 +:1089200010B50A7B02F01F020A73002282758B18B1 +:108930001B7A03F0010C5B0803F00104A4445B08FC +:1089400003F00104A4445B0803F00104A4445B08A1 +:1089500003F0010464444FEA530C0CF00103234478 +:108960004FEA5C0C0CF00104234403EB5C0300EBC6 +:10897000020C521C8CF8113090F816C0D2B263442D +:108980008375052AD3D3D8B2252888BFFFDF10BD51 +:108990000A4610B40021032A0DD04FF4FA4C002AE5 +:1089A00060D0012A7ED0022A1CBF10BC704701464D +:1089B00010BC3030B4E7018680F8361080F83710EC +:1089C00080F83B1080F83C1080F83D1080F83E1095 +:1089D00080F8321080F8331080F8341080F83510A9 +:1089E00080F84910A0F84C10A0F8521080F85610EA +:1089F000A0F8581080F85A1080F8471080F84810F6 +:108A000080F83F1080F8401080F85B1080F85C1010 +:108A100080F85E10012280F86420A0F8501080F8E1 +:108A20006610A0F89810A0F89A10A0F89C10A0F872 +:108A30009E10A0F8A010A0F8A21080F8A510A0F831 +:108A4000AE1080F8AC10A0F8C010A0F8C21080F8EA +:108A50002810018480F8C81080F8CE1080F8D1105A +:108A600010BC7047A0F8AE1080F8A6104288C488E9 +:108A7000A0F84C10B0F8501000F13003514391FBB6 +:108A8000F2F1A0F85010E100B1FBF2F1491C89B2FB +:108A900001FB02F4A0F84E10B4F5C84FC4BF491E44 +:108AA000D98300E004E0BCFBF2F1491C99847EE725 +:108AB000A0F8AE1000F130024488B0F8EA30B0F807 +:108AC000EE009183118CC0006143B0FBF3F091FB89 +:108AD000F3F1401C118480B200FB03F1D083B1F5A7 +:108AE000C84FC4BF401ED083BCFBF3F0401C908431 +:108AF00010BC70470A4610B40021032A0DD04FF471 +:108B0000FA4C002A4FD0012A6DD0022A1CBF10BC9B +:108B10007047014610BC303002E7018680F83610FD +:108B200080F8371080F83B1080F83C1080F83D103A +:108B300080F83E1080F8321080F8331080F834103E +:108B400080F8351080F84910A0F84C10A0F85210A9 +:108B500080F85610A0F8581080F85A1080F8471086 +:108B600080F8481080F83F1080F8401080F85B10C3 +:108B700080F85C1080F85E10012280F86420A0F874 +:108B8000501080F86610A0F8A01080F8A21080F8AD +:108B90009810C0F89C1080F8281080F8B41080F865 +:108BA000C41010BC70474288C488A0F84C10B0F8BC +:108BB000501000F13003514391FBF2F1A0F8501036 +:108BC000E100B1FBF2F1491C89B201FB02F4A0F80B +:108BD0004E10B4F5C84FC4BF491ED983BCFBF2F197 +:108BE000491C998495E7D0F8BC4000F130024388D5 +:108BF0006089E4899183118C594391FBF0F11184D0 +:108C0000E100B1FBF0F1491C89B201FB00F3D18313 +:108C1000B3F5C84FC4BF491ED183BCFBF0F0401C64 +:108C2000908410BC7047837D0BB1252B01D9122095 +:108C30007047002A04BF0020704770B490F817C036 +:108C40000C7E894D04FB02C22C464FF0000CE2FB67 +:108C5000054C4FEA1C1C6FF024040CFB0422D2B21A +:108C600001EBD20CC27502F007059CF808C0012484 +:108C700004FA05F51CEA050F18BF02762CD1B2FBE9 +:108C8000F3FC03FB1C22521CD2B24FF0000C00BFBD +:108C900000EB0C035B7C93423CBFD21AD2B20ED3E2 +:108CA00001EB0C0500232D7A04FA03F635421CBFB4 +:108CB000521ED2B26AB15B1CDBB2082BF4D30CF1AA +:108CC000010303F0FF0CBCF1050FE1D370BC1F20C2 +:108CD000704703EBCC01017670BC0020704730B5C3 +:108CE0000D460446072988BFFFDFE07805F007013D +:108CF00000F05000084340F08800E070A07800F0D9 +:108D0000A70040F01800A070607800F05E0040F00E +:108D100020006070207800F0BC0040F0400020701F +:108D200030BD017931F01F0113BF00200022114630 +:108D3000704710B4435C491C03F0010C5B0803F05E +:108D40000104A4445B0803F00104A4445B0803F09D +:108D50000104A4445B0803F00104A4445B0803F08D +:108D600001045B08A44403F00104A4440CEB530386 +:108D70001A44D2B20529DDDB012A8CBF0120002074 +:108D800010BC704738B505460C466846F9F77DFBC0 +:108D9000002808BF38BD9DF90020227294F90910FF +:108DA0000020511A48BF494295F829308B42C8BF6C +:108DB00038BDFF2B08BF38BDA17A491CC9B2A172CA +:108DC00095F82A30994203D8617A7F2918BF38BDB7 +:108DD00062720020A072012038BD10B4A2F10B0C09 +:108DE00008293AD2DFE801F004060B10131D3337CF +:108DF00082B332E0022A18BF032A31D02DE0072ABD +:108E000018BF062A2CD028E0082A29D025E01BB15B +:108E1000BCF10B0F24D920E0A2F10A000B281FD9C6 +:108E20001BE01BB1BCF10B0F1AD916E00D2A18BFBD +:108E30000C2A15D090F82C0020B10D2A0DD3152A3C +:108E40000ED90AE0112A08D3152A09D905E0092A02 +:108E500006D002E004E0012A02D010BC00207047D6 +:108E600010BC01207047000053E4B36E282102F0CB +:108E700062B830B50546007801F00F0220F00F000F +:108E80001043287007290BD2DFE801F0040604061E +:108E900004080400062405E00C2403E0222401E079 +:108EA0000024FFDF687820F03F002043687030BD69 +:108EB000007800F00F0070470A68C0F80320898826 +:108EC000A0F807107047D0F803200A60B0F8070038 +:108ED000888070470A68C0F809208988A0F80D10BA +:108EE00070470278402322F0400203EA81111143C7 +:108EF000017070470078C0F38010704702788023BB +:108F000022F0800203EAC111114301707047D0F8CA +:108F10000320C1F80920B0F80720A1F80D200A7835 +:108F200022F080020A700078800942EAC0100870BE +:108F3000704770B515460E4604461F2A88BFFFDFEE +:108F40002A46314604F1090001F07EFF6078A91D30 +:108F500020F03F0001F03F010843607070BD70B524 +:108F6000054640780E4600F03F04062C38BFFFDF70 +:108F7000A01FC4B21F2C88BF1F24224605F109017F +:108F8000304601F061FF204670BD70B515460E46B3 +:108F900004461F2A88BFFFDF2A46314604F1090034 +:108FA00001F052FF6078A91D20F03F0001F03F0161 +:108FB0000843607070BD70B5054640780E4600F0FD +:108FC0003F04062C38BFFFDFA01FC4B21F2C88BF90 +:108FD000FFDF224605F10901304601F035FF20464A +:108FE00070BD0968C0F80F1070470A88A0F81320F8 +:108FF0008978417570474176090A81767047C17654 +:10900000090A017770474177090A81777047C1756E +:10901000090A017670478175704790F8242001F0A5 +:109020001F0122F01F02114380F82410704790F8AE +:109030002420E02322F0E00203EA4111114380F8EA +:10904000241070471F3002F0BEB84178007801F05C +:109050003F0110F00F0006D0012808D0022809D0E7 +:1090600006280BD00FE0881F1F280AD90BE00C2917 +:1090700009D106E0881F1F2803D904E0881F1F2894 +:1090800001D801207047002070474178007801F036 +:109090003F0100F00F00042805D1062903D325293C +:1090A0009CBF012070470020704710B4017801F088 +:1090B0000F01032922D0052925D14478B0F81910D1 +:1090C000B0F81BC0B0F81730827D04F03F04222CAA +:1090D00019D1062917D3B1F5486F98BFBCF5FA7FAF +:1090E00011D282B1082A98BF8A420CD28B429CBF0F +:1090F000B0F81D00B0F5486F05D807E0407800F0E3 +:109100003F000C2802D010BC0020704710BC01208A +:109110007047222101F00FBF00B5027801F0030370 +:1091200022F003021A4302704278012922F01F0242 +:10913000427014BF022900BD032912BFFFDF42F0B5 +:109140000101417000BD01F0030300B5027822F077 +:1091500003021A4302704278012922F01F02427072 +:1091600014BF022900BD032912BFFFDF42F0010135 +:10917000417000BD007800F00300704702781023B2 +:1091800022F0100203EA0111114301707047417887 +:10919000C07801F01F010E2832D2DFE800F0070A84 +:1091A0000D101316191C1F2225282B2E0C2929D02F +:1091B0002AE0082926D027E0022923D024E0172915 +:1091C00020D021E00D291DD01EE001291AD01BE07E +:1091D000012917D018E0022914D015E0092911D06F +:1091E00012E009290ED00FE001290BD00CE0012973 +:1091F00008D009E0062905D006E0022902D003E0E4 +:109200001B2901D8012070470020704730B5054662 +:10921000C1700E2918D2DFE801F007090B0D0F11FC +:10922000110B13131111150B0C240FE008240DE082 +:1092300002240BE0172409E00D2407E0012405E0D7 +:10924000092403E0062401E00024FFDF687820F011 +:109250001F002043687030BDC0787047C171090A93 +:1092600001727047B0F8070070474172090A8172B5 +:109270007047B0F809007047C172090A017370475E +:10928000B0F80B0070474171090A81717047B0F85E +:109290000500704701717047007970474173090AF2 +:1092A00081737047B0F80D00704730B4B0F80720F4 +:1092B000504DB0F809C0B0F805300179941F2D1950 +:1092C00098BFBCF5FA7F0ED269B1082998BF9142C8 +:1092D00009D293429FBFB0F80B00B0F5486F012050 +:1092E00030BC98BF7047002030BC7047001D01F0B3 +:1092F0006ABF021D0846114601F065BF4172090AA6 +:1093000081727047B0F809007047017170470079A9 +:1093100070470A68426049688160704742680A6025 +:10932000806848607047098881817047808908801B +:1093300070470A68C0F80E204968C0F812107047DC +:10934000D0F80E200A60D0F8120048607047096813 +:10935000C0F816107047D0F81600086070470A6809 +:10936000426049688160704742680A60806848606E +:1093700070470968C1607047C06808607047017134 +:1093800070474171090A81717047C171090A017200 +:10939000704700797047B0F805007047B0F80700D3 +:1093A00070470171704700797047017170470A6812 +:1093B000426049688160704742680A60806848601E +:1093C00070470A68426049688160704742680A6075 +:1093D00080684860704730B50C4605461B2988BF39 +:1093E000FFDF687804F01F0120F01F000843687059 +:1093F00030BD000086F3FFFF70B50446C2F11005D2 +:10940000281901F021FD15F0FF0108D0491EC9B24D +:10941000802060542046BDE8704001F08CBD70BDD6 +:1094200030B505E05B1EDBB2CC5CD55C6C40C4544F +:10943000002BF7D130BD10B5002409E00B78521E87 +:1094400044EA430300F8013B11F8013BD2B2DC09C6 +:10945000002AF3D110BD30B50C46097889B0154605 +:10946000012049B1012905D12978042902D105201B +:109470001070002009B030BD60680590CDF818D09C +:109480000D210DF1030001F056FDA0680188ADF833 +:10949000001080788DF802000120207006208DF8E1 +:1094A0001000606A0890294604A8F5F73BFEE1E742 +:1094B0002DE9F0410C46097892B0154601204FF095 +:1094C000020CFE4F06264FF0040869B101291ED098 +:1094D000022946D0032904D12978042901D1167024 +:1094E000002012B0BDE8F081606850B1CDE90107FD +:1094F000012020708DF80060606A04901146684673 +:1095000065E084F800C085F80080576027E029787E +:109510000429E6D1696810222069FFF78CFF68688A +:10952000C07B000606D5E54A2069102310320146AB +:10953000FFF776FFD4E904101022FFF77CFF2069C3 +:10954000C07B000606D5DD4A606910231032014653 +:10955000FFF766FF84F800C085F800806F60032085 +:10956000BFE729780429BCD1A08910280CD9A0F123 +:10957000100080B2A081A1684FF01003014468463A +:109580006A68FFF74DFF18E004D14FF0100322691D +:10959000A16807E0C2B20DA8A168FFF72DFF6269BC +:1095A00010230DA909A8FFF73BFF102309A968465E +:1095B0006A68FFF735FF0320207060680590CDF8DA +:1095C00018D08DF81060606A0890294604A8F5F755 +:1095D000A9FD86E72DE9F04107460D4601200B78ED +:1095E00007213BB1012B04D11378062B01D1117057 +:1095F000002077E76C69012620226170E8686060CE +:10960000686A6062A168287C0870A681A068A96861 +:10961000401C01F019FCA08920222030A081A06804 +:109620006968213001F010FCA08921462030A0811A +:109630002E703846BDE8F041F5F78BBD2DE9F05F9F +:109640000D46834601200978174606464FF0070865 +:10965000D1B1DFF868A24FF00009AAF1080A012988 +:1096600023D002297ED003290CD13978062909D1CB +:1096700079681022E86901F0E7FB08203870183596 +:1096800000207D60BDE8F09F2C6A8C48202284F881 +:109690000180203060602020A081686A6062696873 +:1096A000A06801F0D1FB2E70D4E039780629E9D109 +:1096B0002C6A84F80180686A606251681022E86947 +:1096C00001F0C2FBE8696060A0684F4680F8009036 +:1096D000A681A0684670A089401C80B2A081A168C4 +:1096E0000844696951F8012F026089888180A08946 +:1096F000801D80B2A0816969A268097801F001012A +:109700001154A089401C80B2A081A1680844296935 +:1097100051F8012F026089888180A089801D80B264 +:10972000A0812969A268097801F001011154A0897A +:109730001022401C80B2A081A1680844E96801F0B1 +:1097400083FBA0891022103080B2A081A168084458 +:10975000A96801F079FBA089103080B2A081A168CE +:10976000014400E00DE0DAF804000860A089001D63 +:1097700080B2A081A1680F54A089401CA081022062 +:1097800067E03978062992D151681022A86901F062 +:109790005BFB2C6A84F80180E8696060686A60623B +:1097A000A16881F80090A681A0684670A089401C3D +:1097B00080B2A081A1680844696951F8012F026054 +:1097C00089888180A089801D80B2A0816969A26892 +:1097D000097801F001011154A089401C80B2A081D8 +:1097E000A1680844296951F8012F026089888180A5 +:1097F000A089801D80B2A0812969A268097801F042 +:1098000001011154A0891022401C80B2A081A168DE +:109810000844E96801F018FBA0891022103080B2DA +:10982000A081A1680844A96801F00EFBA08910304E +:1098300080B2A081A1680144DAF804000860A08920 +:10984000001D80B2A081A1680E54A089401CA08197 +:109850000320287021465846BDE8F05FF5F779BC33 +:1098600070B50D4606460978012041B1012905D1A0 +:109870001178062902D109201070002070BD2C6AD1 +:109880000720607068686060686A6062E969A06863 +:1098900051F8012F0260898881800620A081E86943 +:1098A000A168007800F001008871A089401C80B296 +:1098B000A081A1680844A96902E000007EB501000A +:1098C00051F8012F026089888180A089801D80B2B3 +:1098D000A081A969A268097801F001011154A08949 +:1098E000401C80B2A081A168084469690A8802808E +:1098F00089788170A0891022C01C80B2A081A168E3 +:109900000844296901F0A0FAA0891022103080B221 +:10991000A081A1680844E96801F096FAA0891022A4 +:10992000103080B2A081A1680844A96801F08CFAC7 +:10993000A08921461030A081012028703046BDE862 +:109940007040F5F706BC70B50D4606460978012053 +:1099500059B1012908D11178062905D10A201070C2 +:10996000506800685060002070BD6C6907201022AC +:109970006070E8686060686A60622969A06801F0E8 +:1099800063FA1020A081A06820221030A96801F09D +:109990005BFAA0892022203080B2A081A16808440F +:1099A000696801F051FAA08921462030A081012088 +:1099B00028703046BDE87040F5F7CBBB70B50C465B +:1099C000012009788EB01546062659B1012934D0F8 +:1099D000022905D12978042902D10B20107000201A +:1099E0000EB070BD606910236A46007800F0010077 +:1099F0008DF80000A069007800F001008DF80100EA +:109A0000E0680168CDF802108188ADF80610807911 +:109A10008DF8080020690168CDF809108188ADF83B +:109A20000D1080798DF80F006068059009A80690E8 +:109A3000A168FFF7F5FC01201DE029780429CFD1AA +:109A4000A06910236A4650F8011F00918088ADF884 +:109A50000400606950F8011FCDF806108088ADF849 +:109A60000A00002003906068059009A806906968C4 +:109A7000FFF7D6FC022020708DF81060606A089015 +:109A8000294604A8F5F74EFBAAE700B50B7889B084 +:109A900001204BB1012B05D11178042902D10C20F2 +:109AA0001070002009B000BD4868019005A8029020 +:109AB000C868036805934068069088680368079340 +:109AC000406808900120087006208DF80000486A60 +:109AD000049011466846F5F725FBE3E700B50B78DF +:109AE00089B0012043B1012BDCD111780429D9D1EF +:109AF0000D2010700020D5E74868019005A802905D +:109B000088680368059340680690002007900890D5 +:109B10000120087006208DF80000486A0490114664 +:109B20006846F5F7FFFABDE700B50B7889B001206C +:109B300043B1012BB6D111780429B3D10E20107096 +:109B40000020AFE748680590CDF818D088680088F5 +:109B5000ADF80000C8680088ADF802000020019050 +:109B6000029003900120087006208DF81000486ACA +:109B70000890114604A8F5F7D5FA93E730B40346E8 +:109B80000C7801205CB1012C15D0022C05D1117884 +:109B90000D2902D10F201070002030BC7047012029 +:109BA0000870C868052242704A6842600B4A8260A9 +:109BB000921EC2600BE014780E2CEED102200870C9 +:109BC000C86804244470526842608A688260496AA6 +:109BD0004162014630BC1846F5F7BBBA78B50100C2 +:109BE0002DE9F0410C4611490D68104A1049083220 +:109BF0001160A0F12001342901D301200CE0482894 +:109C000010D040CC0B4F94E80E0007EB8000241FCF +:109C100050F8807C3046B84720600448001D05603D +:109C2000BDE8F0812046E7F7CBFAF5E710050240E2 +:109C300001000001B0B5010010B5524800F04EFA25 +:109C400000B1FFDF4F48401C00F048FA002800D068 +:109C5000FFDF10BD2DE9F14F4B4ED6F800B00127C4 +:109C6000484800F043FADFF81C8128B95FF000078C +:109C700008F1010000F050FA444C00254FF00309B0 +:109C800001206060C4F80051C4F8045100993160AB +:109C90002060DFF8FCA018E0DAF80000C00614D558 +:109CA0000E2000F064F8EFF3108010F0010072B69F +:109CB00000D00120C4F80493D4F8001119B9D4F8E5 +:109CC000041101B920BF00B962B6D4F8000118B977 +:109CD000D4F804010028DFD0D4F804010028CFD143 +:109CE00037B1C6F800B008F1010000F0FFF911E04B +:109CF00008F1010000F0FAF90028B9D1C4F808937E +:109D0000C4F80451C4F800510E2000F030F81D488A +:109D100000F002FA0020BDE8F88F2DE9F0438DB085 +:109D20000D46064600240DF110090DF1200817E03C +:109D300004EB4407102255F82710684601F084F818 +:109D400005EB870710224846796801F07DF86846E0 +:109D5000FFF780FF10224146B86801F075F8641CD7 +:109D6000B442E5DB0DB00020BDE8F08372E700F0FF +:109D70001F02012191404009800000F1E020C0F85D +:109D8000801270475401002004E5004000E00040CC +:109D900010ED00E0C748002101708170704770B578 +:109DA000C54D01232B60C54B1C68002CFCD0002442 +:109DB00007E00E6806601E68002EFCD0001D091D1D +:109DC000641C9442F5D30020286018680028FCD059 +:109DD00070BD70B5B74E0446B94D3078022800D03A +:109DE000FFDFAC4200D3FFDF7169B648012903D819 +:109DF00047F23052944201DD03224271491C7161E5 +:109E0000291BC160AF497078BDE87040F6F70CB906 +:109E100070B5A84C0D466178884200D0FFDFA84E8F +:109E2000092D4FD2DFE805F04E0522314E4E4E4E41 +:109E30003C002078022800D0FFDF03202070A078AB +:109E4000022802D0012804D008E0A06800F0F8FB46 +:109E500004E004F1080007C8FFF7A1FF0520207007 +:109E60000020A070BDE87040F5F7BFBBF5F78CFC93 +:109E700001466068F6F7D0FEB04202D2616902295D +:109E80000BD30320F7F730F912E0F5F77DFC01461C +:109E90006068F6F7C1FEB042F3D2BDE8704098E7C3 +:109EA000207802280AD0052806D0FFDF0420207081 +:109EB000BDE8704000F0F4B8022000E00320F7F79E +:109EC00013F9F3E7FFDF70BD70B50546F5F75CFCED +:109ED000784C60602078012800D0FFDF79490220AB +:109EE000087000220A718D6004224A71744ACA60A7 +:109EF00020706078BDE87040F6F796B810B56D4CEC +:109F0000A07808B9207808B1112010BD6E48F5F787 +:109F1000D6FB6070607820B1012020700020606165 +:109F200010BD032010BD0246010B0120B2F5003F19 +:109F300002D2884000F018BFB2F5802F03D220393A +:109F4000884000F019BFB2F5C02F03D240398840D5 +:109F500000F01BBFB2F5002F03D26039884000F03B +:109F60001DBF002070472DE9F041144600EB840727 +:109F70000E4605463F1F00F076FB4FF080510A6900 +:109F8000504306EB8402121FB24201D2012200E0CC +:109F900000221CB10969B4EB910F02D90920BDE878 +:109FA000F0814A498D4216D3AF4214D3854205D27F +:109FB000874203D245EA0600800701D01020EEE771 +:109FC0008E4208D33AB92846FFF7ADFF18B9384694 +:109FD000FFF7A9FF08B10F20E1E73D483D490068C0 +:109FE000884205D0224631462846FFF7D8FE10E0C9 +:109FF000FFF784FF0028D2D12E4801218560C0E9F7 +:10A00000036481704FF4A97104FB01F01830FFF76D +:10A010005BFF0020C3E770B54FF080550446286908 +:10A020002A49B1FBF0F084420AD300F01CFBA042A5 +:10A0300001D8102070BD28696043FFF774FF08B194 +:10A040000F2070BD224823490068884204D0286947 +:10A05000604300F0F5FA0CE0FFF750FF0028F0D164 +:10A060002969144861438160022181701A48FFF711 +:10A070002BFF002070BD1548010B01208840401EB9 +:10A08000704770B50D460446FFF7F5FF204201D03A +:10A090000F2070BD29462046BDE8704000F087BE05 +:10A0A00010B5044C6078F5F759FB00202070A070C3 +:10A0B00010BD00005801002004E5014000E401400B +:10A0C000105C0C0068110020119E010000C001000E +:10A0D00098000020BEBAFECA7C5E0100002101701B +:10A0E000084670470146002008707047EFF3108162 +:10A0F00001F0010172B60278012A01D0012200E0CC +:10A1000000220123037001B962B60AB10020704732 +:10A110004FF400507047E9E7EFF3108111F0010FA1 +:10A1200072B64FF00002027000D162B60020704794 +:10A13000F2E700004E4909680160002070474C4971 +:10A1400008600020704701218A0720B1012804D04F +:10A1500042F204007047916700E0D1670020704729 +:10A1600044490120086042F20600704708B5042304 +:10A17000404A1907103230B1C1F80433106840F07A +:10A18000010010600BE0106820F001001060C1F8C1 +:10A1900008330020C1F8080137480068009000200B +:10A1A00008BD3449103140B101280CD0022812D02A +:10A1B000032816D042F205007047086820F01E0000 +:10A1C00040F0100004E0086820F01E0040F0140089 +:10A1D000086000207047086820F01E0040F018005A +:10A1E000F6E7086820F01E0040F01C00F0E7214967 +:10A1F00024310A6802430A60002070471D49243157 +:10A200000A6882430A60002070471A4924310968AD +:10A2100001600020704717491C310A6802430A6038 +:10A220000020704713491C310A6882430A600020ED +:10A23000704710491C310968016000207047020016 +:10A240000E494FF0000003D0012A01D007207047CB +:10A250000A6070474FF080410020C1F808014FF0BC +:10A26000E020802180F800140121C0F8001170471F +:10A27000000400400005004008010040780500404F +:10A280006249634B0A6863499A42096801D1C1F384 +:10A2900010010160002070475C495D4B0A685D4910 +:10A2A000091D9A4201D1C0F31000086000207047D8 +:10A2B0005649574B0A68574908319A4201D1C0F3B1 +:10A2C000100008600020704730B5504B504D1C689E +:10A2D00042F20803AC4202D0142802D203E0112853 +:10A2E00001D3184630BDC3004B481844C0F81015C0 +:10A2F000C0F81425002030BD4449454B0A6842F29D +:10A3000009019A4202D0062802D203E0042801D3B0 +:10A3100008467047404A012142F83010002070473B +:10A320003A493B4B0A6842F209019A4202D0062898 +:10A3300002D203E0042801D308467047364A0121BF +:10A3400002EBC00041600020704770B52F4A304ECC +:10A35000314C156842F2090304EB8002B54204D087 +:10A36000062804D2C2F8001807E0042801D31846D2 +:10A3700070BDC1F31000C2F80008002070BD70B5B8 +:10A38000224A234E244C156842F2090304EB800252 +:10A39000B54204D0062804D2D2F8000807E0042809 +:10A3A00001D3184670BDD2F80008C0F31000086051 +:10A3B000002070BD174910B50831184808601120F9 +:10A3C000154A002102EBC003C3F81015C3F8141599 +:10A3D000401C1428F6D3002006E0042804D302EB26 +:10A3E0008003C3F8001807E002EB8003D3F80048AD +:10A3F000C4F31004C3F80048401C0628EDD310BD78 +:10A4000004490648083108607047000098000020A1 +:10A41000BEBAFECA00F5014000F001400000FEFF98 +:10A4200010B572B600F0C2F850B1E6F769FFF5F763 +:10A43000C4F8F6F7FFFDEFF712F861490020086055 +:10A4400062B6002010BD2DE9F0410F46044672B6F9 +:10A4500000F0ACF818B162B60820BDE8F081E6F76C +:10A46000C5FEE6F74FFF064600256909890001F1A0 +:10A47000E02105F01F00D1F80011C140C80717D036 +:10A48000202D03D226FA05F0C00716D168B20028A5 +:10A4900006DA00F00F0000F1E02090F8140D03E060 +:10A4A00000F1E02090F80004400900F0E5F820B148 +:10A4B0006D1C642DD9D324B104E062B641F20100D1 +:10A4C000CBE7404C2078022803D962B64FF4805085 +:10A4D000C3E73D49802081F8140DEEF797FF2078FF +:10A4E0000028607801D058B908E048B1202807D882 +:10A4F000A078212804D8012802D003E0A07808B170 +:10A500000720AAE72E493148086031480760E6F77E +:10A51000F9FE2146F6F774FDF5F703F800F0F4F9BB +:10A52000FFF738FC2046E6F7B9FE040062B603D018 +:10A53000FFF776FF204690E700208EE710B504462F +:10A5400000F034F800B101202070002010BD214936 +:10A5500008600020704770B50C461F490D681E4901 +:10A560001E4E08310E60102807D011280CD012287A +:10A570000FD0132811D0012013E0D4E90001FFF718 +:10A5800062FF354620600DE0FFF74AFF002520609E +:10A5900008E02068FFF7D2FF03E00E49206808605A +:10A5A000002020600C48001D056070BD044807496C +:10A5B0000068884201D101207047002070470000E8 +:10A5C0009800002080B601000BE000E0BEBAFECA91 +:10A5D000700100200400002010050240010000016D +:10A5E000F0B585B00F460646FEF7C4FD0446707808 +:10A5F000694600F01F053846F3F739F8C0B1012C61 +:10A6000007BF0199B1F80310032005B018BFF0BDD2 +:10A61000091D89B22844884238BF012008BF0020A4 +:10A620009CBF05B0F0BD00BF05B04FF00200F0BD0B +:10A63000022CF9D1042D28BFB6F80310F4D3E7E7B4 +:10A640000B4A022111600B490B68002BFCD0084B10 +:10A650001B1D186008680028FCD0002010600868E6 +:10A660000028FCD070474FF08050406970470000D0 +:10A6700004E5014000E40140082808D238B104286C +:10A6800005D0012803D0052801D001207047002003 +:10A69000704710B5044600F0F5F880B1204600F090 +:10A6A000E2F8FFF7E9FF68B17D4A04F01F010120DD +:10A6B000137888404BB15168084350600BE042F278 +:10A6C000010010BD42F2020010BD6109890001F1D4 +:10A6D000E021C1F80001002010BD10B5044600F0D3 +:10A6E000D1F850B16E4A04F01F0101201378884060 +:10A6F00033B151688143516008E042F2010010BD5E +:10A700006109890001F1E021C1F88001002010BD3C +:10A7100070B50D46044600F0B5F878B160098000C8 +:10A7200000F1E020D0F8000204F01F020121914066 +:10A73000084000D001202860002070BD42F20100D6 +:10A7400070BD10B5044600F09DF858B104F01F012B +:10A75000012088406109890001F1E021C1F800026F +:10A76000002010BD42F2010010BD10B5044600F0FB +:10A7700089F858B104F01F0101208840610989005F +:10A7800001F1E021C1F88002002010BD42F2010079 +:10A7900010BD70B50D46044600F074F870B128463F +:10A7A000FFF76AFF68B16807000E002C0CDA04F0AE +:10A7B0000F0101F1E02181F8140D09E042F20100DE +:10A7C00070BD42F2020070BD04F1E02484F8000480 +:10A7D000002070BD70B50C46054600F053F830B14E +:10A7E000284600F040F8C0B22060002070BD42F260 +:10A7F000010070BDBFF34F8F2A4801682A4A01F457 +:10A80000E06111430160BFF34F8FFEE770B505466D +:10A81000F7F7E6F808B1072070BD214C0120217838 +:10A8200089B9207072B6F6F714FC4FF0E026D6F81E +:10A83000801106F5C07681436160F6F70AFCC043DB +:10A84000306062B600202870002070BD14490A787C +:10A850003AB130B94FF0E0224868C2F80001002058 +:10A86000087000207047002806DA00F00F0000F1A1 +:10A87000E02090F8140D03E000F1E02090F80004CF +:10A880004009704710B50446642807DAF6F7E1FB83 +:10A890000121A140084201D1012010BD002010BDBE +:10A8A000740100200CED00E00400FA0510B54FF033 +:10A8B00000040B460200204621461ED0012A04D087 +:10A8C000022A04D0032A1DD103E0012002E0022065 +:10A8D00013E00320072B15D2DFE803F01404060869 +:10A8E0000A0C0E00012108E0022106E0032104E029 +:10A8F000042102E0052100E00621F4F7F9FE08B189 +:10A90000204610BD0724FBE7FE4805218170002189 +:10A9100001704170C17081607047FB490A78022A5A +:10A9200006D0CA681044C860C8683238F6F72FB934 +:10A930008A68104488608868F7E70378F349F44A26 +:10A9400013B1012B0ED011E00379012B00D06BB9AC +:10A9500043790BB1012B09D18368643B8B4205D24B +:10A96000C0680EE00379012B02D00BB100207047C4 +:10A9700043790BB1012BF9D1C368643B8B42F5D20B +:10A9800080689042F2D8012070472DE9F0470446D4 +:10A990000226F5F7ACFD006800B1FFDFD94D0127B5 +:10A9A0003CB12078B0B1012805D0022810D003288E +:10A9B00013D02F710CE06068C82807D3F6F757F959 +:10A9C00020B16068FFF7A9FF012603E0002601E03F +:10A9D00000F0AFF93046BDE8F08728780028F7D1BD +:10A9E0006068FFF7AAFF0028E3D06068DFF81883EB +:10A9F000007810B3A878042800D0FFDF0020474675 +:10AA000088F8000060680079C0B300203871606881 +:10AA10004079A0B30420787160688168E868F5F730 +:10AA200075F9B8606068C0683230F8600320A870BB +:10AA3000B549E878F5F7F8FACAE74FF00209404659 +:10AA400088F8009061680979D1B1002101716168CD +:10AA50004979B9B1042141716168896832318160F5 +:10AA60006168C968C160C068A64C14346060F4F7BE +:10AA70008BFE20606F7085F80290A9E704E005E086 +:10AA80000321E3E70321E6E70120BFE70320C2E754 +:10AA90002DE9F0479B4C8846E178884200D0FFDFE3 +:10AAA000DFF8609200250127974E09F11409B8F1EB +:10AAB000090F76D2DFE808F0050D2A3D646A769E1C +:10AAC0007E00A078032886D0A078022883D0FFDFFC +:10AAD00081E7A078032803D0A078022800D0FFDF08 +:10AAE0000420A0702571207800285FD1FFF715FFA2 +:10AAF0003078022806D0B068E06000F06CF9206180 +:10AB0000002048E0E078F5F71FF9F5E7A078032882 +:10AB100003D0A078022800D0FFDF207878BBA0788F +:10AB2000032812D1042026E00420F6F7DDFAA570F0 +:10AB300051E7A078032803D0A078022800D0FFDFD7 +:10AB40002078E0B9A078032814D0F4F71DFE014660 +:10AB50004F46D9F80000F6F75FF80028E4DB796883 +:10AB60008142E1DB081AF0606749E078BDE8F04710 +:10AB7000F5F75ABA0520F6F7B7FAA7702BE724E0E5 +:10AB8000A078042800D0FFDF022004E0A078042889 +:10AB900000D0FFDF0120A1688847FFF7F6FE0546D9 +:10ABA0002EE027E0A078042800D0FFDFBDE8F047C2 +:10ABB00000F0BFB8A078042805D0607810B1A07864 +:10ABC000022800D0FFDF207818B1BDE8F04700F080 +:10ABD000B9B8207920B10620F6F786FA2571CCE7BE +:10ABE000607828B14849E078F5F71EFA6570F2E61A +:10ABF0000720C0E7FFDFEEE63DB1012D03D0FFDF08 +:10AC0000022DF9D1E7E60420C5E70320C3E770B5BC +:10AC1000050005D03B4CA078052803D0112070BD5D +:10AC2000102070BD3B48F4F74AFDE070E07818B1A1 +:10AC3000A5600020A07070BD032070BD314810B524 +:10AC4000017809B1112010BD817805290CD08178D7 +:10AC500001290BD0817849B1012101708178012946 +:10AC600004D0807810B103E00F2010BD00F06AF826 +:10AC7000002010BD2DE9F041224E0446B07808B105 +:10AC800001280AD164B12046FFF757FE50B1207861 +:10AC90001D4D48B1B078012822D00F20BDE8F081C9 +:10ACA0001020FBE70720F9E702272F70207998B1E1 +:10ACB00000202871607988B104206871A068323062 +:10ACC000A860E068E860E8680E4C14346060F4F74F +:10ACD0005BFD2060B77022E00320EAE70320ECE789 +:10ACE00000202870207900B3002028716079F0B12D +:10ACF00004206871A168F068F5F708F8A860E068BA +:10AD0000323009E07C010020781100203D860100EE +:10AD1000FF1FA10791AA0100E8600320B07010494D +:10AD2000F078F5F781F90020B8E70320DDE703208C +:10AD3000DFE70C4810B5006900F045F8BDE81040A9 +:10AD4000F4F753BC10B5074CE078F4F707FD082082 +:10AD5000F6F7CAF90520A07000202070607010BDC1 +:10AD6000781100207C0100201F490968014201D0B0 +:10AD700001207047002070471B49091D09680142E6 +:10AD800001D0012070470020704717491031096831 +:10AD9000014201D001207047002070471249143150 +:10ADA0000968014201D0012070470020704710B5AA +:10ADB0000D4C2060201D01600B4810300260001D0A +:10ADC0000360002010BD09490A6848F202139A4343 +:10ADD00002430A607047054A116848F2021301EA0B +:10ADE000030099431160704700060040C806024006 +:10ADF00040EA010310B59B070FD1042A0DD310C8F8 +:10AE000008C9121F9C42F8D020BA19BA884201D949 +:10AE1000012010BD4FF0FF3010BD1AB1D30703D091 +:10AE2000521C07E0002010BD10F8013B11F8014B47 +:10AE30001B1B07D110F8013B11F8014B1B1B01D163 +:10AE4000921EF1D1184610BD032A40F2308010F056 +:10AE5000030C00F0158011F8013BBCF1020F6244B5 +:10AE600098BF11F801CB00F8013B38BF11F8013B46 +:10AE7000A2F1040298BF00F801CB38BF00F8013BF3 +:10AE800011F0030300F02580083AC0F0088051F863 +:10AE9000043B083A51F804CBA0E80810F5E7121D6E +:10AEA0005CBF51F8043B40F8043BAFF30080D2078D +:10AEB00024BF11F8013B11F801CB48BF11F8012B59 +:10AEC00024BF00F8013B00F801CB48BF00F8012B7C +:10AED000704710B5203AC0F00B80B1E81850203A06 +:10AEE000A0E81850B1E81850A0E81850BFF4F5AF2A +:10AEF0005FEA027C24BFB1E81850A0E8185044BFB4 +:10AF000018C918C0BDE810405FEA827C24BF51F820 +:10AF1000043B40F8043B08BF7047D20728BF31F814 +:10AF2000023B48BF11F8012B28BF20F8023B48BF65 +:10AF300000F8012B70474FF000020429C0F0128086 +:10AF400010F0030C00F01B80CCF1040CBCF1020FDC +:10AF500018BF00F8012BA8BF20F8022BA1EB0C01B1 +:10AF600000F00DB85FEAC17C24BF00F8012B00F8A7 +:10AF7000012B48BF00F8012B70474FF0000200B5CD +:10AF8000134694469646203922BFA0E80C50A0E80C +:10AF90000C50B1F12001BFF4F7AF090728BFA0E8BA +:10AFA0000C5048BF0CC05DF804EB890028BF40F886 +:10AFB000042B08BF704748BF20F8022B11F0804FC8 +:10AFC00018BF00F8012B70477047704770477047F3 +:10AFD000164B1860164B1960164B1A607047FEDF4F +:10AFE0000420714608421BD10699134A914217DC8E +:10AFF000069902394878DF2812D10878FE2808D04F +:10B00000FF280DD14FF001004FF000020B4B1B68E1 +:10B01000184741F201000099019A084B1B68184734 +:10B0200006980599064B1B68DB6818479C010020B1 +:10B03000A0010020A401002000C001007001002038 +:10B0400004000020204821497047FFF7FBFFE6F786 +:10B05000A5F800BD01200007C06AC0B2FF2806D1D4 +:10B060004FF0FF304FF010210968884203D0184894 +:10B070004FF0080101604FF480501649096888427A +:10B0800003D1154A13605B68184700BD20BFFDE778 +:10B090004FF480500F490968884210D10F4B18684F +:10B0A0004FF0FF318842F1D080F308884FF0202123 +:10B0B000884204DD0A48026802210A430260094806 +:10B0C000804709488047FFDF881100208811002051 +:10B0D0002C050040000000200400002000C00100FA +:10B0E000240500406D1A010055B00100042071468E +:10B0F000084202D0EFF3098101E0EFF3088188698B +:10B1000002380078102813DB20280FDB2B280BDBFC +:10B110000A4A12680A4B9A4203D1602804DB094AA2 +:10B120001047022008607047074A1047074A104737 +:10B13000074A12682C32126810470000980000205D +:10B14000BEBAFECA09130000E19B010057A5010029 +:10B15000040000200E4B0F4908470F4B0D490847CC +:10B160000E4B0C4908470E4B0A4908470D4B09493D +:10B1700008470D4B074908470C4B064908470C4B3D +:10B18000044908470B4B034908470B4B0149084743 +:10B190008791000051960000A52F0000AD8D0000A2 +:10B1A000318D0000639300002513000053740000EC +:10B1B000A78E0000D9950000A911000000210160B0 +:10B1C0004160017270470A6802600B790371704731 +:10B1D000AF7B00004F7D0000837B0000497E0000B4 +:10B1E0006D7E0000A77E0000DB7E0000157F000062 +:10B1F000457F0000977F000091120000911200002F +:10B2000091120000911200009112000091120000B2 +:10B21000F122000093230000B3230000BD240000AE +:10B22000FB1E000005270000E527000005280000A0 +:10B23000C72D0000EB2D00001B2D00006F2D00001E +:10B240001D2E0000A72E0000B34100007743000030 +:10B250001F4700003B480000BF4800006549000050 +:10B26000D5490000F14A0000BF4B00003B4C0000F4 +:10B270001F280000252800002F280000BD1E000008 +:10B28000FB2800008F1E0000552A000091120000CC +:10B29000195500009F550000BB550000D755000010 +:10B2A0004B570000015600000B5600004D560000A1 +:10B2B0006F560000315700009112000091120000FB +:10B2C00091120000911200009112000091120000F2 +:10B2D000236D0000436D0000456D00007F6D000090 +:10B2E000AD6D0000976E0000416F0000556F0000CB +:10B2F000A16F0000997000003F7200006F730000A2 +:10B300001D5F0000911200009112000091120000D8 +:10B31000E18900001F8A0000418A0000100110012D +:10B320003A0200001A0200006D740000FD76000071 +:10B33000FFFFFFFF0000FFFFEB830000CF1B0000BB +:10B3400045520000675F00009B760000000000008F +:10B350002300230046004D0023002300F5000000D9 +:10B36000000000000000000001BB00000000000021 +:10B37000000000000000000089C80000000000007C +:10B38000000000000000000061BB0000E7BB0000FF +:10B390000000000000000000E7BE00008FBC0000BD +:10B3A000C7C10000000000000000000009CD00003F +:10B3B0000000000000000000000000009BBF000033 +:10B3C0005FC900000000000033CA0000A7CA0000E7 +:10B3D0000000000061C200003DC30000000000004A +:10B3E0006DCA00009DC3000029C600008DC6000084 +:10B3F00083C7000069C100001DC8000000000000F4 +:10B4000081C000000000000079BD0000F3BC000016 +:10B41000C9C80000E5CB000053CC000000000000CC +:10B4200059BF00001FBD000011BF000047CE000043 +:10B43000AFBE000057CD000000000000B5CC0000FA +:10B440005DBC000093BB0000CDBD0000CBBC000084 +:10B45000C7CD0000E5CE0000E9BF0000A5CE00008A +:10B460008B3800008B380000CD220000558300008F +:10B47000DD6100001552000000000000FD700100B9 +:10B48000D1380000D1380000EF220000A98300006D +:10B49000576200001F52000009690100237101007A +:10B4A000BC01BC013E002C0044000E00D80020016D +:10B4B000010000000100000000010203040010115F +:10B4C000121300000014000057940100BD99010000 +:10B4D0008B9A0100DD9A0100299B01007D9B0100F0 +:10B4E000B1940100D59501003D96010061980100DD +:10B4F00047990100F7DD0000F7EE0000EF5B010067 +:10B500004B4E0100135C01004D4E0100253101003E +:10B510004384010063410100438401009131010033 +:10B52000B38501001B3B0100B38501009D30010084 +:10B53000418501009540010041850100555555D6D2 +:10B54000BE898E0000006606F30C801300000A031B +:10B550003B066C0900005604D308500D555555257F +:10B560002627D6BE898EF401FA00960064004B00AF +:10B5700032001E00140000000300656C74620000BD +:10B580000000000000000000000000000000870034 +:10B590000000000000000000000000000000BE836A +:10B5A000605ADB0B376038A5F5AA9183886C0000E0 +:10B5B00081A2010099A20100B1A20100C9A201006B +:10B5C000F9A2010021A301004BA301007FA3010008 +:10B5D00017A00100679F010083A00100DDA001000A +:10B5E000EDA0010019A1010093A60100DBA6010056 +:10B5F00011A7010043A701006BA7010093A7010059 +:10B60000D5A70100F5A701000DA801004DA8010074 +:10B610009F120100A7120100B512010047A101000D +:10B6200061A1010035A101003FA101006DA1010050 +:10B63000A3A10100EFA10100FDA101000BA20100E7 +:10B6400017A2010025A2010033A201003FA20100C0 +:10B65000000000004B8F0000A18F0000B78F00009A +:10B66000ADA80100559C01001B9D01000FAC01001D +:10B670003DAC010075AC0100951001006D15010095 +:10B6800000100200A4B6010008000020A001000084 +:10B6900044110000C8B60100A8010020E00F00001E +:10B6A0008011000001593601000100683720FB3489 +:10B6B0009B5F80041F800010022001337F0102E4A1 +:08B6C00029E4D1AF01000000F4 +:00000001FF diff --git a/cores/nRF5/SDK/components/softdevice/s132/toolchain/armgcc/armgcc_s132_nrf52832_xxaa.ld b/cores/nRF5/SDK/components/softdevice/s132/toolchain/armgcc/armgcc_s132_nrf52832_xxaa.ld index a338f850..dd970bee 100755 --- a/cores/nRF5/SDK/components/softdevice/s132/toolchain/armgcc/armgcc_s132_nrf52832_xxaa.ld +++ b/cores/nRF5/SDK/components/softdevice/s132/toolchain/armgcc/armgcc_s132_nrf52832_xxaa.ld @@ -6,7 +6,9 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x1c000, LENGTH = 0x64000 - RAM (rwx) : ORIGIN = 0x20002080, LENGTH = 0xdf80 + RAM (rwx) : ORIGIN = 0x20002780, LENGTH = 0xd880 + + UICR_NFCPINS(r) : ORIGIN = 0x1000120C, LENGTH = 0x04 } SECTIONS @@ -17,6 +19,12 @@ SECTIONS KEEP(*(.fs_data)) PROVIDE(__stop_fs_data = .); } > RAM + +.uicrNfcPinsAddress : + { + KEEP(*(.uicrNfcPinsAddress)) + } > UICR_NFCPINS + } INSERT AFTER .data; INCLUDE "nrf5x_common.ld" \ No newline at end of file diff --git a/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf51.S b/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf51.S index bb971bf8..febaf746 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf51.S +++ b/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf51.S @@ -1,45 +1,39 @@ -#if defined(ARDUINO) && defined(NRF51) -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ +#ifdef NRF51 +/* Copyright (c) 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ .syntax unified .arch armv6-m -#ifdef __STARTUP_CONFIG -#include "startup_config.h" -#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 -#endif -#endif - .section .stack -#if defined(__STARTUP_CONFIG) - .align __STARTUP_CONFIG_STACK_ALIGNEMENT - .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE -#elif defined(__STACK_SIZE) .align 3 +#ifdef __STACK_SIZE .equ Stack_Size, __STACK_SIZE #else - .align 3 .equ Stack_Size, 2048 #endif .globl __StackTop @@ -52,12 +46,10 @@ __StackTop: .section .heap .align 3 -#if defined(__STARTUP_CONFIG) - .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE -#elif defined(__HEAP_SIZE) +#ifdef __HEAP_SIZE .equ Heap_Size, __HEAP_SIZE #else - .equ Heap_Size, 2048 + .equ Heap_Size, 2048 #endif .globl __HeapBase .globl __HeapLimit @@ -69,7 +61,7 @@ __HeapBase: __HeapLimit: .size __HeapLimit, . - __HeapLimit - .section .isr_vector, "ax" + .section .isr_vector .align 2 .globl __isr_vector __isr_vector: @@ -141,7 +133,7 @@ __isr_vector: Reset_Handler: MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk - + LDR R0, =NRF_POWER_RAMON_ADDRESS LDR R2, [R0] ORRS R2, R1 @@ -157,26 +149,24 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * the user can add their own initialized data section before BSS section with the INTERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ -#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ - subs r3, r3, r2 + subs r3, r2 ble .L_loop1_done .L_loop1: - subs r3, r3, #4 + subs r3, #4 ldr r0, [r1,r3] str r0, [r2,r3] bgt .L_loop1 .L_loop1_done: -#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section @@ -194,11 +184,11 @@ Reset_Handler: movs r0, 0 - subs r2, r2, r1 + subs r2, r1 ble .L_loop3_done .L_loop3: - subs r2, r2, #4 + subs r2, #4 str r0, [r1, r2] bgt .L_loop3 diff --git a/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf52.S b/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf52.S index 7778c8f0..2df44e76 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf52.S +++ b/cores/nRF5/SDK/components/toolchain/gcc/gcc_startup_nrf52.S @@ -1,46 +1,40 @@ -#if defined(ARDUINO) && defined(NRF52) -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ +#ifdef NRF52 +/* Copyright (c) 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ .syntax unified .arch armv7e-m -#ifdef __STARTUP_CONFIG -#include "startup_config.h" -#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT -#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3 -#endif -#endif - .section .stack -#if defined(__STARTUP_CONFIG) - .align __STARTUP_CONFIG_STACK_ALIGNEMENT - .equ Stack_Size, __STARTUP_CONFIG_STACK_SIZE -#elif defined(__STACK_SIZE) .align 3 +#ifdef __STACK_SIZE .equ Stack_Size, __STACK_SIZE #else - .align 3 - .equ Stack_Size, 4096 + .equ Stack_Size, 8192 #endif .globl __StackTop .globl __StackLimit @@ -52,12 +46,10 @@ __StackTop: .section .heap .align 3 -#if defined(__STARTUP_CONFIG) - .equ Heap_Size, __STARTUP_CONFIG_HEAP_SIZE -#elif defined(__HEAP_SIZE) +#ifdef __HEAP_SIZE .equ Heap_Size, __HEAP_SIZE #else - .equ Heap_Size, 4096 + .equ Heap_Size, 8192 #endif .globl __HeapBase .globl __HeapLimit @@ -69,7 +61,7 @@ __HeapBase: __HeapLimit: .size __HeapLimit, . - __HeapLimit - .section .isr_vector, "ax" + .section .isr_vector .align 2 .globl __isr_vector __isr_vector: @@ -85,7 +77,7 @@ __isr_vector: .long 0 /*Reserved */ .long 0 /*Reserved */ .long SVC_Handler - .long DebugMon_Handler + .long DebugMonitor_Handler .long 0 /*Reserved */ .long PendSV_Handler .long SysTick_Handler @@ -203,6 +195,134 @@ __isr_vector: .long 0 /*Reserved */ .long 0 /*Reserved */ .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ + .long 0 /*Reserved */ .size __isr_vector, . - __isr_vector @@ -223,26 +343,24 @@ Reset_Handler: * __etext: LMA of start of the section to copy from. Usually end of text * __data_start__: VMA of start of the section to copy to. * __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__ - * the user can add their own initialized data section before BSS section with the INSERT AFTER command. + * the user can add their own initialized data section before BSS section with the INTERT AFTER command. * * All addresses must be aligned to 4 bytes boundary. */ -#ifndef __STARTUP_SKIP_ETEXT ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__bss_start__ - subs r3, r3, r2 + subs r3, r2 ble .L_loop1_done .L_loop1: - subs r3, r3, #4 + subs r3, #4 ldr r0, [r1,r3] str r0, [r2,r3] bgt .L_loop1 .L_loop1_done: -#endif /* This part of work usually is done in C library startup code. Otherwise, * define __STARTUP_CLEAR_BSS to enable it in this startup. This section @@ -260,11 +378,11 @@ Reset_Handler: movs r0, 0 - subs r2, r2, r1 + subs r2, r1 ble .L_loop3_done .L_loop3: - subs r2, r2, #4 + subs r2, #4 str r0, [r1, r2] bgt .L_loop3 @@ -332,11 +450,11 @@ SVC_Handler: .size SVC_Handler, . - SVC_Handler - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: + .weak DebugMonitor_Handler + .type DebugMonitor_Handler, %function +DebugMonitor_Handler: b . - .size DebugMon_Handler, . - DebugMon_Handler + .size DebugMonitor_Handler, . - DebugMonitor_Handler .weak PendSV_Handler diff --git a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_common.ld b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_common.ld index 1495511d..69c98f89 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_common.ld +++ b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_common.ld @@ -1,6 +1,4 @@ -/* Deprecated linker script for Nordic Semiconductor nRF51 devices - * please use nrfx_common.ld. This version exists for backwards - * compatibility. +/* Linker script for Nordic Semiconductor nRF51 devices * * Version: Sourcery G++ 4.5-1 * Support: https://support.codesourcery.com/GNUToolchain/ @@ -23,7 +21,7 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end @@ -40,7 +38,6 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") * __bss_end__ * __end__ * end - * __HeapBase * __HeapLimit * __StackLimit * __StackTop @@ -76,8 +73,8 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - - .ARM.extab : + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -89,9 +86,8 @@ SECTIONS } > FLASH __exidx_end = .; - . = ALIGN(4); __etext = .; - + .data : AT (__etext) { __data_start__ = .; @@ -138,10 +134,9 @@ SECTIONS .heap (COPY): { - __HeapBase = .; __end__ = .; PROVIDE(end = .); - KEEP(*(.heap*)) + *(.heap*) __HeapLimit = .; } > RAM @@ -150,7 +145,7 @@ SECTIONS * values to stack symbols later */ .stack_dummy (COPY): { - KEEP(*(.stack*)) + *(.stack*) } > RAM /* Set stack top to end of RAM, and stack limit move down by @@ -158,14 +153,8 @@ SECTIONS __StackTop = ORIGIN(RAM) + LENGTH(RAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); - + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if text sections + data exceeds FLASH limit */ - DataInitFlashUsed = __bss_start__ - __data_start__; - CodeFlashUsed = __etext - ORIGIN(FLASH); - TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; - ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - } + diff --git a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxaa.ld b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxaa.ld index 03958b36..387559b6 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxaa.ld +++ b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxaa.ld @@ -6,8 +6,8 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 } -INCLUDE "nrf_common.ld" +INCLUDE "nrf51_common.ld" diff --git a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxab.ld b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxab.ld index df2854c0..277fe118 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxab.ld +++ b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxab.ld @@ -6,8 +6,8 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 } -INCLUDE "nrf_common.ld" +INCLUDE "nrf51_common.ld" diff --git a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxac.ld b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxac.ld index de01abf2..5750f382 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxac.ld +++ b/cores/nRF5/SDK/components/toolchain/gcc/nrf51_xxac.ld @@ -6,8 +6,8 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 } -INCLUDE "nrf_common.ld" +INCLUDE "nrf51_common.ld" diff --git a/cores/nRF5/SDK/components/toolchain/gcc/nrf52_common.ld b/cores/nRF5/SDK/components/toolchain/gcc/nrf52_common.ld index c0ff5542..75e2f4c5 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/nrf52_common.ld +++ b/cores/nRF5/SDK/components/toolchain/gcc/nrf52_common.ld @@ -1,6 +1,4 @@ -/* Deprecated linker script for Nordic Semiconductor nRF52 devices, - * please use nrfx_common.ld. This version exists for backwards - * compatibility. +/* Linker script for Nordic Semiconductor nRF52 devices * * Version: Sourcery G++ 4.5-1 * Support: https://support.codesourcery.com/GNUToolchain/ @@ -23,7 +21,7 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end @@ -40,7 +38,6 @@ OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") * __bss_end__ * __end__ * end - * __HeapBase * __HeapLimit * __StackLimit * __StackTop @@ -76,8 +73,8 @@ SECTIONS KEEP(*(.eh_frame*)) } > FLASH - - .ARM.extab : + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH @@ -89,9 +86,8 @@ SECTIONS } > FLASH __exidx_end = .; - . = ALIGN(4); __etext = .; - + .data : AT (__etext) { __data_start__ = .; @@ -135,13 +131,12 @@ SECTIONS . = ALIGN(4); __bss_end__ = .; } > RAM - + .heap (COPY): { - __HeapBase = .; __end__ = .; PROVIDE(end = .); - KEEP(*(.heap*)) + *(.heap*) __HeapLimit = .; } > RAM @@ -150,7 +145,7 @@ SECTIONS * values to stack symbols later */ .stack_dummy (COPY): { - KEEP(*(.stack*)) + *(.stack*) } > RAM /* Set stack top to end of RAM, and stack limit move down by @@ -158,14 +153,8 @@ SECTIONS __StackTop = ORIGIN(RAM) + LENGTH(RAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); PROVIDE(__stack = __StackTop); - + /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - /* Check if text sections + data exceeds FLASH limit */ - DataInitFlashUsed = __bss_start__ - __data_start__; - CodeFlashUsed = __etext - ORIGIN(FLASH); - TotalFlashUsed = CodeFlashUsed + DataInitFlashUsed; - ASSERT(TotalFlashUsed <= LENGTH(FLASH), "region FLASH overflowed with .data and user data") - } + diff --git a/cores/nRF5/SDK/components/toolchain/gcc/nrf52_xxaa.ld b/cores/nRF5/SDK/components/toolchain/gcc/nrf52_xxaa.ld index fc571720..bc89f440 100755 --- a/cores/nRF5/SDK/components/toolchain/gcc/nrf52_xxaa.ld +++ b/cores/nRF5/SDK/components/toolchain/gcc/nrf52_xxaa.ld @@ -6,9 +6,8 @@ GROUP(-lgcc -lc -lnosys) MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 - CODE_RAM (rwx) : ORIGIN = 0x800000, LENGTH = 0x10000 + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 } -INCLUDE "nrf_common.ld" +INCLUDE "nrf52_common.ld" diff --git a/cores/nRF5/SDK/components/toolchain/system_nrf51.c b/cores/nRF5/SDK/components/toolchain/system_nrf51.c index 1b0b538b..14e6c867 100755 --- a/cores/nRF5/SDK/components/toolchain/system_nrf51.c +++ b/cores/nRF5/SDK/components/toolchain/system_nrf51.c @@ -1,24 +1,34 @@ -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifdef NRF51 /* NOTE: Template files (including this one) are application specific and therefore expected to be copied into the application project folder prior to its use! */ @@ -26,8 +36,6 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #include #include #include "nrf.h" -#include "nrf_erratas.h" -#if defined(ARDUINO) && defined(NRF51_SERIES) #include "system_nrf51.h" /*lint ++flb "Enter library region" */ @@ -35,6 +43,11 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. #define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ +static bool is_manual_peripheral_setup_needed(void); +static bool is_disabled_in_debug_needed(void); +static bool is_peripheral_domain_setup_needed(void); + + #if defined ( __CC_ARM ) uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; #elif defined ( __ICCARM__ ) @@ -55,10 +68,10 @@ void SystemInit(void) /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required to enable the use of peripherals" found at Product Anomaly document for your device found at - https://infocenter.nordicsemi.com/index.jsp The side effect of executing these instructions in the devices + https://www.nordicsemi.com/. The side effect of executing these instructions in the devices that do not need it is that the new peripherals in the second generation devices (LPCOMP for example) will not be available. */ - if (nrf51_errata_26()) + if (is_manual_peripheral_setup_needed()) { *(uint32_t volatile *)0x40000504 = 0xC007FFDF; *(uint32_t volatile *)0x40006C18 = 0x00008000; @@ -66,16 +79,16 @@ void SystemInit(void) /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG register is incorrect" found at Product Anomaly document for your device found at - https://infocenter.nordicsemi.com/index.jsp There is no side effect of using these instruction if not needed. */ - if (nrf51_errata_59()) + https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ + if (is_disabled_in_debug_needed()) { NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; } /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices, as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document - for your device found at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf51_errata_76()){ + for your device found at https://www.nordicsemi.com/. */ + if (is_peripheral_domain_setup_needed()){ if (*(uint32_t volatile *)0x4006EC00 != 1){ *(uint32_t volatile *)0x4006EC00 = 0x9375; while (*(uint32_t volatile *)0x4006EC00 != 1){ @@ -83,9 +96,60 @@ void SystemInit(void) } *(uint32_t volatile *)0x4006EC14 = 0xC0; } +} + + +static bool is_manual_peripheral_setup_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } - SystemCoreClockUpdate(); + return false; +} + +static bool is_disabled_in_debug_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; +} + +static bool is_peripheral_domain_setup_needed(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) + { + return true; + } + } + + return false; } /*lint --flb "Leave library region" */ + #endif diff --git a/cores/nRF5/SDK/components/toolchain/system_nrf51.h b/cores/nRF5/SDK/components/toolchain/system_nrf51.h index 15e58b89..33ed2d54 100755 --- a/cores/nRF5/SDK/components/toolchain/system_nrf51.h +++ b/cores/nRF5/SDK/components/toolchain/system_nrf51.h @@ -1,24 +1,32 @@ -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef SYSTEM_NRF51_H #define SYSTEM_NRF51_H @@ -49,7 +57,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/cores/nRF5/SDK/components/toolchain/system_nrf52.c b/cores/nRF5/SDK/components/toolchain/system_nrf52.c index 6bcfcd8f..3ee739d4 100755 --- a/cores/nRF5/SDK/components/toolchain/system_nrf52.c +++ b/cores/nRF5/SDK/components/toolchain/system_nrf52.c @@ -1,38 +1,52 @@ -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifdef NRF52 #include #include #include "nrf.h" -#include "nrf_peripherals.h" -#include "nrf_erratas.h" -#if defined(ARDUINO) && defined(NRF52_SERIES) #include "system_nrf52.h" +/*lint ++flb "Enter library region" */ + #define __SYSTEM_CLOCK_64M (64000000UL) +static bool errata_16(void); +static bool errata_31(void); +static bool errata_32(void); +static bool errata_36(void); +static bool errata_37(void); +static bool errata_57(void); +static bool errata_66(void); + #if defined ( __CC_ARM ) uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; @@ -42,46 +56,6 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA. uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M; #endif -/* Select correct reset pin */ -/* Handle DEVELOP_IN-targets first as they take precedence over the later macros */ -#if defined (DEVELOP_IN_NRF52805) \ - || defined (DEVELOP_IN_NRF52810) \ - || defined (DEVELOP_IN_NRF52811) \ - || defined (DEVELOP_IN_NRF52832) - #define RESET_PIN 21 -#elif defined (DEVELOP_IN_NRF52820) \ - || defined (DEVELOP_IN_NRF52833) \ - || defined (DEVELOP_IN_NRF52840) - #define RESET_PIN 18 -#elif defined (NRF52805_XXAA) \ - || defined (NRF52810_XXAA) \ - || defined (NRF52811_XXAA) \ - || defined (NRF52832_XXAA) \ - || defined (NRF52832_XXAB) - #define RESET_PIN 21 -#elif defined (NRF52820_XXAA) \ - || defined (NRF52833_XXAA) \ - || defined (NRF52840_XXAA) - #define RESET_PIN 18 -#else - #error "A supported device macro must be defined." -#endif - -/* -- NVMC utility functions -- */ -/* Waits until NVMC is done with the current pending action */ -void nvmc_wait(void) -{ - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} -} - -/* Configure the NVMC to "mode". - Mode must be an enumerator of field NVMC_CONFIG_WEN */ -void nvmc_config(uint32_t mode) -{ - NRF_NVMC->CONFIG = mode << NVMC_CONFIG_WEN_Pos; - nvmc_wait(); -} - void SystemCoreClockUpdate(void) { SystemCoreClock = __SYSTEM_CLOCK_64M; @@ -89,9 +63,114 @@ void SystemCoreClockUpdate(void) void SystemInit(void) { + /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_16()){ + *(volatile uint32_t *)0x4007C074 = 3131961357ul; + } + + /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_31()){ + *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; + } + + /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_32()){ + CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; + } + + /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_36()){ + NRF_CLOCK->EVENTS_DONE = 0; + NRF_CLOCK->EVENTS_CTTO = 0; + NRF_CLOCK->CTIV = 0; + } + + /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_37()){ + *(volatile uint32_t *)0x400005A0 = 0x3; + } + + /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_57()){ + *(volatile uint32_t *)0x40005610 = 0x00000005; + *(volatile uint32_t *)0x40005688 = 0x00000001; + *(volatile uint32_t *)0x40005618 = 0x00000000; + *(volatile uint32_t *)0x40005614 = 0x0000003F; + } + + /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document + for your device located at https://infocenter.nordicsemi.com/ */ + if (errata_66()){ + NRF_TEMP->A0 = NRF_FICR->TEMP.A0; + NRF_TEMP->A1 = NRF_FICR->TEMP.A1; + NRF_TEMP->A2 = NRF_FICR->TEMP.A2; + NRF_TEMP->A3 = NRF_FICR->TEMP.A3; + NRF_TEMP->A4 = NRF_FICR->TEMP.A4; + NRF_TEMP->A5 = NRF_FICR->TEMP.A5; + NRF_TEMP->B0 = NRF_FICR->TEMP.B0; + NRF_TEMP->B1 = NRF_FICR->TEMP.B1; + NRF_TEMP->B2 = NRF_FICR->TEMP.B2; + NRF_TEMP->B3 = NRF_FICR->TEMP.B3; + NRF_TEMP->B4 = NRF_FICR->TEMP.B4; + NRF_TEMP->B5 = NRF_FICR->TEMP.B5; + NRF_TEMP->T0 = NRF_FICR->TEMP.T0; + NRF_TEMP->T1 = NRF_FICR->TEMP.T1; + NRF_TEMP->T2 = NRF_FICR->TEMP.T2; + NRF_TEMP->T3 = NRF_FICR->TEMP.T3; + NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + } + + /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the + * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit + * operations are not used in your code. */ + #if (__FPU_USED == 1) + SCB->CPACR |= (3UL << 20) | (3UL << 22); + __DSB(); + __ISB(); + #endif + + /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, + two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as + normal GPIOs. */ + #if defined (CONFIG_NFCT_PINS_AS_GPIOS) + if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + + /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not + defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be + reserved for PinReset and not available as normal GPIO. */ + #if defined (CONFIG_GPIO_AS_PINRESET) + if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || + ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[0] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_UICR->PSELRESET[1] = 21; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; + while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} + NVIC_SystemReset(); + } + #endif + /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product Specification to see which one). */ - #if defined (ENABLE_SWO) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) + #if defined (ENABLE_SWO) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); @@ -99,7 +178,7 @@ void SystemInit(void) /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product Specification to see which ones). */ - #if defined (ENABLE_TRACE) && defined(CLOCK_TRACECONFIG_TRACEMUX_Pos) + #if defined (ENABLE_TRACE) CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos; NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); @@ -109,210 +188,118 @@ void SystemInit(void) NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); #endif - #if NRF52_ERRATA_12_ENABLE_WORKAROUND - /* Workaround for Errata 12 "COMP: Reference ladder not correctly calibrated" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_12()){ - *(volatile uint32_t *)0x40013540 = (*(uint32_t *)0x10000324 & 0x00001F00) >> 8; - } - #endif - - #if NRF52_ERRATA_16_ENABLE_WORKAROUND - /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_16()){ - *(volatile uint32_t *)0x4007C074 = 3131961357ul; - } - #endif + SystemCoreClockUpdate(); +} - #if NRF52_ERRATA_31_ENABLE_WORKAROUND - /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_31()){ - *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13; - } - #endif - #if NRF52_ERRATA_32_ENABLE_WORKAROUND - /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_32()){ - CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; +static bool errata_16(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; } - #endif + } - #if NRF52_ERRATA_36_ENABLE_WORKAROUND - /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_36()){ - NRF_CLOCK->EVENTS_DONE = 0; - NRF_CLOCK->EVENTS_CTTO = 0; - NRF_CLOCK->CTIV = 0; - } - #endif + return false; +} - #if NRF52_ERRATA_37_ENABLE_WORKAROUND - /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_37()){ - *(volatile uint32_t *)0x400005A0 = 0x3; +static bool errata_31(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; } - #endif - - #if NRF52_ERRATA_57_ENABLE_WORKAROUND - /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_57()){ - *(volatile uint32_t *)0x40005610 = 0x00000005; - *(volatile uint32_t *)0x40005688 = 0x00000001; - *(volatile uint32_t *)0x40005618 = 0x00000000; - *(volatile uint32_t *)0x40005614 = 0x0000003F; + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) + { + return true; } - #endif - - #if NRF52_ERRATA_66_ENABLE_WORKAROUND - /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_66()){ - NRF_TEMP->A0 = NRF_FICR->TEMP.A0; - NRF_TEMP->A1 = NRF_FICR->TEMP.A1; - NRF_TEMP->A2 = NRF_FICR->TEMP.A2; - NRF_TEMP->A3 = NRF_FICR->TEMP.A3; - NRF_TEMP->A4 = NRF_FICR->TEMP.A4; - NRF_TEMP->A5 = NRF_FICR->TEMP.A5; - NRF_TEMP->B0 = NRF_FICR->TEMP.B0; - NRF_TEMP->B1 = NRF_FICR->TEMP.B1; - NRF_TEMP->B2 = NRF_FICR->TEMP.B2; - NRF_TEMP->B3 = NRF_FICR->TEMP.B3; - NRF_TEMP->B4 = NRF_FICR->TEMP.B4; - NRF_TEMP->B5 = NRF_FICR->TEMP.B5; - NRF_TEMP->T0 = NRF_FICR->TEMP.T0; - NRF_TEMP->T1 = NRF_FICR->TEMP.T1; - NRF_TEMP->T2 = NRF_FICR->TEMP.T2; - NRF_TEMP->T3 = NRF_FICR->TEMP.T3; - NRF_TEMP->T4 = NRF_FICR->TEMP.T4; + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) + { + return true; } - #endif + } - #if NRF52_ERRATA_98_ENABLE_WORKAROUND - /* Workaround for Errata 98 "NFCT: Not able to communicate with the peer" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_98()){ - *(volatile uint32_t *)0x4000568Cul = 0x00038148ul; - } - #endif + return false; +} - #if NRF52_ERRATA_103_ENABLE_WORKAROUND && defined(CCM_MAXPACKETSIZE_MAXPACKETSIZE_Pos) - /* Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_103()){ - NRF_CCM->MAXPACKETSIZE = 0xFBul; +static bool errata_32(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; } - #endif + } - #if NRF52_ERRATA_108_ENABLE_WORKAROUND - /* Workaround for Errata 108 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_108()){ - *(volatile uint32_t *)0x40000EE4ul = *(volatile uint32_t *)0x10000258ul & 0x0000004Ful; - } - #endif + return false; +} - #if NRF52_ERRATA_115_ENABLE_WORKAROUND - /* Workaround for Errata 115 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_115()){ - *(volatile uint32_t *)0x40000EE4 = (*(volatile uint32_t *)0x40000EE4 & 0xFFFFFFF0) | (*(uint32_t *)0x10000258 & 0x0000000F); +static bool errata_36(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; } - #endif - - #if NRF52_ERRATA_120_ENABLE_WORKAROUND - /* Workaround for Errata 120 "QSPI: Data read or written is corrupted" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_120()){ - *(volatile uint32_t *)0x40029640ul = 0x200ul; + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) + { + return true; } - #endif - - #if NRF52_ERRATA_136_ENABLE_WORKAROUND - /* Workaround for Errata 136 "System: Bits in RESETREAS are set when they should not be" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_136()){ - if (NRF_POWER->RESETREAS & POWER_RESETREAS_RESETPIN_Msk){ - NRF_POWER->RESETREAS = ~POWER_RESETREAS_RESETPIN_Msk; - } + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) + { + return true; } - #endif + } - #if NRF52_ERRATA_182_ENABLE_WORKAROUND - /* Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and #107 do not take effect" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_182()){ - *(volatile uint32_t *) 0x4000173C |= (0x1 << 10); - } - #endif + return false; +} - #if NRF52_ERRATA_217_ENABLE_WORKAROUND - /* Workaround for Errata 217 "RAM: RAM content cannot be trusted upon waking up from System ON Idle or System OFF mode" found at the Errata document - for your device located at https://infocenter.nordicsemi.com/index.jsp */ - if (nrf52_errata_217()){ - *(volatile uint32_t *)0x40000EE4ul |= 0x0000000Ful; +static bool errata_37(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; } - #endif + } - /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the - * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit - * operations are not used in your code. */ - #if (__FPU_USED == 1) - SCB->CPACR |= (3UL << 20) | (3UL << 22); - __DSB(); - __ISB(); - #endif + return false; +} - /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined, - two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as - normal GPIOs. */ - #if defined (CONFIG_NFCT_PINS_AS_GPIOS) && defined(NFCT_PRESENT) - if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){ - nvmc_config(NVMC_CONFIG_WEN_Wen); - NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk; - nvmc_wait(); - nvmc_config(NVMC_CONFIG_WEN_Ren); - NVIC_SystemReset(); +static bool errata_57(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) + { + return true; } - #endif + } - /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not - defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be - reserved for PinReset and not available as normal GPIO. */ - #if defined (CONFIG_GPIO_AS_PINRESET) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ - nvmc_config(NVMC_CONFIG_WEN_Wen); - NRF_UICR->PSELRESET[0] = RESET_PIN; - nvmc_wait(); - NRF_UICR->PSELRESET[1] = RESET_PIN; - nvmc_wait(); - nvmc_config(NVMC_CONFIG_WEN_Ren); - NVIC_SystemReset(); - } - #endif + return false; +} - /* When developing for nRF52810 on an nRF52832, or nRF52811 on an nRF52840, - make sure NFC pins are mapped as GPIO. */ - #if defined (DEVELOP_IN_NRF52832) && defined(NRF52810_XXAA) \ - || defined (DEVELOP_IN_NRF52840) && defined(NRF52811_XXAA) - if (((*((uint32_t *)0x10001200) & (1 << 0)) != 0) || ((*((uint32_t *)0x10001204) & (1 << 0)) != 0)){ - nvmc_config(NVMC_CONFIG_WEN_Wen); - *((uint32_t *)0x10001200) = 0; - nvmc_wait(); - *((uint32_t *)0x10001204) = 0; - nvmc_wait(); - nvmc_config(NVMC_CONFIG_WEN_Ren); - NVIC_SystemReset(); +static bool errata_66(void) +{ + if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) + { + if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50) + { + return true; } - #endif + } - SystemCoreClockUpdate(); + return false; } + + +/*lint --flb "Leave library region" */ + #endif diff --git a/cores/nRF5/SDK/components/toolchain/system_nrf52.h b/cores/nRF5/SDK/components/toolchain/system_nrf52.h index 753efc58..d16037fc 100755 --- a/cores/nRF5/SDK/components/toolchain/system_nrf52.h +++ b/cores/nRF5/SDK/components/toolchain/system_nrf52.h @@ -1,24 +1,32 @@ -/* - -Copyright (c) 2009-2020 ARM Limited. All rights reserved. - - SPDX-License-Identifier: Apache-2.0 - -Licensed under the Apache License, Version 2.0 (the License); you may -not use this file except in compliance with the License. -You may obtain a copy of the License at - - www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an AS IS BASIS, WITHOUT -WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -NOTICE: This file has been modified by Nordic Semiconductor ASA. - -*/ +/* Copyright (c) 2015, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * * Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ #ifndef SYSTEM_NRF52_H #define SYSTEM_NRF52_H @@ -49,7 +57,7 @@ extern void SystemInit (void); * @param none * @return none * - * @brief Updates the SystemCoreClock with current core Clock + * @brief Updates the SystemCoreClock with current core Clock * retrieved from cpu registers. */ extern void SystemCoreClockUpdate (void); diff --git a/cores/nRF5/Uart.cpp b/cores/nRF5/Uart.cpp index bc6b923f..9f6b7f92 100644 --- a/cores/nRF5/Uart.cpp +++ b/cores/nRF5/Uart.cpp @@ -78,7 +78,7 @@ void Uart::begin(unsigned long baudrate, uint16_t /*config*/) uint32_t nrfBaudRate; -#if defined(NRF52_SERIES) +#ifdef NRF52 if (baudrate <= 1200) { nrfBaudRate = UARTE_BAUDRATE_BAUDRATE_Baud1200; } else if (baudrate <= 2400) { @@ -225,9 +225,9 @@ size_t Uart::write(const uint8_t data) return 1; } -#if defined(NRF52_SERIES) +#if defined(NRF52) #define NRF_UART0_IRQn UARTE0_UART0_IRQn -#elif defined(NRF51_SERIES) +#elif defined(NRF51) #define NRF_UART0_IRQn UART0_IRQn #endif @@ -237,7 +237,7 @@ size_t Uart::write(const uint8_t data) Uart Serial( NRF_UART0, NRF_UART0_IRQn, PIN_SERIAL_RX, PIN_SERIAL_TX ); #endif -#if defined(NRF52_SERIES) +#if defined(NRF52) extern "C" { void UARTE0_UART0_IRQHandler() @@ -245,7 +245,7 @@ extern "C" Serial.IrqHandler(); } } -#elif defined(NRF51_SERIES) +#elif defined(NRF51) extern "C" { void UART0_IRQHandler() diff --git a/cores/nRF5/WInterrupts.c b/cores/nRF5/WInterrupts.c index 3ea3f1a9..14600998 100644 --- a/cores/nRF5/WInterrupts.c +++ b/cores/nRF5/WInterrupts.c @@ -16,6 +16,8 @@ License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define _REMOVED_CODE_ +#ifdef _REMOVED_CODE_ #include @@ -24,7 +26,7 @@ #include -#if defined(NRF52_SERIES) +#ifdef NRF52 #define NUMBER_OF_GPIO_TE 8 #else #define NUMBER_OF_GPIO_TE 4 @@ -42,7 +44,7 @@ static void __initialize() NVIC_DisableIRQ(GPIOTE_IRQn); NVIC_ClearPendingIRQ(GPIOTE_IRQn); - NVIC_SetPriority(GPIOTE_IRQn, 2); + NVIC_SetPriority(GPIOTE_IRQn, 1); NVIC_EnableIRQ(GPIOTE_IRQn); } @@ -136,12 +138,14 @@ void GPIOTE_IRQHandler() } *(uint32_t *)((uint32_t)NRF_GPIOTE + event) = 0; -#if __CORTEX_M == 0x04 +//#if __CORTEX_M == 0x04 volatile uint32_t dummy = *((volatile uint32_t *)((uint32_t)NRF_GPIOTE + event)); (void)dummy; -#endif +//#endif } event = (uint32_t)((uint32_t)event + 4); } } + +#endif // #ifdef _REMVOED_CODE_ diff --git a/cores/nRF5/WInterrupts.h b/cores/nRF5/WInterrupts.h index 5d2b24a0..237c5279 100644 --- a/cores/nRF5/WInterrupts.h +++ b/cores/nRF5/WInterrupts.h @@ -15,6 +15,8 @@ License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define _REMOVED_CODE_ +#ifdef _REMOVED_CODE_ #ifndef _WIRING_INTERRUPTS_ #define _WIRING_INTERRUPTS_ @@ -52,3 +54,5 @@ void detachInterrupt(uint32_t pin); #endif #endif + +#endif // #ifdef _REMVOED_CODE_ diff --git a/cores/nRF5/WVariant.h b/cores/nRF5/WVariant.h index 9d9a7586..c09a17bd 100644 --- a/cores/nRF5/WVariant.h +++ b/cores/nRF5/WVariant.h @@ -19,6 +19,7 @@ #pragma once #include +#include #ifdef __cplusplus extern "C" { diff --git a/cores/nRF5/avr/pgmspace.h b/cores/nRF5/avr/pgmspace.h index c1fd7910..68ff4971 100644 --- a/cores/nRF5/avr/pgmspace.h +++ b/cores/nRF5/avr/pgmspace.h @@ -102,7 +102,7 @@ typedef const void* uint_farptr_t; #define pgm_read_word(addr) (*(const unsigned short *)(addr)) #define pgm_read_dword(addr) (*(const unsigned long *)(addr)) #define pgm_read_float(addr) (*(const float *)(addr)) -#define pgm_read_ptr(addr) (*(const void* *)(addr)) +#define pgm_read_ptr(addr) (*(const void *)(addr)) #define pgm_read_byte_near(addr) pgm_read_byte(addr) #define pgm_read_word_near(addr) pgm_read_word(addr) diff --git a/cores/nRF5/bleConstants.h b/cores/nRF5/bleConstants.h new file mode 100644 index 00000000..8ac0c7ba --- /dev/null +++ b/cores/nRF5/bleConstants.h @@ -0,0 +1,51 @@ +// bleConstants.h + +#ifndef BLE_CONSTANTS_H +#define BLE_CONSTANTS_H + +#include +/** NOTE +Connection Interval Min ≥ 7.5 ms (multiples of 1.25 ms) + suggested min 15ms and then in multiples of 15ms +Connection Interval Max < 4sec + suggested Interval Min + 15 ms ≤ Interval Max (Interval Max == 15 ms is allowed) +Interval Max * (Slave Latency + 1) ≤ 2 seconds +Interval Max * (Slave Latency + 1) * 3 < connSupervisionTimeout +Slave Latency ≤ 30 +2 seconds ≤ connSupervisionTimeout ≤ 6 seconds +****/ + +// default min/max connection interval in ms +// internally converted to multiples of 1.25ms i.e. 100ms => converted internally to 80 +// use setConnectionInterval( , ) to override these settings +const unsigned short DEFAULT_MIN_CONNECTION_INTERVAL_ms = 100; +const unsigned short DEFAULT_MAX_CONNECTION_INTERVAL_ms = 150; + +// default connection slave latency +// use setSlaveLatency() to override. Non-zero lets device skip responding to connection events if no data to send +// must be in the range +// 0 to ((connectionSupervisionTimeout / connectionInterval) 1). +// i.e. must respond within supervision timeout even if no data +const unsigned short DEFAULT_SLAVE_LATENCY = 0; // must respond to every connection event + +// Connection Supervision Timeout in ms +// internally converted to multiples of 10ms i.e. 4000ms => converted internally to 400 +// must be in the range 100ms to 32000ms (32sec) +// no setter for this value, edit default if you need to +const unsigned short DEFAULT_CONNECTION_SUPERVISION_TIMEOUT_ms = 4000; + +// for nRF52 tx power +// -40, -30, -20, -16, -12, -8, -4, 0, 4 +// use setTxPower( ) to override this setting +const uint8_t DEFAULT_BLE_TX_POWER = 4; + +// advertising in ms +// internally converted to multiples of 0.625ms i.e. 100ms => converted internally to 160 +// use setAdvertisingInterval( ) to override this in the range 20ms to 10240ms (10.24sec) +const unsigned short DEFAULT_ADVERTISING_INTERVAL_ms = 500; + +// default connectable setting +// use setConnectable( ) to override this +const bool DEFAULT_CONNECTABLE = true; + +#endif // #ifndef BLE_CONSTANTS_H diff --git a/cores/nRF5/delay.c b/cores/nRF5/delay.c index c2b1f4e6..eb10dd5b 100644 --- a/cores/nRF5/delay.c +++ b/cores/nRF5/delay.c @@ -27,7 +27,7 @@ extern "C" { static volatile uint32_t overflows = 0; -uint32_t millis( void ) +/*uint32_t millis( void ) { uint64_t ticks = (uint64_t)((uint64_t)overflows << (uint64_t)24) | (uint64_t)(NRF_RTC1->COUNTER); @@ -66,7 +66,7 @@ void RTC1_IRQHandler(void) #endif overflows = (overflows + 1) & 0xff; -} +}*/ #ifdef __cplusplus } diff --git a/cores/nRF5/iBeacon.cpp b/cores/nRF5/iBeacon.cpp new file mode 100644 index 00000000..d1f9c22d --- /dev/null +++ b/cores/nRF5/iBeacon.cpp @@ -0,0 +1,45 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + +#include "iBeacon.h" + +iBeacon::iBeacon() : + BLEPeripheral() +{ + this->setConnectable(false); +} + +void iBeacon::begin(const char* uuidString, unsigned short major, unsigned short minor, char measuredPower) { + BLEUuid uuid(uuidString); + int i = 0; + + // 0x004c = Apple, see https://www.bluetooth.org/en-us/specification/assigned-numbers/company-identifiers + this->_manufacturerData[i++] = 0x4c; // Apple Company Identifier LE (16 bit) + this->_manufacturerData[i++] = 0x00; + + // See "Beacon type" in "Building Applications with IBeacon". + this->_manufacturerData[i++] = 0x02; + this->_manufacturerData[i++] = uuid.length() + 5; + + for (int j = (uuid.length() - 1); j >= 0; j--) { + this->_manufacturerData[i++] = uuid.data()[j]; + } + + this->_manufacturerData[i++] = major >> 8; + this->_manufacturerData[i++] = major; + this->_manufacturerData[i++] = minor >> 8; + this->_manufacturerData[i++] = minor; + this->_manufacturerData[i++] = measuredPower; + + this->setManufacturerData(this->_manufacturerData, i); + + BLEPeripheral::begin(); +} + +void iBeacon::loop() { + this->poll(); +} + +#endif diff --git a/cores/nRF5/iBeacon.h b/cores/nRF5/iBeacon.h new file mode 100644 index 00000000..06a317b2 --- /dev/null +++ b/cores/nRF5/iBeacon.h @@ -0,0 +1,26 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _I_BEACON_H_ +#define _I_BEACON_H_ + +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + +#include "BLEPeripheral.h" +#include "BLEUuid.h" + +class iBeacon : public BLEPeripheral +{ + public: + iBeacon(); + + void begin(const char* uuidString, unsigned short major, unsigned short minor, char measuredPower); + void loop(); + + private: + unsigned char _manufacturerData[MAX_UUID_LENGTH + 9]; // 4 bytes of header and 5 bytes of trailer. +}; + +#endif + +#endif diff --git a/cores/nRF5/lp_ADC.c b/cores/nRF5/lp_ADC.c new file mode 100644 index 00000000..67bd0d19 --- /dev/null +++ b/cores/nRF5/lp_ADC.c @@ -0,0 +1,360 @@ +// lp_ADC.c +#include "lp_ADC.h" +#include "WVariant.h" +#include "limits.h" +#include "utility\app_util_platform.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NRF52_SERIES + +#include "nrf_error.h" + +extern int ADC_readResolution; // set in wiring_analog_nRF52.c by analogReadResolution( ) default 10bit + +// these constants set the ADC parameters +// see the nRF52832_PS_v1.3-1117956.pdf for the details + +// set in wiring_analog_nRF52.c by call to analogReference(... ) +// choices are AR_DEFAULT or AR_INTERNAL: => 0.6V gain 1/5 for 3V -> 0.6V fullscale +// and AR_VDD4 => VDD / 4 and gain 1/5 for VDD -> fulscale + +extern uint32_t saadcReference; // default SAADC_CH_CONFIG_REFSEL_Internal; // internal 0.6V ref +extern uint32_t saadcGain; // default SAADC_CH_CONFIG_GAIN_Gain1_5; // gain 1/5 => 3V -> 0.6V fullscale + +extern unsigned long adc_settling_time; // set in wiring_analog_nRF52.c +// default SAADC_CH_CONFIG_TACQ_10us; // < 10 us good for <100K source resisance. +// i.e. a less than 200K + less than 200K voltage divider connected to the ADC pin +// The calculated source resistance == the value of two resistors if they were connected in parallel. + +/** choice depends on the source resistance and are + SAADC_CH_CONFIG_TACQ_3us (0UL) < 3 us for < 10K + SAADC_CH_CONFIG_TACQ_5us (1UL) < 5 us for < 40K + SAADC_CH_CONFIG_TACQ_10us (2UL) < 10 us for <100K + SAADC_CH_CONFIG_TACQ_15us (3UL) < 15 us for <200K + SAADC_CH_CONFIG_TACQ_20us (4UL) < 20 us for <400K + SAADC_CH_CONFIG_TACQ_40us (5UL) < 40 us for <800K +*/ + +static uint32_t resolution; +static bool calibrateOffsetFlag = false; // set by lp_ADC_calibrate(); +static volatile bool calibrateOffset = false; // picked up from calibrateOffsetFlag, when lp_ADC_start( ..) runs +static uint32_t saadcResolution; +static uint32_t adcPin = 0; // input arg to lp_ADC_start( +static void (*handler_callback)(int) = NULL; + +#define LP_ADC_CONFIG_IRQ_PRIORITY 3 + +static inline uint32_t mapResolution( uint32_t value, uint32_t from, uint32_t to ) +{ + if ( from == to ) + { + return value ; + } + + if ( from > to ) + { + return value >> (from - to) ; + } + else + { + return value << (to - from) ; + } +} + +/** + @brief Function for enabling interrupts from lp_ADC. + + @param[in] lp_ADC_int_mask Mask of interrupts to be enabled. + +*/ +__STATIC_INLINE void nrf_lp_ADC_int_enable(uint32_t lp_ADC_int_mask) { + NRF_SAADC->INTENSET = lp_ADC_int_mask; +} + +__STATIC_INLINE void nrf_lp_ADC_int_clear(uint32_t lp_ADC_int_mask) { + NRF_SAADC->INTENCLR = lp_ADC_int_mask; +} + +// clear all interrupts +__STATIC_INLINE void nrf_lp_ADC_int_clear_all() { + NRF_SAADC->INTEN = 0; +} + +/** + @brief Function for retrieving the state of a specific interrupt. + + @param[in] int_mask Interrupt. + + @retval true If the interrupt is enabled. + @retval false If the interrupt is not enabled. +*/ +__STATIC_INLINE bool nrf_lp_ADC_int_enable_check(uint32_t lp_ADC_int_mask) { + return (NRF_SAADC->INTENSET & lp_ADC_int_mask); +} + +static volatile uint32_t adcResult = UINT32_MAX; + +static volatile bool adcStarted = false; // set true when started and false when result picked up +static int16_t value; // adc result before scaling + + +/** + TASKS_START 0x000 Start the ADC and prepare the result buffer in RAM + TASKS_SAMPLE 0x004 Take one ADC sample, if scan is enabled all channels are sampled + TASKS_STOP 0x008 Stop the ADC and terminate any on-going conversion + TASKS_CALIBRATEOFFSET0x00C Starts offset auto-calibration + EVENTS_STARTED 0x100 The ADC has started + EVENTS_END 0x104 The ADC has filled up the Result buffer + EVENTS_DONE 0x108 A conversion task has been completed. Depending on the mode, multiple conversions might be + needed for a result to be transferred to RAM. + EVENTS_RESULTDONE 0x10C A result is ready to get transferred to RAM. + EVENTS_CALIBRATEDONE0x110 Calibration is complete + EVENTS_STOPPED 0x114 The ADC has stopped + EVENTS_CH[0].LIMITH 0x118 Last results is equal or above CH[0] +**/ + +// this is the interrupt handler for the ADC module +// Must clear the interrupt being handled or will just call this again, and again. +void SAADC_IRQHandler(void) { // handle ADC interrupt + // calibrate + if (nrf_lp_ADC_int_enable_check(SAADC_INTENSET_CALIBRATEDONE_Msk)) { + //nrf_lp_ADC_int_clear(SAADC_INTENSET_CALIBRATEDONE_Msk); + nrf_lp_ADC_int_clear_all(); + NRF_SAADC->EVENTS_CALIBRATEDONE = 0x00UL; + // finished calibration now start sample task + nrf_lp_ADC_int_enable(SAADC_INTENSET_STOPPED_Msk); + NRF_SAADC->TASKS_STOP = 0x01UL; + + // start + } else if (nrf_lp_ADC_int_enable_check(SAADC_INTENSET_STARTED_Msk)) { + //nrf_lp_ADC_int_clear(SAADC_INTENSET_STARTED_Msk); + nrf_lp_ADC_int_clear_all(); + NRF_SAADC->EVENTS_STARTED = 0x00UL; + nrf_lp_ADC_int_enable(SAADC_INTENSET_END_Msk); + NRF_SAADC->TASKS_SAMPLE = 0x01UL; + + // sample + } else if (nrf_lp_ADC_int_enable_check(SAADC_INTENSET_END_Msk)) { + // nrf_lp_ADC_int_clear(SAADC_INTENSET_END_Msk); + nrf_lp_ADC_int_clear_all(); + NRF_SAADC->EVENTS_END = 0x00UL; + nrf_lp_ADC_int_enable(SAADC_INTENSET_STOPPED_Msk); + NRF_SAADC->TASKS_STOP = 0x01UL; + + // stop + } else if (nrf_lp_ADC_int_enable_check(SAADC_INTENSET_STOPPED_Msk)) { + //nrf_lp_ADC_int_clear(SAADC_INTENSET_STOPPED_Msk); + nrf_lp_ADC_int_clear_all(); + NRF_SAADC->EVENTS_STOPPED = 0x00UL; + if (calibrateOffset) { + value = 0; + } else { // not calibrate so return result + // pick up result + if (value < 0) { + value = 0; + } + } + NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos); + uint32_t result = mapResolution(value, resolution, ADC_readResolution); + CRITICAL_REGION_ENTER(); + adcResult = result; + CRITICAL_REGION_EXIT(); + } else { // unexpected ADC interrupt, just clear all + nrf_lp_ADC_int_clear_all(); + } +} + +// this is called after sleep wakes up +// BEFORE any other callback +// this is called on the loop() thread so no need to use volatiles or synchronization +void postADCResult() { + // critical to check result + uint32_t adcPostResult = UINT32_MAX; + CRITICAL_REGION_ENTER(); + if (adcResult != UINT32_MAX) { + adcPostResult = adcResult; + adcResult = UINT32_MAX; + adcStarted = false; + } + CRITICAL_REGION_EXIT(); + if ((adcPostResult != UINT32_MAX) && (handler_callback != NULL)) { + if (!calibrateOffset) { + // call callback + if (adcPostResult > INT_MAX) { + adcPostResult = INT_MAX; + } + handler_callback((int)adcPostResult); + } else { + // do the sample now + lp_ADC_start(adcPin, handler_callback); + } + } +} + + +// Uses internal reference and 1/5 gain for 0 to 3V range (max input must be less than VDD, the supply voltage) +// lp_ADC_start(A0, handler) +// You can use ADC and lp_compator at the same time BUT not on the same pin +// can use getChipTemperature() while lp_comparator is active +// this call starts the SAADC, samples the pin, saves the result and stops the SAADC to save the residual current +// the handler is call with the ADC count when the SAADC has stopped. +// NOTE ulPin is A0 to A7 mapped to chip pin from g_ADigitalPinMap +// for NanoV2 and Skylab NanoV2 replacement only A0 to A5 available + +/** + A0 = AIN5 = pin 4 + A1 = AIN6 = pin 5 + A2 = AIN7 = pin 6 + A3 = AIN5 = pin 7 + A4 = AIN6 = pin 28 + A5 = AIN7 = pin 29 + A6 = AIN6 = pin 30 + A7 = AIN7 = pin 31 +**/ + +// set calibrate flag to perform offset calibration, just once, before next sample +// need to call lp_ADC_start(..) after call lp_ADC_calibrate() +// only calibrates once on next lp_ADC_start(..) +// calibrate setting is cleared after next successful lp_ADC_start(..) +// NOTE: if lp_ADC_start(..) returns an error OR NRF_ERROR_BUSY +// the calibrate flag is not cleared. +void lp_ADC_calibrate() { + calibrateOffsetFlag = true; +} + +// handler_fun is the method called when ADC completes arg is the ADC count +// returns 0 if arguments OK, else error no. +// returns NRF_ERROR_BUSY if conversion already in progress. +uint32_t lp_ADC_start(uint32_t ulPin, void (*adc_handler_fun)(int) ) { + // flag = false; // testing only + handler_callback = adc_handler_fun; + adcPin = ulPin; + + // do checks first before starting + if (adc_handler_fun == NULL) { + return NRF_ERROR_INVALID_PARAM; + } + if (ulPin >= PINS_COUNT) { + return NRF_ERROR_INVALID_PARAM; + } + + uint32_t pin = SAADC_CH_PSELP_PSELP_NC; + + ulPin = g_ADigitalPinMap[ulPin]; + + switch ( ulPin ) { + case 2: + pin = SAADC_CH_PSELP_PSELP_AnalogInput0; + break; + + case 3: + pin = SAADC_CH_PSELP_PSELP_AnalogInput1; + break; + + case 4: + pin = SAADC_CH_PSELP_PSELP_AnalogInput2; + break; + + case 5: + pin = SAADC_CH_PSELP_PSELP_AnalogInput3; + break; + + case 28: + pin = SAADC_CH_PSELP_PSELP_AnalogInput4; + break; + + case 29: + pin = SAADC_CH_PSELP_PSELP_AnalogInput5; + break; + + case 30: + pin = SAADC_CH_PSELP_PSELP_AnalogInput6; + break; + + case 31: + pin = SAADC_CH_PSELP_PSELP_AnalogInput7; + break; + + default: + return NRF_ERROR_INVALID_PARAM; + } + + bool alreadyStarted = false; + CRITICAL_REGION_ENTER(); + if (adcStarted) { // started and not complete yet + alreadyStarted = true; + } else { + adcResult = UINT32_MAX; + adcStarted = true; + } + CRITICAL_REGION_EXIT(); + if (alreadyStarted) { + return NRF_ERROR_BUSY; // still running so ignore this start + } + + //_sasdc_handler = (pfod_sasdc_handler_fun)handler_fun; + uint32_t saadcResolution; + + + if (ADC_readResolution <= 8) { + resolution = 8; + saadcResolution = SAADC_RESOLUTION_VAL_8bit; + } else if (ADC_readResolution <= 10) { + resolution = 10; + saadcResolution = SAADC_RESOLUTION_VAL_10bit; + } else if (ADC_readResolution <= 12) { + resolution = 12; + saadcResolution = SAADC_RESOLUTION_VAL_12bit; + } else { + resolution = 14; + saadcResolution = SAADC_RESOLUTION_VAL_14bit; + } + + NRF_SAADC->RESOLUTION = saadcResolution; + + NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos); + for (int i = 0; i < 8; i++) { + NRF_SAADC->CH[i].PSELN = SAADC_CH_PSELP_PSELP_NC; + NRF_SAADC->CH[i].PSELP = SAADC_CH_PSELP_PSELP_NC; + } + NRF_SAADC->CH[0].CONFIG = ((SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESP_Pos) & SAADC_CH_CONFIG_RESP_Msk) + | ((SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) + | ((saadcGain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) + | ((saadcReference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk) + | ((adc_settling_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) + | ((SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk); + NRF_SAADC->CH[0].PSELN = pin; + NRF_SAADC->CH[0].PSELP = pin; + + + NRF_SAADC->RESULT.PTR = (uint32_t)&value; + NRF_SAADC->RESULT.MAXCNT = 1; // One sample + + nrf_drv_common_irq_enable(SAADC_IRQn, LP_ADC_CONFIG_IRQ_PRIORITY); + // this is called first for calibration and then to do the actual sample. + if (calibrateOffsetFlag) { // setting this flag starts calibration + if (!calibrateOffset) { // pickup calibrate setting and clear it. + calibrateOffset = true; // this discards any result and start actual sample after calibration finishes + calibrateOffsetFlag = false; + nrf_lp_ADC_int_enable(SAADC_INTENSET_CALIBRATEDONE_Msk); + NRF_SAADC->TASKS_CALIBRATEOFFSET = 0x01UL; + } else { // calibrateOffset set so have finished calibration normal ADC BUT lp_ADC_calibrate has been called since calibration started, so leave it set for next sample call + calibrateOffset = false; // this is the actual sample, result will be returned. + nrf_lp_ADC_int_enable(SAADC_INTENSET_STARTED_Msk); + NRF_SAADC->TASKS_START = 0x01UL; // will call SAADC_IRQHandler when started + } + } else { // calibrateOffsetFlag not set OR was cleared above when picked up AND NOT called since lp_ADC_start( ) called to start calibration + // so just a normal ADC sample perhaps after a calibration so clear calibrationOffset flag in any case + calibrateOffset = false; + nrf_lp_ADC_int_enable(SAADC_INTENSET_STARTED_Msk); + NRF_SAADC->TASKS_START = 0x01UL; // will call SAADC_IRQHandler when started + } + + return 0; // OK started +} +#ifdef __cplusplus +} +#endif diff --git a/cores/nRF5/lp_ADC.h b/cores/nRF5/lp_ADC.h new file mode 100644 index 00000000..ff67a959 --- /dev/null +++ b/cores/nRF5/lp_ADC.h @@ -0,0 +1,48 @@ +// lp_ADC.h +#ifndef LP_ADC_H +#define LP_ADC_H + +#include "utility/nrf_lpcomp.h" +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +// Uses internal reference and 1/5 gain for 0 to 3V range (max input must be less than VDD, the supply voltage) +// lp_ADC_start(A0, adc_handler) +// NOTE: the handler is called on the loop() thread so no need for volatiles or synchronization. +// +// You can use ADC and lp_compator at the same time BUT not on the same pin +// can use getChipTemperature() while lp_comparator is active +// this call starts the SAADC, samples the pin, saves the result and stops the SAADC to save the residual current +// the handler is call with the ADC count when the SAADC has stopped. +/** +A0 = AIN5 = pin 4 +A1 = AIN6 = pin 5 +A2 = AIN7 = pin 6 +A3 = AIN5 = pin 7 +A4 = AIN6 = pin 28 +A5 = AIN7 = pin 29 +A6 = AIN6 = pin 30 +A7 = AIN7 = pin 31 +**/ +// non-blocking ~42us (without lp_ADC_calibrate() called) +// non-blocking ~140us if lp_ADC_calibrate() called first. +uint32_t lp_ADC_start(uint32_t ulPin, void (*adc_handler_fun)(int) ); + +// Can call lp_ADC_calibrate() from loop() at any time and the next +// lp_ADC_start( .. ) will do an offset calibration first +// takes about ~140us (non-blocking) from lp_ADC_start(..) to value returned +// with no calibration takes ~45us (non-blocking) +void lp_ADC_calibrate(); + + +void postADCResult(); + +#ifdef __cplusplus +} +#endif + +#endif // LP_ADC_H diff --git a/cores/nRF5/lp_BLESerial.cpp b/cores/nRF5/lp_BLESerial.cpp new file mode 100644 index 00000000..9d24ffa8 --- /dev/null +++ b/cores/nRF5/lp_BLESerial.cpp @@ -0,0 +1,427 @@ +#include "lp_BLESerial.h" + +//#define DEBUG + +volatile size_t lp_BLESerial::rxHead = 0; +volatile size_t lp_BLESerial::rxTail = 0; + +volatile uint8_t lp_BLESerial::rxBuffer[BLE_RX_MAX_LENGTH]; +volatile bool lp_BLESerial::connected = false; + +// ========== lp_BLESerial methods + +// static method +void lp_BLESerial::bleWriteAfterDelay() { + ((lp_BLESerial*)(BLEPeripheral::pollInstance))->internalBleWriteAfterDelay(); +} + +void lp_BLESerial::internalBleWriteAfterDelay() { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("bleWriteAfterDelay at "); debugOut->print(millis()); debugOut->println(); + } +#endif + + BLEPeripheral::poll(); + + // send next 20bytes here and stop timer if buffer empty +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("bytesToBeSent() :"); debugOut->println(bytesToBeSent()+sendBlockLen); + debugOut->print("bytes to be resent :"); debugOut->println(sendBlockLen); + } +#endif + + if (!isConnected() || ((txHead == txTail) && (sendBlockLen == 0))) { // common cases + clearTxBuffer(); + return; // nothing to do + } + + bool setSuccess = false; + // else have something to send + if (sendBlockLen != 0) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("resend:"); + debugOut->write(sendBlock,sendBlockLen); + debugOut->println(); + } +#endif // DEBUG + // send the last failed block + setSuccess =_txCharacteristic.setValue(sendBlock, sendBlockLen); + if (setSuccess) { + sendBlockLen = 0; + } + } + if (sendBlockLen != 0) { + return; + } + // else + // send next 20 bytes + while ((txHead != txTail) && (sendBlockLen == 0)) { + size_t i = 0; // max to send is + while ((i < BLE_ATTRIBUTE_MAX_VALUE_LENGTH) && (txHead != txTail)) { + sendBlock[i] = (const uint8_t)(txBuffer[txTail]); + i++; + txTail = (txTail + 1) % txBufferSize; + } + sendBlockLen = i; +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("send:"); + debugOut->write(sendBlock,sendBlockLen); + debugOut->println(); + } +#endif // DEBUG + setSuccess = _txCharacteristic.setValue(sendBlock, sendBlockLen); + if (setSuccess) { + sendBlockLen = 0; + } + BLEPeripheral::poll(); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->println(); + } +#endif // DEBUG + if ((txHead == txTail) && (sendBlockLen == 0)) { + stopTimer(); + } + } +} + +void lp_BLESerial::setDebugStream(Print* out) { + debugOut = out; +} + +void lp_BLESerial::setName(const char* localName) { + setLocalName(localName); +} + +void lp_BLESerial::setLocalName(const char* localName) { + if (localName == NULL) { + BLEPeripheral::setLocalName("Nordic BLE UART"); + } else { + BLEPeripheral::setLocalName(localName); + } +} + +lp_BLESerial::lp_BLESerial(size_t _txBufferSize) : BLEPeripheral() { + init(_txBufferSize); +} + + +void lp_BLESerial::setConnectedHandler(void(*connectHandler)(BLECentral& central)) { + _connectHandler = connectHandler; +} +void lp_BLESerial::setDisconnectedHandler(void(*disconnectHandler)(BLECentral& central)){ + _disconnectHandler = disconnectHandler; +} + +void lp_BLESerial::init(size_t _txBufferSize ) { + _connectHandler = NULL; + _disconnectHandler = NULL; + sendBlockLen = 0; + setTxBuffer(_txBufferSize); + debugOut = NULL; + setSendDelay(10); // min connection interval is 7.5ms so 10 seems OK + setLocalName(NULL); // use default to start with + addAttribute(_uartService); + addAttribute(_uartNameDescriptor); + setAdvertisedServiceUuid(_uartService.uuid()); + addAttribute(_rxCharacteristic); + addAttribute(_rxNameDescriptor); + _rxCharacteristic.setEventHandler(BLEWritten, lp_BLESerial::receiveHandler); + setEventHandler(BLEConnected, lp_BLESerial::connectHandler); + setEventHandler(BLEDisconnected, lp_BLESerial::disconnectHandler); + addAttribute(_txCharacteristic); + addAttribute(_txNameDescriptor); + + clearTxBuffer(); +}; + +void lp_BLESerial::clearTxBuffer() { +/********* +#ifdef DEBUG + if (debugOut) { + debugOut->println("lp_BLESerial clearTxBuffer."); + } +#endif // DEBUG +*********/ + txHead = 0; + txTail = 0; + sendBlockLen = 0; + stopTimer(); +} + +uint32_t lp_BLESerial::startTimer() { + if (timerRunning) { + // already running + return 0; // no error + } + // else + uint32_t err_code; + // access the global C code method + err_code = lp_BLEBufferedSerial_timer.startTimer(sendDelay_ms, bleWriteAfterDelay); // timeout in mS +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->println(); + debugOut->print(" startTimer errorCode:"); debugOut->println(err_code); + } +#endif + if (err_code == 0) { + timerRunning = true; + } + return err_code; +} + +uint32_t lp_BLESerial::stopTimer() { + if (!timerRunning) { + // already stopped + return 0; // no error + } + // else + uint32_t err_code; + // access the global C code method + err_code = lp_BLEBufferedSerial_timer.stop(); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->println(); + debugOut->print("stopTimer errorCode:"); debugOut->println(err_code); + } +#endif + if (err_code == 0) { + timerRunning = false; + } + return err_code; +} + +void lp_BLESerial::setConnectionInterval(unsigned short minimumConnectionInterval_ms, unsigned short maximumConnectionInterval_ms) { + unsigned short minConInterval = BLE_GAP_CP_MIN_CONN_INTVL_MIN + (BLE_GAP_CP_MIN_CONN_INTVL_MIN >> 2) + 1; // in 1.25ms units => mS + unsigned short maxConInterval = BLE_GAP_CP_MAX_CONN_INTVL_MAX + (BLE_GAP_CP_MAX_CONN_INTVL_MAX >> 2); // in 1.25ms units => mS truncated down + +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print(" maxConInterval "); + debugOut->print(maxConInterval); + debugOut->print(" minConInterval "); + debugOut->print(minConInterval); + debugOut->println(); + } +#endif // DEBUG + + if (maximumConnectionInterval_ms > maxConInterval) { + maximumConnectionInterval_ms = maxConInterval; // 4sec max + } + if (maximumConnectionInterval_ms < minConInterval) { + maximumConnectionInterval_ms = minConInterval; // 7.5mS min + } + + if (minimumConnectionInterval_ms > maxConInterval) { + minimumConnectionInterval_ms = maxConInterval; // 4sec max + } + if (minimumConnectionInterval_ms < minConInterval) { + minimumConnectionInterval_ms = minConInterval; // 7.5mS min + } + + if (minimumConnectionInterval_ms > maximumConnectionInterval_ms) { + minimumConnectionInterval_ms = maximumConnectionInterval_ms; + } + +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print(" minimumConnectionInterval_ms "); + debugOut->print(minimumConnectionInterval_ms); + debugOut->print(" maximumConnectionInterval_ms "); + debugOut->print(maximumConnectionInterval_ms); + debugOut->println(); + } +#endif // DEBUG + + BLEPeripheral::setConnectionInterval(minimumConnectionInterval_ms, maximumConnectionInterval_ms); + //It is important to know that maximum number of packets per connection event is dependent on the BLE stack/chipsets and is limited + // to 4 packets per connection event with iOS, and 6 packets per connection event in Android. + // setSendDelay(10); try to send more every 10msec just return if not space +} + +void lp_BLESerial::setSendDelay(unsigned short msec) { + sendDelay_ms = msec; +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("setSendDelay to "); + debugOut->print(sendDelay_ms); + debugOut->println(" ms"); + } +#endif // DEBUG +} + +void lp_BLESerial::setTxBuffer(size_t _txBufferSize) { + txHead = 0; + txTail = 0; + + if ((txBuffer == NULL) && (_txBufferSize > defaultBufferSize)) { + txBufferSize = _txBufferSize; + txBuffer = (uint8_t*)malloc(_txBufferSize); + } + if (txBuffer == NULL) { + txBufferSize = defaultBufferSize; + txBuffer = defaultBuffer; + } +} + +// space in tx buffer +size_t lp_BLESerial::availableForWrite() { + return txBufferSize - bytesToBeSent(); +} + +bool lp_BLESerial::isConnected() { + return (connected && _txCharacteristic.subscribed() && BLEPeripheral::connected()); +} + +void lp_BLESerial::begin() { + BLEPeripheral::begin(); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->println(F("lp_BLESerial::begin()")); + } +#endif +} + +void lp_BLESerial::setAdvertisingTimeout(uint16_t secs) { + BLEPeripheral::setAdvertisingTimeout(secs); // just call the superclass method +} + +bool lp_BLESerial::setAdvertising(bool on) { + return BLEPeripheral::setAdvertising(on); +} + +void lp_BLESerial::close() { + connected = false; // stop writes + BLEPeripheral::disconnect(); +} + +bool lp_BLESerial::poll() { + return BLEPeripheral::poll(); +} + +size_t lp_BLESerial::write(const uint8_t* bytes, size_t len) { + for (size_t i = 0; i < len; i++) { + write(bytes[i]); + } + return len; // just assume it is all written +} + + +size_t lp_BLESerial::write(uint8_t c) { + BLEPeripheral::poll(); + if (!isConnected()) { + clearTxBuffer(); + return 0; + } + + size_t rtn = 1; + size_t i = (txHead + 1) % txBufferSize; + while(i==txTail) { + internalBleWriteAfterDelay(); + // just spin trying to write a packet + } + txBuffer[txHead] = c; + txHead = i; + +/*********** +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print((char)c); + } +#endif // DEBUG +**********/ + + startTimer(); + return rtn; +} + +size_t lp_BLESerial::bytesToBeSent() { + if (txTail <= txHead) { + return (txHead - txTail); + } // else + return (txHead + txBufferSize - txTail); +} + +int lp_BLESerial::read() { + if (rxTail == rxHead) { + return -1; + } + // note increment rxHead befor writing + // so need to increment rxTail befor reading + rxTail = (rxTail + 1) % sizeof(rxBuffer); + uint8_t b = rxBuffer[rxTail]; + return b; +} + +int lp_BLESerial::available() { + BLEPeripheral::poll(); + int rtn = ((rxHead + sizeof(rxBuffer)) - rxTail ) % sizeof(rxBuffer); + //#ifdef DEBUG + // if (debugOut != NULL) { + // debugOut->print("lp_BLESerial available():"); debugOut->println(rtn); + // } + //#endif // DEBUG + return rtn; +} + +void lp_BLESerial::flush() { + BLEPeripheral::poll(); +} + +int lp_BLESerial::peek() { + BLEPeripheral::poll(); + if (rxTail == rxHead) { + return -1; + } + size_t nextIdx = (rxTail + 1) % sizeof(rxBuffer); + uint8_t byte = rxBuffer[nextIdx]; + return byte; +} + +// called from lp_BLEPeripherial class +void lp_BLESerial::connectHandler(BLECentral& central) { + connected = true; + ((lp_BLESerial*)BLEPeripheral::pollInstance)->clearTxBuffer(); // clear anything not sent yet + if (((lp_BLESerial*)BLEPeripheral::pollInstance)->_connectHandler != NULL) { + ((lp_BLESerial*)BLEPeripheral::pollInstance)->_connectHandler(central); + } +} + +// called from lp_BLEPeripherial class +void lp_BLESerial::disconnectHandler(BLECentral& central) { + connected = false; + ((lp_BLESerial*)BLEPeripheral::pollInstance)->clearTxBuffer(); // clear anything not sent yet + if (((lp_BLESerial*)BLEPeripheral::pollInstance)->_disconnectHandler != NULL) { + ((lp_BLESerial*)BLEPeripheral::pollInstance)->_disconnectHandler(central); + } +} + +void lp_BLESerial::addReceiveBytes(const uint8_t* bytes, size_t len) { + // note increment rxHead before writing + // so need to increment rxTail before reading + for (size_t i = 0; i < len; i++) { + size_t nextIdx = (rxHead + 1) % sizeof(rxBuffer); + if (nextIdx == rxTail) { + // If the output buffer is full, just drop the char +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("buffer full drop received byte "); debugOut->print((char)bytes[i]); + } +#endif // DEBUG + return; + } + rxHead = nextIdx; + rxBuffer[rxHead] = bytes[i]; + } +} + +void lp_BLESerial::receiveHandler(BLECentral& central, BLECharacteristic& rxCharacteristic) { + size_t len = rxCharacteristic.valueLength(); + const unsigned char *data = rxCharacteristic.value(); + ((lp_BLESerial*)BLEPeripheral::pollInstance) -> addReceiveBytes((const uint8_t*)data, len); +} +//======================= end lp_BLESerial methods diff --git a/cores/nRF5/lp_BLESerial.h b/cores/nRF5/lp_BLESerial.h new file mode 100644 index 00000000..6c26d865 --- /dev/null +++ b/cores/nRF5/lp_BLESerial.h @@ -0,0 +1,125 @@ +#ifndef _BLE_SERIAL_H_ +#define _BLE_SERIAL_H_ + +#include +#include + +class lp_BLESerial : public BLEPeripheral, public Stream { + public: + lp_BLESerial(size_t txBufferSize = DEFAULT_SEND_BUFFER_SIZE); + void setLocalName(const char* localName); // max length 29 + void setName(const char* localName); // max length 29 same as setLocalName + void begin(); + bool poll(); + void setConnectedHandler(void(*disconnectHandler)(BLECentral& central)); + void setDisconnectedHandler(void(*disconnectHandler)(BLECentral& central)); + size_t write(uint8_t); + size_t write(const uint8_t*, size_t); + int read(); + int available(); + void flush(); + int peek(); + void close(); + bool isConnected(); + void setDebugStream(Print* out); + size_t bytesToBeSent(); // bytes in buffer to be sent + size_t availableForWrite(); // space in tx buffer + void clearTxBuffer(); + static void bleWriteAfterDelay(); + + /** setAdvertising + start(true) / stop(false) advertising. + calls to this are ignored if BLE is connected + Note: advertising automatically startes when connection lost. + just calls superclass, BLEPeripheral::setAdvertising(bool on); + included here for documentation purposes + @param: on, true to turn on, false to stop + @return: true if succeeds else false, already started,stopped or some other error + */ + bool setAdvertising(bool on); // NOTE: advertising is ALWAYS started on BLE disconnect + + /** setAdvertisingTimeout + How many secs to advertise after starting advertising + This timeout is not applied until next time advertising starts. + just calls superclass, BLEPeripheral::setAdvertisingTimeout(secs); + included here for documentation purposes + @param secs the number of secs to advertise before stopping advert. + */ + void setAdvertisingTimeout(uint16_t secs); + + + /** + setConnectionInterval min/max that this device peripherial will accept + see https://punchthrough.com/maximizing-ble-throughput-on-ios-and-android/ + If this method is not called the defaults are min 100ms max 150ms + Sets the min and max connection interval. Arguments are in ms, but internally handled as counts * 1.25ms + must be call BEFORE begin() is called, otherwise ignored + Sets sendDelay to match (maximumConnectionIntervalCounts * 1.25ms) + 1ms + Note: This assumes only one 20byte data packet per connection interval, which may be overly cautious. + Note this connection uses Notify so does not wait for acks so always at lease one packet per connection interval + NOTE: count is number of 1.25ms to delay between send blocks of BLE data + this number should be > maxConnection interval number so previous block is picked up prior to sending next one. + note: minimumConnectionInterval,maximumConnectionInterval are actually counts of 1.25ms each + i.e. 80 => 100mS timeInterval + @param: minimumConnectionInterval_ms minimum connection interval in msec + @param: maximumConnectionInterval_ms maximum connection interval in msec + */ + void setConnectionInterval(unsigned short minimumConnectionInterval_ms, unsigned short maximumConnectionInterval_ms); + + protected: + void internalBleWriteAfterDelay(); + Print* debugOut; + const char* _localName; + void init(size_t bufferSize ); + + private: + void setSendDelay(unsigned short msec); // default is 10msec + bool connectCalled; + bool timerRunning = false; + + void setTxBuffer(size_t txBufferSize); + size_t txBufferSize; + size_t txHead; + size_t txTail; + uint8_t* txBuffer; + static const size_t DEFAULT_SEND_BUFFER_SIZE = 1024; // Max data size pfodApp msg + static const size_t defaultBufferSize = 32; // > BLE msg size + uint8_t defaultBuffer[defaultBufferSize]; // if malloc fails + + unsigned long sendDelay_ms; + uint8_t sendBlock[BLE_ATTRIBUTE_MAX_VALUE_LENGTH]; + size_t sendBlockLen; + + uint32_t startTimer(); + uint32_t stopTimer(); + lp_timer lp_BLEBufferedSerial_timer; + + static const int BLE_RX_MAX_LENGTH = 256; + static volatile size_t rxHead; + static volatile size_t rxTail; + volatile static uint8_t rxBuffer[BLE_RX_MAX_LENGTH]; + volatile static bool connected; + + static void connectHandler(BLECentral& central); + static void disconnectHandler(BLECentral& central); + static void receiveHandler(BLECentral& central, BLECharacteristic& rxCharacteristic); + void addReceiveBytes(const uint8_t* bytes, size_t len); + void(*_connectHandler)(BLECentral& central); // extra handler to call on connect NULL if not set + void(*_disconnectHandler)(BLECentral& central); // extra handler to call on disconnect NULL if not set + + // ==== create Nordic UART service ========= + BLEService _uartService = BLEService("6E400001-B5A3-F393-E0A9-E50E24DCCA9E"); + BLEDescriptor _uartNameDescriptor = BLEDescriptor("2901", "UART"); + BLECharacteristic _rxCharacteristic = BLECharacteristic("6E400002-B5A3-F393-E0A9-E50E24DCCA9E", BLEWriteWithoutResponse, BLE_ATTRIBUTE_MAX_VALUE_LENGTH); // == TX on central (android app) + BLEDescriptor _rxNameDescriptor = BLEDescriptor("2901", "RX - Receive Data (Write)"); + BLECharacteristic _txCharacteristic = BLECharacteristic("6E400003-B5A3-F393-E0A9-E50E24DCCA9E", BLENotify, BLE_ATTRIBUTE_MAX_VALUE_LENGTH); // == RX on central (android app) + // tx is Notify so does not wait for ack from client (Android/IPhone) so can send multiple packets per connection, but limited to just one here by sendDelay + BLEDescriptor _txNameDescriptor = BLEDescriptor("2901", "TX - Transfer Data (Notify)"); + +}; + + +// =========== end lp_BLESerial definitions + + +#endif diff --git a/cores/nRF5/lp_comparator.c b/cores/nRF5/lp_comparator.c new file mode 100644 index 00000000..c7b6a007 --- /dev/null +++ b/cores/nRF5/lp_comparator.c @@ -0,0 +1,198 @@ +// lp_comparator.c + +#define NRF52_SERIES +// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority +// Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +#define LPCOMP_CONFIG_IRQ_PRIORITY 3 + +// LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#include "utility/nrf_lpcomp.h" +#include "utility/nrf_drv_lpcomp.h" +#include "lp_comparator.h" +#include "nrf_error.h" +#include "WVariant.h" + +static bool running = false; + +bool lp_comparator_isRunning() { + return running; +} + +//void cprint(const char* str); +//void cprintNum(const char* str, const uint32_t num); + +enum LPCOMP_REF lp_comp_ref; + +typedef void (*pfod_lpcomp_handler_fun)(int); +// in c++ file +static pfod_lpcomp_handler_fun _lpcomp_handler; // this has C++ linkage so just declare it in your sketch and pass as arg + +/** LPCOMP configuration. + typedef struct { + nrf_lpcomp_ref_t reference; // LPCOMP reference + nrf_lpcomp_detect_t detection; // LPCOMP detection type + nrf_lpcomp_hysteresis_t hyst; // LPCOMP hysteresis + } nrf_lpcomp_config_t; +**/ +/** + typedef enum { + NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, // Generate ANADETEC on crossing, both upwards and downwards crossing + NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, // Generate ANADETEC on upwards crossing only + NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down // Generate ANADETEC on downwards crossing only + } nrf_lpcomp_detect_t; +**/ + +void pfod_lpcom_schedule_event_handler(void* nullPtr, uint16_t isHigh) { + _lpcomp_handler((int)isHigh); +} + +void sampleAndSendEvent() { + NRF_LPCOMP->TASKS_SAMPLE = 1; + uint32_t result = nrf_lpcomp_result_get(); + uint8_t cmpResult = 0; + if (result != 0) { + cmpResult = 1; + } + app_sched_comp_event_put(cmpResult, pfod_lpcom_schedule_event_handler); +} + +/** + @brief LPCOMP event handler is called when LPCOMP detects voltage drop. + + This function is called from interrupt context so it is very important + to return quickly. Don't put busy loops or any other CPU intensive actions here. + It is also not allowed to call soft device functions from it (if LPCOMP IRQ + priority is set to APP_IRQ_PRIORITY_HIGH). +*/ +static void pfod_lpcomp_event_handler(nrf_lpcomp_event_t event) { + // NRF_LPCOMP_EVENT_READY or NRF_LPCOMP_EVENT_CROSS + sampleAndSendEvent(); +} + +// call this is you want to use the ADC +// you will need to start lpcomp again afterwards +void lp_comparator_stop() { + nrf_drv_lpcomp_uninit(); + running = false; +} + +/** + // comparator pins for nRF52832 + // INPUT0 P0_02 + // INPUT1 P0_03 + // INPUT2 P0_04 + // INPUT3 P0_05 + // INPUT4 P0_28 + // INPUT5 P0_29 + // INPUT6 P0_30 + // INPUT7 P0_31 + + uint32_t lp_comparator_start(uint32_t ulPin, lp_ref refVolts, void (*handler_fun)(int) ) + NOTE ulPin is specified as A0 to A7 mapped to chip pin from g_ADigitalPinMap[] in variants + for NanoV2 and Skylab NanoV2 replacement only A0 to A5 are available for lp_comparator + +****/ + +/******** + typedef struct { + nrf_lpcomp_config_t hal; // LPCOMP HAL configuration + nrf_lpcomp_input_t input; // Input to be monitored + uint8_t interrupt_priority; // LPCOMP interrupt priority + } nrf_drv_lpcomp_config_t; +**********/ + +// to used 1/2 VDD as ref +// lp_comparator_start(A0, REF_8_16Vdd, handler) +// used ADC MUX so cannot read ADC from another pin while using comparator +// call lp_comparator_stop first +// can use getChipTemperature() while lp_comparator is active +// NOTE ulPin is A0 to A7 mapped to chip pin from g_ADigitalPinMap +// for NanoV2 and Skylab NanoV2 replacement only A0 to A5 available +// NOTE: lp_comparator_start returns an error if already initialized and stops the current lp_comparator +// so check lp_comparator_isRunning() first if restarting comparator +uint32_t lp_comparator_start(uint32_t ulPin, lp_ref refVolts, void (*handler_fun)(int) ) { + + if (handler_fun == NULL) { + return NRF_ERROR_INVALID_PARAM; + } + if (ulPin >= PINS_COUNT) { + return NRF_ERROR_INVALID_PARAM; + } + + nrf_lpcomp_input_t input = NRF_LPCOMP_INPUT_0; + ulPin = g_ADigitalPinMap[ulPin]; // picked up from board variant.cpp + if (ulPin == 2) { + input = NRF_LPCOMP_INPUT_0; // Input 0 + } else if (ulPin == 3) { + input = NRF_LPCOMP_INPUT_1; // Input 1 + } else if (ulPin == 4 ) { + input = NRF_LPCOMP_INPUT_2; // Input 2 + } else if (ulPin == 5) { + input = NRF_LPCOMP_INPUT_3; // Input 3 + } else if (ulPin == 28) { + input = NRF_LPCOMP_INPUT_4; // Input 4 + } else if (ulPin == 29) { + input = NRF_LPCOMP_INPUT_5; // Input 5 + } else if (ulPin == 30) { + input = NRF_LPCOMP_INPUT_6; // Input 6 + } else if (ulPin == 31) { + input = NRF_LPCOMP_INPUT_7; // Input 7 + } else { + // invalid pin do not initialize + return NRF_ERROR_INVALID_PARAM; // invalid input arg + } + + _lpcomp_handler = (pfod_lpcomp_handler_fun)handler_fun; + nrf_lpcomp_ref_t triggerLevel = (nrf_lpcomp_ref_t)refVolts; + + + nrf_lpcomp_config_t config_trigger; + config_trigger.reference = triggerLevel; // default cross + config_trigger.detection = NRF_LPCOMP_DETECT_CROSS; // this will actually do up/down/ready + config_trigger.hyst = NRF_LPCOMP_HYST_50mV; + + nrf_drv_lpcomp_config_t config; + config.hal = config_trigger; + config.input = input; + config.interrupt_priority = LPCOMP_CONFIG_IRQ_PRIORITY; \ + + // initialize LPCOMP driver, from this point LPCOMP will be active and provided + // event handler will be executed when defined action is detected + // NOTE: nrf_drv_lpcomp_init has been modified to translate + // NRF_LPCOMP_DETECT_CROSS into + // LPCOMP_INTENSET_UP_Msk|LPCOMP_INTENSET_DOWN_Msk|LPCOMP_INTENSET_READY_Msk + // NOTE: nrf_drv_lpcomp_init returns an error if already initialized and stops the current lp_comparator + uint32_t err_code = nrf_drv_lpcomp_init(&config, pfod_lpcomp_event_handler); + + if (err_code == 0) { + nrf_drv_lpcomp_enable(); + running = true; + } else { + nrf_drv_lpcomp_uninit(); + running = false; + } + return err_code; +} diff --git a/cores/nRF5/lp_comparator.h b/cores/nRF5/lp_comparator.h new file mode 100644 index 00000000..7d86a14d --- /dev/null +++ b/cores/nRF5/lp_comparator.h @@ -0,0 +1,61 @@ +// lp_comparator.h +#ifndef LP_COMPARATOR_H +#define LP_COMPARATOR_H + +#include "utility/nrf_lpcomp.h" + +typedef enum { + DOWN, + UP +} pfod_lpcomp_event; + + +#ifdef __cplusplus +extern "C" { +#endif + + +enum lp_ref_enum { + REF_1_16Vdd = 8, + REF_2_16Vdd = 0, + REF_3_16Vdd = 9, + REF_4_16Vdd = 1, + REF_5_16Vdd = 10, + REF_6_16Vdd = 2, + REF_7_16Vdd = 11, + REF_8_16Vdd = 3, + REF_9_16Vdd = 12, + REF_10_16Vdd = 4, + REF_11_16Vdd = 13, + REF_12_16Vdd = 5, + REF_13_16Vdd = 14, + REF_14_16Vdd = 6, + REF_15_16Vdd = 15, + REF_ext_1 = 7, + REF_ext_2 = 65543 +}; + +typedef enum lp_ref_enum lp_ref; + +// returns true if lp_comparator is currently enabled +// retarting the lp_comparator while already running will just stop it. +bool lp_comparator_isRunning(); + +// to used 1/2 VDD as ref +// lp_comparator_start(A0, REF_8_16Vdd, handler) +// You can use ADC and lp_compator at the same time BUT not on the same pin +// can use getChipTemperature() while lp_comparator is active +// NOTE: lp_comparator_start returns an error if already initialized and stops the current lp_comparator +// so check lp_comparator_isRunning() first if restarting comparator +uint32_t lp_comparator_start(uint32_t ulPin, lp_ref refVolts, void (*handler_fun)(int) ); + +// call this is you want to use the ADC on the same pin +// you will need to start lpcomp again afterwards +void lp_comparator_stop(); + + +#ifdef __cplusplus +} +#endif + +#endif // LP_COMPARATOR_H diff --git a/cores/nRF5/lp_timer.cpp b/cores/nRF5/lp_timer.cpp new file mode 100644 index 00000000..38568da1 --- /dev/null +++ b/cores/nRF5/lp_timer.cpp @@ -0,0 +1,337 @@ + +#include "lp_timer_init.h" +// lp_timer_init.h has LP_TIMER_US define if defined +#include "utility/app_scheduler.h" +// include collection of nordic macros +#include "utility/nordic_common.h" +// include nrf error defines, only NRF_SUCCESS used here but you can use these to check error returns +// which in general are not checked in this code/library +#include "nrf_error.h" +// include scheduled timer, uses LF clock and RTC1 millis(), micros(), delay() moved to RTC2 delay() +// uses SWI0_IRQn and SWI0_IRQHandler +#include "utility/app_timer_appsh.h" +// included LF clock handling. Note: this shares an interrupt with nrf_drv_power but that is not used in these examples/library so no special handling needed +#include "utility/nrf_drv_clock.h" +#include "lp_timer.h" + +//For nRF52, the application must ensure calibration at least once +//every 8 seconds to ensure +/-500 ppm clock stability. The +//recommended configuration for ::NRF_CLOCK_LF_SRC_RC on nRF52 is +//rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at +//least once every 8 seconds and for temperature changes of 0.5 +//degrees Celsius every 4 seconds. See the Product Specification +//for the nRF52 device being used for more information. + +//typedef struct +//{ +// uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ +// uint8_t rc_ctiv; /**< Only for NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second +// units (nRF51: 1-64, nRF52: 1-32). +// @note To avoid excessive clock drift, 0.5 degrees Celsius is the +// maximum temperature change allowed in one calibration timer +// interval. The interval should be selected to ensure this. +// +// @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. */ +// uint8_t rc_temp_ctiv; /**< Only for NRF_CLOCK_LF_SRC_RC: How often (in number of calibration +// intervals) the RC oscillator shall be calibrated if the temperature +// hasn't changed. +// 0: Always calibrate even if the temperature hasn't changed. +// 1: Only calibrate if the temperature has changed (nRF51 only). +// 2-33: Check the temperature and only calibrate if it has changed, +// however calibration will take place every rc_temp_ctiv +// intervals in any case. +// +// @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. +// +// @note For nRF52, the application must ensure calibration at least once +// every 8 seconds to ensure +/-250ppm clock stability. The +// recommended configuration for NRF_CLOCK_LF_SRC_RC on nRF52 is +// rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at +// least once every 8 seconds and for temperature changes of 0.5 +// degrees Celsius every 4 seconds. See the Product Specification +// for the nRF52 device being used for more information.*/ +// uint8_t xtal_accuracy; /**< External crystal clock accuracy used in the LL to compute timing windows. +// +// @note For the NRF_CLOCK_LF_SRC_RC clock source this parameter is ignored. */ +//} nrf_clock_lf_cfg_t; + + +//#define DEBUG +void lp_timer::setDebugStream(Print* _debugOut) { + debugOut = _debugOut; +} + +#ifdef LP_TIMER_US +// in us +const static uint32_t LP_TIMER_SCALING = 1000; +#endif + +typedef struct { + uint32_t ticks_to_expire; /**< Number of ticks from previous timer interrupt to timer expiry. */ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + bool is_running; /**< True if timer is running, False otherwise. */ + app_timer_mode_t mode; /**< Timer mode. */ + app_timer_timeout_handler_t p_timeout_handler; /**< Pointer to function to be executed when the timer expires. */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ + void * next; /**< Pointer to the next node. */ +} timer_node_t; + + +extern "C" { + static void internalTimeoutHandler(lp_timer* timerPtr) { + if (timerPtr == NULL) { // should not happen + return; + } + if (timerPtr->_timeoutHandler != NULL) { + timerPtr->_timeoutHandler(); + } + } +} + +lp_timer::lp_timer() { + timer_data = {0}; + p_timer_data = &timer_data; + created = false; + debugOut = NULL; +} + +uint32_t lp_timer::init(void (*timeout_handler)(void), app_timer_mode_t mode) { + uint32_t err_code; + // Create timers + _timeoutHandler = timeout_handler; + err_code = app_timer_create(p_timer_data, mode, (app_timer_timeout_handler_t) internalTimeoutHandler); + repeating = (mode == APP_TIMER_MODE_REPEATED); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("init return:"); debugOut->println(err_code); + } +#endif + return err_code; +} + +bool lp_timer::isRepeating() { + if (!isRunning()) { + return false; + } else { + return repeating; + } +} + +bool lp_timer::isRunning() { + if (!created) { + return false; + } // else + timer_node_t* node = (timer_node_t*)(p_timer_data); + return node->is_running; +} + +uint32_t lp_timer::stop() { + if (!isRunning()) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("stop() not running return:"); debugOut->println(0); + } +#endif + return 0; // not running + } + uint32_t err_code; + err_code = app_timer_stop(p_timer_data); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("stop() return:"); debugOut->println(err_code); + } +#endif + return err_code; +} + +// if LP_TIMER_US defined in utility/lp_timer_speed.h.h +// this method returns ms +uint32_t lp_timer::getTimeout() { + if (!created) { + return 0; + } // else +#ifdef LP_TIMER_US + return timeout / LP_TIMER_SCALING; +#else + return timeout; +#endif +} + + +// if LP_TIMER_US defined in utility/lp_timer_speed.h.h +#ifdef LP_TIMER_US +uint32_t lp_timer::startDelay(uint32_t timeout_ms, void (*handler)(void)) { + if (timeout_ms > MAX_TIMEOUT) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("startDelay timeout:"); debugOut->print(timeout_ms); debugOut->println("ms"); + debugOut->print("startDelay timeout limited to "); debugOut->print(MAX_TIMEOUT); debugOut->println("ms"); + } +#endif + timeout_ms = MAX_TIMEOUT; + } + return start(timeout_ms * LP_TIMER_SCALING, handler , APP_TIMER_MODE_SINGLE_SHOT); +} + +uint32_t lp_timer::startTimer(uint32_t timeout_ms, void (*handler)(void)) { + if (timeout_ms > MAX_TIMEOUT) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("startTimer timeout:"); debugOut->print(timeout_ms); debugOut->println("ms"); + debugOut->print("startTimer timeout limited to "); debugOut->print(MAX_TIMEOUT); debugOut->println("ms"); + } +#endif + timeout_ms = MAX_TIMEOUT; + } + return start(timeout_ms * LP_TIMER_SCALING, handler , APP_TIMER_MODE_REPEATED); +} + +uint32_t lp_timer::startTimer_us(uint32_t timeout_us, void (*handler)(void)) { + if (timeout_us > MAX_TIMEOUT_US) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("startTimer_us timeout:"); debugOut->print(timeout_us); debugOut->println("us"); + debugOut->print("startTimer_us timeout limited to "); debugOut->print(MAX_TIMEOUT_US); debugOut->println("us"); + } +#endif + timeout_us = MAX_TIMEOUT_US; + } + return start(timeout_us, handler , APP_TIMER_MODE_REPEATED); +} + +uint32_t lp_timer::startDelay_us(uint32_t timeout_us, void (*handler)(void)) { + if (timeout_us > MAX_TIMEOUT_US) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("startDelay_us timeout:"); debugOut->print(timeout_us); debugOut->println("us"); + debugOut->print("startDelay_us timeout limited to "); debugOut->print(MAX_TIMEOUT_US); debugOut->println("us"); + } +#endif + timeout_us = MAX_TIMEOUT_US; + } + return start(timeout_us, handler , APP_TIMER_MODE_SINGLE_SHOT); +} + +uint32_t lp_timer::getTimeout_us() { + if (!created) { + return 0; + } // else + return timeout; +} + +#else +// previous version +uint32_t lp_timer::startTimer(uint32_t timeout_ms, void (*handler)(void)) { + return start(timeout_ms, handler , APP_TIMER_MODE_REPEATED); +} + +uint32_t lp_timer::startDelay(uint32_t timeout_ms, void (*handler)(void)) { + return start(timeout_ms, handler , APP_TIMER_MODE_SINGLE_SHOT); +} +#endif + +// if LP_TIMER_US defined in utility/lp_timer_speed.h.h +// this method takes us, else ms +// returns 0 if OK +uint32_t lp_timer::start(uint32_t timeout_in, void (*handler)(void), app_timer_mode_t mode) { + if (handler == NULL) { + return NRF_ERROR_INVALID_PARAM;// null handler + } + uint32_t err_code = 0; + if (created) { + if (isRunning()) { + err_code = NRF_ERROR_INVALID_STATE; +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() still running return:"); debugOut->println(err_code); + } +#endif + return err_code;// error still running + } else { + // stopped re-initialize +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() created re-init "); + } +#endif + err_code = init(handler, mode); + if (err_code != 0) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() init return: "); debugOut->println(err_code); + } +#endif + return err_code; + } + } + } else { + // not created yet +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() not yet created "); + } +#endif + err_code = init(handler, mode); + if (err_code != 0) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() init return: "); debugOut->println(err_code); + } +#endif + return err_code; + } + created = true; + } +#ifdef LP_TIMER_US + if (timeout_in > MAX_TIMEOUT_US) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer timeout:"); debugOut->print(timeout_in); debugOut->println("us"); + debugOut->print("lp_timer timeout limited to "); debugOut->print(MAX_TIMEOUT_US); debugOut->println("us"); + } +#endif + timeout_in = MAX_TIMEOUT_US; // limit to max RTC can handle + } +#else + if (timeout_in > MAX_TIMEOUT) { +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer timeout:"); debugOut->print(timeout_in); debugOut->println("ms"); + debugOut->print("lp_timer timeout limited to "); debugOut->print(MAX_TIMEOUT); debugOut->println("ms"); + } +#endif + timeout_in = MAX_TIMEOUT; // limit to max RTC can handle + } +#endif + + uint32_t ticks = APP_TIMER_TICKS(timeout_in, APP_TIMER_PRESCALER); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() timeout_in == "); debugOut->print(timeout_in); +#ifdef LP_TIMER_US + debugOut->println("us"); +#else + debugOut->println("ms"); +#endif + debugOut->print("lp_timer.start() ticks == "); debugOut->println(ticks); + } +#endif + if (ticks < APP_TIMER_MIN_TIMEOUT_TICKS) { + ticks = APP_TIMER_MIN_TIMEOUT_TICKS; +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->println("lp_timer.start() ticks < 5 set to 5 ticks"); + } +#endif + } + timeout = timeout_in; + err_code = app_timer_start(p_timer_data, ticks, this); +#ifdef DEBUG + if (debugOut != NULL) { + debugOut->print("lp_timer.start() return:"); debugOut->println(err_code); + } +#endif + return err_code; +} diff --git a/cores/nRF5/lp_timer.h b/cores/nRF5/lp_timer.h new file mode 100644 index 00000000..ade72a9a --- /dev/null +++ b/cores/nRF5/lp_timer.h @@ -0,0 +1,72 @@ +#ifndef LP_TIMER_H +#define LP_TIMER_H +//lp_timer.h + +// 0.7.11 Rev 11 25th May 2023, added LP_TIMER_US for us timings +// LP_TIMER_US is defined in utility/lp_timer_speed.h.h +// with LP_TIMER_US defined (the default), the maximum timeout is reduced from 4069sec to 511sec +// and startTimer_us, startDelay_us and getTimeout_us methods are available. +// use them in preference to startTimer, startDelay and getTimeout which include ms to us multipliers and dividers. +// To revert to the previous lp_timer code with the longer maximum timeout +// comment out the #define LP_TIMER_US in utility/lp_timer_speed.h.h + +#include + +#include "utility/app_timer.h" +#include "utility/app_scheduler.h" +#include "Print.h" +#include "utility/lp_timer_speed.h" + + +class lp_timer { + public: + lp_timer(); + // if LP_TIMER_US is defined then timeout is in us in multiples of 30.5us, maximum timer is 511sec (511000000 us) + // min is 5 ticks => 152.5us + // else timeout is in ms in multiples of 244us, i.e. 1ms => 41 ticks of 244us each =>10.11ms, maximum timer is 4095sec (4095000 ms) + // min is 5 ticks => 1.222ms + // NOTE: if the timeout (rounded) is less than 5 RTC timer ticks the delay is set to 5 tick1s. + uint32_t startTimer(uint32_t timeout_ms, void (*handler)(void)); // if LP_TIMER_US defined this method has a ms to us multiplier startTimer_us(..) instead + uint32_t startDelay(uint32_t timeout_ms, void (*handler)(void)); // if LP_TIMER_US defined this method has a ms to us multiplier startDelay_us(..) instead + uint32_t getTimeout(); // if LP_TIMER_US defined this method has a us to ms divider use getTimeout_us(..) instead + +#ifdef LP_TIMER_US + uint32_t startTimer_us(uint32_t timeout_us, void (*handler)(void)); + uint32_t startDelay_us(uint32_t timeout_us, void (*handler)(void)); + uint32_t getTimeout_us(); +#endif + + void setDebugStream(Print* debugOut); + bool isRunning(); + bool isRepeating(); // true if running and repeating else false if stopped OR single shot + uint32_t stop(); +#ifdef LP_TIMER_US + // in us + const static uint32_t MAX_TIMEOUT = 511000; + const static uint32_t MAX_TIMEOUT_US = 511000000; + // minimum timeout 156us if argument <156 +#else + // in ms + const static uint32_t MAX_TIMEOUT = 4095000; + // minimum timeout 1220us (1.22ms) if argument <2 +#endif + void (*_timeoutHandler)(void); + + protected: + Print* debugOut; + // options for mode are defined in utility/app_timer.h + // APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ + // APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ + uint32_t start(uint32_t timeout, void (*handler)(void), app_timer_mode_t mode); + + private: + uint32_t init(void (*timeout_handler)(void) , app_timer_mode_t mode); + bool repeating; + bool created; + uint32_t timeout; + app_timer_t timer_data; + app_timer_t* p_timer_data; + +}; + +#endif // #ifndef LP_TIMER_H diff --git a/cores/nRF5/lp_timer_init.c b/cores/nRF5/lp_timer_init.c new file mode 100644 index 00000000..b8069290 --- /dev/null +++ b/cores/nRF5/lp_timer_init.c @@ -0,0 +1,104 @@ + +#include +#include + +#include "lp_timer_init.h" +#include "lp_ADC.h" + +void cprint(const char* str); +void cprintNum(const char* str, const uint32_t num); + + +/***** +// use this code in you sketch for debugging C code files +extern "C" void cprint(const char* str) { +#ifdef DEBUG + Serial.println(str); +#else + // nothing here +#endif +} + +extern "C" void cprintNum(const char* str, uint32_t num) { +#ifdef DEBUG + Serial.print(str); + Serial.print(' '); + Serial.println(num); +#else + // nothing here +#endif +} + +***********/ + +// note these methods have "C" code calling conventions +void clearFPU_IRQ(); +void app_sched_execute(void); +void app_sched_comp_execute(void); + +void BLEPeripheralInstancePoll(); + +// see https://devzone.nordicsemi.com/f/nordic-q-a/12433/fpu-divide-by-0-and-high-current-consumption +// call this is using floating point processor to clear any exceptions that may be raised +void clearFPU_IRQ() { + // may not be needed if not using Floating Point Processor + // Set bit 7 and bits 4..0 in the mask to one (0x ...00 1001 1111) +#define FPU_EXCEPTION_MASK 0x0000009F + //https://devzone.nordicsemi.com/f/nordic-q-a/13670/solved-nrf52-sd_app_evt_wait-will-not-go-to-sleep + // The FPU will generate an exception when dividing by 0 due to overflow/underflow. + // This exception will trigger the FPU interrupt. + // If the interrupt is not cleared/handled the CPU will not be able to go to sleep. + + /* Clear exceptions and PendingIRQ from the FPU unit */ + __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); + (void) __get_FPSCR(); // cortexM4 i.e. nrf52832 needs read after write to commit of change + NVIC_ClearPendingIRQ(FPU_IRQn); //this fixes low power as the stuck IRQ is cleared +} + +void sleep() { + waitForTrigger(); + processTrigger(); +} + +void waitForTrigger() { + clearFPU_IRQ(); // clear any FPU exceptions your loop code (or other code) generated + sd_app_evt_wait(); // sleep here waiting for next event/interrupt + // do this now so that we will detect any interrupt generated while we are processing the ble events and timing events + NVIC_ClearPendingIRQ(SD_EVT_IRQn); //this fixes low power as the stuck IRQ is cleared +} + +void processTrigger() { + postADCResult(); + BLEPeripheralInstancePoll(); // handle BLE msgs + app_sched_comp_execute(); // then handle comparator events first max 4 events + app_sched_execute(); // then handle queued events, e.g. timers +} + +// Function returns true if called from main context (CPU in thread +// mode), and returns false if called from an interrupt context. +bool is_main_context ( void ) { + static const uint8_t ISR_NUMBER_THREAD_MODE = 0; + uint8_t isr_number = __get_IPSR(); + if ((isr_number ) == ISR_NUMBER_THREAD_MODE) { + return true; + } else { + return false; + } +} + + +// setup the nrf52 SDK timer and scheduler +// uses defines APP_TIMER_PRESCALER , APP_TIMER_OP_QUEUE_SIZE +// and SCHED_MAX_EVENT_DATA_SIZE, SCHED_MAX_EVENT_DATA_SIZE, SCHED_QUEUE_SIZE +// COMP_QUEUE_SIZE must be < SCHED_QUEUE_SIZE +// from lp_timer_init.h header +void lp_timer_init() { + // this version on INIT creates two queues in one array to seperate comparator triggers from + // overloading other triggers. + APP_SCHED_COMP_INIT(SCHED_MAX_EVENT_DATA_SIZE, SCHED_QUEUE_SIZE, SCHED_COMP_QUEUE_SIZE); + // Initialize the application timer module. + APP_TIMER_APPSH_INIT(APP_TIMER_PRESCALER, APP_TIMER_OP_QUEUE_SIZE, true); + // wiring.c init() starts RTC2 + // init() (in wiring.c) called from main() before calling lp_timer.init +} + diff --git a/cores/nRF5/lp_timer_init.h b/cores/nRF5/lp_timer_init.h new file mode 100644 index 00000000..b18f9749 --- /dev/null +++ b/cores/nRF5/lp_timer_init.h @@ -0,0 +1,76 @@ +#ifndef LP_TIMER_INIT_H +#define LP_TIMER_INIT_H + +#include "utility/lp_timer_speed.h" + +// General application timer settings. +// see utility/lp_timer_speed.h for LP_TIME_US define +#ifdef LP_TIMER_US + // for APP_TIMER_PRESCALER 0 micros increment is 30.51us max timer is 512sec + // min lp_timer time is 31us +#define APP_TIMER_PRESCALER 0 + +#else // not LP_TIMER_US +// Value of the RTC1 PRESCALER register. 7 => 4096Hz counter for millis and lp_timer +// max timer is 4096sec +// Min lp_timer time is 1ms +// micros increment in intervals of 244us +#define APP_TIMER_PRESCALER 7 +#endif + +// Size of timer operation queues. +#define APP_TIMER_OP_QUEUE_SIZE 20 + +// Scheduler settings +//#define SCHED_MAX_EVENT_DATA_SIZE sizeof(uint32_t) +// allow for both scheduled timer event and your own scheduled events +#define SCHED_MAX_EVENT_DATA_SIZE MAX(APP_TIMER_SCHED_EVT_SIZE, sizeof(uint32_t)) +#define SCHED_QUEUE_SIZE 8 +#define SCHED_COMP_QUEUE_SIZE 4 +// queue goes from 0 to 8 for normal sched and 9 to 13 for comp, +// loose one index to detect empty queue (start == end) + +// uncomment this in utility/app_schedule.h to enable SCHEDULER TRIGGER QUEUE profiler +//#define SCHEDULER_PROFILER +// then call uint16_t app_sched_queue_utilization_get() to see the max queue size, excluding lp_comparator + +#include "utility/app_scheduler.h" + +// include collection of nordic macros +#include "utility/nordic_common.h" + +// include nrf error defines, only NRF_SUCCESS used here but you can use these to check error returns +// which in general are not checked in this code/library +#include "nrf_error.h" + +// include scheduled timer, uses LF clock and RTC1 millis(), micros(), delay() also use RTC1 +// uses SWI0_IRQn and SWI0_IRQHandler +#include "utility/app_timer_appsh.h" + +// included LF clock handling. Note: this shares an interrupt with nrf_drv_power but that is not used in these examples/library so no special handling needed +#include "utility/nrf_drv_clock.h" + + +#ifdef __cplusplus +extern "C" { +#endif + + +// setup the nrf52 SDK timer and scheduler +// uses defines APP_TIMER_PRESCALER , APP_TIMER_OP_QUEUE_SIZE +// and SCHED_MAX_EVENT_DATA_SIZE, SCHED_MAX_EVENT_DATA_SIZE, SCHED_QUEUE_SIZE +// from lp_timer_init.h header +void lp_timer_init(); + +// starts the softdevice and LF clock +void BLEPeripheralStartSoftDevice(); + +// Function returns true if called from main context (CPU in thread +// mode), and returns false if called from an interrupt context. +bool is_main_context ( void ); + +#ifdef __cplusplus +} +#endif + +#endif // #define LP_TIMER_INIT_H diff --git a/cores/nRF5/main.cpp b/cores/nRF5/main.cpp index 2a5247a3..13054a84 100644 --- a/cores/nRF5/main.cpp +++ b/cores/nRF5/main.cpp @@ -16,21 +16,30 @@ #define ARDUINO_MAIN #include "Arduino.h" +#include "lp_timer_init.h" + // Weak empty variant initialization function. // May be redefined by variant files. void initVariant() __attribute__((weak)); void initVariant() { } + /* * \brief Main entry point of Arduino application */ int main( void ) { - init(); + init(); // in wiring.c + delayMicroseconds(100); initVariant(); + delayMicroseconds(100); + + BLEPeripheralStartSoftDevice(); + delayMicroseconds(100); - delay(1); + lp_timer_init(); + delayMicroseconds(100); setup(); diff --git a/cores/nRF5/nRF51822.cpp b/cores/nRF5/nRF51822.cpp new file mode 100644 index 00000000..3428ce80 --- /dev/null +++ b/cores/nRF5/nRF51822.cpp @@ -0,0 +1,1661 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#include "bleConstants.h" +#define NRF5 +#define NRF52 +#if defined(NRF51) || defined(NRF52) || defined(__RFduino__) + +#ifdef __RFduino__ + #include + #include + #include +#elif defined(NRF5) || defined(NRF51_S130) + #include + #include + #include +#elif defined(NRF52) && defined(S132) // ARDUINO_RBL_nRF52832 + #ifndef ARDUINO_RBL_nRF52832 + #define ARDUINO_RBL_nRF52832 + #endif + + #include + #include + #include +#else + #include + #include + #include +#endif + +#if defined(NRF5) || defined(NRF51_S130) || defined(ARDUINO_RBL_nRF52832) +uint32_t sd_ble_gatts_value_set(uint16_t handle, uint16_t offset, uint16_t* const p_len, uint8_t const * const p_value) { + ble_gatts_value_t val; + + val.len = *p_len; + val.offset = offset; + val.p_value = (uint8_t*)p_value; + return sd_ble_gatts_value_set(BLE_CONN_HANDLE_INVALID, handle, &val); +} +#endif + +#include "Arduino.h" + +#include "BLEAttribute.h" +#include "BLEService.h" +#include "BLECharacteristic.h" +#include "BLEDescriptor.h" +#include "BLEUtil.h" +#include "BLEUuid.h" + +#include "nRF51822.h" + +// #define NRF_51822_DEBUG + +#define BLE_STACK_EVT_MSG_BUF_SIZE (sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT)) + +#ifndef BLE_GATTS_ATTR_TAB_SIZE + #define BLE_GATTS_ATTR_TAB_SIZE BLE_GATTS_ATTR_TAB_SIZE_DEFAULT +#endif + +#define SCAN_INTERVAL_MS 100 +#define WINDOW_LEN_MS (SCAN_INTERVAL_MS / 4) +#define MAX_ADV_PACK_LEN (BLE_GAP_ADV_MAX_SIZE + BLE_GAP_ADDR_LEN + 2) +#define ADV_TYPE_LEN 2 +#define BEACON_DATA_LEN 21 + +#ifdef __cplusplus +extern "C" { +#endif +static void initScanParams(); +#ifdef __cplusplus +} +#endif + +nRF51822::nRF51822() : + BLEDevice(), + + _advDataLen(0), + _hasScanData(false), + _broadcastCharacteristic(NULL), + + _connectionHandle(BLE_CONN_HANDLE_INVALID), + + _txBufferCount(0), + + _numLocalCharacteristics(0), + _localCharacteristicInfo(NULL), + + _numRemoteServices(0), + _remoteServiceInfo(NULL), + _remoteServiceDiscoveryIndex(0), + _numRemoteCharacteristics(0), + _remoteCharacteristicInfo(NULL), + _remoteRequestInProgress(false) +{ +#if defined(NRF5) || defined(NRF51_S130) + this->_encKey = (ble_gap_enc_key_t*)&this->_bondData; + memset(&this->_bondData, 0, sizeof(this->_bondData)); +#else + this->_authStatus = (ble_gap_evt_auth_status_t*)&this->_authStatusBuffer; + memset(&this->_authStatusBuffer, 0, sizeof(this->_authStatusBuffer)); +#endif + initScanParams(); +} + +nRF51822::~nRF51822() { + this->end(); +} + +#ifdef __cplusplus +extern "C" { +#endif + +static ble_gap_scan_params_t scan_params; + +static void initScanParams() { + memset(&scan_params, 0, sizeof(scan_params)); + scan_params.active = false; + scan_params.selective = false; + scan_params.p_whitelist = NULL; + scan_params.interval = MSEC_TO_UNITS(SCAN_INTERVAL_MS, UNIT_0_625_MS); + scan_params.window = MSEC_TO_UNITS(WINDOW_LEN_MS, UNIT_0_625_MS); + scan_params.timeout = 0; // disable timeout +} + +void BLEPeripheralStartSoftDevice() { + /** test code for RC low freq clock + nrf_clock_lf_cfg_t cfg = { + .source = NRF_CLOCK_LF_SRC_RC, + .rc_ctiv = 16, // SEE NOTES IN lp_timer.cpp + .rc_temp_ctiv = 2, + .xtal_accuracy = 0 // not used NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM + }; + sd_softdevice_enable(&cfg, NULL); + ***/ + #ifdef __RFduino__ + sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_SYNTH_250_PPM, NULL); +#elif defined(NRF5) && !defined(S110) + #if defined(USE_LFRC) + nrf_clock_lf_cfg_t cfg = { + .source = NRF_CLOCK_LF_SRC_RC, + .rc_ctiv = 16, // SEE NOTES IN lp_timer.cpp + .rc_temp_ctiv = 2, + .xtal_accuracy = 0 // not used NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM + }; + #elif defined(USE_LFSYNT) + + nrf_clock_lf_cfg_t cfg = { + .source = NRF_CLOCK_LF_SRC_SYNTH, + .rc_ctiv = 0, + .rc_temp_ctiv = 0, + .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM + }; + + #else + //default USE_LFXO + nrf_clock_lf_cfg_t cfg = { + .source = NRF_CLOCK_LF_SRC_XTAL, + .rc_ctiv = 0, + .rc_temp_ctiv = 0, + .xtal_accuracy = NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM + }; + #endif + + sd_softdevice_enable(&cfg, NULL); + +#else + #if defined(USE_LFRC) + sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_RC_250_PPM_250MS_CALIBRATION, NULL); + #elif defined(USE_LFSYNT) + sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_SYNTH_250_PPM, NULL); + #else + //default USE_LFXO + sd_softdevice_enable(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, NULL); + #endif +#endif +} + +#ifdef __cplusplus +} +#endif + + // update these while not scanning and then call startScanning() to apply them +void nRF51822::setScanInterval(uint16_t interval, uint16_t window) { + // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms + scan_params.interval = interval; + scan_params.window = window; +} + +void nRF51822::setActiveScan(bool enable) { + // Request scan response data, default is false + scan_params.active = enable; +} + +void nRF51822::setScanTimeout(uint16_t timeout) { + // 0 = Don't stop scanning after n seconds + scan_params.timeout = timeout; +} + + +// define this to print out to serial the min ram needed +// then set +//C:\Users\matthew\AppData\Local\Arduino15\packages\sandeepmistry\hardware\nRF5\0.6.0\cores\nRF5\SDK\components\softdevice\s132\toolchain\armgcc +// armgcc_s132_nrf52832_xxaa.ld +// RAM (rwx) : ORIGIN = 0x20002080, LENGTH = 0xdf80 +// actually returned 20002078 but add 8 bytes (possible corruption) +//#define DEBUG_RAM_BASE +// NOTE: must have called Serial.begin(...) in sketch before ble begin() + +void nRF51822::begin(unsigned char advertisementDataSize, + BLEEirData *advertisementData, + unsigned char scanDataSize, + BLEEirData *scanData, + BLELocalAttribute** localAttributes, + unsigned char numLocalAttributes, + BLERemoteAttribute** remoteAttributes, + unsigned char numRemoteAttributes) +{ + +// BLEPeripheralStartSoftDevice(); called in main.cpp to startup softdevice and LC clock +uint32_t errorCode = 0; +uint32_t app_ram_base_required = 0; + +#if defined(NRF5) && !defined(S110) + extern uint32_t __data_start__; + uint32_t app_ram_base = 0x20002780; + + ble_enable_params_t enableParams; + + memset(&enableParams, 0, sizeof(ble_enable_params_t)); + enableParams.common_enable_params.vs_uuid_count = 50; + enableParams.gatts_enable_params.attr_tab_size = 0x800;//BLE_GATTS_ATTR_TAB_SIZE; + enableParams.gatts_enable_params.service_changed = 1; + enableParams.gap_enable_params.periph_conn_count = 1; + enableParams.gap_enable_params.central_conn_count = 0; + enableParams.gap_enable_params.central_sec_count = 0; + +#ifdef DEBUG_RAM_BASE + //errorCode = sd_ble_enable(&enableParams, &app_ram_base); // testing + errorCode = sd_ble_enable(&enableParams, &app_ram_base_required); + Serial.print(F("sd_ble_enable = ")); + Serial.print(errorCode); + Serial.print(F(" sd Ram Required = ")); + Serial.println(app_ram_base_required, HEX); + Serial.print(F(" __data_start__ = ")); + Serial.println(__data_start__, HEX); + +#else + errorCode = sd_ble_enable(&enableParams, &app_ram_base); // normal call should return 0 +#endif + +#elif defined(S110) + ble_enable_params_t enableParams = { + .gatts_enable_params = { + .service_changed = true, + .attr_tab_size = BLE_GATTS_ATTR_TAB_SIZE + } + }; + + sd_ble_enable(&enableParams); +#elif defined(NRF51_S130) + ble_enable_params_t enableParams = { + .gatts_enable_params = { + .service_changed = true + } + }; + + sd_ble_enable(&enableParams); +#endif + +#ifdef NRF_51822_DEBUG + ble_version_t version; + + sd_ble_version_get(&version); + + Serial.print(F("version = ")); + Serial.print(version.version_number); + Serial.print(F(" ")); + Serial.print(version.company_id); + Serial.print(F(" ")); + Serial.print(version.subversion_number); + Serial.println(); +#endif + + ble_gap_conn_params_t gap_conn_params; + + gap_conn_params.min_conn_interval = (DEFAULT_MIN_CONNECTION_INTERVAL_ms * 8) / 10; // in 1.25ms units + gap_conn_params.max_conn_interval = (DEFAULT_MAX_CONNECTION_INTERVAL_ms * 8) / 10; // in 1.25ms unit + gap_conn_params.slave_latency = 0; + gap_conn_params.conn_sup_timeout = DEFAULT_CONNECTION_SUPERVISION_TIMEOUT_ms / 10; // in 10ms unit + + sd_ble_gap_ppcp_set(&gap_conn_params); + sd_ble_gap_tx_power_set(DEFAULT_BLE_TX_POWER); + + unsigned char srData[31]; + unsigned char srDataLen = 0; + + this->_advDataLen = 0; + + // flags + this->_advData[this->_advDataLen + 0] = 2; + this->_advData[this->_advDataLen + 1] = 0x01; + this->_advData[this->_advDataLen + 2] = 0x06; + + this->_advDataLen += 3; + + if (advertisementDataSize && advertisementData) { + for (int i = 0; i < advertisementDataSize; i++) { + this->_advData[this->_advDataLen + 0] = advertisementData[i].length + 1; + this->_advData[this->_advDataLen + 1] = advertisementData[i].type; + this->_advDataLen += 2; + + memcpy(&this->_advData[this->_advDataLen], advertisementData[i].data, advertisementData[i].length); + + this->_advDataLen += advertisementData[i].length; + } + } + + if (scanDataSize && scanData) { + for (int i = 0; i < scanDataSize; i++) { + srData[srDataLen + 0] = scanData[i].length + 1; + srData[srDataLen + 1] = scanData[i].type; + srDataLen += 2; + + memcpy(&srData[srDataLen], scanData[i].data, scanData[i].length); + + srDataLen += scanData[i].length; + _hasScanData = true; + } + } + + sd_ble_gap_adv_data_set(this->_advData, this->_advDataLen, srData, srDataLen); + sd_ble_gap_appearance_set(0); + + for (int i = 0; i < numLocalAttributes; i++) { + BLELocalAttribute *localAttribute = localAttributes[i]; + + if (localAttribute->type() == BLETypeCharacteristic) { + this->_numLocalCharacteristics++; + } + } + + this->_numLocalCharacteristics -= 3; // 0x2a00, 0x2a01, 0x2a05 + + this->_localCharacteristicInfo = (struct localCharacteristicInfo*)malloc(sizeof(struct localCharacteristicInfo) * this->_numLocalCharacteristics); + + unsigned char localCharacteristicIndex = 0; + + uint16_t handle = 0; + BLEService *lastService = NULL; + + for (int i = 0; i < numLocalAttributes; i++) { + BLELocalAttribute *localAttribute = localAttributes[i]; + BLEUuid uuid = BLEUuid(localAttribute->uuid()); + const unsigned char* uuidData = uuid.data(); + unsigned char value[255]; + + ble_uuid_t nordicUUID; + + if (uuid.length() == 2) { + nordicUUID.uuid = (uuidData[1] << 8) | uuidData[0]; + nordicUUID.type = BLE_UUID_TYPE_BLE; + } else { + unsigned char uuidDataTemp[16]; + + memcpy(&uuidDataTemp, uuidData, sizeof(uuidDataTemp)); + + nordicUUID.uuid = (uuidData[13] << 8) | uuidData[12]; + + uuidDataTemp[13] = 0; + uuidDataTemp[12] = 0; + + sd_ble_uuid_vs_add((ble_uuid128_t*)&uuidDataTemp, &nordicUUID.type); + } + + if (localAttribute->type() == BLETypeService) { + BLEService *service = (BLEService *)localAttribute; + + if (strcmp(service->uuid(), "1800") == 0 || strcmp(service->uuid(), "1801") == 0) { + continue; // skip + } + + sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY, &nordicUUID, &handle); + + lastService = service; + } else if (localAttribute->type() == BLETypeCharacteristic) { + BLECharacteristic *characteristic = (BLECharacteristic *)localAttribute; + + if (strcmp(characteristic->uuid(), "2a00") == 0) { + ble_gap_conn_sec_mode_t secMode; + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&secMode); // no security is needed + + sd_ble_gap_device_name_set(&secMode, characteristic->value(), characteristic->valueLength()); + } else if (strcmp(characteristic->uuid(), "2a01") == 0) { + const uint16_t *appearance = (const uint16_t*)characteristic->value(); + + sd_ble_gap_appearance_set(*appearance); + } else if (strcmp(characteristic->uuid(), "2a05") == 0) { + // do nothing + } else { + uint8_t properties = characteristic->properties() & 0xfe; + uint16_t valueLength = characteristic->valueLength(); + + this->_localCharacteristicInfo[localCharacteristicIndex].characteristic = characteristic; + this->_localCharacteristicInfo[localCharacteristicIndex].notifySubscribed = false; + this->_localCharacteristicInfo[localCharacteristicIndex].indicateSubscribed = false; + this->_localCharacteristicInfo[localCharacteristicIndex].service = lastService; + + ble_gatts_char_md_t characteristicMetaData; + ble_gatts_attr_md_t clientCharacteristicConfigurationMetaData; + ble_gatts_attr_t characteristicValueAttribute; + ble_gatts_attr_md_t characteristicValueAttributeMetaData; + + memset(&characteristicMetaData, 0, sizeof(characteristicMetaData)); + + memcpy(&characteristicMetaData.char_props, &properties, 1); + + characteristicMetaData.p_char_user_desc = NULL; + characteristicMetaData.p_char_pf = NULL; + characteristicMetaData.p_user_desc_md = NULL; + characteristicMetaData.p_cccd_md = NULL; + characteristicMetaData.p_sccd_md = NULL; + + if (properties & (BLENotify | BLEIndicate)) { + memset(&clientCharacteristicConfigurationMetaData, 0, sizeof(clientCharacteristicConfigurationMetaData)); + + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&clientCharacteristicConfigurationMetaData.read_perm); + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&clientCharacteristicConfigurationMetaData.write_perm); + + clientCharacteristicConfigurationMetaData.vloc = BLE_GATTS_VLOC_STACK; + + characteristicMetaData.p_cccd_md = &clientCharacteristicConfigurationMetaData; + } + + memset(&characteristicValueAttributeMetaData, 0, sizeof(characteristicValueAttributeMetaData)); + + if (properties & (BLERead | BLENotify | BLEIndicate)) { + if (this->_bondStore) { + BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(&characteristicValueAttributeMetaData.read_perm); + } else { + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&characteristicValueAttributeMetaData.read_perm); + } + } + + if (properties & (BLEWriteWithoutResponse | BLEWrite)) { + if (this->_bondStore) { + BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(&characteristicValueAttributeMetaData.write_perm); + } else { + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&characteristicValueAttributeMetaData.write_perm); + } + } + + characteristicValueAttributeMetaData.vloc = BLE_GATTS_VLOC_STACK; + characteristicValueAttributeMetaData.rd_auth = 0; + characteristicValueAttributeMetaData.wr_auth = 0; + characteristicValueAttributeMetaData.vlen = !characteristic->fixedLength(); + + for (int j = (i + 1); j < numLocalAttributes; j++) { + localAttribute = localAttributes[j]; + + if (localAttribute->type() != BLETypeDescriptor) { + break; + } + + BLEDescriptor *descriptor = (BLEDescriptor *)localAttribute; + + if (strcmp(descriptor->uuid(), "2901") == 0) { + characteristicMetaData.p_char_user_desc = (uint8_t*)descriptor->value(); + characteristicMetaData.char_user_desc_max_size = descriptor->valueLength(); + characteristicMetaData.char_user_desc_size = descriptor->valueLength(); + } else if (strcmp(descriptor->uuid(), "2904") == 0) { + characteristicMetaData.p_char_pf = (ble_gatts_char_pf_t *)descriptor->value(); + } + } + + memset(&characteristicValueAttribute, 0, sizeof(characteristicValueAttribute)); + + characteristicValueAttribute.p_uuid = &nordicUUID; + characteristicValueAttribute.p_attr_md = &characteristicValueAttributeMetaData; + characteristicValueAttribute.init_len = valueLength; + characteristicValueAttribute.init_offs = 0; + characteristicValueAttribute.max_len = characteristic->valueSize(); + characteristicValueAttribute.p_value = NULL; + + sd_ble_gatts_characteristic_add(BLE_GATT_HANDLE_INVALID, &characteristicMetaData, &characteristicValueAttribute, &this->_localCharacteristicInfo[localCharacteristicIndex].handles); + + if (valueLength) { + for (int j = 0; j < valueLength; j++) { + value[j] = (*characteristic)[j]; + } + + sd_ble_gatts_value_set(this->_localCharacteristicInfo[localCharacteristicIndex].handles.value_handle, 0, &valueLength, value); + } + + localCharacteristicIndex++; + } + } else if (localAttribute->type() == BLETypeDescriptor) { + BLEDescriptor *descriptor = (BLEDescriptor *)localAttribute; + + if (strcmp(descriptor->uuid(), "2901") == 0 || + strcmp(descriptor->uuid(), "2902") == 0 || + strcmp(descriptor->uuid(), "2903") == 0 || + strcmp(descriptor->uuid(), "2904") == 0) { + continue; // skip + } + + uint16_t valueLength = descriptor->valueLength(); + + ble_gatts_attr_t descriptorAttribute; + ble_gatts_attr_md_t descriptorMetaData; + + memset(&descriptorAttribute, 0, sizeof(descriptorAttribute)); + memset(&descriptorMetaData, 0, sizeof(descriptorMetaData)); + + descriptorMetaData.vloc = BLE_GATTS_VLOC_STACK; + descriptorMetaData.vlen = (valueLength == descriptor->valueLength()) ? 0 : 1; + + if (this->_bondStore) { + BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(&descriptorMetaData.read_perm); + } else { + BLE_GAP_CONN_SEC_MODE_SET_OPEN(&descriptorMetaData.read_perm); + } + + descriptorAttribute.p_uuid = &nordicUUID; + descriptorAttribute.p_attr_md = &descriptorMetaData; + descriptorAttribute.init_len = valueLength; + descriptorAttribute.max_len = descriptor->valueLength(); + descriptorAttribute.p_value = NULL; + + sd_ble_gatts_descriptor_add(BLE_GATT_HANDLE_INVALID, &descriptorAttribute, &handle); + + if (valueLength) { + for (int j = 0; j < valueLength; j++) { + value[j] = (*descriptor)[j]; + } + + sd_ble_gatts_value_set(handle, 0, &valueLength, value); + } + } + } + + if ( numRemoteAttributes > 0) { + numRemoteAttributes -= 2; // 0x1801, 0x2a05 + } + + for (int i = 0; i < numRemoteAttributes; i++) { + BLERemoteAttribute *remoteAttribute = remoteAttributes[i]; + + if (remoteAttribute->type() == BLETypeService) { + this->_numRemoteServices++; + } else if (remoteAttribute->type() == BLETypeCharacteristic) { + this->_numRemoteCharacteristics++; + } + } + + this->_remoteServiceInfo = (struct remoteServiceInfo*)malloc(sizeof(struct remoteServiceInfo) * this->_numRemoteServices); + this->_remoteCharacteristicInfo = (struct remoteCharacteristicInfo*)malloc(sizeof(struct remoteCharacteristicInfo) * this->_numRemoteCharacteristics); + + BLERemoteService *lastRemoteService = NULL; + unsigned char remoteServiceIndex = 0; + unsigned char remoteCharacteristicIndex = 0; + + for (int i = 0; i < numRemoteAttributes; i++) { + BLERemoteAttribute *remoteAttribute = remoteAttributes[i]; + BLEUuid uuid = BLEUuid(remoteAttribute->uuid()); + const unsigned char* uuidData = uuid.data(); + + ble_uuid_t nordicUUID; + + if (uuid.length() == 2) { + nordicUUID.uuid = (uuidData[1] << 8) | uuidData[0]; + nordicUUID.type = BLE_UUID_TYPE_BLE; + } else { + unsigned char uuidDataTemp[16]; + + memcpy(&uuidDataTemp, uuidData, sizeof(uuidDataTemp)); + + nordicUUID.uuid = (uuidData[13] << 8) | uuidData[12]; + + uuidDataTemp[13] = 0; + uuidDataTemp[12] = 0; + + sd_ble_uuid_vs_add((ble_uuid128_t*)&uuidDataTemp, &nordicUUID.type); + } + + if (remoteAttribute->type() == BLETypeService) { + this->_remoteServiceInfo[remoteServiceIndex].service = lastRemoteService = (BLERemoteService *)remoteAttribute; + this->_remoteServiceInfo[remoteServiceIndex].uuid = nordicUUID; + + memset(&this->_remoteServiceInfo[remoteServiceIndex].handlesRange, 0, sizeof(this->_remoteServiceInfo[remoteServiceIndex].handlesRange)); + + remoteServiceIndex++; + } else if (remoteAttribute->type() == BLETypeCharacteristic) { + this->_remoteCharacteristicInfo[remoteCharacteristicIndex].characteristic = (BLERemoteCharacteristic *)remoteAttribute; + this->_remoteCharacteristicInfo[remoteCharacteristicIndex].service = lastRemoteService; + this->_remoteCharacteristicInfo[remoteCharacteristicIndex].uuid = nordicUUID; + + memset(&this->_remoteCharacteristicInfo[remoteCharacteristicIndex].properties, 0, sizeof(this->_remoteCharacteristicInfo[remoteCharacteristicIndex].properties)); + this->_remoteCharacteristicInfo[remoteCharacteristicIndex].valueHandle = 0; + + remoteCharacteristicIndex++; + } + } + + if (this->_bondStore && this->_bondStore->hasData()) { +#ifdef NRF_51822_DEBUG + Serial.println(F("Restoring bond data")); +#endif +#if defined(NRF5) || defined(NRF51_S130) + this->_bondStore->getData(this->_bondData, 0, sizeof(this->_bondData)); +#else + this->_bondStore->getData(this->_authStatusBuffer, 0, sizeof(this->_authStatusBuffer)); +#endif + } + + this->startAdvertising(); + +#ifdef __RFduino__ + RFduinoBLE_enabled = 1; +#endif +} + + +bool nRF51822::startScanning(ble_scan_response_handler_t scanResponseHandler) { + _scanResponseHandler = scanResponseHandler; + uint32_t err_code = sd_ble_gap_scan_start(&scan_params); + return err_code == NRF_SUCCESS; // true if OK +} + +bool nRF51822::stopScanning() { + uint32_t err_code = sd_ble_gap_scan_stop(); + return err_code == NRF_SUCCESS; // true if OK +} + +bool nRF51822::poll() { + uint32_t evtBuf[BLE_STACK_EVT_MSG_BUF_SIZE] __attribute__ ((__aligned__(BLE_EVTS_PTR_ALIGNMENT))); + uint16_t evtLen = sizeof(evtBuf); + ble_evt_t* bleEvt = (ble_evt_t*)evtBuf; + bool rtn = false; + if (sd_ble_evt_get((uint8_t*)evtBuf, &evtLen) == NRF_SUCCESS) { + rtn = true; // found one + switch (bleEvt->header.evt_id) { + case BLE_EVT_TX_COMPLETE: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt TX complete ")); + Serial.println(bleEvt->evt.common_evt.params.tx_complete.count); +#endif + this->_txBufferCount += bleEvt->evt.common_evt.params.tx_complete.count; + break; + + case BLE_GAP_EVT_ADV_REPORT: { +/********** +typedef struct +{ + ble_evt_hdr_t header; /**< Event header. + union + { + ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. + ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. + ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. + ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. + ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. + } evt; +} ble_evt_t; + +/** GAP event structure. +typedef struct +{ + uint16_t conn_handle; /**< Connection Handle on which event occurred. + union /**< union alternative identified by evt_id in enclosing struct. + { + ble_gap_evt_connected_t connected; /**< Connected Event Parameters. + ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. + ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. + ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. + ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. + ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. + ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. + ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. + ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. + ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. + ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. + ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. + ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event parameters. + ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. + ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. + ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. + ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report parameters. + } params; /**< Event Parameters. + +} ble_gap_evt_t; + + typedef struct { + ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. + int8_t rssi; /**< Received Signal Strength Indication in dBm. + uint8_t scan_rsp : 1; /**< If 1, the report corresponds to a scan response and the type field may be ignored. + uint8_t type : 2; /**< See @ref BLE_GAP_ADV_TYPES. Only valid if the scan_rsp field is 0. + uint8_t dlen : 5; /**< Advertising or scan response data length. + uint8_t data[BLE_GAP_ADV_MAX_SIZE]; /**< Advertising or scan response data. +} ble_gap_evt_adv_report_t; + +typedef struct { + uint8_t addr_id_peer : 1; /**< Only valid for peer addresses. + This bit is set by the SoftDevice to indicate whether the address has been resolved from + a Resolvable Private Address (when the peer is using privacy). + If set to 1, @ref addr and @ref addr_type refer to the identity address of the resolved address. + + This bit is ignored when a variable of type @ref ble_gap_addr_t is used as input to API functions. + uint8_t addr_type : 7; /**< See @ref BLE_GAP_ADDR_TYPES. + uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. + @ref addr is not used if @ref addr_type is @ref BLE_GAP_ADDR_TYPE_ANONYMOUS. +} ble_gap_addr_t; + +BLE address length. +#define BLE_GAP_ADDR_LEN (6) +#define BLE_GAP_ADV_MAX_SIZE 31 + +/** BLE_GAP_ADV_TYPES GAP Advertising types +#define BLE_GAP_ADV_TYPE_ADV_IND 0x00 /**< Connectable undirected. +#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND 0x01 /**< Connectable directed. +#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND 0x02 /**< Scannable undirected. +#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND 0x03 /**< Non connectable undirected. +**********/ + + ble_gap_evt_t * p_gap_evt = &(bleEvt->evt.gap_evt); + ble_gap_evt_adv_report_t *p_adv_report = &(p_gap_evt->params.adv_report); + //ble_gap_evt_adv_report_t const * p_adv_report = &bleEvt->evt.gap_evt.params.adv_report; + uint8_t scan_response_type = p_adv_report->scan_rsp; + uint8_t _len = p_adv_report->dlen; + uint8_t *_data = p_adv_report->data; +#ifdef NRF_51822_DEBUG + if (scan_response_type) { + if (_len > 0) { + Serial.print("Scan response received:"); + BLEUtil::printBuffer(&Serial,_data, _len); + } else { + Serial.print("Empty scan response received."); + } + } else { + Serial.print("Advertising packet received:"); + BLEUtil::printBuffer(&Serial,_data, _len); + } +#endif + if (this->_scanResponseHandler != NULL) { +#ifdef NRF_51822_DEBUG + Serial.println("call handler"); +#endif + this->_scanResponseHandler(p_adv_report); + } + // Continue scanning. + //sd_ble_gap_scan_start(NULL, &m_scan_buffer); + break; + } + + case BLE_GAP_EVT_CONNECTED: { + +#ifdef NRF_51822_DEBUG + char address[18]; + + BLEUtil::addressToString(bleEvt->evt.gap_evt.params.connected.peer_addr.addr, address); + + Serial.print(F("Evt Connected ")); + Serial.println(address); +#endif + + this->_connectionHandle = bleEvt->evt.gap_evt.conn_handle; + +#if defined(NRF5) && !defined(S110) + { + uint8_t count; + + sd_ble_tx_packet_count_get(this->_connectionHandle, &count); + + this->_txBufferCount = count; + } +#else + sd_ble_tx_buffer_count_get(&this->_txBufferCount); +#endif + + if (this->_eventListener) { + this->_eventListener->BLEDeviceConnected(*this, bleEvt->evt.gap_evt.params.connected.peer_addr.addr); + } + // note this case is inside a { } block + unsigned short minConInterval = (this->_minimumConnectionInterval * 8) /10; // in 1.25ms units + unsigned short maxConInterval = (this->_maximumConnectionInterval * 8) /10; // in 1.25ms units + + if ((minConInterval >= BLE_GAP_CP_MIN_CONN_INTVL_MIN) && + (maxConInterval <= BLE_GAP_CP_MAX_CONN_INTVL_MAX)) { + + ble_gap_conn_params_t gap_conn_params; + +#ifdef NRF_51822_DEBUG + Serial.print(F(" minConInterval: ")); Serial.print(minConInterval); + Serial.print(F(" maxConInterval: ")); Serial.print(maxConInterval); + Serial.println(); +#endif + // check slaveLatency + int latency = this->_slaveLatency; + int maxLatency = ((int)DEFAULT_CONNECTION_SUPERVISION_TIMEOUT_ms) / ((int)this->_maximumConnectionInterval) -1; + if (latency > maxLatency) { + latency = maxLatency -1 ; + } + if (latency < 0) { + latency = 0; + } + this->_slaveLatency = latency; + gap_conn_params.min_conn_interval = minConInterval; // in 1.25ms units + gap_conn_params.max_conn_interval = maxConInterval; // in 1.25ms units + gap_conn_params.slave_latency = this->_slaveLatency; + gap_conn_params.conn_sup_timeout = DEFAULT_CONNECTION_SUPERVISION_TIMEOUT_ms / 10; // in 10ms unit + + sd_ble_gap_conn_param_update(this->_connectionHandle, &gap_conn_params); + } + + if (this->_numRemoteServices > 0) { + sd_ble_gattc_primary_services_discover(this->_connectionHandle, 1, NULL); + } + break; + } + case BLE_GAP_EVT_DISCONNECTED: +#ifdef NRF_51822_DEBUG + Serial.println(F("Evt Disconnected")); +#endif + this->_connectionHandle = BLE_CONN_HANDLE_INVALID; + this->_txBufferCount = 0; + + for (int i = 0; i < this->_numLocalCharacteristics; i++) { + struct localCharacteristicInfo* localCharacteristicInfo = &this->_localCharacteristicInfo[i]; + + localCharacteristicInfo->notifySubscribed = false; + localCharacteristicInfo->indicateSubscribed = false; + + if (localCharacteristicInfo->characteristic->subscribed()) { + if (this->_eventListener) { + this->_eventListener->BLEDeviceCharacteristicSubscribedChanged(*this, *localCharacteristicInfo->characteristic, false); + } + } + } + + if (this->_eventListener) { + this->_eventListener->BLEDeviceDisconnected(*this); + } + + // clear remote handle info + for (int i = 0; i < this->_numRemoteServices; i++) { + memset(&this->_remoteServiceInfo[i].handlesRange, 0, sizeof(this->_remoteServiceInfo[i].handlesRange)); + } + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + memset(&this->_remoteCharacteristicInfo[i].properties, 0, sizeof(this->_remoteCharacteristicInfo[i].properties)); + this->_remoteCharacteristicInfo[i].valueHandle = 0; + } + + this->_remoteRequestInProgress = false; + + this->startAdvertising(); + break; + + case BLE_GAP_EVT_CONN_PARAM_UPDATE: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Conn Param Update 0x")); + Serial.print(bleEvt->evt.gap_evt.params.conn_param_update.conn_params.min_conn_interval, HEX); + Serial.print(F(" 0x")); + Serial.print(bleEvt->evt.gap_evt.params.conn_param_update.conn_params.max_conn_interval, HEX); + Serial.print(F(" 0x")); + Serial.print(bleEvt->evt.gap_evt.params.conn_param_update.conn_params.slave_latency, HEX); + Serial.print(F(" 0x")); + Serial.print(bleEvt->evt.gap_evt.params.conn_param_update.conn_params.conn_sup_timeout, HEX); + Serial.println(); +#endif + break; + + case BLE_GAP_EVT_SEC_PARAMS_REQUEST: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Sec Params Request ")); +#if !defined(NRF5) && !defined(NRF51_S130) + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.timeout); + Serial.print(F(" ")); +#endif + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.bond); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.mitm); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.io_caps); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.oob); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.min_key_size); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_params_request.peer_params.max_key_size); + Serial.println(); +#endif + + if (this->_bondStore && !this->_bondStore->hasData()) { + // only allow bonding if bond store exists and there is no data + + ble_gap_sec_params_t gapSecParams; + + memset(&gapSecParams, 0x00, sizeof(ble_gap_sec_params_t)); + +#if defined(NRF5) && !defined(S110) + gapSecParams.kdist_own.enc = 1; +#elif defined(NRF51_S130) + gapSecParams.kdist_periph.enc = 1; +#elif !defined(NRF5) + gapSecParams.timeout = 30; // must be 30s +#endif + gapSecParams.bond = true; + gapSecParams.mitm = false; + gapSecParams.io_caps = BLE_GAP_IO_CAPS_NONE; + gapSecParams.oob = false; + gapSecParams.min_key_size = 7; + gapSecParams.max_key_size = 16; + +#if defined(NRF5) && !defined(S110) + ble_gap_sec_keyset_t keyset; + + keyset.keys_peer.p_enc_key = NULL; + keyset.keys_peer.p_id_key = NULL; + keyset.keys_peer.p_sign_key = NULL; + keyset.keys_own.p_enc_key = this->_encKey; + keyset.keys_own.p_id_key = NULL; + keyset.keys_own.p_sign_key = NULL; + + sd_ble_gap_sec_params_reply(this->_connectionHandle, BLE_GAP_SEC_STATUS_SUCCESS, &gapSecParams, &keyset); +#elif defined(NRF51_S130) || defined(S110) + ble_gap_sec_keyset_t keyset; + + keyset.keys_central.p_enc_key = NULL; + keyset.keys_central.p_id_key = NULL; + keyset.keys_central.p_sign_key = NULL; + keyset.keys_periph.p_enc_key = this->_encKey; + keyset.keys_periph.p_id_key = NULL; + keyset.keys_periph.p_sign_key = NULL; + + sd_ble_gap_sec_params_reply(this->_connectionHandle, BLE_GAP_SEC_STATUS_SUCCESS, &gapSecParams, &keyset); +#else + sd_ble_gap_sec_params_reply(this->_connectionHandle, BLE_GAP_SEC_STATUS_SUCCESS, &gapSecParams); +#endif + } else { +#if defined(NRF5) || defined(NRF51_S130) + sd_ble_gap_sec_params_reply(this->_connectionHandle, BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, NULL, NULL); +#else + sd_ble_gap_sec_params_reply(this->_connectionHandle, BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP, NULL); +#endif + } + break; + + case BLE_GAP_EVT_SEC_INFO_REQUEST: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Sec Info Request ")); + // Serial.print(bleEvt->evt.gap_evt.params.sec_info_request.peer_addr); + // Serial.print(F(" ")); +#if defined(NRF5) || defined(NRF51_S130) + Serial.print(bleEvt->evt.gap_evt.params.sec_info_request.master_id.ediv); +#else + Serial.print(bleEvt->evt.gap_evt.params.sec_info_request.div); +#endif + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_info_request.enc_info); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_info_request.id_info); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.sec_info_request.sign_info); + Serial.println(); +#endif +#if defined(NRF5) || defined(NRF51_S130) + if (this->_encKey->master_id.ediv == bleEvt->evt.gap_evt.params.sec_info_request.master_id.ediv) { + sd_ble_gap_sec_info_reply(this->_connectionHandle, &this->_encKey->enc_info, NULL, NULL); + } else { + sd_ble_gap_sec_info_reply(this->_connectionHandle, NULL, NULL, NULL); + } +#else + if (this->_authStatus->periph_keys.enc_info.div == bleEvt->evt.gap_evt.params.sec_info_request.div) { + sd_ble_gap_sec_info_reply(this->_connectionHandle, &this->_authStatus->periph_keys.enc_info, NULL); + } else { + sd_ble_gap_sec_info_reply(this->_connectionHandle, NULL, NULL); + } +#endif + break; + + case BLE_GAP_EVT_AUTH_STATUS: +#ifdef NRF_51822_DEBUG + Serial.println(F("Evt Auth Status")); + Serial.println(bleEvt->evt.gap_evt.params.auth_status.auth_status); +#endif + if (BLE_GAP_SEC_STATUS_SUCCESS == bleEvt->evt.gap_evt.params.auth_status.auth_status) { +#if !defined(NRF5) && !defined(NRF51_S130) + *this->_authStatus = bleEvt->evt.gap_evt.params.auth_status; +#endif + if (this->_bondStore) { +#ifdef NRF_51822_DEBUG + Serial.println(F("Storing bond data")); +#endif +#if defined(NRF5) || defined(NRF51_S130) + this->_bondStore->putData(this->_bondData, 0, sizeof(this->_bondData)); +#else + this->_bondStore->putData(this->_authStatusBuffer, 0, sizeof(this->_authStatusBuffer)); +#endif + } + + if (this->_eventListener) { + this->_eventListener->BLEDeviceBonded(*this); + } + } + break; + + case BLE_GAP_EVT_CONN_SEC_UPDATE: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Conn Sec Update ")); + Serial.print(bleEvt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.sm); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv); + Serial.print(F(" ")); + Serial.print(bleEvt->evt.gap_evt.params.conn_sec_update.conn_sec.encr_key_size); + Serial.println(); +#endif + break; + + case BLE_GATTS_EVT_WRITE: { +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Write, handle = ")); + Serial.println(bleEvt->evt.gatts_evt.params.write.handle, DEC); + + BLEUtil::printBuffer(&Serial,bleEvt->evt.gatts_evt.params.write.data, bleEvt->evt.gatts_evt.params.write.len); +#endif + + uint16_t handle = bleEvt->evt.gatts_evt.params.write.handle; + + for (int i = 0; i < this->_numLocalCharacteristics; i++) { + struct localCharacteristicInfo* localCharacteristicInfo = &this->_localCharacteristicInfo[i]; + + if (localCharacteristicInfo->handles.value_handle == handle) { + if (this->_eventListener) { + this->_eventListener->BLEDeviceCharacteristicValueChanged(*this, *localCharacteristicInfo->characteristic, bleEvt->evt.gatts_evt.params.write.data, bleEvt->evt.gatts_evt.params.write.len); + } + break; + } else if (localCharacteristicInfo->handles.cccd_handle == handle) { + uint8_t* data = &bleEvt->evt.gatts_evt.params.write.data[0]; + uint16_t value = data[0] | (data[1] << 8); + + localCharacteristicInfo->notifySubscribed = (value & 0x0001); + localCharacteristicInfo->indicateSubscribed = (value & 0x0002); + + bool subscribed = (localCharacteristicInfo->notifySubscribed || localCharacteristicInfo->indicateSubscribed); + + if (subscribed != localCharacteristicInfo->characteristic->subscribed()) { + if (this->_eventListener) { + this->_eventListener->BLEDeviceCharacteristicSubscribedChanged(*this, *localCharacteristicInfo->characteristic, subscribed); + } + break; + } + } + } + break; + } + + case BLE_GATTS_EVT_SYS_ATTR_MISSING: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Sys Attr Missing ")); + Serial.println(bleEvt->evt.gatts_evt.params.sys_attr_missing.hint); +#endif +#if defined(NRF5) || defined(NRF51_S130) + sd_ble_gatts_sys_attr_set(this->_connectionHandle, NULL, 0, 0); +#else + sd_ble_gatts_sys_attr_set(this->_connectionHandle, NULL, 0); +#endif + break; + + case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Prim Srvc Disc Rsp 0x")); + Serial.println(bleEvt->evt.gattc_evt.gatt_status, HEX); +#endif + if (bleEvt->evt.gattc_evt.gatt_status == BLE_GATT_STATUS_SUCCESS) { + uint16_t count = bleEvt->evt.gattc_evt.params.prim_srvc_disc_rsp.count; + for (int i = 0; i < count; i++) { + for (int j = 0; j < this->_numRemoteServices; j++) { + if ((bleEvt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i].uuid.type == this->_remoteServiceInfo[j].uuid.type) && + (bleEvt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i].uuid.uuid == this->_remoteServiceInfo[j].uuid.uuid)) { + this->_remoteServiceInfo[j].handlesRange = bleEvt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[i].handle_range; + break; + } + } + } + + uint16_t startHandle = bleEvt->evt.gattc_evt.params.prim_srvc_disc_rsp.services[count - 1].handle_range.end_handle + 1; + + sd_ble_gattc_primary_services_discover(this->_connectionHandle, startHandle, NULL); + } else { + // done discovering services + for (int i = 0; i < this->_numRemoteServices; i++) { + if (this->_remoteServiceInfo[i].handlesRange.start_handle != 0 && this->_remoteServiceInfo[i].handlesRange.end_handle != 0) { + this->_remoteServiceDiscoveryIndex = i; + + sd_ble_gattc_characteristics_discover(this->_connectionHandle, &this->_remoteServiceInfo[i].handlesRange); + break; + } + } + } + break; + + case BLE_GATTC_EVT_CHAR_DISC_RSP: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Char Disc Rsp 0x")); + Serial.println(bleEvt->evt.gattc_evt.gatt_status, HEX); +#endif + if (bleEvt->evt.gattc_evt.gatt_status == BLE_GATT_STATUS_SUCCESS) { + ble_gattc_handle_range_t serviceHandlesRange = this->_remoteServiceInfo[this->_remoteServiceDiscoveryIndex].handlesRange; + + uint16_t count = bleEvt->evt.gattc_evt.params.char_disc_rsp.count; + + for (int i = 0; i < count; i++) { + for (int j = 0; j < this->_numRemoteCharacteristics; j++) { + if ((this->_remoteServiceInfo[this->_remoteServiceDiscoveryIndex].service == this->_remoteCharacteristicInfo[j].service) && + (bleEvt->evt.gattc_evt.params.char_disc_rsp.chars[i].uuid.type == this->_remoteCharacteristicInfo[j].uuid.type) && + (bleEvt->evt.gattc_evt.params.char_disc_rsp.chars[i].uuid.uuid == this->_remoteCharacteristicInfo[j].uuid.uuid)) { + this->_remoteCharacteristicInfo[j].properties = bleEvt->evt.gattc_evt.params.char_disc_rsp.chars[i].char_props; + this->_remoteCharacteristicInfo[j].valueHandle = bleEvt->evt.gattc_evt.params.char_disc_rsp.chars[i].handle_value; + } + } + + serviceHandlesRange.start_handle = bleEvt->evt.gattc_evt.params.char_disc_rsp.chars[i].handle_value; + } + + sd_ble_gattc_characteristics_discover(this->_connectionHandle, &serviceHandlesRange); + } else { + bool discoverCharacteristics = false; + + for (int i = this->_remoteServiceDiscoveryIndex + 1; i < this->_numRemoteServices; i++) { + if (this->_remoteServiceInfo[i].handlesRange.start_handle != 0 && this->_remoteServiceInfo[i].handlesRange.end_handle != 0) { + this->_remoteServiceDiscoveryIndex = i; + + sd_ble_gattc_characteristics_discover(this->_connectionHandle, &this->_remoteServiceInfo[i].handlesRange); + discoverCharacteristics = true; + break; + } + } + + if (!discoverCharacteristics) { + if (this->_eventListener) { + this->_eventListener->BLEDeviceRemoteServicesDiscovered(*this); + } + } + } + break; + + case BLE_GATTC_EVT_READ_RSP: { +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Read Rsp 0x")); + Serial.println(bleEvt->evt.gattc_evt.gatt_status, HEX); + Serial.println(bleEvt->evt.gattc_evt.params.read_rsp.handle, DEC); + BLEUtil::printBuffer(&Serial,bleEvt->evt.gattc_evt.params.read_rsp.data, bleEvt->evt.gattc_evt.params.read_rsp.len); +#endif + this->_remoteRequestInProgress = false; + + if (bleEvt->evt.gattc_evt.gatt_status == BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION && + this->_bondStore) { + ble_gap_sec_params_t gapSecParams; + + memset(&gapSecParams, 0x00, sizeof(ble_gap_sec_params_t)); + +#if defined(NRF5) && !defined(S110) + gapSecParams.kdist_own.enc = 1; +#elif defined(NRF51_S130) + gapSecParams.kdist_periph.enc = 1; +#elif !defined(NRF5) + gapSecParams.timeout = 30; // must be 30s +#endif + gapSecParams.bond = true; + gapSecParams.mitm = false; + gapSecParams.io_caps = BLE_GAP_IO_CAPS_NONE; + gapSecParams.oob = false; + gapSecParams.min_key_size = 7; + gapSecParams.max_key_size = 16; + + sd_ble_gap_authenticate(this->_connectionHandle, &gapSecParams); + } else { + uint16_t handle = bleEvt->evt.gattc_evt.params.read_rsp.handle; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].valueHandle == handle) { + if (this->_eventListener) { + this->_eventListener->BLEDeviceRemoteCharacteristicValueChanged(*this, *this->_remoteCharacteristicInfo[i].characteristic, bleEvt->evt.gattc_evt.params.read_rsp.data, bleEvt->evt.gattc_evt.params.read_rsp. len); + } + break; + } + } + } + break; + } + + case BLE_GATTC_EVT_WRITE_RSP: +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Write Rsp 0x")); + Serial.println(bleEvt->evt.gattc_evt.gatt_status, HEX); + Serial.println(bleEvt->evt.gattc_evt.params.write_rsp.handle, DEC); +#endif + this->_remoteRequestInProgress = false; + + if (bleEvt->evt.gattc_evt.gatt_status == BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION && + this->_bondStore) { + ble_gap_sec_params_t gapSecParams; + + memset(&gapSecParams, 0x00, sizeof(ble_gap_sec_params_t)); + +#if defined(NRF5) && !defined(S110) + gapSecParams.kdist_own.enc = 1; +#elif defined(NRF51_S130) + gapSecParams.kdist_periph.enc = 1; +#elif !defined(NRF5) + gapSecParams.timeout = 30; // must be 30s +#endif + gapSecParams.bond = true; + gapSecParams.mitm = false; + gapSecParams.io_caps = BLE_GAP_IO_CAPS_NONE; + gapSecParams.oob = false; + gapSecParams.min_key_size = 7; + gapSecParams.max_key_size = 16; + + sd_ble_gap_authenticate(this->_connectionHandle, &gapSecParams); + } + break; + + case BLE_GATTC_EVT_HVX: { +#ifdef NRF_51822_DEBUG + Serial.print(F("Evt Hvx 0x")); + Serial.println(bleEvt->evt.gattc_evt.gatt_status, HEX); + Serial.println(bleEvt->evt.gattc_evt.params.hvx.handle, DEC); +#endif + uint16_t handle = bleEvt->evt.gattc_evt.params.hvx.handle; + + if (bleEvt->evt.gattc_evt.params.hvx.type == BLE_GATT_HVX_INDICATION) { + sd_ble_gattc_hv_confirm(this->_connectionHandle, handle); + } + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].valueHandle == handle) { + if (this->_eventListener) { + this->_eventListener->BLEDeviceRemoteCharacteristicValueChanged(*this, *this->_remoteCharacteristicInfo[i].characteristic, bleEvt->evt.gattc_evt.params.read_rsp.data, bleEvt->evt.gattc_evt.params.read_rsp. len); + } + break; + } + } + break; + } + + default: +#ifdef NRF_51822_DEBUG + Serial.print(F("bleEvt->header.evt_id = 0x")); + Serial.print(bleEvt->header.evt_id, HEX); + Serial.print(F(" ")); + Serial.println(bleEvt->header.evt_len); +#endif + break; + } + } + + // sd_app_evt_wait(); + return rtn; +} + +void nRF51822::end() { + //sd_softdevice_disable(); keep the LF clock running + + if (this->_remoteCharacteristicInfo) { + free(this->_remoteCharacteristicInfo); + } + + if (this->_remoteServiceInfo) { + free(this->_remoteServiceInfo); + } + + if (this->_localCharacteristicInfo) { + free(this->_localCharacteristicInfo); + } + + this->_numLocalCharacteristics = 0; + this->_numRemoteServices = 0; + this->_numRemoteCharacteristics = 0; + sd_ble_gap_adv_stop(); +} + +bool nRF51822::updateCharacteristicValue(BLECharacteristic& characteristic) { + bool success = true; + + for (int i = 0; i < this->_numLocalCharacteristics; i++) { + struct localCharacteristicInfo* localCharacteristicInfo = &this->_localCharacteristicInfo[i]; + + if (localCharacteristicInfo->characteristic == &characteristic) { + if (&characteristic == this->_broadcastCharacteristic) { + this->broadcastCharacteristic(characteristic); + } + + uint16_t valueLength = characteristic.valueLength(); + + sd_ble_gatts_value_set(localCharacteristicInfo->handles.value_handle, 0, &valueLength, characteristic.value()); + + ble_gatts_hvx_params_t hvxParams; + + memset(&hvxParams, 0, sizeof(hvxParams)); + + hvxParams.handle = localCharacteristicInfo->handles.value_handle; + hvxParams.offset = 0; + hvxParams.p_data = NULL; + hvxParams.p_len = &valueLength; + + if (localCharacteristicInfo->notifySubscribed) { + if (this->_txBufferCount > 0) { + this->_txBufferCount--; + + hvxParams.type = BLE_GATT_HVX_NOTIFICATION; + + if (sd_ble_gatts_hvx(this->_connectionHandle, &hvxParams) == NRF_SUCCESS) { + success = true; + } else { + success = false; + } + } else { + success = false; + } + } + + if (localCharacteristicInfo->indicateSubscribed) { + if (this->_txBufferCount > 0) { + this->_txBufferCount--; + + hvxParams.type = BLE_GATT_HVX_INDICATION; + + if (sd_ble_gatts_hvx(this->_connectionHandle, &hvxParams) == NRF_SUCCESS) { + success = true; + } else { + success = false; + } + } else { + success = false; + } + } + } + } + + return success; +} + +bool nRF51822::broadcastCharacteristic(BLECharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numLocalCharacteristics; i++) { + struct localCharacteristicInfo* localCharacteristicInfo = &this->_localCharacteristicInfo[i]; + + if (localCharacteristicInfo->characteristic == &characteristic) { + if (characteristic.properties() & BLEBroadcast && localCharacteristicInfo->service) { + unsigned char advData[31]; + unsigned char advDataLen = this->_advDataLen; + + // copy the existing advertisement data + memcpy(advData, this->_advData, advDataLen); + + advDataLen += (4 + characteristic.valueLength()); + + if (advDataLen <= 31) { + BLEUuid uuid = BLEUuid(localCharacteristicInfo->service->uuid()); + + advData[this->_advDataLen + 0] = 3 + characteristic.valueLength(); + advData[this->_advDataLen + 1] = 0x16; + + memcpy(&advData[this->_advDataLen + 2], uuid.data(), 2); + memcpy(&advData[this->_advDataLen + 4], characteristic.value(), characteristic.valueLength()); + + sd_ble_gap_adv_data_set(advData, advDataLen, NULL, 0); // update advertisement data + success = true; + + this->_broadcastCharacteristic = &characteristic; + } + } + break; + } + } + + return success; +} + +bool nRF51822::canNotifyCharacteristic(BLECharacteristic& /*characteristic*/) { + return (this->_txBufferCount > 0); +} + +bool nRF51822::canIndicateCharacteristic(BLECharacteristic& /*characteristic*/) { + return (this->_txBufferCount > 0); +} + +bool nRF51822::canReadRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + success = (this->_remoteCharacteristicInfo[i].valueHandle && + this->_remoteCharacteristicInfo[i].properties.read && + !this->_remoteRequestInProgress); + break; + } + } + + return success; +} + +bool nRF51822::readRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + if (this->_remoteCharacteristicInfo[i].valueHandle && this->_remoteCharacteristicInfo[i].properties.read) { + this->_remoteRequestInProgress = true; + success = (sd_ble_gattc_read(this->_connectionHandle, this->_remoteCharacteristicInfo[i].valueHandle, 0) == NRF_SUCCESS); + } + break; + } + } + + return success; +} + +bool nRF51822::canWriteRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + if (this->_remoteCharacteristicInfo[i].valueHandle) { + if (this->_remoteCharacteristicInfo[i].properties.write) { + success = !this->_remoteRequestInProgress; + } else if (this->_remoteCharacteristicInfo[i].properties.write_wo_resp) { + success = (this->_txBufferCount > 0); + } + } + break; + } + } + + return success; +} + +bool nRF51822::writeRemoteCharacteristic(BLERemoteCharacteristic& characteristic, const unsigned char value[], unsigned char length) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + if (this->_remoteCharacteristicInfo[i].valueHandle && + (this->_remoteCharacteristicInfo[i].properties.write_wo_resp || this->_remoteCharacteristicInfo[i].properties.write) && + (this->_txBufferCount > 0)) { + + ble_gattc_write_params_t writeParams; + + writeParams.write_op = (this->_remoteCharacteristicInfo[i].properties.write) ? BLE_GATT_OP_WRITE_REQ : BLE_GATT_OP_WRITE_CMD; +#ifndef __RFduino__ + writeParams.flags = 0; +#endif + writeParams.handle = this->_remoteCharacteristicInfo[i].valueHandle; + writeParams.offset = 0; + writeParams.len = length; + writeParams.p_value = (uint8_t*)value; + + this->_remoteRequestInProgress = true; + + this->_txBufferCount--; + + success = (sd_ble_gattc_write(this->_connectionHandle, &writeParams) == NRF_SUCCESS); + } + break; + } + } + + return success; +} + +bool nRF51822::canSubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + success = (this->_remoteCharacteristicInfo[i].valueHandle && + (this->_remoteCharacteristicInfo[i].properties.notify || this->_remoteCharacteristicInfo[i].properties.indicate)); + break; + } + } + + return success; +} + +bool nRF51822::subscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + if (this->_remoteCharacteristicInfo[i].valueHandle && + (this->_remoteCharacteristicInfo[i].properties.notify || this->_remoteCharacteristicInfo[i].properties.indicate)) { + + ble_gattc_write_params_t writeParams; + + uint16_t value = (this->_remoteCharacteristicInfo[i].properties.notify ? 0x0001 : 0x002); + + writeParams.write_op = BLE_GATT_OP_WRITE_REQ; +#ifndef __RFduino__ + writeParams.flags = 0; +#endif + writeParams.handle = (this->_remoteCharacteristicInfo[i].valueHandle + 1); // don't discover descriptors for now + writeParams.offset = 0; + writeParams.len = sizeof(value); + writeParams.p_value = (uint8_t*)&value; + + this->_remoteRequestInProgress = true; + + success = (sd_ble_gattc_write(this->_connectionHandle, &writeParams) == NRF_SUCCESS); + } + break; + } + } + + return success; +} + +bool nRF51822::canUnsubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + return this->canSubscribeRemoteCharacteristic(characteristic); +} + +bool nRF51822::unsubcribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic) { + bool success = false; + + for (int i = 0; i < this->_numRemoteCharacteristics; i++) { + if (this->_remoteCharacteristicInfo[i].characteristic == &characteristic) { + if (this->_remoteCharacteristicInfo[i].valueHandle && + (this->_remoteCharacteristicInfo[i].properties.notify || this->_remoteCharacteristicInfo[i].properties.indicate)) { + + ble_gattc_write_params_t writeParams; + + uint16_t value = 0x0000; + + writeParams.write_op = BLE_GATT_OP_WRITE_REQ; +#ifndef __RFduino__ + writeParams.flags = 0; +#endif + writeParams.handle = (this->_remoteCharacteristicInfo[i].valueHandle + 1); // don't discover descriptors for now + writeParams.offset = 0; + writeParams.len = sizeof(value); + writeParams.p_value = (uint8_t*)&value; + + this->_remoteRequestInProgress = true; + + success = (sd_ble_gattc_write(this->_connectionHandle, &writeParams) == NRF_SUCCESS); + } + break; + } + } + + return success; +} + +bool nRF51822::setTxPower(int txPower) { + if (txPower <= -40) { + txPower = -40; + } else if (txPower <= -30) { + txPower = -30; + } else if (txPower <= -20) { + txPower = -20; + } else if (txPower <= -16) { + txPower = -16; + } else if (txPower <= -12) { + txPower = -12; + } else if (txPower <= -8) { + txPower = -8; + } else if (txPower <= -4) { + txPower = -4; + } else if (txPower <= 0) { + txPower = 0; + } else { + txPower = 4; + } + + return (sd_ble_gap_tx_power_set(txPower) == NRF_SUCCESS); +} + +bool nRF51822::startAdvertising() { + + ble_gap_adv_params_t advertisingParameters; + + memset(&advertisingParameters, 0x00, sizeof(advertisingParameters)); + + advertisingParameters.type = this->_connectable ? BLE_GAP_ADV_TYPE_ADV_IND : ( this->_hasScanData ? BLE_GAP_ADV_TYPE_ADV_SCAN_IND : BLE_GAP_ADV_TYPE_ADV_NONCONN_IND ); + advertisingParameters.p_peer_addr = NULL; + advertisingParameters.fp = BLE_GAP_ADV_FP_ANY; + advertisingParameters.p_whitelist = NULL; + advertisingParameters.interval = (this->_advertisingInterval * 16) / 10; // advertising interval (in units of 0.625 ms) + advertisingParameters.timeout = (this->_advertisingTimeout); + +#ifdef NRF_51822_DEBUG + Serial.print(F("Start advertisement advertisingParameters.interval:")); Serial.print(advertisingParameters.interval); + Serial.println(); +#endif + + return (sd_ble_gap_adv_start(&advertisingParameters) == NRF_SUCCESS); +} + +void nRF51822::disconnect() { + sd_ble_gap_disconnect(this->_connectionHandle, BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION); +} + +void nRF51822::requestAddress() { + ble_gap_addr_t gapAddress; + + sd_ble_gap_address_get(&gapAddress); + + if (this->_eventListener) { + this->_eventListener->BLEDeviceAddressReceived(*this, gapAddress.addr); + } +} + +#ifdef __cplusplus +extern "C" { +#endif + +float getChipTemperature() { +#ifndef __RFduino__ + int32_t rawTemperature = getRawChipTemperature(); + float temperature = rawTemperature / 4.0; + return temperature; +#else + return 0.0; +#endif +} + +int32_t getRawChipTemperature() { +#ifndef __RFduino__ + int32_t rawTemperature = 0; + sd_temp_get(&rawTemperature); + return rawTemperature; +#else + return 0.0; +#endif +} + +#ifdef __cplusplus +} +#endif + + +void nRF51822::requestTemperature() { +#ifndef __RFduino__ + int32_t rawTemperature = 0; + + sd_temp_get(&rawTemperature); + + float temperature = rawTemperature / 4.0; + + if (this->_eventListener) { + this->_eventListener->BLEDeviceTemperatureReceived(*this, temperature); + } +#endif +} + +void nRF51822::requestBatteryLevel() { +} + +#endif diff --git a/cores/nRF5/nRF51822.h b/cores/nRF5/nRF51822.h new file mode 100644 index 00000000..e87f1e69 --- /dev/null +++ b/cores/nRF5/nRF51822.h @@ -0,0 +1,133 @@ +// Copyright (c) Sandeep Mistry. All rights reserved. +// Licensed under the MIT license. See LICENSE file in the project root for full license information. + +#ifndef _NRF_51822_H_ +#define _NRF_51822_H_ + +#if defined(__RFduino__) + #include + #include +#elif defined(NRF5) || defined(NRF51_S130) + #include + #include + #include +#elif defined(NRF52) && defined(S132) // ARDUINO_RBL_nRF52832 + #ifndef ARDUINO_RBL_nRF52832 + #define ARDUINO_RBL_nRF52832 + #endif + #define NRF5 + + #include + #include + #include +#else + #include + #include +#endif + +#include "BLEDevice.h" + +class nRF51822 : public BLEDevice +{ + friend class BLEPeripheral; + + protected: + struct localCharacteristicInfo { + BLECharacteristic* characteristic; + BLEService* service; + + ble_gatts_char_handles_t handles; + bool notifySubscribed; + bool indicateSubscribed; + }; + + struct remoteServiceInfo { + BLERemoteService* service; + + ble_uuid_t uuid; + ble_gattc_handle_range_t handlesRange; + }; + + struct remoteCharacteristicInfo { + BLERemoteCharacteristic* characteristic; + BLERemoteService* service; + + ble_uuid_t uuid; + ble_gatt_char_props_t properties; + uint16_t valueHandle; + }; + + nRF51822(); + + virtual ~nRF51822(); + + virtual void begin(unsigned char advertisementDataSize, + BLEEirData *advertisementData, + unsigned char scanDataSize, + BLEEirData *scanData, + BLELocalAttribute** localAttributes, + unsigned char numLocalAttributes, + BLERemoteAttribute** remoteAttributes, + unsigned char numRemoteAttributes); + + virtual bool poll(); + + virtual void end(); + + virtual bool setTxPower(int txPower); + bool startAdvertising(); + virtual void disconnect(); + virtual bool startScanning(ble_scan_response_handler_t); + virtual bool stopScanning(); + // update these while not scanning and then call startScanning() to apply them + virtual void setScanInterval(uint16_t interval, uint16_t window); // in units of 0.625 ms, default 160,40 i.e. 100ms,25ms + virtual void setActiveScan(bool enable); // Request scan response data, default is false + virtual void setScanTimeout(uint16_t timeout); // 0 = Don't stop scanning after n seconds + + virtual bool updateCharacteristicValue(BLECharacteristic& characteristic); + virtual bool broadcastCharacteristic(BLECharacteristic& characteristic); + virtual bool canNotifyCharacteristic(BLECharacteristic& characteristic); + virtual bool canIndicateCharacteristic(BLECharacteristic& characteristic); + + virtual bool canReadRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + virtual bool readRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + virtual bool canWriteRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + virtual bool writeRemoteCharacteristic(BLERemoteCharacteristic& characteristic, const unsigned char value[], unsigned char length); + virtual bool canSubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + virtual bool subscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + virtual bool canUnsubscribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + virtual bool unsubcribeRemoteCharacteristic(BLERemoteCharacteristic& characteristic); + + virtual void requestAddress(); + virtual void requestTemperature(); + virtual void requestBatteryLevel(); + + private: + + unsigned char _advData[31]; + unsigned char _advDataLen; + bool _hasScanData; + BLECharacteristic* _broadcastCharacteristic; + + uint16_t _connectionHandle; +#if defined(NRF5) || defined(NRF51_S130) + uint8_t _bondData[((sizeof(ble_gap_enc_key_t) + 3) / 4) * 4] __attribute__ ((__aligned__(4))); + ble_gap_enc_key_t* _encKey; +#else + uint8_t _authStatusBuffer[((sizeof(ble_gap_evt_auth_status_t) + 3) / 4) * 4] __attribute__ ((__aligned__(4))); + ble_gap_evt_auth_status_t* _authStatus; +#endif + unsigned char _txBufferCount; + + unsigned char _numLocalCharacteristics; + struct localCharacteristicInfo* _localCharacteristicInfo; + + unsigned char _numRemoteServices; + struct remoteServiceInfo* _remoteServiceInfo; + unsigned char _remoteServiceDiscoveryIndex; + unsigned char _numRemoteCharacteristics; + struct remoteCharacteristicInfo* _remoteCharacteristicInfo; + bool _remoteRequestInProgress; +}; + +#endif diff --git a/cores/nRF5/nRFChipInfo.c b/cores/nRF5/nRFChipInfo.c new file mode 100644 index 00000000..9efd6996 --- /dev/null +++ b/cores/nRF5/nRFChipInfo.c @@ -0,0 +1,61 @@ +#include +#include "nRFChipInfo.h" + +/******** EXAMPLE USAGE +#include + +void setup() { + // put your setup code here, to run once: + Serial.begin(115200); + for (int i=10; i>0; i--) { + Serial.print(i); Serial.print(' '); + delay(500); + } + Serial.println(); + Serial.print("Part: nRF"); Serial.println(nRF52PartNo(),HEX); + Serial.print("Variant: "); Serial.println((char*)nRF52Variant()); + Serial.print("Ram: "); Serial.print(nRF52RamKb()); Serial.println("Kb"); + Serial.print("Flash: "); Serial.print(nRF52FlashKb()); Serial.println("Kb"); + Serial.println("Setup finished"); + +} + +void loop() { + // nothing here +} +**********************/ + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t nRF52PartNo() { + return NRF_FICR->INFO.PART; +} + +static uint8_t variant[5]; // allow for null + +uint8_t* nRF52Variant() { + uint32_t info = NRF_FICR->INFO.VARIANT; + uint8_t *p = (uint8_t *)&info; + variant[0] = p[3]; + variant[1] = p[2]; + variant[2] = p[1]; + variant[3] = p[0]; + variant[4] = 0; + return variant; +} + +int nRF52FlashKb() { + uint32_t flash = NRF_FICR->INFO.FLASH; + return (int)flash; +} +int nRF52RamKb() { + uint32_t ram = NRF_FICR->INFO.RAM; + return (int)ram; +} + + +#ifdef __cplusplus +} +#endif diff --git a/cores/nRF5/nRFChipInfo.h b/cores/nRF5/nRFChipInfo.h new file mode 100644 index 00000000..6623f2cd --- /dev/null +++ b/cores/nRF5/nRFChipInfo.h @@ -0,0 +1,42 @@ +#ifndef _NRF_CHIP_INFO_H_ +#define _NRF_CHIP_INFO_H_ + +/******** EXAMPLE USAGE +#include + +void setup() { + // put your setup code here, to run once: + Serial.begin(115200); + for (int i=10; i>0; i--) { + Serial.print(i); Serial.print(' '); + delay(500); + } + Serial.println(); + Serial.print("Part: nRF"); Serial.println(nRF52PartNo(),HEX); + Serial.print("Variant: "); Serial.println((char*)nRF52Variant()); + Serial.print("Ram: "); Serial.print(nRF52RamKb()); Serial.println("Kb"); + Serial.print("Flash: "); Serial.print(nRF52FlashKb()); Serial.println("Kb"); + Serial.println("Setup finished"); + +} + +void loop() { + // nothing here +} +**********************/ + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t nRF52PartNo(void); +uint8_t* nRF52Variant(void); +int nRF52FlashKb(void); +int nRF52RamKb(void); + +#ifdef __cplusplus +} +#endif + +#endif // _NRF_CHIP_INFO_H_ + diff --git a/cores/nRF5/pulse.c b/cores/nRF5/pulse.c index 43b9d218..111279ac 100644 --- a/cores/nRF5/pulse.c +++ b/cores/nRF5/pulse.c @@ -16,10 +16,14 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define _REMOVED_CODE_ +#ifdef _REMOVED_CODE_ + #include "nrf.h" #include + // See pulse_asm.S extern unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, uint32_t stateMask, unsigned long maxloops); @@ -27,26 +31,29 @@ extern unsigned long countPulseASM(const volatile uint32_t *port, uint32_t bit, * or LOW, the type of pulse to measure. Works on pulses from 2-3 microseconds * to 3 minutes in length, but must be called at least a few dozen microseconds * before the start of the pulse. */ -uint32_t pulseIn(uint32_t ulPin, uint32_t state, uint32_t timeout) +uint32_t pulseIn(uint32_t pin, uint32_t state, uint32_t timeout) { // cache the port and bit of the pin in order to speed up the // pulse width measuring loop and achieve finer resolution. calling // digitalRead() instead yields much coarser resolution. // PinDescription p = g_APinDescription[pin]; - NRF_GPIO_Type* port = digitalPinToPort(ulPin); - uint32_t bit = digitalPinToBitMask(ulPin); + uint32_t bit = 1 << pin; //p.ulPin; uint32_t stateMask = state ? bit : 0; // convert the timeout from microseconds to a number of times through - // the initial loop; it takes (roughly) 10 clock cycles per iteration. - uint32_t maxloops = microsecondsToClockCycles(timeout) / 10; - - // count low-level loops during the pulse (or until maxLoops) - // a zero loopCount means that a complete pulse was not detected within the timeout - uint32_t loopCount = countPulseASM(&(port->IN), bit, stateMask, maxloops); - - // convert the reading to (approximate) microseconds. The loop time as measured with an - // oscilloscope is 10 cycles on a BBC micro:bit 1.3 (nRF51822). There is error because the - // time is quantized to an integral number of loops and because interrupt may steal cycles. - return clockCyclesToMicroseconds(10 * loopCount); + // the initial loop; it takes (roughly) 13 clock cycles per iteration. + uint32_t maxloops = microsecondsToClockCycles(timeout) / 13; + + uint32_t width = countPulseASM(&(NRF_GPIO->IN), bit, stateMask, maxloops); + + // convert the reading to microseconds. The loop has been determined + // to be 13 clock cycles long and have about 16 clocks between the edge + // and the start of the loop. There will be some error introduced by + // the interrupt handlers. + if (width) + return clockCyclesToMicroseconds(width * 13 + 16); + else + return 0; } + +#endif // #ifdef _REMOVED_CODE_ \ No newline at end of file diff --git a/cores/nRF5/utility/README.md b/cores/nRF5/utility/README.md new file mode 100644 index 00000000..a29df0a7 --- /dev/null +++ b/cores/nRF5/utility/README.md @@ -0,0 +1,5 @@ +These files are from the [@NordicSemiconductor](https://github.com/NordicSemiconductor)[ble-sdk-arduino](https://github.com/NordicSemiconductor/ble-sdk-arduino). + +Some file have been slightly modified. + +extra files added by Low Power nRF52 are from nRF5_SDK_12.3.0_d7731ad.zip Some files have been slightly modified \ No newline at end of file diff --git a/cores/nRF5/utility/aci.h b/cores/nRF5/utility/aci.h new file mode 100644 index 00000000..a00e7012 --- /dev/null +++ b/cores/nRF5/utility/aci.h @@ -0,0 +1,664 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @defgroup aci aci + * @{ + * @ingroup lib + * + * @brief Definitions for the ACI (Application Control Interface) + * @remarks + * + * Flow control from application mcu to nRF8001 + * + * Data flow control: + * The flow control is credit based and the credit is initally given using the "device started" event. + * A credit of more than 1 is given to the application mcu. + * These credits are used only after the "ACI Connected Event" is sent to the application mcu. + * + * every send_data that is used decrements the credit available by 1. This is to be tracked by the application mcu. + * When the credit available reaches 0, the application mcu shall not send any more send_data. + * Credit is returned using the "credit event", this returned credit can then be used to send more send_data. + * This flow control is not necessary and not available for Broadcast. + * The entire credit available with the external mcu expires when a "disconnected" event arrives. + * + * Command flow control: + * When a command is sent over the ACI, the next command shall not be sent until after a response + * for the command sent has arrived. + * + */ + +#ifndef ACI_H__ +#define ACI_H__ + +/** + * Define an _aci_packed_ macro we can use in structure and enumerated type + * declarations so that the types are sized consistently across different + * platforms. In particular Arduino platforms using the GCC compiler and the + * Nordic processors using the Keil compiler. + * + * It's really the GNU compiler platforms that need a special keyword to get + * tight packing of values. On GNU platforms we can use the keyword: + * __attribute__((__packed__)) + * The thing is that while this keyword does the right thing with old and new + * versions of the gcc (C) compiler it only works right with g++ (C++) compiler + * versions that are version 4 or newer. + */ +#ifdef __GNUC__ +# if __GNUC__ >= 4 +# define _aci_packed_ __attribute__((__packed__)) +# else +# error "older g++ versions don't handle packed attribute in typedefs" +# endif +#else +# define _aci_packed_ +#endif + +/* + * Define a macro that compares the size of the first parameter to the integer + * value of the second parameter. If they do not match, a compile time error + * for negative array size occurs (even gnu chokes on negative array size). + * + * This compare is done by creating a typedef for an array. No variables are + * created and no memory is consumed with this check. The created type is + * used for checking only and is not for use by any other code. The value + * of 10 in this macro is arbitrary, it just needs to be a value larger + * than one to result in a positive number for the array size. + */ +#define ACI_ASSERT_SIZE(x,y) typedef char x ## _assert_size_t[-1+10*(sizeof(x) == (y))] + +/** + * @def ACI_VERSION + * @brief Current ACI protocol version. 0 means a device that is not yet released. + * A numer greater than 0 refers to a specific ACI version documented and released. + * The ACI consists of the ACI commands, ACI events and error codes. + */ +#define ACI_VERSION (0x02) +/** + * @def BTLE_DEVICE_ADDRESS_SIZE + * @brief Size in bytes of a Bluetooth Address + */ +#define BTLE_DEVICE_ADDRESS_SIZE (6) +/** + * @def ACI_PACKET_MAX_LEN + * @brief Maximum length in bytes of a full ACI packet, including length prefix, opcode and payload + */ +#define ACI_PACKET_MAX_LEN (32) +/** + * @def ACI_ECHO_DATA_MAX_LEN + * @brief Maximum length in bytes of the echo data portion + */ +#define ACI_ECHO_DATA_MAX_LEN (ACI_PACKET_MAX_LEN - 3) +/** + * @def ACI_DEVICE_MAX_PIPES + * @brief Maximum number of ACI pipes + */ +#define ACI_DEVICE_MAX_PIPES (62) +/** + * @def ACI_PIPE_TX_DATA_MAX_LEN + * @brief Maximum length in bytes of a transmission data pipe packet + */ +#define ACI_PIPE_TX_DATA_MAX_LEN (20) +/** + * @def ACI_PIPE_RX_DATA_MAX_LEN + * @brief Maximum length in bytes of a reception data pipe packet + */ +#define ACI_PIPE_RX_DATA_MAX_LEN (22) +/** + * @def ACI_GAP_DEVNAME_MAX_LEN + * @brief Maximum length in bytes of the GAP device name + */ +#define ACI_GAP_DEVNAME_MAX_LEN (20) +/** + * @def ACI_AD_PACKET_MAX_LEN + * @brief Maximum length in bytes of an AD packet + */ +#define ACI_AD_PACKET_MAX_LEN (31) +/** + * @def ACI_AD_PACKET_MAX_USER_LEN + * @brief Maximum usable length in bytes of an AD packet + */ +#define ACI_AD_PACKET_MAX_USER_LEN (31 - 3) +/** + * @def ACI_PIPE_INVALID + * @brief Invalid pipe number + */ +#define ACI_PIPE_INVALID (0xFF) + +/** + * @enum aci_pipe_store_t + * @brief Storage type identifiers: local and remote + */ +typedef enum +{ + ACI_STORE_INVALID = 0x0, + ACI_STORE_LOCAL= 0x01, + ACI_STORE_REMOTE= 0x02 +} _aci_packed_ aci_pipe_store_t; + +/** + * @enum aci_pipe_type_t + * @brief Pipe types + */ +typedef enum +{ + ACI_TX_BROADCAST = 0x0001, + ACI_TX = 0x0002, + ACI_TX_ACK = 0x0004, + ACI_RX = 0x0008, + ACI_RX_ACK = 0x0010, + ACI_TX_REQ = 0x0020, + ACI_RX_REQ = 0x0040, + ACI_SET = 0x0080, + ACI_TX_SIGN = 0x0100, + ACI_RX_SIGN = 0x0200, + ACI_RX_ACK_AUTO = 0x0400 +} _aci_packed_ aci_pipe_type_t; + +ACI_ASSERT_SIZE(aci_pipe_type_t, 2); + +/** + * @enum aci_bd_addr_type_t + * @brief Bluetooth Address types + */ +typedef enum +{ + ACI_BD_ADDR_TYPE_INVALID = 0x00, + ACI_BD_ADDR_TYPE_PUBLIC = 0x01, + ACI_BD_ADDR_TYPE_RANDOM_STATIC = 0x02, + ACI_BD_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE = 0x03, + ACI_BD_ADDR_TYPE_RANDOM_PRIVATE_UNRESOLVABLE = 0x04 +} _aci_packed_ aci_bd_addr_type_t; + +/** + * @enum aci_device_output_power_t + * @brief Radio output power levels + */ +typedef enum +{ + ACI_DEVICE_OUTPUT_POWER_MINUS_18DBM = 0x00, /**< Output power set to -18dBm */ + ACI_DEVICE_OUTPUT_POWER_MINUS_12DBM = 0x01, /**< Output power set to -12dBm */ + ACI_DEVICE_OUTPUT_POWER_MINUS_6DBM = 0x02, /**< Output power set to -6dBm */ + ACI_DEVICE_OUTPUT_POWER_0DBM = 0x03 /**< Output power set to 0dBm - DEFAULT*/ +} _aci_packed_ aci_device_output_power_t; + +/** + * @enum aci_device_operation_mode_t + * @brief Device operation modes + */ +typedef enum +{ + ACI_DEVICE_INVALID =0x00, + ACI_DEVICE_TEST =0x01, + ACI_DEVICE_SETUP =0x02, + ACI_DEVICE_STANDBY =0x03, + ACI_DEVICE_SLEEP =0x04 +} _aci_packed_ aci_device_operation_mode_t; + +/** + * @enum aci_disconnect_reason_t + * @brief Reason enumeration for ACI_CMD_DISCONNECT + */ +typedef enum +{ + ACI_REASON_TERMINATE =0x01, /**< Use this to disconnect (does a terminate request), you need to wait for the "disconnected" event */ + ACI_REASON_BAD_TIMING =0x02 /* Opcode of the ACI command */ + union + { + aci_cmd_params_test_t test; + aci_cmd_params_echo_t echo; + aci_cmd_params_dtm_cmd_t dtm_cmd; + aci_cmd_params_setup_t setup; + aci_cmd_params_write_dynamic_data_t write_dynamic_data; + aci_cmd_params_set_local_data_t set_local_data; + aci_cmd_params_connect_t connect; + aci_cmd_params_bond_t bond; + aci_cmd_params_disconnect_t disconnect; + aci_cmd_params_set_tx_power_t set_tx_power; + aci_cmd_params_change_timing_t change_timing; + aci_cmd_params_open_remote_pipe_t open_remote_pipe; + aci_cmd_params_send_data_t send_data; + aci_cmd_params_send_data_ack_t send_data_ack; + aci_cmd_params_request_data_t request_data; + aci_cmd_params_send_data_nack_t send_data_nack; + aci_cmd_params_set_app_latency_t set_app_latency; + aci_cmd_params_set_key_t set_key; + aci_cmd_params_open_adv_pipe_t open_adv_pipe; + aci_cmd_params_broadcast_t broadcast; + aci_cmd_params_close_remote_pipe_t close_remote_pipe; + + } params; +} _aci_packed_ aci_cmd_t; + +#endif // ACI_CMDS_H__ + + diff --git a/cores/nRF5/utility/aci_evts.h b/cores/nRF5/utility/aci_evts.h new file mode 100644 index 00000000..f6da46a1 --- /dev/null +++ b/cores/nRF5/utility/aci_evts.h @@ -0,0 +1,397 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup aci + * + * @brief Definitions for the ACI (Application Control Interface) events + */ + +#ifndef ACI_EVTS_H__ +#define ACI_EVTS_H__ + +#include "aci.h" + +/** + * @enum aci_evt_opcode_t + * @brief ACI event opcodes + */ +typedef enum +{ + /** + * Invalid event code + */ + ACI_EVT_INVALID = 0x00, + /** + * Sent every time the device starts + */ + ACI_EVT_DEVICE_STARTED = 0x81, + /** + * Mirrors the ACI_CMD_ECHO + */ + ACI_EVT_ECHO = 0x82, + /** + * Asynchronous hardware error event + */ + ACI_EVT_HW_ERROR = 0x83, + /** + * Event opcode used as a event response for all commands + */ + ACI_EVT_CMD_RSP = 0x84, + /** + * Link connected + */ + ACI_EVT_CONNECTED = 0x85, + /** + * Link disconnected + */ + ACI_EVT_DISCONNECTED = 0x86, + /** + * Bond completion result + */ + ACI_EVT_BOND_STATUS = 0x87, + /** + * Pipe bitmap for available pipes + */ + ACI_EVT_PIPE_STATUS = 0x88, + /** + * Sent to the application when the radio enters a connected state + * or when the timing of the radio connection changes + */ + ACI_EVT_TIMING = 0x89, + /** + * Notification to the application that transmit credits are + * available + */ + ACI_EVT_DATA_CREDIT = 0x8A, + /** + * Data acknowledgement event + */ + ACI_EVT_DATA_ACK = 0x8B, + /** + * Data received notification event + */ + ACI_EVT_DATA_RECEIVED = 0x8C, + /** + * Error notification event + */ + ACI_EVT_PIPE_ERROR = 0x8D, + /** + * Display Passkey Event + */ + ACI_EVT_DISPLAY_PASSKEY = 0x8E, + /** + * Security Key request + */ + ACI_EVT_KEY_REQUEST = 0x8F + +} _aci_packed_ aci_evt_opcode_t; + +ACI_ASSERT_SIZE(aci_evt_opcode_t, 1); + +/** + * @struct aci_evt_params_device_started_t + * @brief Structure for the ACI_EVT_DEVICE_STARTED event return parameters + */ +typedef struct +{ + aci_device_operation_mode_t device_mode; /**< Mode in which the device is being started */ + aci_hw_error_t hw_error; /**< Hardware Error if available for the start */ + uint8_t credit_available; /**< Flow control credit available for this specific FW build */ +} _aci_packed_ aci_evt_params_device_started_t; + +ACI_ASSERT_SIZE(aci_evt_params_device_started_t, 3); + +/** + * @struct aci_evt_params_hw_error_t + * @brief Structure for the ACI_EVT_HW_ERROR event return parameters + */ +typedef struct +{ + uint16_t line_num; + uint8_t file_name[20]; +} _aci_packed_ aci_evt_params_hw_error_t; + +ACI_ASSERT_SIZE(aci_evt_params_hw_error_t, 22); + +/** + * @struct aci_evt_cmd_rsp_params_dtm_cmd_t + * @brief Structure for the ACI_EVT_CMD_RSP event with opcode=ACI_CMD_DTM_CMD event return parameters + */ +typedef struct +{ + uint8_t evt_msb; + uint8_t evt_lsb; +} _aci_packed_ aci_evt_cmd_rsp_params_dtm_cmd_t; + +/** + * @struct aci_evt_cmd_rsp_read_dynamic_data_t + * @brief Structure for the ACI_EVT_CMD_RSP event with opcode=ACI_CMD_READ_DYNAMIC_DATA event return parameters + * @note Dynamic data chunk size in this event is defined to go up to ACI_PACKET_MAX_LEN - 5 + */ +typedef struct +{ + uint8_t seq_no; + uint8_t dynamic_data[1]; +} _aci_packed_ aci_evt_cmd_rsp_read_dynamic_data_t; + +/** + * @struct aci_evt_cmd_rsp_params_get_device_version_t + * @brief Structure for the ACI_EVT_CMD_RSP event with opcode=ACI_CMD_GET_DEVICE_VERSION event return parameters + */ +typedef struct +{ + uint16_t configuration_id; + uint8_t aci_version; + uint8_t setup_format; + uint32_t setup_id; + uint8_t setup_status; +} _aci_packed_ aci_evt_cmd_rsp_params_get_device_version_t; + +ACI_ASSERT_SIZE(aci_evt_cmd_rsp_params_get_device_version_t, 9); + +/** + * @struct aci_evt_cmd_rsp_params_get_device_address_t + * @brief Structure for the ACI_EVT_CMD_RSP event with opcode=ACI_CMD_GET_DEVICE_ADDRESS event return parameters + */ +typedef struct +{ + uint8_t bd_addr_own[BTLE_DEVICE_ADDRESS_SIZE]; + aci_bd_addr_type_t bd_addr_type; +} _aci_packed_ aci_evt_cmd_rsp_params_get_device_address_t; + +ACI_ASSERT_SIZE(aci_evt_cmd_rsp_params_get_device_address_t, BTLE_DEVICE_ADDRESS_SIZE + 1); + +/** + * @struct aci_evt_cmd_rsp_params_get_battery_level_t + * @brief Structure for the ACI_EVT_CMD_RSP event with opcode=ACI_CMD_GET_BATTERY_LEVEL event return parameters + */ +typedef struct +{ + uint16_t battery_level; +} _aci_packed_ aci_evt_cmd_rsp_params_get_battery_level_t; + +/** + * @struct aci_evt_cmd_rsp_params_get_temperature_t + * @brief Structure for the ACI_EVT_CMD_RSP event with opcode=ACI_CMD_GET_TEMPERATURE event return parameters + */ +typedef struct +{ + int16_t temperature_value; +} _aci_packed_ aci_evt_cmd_rsp_params_get_temperature_t; + +/** + * @struct aci_evt_params_cmd_rsp_t + * @brief Structure for the ACI_EVT_CMD_RSP event return parameters + */ +typedef struct +{ + aci_cmd_opcode_t cmd_opcode; /**< Command opcode for which the event response is being sent */ + aci_status_code_t cmd_status; /**< Status of the command that was sent. Used in the context of the command. */ + union + { + aci_evt_cmd_rsp_params_dtm_cmd_t dtm_cmd; + aci_evt_cmd_rsp_read_dynamic_data_t read_dynamic_data; + aci_evt_cmd_rsp_params_get_device_version_t get_device_version; + aci_evt_cmd_rsp_params_get_device_address_t get_device_address; + aci_evt_cmd_rsp_params_get_battery_level_t get_battery_level; + aci_evt_cmd_rsp_params_get_temperature_t get_temperature; + uint8_t padding[29]; + } params; +} _aci_packed_ aci_evt_params_cmd_rsp_t; + +ACI_ASSERT_SIZE(aci_evt_params_cmd_rsp_t, 31); + +/** + * @struct aci_evt_params_connected_t + * @brief Structure for the ACI_EVT_CONNECTED event return parameters + */ +typedef struct +{ + aci_bd_addr_type_t dev_addr_type; + uint8_t dev_addr[BTLE_DEVICE_ADDRESS_SIZE]; + uint16_t conn_rf_interval; /**< rf_interval = conn_rf_interval * 1.25 ms Range:0x0006 to 0x0C80 */ + uint16_t conn_slave_rf_latency; /**< Number of RF events the slave can skip */ + uint16_t conn_rf_timeout; /**< Timeout as a multiple of 10ms i.e timeout = conn_rf_timeout * 10ms Range: 0x000A to 0x0C80 */ + aci_clock_accuracy_t master_clock_accuracy; /**< Clock accuracy of Bluetooth master: Enumerated list of values from 500 ppm to 20 ppm */ +} _aci_packed_ aci_evt_params_connected_t; + +ACI_ASSERT_SIZE(aci_evt_params_connected_t, 14); + +/** + * @struct aci_evt_params_disconnected_t + * @brief Structure for the ACI_EVT_DISCONNECTED event return parameters + */ +typedef struct +{ + aci_status_code_t aci_status; + uint8_t btle_status; +} _aci_packed_ aci_evt_params_disconnected_t; + +ACI_ASSERT_SIZE(aci_evt_params_disconnected_t, 2); + +/** + * @struct aci_evt_params_bond_status_t + * @brief Structure for the ACI_EVT_BOND_STATUS event return parameters + */ +typedef struct +{ + aci_bond_status_code_t status_code; + aci_bond_status_source_t status_source; + uint8_t secmode1_bitmap; + uint8_t secmode2_bitmap; + uint8_t keys_exchanged_slave; + uint8_t keys_exchanged_master; +} _aci_packed_ aci_evt_params_bond_status_t; + +ACI_ASSERT_SIZE(aci_evt_params_bond_status_t, 6); + +/** + * @struct aci_evt_params_pipe_status_t + * @brief Structure for the ACI_EVT_PIPE_STATUS event return parameters + */ +typedef struct +{ + uint8_t pipes_open_bitmap[8]; + uint8_t pipes_closed_bitmap[8]; +} _aci_packed_ aci_evt_params_pipe_status_t; + +ACI_ASSERT_SIZE(aci_evt_params_pipe_status_t, 16); + +/** + * @struct aci_evt_params_timing_t + * @brief Structure for the ACI_EVT_TIMING event return parameters + */ +typedef struct +{ + uint16_t conn_rf_interval; /**< rf_interval = conn_rf_interval * 1.25 ms Range:0x0006 to 0x0C80 */ + uint16_t conn_slave_rf_latency; /**< Number of RF events the slave can skip */ + uint16_t conn_rf_timeout; /**< Timeout as a multiple of 10ms i.e timeout = conn_rf_timeout * 10ms Range: 0x000A to 0x0C80 */ +} _aci_packed_ aci_evt_params_timing_t; + +ACI_ASSERT_SIZE(aci_evt_params_timing_t, 6); + +/** + * @struct aci_evt_params_data_credit_t + * @brief Structure for the ACI_EVT_DATA_CREDIT event return parameters + */ +typedef struct +{ + uint8_t credit; +} _aci_packed_ aci_evt_params_data_credit_t; + +/** + * @struct aci_evt_params_data_ack_t + * @brief Structure for the ACI_EVT_DATA_ACK event return parameters + */ +typedef struct +{ + uint8_t pipe_number; +} _aci_packed_ aci_evt_params_data_ack_t; + +/** + * @struct aci_evt_params_data_received_t + * @brief Structure for the ACI_EVT_DATA_RECEIVED event return parameters + */ +typedef struct +{ + aci_rx_data_t rx_data; +} _aci_packed_ aci_evt_params_data_received_t; + +typedef struct +{ + uint8_t content[1]; +} _aci_packed_ error_data_t; + +/** + * @struct aci_evt_params_pipe_error_t + * @brief Structure for the ACI_EVT_PIPE_ERROR event return parameters + */ +typedef struct +{ + uint8_t pipe_number; + uint8_t error_code; + union + { + error_data_t error_data; + } params; +} _aci_packed_ aci_evt_params_pipe_error_t; + +/** + * @struct aci_evt_params_display_passkey_t + * @brief Structure for the ACI_EVT_DISPLAY_PASSKEY event return parameters + */ +typedef struct +{ + uint8_t passkey[6]; +} _aci_packed_ aci_evt_params_display_passkey_t; + +/** + * @struct aci_evt_params_key_request_t + * @brief Structure for the ACI_EVT_KEY_REQUEST event return parameters + */ +typedef struct +{ + aci_key_type_t key_type; +} _aci_packed_ aci_evt_params_key_request_t; + +/** + * @struct aci_event_params_echo_t + * @brief Structure for the ACI_EVT_ECHO ACI event parameters + */ +typedef struct +{ + uint8_t echo_data[ACI_ECHO_DATA_MAX_LEN]; +} _aci_packed_ aci_evt_params_echo_t; + +/** + * @struct aci_evt_t + * @brief Encapsulates a generic ACI event + */ +typedef struct +{ + uint8_t len; + aci_evt_opcode_t evt_opcode; + union + { + aci_evt_params_device_started_t device_started; + aci_evt_params_echo_t echo; + aci_evt_params_hw_error_t hw_error; + aci_evt_params_cmd_rsp_t cmd_rsp; + aci_evt_params_connected_t connected; + aci_evt_params_disconnected_t disconnected; + aci_evt_params_bond_status_t bond_status; + aci_evt_params_pipe_status_t pipe_status; + aci_evt_params_timing_t timing; + aci_evt_params_data_credit_t data_credit; + aci_evt_params_data_ack_t data_ack; + aci_evt_params_data_received_t data_received; + aci_evt_params_pipe_error_t pipe_error; + aci_evt_params_display_passkey_t display_passkey; + aci_evt_params_key_request_t key_request; + } params; +} _aci_packed_ aci_evt_t; + +ACI_ASSERT_SIZE(aci_evt_t, 33); + +#endif // ACI_EVTS_H__ diff --git a/cores/nRF5/utility/aci_protocol_defines.h b/cores/nRF5/utility/aci_protocol_defines.h new file mode 100644 index 00000000..2db23199 --- /dev/null +++ b/cores/nRF5/utility/aci_protocol_defines.h @@ -0,0 +1,188 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * This file contents defines for the position of all the fields of ACI + * command or event messages + */ + +#ifndef ACI_OFFSET_H__ +#define ACI_OFFSET_H__ + + + #define OFFSET_ACI_LL_CONN_PARAMS_T_MIN_CONN_INTERVAL_LSB 0 + #define OFFSET_ACI_LL_CONN_PARAMS_T_MIN_CONN_INTERVAL_MSB 1 + #define OFFSET_ACI_LL_CONN_PARAMS_T_MAX_CONN_INTERVAL_LSB 2 + #define OFFSET_ACI_LL_CONN_PARAMS_T_MAX_CONN_INTERVAL_MSB 3 + #define OFFSET_ACI_LL_CONN_PARAMS_T_SLAVE_LATENCY_LSB 4 + #define OFFSET_ACI_LL_CONN_PARAMS_T_SLAVE_LATENCY_MSB 5 + #define OFFSET_ACI_LL_CONN_PARAMS_T_TIMEOUT_MULT_LSB 6 + #define OFFSET_ACI_LL_CONN_PARAMS_T_TIMEOUT_MULT_MSB 7 + #define OFFSET_ACI_TX_DATA_T_PIPE_NUMBER 0 + #define OFFSET_ACI_TX_DATA_T_ACI_DATA 1 + #define OFFSET_ACI_RX_DATA_T_PIPE_NUMBER 0 + #define OFFSET_ACI_RX_DATA_T_ACI_DATA 1 + #define OFFSET_ACI_CMD_PARAMS_TEST_T_TEST_MODE_CHANGE 0 + #define OFFSET_ACI_CMD_PARAMS_ECHO_T_ECHO_DATA 0 + #define OFFSET_ACI_CMD_PARAMS_DTM_CMD_T_CMD_MSB 0 + #define OFFSET_ACI_CMD_PARAMS_DTM_CMD_T_CMD_LSB 1 + #define OFFSET_ACI_CMD_PARAMS_SETUP_T_SETUP_DATA 0 + #define OFFSET_ACI_CMD_PARAMS_WRITE_DYNAMIC_DATA_T_SEQ_NO 0 + #define OFFSET_ACI_CMD_PARAMS_WRITE_DYNAMIC_DATA_T_DYNAMIC_DATA 1 + #define OFFSET_ACI_CMD_PARAMS_SET_LOCAL_DATA_T_TX_DATA 0 + #define OFFSET_ACI_CMD_PARAMS_CONNECT_T_TIMEOUT_LSB 0 + #define OFFSET_ACI_CMD_PARAMS_CONNECT_T_TIMEOUT_MSB 1 + #define OFFSET_ACI_CMD_PARAMS_CONNECT_T_ADV_INTERVAL_LSB 2 + #define OFFSET_ACI_CMD_PARAMS_CONNECT_T_ADV_INTERVAL_MSB 3 + #define OFFSET_ACI_CMD_PARAMS_BOND_T_TIMEOUT_LSB 0 + #define OFFSET_ACI_CMD_PARAMS_BOND_T_TIMEOUT_MSB 1 + #define OFFSET_ACI_CMD_PARAMS_BOND_T_ADV_INTERVAL_LSB 2 + #define OFFSET_ACI_CMD_PARAMS_BOND_T_ADV_INTERVAL_MSB 3 + #define OFFSET_ACI_CMD_PARAMS_DISCONNECT_T_REASON 0 + #define OFFSET_ACI_CMD_PARAMS_SET_TX_POWER_T_DEVICE_POWER 0 + #define OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS 0 + #define OFFSET_ACI_CMD_PARAMS_OPEN_REMOTE_PIPE_T_PIPE_NUMBER 0 + #define OFFSET_ACI_CMD_PARAMS_SEND_DATA_T_TX_DATA 0 + #define OFFSET_ACI_CMD_PARAMS_SEND_DATA_ACK_T_PIPE_NUMBER 0 + #define OFFSET_ACI_CMD_PARAMS_REQUEST_DATA_T_PIPE_NUMBER 0 + #define OFFSET_ACI_CMD_PARAMS_SEND_DATA_NACK_T_PIPE_NUMBER 0 + #define OFFSET_ACI_CMD_PARAMS_SEND_DATA_NACK_T_ERROR_CODE 1 + #define OFFSET_ACI_CMD_PARAMS_SET_APP_LATENCY_T_MODE 0 + #define OFFSET_ACI_CMD_PARAMS_SET_APP_LATENCY_T_LATENCY_LSB 1 + #define OFFSET_ACI_CMD_PARAMS_SET_APP_LATENCY_T_LATENCY_MSB 2 + #define OFFSET_ACI_CMD_PARAMS_SET_KEY_T_KEY_TYPE 0 + #define OFFSET_ACI_CMD_PARAMS_SET_KEY_T_PASSKEY 1 + #define OFFSET_ACI_CMD_PARAMS_SET_KEY_T_OOB_KEY 1 + #define OFFSET_ACI_CMD_PARAMS_OPEN_ADV_PIPE_T_PIPES 0 + #define OFFSET_ACI_CMD_PARAMS_BROADCAST_T_TIMEOUT_LSB 0 + #define OFFSET_ACI_CMD_PARAMS_BROADCAST_T_TIMEOUT_MSB 1 + #define OFFSET_ACI_CMD_PARAMS_BROADCAST_T_ADV_INTERVAL_LSB 2 + #define OFFSET_ACI_CMD_PARAMS_BROADCAST_T_ADV_INTERVAL_MSB 3 + #define OFFSET_ACI_CMD_PARAMS_CLOSE_REMOTE_PIPE_T_PIPE_NUMBER 0 + #define OFFSET_ACI_CMD_T_LEN 0 + #define OFFSET_ACI_CMD_T_CMD_OPCODE 1 + #define OFFSET_ACI_CMD_T_TEST 2 + #define OFFSET_ACI_CMD_T_ECHO 2 + #define OFFSET_ACI_CMD_T_DTM_CMD 2 + #define OFFSET_ACI_CMD_T_SETUP 2 + #define OFFSET_ACI_CMD_T_WRITE_DYNAMIC_DATA 2 + #define OFFSET_ACI_CMD_T_SET_LOCAL_DATA 2 + #define OFFSET_ACI_CMD_T_CONNECT 2 + #define OFFSET_ACI_CMD_T_BOND 2 + #define OFFSET_ACI_CMD_T_DISCONNECT 2 + #define OFFSET_ACI_CMD_T_SET_TX_POWER 2 + #define OFFSET_ACI_CMD_T_CHANGE_TIMING 2 + #define OFFSET_ACI_CMD_T_OPEN_REMOTE_PIPE 2 + #define OFFSET_ACI_CMD_T_SEND_DATA 2 + #define OFFSET_ACI_CMD_T_SEND_DATA_ACK 2 + #define OFFSET_ACI_CMD_T_REQUEST_DATA 2 + #define OFFSET_ACI_CMD_T_SEND_DATA_NACK 2 + #define OFFSET_ACI_CMD_T_SET_APP_LATENCY 2 + #define OFFSET_ACI_CMD_T_SET_KEY 2 + #define OFFSET_ACI_CMD_T_OPEN_ADV_PIPE 2 + #define OFFSET_ACI_CMD_T_BROADCAST 2 + #define OFFSET_ACI_CMD_T_CLOSE_REMOTE_PIPE 2 + #define OFFSET_ACI_EVT_PARAMS_DEVICE_STARTED_T_DEVICE_MODE 0 + #define OFFSET_ACI_EVT_PARAMS_DEVICE_STARTED_T_HW_ERROR 1 + #define OFFSET_ACI_EVT_PARAMS_DEVICE_STARTED_T_CREDIT_AVAILABLE 2 + #define OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_LINE_NUM_LSB 0 + #define OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_LINE_NUM_MSB 1 + #define OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_FILE_NAME 2 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_DTM_CMD_T_EVT_MSB 0 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_DTM_CMD_T_EVT_LSB 1 + #define OFFSET_ACI_EVT_CMD_RSP_READ_DYNAMIC_DATA_T_SEQ_NO 0 + #define OFFSET_ACI_EVT_CMD_RSP_READ_DYNAMIC_DATA_T_DYNAMIC_DATA 1 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_CONFIGURATION_ID_LSB 0 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_CONFIGURATION_ID_MSB 1 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_ACI_VERSION 2 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_FORMAT 3 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_LSB0 4 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_LSB1 5 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_MSB0 6 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_MSB1 7 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_STATUS 8 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_ADDRESS_T_BD_ADDR_OWN 0 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_ADDRESS_T_BD_ADDR_TYPE 6 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_BATTERY_LEVEL_T_BATTERY_LEVEL_LSB 0 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_BATTERY_LEVEL_T_BATTERY_LEVEL_MSB 1 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_TEMPERATURE_T_TEMPERATURE_VALUE_LSB 0 + #define OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_TEMPERATURE_T_TEMPERATURE_VALUE_MSB 1 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_CMD_OPCODE 0 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_CMD_STATUS 1 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_DTM_CMD 2 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_READ_DYNAMIC_DATA 2 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION 2 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_ADDRESS 2 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_BATTERY_LEVEL 2 + #define OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_TEMPERATURE 2 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_DEV_ADDR_TYPE 0 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_DEV_ADDR 1 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_INTERVAL_LSB 7 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_INTERVAL_MSB 8 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_SLAVE_RF_LATENCY_LSB 9 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_SLAVE_RF_LATENCY_MSB 10 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_TIMEOUT_LSB 11 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_TIMEOUT_MSB 12 + #define OFFSET_ACI_EVT_PARAMS_CONNECTED_T_MASTER_CLOCK_ACCURACY 13 + #define OFFSET_ACI_EVT_PARAMS_DISCONNECTED_T_ACI_STATUS 0 + #define OFFSET_ACI_EVT_PARAMS_DISCONNECTED_T_BTLE_STATUS 1 + #define OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_STATUS_CODE 0 + #define OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_STATUS_SOURCE 1 + #define OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_SECMODE1_BITMAP 2 + #define OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_SECMODE2_BITMAP 3 + #define OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_KEYS_EXCHANGED_SLAVE 4 + #define OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_KEYS_EXCHANGED_MASTER 5 + #define OFFSET_ACI_EVT_PARAMS_PIPE_STATUS_T_PIPES_OPEN_BITMAP 0 + #define OFFSET_ACI_EVT_PARAMS_PIPE_STATUS_T_PIPES_CLOSED_BITMAP 8 + #define OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_INTERVAL_LSB 0 + #define OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_INTERVAL_MSB 1 + #define OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_SLAVE_RF_LATENCY_LSB 2 + #define OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_SLAVE_RF_LATENCY_MSB 3 + #define OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_TIMEOUT_LSB 4 + #define OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_TIMEOUT_MSB 5 + #define OFFSET_ACI_EVT_PARAMS_DATA_CREDIT_T_CREDIT 0 + #define OFFSET_ACI_EVT_PARAMS_DATA_ACK_T_PIPE_NUMBER 0 + #define OFFSET_ACI_EVT_PARAMS_DATA_RECEIVED_T_RX_DATA 0 + #define OFFSET_ERROR_DATA_T_CONTENT 0 + #define OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_PIPE_NUMBER 0 + #define OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_ERROR_CODE 1 + #define OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_ERROR_DATA 2 + #define OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY 0 + #define OFFSET_ACI_EVT_PARAMS_KEY_REQUEST_T_KEY_TYPE 0 + #define OFFSET_ACI_EVT_T_LEN 0 + #define OFFSET_ACI_EVT_T_EVT_OPCODE 1 + #define OFFSET_ACI_EVT_T_DEVICE_STARTED 2 + #define OFFSET_ACI_EVT_T_HW_ERROR 2 + #define OFFSET_ACI_EVT_T_CMD_RSP 2 + #define OFFSET_ACI_EVT_T_CONNECTED 2 + #define OFFSET_ACI_EVT_T_DISCONNECTED 2 + #define OFFSET_ACI_EVT_T_BOND_STATUS 2 + #define OFFSET_ACI_EVT_T_PIPE_STATUS 2 + #define OFFSET_ACI_EVT_T_TIMING 2 + #define OFFSET_ACI_EVT_T_DATA_CREDIT 2 + #define OFFSET_ACI_EVT_T_DATA_ACK 2 + #define OFFSET_ACI_EVT_T_DATA_RECEIVED 2 + #define OFFSET_ACI_EVT_T_PIPE_ERROR 2 + #define OFFSET_ACI_EVT_T_DISPLAY_PASSKEY 2 + #define OFFSET_ACI_EVT_T_KEY_REQUEST 2 + +#endif //ACI_OFFSET_H__ + diff --git a/cores/nRF5/utility/aci_queue.cpp b/cores/nRF5/utility/aci_queue.cpp new file mode 100644 index 00000000..e1608dab --- /dev/null +++ b/cores/nRF5/utility/aci_queue.cpp @@ -0,0 +1,207 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /** @file +@brief Implementation of a circular queue for ACI data +*/ + +#if !defined(NRF51) && !defined(NRF52) &&!defined(__RFduino__) + +#include "hal_aci_tl.h" +#include "aci_queue.h" +#include "ble_assert.h" + +void aci_queue_init(aci_queue_t *aci_q) +{ + uint8_t loop; + + ble_assert(NULL != aci_q); + + aci_q->head = 0; + aci_q->tail = 0; + for(loop=0; loopaci_data[loop].buffer[0] = 0x00; + aci_q->aci_data[loop].buffer[1] = 0x00; + } +} + +bool aci_queue_dequeue(aci_queue_t *aci_q, hal_aci_data_t *p_data) +{ + ble_assert(NULL != aci_q); + ble_assert(NULL != p_data); + + if (aci_queue_is_empty(aci_q)) + { + return false; + } + + memcpy((uint8_t *)p_data, (uint8_t *)&(aci_q->aci_data[aci_q->head % ACI_QUEUE_SIZE]), sizeof(hal_aci_data_t)); + ++aci_q->head; + + return true; +} + +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_dequeue_from_isr(aci_queue_t *aci_q, hal_aci_data_t *p_data) +{ + ble_assert(NULL != aci_q); + ble_assert(NULL != p_data); + + if (aci_queue_is_empty_from_isr(aci_q)) + { + return false; + } + + memcpy((uint8_t *)p_data, (uint8_t *)&(aci_q->aci_data[aci_q->head % ACI_QUEUE_SIZE]), sizeof(hal_aci_data_t)); + ++aci_q->head; + + return true; +} +#endif + +bool aci_queue_enqueue(aci_queue_t *aci_q, hal_aci_data_t *p_data) +{ + const uint8_t length = p_data->buffer[0]; + + ble_assert(NULL != aci_q); + ble_assert(NULL != p_data); + + if (aci_queue_is_full(aci_q)) + { + return false; + } + + aci_q->aci_data[aci_q->tail % ACI_QUEUE_SIZE].status_byte = 0; + memcpy((uint8_t *)&(aci_q->aci_data[aci_q->tail % ACI_QUEUE_SIZE].buffer[0]), (uint8_t *)&p_data->buffer[0], length + 1); + ++aci_q->tail; + + return true; +} + +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_enqueue_from_isr(aci_queue_t *aci_q, hal_aci_data_t *p_data) +{ + const uint8_t length = p_data->buffer[0]; + + ble_assert(NULL != aci_q); + ble_assert(NULL != p_data); + + if (aci_queue_is_full_from_isr(aci_q)) + { + return false; + } + + aci_q->aci_data[aci_q->tail % ACI_QUEUE_SIZE].status_byte = 0; + memcpy((uint8_t *)&(aci_q->aci_data[aci_q->tail % ACI_QUEUE_SIZE].buffer[0]), (uint8_t *)&p_data->buffer[0], length + 1); + ++aci_q->tail; + + return true; +} +#endif + +bool aci_queue_is_empty(aci_queue_t *aci_q) +{ + bool state = false; + + ble_assert(NULL != aci_q); + +#ifdef HAL_ACI_TL_INTERRUPT + //Critical section + noInterrupts(); +#endif + if (aci_q->head == aci_q->tail) + { + state = true; + } +#ifdef HAL_ACI_TL_INTERRUPT + interrupts(); +#endif + + return state; +} + +bool aci_queue_is_empty_from_isr(aci_queue_t *aci_q) +{ + ble_assert(NULL != aci_q); + + return aci_q->head == aci_q->tail; +} + +bool aci_queue_is_full(aci_queue_t *aci_q) +{ + bool state; + + ble_assert(NULL != aci_q); + +#ifdef HAL_ACI_TL_INTERRUPT + //This should be done in a critical section + noInterrupts(); +#endif + + state = (aci_q->tail == aci_q->head + ACI_QUEUE_SIZE); + +#ifdef HAL_ACI_TL_INTERRUPT + interrupts(); + //end +#endif + + return state; +} + +bool aci_queue_is_full_from_isr(aci_queue_t *aci_q) +{ + ble_assert(NULL != aci_q); + + return (aci_q->tail == aci_q->head + ACI_QUEUE_SIZE); +} + +bool aci_queue_peek(aci_queue_t *aci_q, hal_aci_data_t *p_data) +{ + ble_assert(NULL != aci_q); + ble_assert(NULL != p_data); + + if (aci_queue_is_empty(aci_q)) + { + return false; + } + + memcpy((uint8_t *)p_data, (uint8_t *)&(aci_q->aci_data[aci_q->head % ACI_QUEUE_SIZE]), sizeof(hal_aci_data_t)); + + return true; +} + +bool aci_queue_peek_from_isr(aci_queue_t *aci_q, hal_aci_data_t *p_data) +{ + ble_assert(NULL != aci_q); + ble_assert(NULL != p_data); + + if (aci_queue_is_empty_from_isr(aci_q)) + { + return false; + } + + memcpy((uint8_t *)p_data, (uint8_t *)&(aci_q->aci_data[aci_q->head % ACI_QUEUE_SIZE]), sizeof(hal_aci_data_t)); + + return true; +} + +#endif diff --git a/cores/nRF5/utility/aci_queue.h b/cores/nRF5/utility/aci_queue.h new file mode 100644 index 00000000..e0e30cae --- /dev/null +++ b/cores/nRF5/utility/aci_queue.h @@ -0,0 +1,86 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** @file + * @brief Interface for buffer. + */ + +/** @defgroup aci_queue aci_queue +@{ +@ingroup aci_queue + +*/ + +#ifndef ACI_QUEUE_H__ +#define ACI_QUEUE_H__ + +#include "aci.h" +#include "hal_aci_tl.h" + +/*********************************************************************** */ +/* The ACI_QUEUE_SIZE determines the memory usage of the system. */ +/* Successfully tested to a ACI_QUEUE_SIZE of 4 (interrupt) and 4 (polling) */ +/*********************************************************************** */ +#define ACI_QUEUE_SIZE 4 + +/** Data type for queue of data packets to send/receive from radio. + * + * A FIFO queue is maintained for packets. New packets are added (enqueued) + * at the tail and taken (dequeued) from the head. The head variable is the + * index of the next packet to dequeue while the tail variable is the index of + * where the next packet should be queued. + */ + +typedef struct { + hal_aci_data_t aci_data[ACI_QUEUE_SIZE]; + uint8_t head; + uint8_t tail; +} aci_queue_t; + +void aci_queue_init(aci_queue_t *aci_q); + +bool aci_queue_dequeue(aci_queue_t *aci_q, hal_aci_data_t *p_data); +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_dequeue_from_isr(aci_queue_t *aci_q, hal_aci_data_t *p_data); +#endif + +bool aci_queue_enqueue(aci_queue_t *aci_q, hal_aci_data_t *p_data); +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_enqueue_from_isr(aci_queue_t *aci_q, hal_aci_data_t *p_data); +#endif + +bool aci_queue_is_empty(aci_queue_t *aci_q); +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_is_empty_from_isr(aci_queue_t *aci_q); +#endif + +bool aci_queue_is_full(aci_queue_t *aci_q); +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_is_full_from_isr(aci_queue_t *aci_q); +#endif + +bool aci_queue_peek(aci_queue_t *aci_q, hal_aci_data_t *p_data); +#ifdef HAL_ACI_TL_INTERRUPT +bool aci_queue_peek_from_isr(aci_queue_t *aci_q, hal_aci_data_t *p_data); +#endif + +#endif /* ACI_QUEUE_H__ */ +/** @} */ diff --git a/cores/nRF5/utility/acilib.cpp b/cores/nRF5/utility/acilib.cpp new file mode 100644 index 00000000..4e26ef23 --- /dev/null +++ b/cores/nRF5/utility/acilib.cpp @@ -0,0 +1,616 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup group_acilib + * + * @brief Implementation of the acilib module. + */ + +#if !defined(NRF51) && !defined(NRF52) &&!defined(__RFduino__) + +#include "hal_platform.h" +#include "aci.h" +#include "aci_cmds.h" +#include "aci_evts.h" +#include "acilib.h" +#include "aci_protocol_defines.h" +#include "acilib_defs.h" +#include "acilib_if.h" +#include "acilib_types.h" + + +void acil_encode_cmd_set_test_mode(uint8_t *buffer, aci_cmd_params_test_t *p_aci_cmd_params_test) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 2; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_TEST; + *(buffer + OFFSET_ACI_CMD_T_TEST + OFFSET_ACI_CMD_PARAMS_TEST_T_TEST_MODE_CHANGE) = p_aci_cmd_params_test->test_mode_change; +} + +void acil_encode_cmd_sleep(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 1; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SLEEP; +} + +void acil_encode_cmd_get_device_version(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 1; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_GET_DEVICE_VERSION; +} + +void acil_encode_cmd_set_local_data(uint8_t *buffer, aci_cmd_params_set_local_data_t *p_aci_cmd_params_set_local_data, uint8_t data_size) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_SET_LOCAL_DATA_BASE_LEN + data_size; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SET_LOCAL_DATA; + *(buffer + OFFSET_ACI_CMD_T_SET_LOCAL_DATA + OFFSET_ACI_CMD_PARAMS_SEND_DATA_T_TX_DATA + OFFSET_ACI_TX_DATA_T_PIPE_NUMBER) = p_aci_cmd_params_set_local_data->tx_data.pipe_number; + memcpy(buffer + OFFSET_ACI_CMD_T_SET_LOCAL_DATA + OFFSET_ACI_CMD_PARAMS_SEND_DATA_T_TX_DATA + OFFSET_ACI_TX_DATA_T_ACI_DATA, &(p_aci_cmd_params_set_local_data->tx_data.aci_data[0]), data_size); +} + +void acil_encode_cmd_connect(uint8_t *buffer, aci_cmd_params_connect_t *p_aci_cmd_params_connect) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_CONNECT_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_CONNECT; + *(buffer + OFFSET_ACI_CMD_T_CONNECT + OFFSET_ACI_CMD_PARAMS_CONNECT_T_TIMEOUT_MSB) = (uint8_t)(p_aci_cmd_params_connect->timeout >> 8); + *(buffer + OFFSET_ACI_CMD_T_CONNECT + OFFSET_ACI_CMD_PARAMS_CONNECT_T_TIMEOUT_LSB) = (uint8_t)(p_aci_cmd_params_connect->timeout); + *(buffer + OFFSET_ACI_CMD_T_CONNECT + OFFSET_ACI_CMD_PARAMS_CONNECT_T_ADV_INTERVAL_MSB) = (uint8_t)(p_aci_cmd_params_connect->adv_interval >> 8); + *(buffer + OFFSET_ACI_CMD_T_CONNECT + OFFSET_ACI_CMD_PARAMS_CONNECT_T_ADV_INTERVAL_LSB) = (uint8_t)(p_aci_cmd_params_connect->adv_interval); +} + +void acil_encode_cmd_bond(uint8_t *buffer, aci_cmd_params_bond_t *p_aci_cmd_params_bond) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_BOND_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_BOND; + *(buffer + OFFSET_ACI_CMD_T_BOND + OFFSET_ACI_CMD_PARAMS_BOND_T_TIMEOUT_MSB) = (uint8_t)(p_aci_cmd_params_bond->timeout >> 8); + *(buffer + OFFSET_ACI_CMD_T_BOND + OFFSET_ACI_CMD_PARAMS_BOND_T_TIMEOUT_LSB) = (uint8_t)(p_aci_cmd_params_bond->timeout); + *(buffer + OFFSET_ACI_CMD_T_BOND + OFFSET_ACI_CMD_PARAMS_BOND_T_ADV_INTERVAL_MSB) = (uint8_t)(p_aci_cmd_params_bond->adv_interval >> 8); + *(buffer + OFFSET_ACI_CMD_T_BOND + OFFSET_ACI_CMD_PARAMS_BOND_T_ADV_INTERVAL_LSB) = (uint8_t)(p_aci_cmd_params_bond->adv_interval); +} + +void acil_encode_cmd_disconnect(uint8_t *buffer, aci_cmd_params_disconnect_t *p_aci_cmd_params_disconnect) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_DISCONNECT_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_DISCONNECT; + *(buffer + OFFSET_ACI_CMD_T_DISCONNECT + OFFSET_ACI_CMD_PARAMS_DISCONNECT_T_REASON) = (uint8_t)(p_aci_cmd_params_disconnect->reason); +} + +void acil_encode_baseband_reset(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_BASEBAND_RESET_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_RADIO_RESET; +} + +void acil_encode_direct_connect(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_DIRECT_CONNECT_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_CONNECT_DIRECT; +} + +void acil_encode_cmd_wakeup(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_WAKEUP_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_WAKEUP; +} + +void acil_encode_cmd_set_radio_tx_power(uint8_t *buffer, aci_cmd_params_set_tx_power_t *p_aci_cmd_params_set_tx_power) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_SET_RADIO_TX_POWER_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SET_TX_POWER; + *(buffer + OFFSET_ACI_CMD_T_SET_TX_POWER + OFFSET_ACI_CMD_PARAMS_SET_TX_POWER_T_DEVICE_POWER) = (uint8_t)p_aci_cmd_params_set_tx_power->device_power; +} + +void acil_encode_cmd_get_address(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_GET_DEVICE_ADDR_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_GET_DEVICE_ADDRESS; +} + +void acil_encode_cmd_send_data(uint8_t *buffer, aci_cmd_params_send_data_t *p_aci_cmd_params_send_data_t, uint8_t data_size) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_SEND_DATA_BASE_LEN + data_size; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SEND_DATA; + *(buffer + OFFSET_ACI_CMD_T_SEND_DATA + OFFSET_ACI_CMD_PARAMS_SEND_DATA_T_TX_DATA + OFFSET_ACI_TX_DATA_T_PIPE_NUMBER) = p_aci_cmd_params_send_data_t->tx_data.pipe_number; + memcpy((buffer + OFFSET_ACI_CMD_T_SEND_DATA + OFFSET_ACI_CMD_PARAMS_SEND_DATA_T_TX_DATA + OFFSET_ACI_TX_DATA_T_ACI_DATA), &(p_aci_cmd_params_send_data_t->tx_data.aci_data[0]), data_size); +} + +void acil_encode_cmd_request_data(uint8_t *buffer, aci_cmd_params_request_data_t *p_aci_cmd_params_request_data) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_DATA_REQUEST_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_REQUEST_DATA; + *(buffer + OFFSET_ACI_CMD_T_REQUEST_DATA + OFFSET_ACI_CMD_PARAMS_REQUEST_DATA_T_PIPE_NUMBER) = p_aci_cmd_params_request_data->pipe_number; +} + +void acil_encode_cmd_open_remote_pipe(uint8_t *buffer, aci_cmd_params_open_remote_pipe_t *p_aci_cmd_params_open_remote_pipe) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_OPEN_REMOTE_PIPE_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_OPEN_REMOTE_PIPE; + *(buffer + OFFSET_ACI_CMD_T_OPEN_REMOTE_PIPE + OFFSET_ACI_CMD_PARAMS_OPEN_REMOTE_PIPE_T_PIPE_NUMBER) = p_aci_cmd_params_open_remote_pipe->pipe_number; +} + +void acil_encode_cmd_close_remote_pipe(uint8_t *buffer, aci_cmd_params_close_remote_pipe_t *p_aci_cmd_params_close_remote_pipe) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_CLOSE_REMOTE_PIPE_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_CLOSE_REMOTE_PIPE; + *(buffer + OFFSET_ACI_CMD_T_CLOSE_REMOTE_PIPE + OFFSET_ACI_CMD_PARAMS_CLOSE_REMOTE_PIPE_T_PIPE_NUMBER) = p_aci_cmd_params_close_remote_pipe->pipe_number; +} + +void acil_encode_cmd_echo_msg(uint8_t *buffer, aci_cmd_params_echo_t *p_cmd_params_echo, uint8_t msg_size) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_ECHO_MSG_CMD_BASE_LEN + msg_size; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_ECHO; + memcpy((buffer + OFFSET_ACI_CMD_T_ECHO + OFFSET_ACI_CMD_PARAMS_ECHO_T_ECHO_DATA), &(p_cmd_params_echo->echo_data[0]), msg_size); +} + +void acil_encode_cmd_battery_level(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 1; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_GET_BATTERY_LEVEL; +} + +void acil_encode_cmd_temparature(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 1; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_GET_TEMPERATURE; +} + +void acil_encode_cmd_read_dynamic_data(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 1; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_READ_DYNAMIC_DATA; +} + +void acil_encode_cmd_write_dynamic_data(uint8_t *buffer, uint8_t seq_no, uint8_t* dynamic_data, uint8_t dynamic_data_size) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_WRITE_DYNAMIC_DATA_BASE_LEN + dynamic_data_size; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_WRITE_DYNAMIC_DATA; + *(buffer + OFFSET_ACI_CMD_T_WRITE_DYNAMIC_DATA + OFFSET_ACI_CMD_PARAMS_WRITE_DYNAMIC_DATA_T_SEQ_NO) = seq_no; + memcpy((buffer + OFFSET_ACI_CMD_T_WRITE_DYNAMIC_DATA + OFFSET_ACI_CMD_PARAMS_WRITE_DYNAMIC_DATA_T_DYNAMIC_DATA), dynamic_data, dynamic_data_size); +} + +void acil_encode_cmd_change_timing_req(uint8_t *buffer, aci_cmd_params_change_timing_t *p_aci_cmd_params_change_timing) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_CHANGE_TIMING_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_CHANGE_TIMING; + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_MIN_CONN_INTERVAL_MSB) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.min_conn_interval >> 8); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_MIN_CONN_INTERVAL_LSB) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.min_conn_interval); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_MAX_CONN_INTERVAL_MSB) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.max_conn_interval >> 8); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_MAX_CONN_INTERVAL_LSB) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.max_conn_interval); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_SLAVE_LATENCY_MSB ) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.slave_latency >> 8); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_SLAVE_LATENCY_LSB ) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.slave_latency); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_TIMEOUT_MULT_MSB ) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.timeout_mult >> 8); + *(buffer + OFFSET_ACI_CMD_T_CHANGE_TIMING + OFFSET_ACI_CMD_PARAMS_CHANGE_TIMING_T_CONN_PARAMS + OFFSET_ACI_LL_CONN_PARAMS_T_TIMEOUT_MULT_LSB ) = (uint8_t)(p_aci_cmd_params_change_timing->conn_params.timeout_mult); +} + +void acil_encode_cmd_set_app_latency(uint8_t *buffer, aci_cmd_params_set_app_latency_t *p_aci_cmd_params_set_app_latency) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_SET_APP_LATENCY_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SET_APP_LATENCY; + *(buffer + OFFSET_ACI_CMD_T_SET_APP_LATENCY + OFFSET_ACI_CMD_PARAMS_SET_APP_LATENCY_T_MODE) = (uint8_t)( p_aci_cmd_params_set_app_latency->mode); + *(buffer + OFFSET_ACI_CMD_T_SET_APP_LATENCY + OFFSET_ACI_CMD_PARAMS_SET_APP_LATENCY_T_LATENCY_MSB) = (uint8_t)( p_aci_cmd_params_set_app_latency->latency>>8); + *(buffer + OFFSET_ACI_CMD_T_SET_APP_LATENCY + OFFSET_ACI_CMD_PARAMS_SET_APP_LATENCY_T_LATENCY_LSB) = (uint8_t)( p_aci_cmd_params_set_app_latency->latency); +} + +void acil_encode_cmd_change_timing_req_GAP_PPCP(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_CHANGE_TIMING_LEN_GAP_PPCP; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_CHANGE_TIMING; +} + + +void acil_encode_cmd_setup(uint8_t *buffer, aci_cmd_params_setup_t *p_aci_cmd_params_setup, uint8_t setup_data_size) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = setup_data_size + MSG_SETUP_CMD_BASE_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SETUP; + memcpy((buffer + OFFSET_ACI_CMD_T_SETUP), &(p_aci_cmd_params_setup->setup_data[0]), setup_data_size); +} + +void acil_encode_cmd_dtm_cmd(uint8_t *buffer, aci_cmd_params_dtm_cmd_t *p_aci_cmd_params_dtm_cmd) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_DTM_CMD; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_DTM_CMD; + *(buffer + OFFSET_ACI_CMD_T_DTM_CMD) = p_aci_cmd_params_dtm_cmd->cmd_msb; + *(buffer + OFFSET_ACI_CMD_T_DTM_CMD + 1) = p_aci_cmd_params_dtm_cmd->cmd_lsb; +} + +void acil_encode_cmd_send_data_ack(uint8_t *buffer, const uint8_t pipe_number ) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_ACK_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SEND_DATA_ACK; + *(buffer + OFFSET_ACI_CMD_T_SEND_DATA_ACK + OFFSET_ACI_CMD_PARAMS_SEND_DATA_ACK_T_PIPE_NUMBER) = pipe_number; +} + +void acil_encode_cmd_send_data_nack(uint8_t *buffer, const uint8_t pipe_number, const uint8_t err_code ) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_NACK_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SEND_DATA_NACK; + *(buffer + OFFSET_ACI_CMD_T_SEND_DATA_NACK + OFFSET_ACI_CMD_PARAMS_SEND_DATA_NACK_T_PIPE_NUMBER) = pipe_number; + *(buffer + OFFSET_ACI_CMD_T_SEND_DATA_NACK + OFFSET_ACI_CMD_PARAMS_SEND_DATA_NACK_T_ERROR_CODE) = err_code; +} + +void acil_encode_cmd_bond_security_request(uint8_t *buffer) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = 1; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_BOND_SECURITY_REQUEST; +} + +void acil_encode_cmd_broadcast(uint8_t *buffer, aci_cmd_params_broadcast_t * p_aci_cmd_params_broadcast) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_BROADCAST_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_BROADCAST; + *(buffer + OFFSET_ACI_CMD_T_BROADCAST + OFFSET_ACI_CMD_PARAMS_BROADCAST_T_TIMEOUT_LSB) = (p_aci_cmd_params_broadcast->timeout & 0xff); + *(buffer + OFFSET_ACI_CMD_T_BROADCAST + OFFSET_ACI_CMD_PARAMS_BROADCAST_T_TIMEOUT_MSB) = (uint8_t)(p_aci_cmd_params_broadcast->timeout >> 8); + *(buffer + OFFSET_ACI_CMD_T_BROADCAST + OFFSET_ACI_CMD_PARAMS_BROADCAST_T_ADV_INTERVAL_LSB) = (p_aci_cmd_params_broadcast->adv_interval & 0xff); + *(buffer + OFFSET_ACI_CMD_T_BROADCAST + OFFSET_ACI_CMD_PARAMS_BROADCAST_T_ADV_INTERVAL_MSB) = (uint8_t)(p_aci_cmd_params_broadcast->adv_interval >> 8); +} + +void acil_encode_cmd_open_adv_pipes(uint8_t *buffer, aci_cmd_params_open_adv_pipe_t * p_aci_cmd_params_open_adv_pipe) +{ + *(buffer + OFFSET_ACI_CMD_T_LEN) = MSG_OPEN_ADV_PIPES_LEN; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_OPEN_ADV_PIPE; + memcpy(buffer + OFFSET_ACI_CMD_T_OPEN_ADV_PIPE + OFFSET_ACI_CMD_PARAMS_OPEN_ADV_PIPE_T_PIPES, p_aci_cmd_params_open_adv_pipe->pipes, 8); +} + + +void acil_encode_cmd_set_key(uint8_t *buffer, aci_cmd_params_set_key_t *p_aci_cmd_params_set_key) +{ + /* + The length of the key is computed based on the type of key transaction. + - Key Reject + - Key type is passkey + */ + uint8_t len; + + switch (p_aci_cmd_params_set_key->key_type) + { + case ACI_KEY_TYPE_INVALID: + len = MSG_SET_KEY_REJECT_LEN; + break; + case ACI_KEY_TYPE_PASSKEY: + len = MSG_SET_KEY_PASSKEY_LEN; + break; + default: + len=0; + break; + } + *(buffer + OFFSET_ACI_CMD_T_LEN) = len; + *(buffer + OFFSET_ACI_CMD_T_CMD_OPCODE) = ACI_CMD_SET_KEY; + *(buffer + OFFSET_ACI_CMD_T_SET_KEY + OFFSET_ACI_CMD_PARAMS_SET_KEY_T_KEY_TYPE) = p_aci_cmd_params_set_key->key_type; + memcpy((buffer + OFFSET_ACI_CMD_T_SET_KEY + OFFSET_ACI_CMD_PARAMS_SET_KEY_T_PASSKEY), (uint8_t * )&(p_aci_cmd_params_set_key->key), len-2);//Reducing 2 for the opcode byte and type +} + +bool acil_encode_cmd(uint8_t *buffer, aci_cmd_t *p_aci_cmd) +{ + bool ret_val = false; + + switch(p_aci_cmd->cmd_opcode) + { + case ACI_CMD_TEST: + acil_encode_cmd_set_test_mode(buffer, &(p_aci_cmd->params.test)); + break; + case ACI_CMD_SLEEP: + acil_encode_cmd_sleep(buffer); + break; + case ACI_CMD_GET_DEVICE_VERSION: + acil_encode_cmd_get_device_version(buffer); + break; + case ACI_CMD_WAKEUP: + acil_encode_cmd_wakeup(buffer); + break; + case ACI_CMD_ECHO: + acil_encode_cmd_echo_msg(buffer, &(p_aci_cmd->params.echo), (p_aci_cmd->len - MSG_ECHO_MSG_CMD_BASE_LEN)); + break; + case ACI_CMD_GET_BATTERY_LEVEL: + acil_encode_cmd_battery_level(buffer); + break; + case ACI_CMD_GET_TEMPERATURE: + acil_encode_cmd_temparature(buffer); + break; + case ACI_CMD_GET_DEVICE_ADDRESS: + acil_encode_cmd_get_address(buffer); + break; + case ACI_CMD_SET_TX_POWER: + acil_encode_cmd_set_radio_tx_power(buffer, &(p_aci_cmd->params.set_tx_power)); + break; + case ACI_CMD_CONNECT: + acil_encode_cmd_connect(buffer, &(p_aci_cmd->params.connect)); + break; + case ACI_CMD_BOND: + acil_encode_cmd_bond(buffer, &(p_aci_cmd->params.bond)); + break; + case ACI_CMD_DISCONNECT: + acil_encode_cmd_disconnect(buffer, &(p_aci_cmd->params.disconnect)); + break; + case ACI_CMD_RADIO_RESET: + acil_encode_baseband_reset(buffer); + break; + case ACI_CMD_CHANGE_TIMING: + acil_encode_cmd_change_timing_req(buffer, &(p_aci_cmd->params.change_timing)); + break; + case ACI_CMD_SETUP: + acil_encode_cmd_setup(buffer, &(p_aci_cmd->params.setup), (p_aci_cmd->len - MSG_SETUP_CMD_BASE_LEN)); + break; + case ACI_CMD_DTM_CMD: + acil_encode_cmd_dtm_cmd(buffer, &(p_aci_cmd->params.dtm_cmd)); + break; + case ACI_CMD_READ_DYNAMIC_DATA: + acil_encode_cmd_read_dynamic_data(buffer); + break; + case ACI_CMD_WRITE_DYNAMIC_DATA: + acil_encode_cmd_write_dynamic_data(buffer, p_aci_cmd->params.write_dynamic_data.seq_no, &(p_aci_cmd->params.write_dynamic_data.dynamic_data[0]), (p_aci_cmd->len - MSG_WRITE_DYNAMIC_DATA_BASE_LEN)); + break; + case ACI_CMD_OPEN_REMOTE_PIPE: + acil_encode_cmd_open_remote_pipe(buffer, &(p_aci_cmd->params.open_remote_pipe)); + break; + case ACI_CMD_SEND_DATA: + acil_encode_cmd_send_data(buffer, &(p_aci_cmd->params.send_data), (p_aci_cmd->len - MSG_SEND_DATA_BASE_LEN)); + break; + case ACI_CMD_SEND_DATA_ACK: + acil_encode_cmd_send_data_ack(buffer, p_aci_cmd->params.send_data_ack.pipe_number ); + break; + case ACI_CMD_REQUEST_DATA: + acil_encode_cmd_request_data(buffer, &(p_aci_cmd->params.request_data)); + break; + case ACI_CMD_SET_LOCAL_DATA: + acil_encode_cmd_set_local_data(buffer, (aci_cmd_params_set_local_data_t *)(&(p_aci_cmd->params.send_data)), (p_aci_cmd->len - MSG_SET_LOCAL_DATA_BASE_LEN)); + break; + case ACI_CMD_BOND_SECURITY_REQUEST: + acil_encode_cmd_bond_security_request(buffer); + break; + default: + break; + } + return ret_val; +} + +void acil_decode_evt_command_response(uint8_t *buffer_in, aci_evt_params_cmd_rsp_t *p_evt_params_cmd_rsp) +{ + aci_evt_cmd_rsp_params_get_device_version_t *p_device_version; + aci_evt_cmd_rsp_params_get_device_address_t *p_device_address; + aci_evt_cmd_rsp_params_get_temperature_t *p_temperature; + aci_evt_cmd_rsp_params_get_battery_level_t *p_batt_lvl; + aci_evt_cmd_rsp_read_dynamic_data_t *p_read_dyn_data; + aci_evt_cmd_rsp_params_dtm_cmd_t *p_dtm_evt; + + p_evt_params_cmd_rsp->cmd_opcode = (aci_cmd_opcode_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_CMD_OPCODE); + p_evt_params_cmd_rsp->cmd_status = (aci_status_code_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_CMD_STATUS); + + switch (p_evt_params_cmd_rsp->cmd_opcode) + { + case ACI_CMD_GET_DEVICE_VERSION: + p_device_version = &(p_evt_params_cmd_rsp->params.get_device_version); + p_device_version->configuration_id = (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_CONFIGURATION_ID_LSB); + p_device_version->configuration_id |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_CONFIGURATION_ID_MSB) << 8; + p_device_version->aci_version = *(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_ACI_VERSION); + p_device_version->setup_format = *(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_FORMAT); + p_device_version->setup_id = (uint32_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_LSB0); + p_device_version->setup_id |= (uint32_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_LSB1) << 8; + p_device_version->setup_id |= (uint32_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_MSB0) << 16; + p_device_version->setup_id |= (uint32_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_ID_MSB1) << 24; + p_device_version->setup_status = *(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_VERSION + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_VERSION_T_SETUP_STATUS); + break; + + case ACI_CMD_GET_DEVICE_ADDRESS: + p_device_address = &(p_evt_params_cmd_rsp->params.get_device_address); + memcpy((uint8_t *)(p_device_address->bd_addr_own), (buffer_in + OFFSET_ACI_EVT_T_CMD_RSP+OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_ADDRESS+OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_ADDRESS_T_BD_ADDR_OWN), BTLE_DEVICE_ADDRESS_SIZE); + p_device_address->bd_addr_type = (aci_bd_addr_type_t) *(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP+OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_DEVICE_ADDRESS+OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_DEVICE_ADDRESS_T_BD_ADDR_TYPE); + break; + + case ACI_CMD_GET_TEMPERATURE: + p_temperature = &(p_evt_params_cmd_rsp->params.get_temperature); + p_temperature->temperature_value = (int16_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_TEMPERATURE + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_TEMPERATURE_T_TEMPERATURE_VALUE_LSB); + p_temperature->temperature_value |= (int16_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_TEMPERATURE + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_TEMPERATURE_T_TEMPERATURE_VALUE_MSB) << 8; + break; + + case ACI_CMD_GET_BATTERY_LEVEL: + p_batt_lvl = &(p_evt_params_cmd_rsp->params.get_battery_level); + p_batt_lvl->battery_level = (int16_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_BATTERY_LEVEL + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_BATTERY_LEVEL_T_BATTERY_LEVEL_LSB); + p_batt_lvl->battery_level |= (int16_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_GET_BATTERY_LEVEL + OFFSET_ACI_EVT_CMD_RSP_PARAMS_GET_BATTERY_LEVEL_T_BATTERY_LEVEL_MSB) << 8; + break; + + case ACI_CMD_READ_DYNAMIC_DATA: + p_read_dyn_data = &(p_evt_params_cmd_rsp->params.read_dynamic_data); + p_read_dyn_data->seq_no = (uint8_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_READ_DYNAMIC_DATA + OFFSET_ACI_EVT_CMD_RSP_READ_DYNAMIC_DATA_T_SEQ_NO); + memcpy((uint8_t *)(p_read_dyn_data->dynamic_data), (buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_READ_DYNAMIC_DATA + OFFSET_ACI_CMD_PARAMS_WRITE_DYNAMIC_DATA_T_DYNAMIC_DATA), ACIL_DECODE_EVT_GET_LENGTH(buffer_in) - 3); // 3 bytes subtracted account for EventCode, CommandOpCode and Status bytes. + // Now that the p_read_dyn_data->dynamic_data will be pointing to memory location with enough space to accommodate upto 27 bytes of dynamic data received. This is because of the padding element in aci_evt_params_cmd_rsp_t + break; + + case ACI_CMD_DTM_CMD: + p_dtm_evt = &(p_evt_params_cmd_rsp->params.dtm_cmd); + p_dtm_evt->evt_msb = (uint8_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_DTM_CMD + OFFSET_ACI_EVT_CMD_RSP_PARAMS_DTM_CMD_T_EVT_MSB); + p_dtm_evt->evt_lsb = (uint8_t)*(buffer_in + OFFSET_ACI_EVT_T_CMD_RSP + OFFSET_ACI_EVT_PARAMS_CMD_RSP_T_DTM_CMD + OFFSET_ACI_EVT_CMD_RSP_PARAMS_DTM_CMD_T_EVT_LSB); + break; + + default: + break; + } +} + +void acil_decode_evt_device_started(uint8_t *buffer_in, aci_evt_params_device_started_t *p_evt_params_device_started) +{ + p_evt_params_device_started->device_mode = (aci_device_operation_mode_t) *(buffer_in + OFFSET_ACI_EVT_T_DEVICE_STARTED+OFFSET_ACI_EVT_PARAMS_DEVICE_STARTED_T_DEVICE_MODE); + p_evt_params_device_started->hw_error = (aci_hw_error_t) *(buffer_in + OFFSET_ACI_EVT_T_DEVICE_STARTED+OFFSET_ACI_EVT_PARAMS_DEVICE_STARTED_T_HW_ERROR); + p_evt_params_device_started->credit_available = *(buffer_in + OFFSET_ACI_EVT_T_DEVICE_STARTED+OFFSET_ACI_EVT_PARAMS_DEVICE_STARTED_T_CREDIT_AVAILABLE); +} + +void acil_decode_evt_pipe_status(uint8_t *buffer_in, aci_evt_params_pipe_status_t *p_aci_evt_params_pipe_status) +{ + memcpy((uint8_t *)p_aci_evt_params_pipe_status->pipes_open_bitmap, (buffer_in + OFFSET_ACI_EVT_T_PIPE_STATUS + OFFSET_ACI_EVT_PARAMS_PIPE_STATUS_T_PIPES_OPEN_BITMAP), 8); + memcpy((uint8_t *)p_aci_evt_params_pipe_status->pipes_closed_bitmap, (buffer_in + OFFSET_ACI_EVT_T_PIPE_STATUS + OFFSET_ACI_EVT_PARAMS_PIPE_STATUS_T_PIPES_CLOSED_BITMAP), 8); +} + +void acil_decode_evt_disconnected(uint8_t *buffer_in, aci_evt_params_disconnected_t *p_aci_evt_params_disconnected) +{ + p_aci_evt_params_disconnected->aci_status = (aci_status_code_t)*(buffer_in + OFFSET_ACI_EVT_T_DISCONNECTED + OFFSET_ACI_EVT_PARAMS_DISCONNECTED_T_ACI_STATUS); + p_aci_evt_params_disconnected->btle_status = *(buffer_in + OFFSET_ACI_EVT_T_DISCONNECTED + OFFSET_ACI_EVT_PARAMS_DISCONNECTED_T_BTLE_STATUS); +} + +void acil_decode_evt_bond_status(uint8_t *buffer_in, aci_evt_params_bond_status_t *p_aci_evt_params_bond_status) +{ + p_aci_evt_params_bond_status->status_code = (aci_bond_status_code_t)*(buffer_in + OFFSET_ACI_EVT_T_BOND_STATUS + OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_STATUS_CODE); + p_aci_evt_params_bond_status->status_source = (aci_bond_status_source_t)*(buffer_in + OFFSET_ACI_EVT_T_BOND_STATUS + OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_STATUS_SOURCE); + p_aci_evt_params_bond_status->secmode1_bitmap = *(buffer_in + OFFSET_ACI_EVT_T_BOND_STATUS + OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_SECMODE1_BITMAP); + p_aci_evt_params_bond_status->secmode2_bitmap = *(buffer_in + OFFSET_ACI_EVT_T_BOND_STATUS + OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_SECMODE2_BITMAP); + p_aci_evt_params_bond_status->keys_exchanged_slave = *(buffer_in + OFFSET_ACI_EVT_T_BOND_STATUS + OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_KEYS_EXCHANGED_SLAVE); + p_aci_evt_params_bond_status->keys_exchanged_master = *(buffer_in + OFFSET_ACI_EVT_T_BOND_STATUS + OFFSET_ACI_EVT_PARAMS_BOND_STATUS_T_KEYS_EXCHANGED_MASTER); +} + +uint8_t acil_decode_evt_data_received(uint8_t *buffer_in, aci_evt_params_data_received_t *p_evt_params_data_received) +{ + uint8_t size = *( buffer_in + OFFSET_ACI_EVT_T_LEN) - (OFFSET_ACI_EVT_T_DATA_RECEIVED + OFFSET_ACI_RX_DATA_T_ACI_DATA) + 1 ; + p_evt_params_data_received->rx_data.pipe_number = *(buffer_in + OFFSET_ACI_EVT_T_DATA_RECEIVED + OFFSET_ACI_RX_DATA_T_PIPE_NUMBER); + memcpy((uint8_t *)p_evt_params_data_received->rx_data.aci_data, (buffer_in + OFFSET_ACI_EVT_T_DATA_RECEIVED + OFFSET_ACI_RX_DATA_T_ACI_DATA), size); + return size; +} + +void acil_decode_evt_data_ack(uint8_t *buffer_in, aci_evt_params_data_ack_t *p_evt_params_data_ack) +{ + p_evt_params_data_ack->pipe_number = *(buffer_in + OFFSET_ACI_EVT_T_DATA_ACK + OFFSET_ACI_EVT_PARAMS_DATA_ACK_T_PIPE_NUMBER); +} + +uint8_t acil_decode_evt_hw_error(uint8_t *buffer_in, aci_evt_params_hw_error_t *p_aci_evt_params_hw_error) +{ + uint8_t size = *(buffer_in + OFFSET_ACI_EVT_T_LEN) - (OFFSET_ACI_EVT_T_HW_ERROR + OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_FILE_NAME) + 1; + p_aci_evt_params_hw_error->line_num = (uint16_t)(*(buffer_in + OFFSET_ACI_EVT_T_HW_ERROR + OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_LINE_NUM_MSB)) << 8; + p_aci_evt_params_hw_error->line_num |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_HW_ERROR + OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_LINE_NUM_LSB); + memcpy((uint8_t *)p_aci_evt_params_hw_error->file_name, (buffer_in + OFFSET_ACI_EVT_T_HW_ERROR + OFFSET_ACI_EVT_PARAMS_HW_ERROR_T_FILE_NAME), size); + return size; +} + +void acil_decode_evt_credit(uint8_t *buffer_in, aci_evt_params_data_credit_t *p_evt_params_data_credit) +{ + p_evt_params_data_credit->credit = *(buffer_in + OFFSET_ACI_EVT_T_DATA_CREDIT + OFFSET_ACI_EVT_PARAMS_DATA_CREDIT_T_CREDIT); +} + +void acil_decode_evt_connected(uint8_t *buffer_in, aci_evt_params_connected_t *p_aci_evt_params_connected) +{ + p_aci_evt_params_connected->dev_addr_type = (aci_bd_addr_type_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_DEV_ADDR_TYPE); + memcpy(&(p_aci_evt_params_connected->dev_addr[0]), (buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_DEV_ADDR), BTLE_DEVICE_ADDRESS_SIZE); + p_aci_evt_params_connected->conn_rf_interval = (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_INTERVAL_MSB) << 8; + p_aci_evt_params_connected->conn_rf_interval |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_INTERVAL_LSB); + p_aci_evt_params_connected->conn_slave_rf_latency = (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_SLAVE_RF_LATENCY_MSB) << 8; + p_aci_evt_params_connected->conn_slave_rf_latency |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_SLAVE_RF_LATENCY_LSB); + p_aci_evt_params_connected->conn_rf_timeout = (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_TIMEOUT_MSB) << 8; + p_aci_evt_params_connected->conn_rf_timeout |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_CONN_RF_TIMEOUT_LSB); + p_aci_evt_params_connected->master_clock_accuracy = (aci_clock_accuracy_t)*(buffer_in + OFFSET_ACI_EVT_T_CONNECTED + OFFSET_ACI_EVT_PARAMS_CONNECTED_T_MASTER_CLOCK_ACCURACY); + +} + +void acil_decode_evt_timing(uint8_t *buffer_in, aci_evt_params_timing_t *p_evt_params_timing) +{ + p_evt_params_timing->conn_rf_interval = *(buffer_in + OFFSET_ACI_EVT_T_TIMING + OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_INTERVAL_MSB) << 8; + p_evt_params_timing->conn_rf_interval |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_TIMING + OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_INTERVAL_LSB); + p_evt_params_timing->conn_slave_rf_latency = (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_TIMING + OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_SLAVE_RF_LATENCY_MSB) << 8; + p_evt_params_timing->conn_slave_rf_latency |= (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_TIMING + OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_SLAVE_RF_LATENCY_LSB); + p_evt_params_timing->conn_rf_timeout = (uint16_t)*(buffer_in + OFFSET_ACI_EVT_T_TIMING + OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_TIMEOUT_MSB) << 8; + p_evt_params_timing->conn_rf_timeout |= *(buffer_in + OFFSET_ACI_EVT_T_TIMING + OFFSET_ACI_EVT_PARAMS_TIMING_T_CONN_RF_TIMEOUT_LSB); +} + +void acil_decode_evt_pipe_error(uint8_t *buffer_in, aci_evt_params_pipe_error_t *p_evt_params_pipe_error) +{ + //volatile uint8_t size = *(buffer_in + OFFSET_ACI_EVT_T_LEN) - (OFFSET_ACI_EVT_T_PIPE_ERROR + OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_ERROR_DATA) + 1; + p_evt_params_pipe_error->pipe_number = *(buffer_in + OFFSET_ACI_EVT_T_PIPE_ERROR + OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_PIPE_NUMBER); + p_evt_params_pipe_error->error_code = *(buffer_in + OFFSET_ACI_EVT_T_PIPE_ERROR + OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_ERROR_CODE); + p_evt_params_pipe_error->params.error_data.content[0] = *(buffer_in + OFFSET_ACI_EVT_T_PIPE_ERROR + OFFSET_ACI_EVT_PARAMS_PIPE_ERROR_T_ERROR_DATA + OFFSET_ERROR_DATA_T_CONTENT); +} + +void acil_decode_evt_key_request(uint8_t *buffer_in, aci_evt_params_key_request_t *p_evt_params_key_request) +{ + p_evt_params_key_request->key_type = (aci_key_type_t)*(buffer_in + OFFSET_ACI_EVT_T_KEY_REQUEST + OFFSET_ACI_EVT_PARAMS_KEY_REQUEST_T_KEY_TYPE); +} + +uint8_t acil_decode_evt_echo(uint8_t *buffer_in, aci_evt_params_echo_t *aci_evt_params_echo) +{ + uint8_t size = *(buffer_in + OFFSET_ACI_EVT_T_LEN) - 1; + memcpy(&aci_evt_params_echo->echo_data[0], (buffer_in + OFFSET_ACI_EVT_T_EVT_OPCODE + 1), size); + return size; +} + +void acil_decode_evt_display_passkey(uint8_t *buffer_in, aci_evt_params_display_passkey_t *p_aci_evt_params_display_passkey) +{ + p_aci_evt_params_display_passkey->passkey[0] = *(buffer_in + OFFSET_ACI_EVT_T_DISPLAY_PASSKEY + OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY + 0); + p_aci_evt_params_display_passkey->passkey[1] = *(buffer_in + OFFSET_ACI_EVT_T_DISPLAY_PASSKEY + OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY + 1); + p_aci_evt_params_display_passkey->passkey[2] = *(buffer_in + OFFSET_ACI_EVT_T_DISPLAY_PASSKEY + OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY + 2); + p_aci_evt_params_display_passkey->passkey[3] = *(buffer_in + OFFSET_ACI_EVT_T_DISPLAY_PASSKEY + OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY + 3); + p_aci_evt_params_display_passkey->passkey[4] = *(buffer_in + OFFSET_ACI_EVT_T_DISPLAY_PASSKEY + OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY + 4); + p_aci_evt_params_display_passkey->passkey[5] = *(buffer_in + OFFSET_ACI_EVT_T_DISPLAY_PASSKEY + OFFSET_ACI_EVT_PARAMS_DISPLAY_PASSKEY_T_PASSKEY + 5); +} + +bool acil_decode_evt(uint8_t *buffer_in, aci_evt_t *p_aci_evt) +{ + bool ret_val = true; + + p_aci_evt->len = ACIL_DECODE_EVT_GET_LENGTH(buffer_in); + p_aci_evt->evt_opcode = (aci_evt_opcode_t)ACIL_DECODE_EVT_GET_OPCODE(buffer_in); + + switch(p_aci_evt->evt_opcode) + { + case ACI_EVT_DEVICE_STARTED: + acil_decode_evt_device_started(buffer_in, &(p_aci_evt->params.device_started)); + break; + case ACI_EVT_HW_ERROR: + acil_decode_evt_hw_error(buffer_in, &(p_aci_evt->params.hw_error)); + break; + case ACI_EVT_CMD_RSP: + acil_decode_evt_command_response(buffer_in, &(p_aci_evt->params.cmd_rsp)); + break; + case ACI_EVT_DATA_CREDIT: + acil_decode_evt_credit(buffer_in, &(p_aci_evt->params.data_credit)); + break; + case ACI_EVT_CONNECTED: + acil_decode_evt_connected(buffer_in, &(p_aci_evt->params.connected)); + break; + case ACI_EVT_PIPE_STATUS: + acil_decode_evt_pipe_status(buffer_in, &(p_aci_evt->params.pipe_status)); + break; + case ACI_EVT_DISCONNECTED: + acil_decode_evt_disconnected(buffer_in, &(p_aci_evt->params.disconnected)); + break; + case ACI_EVT_BOND_STATUS: + acil_decode_evt_bond_status(buffer_in, &(p_aci_evt->params.bond_status)); + break; + case ACI_EVT_TIMING: + acil_decode_evt_timing(buffer_in, &(p_aci_evt->params.timing)); + break; + case ACI_EVT_DATA_ACK: + acil_decode_evt_data_ack(buffer_in, &(p_aci_evt->params.data_ack)); + break; + case ACI_EVT_DATA_RECEIVED: + acil_decode_evt_data_received(buffer_in, &(p_aci_evt->params.data_received)); + break; + case ACI_EVT_PIPE_ERROR: + acil_decode_evt_pipe_error(buffer_in, &(p_aci_evt->params.pipe_error)); + break; + case ACI_EVT_KEY_REQUEST: + acil_decode_evt_key_request(buffer_in, &(p_aci_evt->params.key_request)); + break; + case ACI_EVT_DISPLAY_PASSKEY: + acil_decode_evt_display_passkey(buffer_in, &(p_aci_evt->params.display_passkey)); + break; + default: + ret_val = false; + break; + } + return ret_val; +} + +#endif diff --git a/cores/nRF5/utility/acilib.h b/cores/nRF5/utility/acilib.h new file mode 100644 index 00000000..5f901ddd --- /dev/null +++ b/cores/nRF5/utility/acilib.h @@ -0,0 +1,61 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup group_acilib + * + * @brief Internal prototype for acilib module. + */ + +#ifndef _acilib_H_ +#define _acilib_H_ + +#define MSG_SET_LOCAL_DATA_BASE_LEN 2 +#define MSG_CONNECT_LEN 5 +#define MSG_BOND_LEN 5 +#define MSG_DISCONNECT_LEN 2 +#define MSG_BASEBAND_RESET_LEN 1 +#define MSG_WAKEUP_LEN 1 +#define MSG_SET_RADIO_TX_POWER_LEN 2 +#define MSG_GET_DEVICE_ADDR_LEN 1 +#define MSG_SEND_DATA_BASE_LEN 2 +#define MSG_DATA_REQUEST_LEN 2 +#define MSG_OPEN_REMOTE_PIPE_LEN 2 +#define MSG_CLOSE_REMOTE_PIPE_LEN 2 +#define MSG_DTM_CMD 3 +#define MSG_WRITE_DYNAMIC_DATA_BASE_LEN 2 +#define MSG_SETUP_CMD_BASE_LEN 1 +#define MSG_ECHO_MSG_CMD_BASE_LEN 1 +#define MSG_CHANGE_TIMING_LEN 9 +#define MSG_SET_APP_LATENCY_LEN 4 +#define MSG_CHANGE_TIMING_LEN_GAP_PPCP 1 +#define MSG_DIRECT_CONNECT_LEN 1 +#define MSG_SET_KEY_REJECT_LEN 2 +#define MSG_SET_KEY_PASSKEY_LEN 8 +#define MSG_SET_KEY_OOB_LEN 18 +#define MSG_ACK_LEN 2 +#define MSG_NACK_LEN 3 +#define MSG_BROADCAST_LEN 5 +#define MSG_OPEN_ADV_PIPES_LEN 9 + +#endif /* _acilib_H_ */ diff --git a/cores/nRF5/utility/acilib_defs.h b/cores/nRF5/utility/acilib_defs.h new file mode 100644 index 00000000..25826d2f --- /dev/null +++ b/cores/nRF5/utility/acilib_defs.h @@ -0,0 +1,37 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup group_acilib + * + * @brief Definitions for the acilib interfaces + */ + +#ifndef _acilib_DEFS_H_ +#define _acilib_DEFS_H_ + +#define ACIL_DECODE_EVT_GET_LENGTH(buffer_in) (*(buffer_in + OFFSET_ACI_EVT_T_LEN)) + +#define ACIL_DECODE_EVT_GET_OPCODE(buffer_in) (*(buffer_in + OFFSET_ACI_EVT_T_EVT_OPCODE)) + +#endif /* _acilib_DEFS_H_ */ diff --git a/cores/nRF5/utility/acilib_if.h b/cores/nRF5/utility/acilib_if.h new file mode 100644 index 00000000..f1cd21f8 --- /dev/null +++ b/cores/nRF5/utility/acilib_if.h @@ -0,0 +1,471 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup group_acilib + * + * @brief Prototypes for the acilib interfaces. + */ + +#ifndef _acilib_IF_H_ +#define _acilib_IF_H_ + +/** @brief Encode the ACI message for set test mode command + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] test_mode Pointer to the test mode in ::aci_cmd_params_test_t + * + * @return None + */ +void acil_encode_cmd_set_test_mode(uint8_t *buffer, aci_cmd_params_test_t *p_aci_cmd_params_test); + +/** @brief Encode the ACI message for sleep command + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_sleep(uint8_t *buffer); + +/** @brief Encode the ACI message for get device version + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_get_device_version(uint8_t *buffer); + +/** @brief Encode the ACI message for set local data + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_set_local_data Pointer to the local data parameters in ::aci_cmd_params_set_local_data_t + * @param[in] data_size Size of data message + * + * @return None + */ +void acil_encode_cmd_set_local_data(uint8_t *buffer, aci_cmd_params_set_local_data_t *p_aci_cmd_params_set_local_data, uint8_t data_size); + +/** @brief Encode the ACI message to connect + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_connect Pointer to the run parameters in ::aci_cmd_params_connect_t + * + * @return None + */ +void acil_encode_cmd_connect(uint8_t *buffer, aci_cmd_params_connect_t *p_aci_cmd_params_connect); + +/** @brief Encode the ACI message to bond + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_bond Pointer to the run parameters in ::aci_cmd_params_bond_t + * + * @return None + */ +void acil_encode_cmd_bond(uint8_t *buffer, aci_cmd_params_bond_t *p_aci_cmd_params_bond); + +/** @brief Encode the ACI message to disconnect + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_disconnect Pointer to the run parameters in ::aci_cmd_params_disconnect_t + * + * @return None + */ +void acil_encode_cmd_disconnect(uint8_t *buffer, aci_cmd_params_disconnect_t *p_aci_cmd_params_disconnect); + +/** @brief Encode the ACI message to baseband reset + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ + void acil_encode_baseband_reset(uint8_t *buffer); + + /** @brief Encode the ACI message for Directed Advertising + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ + void acil_encode_direct_connect(uint8_t *buffer); + +/** @brief Encode the ACI message to wakeup + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_wakeup(uint8_t *buffer); + +/** @brief Encode the ACI message for set radio Tx power + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_set_tx_power Pointer to the set Tx power parameters in ::aci_cmd_params_set_tx_power_t + * + * @return None + */ +void acil_encode_cmd_set_radio_tx_power(uint8_t *buffer, aci_cmd_params_set_tx_power_t *p_aci_cmd_params_set_tx_power); + +/** @brief Encode the ACI message for get device address + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_get_address(uint8_t *buffer); + +/** @brief Encode the ACI message for send data + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_send_data_t Pointer to the data parameters in ::aci_cmd_params_send_data_t + * @param[in] data_size Size of data message + * + * @return None + */ +void acil_encode_cmd_send_data(uint8_t *buffer, aci_cmd_params_send_data_t *p_aci_cmd_params_send_data_t, uint8_t data_size); + +/** @brief Encode the ACI message for request data + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_request_data Pointer to the request data parameters in ::aci_cmd_params_request_data_t + * + * @return None + */ +void acil_encode_cmd_request_data(uint8_t *buffer, aci_cmd_params_request_data_t *p_aci_cmd_params_request_data); + +/** @brief Encode the ACI message for open remote pipe + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_open_remote_pipe Pointer to the dynamic data parameters in ::aci_cmd_params_open_remote_pipe_t + * + * @return None + */ +void acil_encode_cmd_open_remote_pipe(uint8_t *buffer, aci_cmd_params_open_remote_pipe_t *p_aci_cmd_params_open_remote_pipe); + +/** @brief Encode the ACI message for close remote pipe + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_close_remote_pipe Pointer to the dynamic data parameters in ::aci_cmd_params_close_remote_pipe_t + * + * @return None + */ +void acil_encode_cmd_close_remote_pipe(uint8_t *buffer, aci_cmd_params_close_remote_pipe_t *p_aci_cmd_params_close_remote_pipe); + +/** @brief Encode the ACI message for echo message + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_cmd_params_echo Pointer to the dynamic data parameters in ::aci_cmd_params_echo_t + * @param[in] msg_size Size of the message + * + * @return None + */ +void acil_encode_cmd_echo_msg(uint8_t *buffer, aci_cmd_params_echo_t *p_cmd_params_echo, uint8_t msg_size); + +/** @brief Encode the ACI message to battery level + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_battery_level(uint8_t *buffer); + +/** @brief Encode the ACI message to temparature + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_temparature(uint8_t *buffer); + +/** @brief Encode the ACI message to read dynamic data + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_read_dynamic_data(uint8_t *buffer); + +/** @brief Encode the ACI message to change timing request + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_change_timing Pointer to the change timing parameters in ::aci_cmd_params_change_timing_t + * + * @return None + */ +void acil_encode_cmd_change_timing_req(uint8_t *buffer, aci_cmd_params_change_timing_t *p_aci_cmd_params_change_timing); + +/** @brief Encode the ACI message to change timing request using the timing parameters from GAP PPCP + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_change_timing Pointer to the change timing parameters in ::aci_cmd_params_change_timing_t + * + * @return None + */ +void acil_encode_cmd_change_timing_req_GAP_PPCP(uint8_t *buffer); + + +/** @brief Encode the ACI message for write dynamic data + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] seq_no Sequence number of the dynamic data (as received in the response to @c Read Dynamic Data) + * @param[in] dynamic_data Pointer to the dynamic data + * @param[in] dynamic_data_size Size of dynamic data + * + * @return None + */ +void acil_encode_cmd_write_dynamic_data(uint8_t *buffer, uint8_t seq_no, uint8_t* dynamic_data, uint8_t dynamic_data_size); + +/** @brief Encode the ACI message to send data acknowledgement + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] pipe_number Pipe number for which the ack is to be sent + * + * @return None + */ +void acil_encode_cmd_send_data_ack(uint8_t *buffer, const uint8_t pipe_number); + +/** @brief Encode the ACI message to send negative acknowledgement + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] pipe_number Pipe number for which the nack is to be sent + * @param[in] error_code Error code that has to be sent in the NACK + * + * @return None + */ +void acil_encode_cmd_send_data_nack(uint8_t *buffer, const uint8_t pipe_number,const uint8_t error_code); + +/** @brief Encode the ACI message to set the application latency + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd_params_set_app_latency Pointer to the set_application_latency command parameters in ::aci_cmd_params_dtm_cmd_t + * + * @return None + */ +void acil_encode_cmd_set_app_latency(uint8_t *buffer, aci_cmd_params_set_app_latency_t *p_aci_cmd_params_set_app_latency); + +/** @brief Encode the ACI message for setup + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_cmd_params_set_run_behaviour Pointer to the setup data in ::aci_cmd_params_setup_t + * @param[in] setup_data_size Size of setup message + * + * @return None + */ +void acil_encode_cmd_setup(uint8_t *buffer, aci_cmd_params_setup_t *p_aci_cmd_params_setup, uint8_t setup_data_size); + +/** @brief Encode the ACI message for DTM command + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_cmd_params_set_run_behaviour Pointer to the DTM command parameters in ::aci_cmd_params_dtm_cmd_t + * + * @return None + */ +void acil_encode_cmd_dtm_cmd(uint8_t *buffer, aci_cmd_params_dtm_cmd_t *p_aci_cmd_params_dtm_cmd); + +/** @brief Encode the ACI message for Set Key Request command + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_set_key(uint8_t *buffer, aci_cmd_params_set_key_t *p_aci_cmd_params_set_key); + +/** @brief Encode the ACI message for Bond Security Request command + * + * @param[in,out] buffer Pointer to ACI message buffer + * + * @return None + */ +void acil_encode_cmd_bond_security_request(uint8_t *buffer); + +/** @brief Encode the ACI message + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd Pointer to ACI command data in ::aci_cmd_t + * @param[in] bool + * + * @return bool true, if succesful, else returns false + */ +bool acil_encode_cmd(uint8_t *buffer, aci_cmd_t *p_aci_cmd); + +/** @brief Encode the ACI message for Broadcast command + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd Pointer to ACI command data in ::aci_cmd_params_broadcast_t + * + * @return None + */ +void acil_encode_cmd_broadcast(uint8_t *buffer, aci_cmd_params_broadcast_t * p_aci_cmd_params_broadcast); + +/** @brief Encode the ACI message for Open Adv Pipes + * + * @param[in,out] buffer Pointer to ACI message buffer + * @param[in] p_aci_cmd Pointer to ACI command data in ::aci_cmd_params_open_adv_pipe_t + * + * @return None + */ +void acil_encode_cmd_open_adv_pipes(uint8_t *buffer, aci_cmd_params_open_adv_pipe_t * p_aci_cmd_params_set_adv_svc_data); + +/** @brief Decode the ACI event command response + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] buffer Pointer to the decoded message in ::aci_evt_params_cmd_rsp_t + * + * @return None + */ +void acil_decode_evt_command_response(uint8_t *buffer_in, aci_evt_params_cmd_rsp_t *p_evt_params_cmd_rsp); + +/** @brief Decode the ACI event device started + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt Pointer to the decoded message in ::aci_evt_params_device_started_t + * + * @return None + */ +void acil_decode_evt_device_started(uint8_t *buffer_in, aci_evt_params_device_started_t *p_evt_params_device_started); + +/** @brief Decode the ACI event pipe status + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt_params_pipe_status Pointer to the decoded message in ::aci_evt_params_pipe_status_t + * + * @return None + */ +void acil_decode_evt_pipe_status(uint8_t *buffer_in, aci_evt_params_pipe_status_t *p_aci_evt_params_pipe_status); + +/** @brief Decode the ACI event for disconnected + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt_params_disconnected Pointer to the decoded message in ::aci_evt_params_disconnected_t + * + * @return None + */ +void acil_decode_evt_disconnected(uint8_t *buffer_in, aci_evt_params_disconnected_t *p_aci_evt_params_disconnected); + +/** @brief Decode the ACI event for bond status + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt_params_bond_status Pointer to the decoded message in ::aci_evt_params_bond_status_t + * + * @return None + */ +void acil_decode_evt_bond_status(uint8_t *buffer_in, aci_evt_params_bond_status_t *p_aci_evt_params_bond_status); + +/** @brief Decode the ACI event for data received + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_evt_params_data_received Pointer to the decoded message in ::aci_evt_params_data_received_t + * + * @return size Received data size + */ +uint8_t acil_decode_evt_data_received(uint8_t *buffer_in, aci_evt_params_data_received_t *p_evt_params_data_received); + +/** @brief Decode the ACI event data acknowledgement + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_evt_params_data_ack Pointer to the decoded message in ::aci_evt_params_data_ack_t + * + * @return None + */ +void acil_decode_evt_data_ack(uint8_t *buffer_in, aci_evt_params_data_ack_t *p_evt_params_data_ack); + +/** @brief Decode the ACI event for hardware error + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt_params_hw_error Pointer to the decoded message in ::aci_evt_params_hw_error_t + * + * @return size Size of debug information + */ +uint8_t acil_decode_evt_hw_error(uint8_t *buffer_in, aci_evt_params_hw_error_t *p_aci_evt_params_hw_error); + +/** @brief Decode the ACI event data credit + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_evt_params_data_credit Pointer to the decoded message in ::aci_evt_params_data_credit_t + * + * @return None + */ +void acil_decode_evt_credit(uint8_t *buffer_in, aci_evt_params_data_credit_t *p_evt_params_data_credit); + +/** @brief Decode the ACI event for connected + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt_params_connected Pointer to the decoded message in ::aci_evt_params_connected_t + * + * @return None + */ +void acil_decode_evt_connected(uint8_t *buffer_in, aci_evt_params_connected_t *p_aci_evt_params_connected); + +/** @brief Decode the ACI event for timing + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_evt_params_timing Pointer to the decoded message in ::aci_evt_params_timing_t + * + * @return None + */ +void acil_decode_evt_timing(uint8_t *buffer_in, aci_evt_params_timing_t *p_evt_params_timing); + +/** @brief Decode the ACI event for pipe error + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_evt_params_pipe_error Pointer to the decoded message in ::aci_evt_params_pipe_error_t + * + */ +void acil_decode_evt_pipe_error(uint8_t *buffer_in, aci_evt_params_pipe_error_t *p_evt_params_pipe_error); + +/** @brief Decode the ACI event for key request + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_evt_params_key_type Pointer to the decoded message in ::aci_evt_params_key_type_t + * + * @return None + */ +void acil_decode_evt_key_request(uint8_t *buffer_in, aci_evt_params_key_request_t *p_evt_params_key_request); + +/** @brief Decode the ACI event for echo + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] buffer_out Pointer to the echo message (max size of buffer ::ACI_ECHO_DATA_MAX_LEN) + * + * @return size Received echo message size + */ +uint8_t acil_decode_evt_echo(uint8_t *buffer_in, aci_evt_params_echo_t *buffer_out); + +/** @brief Decode the ACI event + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt Pointer to the decoded message in ::aci_evt_t + * + * @return bool true, if succesful, else returns false + */ +bool acil_decode_evt(uint8_t *buffer_in, aci_evt_t *p_aci_evt); + +/** @brief Decode the Display Key Event + * + * @param[in] buffer_in Pointer to message received + * @param[in,out] p_aci_evt Pointer to the decoded message in ::aci_evt_params_display_passkey_t + * + * @return None + */ +void acil_decode_evt_display_passkey(uint8_t *buffer_in, aci_evt_params_display_passkey_t *p_aci_evt_params_display_passkey); + +#endif /* _acilib_IF_H_ */ diff --git a/cores/nRF5/utility/acilib_types.h b/cores/nRF5/utility/acilib_types.h new file mode 100644 index 00000000..8430197b --- /dev/null +++ b/cores/nRF5/utility/acilib_types.h @@ -0,0 +1,33 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup group_acilib + * + * @brief Type used in the acilib interfaces + */ + +#ifndef _acilib_TYPES_H_ +#define _acilib_TYPES_H_ + +#endif /* _acilib_TYPES_H_ */ diff --git a/cores/nRF5/utility/app_error.h b/cores/nRF5/utility/app_error.h new file mode 100644 index 00000000..13ae3c86 --- /dev/null +++ b/cores/nRF5/utility/app_error.h @@ -0,0 +1,9 @@ +#ifndef APP_ERROR_H__ +#define APP_ERROR_H__ + +// normally prints error msg if code not NRF_SUCCESS (i.e. 0) +// this implementation does nothing +#define APP_ERROR_CHECK(code) +#define APP_ERROR_CHECK_BOOL(code); + +#endif // APP_ERROR_H__ \ No newline at end of file diff --git a/cores/nRF5/utility/app_scheduler.h b/cores/nRF5/utility/app_scheduler.h new file mode 100644 index 00000000..e07e96c1 --- /dev/null +++ b/cores/nRF5/utility/app_scheduler.h @@ -0,0 +1,242 @@ +/** + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @file + * + * @defgroup app_scheduler Scheduler + * @{ + * @ingroup app_common + * + * @brief The scheduler is used for transferring execution from the interrupt context to the main + * context. + * + * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events + * when using the Scheduler. + * + * @section app_scheduler_req Requirements: + * + * @subsection main_context_logic Logic in main context: + * + * - Define an event handler for each type of event expected. + * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the + * application main loop. + * - Call app_sched_execute() from the main loop each time the application wakes up because of an + * event (typically when sd_app_evt_wait() returns). + * + * @subsection int_context_logic Logic in interrupt context: + * + * - In the interrupt handler, call app_sched_event_put() + * with the appropriate data and event handler. This will insert an event into the + * scheduler's queue. The app_sched_execute() function will pull this event and call its + * handler in the main context. + * + * @if (PERIPHERAL) + * For an example usage of the scheduler, see the implementations of + * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. + * @endif + * + * @image html scheduler_working.svg The high level design of the scheduler + */ + +#ifndef APP_SCHEDULER_H__ +#define APP_SCHEDULER_H__ + + +#include "sdk_config.h" +#include +#include "app_error.h" +#include "utility/app_util.h" + +// uncomment this to enable SCHEDULER TRIGGER QUEUE profiler +//#define SCHEDULER_PROFILER +// then call uint16_t app_sched_queue_utilization_get() to see the max queue size +// can use app_sched_queue_utilization_clear() to clear max usage value back to 0 + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef SCHEDULER_PROFILER +/**@brief Function for getting the maximum observed queue utilization. + * + * Function for tuning the module and determining QUEUE_SIZE value and thus module RAM usage. + * + * @note @ref SCHEDULER_PROFILER must be enabled to use this functionality. + * + * @return Maximum number of events in queue observed so far. + */ +uint16_t app_sched_queue_utilization_get(void); + +// clear max variable +void app_sched_queue_utilization_clear(void); // reset to 0 +#endif // #ifdef SCHEDULER_PROFILER + +#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */ + +/**@brief Compute number of bytes required to hold the scheduler buffer. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @return Required scheduler buffer size (in bytes). + */ +#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \ + (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1)) +// need to add one for sched and on for comp queue + +/**@brief Scheduler event handler type. */ +typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size); + +/**@brief Macro for initializing the event scheduler. + * + * @details It will also handle dimensioning and allocation of the memory buffer required by the + * scheduler, making sure the buffer is correctly aligned. + * + * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. + * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events + * that can be scheduled for execution). + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, e.g. to do a reinitialization). + */ +#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \ + do \ + { \ + static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + +// this version sections off some of the queue for the comparator to use +// added extra count because of extra comparator queue +#define APP_SCHED_COMP_INIT(EVENT_SIZE, QUEUE_SIZE, COMP_QUEUE_SIZE) \ + do \ + { \ + static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), ((QUEUE_SIZE)+(COMP_QUEUE_SIZE)+1)), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_sched_comp_init((EVENT_SIZE), (QUEUE_SIZE),(COMP_QUEUE_SIZE), APP_SCHED_BUF); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + +/**@brief Function for initializing the Scheduler. + * + * @details It must be called before entering the main loop. + * + * @param[in] max_event_size Maximum size of events to be passed through the scheduler. + * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of + * events that can be scheduled for execution). + * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must + * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer + * must be aligned to a 4 byte boundary. + * + * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both + * allocate the scheduler buffer, and also align the buffer correctly. + * + * @retval NRF_SUCCESS Successful initialization. + * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte + * boundary). + */ +uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer); + +uint32_t app_sched_comp_init(uint16_t event_size, uint16_t shed_queue_size, uint16_t comp_queue_size, void * p_event_buffer); + +/**@brief Function for executing all scheduled events. + * + * @details This function must be called from within the main loop. It will execute all events + * scheduled since the last time it was called. + */ +void app_sched_execute(void); + +/**@brief Function for scheduling an event. + * + * @details Puts an event into the event queue. + * + * @param[in] p_event_data Pointer to event data to be scheduled. + * @param[in] event_size Size of event data to be scheduled. + * @param[in] handler Event handler to receive the event. + * + * @return NRF_SUCCESS on success, otherwise an error code. + */ +uint32_t app_sched_event_put(void * p_event_data, + uint16_t event_size, + app_sched_event_handler_t handler); + + + +/**@brief Function for getting the current amount of free space in the queue. + * + * @details The real amount of free space may be less if entries are being added from an interrupt. + * To get the sxact value, this function should be called from the critical section. + * + * @return Amount of free space in the queue. + */ +uint16_t app_sched_queue_space_get(void); + +/**@brief A function to pause the scheduler. + * + * @details When the scheduler is paused events are not pulled from the scheduler queue for + * processing. The function can be called multiple times. To unblock the scheduler the + * function @ref app_sched_resume has to be called the same number of times. + * + * @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality. + */ +void app_sched_pause(void); + +/**@brief A function to resume a scheduler. + * + * @details To unblock the scheduler this function has to be called the same number of times as + * @ref app_sched_pause function. + * + * @note @ref APP_SCHEDULER_WITH_PAUSE must be enabled to use this functionality. + */ +void app_sched_resume(void); + +//uint16_t getCompQueueFullCount(void); // low level develompent debugging +//uint16_t comp_queue_length(void); // not normally used + +#ifdef __cplusplus +} +#endif + +#endif // APP_SCHEDULER_H__ + +/** @} */ diff --git a/cores/nRF5/utility/app_scheduler_serconn.c b/cores/nRF5/utility/app_scheduler_serconn.c new file mode 100644 index 00000000..62c3387a --- /dev/null +++ b/cores/nRF5/utility/app_scheduler_serconn.c @@ -0,0 +1,465 @@ +/** + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "app_scheduler.h" +#include +#include +#include +#include "nrf_soc.h" +#include "nrf_assert.h" +#include "app_util.h" +#include "app_util_platform.h" + +//void cprint(const char* str); +//void cprintNum(const char* str, const uint32_t num); + +/**@brief Structure for holding a scheduled event header. */ +typedef struct +{ + app_sched_event_handler_t handler; /**< Pointer to event handler to receive the event. */ + uint16_t event_data_size; /**< Size of event data. */ +} event_header_t; + +STATIC_ASSERT(sizeof (event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE); + +static event_header_t * m_queue_event_headers; /**< Array for holding the queue event headers. */ +static uint8_t * m_queue_event_data; /**< Array for holding the queue event data. */ +static volatile uint8_t m_queue_start_index; /**< Index of queue entry at the start of the queue. */ +static volatile uint8_t m_queue_end_index; /**< Index of queue entry at the end of the queue. */ +static volatile uint8_t m_comp_queue_start_index; /**< Index of comparator queue entry at the start of the queue. */ +static volatile uint8_t m_comp_queue_end_index; /**< Index of comparator queue entry at the end of the queue. */ +static uint16_t m_queue_event_size; /**< Maximum event size in queue. */ +static uint16_t m_queue_size; /**< Number of non-comparator queue entries. */ +static uint16_t m_total_queue_size; /**< Number of all queue entries. */ +static uint16_t m_comp_queue_size; // only used for get_comp_queue_len + +#ifdef SCHEDULER_PROFILER +static uint16_t m_max_queue_utilization; /**< Maximum observed queue utilization. */ +#endif + +static uint32_t m_scheduler_paused_counter = 0; /**< Counter storing the difference between pausing + and resuming the scheduler. */ + +/**@brief Function for incrementing a queue index, and handle wrap-around. + * + * @param[in] index Old index. + * + * @return New (incremented) index. + */ +static __INLINE uint8_t next_index(uint8_t index) +{ + return (index < m_queue_size) ? (index + 1) : 0; // goes from 0 to m_queue_size +} + +static __INLINE uint8_t app_sched_queue_full(void) +{ + uint8_t tmp = m_queue_start_index; + return next_index(m_queue_end_index) == tmp; +} + +/**@brief Macro for checking if a queue is full. */ +#define APP_SCHED_QUEUE_FULL() app_sched_queue_full() + +static __INLINE uint8_t app_sched_queue_empty(void) +{ + uint8_t tmp = m_queue_start_index; + return m_queue_end_index == tmp; +} + +/**@brief Macro for checking if a queue is empty. */ +#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty() + + +// ================== comp queue methods +// idx runs from m_queue_size to m_total_queue_size +// i.e. the second section of the queue +static __INLINE uint8_t next_comp_index(uint8_t index) { + return (index < m_total_queue_size) ? (index + 1) : (m_queue_size+1); + // start at end if schedule queue goes from m_queue_size+1 to m_total_queue_size inclusive +} + +static __INLINE uint8_t prev_comp_index(uint8_t index) { + return (index > (m_queue_size+1)) ? (index -1) : (m_total_queue_size); + // start at end if schedule queue goes from m_queue_size+1 to m_total_queue_size inclusive +} + +static __INLINE uint8_t app_sched_comp_queue_full(void) { + uint8_t tmp = m_comp_queue_start_index; + return next_comp_index(m_comp_queue_end_index) == tmp; +} + +/**@brief Macro for checking if a queue is full. */ +#define APP_SCHED_COMP_QUEUE_FULL() app_sched_comp_queue_full() + +static __INLINE uint8_t app_sched_comp_queue_empty(void) { + uint8_t tmp = m_comp_queue_start_index; + return m_comp_queue_end_index == tmp; +} + +/**@brief Macro for checking if a queue is empty. */ +#define APP_SCHED_COMP_QUEUE_EMPTY() app_sched_comp_queue_empty() + + + +uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer) +{ + uint16_t data_start_index = (queue_size + 1) * sizeof (event_header_t); + + //Check that buffer is correctly aligned + if (!is_word_aligned(p_event_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + + //Initialize event scheduler + m_queue_event_headers = p_event_buffer; + m_queue_event_data = &((uint8_t *)p_event_buffer)[data_start_index]; + m_queue_end_index = 0; + m_queue_start_index = 0; + m_queue_event_size = event_size; + m_queue_size = queue_size; + +#ifdef SCHEDULER_PROFILER + m_max_queue_utilization = 0; +#endif + + return NRF_SUCCESS; +} + +uint32_t app_sched_comp_init(uint16_t event_size, uint16_t shed_queue_size, uint16_t comp_queue_size, void * p_event_buffer) +{ + uint16_t total_queue_size = shed_queue_size + comp_queue_size+1; // add one here to allow for comp_queue + uint16_t data_start_index = (total_queue_size + 1) * sizeof (event_header_t); + + //Check that buffer is correctly aligned + if (!is_word_aligned(p_event_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + + //Initialize event scheduler + m_queue_event_headers = p_event_buffer; + m_queue_event_data = &((uint8_t *)p_event_buffer)[data_start_index]; + m_queue_end_index = 0; + m_queue_start_index = 0; + m_queue_event_size = event_size; + m_queue_size = shed_queue_size; // used in next_index + + m_comp_queue_end_index = shed_queue_size+1; // sched queue uses idx 0 to m_queue_size inclusive + m_comp_queue_start_index = shed_queue_size+1; + m_comp_queue_size = comp_queue_size; // only used in get_comp_queue_len + m_total_queue_size = total_queue_size; // used in next_comp_index, comp_queue uses idx m_total_queue_size+1 + +#ifdef SCHEDULER_PROFILER + m_max_queue_utilization = 0; +#endif + + return NRF_SUCCESS; +} + + +// this uses CRITICAL_REGION_ENTER do not nest in CRITICAL_REGION_ENTER +//uint16_t app_sched_queue_space_get() { +// uint16_t start,end; +// CRITICAL_REGION_ENTER(); +// start = m_queue_start_index; +// end = m_queue_end_index; +// CRITICAL_REGION_EXIT(); + +// uint16_t free_space = m_queue_size - ((end >= start) ? +// (end - start) : (m_queue_size + 1 - start + end)); +// return free_space; +//} + + +#ifdef SCHEDULER_PROFILER +static __INLINE void check_queue_utilization(void) +{ + uint16_t start = m_queue_start_index; + uint16_t end = m_queue_end_index; + uint16_t queue_utilization = (end >= start) ? (end - start) : + (m_queue_size + 1 - start + end); + + if (queue_utilization > m_max_queue_utilization) + { + m_max_queue_utilization = queue_utilization; + } +} + +// reset to 0 +void app_sched_queue_utilization_clear(void) { + m_max_queue_utilization = 0; +} + +uint16_t app_sched_queue_utilization_get(void) { + return m_max_queue_utilization; +} +#endif // SCHEDULER_PROFILER + + +uint32_t app_sched_event_put(void * p_event_data, + uint16_t event_data_size, + app_sched_event_handler_t handler) +{ + uint32_t err_code; + + if (event_data_size <= m_queue_event_size) + { + uint16_t event_index = 0xFFFF; + + CRITICAL_REGION_ENTER(); + + if (!APP_SCHED_QUEUE_FULL()) + { + event_index = m_queue_end_index; + m_queue_end_index = next_index(m_queue_end_index); + #ifdef SCHEDULER_PROFILER + // This function call must be protected with critical region because + // it modifies 'm_max_queue_utilization'. + check_queue_utilization(); + #endif + } + + CRITICAL_REGION_EXIT(); + + if (event_index != 0xFFFF) + { + //NOTE: This can be done outside the critical region since the event consumer will + //always be called from the main loop, and will thus never interrupt this code. + m_queue_event_headers[event_index].handler = handler; + if ((p_event_data != NULL) && (event_data_size > 0)) + { + memcpy(&m_queue_event_data[event_index * m_queue_event_size], + p_event_data, + event_data_size); + m_queue_event_headers[event_index].event_data_size = event_data_size; + } + else + { + m_queue_event_headers[event_index].event_data_size = 0; + } + + err_code = NRF_SUCCESS; + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + else + { + err_code = NRF_ERROR_INVALID_LENGTH; + } + + return err_code; +} + + +/**@brief Function for reading the next event from specified event queue. + * + * @param[out] pp_event_data Pointer to pointer to event data. + * @param[out] p_event_data_size Pointer to size of event data. + * @param[out] p_event_handler Pointer to event handler function pointer. + * + * @return NRF_SUCCESS if new event, NRF_ERROR_NOT_FOUND if event queue is empty. + */ +static uint32_t app_sched_event_get(void * * pp_event_data, + uint16_t * p_event_data_size, + app_sched_event_handler_t * p_event_handler) +{ + uint32_t err_code = NRF_ERROR_NOT_FOUND; + + if (!APP_SCHED_QUEUE_EMPTY()) + { + uint16_t event_index; + + //NOTE: There is no need for a critical region here, as this function will only be called + //from app_sched_execute() from inside the main loop, so it will never interrupt + //app_sched_event_put(). Also, updating of (i.e. writing to) the start index will be + //an atomic operation. + event_index = m_queue_start_index; +// m_queue_start_index = next_index(m_queue_start_index); //defer until after processing event + + *pp_event_data = &m_queue_event_data[event_index * m_queue_event_size]; + *p_event_data_size = m_queue_event_headers[event_index].event_data_size; + *p_event_handler = m_queue_event_headers[event_index].handler; + + err_code = NRF_SUCCESS; + } + + return err_code; +} + + +// =========== comp methods + +//uint16_t get_comp_queue_length(void) { +// uint16_t start = m_comp_queue_start_index; +// uint16_t end = m_comp_queue_end_index; +// return (end >= start) ? (end - start) : (m_comp_queue_size + 1 + end -start); +//} + +/**@brief Function for checking if scheduler is paused which means that should break processing + * events. + * + * @return Boolean value - true if scheduler is paused, false otherwise. + */ +static __INLINE bool is_app_sched_comp_paused(void) +{ + return (m_scheduler_paused_counter > 0); +} + +//static uint16_t m_comp_queue_full_count; +//uint16_t getCompQueueFullCount() { +// return m_comp_queue_full_count; +//} + +// isHigh == 1 if HIGH or 0 if LOW +void app_sched_comp_event_put(uint16_t isHigh, app_sched_event_handler_t handler) { + uint16_t event_index; + CRITICAL_REGION_ENTER(); + if (!APP_SCHED_COMP_QUEUE_FULL()) { + event_index = m_comp_queue_end_index; + m_comp_queue_end_index = next_comp_index(m_comp_queue_end_index); + } else { + event_index = prev_comp_index(m_comp_queue_end_index); // update last one + // m_comp_queue_full_count++; + } + CRITICAL_REGION_EXIT(); + //NOTE: This can be done outside the critical region since the event consumer will + //always be called from the main loop, and will thus never interrupt this code. + m_queue_event_headers[event_index].handler = handler; + m_queue_event_headers[event_index].event_data_size = isHigh; +// cprintNum("put:",event_index); +// cprint((isHigh?"H":"L")); +// cprintNum("pL:",get_comp_queue_length()); +} + +/**@brief Function for reading the next event from specified event queue. + * + * @param[out] pp_event_data Pointer to pointer to event data. + * @param[out] p_event_data_size Pointer to size of event data. + * @param[out] p_event_handler Pointer to event handler function pointer. + * + * @return NRF_SUCCESS if new event, NRF_ERROR_NOT_FOUND if event queue is empty. + */ +static uint32_t app_sched_comp_event_get(uint16_t *p_isHigh, app_sched_event_handler_t *p_event_handler) { + uint32_t err_code = NRF_ERROR_NOT_FOUND; + + if (!APP_SCHED_COMP_QUEUE_EMPTY()) { + uint16_t event_index; + + //NOTE: There is no need for a critical region here, as this function will only be called + //from app_sched_execute() from inside the main loop, so it will never interrupt + //app_sched_event_put(). Also, updating of (i.e. writing to) the start index will be + //an atomic operation. + event_index = m_comp_queue_start_index; + // m_comp_queue_start_index = next_comp_index(m_comp_queue_start_index); // defer unti AFTER processing event +//cprintNum("get:",event_index); +//cprintNum("gL:",get_comp_queue_length()); + *p_isHigh = m_queue_event_headers[event_index].event_data_size; + *p_event_handler = m_queue_event_headers[event_index].handler; + + err_code = NRF_SUCCESS; + } + return err_code; +} + +void app_sched_comp_execute(void){ + uint16_t isHigh; + app_sched_event_handler_t event_handler; + //Get next event (if any), and execute handler + while ((!is_app_sched_comp_paused()) && + (app_sched_comp_event_get(&isHigh, &event_handler) == NRF_SUCCESS)) { + event_handler(NULL, isHigh); + m_comp_queue_start_index = next_comp_index(m_comp_queue_start_index); // defer unti AFTER processing event + } +} + + +//=================================================== + + +void app_sched_pause(void) +{ + CRITICAL_REGION_ENTER(); + + if (m_scheduler_paused_counter < UINT32_MAX) + { + m_scheduler_paused_counter++; + } + CRITICAL_REGION_EXIT(); +} + + +void app_sched_resume(void) +{ + CRITICAL_REGION_ENTER(); + + if (m_scheduler_paused_counter > 0) + { + m_scheduler_paused_counter--; + } + CRITICAL_REGION_EXIT(); +} + +/**@brief Function for checking if scheduler is paused which means that should break processing + * events. + * + * @return Boolean value - true if scheduler is paused, false otherwise. + */ +static __INLINE bool is_app_sched_paused(void) +{ + return (m_scheduler_paused_counter > 0); +} + +void app_sched_execute(void) +{ + void * p_event_data; + uint16_t event_data_size; + app_sched_event_handler_t event_handler; + + //Get next event (if any), and execute handler + while ((!is_app_sched_paused()) && + (app_sched_event_get(&p_event_data, &event_data_size, &event_handler) == NRF_SUCCESS)) { + event_handler(p_event_data, event_data_size); + m_queue_start_index = next_index(m_queue_start_index); // after processing event!! + } +} diff --git a/cores/nRF5/utility/app_timer.c b/cores/nRF5/utility/app_timer.c new file mode 100644 index 00000000..1dd75de1 --- /dev/null +++ b/cores/nRF5/utility/app_timer.c @@ -0,0 +1,1139 @@ +/** + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sdk_common.h" +//#if NRF_MODULE_ENABLED(APP_TIMER) +#include "app_timer.h" +#include +#include "nrf.h" +#include "nrf_soc.h" +#include "app_error.h" +#include "nrf_delay.h" +#include "app_util_platform.h" + +// stop rtc1 when no timers running +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 + +#define RTC1_IRQ_PRI APP_IRQ_PRIORITY_LOWEST /**< Priority of the RTC1 interrupt (used for checking for timeouts and executing timeout handlers). */ +#define SWI_IRQ_PRI APP_IRQ_PRIORITY_LOWEST /**< Priority of the SWI interrupt (used for updating the timer list). */ + +// The current design assumes that both interrupt handlers run at the same interrupt level. +// If this is to be changed, protection must be added to prevent them from interrupting each other +// (e.g. by using guard/trigger flags). +STATIC_ASSERT(RTC1_IRQ_PRI == SWI_IRQ_PRI); + +#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ + +#define RTC_COMPARE_OFFSET_MIN 3 /**< Minimum offset between the current RTC counter value and the Capture Compare register. Although the nRF51 Series User Specification recommends this value to be 2, we use 3 to be safer.*/ + +#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */ + +#define SWI_IRQn SWI0_IRQn +#define SWI_IRQHandler SWI0_IRQHandler + +#define MODULE_INITIALIZED (m_op_queue.p_user_op_queue != NULL) /**< Macro designating whether the module has been initialized properly. */ + +/**@brief Timer node type. The nodes will be used form a linked list of running timers. */ +typedef struct +{ + uint32_t ticks_to_expire; /**< Number of ticks from previous timer interrupt to timer expiry. */ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + bool is_running; /**< True if timer is running, False otherwise. */ + app_timer_mode_t mode; /**< Timer mode. */ + app_timer_timeout_handler_t p_timeout_handler; /**< Pointer to function to be executed when the timer expires. */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ + void * next; /**< Pointer to the next node. */ +} timer_node_t; + +STATIC_ASSERT(sizeof(timer_node_t) == APP_TIMER_NODE_SIZE); + +/**@brief Set of available timer operation types. */ +typedef enum +{ + TIMER_USER_OP_TYPE_NONE, /**< Invalid timer operation type. */ + TIMER_USER_OP_TYPE_START, /**< Timer operation type Start. */ + TIMER_USER_OP_TYPE_STOP, /**< Timer operation type Stop. */ + TIMER_USER_OP_TYPE_STOP_ALL /**< Timer operation type Stop All. */ +} timer_user_op_type_t; + +/**@brief Structure describing a timer start operation. */ +typedef struct +{ + uint32_t ticks_at_start; /**< Current RTC counter value when the timer was started. */ + uint32_t ticks_first_interval; /**< Number of ticks in the first timer interval. */ + uint32_t ticks_periodic_interval; /**< Timer period (for repeating timers). */ + void * p_context; /**< General purpose pointer. Will be passed to the timeout handler when the timer expires. */ +} timer_user_op_start_t; + +/**@brief Structure describing a timer operation. */ +typedef struct +{ + timer_user_op_type_t op_type; /**< Id of timer on which the operation is to be performed. */ + timer_node_t * p_node; + union + { + timer_user_op_start_t start; /**< Structure describing a timer start operation. */ + } params; +} timer_user_op_t; + +STATIC_ASSERT(sizeof(timer_user_op_t) <= APP_TIMER_USER_OP_SIZE); +STATIC_ASSERT(sizeof(timer_user_op_t) % 4 == 0); + +/**@brief Structure describing a timer operations queue. + * + * @details This queue will hold timer operations issued by the application + * until the timer interrupt handler processes these operations. + */ +typedef struct +{ + uint8_t first; /**< Index of first entry to have been inserted in the queue (i.e. the next entry to be executed). */ + uint8_t last; /**< Index of last entry to have been inserted in the queue. */ + uint8_t size; /**< Queue size. */ + timer_user_op_t * p_user_op_queue; /**< Queue buffer. */ +} timer_op_queue_t; + +STATIC_ASSERT(sizeof(timer_op_queue_t) % 4 == 0); + +#define CONTEXT_QUEUE_SIZE_MAX (2) + +static timer_op_queue_t m_op_queue; /**< Timer operations queue. */ +static timer_node_t * mp_timer_id_head; /**< First timer in list of running timers. */ +static uint32_t m_ticks_latest; /**< Last known RTC counter value. */ +static uint32_t m_ticks_elapsed[CONTEXT_QUEUE_SIZE_MAX]; /**< Timer internal elapsed ticks queue. */ +static uint8_t m_ticks_elapsed_q_read_ind; /**< Timer internal elapsed ticks queue read index. */ +static uint8_t m_ticks_elapsed_q_write_ind; /**< Timer internal elapsed ticks queue write index. */ +static app_timer_evt_schedule_func_t m_evt_schedule_func; /**< Pointer to function for propagating timeout events to the scheduler. */ +static bool m_rtc1_running; /**< Boolean indicating if RTC1 is running. */ +static bool m_rtc1_reset; /**< Boolean indicating if RTC1 counter has been reset due to last timer removed from timer list during the timer list handling. */ + +#if APP_TIMER_WITH_PROFILER +static uint8_t m_max_user_op_queue_utilization; /**< Maximum observed timer user operations queue utilization. */ +#endif + +static volatile uint32_t overflows = 0; +static uint32_t prescaler = 1; // initialized by call to rtc1_init( ) below + + +uint32_t millis( void ) { + uint64_t ticks = (uint64_t)((uint64_t)overflows << (uint64_t)24) | (uint64_t)(NRF_RTC1->COUNTER); + + return (ticks * 1000) / (32768/prescaler); +} + +uint32_t micros( void ) { + uint64_t ticks = (uint64_t)((uint64_t)overflows << (uint64_t)24) | (uint64_t)(NRF_RTC1->COUNTER); + + return (ticks * 1000000) / (32768/prescaler); +} + +void delay( uint32_t ms ) { + if ( ms == 0 ) { + return ; + } + + uint32_t start = millis() ; + + do { + yield() ; + } while ( millis() - start < ms ) ; +} + + +/**@brief Function for initializing the RTC1 counter. + * + * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. + */ +static void rtc1_init(uint32_t _prescaler) { + prescaler = _prescaler+1; + NRF_RTC1->PRESCALER = _prescaler; + NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI); +} + + +/**@brief Function for starting the RTC1 timer. + */ +static void rtc1_start(void) +{ + NRF_RTC1->EVTENSET = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk; + // for millis + NRF_RTC1->INTENSET = RTC_INTENSET_OVRFLW_Msk; + NRF_RTC1->EVTENSET = RTC_EVTEN_OVRFLW_Msk; + + + NVIC_ClearPendingIRQ(RTC1_IRQn); + NVIC_EnableIRQ(RTC1_IRQn); + + NRF_RTC1->TASKS_START = 1; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + m_rtc1_running = true; +} + + +/**@brief Function for stopping the RTC1 timer. + */ +static void rtc1_stop(void) +{ + NVIC_DisableIRQ(RTC1_IRQn); + + NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; + NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk; + + NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk; + NRF_RTC1->INTENCLR = RTC_INTENSET_OVRFLW_Msk; + + NRF_RTC1->TASKS_STOP = 1; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + NRF_RTC1->TASKS_CLEAR = 1; + m_ticks_latest = 0; + nrf_delay_us(MAX_RTC_TASKS_DELAY); + + m_rtc1_running = false; +} + + +/**@brief Function for returning the current value of the RTC1 counter. + * + * @return Current value of the RTC1 counter. + */ +static __INLINE uint32_t rtc1_counter_get(void) +{ + return NRF_RTC1->COUNTER; +} + + +/**@brief Function for computing the difference between two RTC1 counter values. + * + * @return Number of ticks elapsed from ticks_old to ticks_now. + */ +static __INLINE uint32_t ticks_diff_get(uint32_t ticks_now, uint32_t ticks_old) +{ + return ((ticks_now - ticks_old) & MAX_RTC_COUNTER_VAL); +} + + +/**@brief Function for setting the RTC1 Capture Compare register 0, and enabling the corresponding + * event. + * + * @param[in] value New value of Capture Compare register 0. + */ +static __INLINE void rtc1_compare0_set(uint32_t value) +{ + NRF_RTC1->CC[0] = value; +} + + +/**@brief Function for inserting a timer in the timer list. + * + * @param[in] timer_id Id of timer to insert. + */ +static void timer_list_insert(timer_node_t * p_timer) +{ + if (mp_timer_id_head == NULL) + { + mp_timer_id_head = p_timer; + } + else + { + if (p_timer->ticks_to_expire <= mp_timer_id_head->ticks_to_expire) + { + mp_timer_id_head->ticks_to_expire -= p_timer->ticks_to_expire; + + p_timer->next = mp_timer_id_head; + mp_timer_id_head = p_timer; + } + else + { + timer_node_t * p_previous; + timer_node_t * p_current; + uint32_t ticks_to_expire; + + ticks_to_expire = p_timer->ticks_to_expire; + p_previous = mp_timer_id_head; + p_current = mp_timer_id_head; + + while ((p_current != NULL) && (ticks_to_expire > p_current->ticks_to_expire)) + { + ticks_to_expire -= p_current->ticks_to_expire; + p_previous = p_current; + p_current = p_current->next; + } + + if (p_current != NULL) + { + p_current->ticks_to_expire -= ticks_to_expire; + } + + p_timer->ticks_to_expire = ticks_to_expire; + p_timer->next = p_current; + p_previous->next = p_timer; + } + } +} + + +/**@brief Function for removing a timer from the timer queue. + * + * @param[in] timer_id Id of timer to remove. + */ +static void timer_list_remove(timer_node_t * p_timer) +{ + timer_node_t * p_previous; + timer_node_t * p_current; + uint32_t timeout; + + // Find the timer's position in timer list. + p_previous = mp_timer_id_head; + p_current = p_previous; + + while (p_current != NULL) + { + if (p_current == p_timer) + { + break; + } + p_previous = p_current; + p_current = p_current->next; + } + + // Timer not in active list. + if (p_current == NULL) + { + return; + } + + // Timer is the first in the list + if (p_previous == p_current) + { + mp_timer_id_head = mp_timer_id_head->next; + + // No more timers in the list. Reset RTC1 in case Start timer operations are present in the queue. + if (mp_timer_id_head == NULL) + { + NRF_RTC1->TASKS_CLEAR = 1; + m_ticks_latest = 0; + m_rtc1_reset = true; + } + } + + // Remaining timeout between next timeout. + timeout = p_current->ticks_to_expire; + + // Link previous timer with next of this timer, i.e. removing the timer from list. + p_previous->next = p_current->next; + + // If this is not the last timer, increment the next timer by this timer timeout. + p_current = p_previous->next; + if (p_current != NULL) + { + p_current->ticks_to_expire += timeout; + } +} + + +/**@brief Function for scheduling a check for timeouts by generating a RTC1 interrupt. + */ +static void timer_timeouts_check_sched(void) +{ + NVIC_SetPendingIRQ(RTC1_IRQn); +} + + +/**@brief Function for scheduling a timer list update by generating a SWI interrupt. + */ +static void timer_list_handler_sched(void) +{ + NVIC_SetPendingIRQ(SWI_IRQn); +} + + +/**@brief Function for executing an application timeout handler, either by calling it directly, or + * by passing an event to the @ref app_scheduler. + * + * @param[in] p_timer Pointer to expired timer. + */ +static void timeout_handler_exec(timer_node_t * p_timer) +{ + if (m_evt_schedule_func != NULL) + { + uint32_t err_code = m_evt_schedule_func(p_timer->p_timeout_handler, p_timer->p_context); + APP_ERROR_CHECK(err_code); + } + else + { + p_timer->p_timeout_handler(p_timer->p_context); + } +} + + +/**@brief Function for checking for expired timers. + */ +static void timer_timeouts_check(void) +{ + // Handle expired of timer + if (mp_timer_id_head != NULL) + { + timer_node_t * p_timer; + timer_node_t * p_previous_timer; + uint32_t ticks_elapsed; + uint32_t ticks_expired; + + // Initialize actual elapsed ticks being consumed to 0. + ticks_expired = 0; + + // ticks_elapsed is collected here, job will use it. + ticks_elapsed = ticks_diff_get(rtc1_counter_get(), m_ticks_latest); + + // Auto variable containing the head of timers expiring. + p_timer = mp_timer_id_head; + + // Expire all timers within ticks_elapsed and collect ticks_expired. + while (p_timer != NULL) + { + // Do nothing if timer did not expire. + if (ticks_elapsed < p_timer->ticks_to_expire) + { + break; + } + + // Decrement ticks_elapsed and collect expired ticks. + ticks_elapsed -= p_timer->ticks_to_expire; + ticks_expired += p_timer->ticks_to_expire; + + // Move to next timer. + p_previous_timer = p_timer; + p_timer = p_timer->next; + + // Execute Task. + if (p_previous_timer->is_running) + { + p_previous_timer->is_running = false; + timeout_handler_exec(p_previous_timer); + } + } + + // Prepare to queue the ticks expired in the m_ticks_elapsed queue. + if (m_ticks_elapsed_q_read_ind == m_ticks_elapsed_q_write_ind) + { + // The read index of the queue is equal to the write index. This means the new + // value of ticks_expired should be stored at a new location in the m_ticks_elapsed + // queue (which is implemented as a double buffer). + + // Check if there will be a queue overflow. + if (++m_ticks_elapsed_q_write_ind == CONTEXT_QUEUE_SIZE_MAX) + { + // There will be a queue overflow. Hence the write index should point to the start + // of the queue. + m_ticks_elapsed_q_write_ind = 0; + } + } + + // Queue the ticks expired. + m_ticks_elapsed[m_ticks_elapsed_q_write_ind] = ticks_expired; + + timer_list_handler_sched(); + } +} + + +/**@brief Function for acquiring the number of ticks elapsed. + * + * @param[out] p_ticks_elapsed Number of ticks elapsed. + * + * @return TRUE if elapsed ticks was read from queue, FALSE otherwise. + */ +static bool elapsed_ticks_acquire(uint32_t * p_ticks_elapsed) +{ + // Pick the elapsed value from queue. + if (m_ticks_elapsed_q_read_ind != m_ticks_elapsed_q_write_ind) + { + // Dequeue elapsed value. + m_ticks_elapsed_q_read_ind++; + if (m_ticks_elapsed_q_read_ind == CONTEXT_QUEUE_SIZE_MAX) + { + m_ticks_elapsed_q_read_ind = 0; + } + + *p_ticks_elapsed = m_ticks_elapsed[m_ticks_elapsed_q_read_ind]; + + m_ticks_latest += *p_ticks_elapsed; + m_ticks_latest &= MAX_RTC_COUNTER_VAL; + + return true; + } + else + { + // No elapsed value in queue. + *p_ticks_elapsed = 0; + return false; + } +} + + +/**@brief Function for handling the timer list deletions. + * + * @return TRUE if Capture Compare register must be updated, FALSE otherwise. + */ +static bool list_deletions_handler(void) +{ + timer_node_t * p_timer_old_head; + uint8_t user_ops_first = m_op_queue.first; + + // Remember the old head, so as to decide if new compare needs to be set. + p_timer_old_head = mp_timer_id_head; + + while (user_ops_first != m_op_queue.last) + { + timer_user_op_t * p_user_op = &m_op_queue.p_user_op_queue[user_ops_first]; + + // Traverse to next operation in queue. + user_ops_first++; + if (user_ops_first == m_op_queue.size) + { + user_ops_first = 0; + } + + switch (p_user_op->op_type) + { + case TIMER_USER_OP_TYPE_STOP: + // Delete node if timer is running. + timer_list_remove(p_user_op->p_node); + break; + + case TIMER_USER_OP_TYPE_STOP_ALL: + // Delete list of running timers, and mark all timers as not running. + while (mp_timer_id_head != NULL) + { + timer_node_t * p_head = mp_timer_id_head; + + p_head->is_running = false; + mp_timer_id_head = p_head->next; + } + break; + + default: + // No implementation needed. + break; + } + } + + // Detect change in head of the list. + return (mp_timer_id_head != p_timer_old_head); +} + + +/**@brief Function for updating the timer list for expired timers. + * + * @param[in] ticks_elapsed Number of elapsed ticks. + * @param[in] ticks_previous Previous known value of the RTC counter. + * @param[out] p_restart_list_head List of repeating timers to be restarted. + */ +static void expired_timers_handler(uint32_t ticks_elapsed, + uint32_t ticks_previous, + timer_node_t ** p_restart_list_head) +{ + uint32_t ticks_expired = 0; + + while (mp_timer_id_head != NULL) + { + timer_node_t * p_timer; + timer_node_t * p_timer_expired; + + // Auto variable for current timer node. + p_timer = mp_timer_id_head; + + // Do nothing if timer did not expire + if (ticks_elapsed < p_timer->ticks_to_expire) + { + p_timer->ticks_to_expire -= ticks_elapsed; + break; + } + + // Decrement ticks_elapsed and collect expired ticks. + ticks_elapsed -= p_timer->ticks_to_expire; + ticks_expired += p_timer->ticks_to_expire; + + // Timer expired, set ticks_to_expire zero. + p_timer->ticks_to_expire = 0; + + // Remove the expired timer from head. + p_timer_expired = mp_timer_id_head; + mp_timer_id_head = p_timer->next; + + // Timer will be restarted if periodic. + if (p_timer->ticks_periodic_interval != 0) + { + p_timer->ticks_at_start = (ticks_previous + ticks_expired) & MAX_RTC_COUNTER_VAL; + p_timer->ticks_first_interval = p_timer->ticks_periodic_interval; + p_timer->next = *p_restart_list_head; + *p_restart_list_head = p_timer_expired; + } + } +} + + +/**@brief Function for handling timer list insertions. + * + * @param[in] p_restart_list_head List of repeating timers to be restarted. + * + * @return TRUE if Capture Compare register must be updated, FALSE otherwise. + */ +static bool list_insertions_handler(timer_node_t * p_restart_list_head) +{ + timer_node_t * p_timer_id_old_head; + + // Remember the old head, so as to decide if new compare needs to be set. + p_timer_id_old_head = mp_timer_id_head; + + // Handle insertions of timers. + while ((p_restart_list_head != NULL) || (m_op_queue.first != m_op_queue.last)) + { + timer_node_t * p_timer; + + if (p_restart_list_head != NULL) + { + p_timer = p_restart_list_head; + p_restart_list_head = p_timer->next; + } + else + { + timer_user_op_t * p_user_op = &m_op_queue.p_user_op_queue[m_op_queue.first]; + + m_op_queue.first++; + if (m_op_queue.first == m_op_queue.size) + { + m_op_queue.first = 0; + } + + p_timer = p_user_op->p_node; + + if ((p_user_op->op_type != TIMER_USER_OP_TYPE_START) || p_timer->is_running) + { + continue; + } + + p_timer->ticks_at_start = p_user_op->params.start.ticks_at_start; + p_timer->ticks_first_interval = p_user_op->params.start.ticks_first_interval; + p_timer->ticks_periodic_interval = p_user_op->params.start.ticks_periodic_interval; + p_timer->p_context = p_user_op->params.start.p_context; + + if (m_rtc1_reset) + { + p_timer->ticks_at_start = 0; + } + } + + // Prepare the node to be inserted. + if ( + ((p_timer->ticks_at_start - m_ticks_latest) & MAX_RTC_COUNTER_VAL) + < + (MAX_RTC_COUNTER_VAL / 2) + ) + { + p_timer->ticks_to_expire = ticks_diff_get(p_timer->ticks_at_start, m_ticks_latest) + + p_timer->ticks_first_interval; + } + else + { + uint32_t delta_current_start; + + delta_current_start = ticks_diff_get(m_ticks_latest, p_timer->ticks_at_start); + if (p_timer->ticks_first_interval > delta_current_start) + { + p_timer->ticks_to_expire = p_timer->ticks_first_interval - delta_current_start; + } + else + { + p_timer->ticks_to_expire = 0; + } + } + + p_timer->ticks_at_start = 0; + p_timer->ticks_first_interval = 0; + p_timer->is_running = true; + p_timer->next = NULL; + + // Insert into list + timer_list_insert(p_timer); + } + + return (mp_timer_id_head != p_timer_id_old_head); +} + + +/**@brief Function for updating the Capture Compare register. + */ +static void compare_reg_update(timer_node_t * p_timer_id_head_old) +{ + // Setup the timeout for timers on the head of the list + if (mp_timer_id_head != NULL) + { + uint32_t ticks_to_expire = mp_timer_id_head->ticks_to_expire; + uint32_t pre_counter_val = rtc1_counter_get(); + uint32_t cc = m_ticks_latest; + uint32_t ticks_elapsed = ticks_diff_get(pre_counter_val, cc) + RTC_COMPARE_OFFSET_MIN; + + if (!m_rtc1_running) + { + // No timers were already running, start RTC + rtc1_start(); + } + + cc += (ticks_elapsed < ticks_to_expire) ? ticks_to_expire : ticks_elapsed; + cc &= MAX_RTC_COUNTER_VAL; + + rtc1_compare0_set(cc); + + uint32_t post_counter_val = rtc1_counter_get(); + + if ( + (ticks_diff_get(post_counter_val, pre_counter_val) + RTC_COMPARE_OFFSET_MIN) + > + ticks_diff_get(cc, pre_counter_val) + ) + { + // When this happens the COMPARE event may not be triggered by the RTC. + // The nRF51 Series User Specification states that if the COUNTER value is N + // (i.e post_counter_val = N), writing N or N + 1 to a CC register may not trigger a + // COMPARE event. Hence the RTC interrupt is forcefully pended by calling the following + // function. + rtc1_compare0_set(rtc1_counter_get()); // this should prevent CC to fire again in the background while the code is in RTC-ISR + nrf_delay_us(MAX_RTC_TASKS_DELAY); + timer_timeouts_check_sched(); + } + } + else + { +#if (APP_TIMER_KEEPS_RTC_ACTIVE == 0) + // No timers are running, stop RTC +// rtc1_stop(); +#endif //(APP_TIMER_KEEPS_RTC_ACTIVE == 0) + } +} + + +/**@brief Function for handling changes to the timer list. + */ +static void timer_list_handler(void) +{ + timer_node_t * p_restart_list_head = NULL; + + uint32_t ticks_elapsed; + uint32_t ticks_previous; + bool ticks_have_elapsed; + bool compare_update; + timer_node_t * p_timer_id_head_old; + +#if APP_TIMER_WITH_PROFILER + { + uint8_t size = m_op_queue.size; + uint8_t first = m_op_queue.first; + uint8_t last = m_op_queue.last; + uint8_t utilization = (first <= last) ? (last - first) : (size + 1 - first + last); + + if (utilization > m_max_user_op_queue_utilization) + { + m_max_user_op_queue_utilization = utilization; + } + } +#endif + + // Back up the previous known tick and previous list head + ticks_previous = m_ticks_latest; + p_timer_id_head_old = mp_timer_id_head; + + // Get number of elapsed ticks + ticks_have_elapsed = elapsed_ticks_acquire(&ticks_elapsed); + + // Handle list deletions + compare_update = list_deletions_handler(); + + // Handle expired timers + if (ticks_have_elapsed) + { + expired_timers_handler(ticks_elapsed, ticks_previous, &p_restart_list_head); + compare_update = true; + } + + // Handle list insertions + if (list_insertions_handler(p_restart_list_head)) + { + compare_update = true; + } + + // Update compare register if necessary + if (compare_update) + { + compare_reg_update(p_timer_id_head_old); + } + m_rtc1_reset = false; +} + + +/**@brief Function for enqueueing a new operations queue entry. + * + * @param[in] last_index Index of the next last index to be enqueued. + */ +static void user_op_enque(uint8_t last_index) +{ + m_op_queue.last = last_index; +} + + +/**@brief Function for allocating a new operations queue entry. + * + * @param[out] p_last_index Index of the next last index to be enqueued. + * + * @return Pointer to allocated queue entry, or NULL if queue is full. + */ +static timer_user_op_t * user_op_alloc( uint8_t * p_last_index) +{ + uint8_t last; + timer_user_op_t * p_user_op; + + last = m_op_queue.last + 1; + if (last == m_op_queue.size) + { + // Overflow case. + last = 0; + } + if (last == m_op_queue.first) + { + // Queue is full. + return NULL; + } + + *p_last_index = last; + p_user_op = &m_op_queue.p_user_op_queue[m_op_queue.last]; + + return p_user_op; +} + + +/**@brief Function for scheduling a Timer Start operation. + * + * @param[in] timer_id Id of timer to start. + * @param[in] timeout_initial Time (in ticks) to first timer expiry. + * @param[in] timeout_periodic Time (in ticks) between periodic expiries. + * @param[in] p_context General purpose pointer. Will be passed to the timeout handler when + * the timer expires. + * @return NRF_SUCCESS on success, otherwise an error code. + */ + +static uint32_t timer_start_op_schedule(timer_node_t * p_node, + uint32_t timeout_initial, + uint32_t timeout_periodic, + void * p_context) +{ + uint8_t last_index; + uint32_t err_code = NRF_SUCCESS; + + CRITICAL_REGION_ENTER(); + timer_user_op_t * p_user_op = user_op_alloc(&last_index); + if (p_user_op == NULL) + { + err_code = NRF_ERROR_NO_MEM; + } + else + { + + p_user_op->op_type = TIMER_USER_OP_TYPE_START; + p_user_op->p_node = p_node; + p_user_op->params.start.ticks_at_start = rtc1_counter_get(); + p_user_op->params.start.ticks_first_interval = timeout_initial; + p_user_op->params.start.ticks_periodic_interval = timeout_periodic; + p_user_op->params.start.p_context = p_context; + + user_op_enque(last_index); + } + CRITICAL_REGION_EXIT(); + + if (err_code == NRF_SUCCESS) + { + timer_list_handler_sched(); // set is_running true + } + + return err_code; +} + + +/**@brief Function for scheduling a Timer Stop operation. + * + * @param[in] timer_id Id of timer to stop. + * @param[in] op_type Type of stop operation + * + * @return NRF_SUCCESS on successful scheduling a timer stop operation. NRF_ERROR_NO_MEM when there + * is no memory left to schedule the timer stop operation. + */ +static uint32_t timer_stop_op_schedule(timer_node_t * p_node, + timer_user_op_type_t op_type) +{ + uint8_t last_index; + uint32_t err_code = NRF_SUCCESS; + + CRITICAL_REGION_ENTER(); + timer_user_op_t * p_user_op = user_op_alloc(&last_index); + if (p_user_op == NULL) + { + err_code = NRF_ERROR_NO_MEM; + } + else + { + p_user_op->op_type = op_type; + p_user_op->p_node = p_node; + + user_op_enque(last_index); + } + CRITICAL_REGION_EXIT(); + + if (err_code == NRF_SUCCESS) + { + timer_list_handler_sched(); + } + + return err_code; +} + +// Note RTC0 is used by the softdevice see section 7.1 of S132_SDS docs +/**@brief Function for handling the RTC1 interrupt. + * + * @details Checks for timeouts, and executes timeout handlers for expired timers. + */ +void RTC1_IRQHandler(void) { + + if (NRF_RTC1->EVENTS_OVRFLW != 0) { + overflows = (overflows + 1) & 0xff; + } + // Clear all events (also unexpected ones) + NRF_RTC1->EVENTS_COMPARE[0] = 0; + NRF_RTC1->EVENTS_COMPARE[1] = 0; + NRF_RTC1->EVENTS_COMPARE[2] = 0; + NRF_RTC1->EVENTS_COMPARE[3] = 0; + NRF_RTC1->EVENTS_TICK = 0; + NRF_RTC1->EVENTS_OVRFLW = 0; + +//#if __CORTEX_M == 0x04 +// make sure they are clear + volatile uint32_t dummy; + dummy = NRF_RTC1->EVENTS_COMPARE[0]; + dummy = NRF_RTC1->EVENTS_COMPARE[1]; + dummy = NRF_RTC1->EVENTS_COMPARE[2]; + dummy = NRF_RTC1->EVENTS_COMPARE[3]; + dummy = NRF_RTC1->EVENTS_TICK; + dummy = NRF_RTC1->EVENTS_OVRFLW; + (void)dummy; +//#endif + // Check for expired timers + timer_timeouts_check(); +} + + +/**@brief Function for handling the SWI interrupt. + * + * @details Performs all updates to the timer list. + */ +void SWI_IRQHandler(void) +{ + timer_list_handler(); +} + + +uint32_t app_timer_init(uint32_t prescaler, + uint8_t op_queue_size, + void * p_buffer, + app_timer_evt_schedule_func_t evt_schedule_func) +{ + // Check that buffer is correctly aligned + if (!is_word_aligned(p_buffer)) + { + return NRF_ERROR_INVALID_PARAM; + } + // Check for NULL buffer + if (p_buffer == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + + // Stop RTC to prevent any running timers from expiring (in case of reinitialization) + rtc1_stop(); + + m_evt_schedule_func = evt_schedule_func; + + // Initialize operation queue + m_op_queue.first = 0; + m_op_queue.last = 0; + m_op_queue.size = op_queue_size; + m_op_queue.p_user_op_queue = p_buffer; + + mp_timer_id_head = NULL; + m_ticks_elapsed_q_read_ind = 0; + m_ticks_elapsed_q_write_ind = 0; + +#if APP_TIMER_WITH_PROFILER + m_max_user_op_queue_utilization = 0; +#endif + + NVIC_ClearPendingIRQ(SWI_IRQn); + NVIC_SetPriority(SWI_IRQn, SWI_IRQ_PRI); + NVIC_EnableIRQ(SWI_IRQn); + + rtc1_init(prescaler); + + m_ticks_latest = rtc1_counter_get(); + + if (!m_rtc1_running) { + // No timers were already running, start RTC + rtc1_start(); + } + + + return NRF_SUCCESS; +} + + +uint32_t app_timer_create(app_timer_id_t p_timer_id, + app_timer_mode_t mode, + app_timer_timeout_handler_t timeout_handler) +{ + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if (timeout_handler == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + if (p_timer_id == NULL) + { + return NRF_ERROR_INVALID_PARAM; + } + if (((timer_node_t*)p_timer_id)->is_running) + { + return NRF_ERROR_INVALID_STATE; + } + + timer_node_t * p_node = (timer_node_t *)p_timer_id; + p_node->is_running = false; + p_node->mode = mode; + p_node->p_timeout_handler = timeout_handler; + return NRF_SUCCESS; +} + +uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context) +{ + uint32_t timeout_periodic; + timer_node_t * p_node = (timer_node_t*)timer_id; + + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if (timer_id == 0) + { + return NRF_ERROR_INVALID_STATE; + } + if (timeout_ticks < APP_TIMER_MIN_TIMEOUT_TICKS) + { + return NRF_ERROR_INVALID_PARAM; + } + if (p_node->p_timeout_handler == NULL) + { + return NRF_ERROR_INVALID_STATE; + } + + // Schedule timer start operation + timeout_periodic = (p_node->mode == APP_TIMER_MODE_REPEATED) ? timeout_ticks : 0; + + return timer_start_op_schedule(p_node, + timeout_ticks, + timeout_periodic, + p_context); +} + + +uint32_t app_timer_stop(app_timer_id_t timer_id) +{ + timer_node_t * p_node = (timer_node_t*)timer_id; + // Check state and parameters + VERIFY_MODULE_INITIALIZED(); + + if ((timer_id == NULL) || (p_node->p_timeout_handler == NULL)) + { + return NRF_ERROR_INVALID_STATE; + } + + p_node->is_running = false; + // Schedule timer stop operation + return timer_stop_op_schedule(p_node, TIMER_USER_OP_TYPE_STOP); +} + + +uint32_t app_timer_stop_all(void) +{ + // Check state + VERIFY_MODULE_INITIALIZED(); + + return timer_stop_op_schedule(NULL, TIMER_USER_OP_TYPE_STOP_ALL); +} + + +uint32_t app_timer_cnt_get(void) +{ + return rtc1_counter_get(); +} + + +uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, + uint32_t ticks_from, + uint32_t * p_ticks_diff) +{ + *p_ticks_diff = ticks_diff_get(ticks_to, ticks_from); + return NRF_SUCCESS; +} + +#if APP_TIMER_WITH_PROFILER +uint8_t app_timer_op_queue_utilization_get(void) +{ + return m_max_user_op_queue_utilization; +} +#endif +//#endif //NRF_MODULE_ENABLED(APP_TIMER) diff --git a/cores/nRF5/utility/app_timer.h b/cores/nRF5/utility/app_timer.h new file mode 100644 index 00000000..1fe4275d --- /dev/null +++ b/cores/nRF5/utility/app_timer.h @@ -0,0 +1,333 @@ +/** + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @file + * + * @defgroup app_timer Application Timer + * @{ + * @ingroup app_common + * + * @brief Application timer functionality. + * + * @details This module enables the application to create multiple timer instances based on the RTC1 + * peripheral. Checking for time-outs and invocation of user time-out handlers is performed + * in the RTC1 interrupt handler. List handling is done using a software interrupt (SWI0). + * Both interrupt handlers are running in APP_LOW priority level. + * + * @details When calling app_timer_start() or app_timer_stop(), the timer operation is just queued, + * and the software interrupt is triggered. The actual timer start/stop operation is + * executed by the SWI0 interrupt handler. Since the SWI0 interrupt is running in APP_LOW, + * if the application code calling the timer function is running in APP_LOW or APP_HIGH, + * the timer operation will not be performed until the application handler has returned. + * This will be the case, for example, when stopping a timer from a time-out handler when not using + * the scheduler. + * + * @details Use the USE_SCHEDULER parameter of the APP_TIMER_INIT() macro to select if the + * @ref app_scheduler should be used or not. Even if the scheduler is + * not used, app_timer.h will include app_scheduler.h, so when + * compiling, app_scheduler.h must be available in one of the compiler include paths. + */ + +#ifndef APP_TIMER_H__ +#define APP_TIMER_H__ + + +#include "sdk_config.h" +#include "app_error.h" +#include "app_util.h" +#include "compiler_abstraction.h" +#include +#include +#include +#include "lp_timer_speed.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#define APP_TIMER_CLOCK_FREQ 32768 /**< Clock frequency of the RTC timer used to implement the app timer module. */ +#define APP_TIMER_MIN_TIMEOUT_TICKS 5 /**< Minimum value of the timeout_ticks parameter of app_timer_start(). */ + +#ifdef RTX +#define APP_TIMER_NODE_SIZE 40 /**< Size of app_timer.timer_node_t (used to allocate data). */ +#else +#define APP_TIMER_NODE_SIZE 32 /**< Size of app_timer.timer_node_t (used to allocate data). */ +#endif // RTX +#define APP_TIMER_USER_OP_SIZE 24 /**< Size of app_timer.timer_user_op_t (only for use inside APP_TIMER_BUF_SIZE()). */ + +/**@brief Compute number of bytes required to hold the application timer data structures. + * + * @param[in] OP_QUEUE_SIZE Size of the queue holding timer operations that are pending execution. + * Note that due to the queue implementation, this size must be one more + * than the size that is actually needed. + * + * @return Required application timer buffer size (in bytes). + */ +#define APP_TIMER_BUF_SIZE(OP_QUEUE_SIZE) \ + ( \ + ( \ + (((OP_QUEUE_SIZE) + 1) * APP_TIMER_USER_OP_SIZE) \ + ) \ + ) + +/**@brief Convert milliseconds to timer ticks. + * + * This macro uses 64-bit integer arithmetic, but as long as the macro parameters are + * constants (i.e. defines), the computation will be done by the preprocessor. + * This macro has been modified to handle LP_TIMER_US define + + * When using this macro, ensure that the + * values provided as input result in an output value that is supported by the + * @ref app_timer_start function. For example, when the ticks for 1 ms is needed, the + * maximum possible value of PRESCALER must be 6, when @ref APP_TIMER_CLOCK_FREQ is 32768. + * This will result in a ticks value as 5. Any higher value for PRESCALER will result in a + * ticks value that is not supported by this module. + * + * @param[in] IN Milliseconds OR Microseconds if LP_TIMER_US defined in lp_timer_init.h + * @param[in] PRESCALER Value of the RTC1 PRESCALER register (must be the same value that was + * passed to APP_TIMER_INIT()). + * + * @return Number of timer ticks. + */ +#ifdef LP_TIMER_US +#define APP_TIMER_TICKS(US, PRESCALER)\ + ((uint32_t)ROUNDED_DIV((US) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1)*1000000)) +#else +#define APP_TIMER_TICKS(MS, PRESCALER)\ + ((uint32_t)ROUNDED_DIV((MS) * (uint64_t)APP_TIMER_CLOCK_FREQ, ((PRESCALER) + 1) * 1000)) +#endif + +typedef struct app_timer_t { uint32_t data[CEIL_DIV(APP_TIMER_NODE_SIZE, sizeof(uint32_t))]; } app_timer_t; + +/**@brief Timer ID type. + * Never declare a variable of this type, but use the macro @ref APP_TIMER_DEF instead.*/ +typedef app_timer_t * app_timer_id_t; + +/** + * @brief Create a timer identifier and statically allocate memory for the timer. + * + * @param timer_id Name of the timer identifier variable that will be used to control the timer. + */ +#define APP_TIMER_DEF(timer_id) \ + static app_timer_t timer_id##_data = { {0} }; \ + static const app_timer_id_t timer_id = &timer_id##_data + + +/**@brief Application time-out handler type. */ +typedef void (*app_timer_timeout_handler_t)(void * p_context); + +/**@brief Type of function for passing events from the timer module to the scheduler. */ +typedef uint32_t (*app_timer_evt_schedule_func_t) (app_timer_timeout_handler_t timeout_handler, + void * p_context); + +/**@brief Timer modes. */ +typedef enum +{ + APP_TIMER_MODE_SINGLE_SHOT, /**< The timer will expire only once. */ + APP_TIMER_MODE_REPEATED /**< The timer will restart each time it expires. */ +} app_timer_mode_t; + +/**@brief Initialize the application timer module. + * + * @details This macro handles dimensioning and allocation of the memory buffer required by the timer, + * making sure that the buffer is correctly aligned. It will also connect the timer module + * to the scheduler (if specified). + * + * @note This module assumes that the LFCLK is already running. If it is not, the module will + * be non-functional, since the RTC will not run. If you do not use a SoftDevice, you + * must start the LFCLK manually. See the rtc_example's lfclk_config() function + * for an example of how to do this. If you use a SoftDevice, the LFCLK is started on + * SoftDevice init. + * + * + * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the + * timer tick rate. Set to 0 for no prescaling. + * @param[in] OP_QUEUE_SIZE Size of the queue holding timer operations that are pending execution. + * @param[in] SCHEDULER_FUNC Pointer to scheduler event handler + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, for example, to do a re-initialization). + */ +/*lint -emacro(506, APP_TIMER_INIT) */ /* Suppress "Constant value Boolean */ +#define APP_TIMER_INIT(PRESCALER, OP_QUEUE_SIZE, SCHEDULER_FUNC) \ + do \ + { \ + static uint32_t APP_TIMER_BUF[CEIL_DIV(APP_TIMER_BUF_SIZE(OP_QUEUE_SIZE), \ + sizeof(uint32_t))]; \ + uint32_t ERR_CODE = app_timer_init((PRESCALER), \ + (OP_QUEUE_SIZE) + 1, \ + APP_TIMER_BUF, \ + SCHEDULER_FUNC); \ + APP_ERROR_CHECK(ERR_CODE); \ + } while (0) + + + +/**@brief Function for initializing the timer module. + * + * Normally, initialization should be done using the APP_TIMER_INIT() macro, because that macro will both + * allocate the buffers needed by the timer module (including aligning the buffers correctly) + * and take care of connecting the timer module to the scheduler (if specified). + * + * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. + * @param[in] op_queue_size Size of the queue holding timer operations that are pending + * execution. Note that due to the queue implementation, this size must + * be one more than the size that is actually needed. + * @param[in] p_buffer Pointer to memory buffer for internal use in the app_timer + * module. The size of the buffer can be computed using the + * APP_TIMER_BUF_SIZE() macro. The buffer must be aligned to a + * 4 byte boundary. + * @param[in] evt_schedule_func Function for passing time-out events to the scheduler. Point to + * app_timer_evt_schedule() to connect to the scheduler. Set to NULL + * to make the timer module call the time-out handler directly from + * the timer interrupt handler. + * + * @retval NRF_SUCCESS If the module was initialized successfully. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid (buffer not aligned to a 4 byte + * boundary or NULL). + */ +uint32_t app_timer_init(uint32_t prescaler, + uint8_t op_queue_size, + void * p_buffer, + app_timer_evt_schedule_func_t evt_schedule_func); + +/**@brief Function for creating a timer instance. + * + * @param[in] p_timer_id Pointer to timer identifier. + * @param[in] mode Timer mode. + * @param[in] timeout_handler Function to be executed when the timer expires. + * + * @retval NRF_SUCCESS If the timer was successfully created. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or + * the timer is running. + * + * @note This function does the timer allocation in the caller's context. It is also not protected + * by a critical region. Therefore care must be taken not to call it from several interrupt + * levels simultaneously. + * @note The function can be called again on the timer instance and will re-initialize the instance if + * the timer is not running. + * @attention The FreeRTOS and RTX app_timer implementation does not allow app_timer_create to + * be called on the previously initialized instance. + */ +uint32_t app_timer_create(app_timer_id_t p_timer_id, + app_timer_mode_t mode, + app_timer_timeout_handler_t timeout_handler); + +/**@brief Function for starting a timer. + * + * @param[in] timer_id Timer identifier. + * @param[in] timeout_ticks Number of ticks (of RTC1, including prescaling) to time-out event + * (minimum 5 ticks). + * @param[in] p_context General purpose pointer. Will be passed to the time-out handler when + * the timer expires. + * + * @retval NRF_SUCCESS If the timer was successfully started. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer + * has not been created. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + * + * @note The minimum timeout_ticks value is 5. + * @note For multiple active timers, time-outs occurring in close proximity to each other (in the + * range of 1 to 3 ticks) will have a positive jitter of maximum 3 ticks. + * @note When calling this method on a timer that is already running, the second start operation + * is ignored. + */ +uint32_t app_timer_start(app_timer_id_t timer_id, uint32_t timeout_ticks, void * p_context); + +/**@brief Function for stopping the specified timer. + * + * @param[in] timer_id Timer identifier. + * + * @retval NRF_SUCCESS If the timer was successfully stopped. + * @retval NRF_ERROR_INVALID_PARAM If a parameter was invalid. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized or the timer + * has not been created. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + */ +uint32_t app_timer_stop(app_timer_id_t timer_id); + +/**@brief Function for stopping all running timers. + * + * @retval NRF_SUCCESS If all timers were successfully stopped. + * @retval NRF_ERROR_INVALID_STATE If the application timer module has not been initialized. + * @retval NRF_ERROR_NO_MEM If the timer operations queue was full. + */ +uint32_t app_timer_stop_all(void); + +/**@brief Function for returning the current value of the RTC1 counter. + * + * @return Current value of the RTC1 counter. + */ +uint32_t app_timer_cnt_get(void); + +/**@brief Function for computing the difference between two RTC1 counter values. + * + * @param[in] ticks_to Value returned by app_timer_cnt_get(). + * @param[in] ticks_from Value returned by app_timer_cnt_get(). + * @param[out] p_ticks_diff Number of ticks from ticks_from to ticks_to. + * + * @retval NRF_SUCCESS If the counter difference was successfully computed. + */ +uint32_t app_timer_cnt_diff_compute(uint32_t ticks_to, + uint32_t ticks_from, + uint32_t * p_ticks_diff); + + +/**@brief Function for getting the maximum observed operation queue utilization. + * + * Function for tuning the module and determining OP_QUEUE_SIZE value and thus module RAM usage. + * + * @note APP_TIMER_WITH_PROFILER must be enabled to use this functionality. + * + * @return Maximum number of events in queue observed so far. + */ +uint8_t app_timer_op_queue_utilization_get(void); + + +#ifdef __cplusplus +} +#endif + +#endif // APP_TIMER_H__ + +/** @} */ diff --git a/cores/nRF5/utility/app_timer_appsh.c b/cores/nRF5/utility/app_timer_appsh.c new file mode 100644 index 00000000..0afb0531 --- /dev/null +++ b/cores/nRF5/utility/app_timer_appsh.c @@ -0,0 +1,62 @@ +/** + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "app_timer_appsh.h" +#include "app_scheduler.h" + +static void app_timer_evt_get(void * p_event_data, uint16_t event_size) +{ + app_timer_event_t * p_timer_event = (app_timer_event_t *)p_event_data; + + APP_ERROR_CHECK_BOOL(event_size == sizeof(app_timer_event_t)); + p_timer_event->timeout_handler(p_timer_event->p_context); +} + +uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, + void * p_context) +{ + app_timer_event_t timer_event; + + timer_event.timeout_handler = timeout_handler; + timer_event.p_context = p_context; + + return app_sched_event_put(&timer_event, sizeof(timer_event), app_timer_evt_get); +} + diff --git a/cores/nRF5/utility/app_timer_appsh.h b/cores/nRF5/utility/app_timer_appsh.h new file mode 100644 index 00000000..68bc764d --- /dev/null +++ b/cores/nRF5/utility/app_timer_appsh.h @@ -0,0 +1,80 @@ +/** + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + #ifndef APP_TIMER_APPSH_H + #define APP_TIMER_APPSH_H + +#include "app_timer.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define APP_TIMER_SCHED_EVT_SIZE sizeof(app_timer_event_t) /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). */ + +/**@brief Macro for initializing the application timer module to use with app_scheduler. + * + * @param[in] PRESCALER Value of the RTC1 PRESCALER register. This will decide the + * timer tick rate. Set to 0 for no prescaling. + * @param[in] OP_QUEUES_SIZE Size of queues holding timer operations that are pending execution. + * @param[in] USE_SCHEDULER TRUE if the application is using the app_scheduler, + * FALSE otherwise. + * + * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it + * several times as long as it is from the same location, e.g. to do a reinitialization). + */ +#define APP_TIMER_APPSH_INIT(PRESCALER, OP_QUEUES_SIZE, USE_SCHEDULER) \ + APP_TIMER_INIT(PRESCALER, OP_QUEUES_SIZE, \ + (USE_SCHEDULER) ? app_timer_evt_schedule : NULL) + +typedef struct +{ + app_timer_timeout_handler_t timeout_handler; + void * p_context; +} app_timer_event_t; + +uint32_t app_timer_evt_schedule(app_timer_timeout_handler_t timeout_handler, + void * p_context); + +#ifdef __cplusplus +} +#endif + +#endif // APP_TIMER_APPSH_H diff --git a/cores/nRF5/utility/app_util.h b/cores/nRF5/utility/app_util.h new file mode 100644 index 00000000..8202d73f --- /dev/null +++ b/cores/nRF5/utility/app_util.h @@ -0,0 +1,1018 @@ +/** + * Copyright (c) 2012 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @file + * + * @defgroup app_util Utility Functions and Definitions + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications. + */ + +#ifndef APP_UTIL_H__ +#define APP_UTIL_H__ + +#include +#include +#include "compiler_abstraction.h" +#include "nrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//lint -save -e27 -e10 -e19 +#if defined ( __CC_ARM ) +extern char STACK$$Base; +extern char STACK$$Length; +#define STACK_BASE &STACK$$Base +#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&STACK$$Length)) +#elif defined ( __ICCARM__ ) +extern char CSTACK$$Base; +extern char CSTACK$$Length; +#define STACK_BASE &CSTACK$$Base +#define STACK_TOP ((void*)((uint32_t)STACK_BASE + (uint32_t)&CSTACK$$Length)) +#elif defined ( __GNUC__ ) +extern uint32_t __StackTop; +extern uint32_t __StackLimit; +#define STACK_BASE &__StackLimit +#define STACK_TOP &__StackTop +#endif +//lint -restore + +enum +{ + UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ + UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ + UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ +}; + + +/**@brief Implementation specific macro for delayed macro expansion used in string concatenation +* +* @param[in] lhs Left hand side in concatenation +* @param[in] rhs Right hand side in concatenation +*/ +#define STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs + + +/**@brief Macro used to concatenate string using delayed macro expansion +* +* @note This macro will delay concatenation until the expressions have been resolved +* +* @param[in] lhs Left hand side in concatenation +* @param[in] rhs Right hand side in concatenation +*/ +#define STRING_CONCATENATE(lhs, rhs) STRING_CONCATENATE_IMPL(lhs, rhs) + + +// Disable lint-warnings/errors for STATIC_ASSERT_MSG +//lint --emacro(10, STATIC_ASSERT_MSG) +//lint --emacro(18, STATIC_ASSERT_MSG) +//lint --emacro(19, STATIC_ASSERT_MSG) +//lint --emacro(30, STATIC_ASSERT_MSG) +//lint --emacro(37, STATIC_ASSERT_MSG) +//lint --emacro(42, STATIC_ASSERT_MSG) +//lint --emacro(26, STATIC_ASSERT_MSG) +//lint --emacro(102,STATIC_ASSERT_MSG) +//lint --emacro(533,STATIC_ASSERT_MSG) +//lint --emacro(534,STATIC_ASSERT_MSG) +//lint --emacro(132,STATIC_ASSERT_MSG) +//lint --emacro(414,STATIC_ASSERT_MSG) +//lint --emacro(578,STATIC_ASSERT_MSG) +//lint --emacro(628,STATIC_ASSERT_MSG) +//lint --emacro(648,STATIC_ASSERT_MSG) +//lint --emacro(830,STATIC_ASSERT_MSG) + + +/**@brief Macro for doing static (i.e. compile time) assertion. +* +* @note If the EXPR isn't resolvable, then the error message won't be shown. +* +* @note The output of STATIC_ASSERT_MSG will be different across different compilers. +* +* @param[in] EXPR Constant expression to be verified. +* @param[in] MSG Name of the static assert. +*/ +#if defined(__COUNTER__) + + #define STATIC_ASSERT_MSG(EXPR, MSG) \ + ;enum { STRING_CONCATENATE(MSG, __COUNTER__) = 1 / (!!(EXPR)) } + +#else + + #define STATIC_ASSERT_MSG(EXPR, MSG) \ + ;enum { STRING_CONCATENATE(MSG, __LINE__) = 1 / (!!(EXPR)) } + +#endif + + +/**@brief Macro for doing static (i.e. compile time) assertion. +* +* @note If the EXPR isn't resolvable, then the error message won't be shown. +* +* @note The output of STATIC_ASSERT will be different across different compilers. +* +* @param[in] EXPR Constant expression to be verified. +*/ +#define STATIC_ASSERT(EXPR) STATIC_ASSERT_MSG((EXPR), static_assert_) + + +/**@brief Implementation details for NUM_VAR_ARGS */ +#define NUM_VA_ARGS_IMPL( \ + _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, N, ...) N + + +/**@brief Macro to get the number of arguments in a call variadic macro call + * + * param[in] ... List of arguments + * + * @retval Number of variadic arguments in the argument list + */ +#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61, \ + 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ + 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ + 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ + 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ + 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ + 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) + +/**@brief Implementation details for NUM_VAR_ARGS */ +#define NUM_VA_ARGS_LESS_1_IMPL( \ + _ignored, \ + _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, N, ...) N + +/**@brief Macro to get the number of arguments in a call variadic macro call. + * First argument is not counted. + * + * param[in] ... List of arguments + * + * @retval Number of variadic arguments in the argument list + */ +#define NUM_VA_ARGS_LESS_1(...) NUM_VA_ARGS_LESS_1_IMPL(__VA_ARGS__, 63, 62, 61, \ + 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ + 50, 49, 48, 47, 46, 45, 44, 43, 42, 41, \ + 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, \ + 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, \ + 20, 19, 18, 17, 16, 15, 14, 13, 12, 11, \ + 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, ~) + + +/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ +typedef uint8_t uint16_le_t[2]; + +/**@brief Type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ +typedef uint8_t uint32_le_t[4]; + +/**@brief Byte array type. */ +typedef struct +{ + uint16_t size; /**< Number of array entries. */ + uint8_t * p_data; /**< Pointer to array entries. */ +} uint8_array_t; + + +/**@brief Macro for performing rounded integer division (as opposed to truncating the result). + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Rounded (integer) result of dividing A by B. + */ +#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) + + +/**@brief Macro for checking if an integer is a power of two. + * + * @param[in] A Number to be tested. + * + * @return true if value is power of two. + * @return false if value not power of two. + */ +#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) + + +/**@brief Macro for converting milliseconds to ticks. + * + * @param[in] TIME Number of milliseconds to convert. + * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. + */ +#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) + + +/**@brief Macro for performing integer division, making sure the result is rounded up. + * + * @details One typical use for this is to compute the number of objects with size B is needed to + * hold A number of bytes. + * + * @param[in] A Numerator. + * @param[in] B Denominator. + * + * @return Integer result of dividing A by B, rounded up. + */ +#define CEIL_DIV(A, B) \ + (((A) + (B) - 1) / (B)) + + +/**@brief Macro for creating a buffer aligned to 4 bytes. + * + * @param[in] NAME Name of the buffor. + * @param[in] MIN_SIZE Size of this buffor (it will be rounded up to multiples of 4 bytes). + */ +#define WORD_ALIGNED_MEM_BUFF(NAME, MIN_SIZE) static uint32_t NAME[CEIL_DIV(MIN_SIZE, sizeof(uint32_t))] + + +/**@brief Macro for calculating the number of words that are needed to hold a number of bytes. + * + * @details Adds 3 and divides by 4. + * + * @param[in] n_bytes The number of bytes. + * + * @return The number of words that @p n_bytes take up (rounded up). + */ +#define BYTES_TO_WORDS(n_bytes) (((n_bytes) + 3) >> 2) + + +/**@brief The number of bytes in a word. + */ +#define BYTES_PER_WORD (4) + + +/**@brief Macro for increasing a number to the nearest (larger) multiple of another number. + * + * @param[in] alignment The number to align to. + * @param[in] number The number to align (increase). + * + * @return The aligned (increased) @p number. + */ +#define ALIGN_NUM(alignment, number) ((number - 1) + alignment - ((number - 1) % alignment)) + +/**@brief Macro for getting first of 2 parameters. + * + * @param[in] a1 First parameter. + * @param[in] a2 Second parameter. + */ +#define GET_ARG_1(a1, a2) a1 + +/**@brief Macro for getting second of 2 parameters. + * + * @param[in] a1 First parameter. + * @param[in] a2 Second parameter. + */ +#define GET_ARG_2(a1, a2) a2 + + +/**@brief Container of macro (borrowed from Linux kernel). + * + * This macro returns parent structure address basing on child member address. + * + * @param ptr Address of child type. + * @param type Type of parent structure. + * @param member Name of child field in parent structure. + * + * @return Parent structure address. + * */ +#define CONTAINER_OF(ptr, type, member) \ + (type *)((char *)ptr - offsetof(type, member)) + + +/** + * @brief Define Bit-field mask + * + * Macro that defined the mask with selected number of bits set, starting from + * provided bit number. + * + * @param[in] bcnt Number of bits in the bit-field + * @param[in] boff Lowest bit number + */ +#define BF_MASK(bcnt, boff) ( ((1U << (bcnt)) - 1U) << (boff) ) + +/** + * @brief Get bit-field + * + * Macro that extracts selected bit-field from provided value + * + * @param[in] val Value from witch selected bit-field would be extracted + * @param[in] bcnt Number of bits in the bit-field + * @param[in] boff Lowest bit number + * + * @return Value of the selected bits + */ +#define BF_GET(val, bcnt, boff) ( ( (val) & BF_MASK((bcnt), (boff)) ) >> (boff) ) + +/** + * @brief Create bit-field value + * + * Value is masked and shifted to match given bit-field + * + * @param[in] val Value to set on bit-field + * @param[in] bcnt Number of bits for bit-field + * @param[in] boff Offset of bit-field + * + * @return Value positioned of given bit-field. + */ +#define BF_VAL(val, bcnt, boff) ( (((uint32_t)(val)) << (boff)) & BF_MASK(bcnt, boff) ) + +/** + * @name Configuration of complex bit-field + * + * @sa BF_CX + * @{ + */ +/** @brief Position of bit count in complex bit-field value */ +#define BF_CX_BCNT_POS 0U +/** @brief Mask of bit count in complex bit-field value */ +#define BF_CX_BCNT_MASK (0xffU << BF_CX_BCNT_POS) +/** @brief Position of bit position in complex bit-field value */ +#define BF_CX_BOFF_POS 8U +/** @brief Mask of bit position in complex bit-field value */ +#define BF_CX_BOFF_MASK (0xffU << BF_CX_BOFF_POS) +/** @} */ + +/** + * @brief Define complex bit-field + * + * Complex bit-field would contain its position and size in one number. + * @sa BF_CX_MASK + * @sa BF_CX_POS + * @sa BF_CX_GET + * + * @param[in] bcnt Number of bits in the bit-field + * @param[in] boff Lowest bit number + * + * @return The single number that describes the bit-field completely. + */ +#define BF_CX(bcnt, boff) ( ((((uint32_t)(bcnt)) << BF_CX_BCNT_POS) & BF_CX_BCNT_MASK) | ((((uint32_t)(boff)) << BF_CX_BOFF_POS) & BF_CX_BOFF_MASK) ) + +/** + * @brief Get number of bits in bit-field + * + * @sa BF_CX + * + * @param bf_cx Complex bit-field + * + * @return Number of bits in given bit-field + */ +#define BF_CX_BCNT(bf_cx) ( ((bf_cx) & BF_CX_BCNT_MASK) >> BF_CX_BCNT_POS ) + +/** + * @brief Get lowest bit number in the field + * + * @sa BF_CX + * + * @param[in] bf_cx Complex bit-field + * + * @return Lowest bit number in given bit-field + */ +#define BF_CX_BOFF(bf_cx) ( ((bf_cx) & BF_CX_BOFF_MASK) >> BF_CX_BOFF_POS ) + +/** + * @brief Get bit mask of the selected field + * + * @sa BF_CX + * + * @param[in] bf_cx Complex bit-field + * + * @return Mask of given bit-field + */ +#define BF_CX_MASK(bf_cx) BF_MASK(BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) + +/** + * @brief Get bit-field + * + * Macro that extracts selected bit-field from provided value. + * Bit-field is given as a complex value. + * + * @sa BF_CX + * @sa BF_GET + * + * @param[in] val Value from witch selected bit-field would be extracted + * @param[in] bf_cx Complex bit-field + * + * @return Value of the selected bits. + */ +#define BF_CX_GET(val, bf_cx) BF_GET(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) + +/** + * @brief Create bit-field value + * + * Value is masked and shifted to match given bit-field. + * + * @param[in] val Value to set on bit-field + * @param[in] bf_cx Complex bit-field + * + * @return Value positioned of given bit-field. + */ +#define BF_CX_VAL(val, bf_cx) BF_VAL(val, BF_CX_BCNT(bf_cx), BF_CX_BOFF(bf_cx)) + +/** + * @brief Extracting data from the brackets + * + * This macro get rid of brackets around the argument. + * It can be used to pass multiple arguments in logical one argument to a macro. + * Call it with arguments inside brackets: + * @code + * #define ARGUMENTS (a, b, c) + * BRACKET_EXTRACT(ARGUMENTS) + * @endcode + * It would produce: + * @code + * a, b, c + * @endcode + * + * @param a Argument with anything inside brackets + * @return Anything that appears inside the brackets of the argument + * + * @note + * The argument of the macro have to be inside brackets. + * In other case the compilation would fail. + */ +#define BRACKET_EXTRACT(a) BRACKET_EXTRACT_(a) +#define BRACKET_EXTRACT_(a) BRACKET_EXTRACT__ a +#define BRACKET_EXTRACT__(...) __VA_ARGS__ + + +/** + * @brief Check if number of parameters is more than 1 + * + * @param ... Arguments to count + * + * @return 0 If argument count is <= 1 + * @return 1 If argument count is > 1 + * + * @sa NUM_VA_ARGS + * @sa NUM_IS_MORE_THAN_1 + */ +#define NUM_VA_ARGS_IS_MORE_THAN_1(...) NUM_IS_MORE_THAN_1(NUM_VA_ARGS(__VA_ARGS__)) + +/** + * @brief Check if given numeric value is bigger than 1 + * + * This macro accepts numeric value, that may be the result of argument expansion. + * This numeric value is then converted to 0 if it is lover than 1 or to 1 if + * its value is higher than 1. + * The generated result can be used to glue it into other macro mnemonic name. + * + * @param N Numeric value to check + * + * @return 0 If argument is <= 1 + * @return 1 If argument is > 1 + * + * @note Any existing definition of a form NUM_IS_MORE_THAN_1_PROBE_[N] can + * broke the result of this macro + */ +#define NUM_IS_MORE_THAN_1(N) NUM_IS_MORE_THAN_1_(N) +#define NUM_IS_MORE_THAN_1_(N) NUM_IS_MORE_THAN_1_PROBE_(NUM_IS_MORE_THAN_1_PROBE_ ## N, 1) +#define NUM_IS_MORE_THAN_1_PROBE_(...) GET_VA_ARG_1(GET_ARGS_AFTER_1(__VA_ARGS__)) +#define NUM_IS_MORE_THAN_1_PROBE_0 ~, 0 +#define NUM_IS_MORE_THAN_1_PROBE_1 ~, 0 + +/** + * @brief Get the first argument + * + * @param ... Arguments to select + * + * @return First argument or empty if no arguments are provided + */ +#define GET_VA_ARG_1(...) GET_VA_ARG_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works +#define GET_VA_ARG_1_(a1, ...) a1 + +/** + * @brief Get all the arguments but the first one + * + * @param ... Arguments to select + * + * @return All arguments after the first one or empty if less than 2 arguments are provided + */ +#define GET_ARGS_AFTER_1(...) GET_ARGS_AFTER_1_(__VA_ARGS__, ) // Make sure that also for 1 argument it works +#define GET_ARGS_AFTER_1_(a1, ...) __VA_ARGS__ + +/** + * @brief Size of a field in declared structure + * + * Macro that returns the size of the structure field. + * @param struct_type Variable type to get the field size from + * @param field Field name to analyze. It can be even field inside field (field.somethingelse.and_another). + * + * @return Size of the field + */ +#define FIELD_SIZE(struct_type, field) sizeof(((struct struct_type*)NULL)->field) + +/** + * @brief Number of elements in field array in declared structure + * + * Macro that returns number of elementy in structure field. + * @param struct_type Variable type to get the field size from + * @param field Field name to analyze. + * + * @return Number of elements in field array + * + * @sa FIELD_SIZE + */ +#define FIELD_ARRAY_SIZE(struct_type, field) (FIELD_SIZE(struct_type, field) / FIELD_SIZE(struct_type, field[0])) + +/** + * @brief Mapping macro + * + * Macro that process all arguments using given macro + * + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument) + * + * @return All arguments processed by given macro + */ +#define MACRO_MAP(...) MACRO_MAP_(__VA_ARGS__) +#define MACRO_MAP_(...) MACRO_MAP_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total + +/** + * @brief Mapping macro, recursive version + * + * Can be used in @ref MACRO_MAP macro + */ +#define MACRO_MAP_REC(...) MACRO_MAP_REC_(__VA_ARGS__) +#define MACRO_MAP_REC_(...) MACRO_MAP_REC_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) // To make sure it works also for 2 arguments in total +/** + * @brief Mapping N arguments macro + * + * Macro similar to @ref MACRO_MAP but maps exact number of arguments. + * If there is more arguments given, the rest would be ignored. + * + * @param N Number of arguments to map + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument) + * + * @return Selected number of arguments processed by given macro + */ +#define MACRO_MAP_N(N, ...) MACRO_MAP_N_(N, __VA_ARGS__) +#define MACRO_MAP_N_(N, ...) CONCAT_2(MACRO_MAP_, N)(__VA_ARGS__, ) + +/** + * @brief Mapping N arguments macro, recursive version + * + * Can be used in @ref MACRO_MAP_N macro + */ +#define MACRO_MAP_REC_N(N, ...) MACRO_MAP_REC_N_(N, __VA_ARGS__) +#define MACRO_MAP_REC_N_(N, ...) CONCAT_2(MACRO_MAP_REC_, N)(__VA_ARGS__, ) + +#define MACRO_MAP_0( ...) +#define MACRO_MAP_1( macro, a, ...) macro(a) +#define MACRO_MAP_2( macro, a, ...) macro(a) MACRO_MAP_1 (macro, __VA_ARGS__, ) +#define MACRO_MAP_3( macro, a, ...) macro(a) MACRO_MAP_2 (macro, __VA_ARGS__, ) +#define MACRO_MAP_4( macro, a, ...) macro(a) MACRO_MAP_3 (macro, __VA_ARGS__, ) +#define MACRO_MAP_5( macro, a, ...) macro(a) MACRO_MAP_4 (macro, __VA_ARGS__, ) +#define MACRO_MAP_6( macro, a, ...) macro(a) MACRO_MAP_5 (macro, __VA_ARGS__, ) +#define MACRO_MAP_7( macro, a, ...) macro(a) MACRO_MAP_6 (macro, __VA_ARGS__, ) +#define MACRO_MAP_8( macro, a, ...) macro(a) MACRO_MAP_7 (macro, __VA_ARGS__, ) +#define MACRO_MAP_9( macro, a, ...) macro(a) MACRO_MAP_8 (macro, __VA_ARGS__, ) +#define MACRO_MAP_10(macro, a, ...) macro(a) MACRO_MAP_9 (macro, __VA_ARGS__, ) +#define MACRO_MAP_11(macro, a, ...) macro(a) MACRO_MAP_10(macro, __VA_ARGS__, ) +#define MACRO_MAP_12(macro, a, ...) macro(a) MACRO_MAP_11(macro, __VA_ARGS__, ) +#define MACRO_MAP_13(macro, a, ...) macro(a) MACRO_MAP_12(macro, __VA_ARGS__, ) +#define MACRO_MAP_14(macro, a, ...) macro(a) MACRO_MAP_13(macro, __VA_ARGS__, ) +#define MACRO_MAP_15(macro, a, ...) macro(a) MACRO_MAP_14(macro, __VA_ARGS__, ) + +#define MACRO_MAP_REC_0( ...) +#define MACRO_MAP_REC_1( macro, a, ...) macro(a) +#define MACRO_MAP_REC_2( macro, a, ...) macro(a) MACRO_MAP_REC_1 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_3( macro, a, ...) macro(a) MACRO_MAP_REC_2 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_4( macro, a, ...) macro(a) MACRO_MAP_REC_3 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_5( macro, a, ...) macro(a) MACRO_MAP_REC_4 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_6( macro, a, ...) macro(a) MACRO_MAP_REC_5 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_7( macro, a, ...) macro(a) MACRO_MAP_REC_6 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_8( macro, a, ...) macro(a) MACRO_MAP_REC_7 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_9( macro, a, ...) macro(a) MACRO_MAP_REC_8 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_10(macro, a, ...) macro(a) MACRO_MAP_REC_9 (macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_11(macro, a, ...) macro(a) MACRO_MAP_REC_10(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_12(macro, a, ...) macro(a) MACRO_MAP_REC_11(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_13(macro, a, ...) macro(a) MACRO_MAP_REC_12(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_14(macro, a, ...) macro(a) MACRO_MAP_REC_13(macro, __VA_ARGS__, ) +#define MACRO_MAP_REC_15(macro, a, ...) macro(a) MACRO_MAP_REC_14(macro, __VA_ARGS__, ) + +/** + * @brief Mapping macro with current index + * + * Basically macro similar to @ref MACRO_MAP, but the processing function would get an argument + * and current argument index (beginning from 0). + * + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index) + * @return All arguments processed by given macro + */ +#define MACRO_MAP_FOR(...) MACRO_MAP_FOR_(__VA_ARGS__) +#define MACRO_MAP_FOR_N_LIST 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define MACRO_MAP_FOR_(...) MACRO_MAP_FOR_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), __VA_ARGS__) + +/** + * @brief Mapping N arguments macro with current index + * + * Macro is similar to @ref MACRO_MAP_FOR but maps exact number of arguments. + * If there is more arguments given, the rest would be ignored. + * + * @param N Number of arguments to map + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index) + * + * @return Selected number of arguments processed by given macro + */ +#define MACRO_MAP_FOR_N(N, ...) MACRO_MAP_FOR_N_(N, __VA_ARGS__) +#define MACRO_MAP_FOR_N_(N, ...) CONCAT_2(MACRO_MAP_FOR_, N)((MACRO_MAP_FOR_N_LIST), __VA_ARGS__, ) + +#define MACRO_MAP_FOR_0( n_list, ...) +#define MACRO_MAP_FOR_1( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) +#define MACRO_MAP_FOR_2( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_3( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_4( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_5( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_6( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_7( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_8( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_9( n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_10(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_11(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_12(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_13(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_14(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_15(n_list, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list))) MACRO_MAP_FOR_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), macro, __VA_ARGS__, ) + + +/** + * @brief Mapping macro with current index and parameter + * + * Version of @ref MACRO_MAP_FOR that passes also the same parameter to all macros. + * + * @param param Parameter that would be passed to each macro call during mapping. + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index, param) + * + * @return All arguments processed by given macro + */ +#define MACRO_MAP_FOR_PARAM(param, ...) MACRO_MAP_FOR_PARAM_(param, __VA_ARGS__) +#define MACRO_MAP_FOR_PARAM_(param, ...) MACRO_MAP_FOR_PARAM_N(NUM_VA_ARGS_LESS_1(__VA_ARGS__), param, __VA_ARGS__) + +/** + * @brief Mapping N arguments macro with with current index and parameter + * + * @param N Number of arguments to map + * @param param Parameter that would be passed to each macro call during mapping. + * @param ... Macro name to be used for argument processing followed by arguments to process. + * Macro should have following form: MACRO(argument, index, param) + * + * @return All arguments processed by given macro + */ +#define MACRO_MAP_FOR_PARAM_N(N, param, ...) MACRO_MAP_FOR_PARAM_N_(N, param, __VA_ARGS__) +#define MACRO_MAP_FOR_PARAM_N_(N, param, ...) CONCAT_2(MACRO_MAP_FOR_PARAM_, N)((MACRO_MAP_FOR_N_LIST), param, __VA_ARGS__, ) + + +#define MACRO_MAP_FOR_PARAM_0( n_list, param, ...) +#define MACRO_MAP_FOR_PARAM_1( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) +#define MACRO_MAP_FOR_PARAM_2( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_1 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_3( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_2 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_4( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_3 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_5( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_4 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_6( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_5 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_7( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_6 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_8( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_7 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_9( n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_8 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_10(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_9 ((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_11(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_10((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_12(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_11((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_13(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_12((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_14(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_13((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) +#define MACRO_MAP_FOR_PARAM_15(n_list, param, macro, a, ...) macro(a, GET_VA_ARG_1(BRACKET_EXTRACT(n_list)), param) MACRO_MAP_FOR_PARAM_14((GET_ARGS_AFTER_1(BRACKET_EXTRACT(n_list))), param, macro, __VA_ARGS__, ) + + +/**@brief Adding curly brace to macro parameter + * + * Useful in array of structures initialization. + * + * @param p parameter to put into the curly brace*/ +#define PARAM_CBRACE(p) { p }, + + +/**@brief Function for changing the value unit. + * + * @param[in] value Value to be rescaled. + * @param[in] old_unit_reversal Reversal of the incoming unit. + * @param[in] new_unit_reversal Reversal of the desired unit. + * + * @return Number of bytes written. + */ +static __INLINE uint64_t value_rescale(uint32_t value, uint32_t old_unit_reversal, uint16_t new_unit_reversal) +{ + return (uint64_t)ROUNDED_DIV((uint64_t)value * new_unit_reversal, old_unit_reversal); +} + +/**@brief Function for encoding a uint16 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); + return sizeof(uint16_t); +} + +/**@brief Function for encoding a three-byte value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint24_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + return 3; +} + +/**@brief Function for encoding a uint32 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); + return sizeof(uint32_t); +} + +/**@brief Function for encoding a uint48 value. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data is to be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint48_encode(uint64_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) ((value & 0x0000000000FF) >> 0); + p_encoded_data[1] = (uint8_t) ((value & 0x00000000FF00) >> 8); + p_encoded_data[2] = (uint8_t) ((value & 0x000000FF0000) >> 16); + p_encoded_data[3] = (uint8_t) ((value & 0x0000FF000000) >> 24); + p_encoded_data[4] = (uint8_t) ((value & 0x00FF00000000) >> 32); + p_encoded_data[5] = (uint8_t) ((value & 0xFF0000000000) >> 40); + return 6; +} + +/**@brief Function for decoding a uint16 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | + (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); +} + +/**@brief Function for decoding a uint16 value in big-endian format. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint16_t uint16_big_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint16_t)((uint8_t *)p_encoded_data)[0]) << 8 ) | + (((uint16_t)((uint8_t *)p_encoded_data)[1])) ); +} + +/**@brief Function for decoding a three-byte value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value (uint32_t). + */ +static __INLINE uint32_t uint24_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16)); +} + +/**@brief Function for decoding a uint32 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); +} + +/**@brief Function for decoding a uint32 value in big-endian format. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. + */ +static __INLINE uint32_t uint32_big_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 24) | + (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 16) | + (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 8) | + (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 0) ); +} + +/** + * @brief Function for encoding an uint16 value in big-endian format. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data will be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint16_big_encode(uint16_t value, uint8_t * p_encoded_data) +{ + p_encoded_data[0] = (uint8_t) (value >> 8); + p_encoded_data[1] = (uint8_t) (value & 0xFF); + + return sizeof(uint16_t); +} + +/**@brief Function for encoding a uint32 value in big-endian format. + * + * @param[in] value Value to be encoded. + * @param[out] p_encoded_data Buffer where the encoded data will be written. + * + * @return Number of bytes written. + */ +static __INLINE uint8_t uint32_big_encode(uint32_t value, uint8_t * p_encoded_data) +{ + *(uint32_t *)p_encoded_data = __REV(value); + return sizeof(uint32_t); +} + +/**@brief Function for decoding a uint48 value. + * + * @param[in] p_encoded_data Buffer where the encoded data is stored. + * + * @return Decoded value. (uint64_t) + */ +static __INLINE uint64_t uint48_decode(const uint8_t * p_encoded_data) +{ + return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0) | + (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8) | + (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) | + (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) | + (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32) | + (((uint64_t)((uint8_t *)p_encoded_data)[5]) << 40 )); +} + +/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. + * + * @details The calculation is based on a linearized version of the battery's discharge + * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and + * is considered to be the lower boundary. + * + * The discharge curve for CR2032 is non-linear. In this model it is split into + * 4 linear sections: + * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) + * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) + * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) + * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) + * + * These numbers are by no means accurate. Temperature and + * load in the actual application is not accounted for! + * + * @param[in] mvolts The voltage in mV + * + * @return Battery level in percent. +*/ +static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) +{ + uint8_t battery_level; + + if (mvolts >= 3000) + { + battery_level = 100; + } + else if (mvolts > 2900) + { + battery_level = 100 - ((3000 - mvolts) * 58) / 100; + } + else if (mvolts > 2740) + { + battery_level = 42 - ((2900 - mvolts) * 24) / 160; + } + else if (mvolts > 2440) + { + battery_level = 18 - ((2740 - mvolts) * 12) / 300; + } + else if (mvolts > 2100) + { + battery_level = 6 - ((2440 - mvolts) * 6) / 340; + } + else + { + battery_level = 0; + } + + return battery_level; +} + +/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. + * + * @param[in] p Pointer value to be checked. + * + * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. + */ +static __INLINE bool is_word_aligned(void const* p) +{ + return (((uintptr_t)p & 0x03) == 0); +} + +/** + * @brief Function for checking if provided address is located in stack space. + * + * @param[in] ptr Pointer to be checked. + * + * @return true if address is in stack space, false otherwise. + */ +static __INLINE bool is_address_from_stack(void * ptr) +{ + if (((uint32_t)ptr >= (uint32_t)STACK_BASE) && + ((uint32_t)ptr < (uint32_t)STACK_TOP) ) + { + return true; + } + else + { + return false; + } +} + + +#ifdef __cplusplus +} +#endif + +#endif // APP_UTIL_H__ + +/** @} */ diff --git a/cores/nRF5/utility/app_util_platform.c b/cores/nRF5/utility/app_util_platform.c new file mode 100644 index 00000000..6caf6595 --- /dev/null +++ b/cores/nRF5/utility/app_util_platform.c @@ -0,0 +1,93 @@ +/** + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "app_util_platform.h" + +#ifdef SOFTDEVICE_PRESENT +/* Global nvic state instance, required by nrf_nvic.h */ +nrf_nvic_state_t nrf_nvic_state; +#endif + +static uint32_t m_in_critical_region = 0; + +void app_util_disable_irq(void) +{ + __disable_irq(); + m_in_critical_region++; +} + +void app_util_enable_irq(void) +{ + m_in_critical_region--; + if (m_in_critical_region == 0) + { + __enable_irq(); + } +} + +void app_util_critical_region_enter(uint8_t *p_nested) +{ +#if __CORTEX_M == (0x04U) + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + (void) sd_nvic_critical_region_enter(p_nested); +#else + app_util_disable_irq(); +#endif +} + +void app_util_critical_region_exit(uint8_t nested) +{ +#if __CORTEX_M == (0x04U) + ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) +#endif + +#if defined(SOFTDEVICE_PRESENT) + /* return value can be safely ignored */ + (void) sd_nvic_critical_region_exit(nested); +#else + app_util_enable_irq(); +#endif +} + + diff --git a/cores/nRF5/utility/app_util_platform.h b/cores/nRF5/utility/app_util_platform.h new file mode 100644 index 00000000..fb725b2a --- /dev/null +++ b/cores/nRF5/utility/app_util_platform.h @@ -0,0 +1,288 @@ +/** + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/**@file + * + * @defgroup app_util_platform Utility Functions and Definitions (Platform) + * @{ + * @ingroup app_common + * + * @brief Various types and definitions available to all applications when using SoftDevice. + */ + +#ifndef APP_UTIL_PLATFORM_H__ +#define APP_UTIL_PLATFORM_H__ + +#define SOFTDEVICE_PRESENT +#define __CORTEX_M 0x04U + +#include +#include "compiler_abstraction.h" +#include "nrf.h" +#ifdef SOFTDEVICE_PRESENT +#include "nrf_soc.h" +#include "nrf_nvic.h" +#endif +#include "nrf_assert.h" +#include "app_error.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if __CORTEX_M == (0x00U) +#define _PRIO_SD_HIGH 0 +#define _PRIO_APP_HIGH 1 +#define _PRIO_APP_MID 1 +#define _PRIO_SD_LOW 2 +#define _PRIO_APP_LOW 3 +#define _PRIO_APP_LOWEST 3 +#define _PRIO_THREAD 4 +#elif __CORTEX_M == (0x04U) +#define _PRIO_SD_HIGH 0 +#define _PRIO_SD_MID 1 +#define _PRIO_APP_HIGH 2 +#define _PRIO_APP_MID 3 +#define _PRIO_SD_LOW 4 +#define _PRIO_SD_LOWEST 5 +#define _PRIO_APP_LOW 6 +#define _PRIO_APP_LOWEST 7 +#define _PRIO_THREAD 15 +#else + #error "No platform defined" +#endif + + +//lint -save -e113 -e452 +/**@brief The interrupt priorities available to the application while the SoftDevice is active. */ +typedef enum +{ +#ifndef SOFTDEVICE_PRESENT + APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH, +#else + APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH, +#endif + APP_IRQ_PRIORITY_HIGH = _PRIO_APP_HIGH, +#ifndef SOFTDEVICE_PRESENT + APP_IRQ_PRIORITY_MID = _PRIO_SD_LOW, +#else + APP_IRQ_PRIORITY_MID = _PRIO_APP_MID, +#endif + APP_IRQ_PRIORITY_LOW = _PRIO_APP_LOW, + APP_IRQ_PRIORITY_LOWEST = _PRIO_APP_LOWEST, + APP_IRQ_PRIORITY_THREAD = _PRIO_THREAD /**< "Interrupt level" when running in Thread Mode. */ +} app_irq_priority_t; +//lint -restore + + +/*@brief The privilege levels available to applications in Thread Mode */ +typedef enum +{ + APP_LEVEL_UNPRIVILEGED, + APP_LEVEL_PRIVILEGED +} app_level_t; + +/**@cond NO_DOXYGEN */ +#define EXTERNAL_INT_VECTOR_OFFSET 16 +/**@endcond */ + +/**@brief Macro for setting a breakpoint. + */ +#if defined(__GNUC__) +#define NRF_BREAKPOINT __builtin_trap() +#else +#define NRF_BREAKPOINT __BKPT(0) +#endif + +/** @brief Macro for setting a breakpoint. + * + * If it is possible to detect debugger presence then it is set only in that case. + * + */ +#if __CORTEX_M == 0x04 +#define NRF_BREAKPOINT_COND do { \ + /* C_DEBUGEN == 1 -> Debugger Connected */ \ + if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) \ + { \ + /* Generate breakpoint if debugger is connected */ \ + NRF_BREAKPOINT; \ + } \ + }while (0) +#else +#define NRF_BREAKPOINT_COND NRF_BREAKPOINT +#endif // __CORTEX_M == 0x04 + +#if defined ( __CC_ARM ) +#define PACKED(TYPE) __packed TYPE +#define PACKED_STRUCT PACKED(struct) +#elif defined ( __GNUC__ ) +#define PACKED __attribute__((packed)) +#define PACKED_STRUCT struct PACKED +#elif defined (__ICCARM__) +#define PACKED_STRUCT __packed struct +#endif + +void app_util_critical_region_enter (uint8_t *p_nested); +void app_util_critical_region_exit (uint8_t nested); + +/**@brief Macro for entering a critical region. + * + * @note Due to implementation details, there must exist one and only one call to + * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located + * in the same scope. + */ +#ifdef SOFTDEVICE_PRESENT +#define CRITICAL_REGION_ENTER() \ + { \ + uint8_t __CR_NESTED = 0; \ + app_util_critical_region_enter(&__CR_NESTED); +#else +#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL) +#endif + +/**@brief Macro for leaving a critical region. + * + * @note Due to implementation details, there must exist one and only one call to + * CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located + * in the same scope. + */ +#ifdef SOFTDEVICE_PRESENT +#define CRITICAL_REGION_EXIT() \ + app_util_critical_region_exit(__CR_NESTED); \ + } +#else +#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0) +#endif + +/* Workaround for Keil 4 */ +#ifndef IPSR_ISR_Msk +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ +#endif + + + +/**@brief Macro to enable anonymous unions from a certain point in the code. + */ +#if defined(__CC_ARM) + #define ANON_UNIONS_ENABLE _Pragma("push") \ + _Pragma("anon_unions") +#elif defined(__ICCARM__) + #define ANON_UNIONS_ENABLE _Pragma("language=extended") +#else + #define ANON_UNIONS_ENABLE + // No action will be taken. + // For GCC anonymous unions are enabled by default. +#endif + +/**@brief Macro to disable anonymous unions from a certain point in the code. + * @note Call only after first calling @ref ANON_UNIONS_ENABLE. + */ +#if defined(__CC_ARM) + #define ANON_UNIONS_DISABLE _Pragma("pop") +#elif defined(__ICCARM__) + #define ANON_UNIONS_DISABLE + // for IAR leave anonymous unions enabled +#else + #define ANON_UNIONS_DISABLE + // No action will be taken. + // For GCC anonymous unions are enabled by default. +#endif + +/* Workaround for Keil 4 */ +#ifndef CONTROL_nPRIV_Msk +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ +#endif + +/**@brief Function for finding the current interrupt level. + * + * @return Current interrupt level. + * @retval APP_IRQ_PRIORITY_HIGH We are running in Application High interrupt level. + * @retval APP_IRQ_PRIORITY_LOW We are running in Application Low interrupt level. + * @retval APP_IRQ_PRIORITY_THREAD We are running in Thread Mode. + */ +static __INLINE uint8_t current_int_priority_get(void) +{ + uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; + if (isr_vector_num > 0) + { + int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET); + return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF); + } + else + { + return APP_IRQ_PRIORITY_THREAD; + } +} + +/**@brief Function for finding out the current privilege level. + * + * @return Current privilege level. + * @retval APP_LEVEL_UNPRIVILEGED We are running in unprivileged level. + * @retval APP_LEVEL_PRIVILEGED We are running in privileged level. + */ +static __INLINE uint8_t privilege_level_get(void) +{ +#if __CORTEX_M == (0x00U) || defined(_WIN32) || defined(__unix) || defined(__APPLE__) + /* the Cortex-M0 has no concept of privilege */ + return APP_LEVEL_PRIVILEGED; +#elif __CORTEX_M == (0x04U) + uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ; + if (0 == isr_vector_num) + { + /* Thread Mode, check nPRIV */ + int32_t control = __get_CONTROL(); + return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED; + } + else + { + /* Handler Mode, always privileged */ + return APP_LEVEL_PRIVILEGED; + } +#endif +} + + +#ifdef __cplusplus +} +#endif + +#endif // APP_UTIL_PLATFORM_H__ + +/** @} */ diff --git a/cores/nRF5/utility/ble_assert.h b/cores/nRF5/utility/ble_assert.h new file mode 100644 index 00000000..34d28f06 --- /dev/null +++ b/cores/nRF5/utility/ble_assert.h @@ -0,0 +1,44 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + + /** @file + * @brief Declaration of assert() + */ + +#ifndef BLE_ASSERT_H__ +#define BLE_ASSERT_H__ + +#ifndef BLE_ASSERT + +#define ble_assert(expr) + +#else + +extern void __ble_assert(const char *file, uint16_t line); + +#define ble_assert(expr) \ + ((expr) \ + ? ((void) 0) \ + : __ble_assert (__FILE__, __LINE__)) + +#endif + +#endif /* BLE_ASSERT_H__ */ diff --git a/cores/nRF5/utility/boards.h b/cores/nRF5/utility/boards.h new file mode 100644 index 00000000..e1ea98d7 --- /dev/null +++ b/cores/nRF5/utility/boards.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** @file + * @brief Defines for the different Bluetooth low energy boards + */ + +#ifndef _BLE_BOARDS_H_ +#define _BLE_BOARDS_H_ + +#define BOARD_DEFAULT 0 //Use this if you do not know the board you are using or you are creating a new one +#define REDBEARLAB_SHIELD_V1_1 1 //Redbearlab Bluetooth low energy shield v1.1 +#define REDBEARLAB_SHIELD_V2012_07 1 //Identical to Redbearlab v1.1 shield +#define REDBEARLAB_SHIELD_V2 0 //Redbearlab Bluetooth low energy shield v2.x - No special handling required for pin reset same as default + +#endif \ No newline at end of file diff --git a/cores/nRF5/utility/dtm.h b/cores/nRF5/utility/dtm.h new file mode 100644 index 00000000..4ac45f94 --- /dev/null +++ b/cores/nRF5/utility/dtm.h @@ -0,0 +1,63 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** + * @file + * + * @ingroup group_acilib + * + * @brief Internal prototype for acilib module. + */ + +#ifndef DTM_H__ +#define DTM_H__ + +/** @brief DTM command codes (upper two bits in the DTM command), use a bitwise OR with the frequency N = 0x00 - 0x27: N = (F-2402)/2 Frequency Range 2402 MHz +to 2480 MHz*/ +#define DTM_LE_CMD_RESET 0x00 +#define DTM_LE_CMD_RECEIVER_TEST 0x40 +#define DTM_LE_CMD_TRANSMITTER_TEST 0x80 +#define DTM_LE_CMD_TEST_END 0xC0 + + +/** @brief Defined packet types for DTM */ +#define DTM_LE_PKT_PRBS9 0x00 /**< Bit pattern PRBS9. */ +#define DTM_LE_PKT_0X0F 0x01 /**< Bit pattern 11110000 (LSB is the leftmost bit). */ +#define DTM_LE_PKT_0X55 0x02 /**< Bit pattern 10101010 (LSB is the leftmost bit). */ +#define DTM_LE_PKT_VENDOR 0x03 /**< Vendor specific. Nordic: continous carrier test */ + +/** @brief Defined bit fields for DTM responses. */ +#define LE_PACKET_REPORTING_EVENT_MSB_BIT 0x80 +#define LE_TEST_STATUS_EVENT_LSB_BIT 0x01 + +/** @brief DTM response types. */ +#define LE_TEST_STATUS_EVENT 0x00 +#define LE_TEST_PACKET_REPORT_EVENT 0x80 + +/** @brief DTM return values. */ +#define LE_TEST_STATUS_SUCCESS 0x00 +#define LE_TEST_STATUS_FAILURE 0x01 + + + +#endif //DTM_H__ + +/** @} */ diff --git a/cores/nRF5/utility/hal_aci_tl.cpp b/cores/nRF5/utility/hal_aci_tl.cpp new file mode 100644 index 00000000..bcbbe85d --- /dev/null +++ b/cores/nRF5/utility/hal_aci_tl.cpp @@ -0,0 +1,519 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** @file +@brief Implementation of the ACI transport layer module +*/ + +#if !defined(NRF51) && !defined(NRF52) &&!defined(__RFduino__) + +#include +#include "hal_platform.h" +#include "hal_aci_tl.h" +#include "aci_queue.h" +#if defined (__AVR__) +#include +#endif + +/* +PIC32 supports only MSbit transfer on SPI and the nRF8001 uses LSBit +Use the REVERSE_BITS macro to convert from MSBit to LSBit +The outgoing command and the incoming event needs to be converted +*/ +//Board dependent defines +#if defined (__AVR__) || defined(__SAM3X8E__) || defined(__SAMD21G18A__)|| defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + //For Arduino add nothing +#elif defined(__PIC32MX__) + //For ChipKit as the transmission has to be reversed, the next definitions have to be added + #define REVERSE_BITS(byte) (((reverse_lookup[(byte & 0x0F)]) << 4) + reverse_lookup[((byte & 0xF0) >> 4)]) + static const uint8_t reverse_lookup[] = { 0, 8, 4, 12, 2, 10, 6, 14,1, 9, 5, 13,3, 11, 7, 15 }; +#else + #error "Unsupported platform" +#endif + +#ifdef HAL_ACI_TL_DEBUG +static void m_aci_data_print(hal_aci_data_t *p_data); +#endif +static void m_aci_event_check(void); +#ifdef HAL_ACI_TL_INTERRUPT +static void m_aci_isr(void); +#endif +static void m_aci_pins_set(aci_pins_t *a_pins_ptr); +static inline void m_aci_reqn_disable (void); +static inline void m_aci_reqn_enable (void); +static void m_aci_q_flush(void); +static bool m_aci_spi_transfer(hal_aci_data_t * data_to_send, hal_aci_data_t * received_data); + +static uint8_t spi_readwrite(uint8_t aci_byte); +#ifdef HAL_ACI_TL_DEBUG +static bool aci_debug_print = false; +#endif + +aci_queue_t aci_tx_q; +aci_queue_t aci_rx_q; + +static aci_pins_t *a_pins_local_ptr; + +#ifdef HAL_ACI_TL_DEBUG +void m_aci_data_print(hal_aci_data_t *p_data) +{ + const uint8_t length = p_data->buffer[0]; + uint8_t i; + Serial.print(length, DEC); + Serial.print(" :"); + for (i=0; i<=length; i++) + { + Serial.print(p_data->buffer[i], HEX); + Serial.print(F(", ")); + } + Serial.println(F("")); +} +#endif + +#ifdef HAL_ACI_TL_INTERRUPT +/* + Interrupt service routine called when the RDYN line goes low. Runs the SPI transfer. +*/ +static void m_aci_isr(void) +{ + hal_aci_data_t data_to_send; + hal_aci_data_t received_data; + + // Receive from queue + if (!aci_queue_dequeue_from_isr(&aci_tx_q, &data_to_send)) + { + /* queue was empty, nothing to send */ + data_to_send.status_byte = 0; + data_to_send.buffer[0] = 0; + } + + // Receive and/or transmit data + m_aci_spi_transfer(&data_to_send, &received_data); + + if (!aci_queue_is_full_from_isr(&aci_rx_q) && !aci_queue_is_empty_from_isr(&aci_tx_q)) + { + m_aci_reqn_enable(); + } + + // Check if we received data + if (received_data.buffer[0] > 0) + { + if (!aci_queue_enqueue_from_isr(&aci_rx_q, &received_data)) + { + /* Receive Buffer full. + Should never happen. + Spin in a while loop. + */ + while(1); + } + + // Disable ready line interrupt until we have room to store incoming messages + if (aci_queue_is_full_from_isr(&aci_rx_q)) + { + detachInterrupt(a_pins_local_ptr->interrupt_number); + } + } + + return; +} +#endif + +/* + Checks the RDYN line and runs the SPI transfer if required. +*/ +static void m_aci_event_check(void) +{ + hal_aci_data_t data_to_send; + hal_aci_data_t received_data; + + // No room to store incoming messages + if (aci_queue_is_full(&aci_rx_q)) + { + return; + } + + // If the ready line is disabled and we have pending messages outgoing we enable the request line + if (HIGH == digitalRead(a_pins_local_ptr->rdyn_pin)) + { + if (!aci_queue_is_empty(&aci_tx_q)) + { + m_aci_reqn_enable(); + } + + return; + } + + // Receive from queue + if (!aci_queue_dequeue(&aci_tx_q, &data_to_send)) + { + /* queue was empty, nothing to send */ + data_to_send.status_byte = 0; + data_to_send.buffer[0] = 0; + } + + // Receive and/or transmit data + m_aci_spi_transfer(&data_to_send, &received_data); + + /* If there are messages to transmit, and we can store the reply, we request a new transfer */ + if (!aci_queue_is_full(&aci_rx_q) && !aci_queue_is_empty(&aci_tx_q)) + { + m_aci_reqn_enable(); + } + + // Check if we received data + if (received_data.buffer[0] > 0) + { + if (!aci_queue_enqueue(&aci_rx_q, &received_data)) + { + /* Receive Buffer full. + Should never happen. + Spin in a while loop. + */ + while(1); + } + } + + return; +} + +/** @brief Point the low level library at the ACI pins specified + * @details + * The ACI pins are specified in the application and a pointer is made available for + * the low level library to use + */ +static void m_aci_pins_set(aci_pins_t *a_pins_ptr) +{ + a_pins_local_ptr = a_pins_ptr; +} + +static inline void m_aci_reqn_disable (void) +{ + digitalWrite(a_pins_local_ptr->reqn_pin, 1); +#if defined(SPI_HAS_TRANSACTION) && !defined(__SAMD21G18A__) + SPI.endTransaction(); +#endif +} + +static inline void m_aci_reqn_enable (void) +{ +#if defined(SPI_HAS_TRANSACTION) && !defined(__SAMD21G18A__) + SPI.beginTransaction(SPISettings(2000000, LSBFIRST, SPI_MODE0)); +#endif + digitalWrite(a_pins_local_ptr->reqn_pin, 0); +} + +static void m_aci_q_flush(void) +{ + noInterrupts(); + /* re-initialize aci cmd queue and aci event queue to flush them*/ + aci_queue_init(&aci_tx_q); + aci_queue_init(&aci_rx_q); + interrupts(); +} + +static bool m_aci_spi_transfer(hal_aci_data_t * data_to_send, hal_aci_data_t * received_data) +{ + uint8_t byte_cnt; + uint8_t byte_sent_cnt; + uint8_t max_bytes; + + m_aci_reqn_enable(); + + // Send length, receive header + byte_sent_cnt = 0; + received_data->status_byte = spi_readwrite(data_to_send->buffer[byte_sent_cnt++]); + // Send first byte, receive length from slave + received_data->buffer[0] = spi_readwrite(data_to_send->buffer[byte_sent_cnt++]); + if (0 == data_to_send->buffer[0]) + { + max_bytes = received_data->buffer[0]; + } + else + { + // Set the maximum to the biggest size. One command byte is already sent + max_bytes = (received_data->buffer[0] > (data_to_send->buffer[0] - 1)) + ? received_data->buffer[0] + : (data_to_send->buffer[0] - 1); + } + + if (max_bytes > HAL_ACI_MAX_LENGTH) + { + max_bytes = HAL_ACI_MAX_LENGTH; + } + + // Transmit/receive the rest of the packet + for (byte_cnt = 0; byte_cnt < max_bytes; byte_cnt++) + { + received_data->buffer[byte_cnt+1] = spi_readwrite(data_to_send->buffer[byte_sent_cnt++]); + } + + // RDYN should follow the REQN line in approx 100ns + m_aci_reqn_disable(); + + return (max_bytes > 0); +} + +#ifdef HAL_ACI_TL_DEBUG +void hal_aci_tl_debug_print(bool enable) +{ + aci_debug_print = enable; +} +#else +void hal_aci_tl_debug_print(bool /*enable*/) +{ +} +#endif + +void hal_aci_tl_pin_reset(void) +{ + if (UNUSED != a_pins_local_ptr->reset_pin) + { + pinMode(a_pins_local_ptr->reset_pin, OUTPUT); +#ifdef SUPPORT_REDBEARLAB_SHIELD_V1_1 + if ((REDBEARLAB_SHIELD_V1_1 == a_pins_local_ptr->board_name) || + (REDBEARLAB_SHIELD_V2012_07 == a_pins_local_ptr->board_name)) + { + //The reset for the Redbearlab v1.1 and v2012.07 boards are inverted and has a Power On Reset + //circuit that takes about 100ms to trigger the reset + digitalWrite(a_pins_local_ptr->reset_pin, 1); + delay(100); + digitalWrite(a_pins_local_ptr->reset_pin, 0); + } + else +#endif + { + digitalWrite(a_pins_local_ptr->reset_pin, 1); + digitalWrite(a_pins_local_ptr->reset_pin, 0); + digitalWrite(a_pins_local_ptr->reset_pin, 1); + } + } +} + +bool hal_aci_tl_event_peek(hal_aci_data_t *p_aci_data) +{ +#ifdef HAL_ACI_TL_INTERRUPT + if (!a_pins_local_ptr->interface_is_interrupt) +#endif + { + m_aci_event_check(); + } + + if (aci_queue_peek(&aci_rx_q, p_aci_data)) + { + return true; + } + + return false; +} + +bool hal_aci_tl_event_get(hal_aci_data_t *p_aci_data) +{ +#ifdef HAL_ACI_TL_INTERRUPT + bool was_full; +#endif + +#ifdef HAL_ACI_TL_INTERRUPT + if (!a_pins_local_ptr->interface_is_interrupt && !aci_queue_is_full(&aci_rx_q)) +#else + if (!aci_queue_is_full(&aci_rx_q)) +#endif + { + m_aci_event_check(); + } + +#ifdef HAL_ACI_TL_DEBUG + was_full = aci_queue_is_full(&aci_rx_q); +#else + aci_queue_is_full(&aci_rx_q); +#endif + + if (aci_queue_dequeue(&aci_rx_q, p_aci_data)) + { +#ifdef HAL_ACI_TL_DEBUG + if (aci_debug_print) + { + Serial.print(" E"); + m_aci_data_print(p_aci_data); + } +#endif + +#ifdef HAL_ACI_TL_INTERRUPT + if (was_full && a_pins_local_ptr->interface_is_interrupt) + { + /* Enable RDY line interrupt again */ + attachInterrupt(a_pins_local_ptr->interrupt_number, m_aci_isr, LOW); +#if defined(SPI_HAS_TRANSACTION) && defined(__SAMD21G18A__) + SPI.usingInterrupt(a_pins->interrupt_number); +#endif + } +#endif + + /* Attempt to pull REQN LOW since we've made room for new messages */ + if (!aci_queue_is_full(&aci_rx_q) && !aci_queue_is_empty(&aci_tx_q)) + { + m_aci_reqn_enable(); + } + + return true; + } + + return false; +} + +#ifdef HAL_ACI_TL_DEBUG +void hal_aci_tl_init(aci_pins_t *a_pins, bool debug) +#else +void hal_aci_tl_init(aci_pins_t *a_pins, bool /*debug*/) +#endif +{ +#ifdef HAL_ACI_TL_DEBUG + aci_debug_print = debug; +#endif + + /* Needs to be called as the first thing for proper intialization*/ + m_aci_pins_set(a_pins); + + /* + The SPI lines used are mapped directly to the hardware SPI + MISO MOSI and SCK + Change here if the pins are mapped differently + + The SPI library assumes that the hardware pins are used + */ + SPI.begin(); +#if !defined(SPI_HAS_TRANSACTION) || defined(__SAMD21G18A__) + //Board dependent defines + #if defined (__AVR__) || defined(__SAM3X8E__) || defined(__SAMD21G18A__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + //For Arduino use the LSB first + SPI.setBitOrder(LSBFIRST); + #elif defined(__PIC32MX__) + //For ChipKit use MSBFIRST and REVERSE the bits on the SPI as LSBFIRST is not supported + SPI.setBitOrder(MSBFIRST); + #else + #error "Unsupported platform" + #endif + SPI.setClockDivider(a_pins->spi_clock_divider); + SPI.setDataMode(SPI_MODE0); +#endif + + /* Initialize the ACI Command queue. This must be called after the delay above. */ + aci_queue_init(&aci_tx_q); + aci_queue_init(&aci_rx_q); + + //Configure the IO lines + pinMode(a_pins->rdyn_pin, INPUT_PULLUP); + pinMode(a_pins->reqn_pin, OUTPUT); + + if (UNUSED != a_pins->active_pin) + { + pinMode(a_pins->active_pin, INPUT); + } + /* Pin reset the nRF8001, required when the nRF8001 setup is being changed */ + hal_aci_tl_pin_reset(); + + /* Set the nRF8001 to a known state as required by the datasheet*/ + digitalWrite(a_pins->reqn_pin, 1); + + delay(30); //Wait for the nRF8001 to get hold of its lines - the lines float for a few ms after the reset + +#ifdef HAL_ACI_TL_INTERRUPT + /* Attach the interrupt to the RDYN line as requested by the caller */ + if (a_pins->interface_is_interrupt) + { + // We use the LOW level of the RDYN line as the atmega328 can wakeup from sleep only on LOW + attachInterrupt(a_pins->interrupt_number, m_aci_isr, LOW); + } +#endif +} + +bool hal_aci_tl_send(hal_aci_data_t *p_aci_cmd) +{ + const uint8_t length = p_aci_cmd->buffer[0]; + bool ret_val = false; + + if (length > HAL_ACI_MAX_LENGTH) + { + return false; + } + + ret_val = aci_queue_enqueue(&aci_tx_q, p_aci_cmd); + if (ret_val) + { + if(!aci_queue_is_full(&aci_rx_q)) + { + // Lower the REQN only when successfully enqueued + m_aci_reqn_enable(); + } + +#ifdef HAL_ACI_TL_DEBUG + if (aci_debug_print) + { + Serial.print("C"); //ACI Command + m_aci_data_print(p_aci_cmd); + } +#endif + } + + return ret_val; +} + +static uint8_t spi_readwrite(const uint8_t aci_byte) +{ + //Board dependent defines +#if defined (__AVR__) || defined(__SAM3X8E__) || defined(__SAMD21G18A__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + //For Arduino the transmission does not have to be reversed + return SPI.transfer(aci_byte); +#elif defined(__PIC32MX__) + //For ChipKit the transmission has to be reversed + uint8_t tmp_bits; + tmp_bits = SPI.transfer(REVERSE_BITS(aci_byte)); + return REVERSE_BITS(tmp_bits); +#else + #error "Unsupported platform" +#endif +} + +bool hal_aci_tl_rx_q_empty (void) +{ + return aci_queue_is_empty(&aci_rx_q); +} + +bool hal_aci_tl_rx_q_full (void) +{ + return aci_queue_is_full(&aci_rx_q); +} + +bool hal_aci_tl_tx_q_empty (void) +{ + return aci_queue_is_empty(&aci_tx_q); +} + +bool hal_aci_tl_tx_q_full (void) +{ + return aci_queue_is_full(&aci_tx_q); +} + +void hal_aci_tl_q_flush (void) +{ + m_aci_q_flush(); +} + +#endif diff --git a/cores/nRF5/utility/hal_aci_tl.h b/cores/nRF5/utility/hal_aci_tl.h new file mode 100644 index 00000000..cbcb18e0 --- /dev/null +++ b/cores/nRF5/utility/hal_aci_tl.h @@ -0,0 +1,180 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** @file + * @brief Interface for hal_aci_tl. + */ + +/** @defgroup hal_aci_tl hal_aci_tl +@{ +@ingroup hal + +@brief Module for the ACI Transport Layer interface +@details This module is responsible for sending and receiving messages over the ACI interface of the nRF8001 chip. + The hal_aci_tl_send_cmd() can be called directly to send ACI commands. + + +The RDYN line is hooked to an interrupt on the MCU when the level is low. +The SPI master clocks in the interrupt context. +The ACI Command is taken from the head of the command queue is sent over the SPI +and the received ACI event is placed in the tail of the event queue. + +*/ + +#ifndef HAL_ACI_TL_H__ +#define HAL_ACI_TL_H__ + +#include "hal_platform.h" +#include "aci.h" +#include "boards.h" + +#ifndef HAL_ACI_MAX_LENGTH +#define HAL_ACI_MAX_LENGTH 31 +#endif + +// #define HAL_ACI_TL_DEBUG +// #define HAL_ACI_TL_INTERRUPT +// #define SUPPORT_REDBEARLAB_SHIELD_V1_1 + +/************************************************************************/ +/* Unused nRF8001 pin */ +/************************************************************************/ +#define UNUSED 255 + +/** Data type for ACI commands and events */ +typedef struct { + uint8_t status_byte; + uint8_t buffer[HAL_ACI_MAX_LENGTH+1]; +} _aci_packed_ hal_aci_data_t; + +ACI_ASSERT_SIZE(hal_aci_data_t, HAL_ACI_MAX_LENGTH + 2); + +/** Datatype for ACI pins and interface (polling/interrupt)*/ +typedef struct aci_pins_t +{ + uint8_t reqn_pin; //Required + uint8_t rdyn_pin; //Required +#if !defined(SPI_HAS_TRANSACTION) || defined(__SAMD21G18A__) + uint8_t spi_clock_divider; //Required : Clock divider on the SPI clock : nRF8001 supports a maximum clock of 3MHz +#endif + uint8_t reset_pin; //Recommended but optional - Set it to UNUSED when not connected + uint8_t active_pin; //Optional - Set it to UNUSED when not connected + uint8_t optional_chip_sel_pin; //Optional - Used only when the reqn line is required to be separate from the SPI chip select. Eg. Arduino DUE +#ifdef HAL_ACI_TL_INTERRUPT + bool interface_is_interrupt; //Required - true = Uses interrupt on RDYN pin. false - Uses polling on RDYN pin + + uint8_t interrupt_number; //Required when using interrupts, otherwise ignored +#endif +} aci_pins_t; + +/** @brief ACI Transport Layer initialization. + * @details + * This function initializes the transport layer, including configuring the SPI, creating + * message queues for Commands and Events and setting up interrupt if required. + * @param a_pins Pins on the MCU used to connect to the nRF8001 + * @param bool True if debug printing should be enabled on the Serial. + */ +void hal_aci_tl_init(aci_pins_t *a_pins, bool debug); + +/** @brief Sends an ACI command to the radio. + * @details + * This function sends an ACI command to the radio. This queue up the message to send and + * lower the request line. When the device lowers the ready line, @ref m_aci_spi_transfer() + * will send the data. + * @param aci_buffer Pointer to the message to send. + * @return True if the data was successfully queued for sending, + * false if there is no more space to store messages to send. + */ +bool hal_aci_tl_send(hal_aci_data_t *aci_buffer); + +/** @brief Process pending transactions. + * @details + * The library code takes care of calling this function to check if the nRF8001 RDYN line indicates a + * pending transaction. It will send a pending message if there is one and return any receive message + * that was pending. + * @return Points to data buffer for received data. Length byte in buffer is 0 if no data received. + */ +hal_aci_data_t * hal_aci_tl_poll_get(void); + +/** @brief Get an ACI event from the event queue + * @details + * Call this function from the main context to get an event from the ACI event queue + * This is called by lib_aci_event_get + */ +bool hal_aci_tl_event_get(hal_aci_data_t *p_aci_data); + +/** @brief Peek an ACI event from the event queue + * @details + * Call this function from the main context to peek an event from the ACI event queue. + * This is called by lib_aci_event_peek + */ +bool hal_aci_tl_event_peek(hal_aci_data_t *p_aci_data); + +/** @brief Enable debug printing of all ACI commands sent and ACI events received + * @details + * when the enable parameter is true. The debug printing is enabled on the Serial. + * When the enable parameter is false. The debug printing is disabled on the Serial. + * By default the debug printing is disabled. + */ +void hal_aci_tl_debug_print(bool enable); + + +/** @brief Pin reset the nRF8001 + * @details + * The reset line of the nF8001 needs to kept low for 200 ns. + * Redbearlab shield v1.1 and v2012.07 are exceptions as they + * have a Power ON Reset circuit that works differently. + * The function handles the exceptions based on the board_name in aci_pins_t + */ +void hal_aci_tl_pin_reset(void); + +/** @brief Return full status of transmit queue + * @details + * + */ + bool hal_aci_tl_rx_q_full(void); + + /** @brief Return empty status of receive queue + * @details + * + */ + bool hal_aci_tl_rx_q_empty(void); + +/** @brief Return full status of receive queue + * @details + * + */ + bool hal_aci_tl_tx_q_full(void); + + /** @brief Return empty status of transmit queue + * @details + * + */ + bool hal_aci_tl_tx_q_empty(void); + +/** @brief Flush the ACI command Queue and the ACI Event Queue + * @details + * Call this function in the main thread + */ +void hal_aci_tl_q_flush(void); + +#endif // HAL_ACI_TL_H__ +/** @} */ diff --git a/cores/nRF5/utility/hal_platform.h b/cores/nRF5/utility/hal_platform.h new file mode 100644 index 00000000..3b941085 --- /dev/null +++ b/cores/nRF5/utility/hal_platform.h @@ -0,0 +1,78 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef PLATFORM_H__ +#define PLATFORM_H__ + +/** @file +* @brief +*/ + +//Board dependent defines +#if defined (__AVR__) || defined(__SAM3X8E__) || defined(__SAMD21G18A__) || defined(__MK20DX128__) || defined(__MK20DX256__) || defined(__MKL26Z64__) + //For Arduino this AVR specific library has to be used for reading from Flash memory + #include + #include "Arduino.h" + #ifdef PROGMEM + #undef PROGMEM + #define PROGMEM __attribute__(( section(".progmem.data") )) + #endif +#elif defined(__PIC32MX__) + //For Chipkit add the following libraries. + #include + #include + #include + #include + #include + + //For making the Serial.Print compatible between Arduino and Chipkit + #define F(X) (X) + + //For ChipKit neither PROGMEM or PSTR are needed for PIC32 + #define PROGMEM + #define PSTR(s) (s) + + #define pgm_read_byte(x) (*((char *)x)) + #define pgm_read_byte_near(x) (*((char *)x)) + #define pgm_read_byte_far(x) (*((char *)x)) + #define pgm_read_word(x) (*((short *)x)) + #define pgm_read_word_near(x) (*((short *)x)) + #define pgm_read_workd_far(x) (*((short *)x)) + + #define prog_void const void + #define prog_char const char + #define prog_uchar const unsigned char + #define prog_int8_t const int8_t + #define prog_uint8_t const uint8_t + #define prog_int16_t const int16_t + #define prog_uint16_t const uint16_t + #define prog_int32_t const int32_t + #define prog_uint32_t const uint32_t + #define prog_int64_t const int64_t + #define prog_uint64_t const uint64_t + + //Redefine the function for reading from flash in ChipKit + #define memcpy_P memcpy +#else + #error "Unsupported platform" +#endif + +#endif /* PLATFORM_H__ */ diff --git a/cores/nRF5/utility/lib_aci.cpp b/cores/nRF5/utility/lib_aci.cpp new file mode 100644 index 00000000..73e1a373 --- /dev/null +++ b/cores/nRF5/utility/lib_aci.cpp @@ -0,0 +1,696 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/** @file + @brief Implementation of the ACI library. + */ + +#if !defined(NRF51) && !defined(NRF52) &&!defined(__RFduino__) + +#include "hal_platform.h" +#include "aci.h" +#include "aci_cmds.h" +#include "aci_evts.h" +#include "aci_protocol_defines.h" +#include "acilib_defs.h" +#include "acilib_if.h" +#include "hal_aci_tl.h" +#include "aci_queue.h" +#include "lib_aci.h" + + +#define LIB_ACI_DEFAULT_CREDIT_NUMBER 1 + +/* +Global additionally used used in aci_setup +*/ +hal_aci_data_t msg_to_send; + +// The following structure (aci_cmd_params_open_adv_pipe) will be used to store the complete command +// including the pipes to be opened. +static aci_cmd_params_open_adv_pipe_t aci_cmd_params_open_adv_pipe; + + + +extern aci_queue_t aci_rx_q; +extern aci_queue_t aci_tx_q; + +bool lib_aci_is_pipe_available(aci_state_t *aci_stat, uint8_t pipe) +{ + uint8_t byte_idx; + + byte_idx = pipe / 8; + if (aci_stat->pipes_open_bitmap[byte_idx] & (0x01 << (pipe % 8))) + { + return(true); + } + return(false); +} + + +bool lib_aci_is_pipe_closed(aci_state_t *aci_stat, uint8_t pipe) +{ + uint8_t byte_idx; + + byte_idx = pipe / 8; + if (aci_stat->pipes_closed_bitmap[byte_idx] & (0x01 << (pipe % 8))) + { + return(true); + } + return(false); +} + + +bool lib_aci_is_discovery_finished(aci_state_t *aci_stat) +{ + return(aci_stat->pipes_open_bitmap[0]&0x01); +} + +void lib_aci_board_init(aci_state_t *aci_stat) +{ +#ifdef SUPPORT_REDBEARLAB_SHIELD_V1_1 + hal_aci_evt_t *aci_data = NULL; + aci_data = (hal_aci_evt_t *)&msg_to_send; + + if (REDBEARLAB_SHIELD_V1_1 == aci_stat->aci_pins.board_name) + { + /* + The Bluetooth low energy Arduino shield v1.1 requires about 100ms to reset. + This is not required for the nRF2740, nRF2741 modules + */ + delay(100); + + /* + Send the soft reset command to the nRF8001 to get the nRF8001 to a known state. + */ + lib_aci_radio_reset(); + + while (1) + { + /*Wait for the command response of the radio reset command. + as the nRF8001 will be in either SETUP or STANDBY after the ACI Reset Radio is processed + */ + + + if (true == lib_aci_event_get(aci_stat, aci_data)) + { + aci_evt_t * aci_evt; + aci_evt = &(aci_data->evt); + + if (ACI_EVT_CMD_RSP == aci_evt->evt_opcode) + { + if (ACI_STATUS_ERROR_DEVICE_STATE_INVALID == aci_evt->params.cmd_rsp.cmd_status) //in SETUP + { + //Inject a Device Started Event Setup to the ACI Event Queue + msg_to_send.buffer[0] = 4; //Length + msg_to_send.buffer[1] = 0x81; //Device Started Event + msg_to_send.buffer[2] = 0x02; //Setup + msg_to_send.buffer[3] = 0; //Hardware Error -> None + msg_to_send.buffer[4] = 2; //Data Credit Available + aci_queue_enqueue(&aci_rx_q, &msg_to_send); + } + else if (ACI_STATUS_SUCCESS == aci_evt->params.cmd_rsp.cmd_status) //We are now in STANDBY + { + //Inject a Device Started Event Standby to the ACI Event Queue + msg_to_send.buffer[0] = 4; //Length + msg_to_send.buffer[1] = 0x81; //Device Started Event + msg_to_send.buffer[2] = 0x03; //Standby + msg_to_send.buffer[3] = 0; //Hardware Error -> None + msg_to_send.buffer[4] = 2; //Data Credit Available + aci_queue_enqueue(&aci_rx_q, &msg_to_send); + } + else if (ACI_STATUS_ERROR_CMD_UNKNOWN == aci_evt->params.cmd_rsp.cmd_status) //We are now in TEST + { + //Inject a Device Started Event Test to the ACI Event Queue + msg_to_send.buffer[0] = 4; //Length + msg_to_send.buffer[1] = 0x81; //Device Started Event + msg_to_send.buffer[2] = 0x01; //Test + msg_to_send.buffer[3] = 0; //Hardware Error -> None + msg_to_send.buffer[4] = 0; //Data Credit Available + aci_queue_enqueue(&aci_rx_q, &msg_to_send); + } + + //Break out of the while loop + break; + } + else + { + //Serial.println(F("Discard any other ACI Events")); + } + + } + } + } +#else + if (aci_stat->aci_pins.reset_pin == UNUSED) { + delay(100); + + lib_aci_radio_reset(); + } +#endif +} + + +void lib_aci_init(aci_state_t *aci_stat, bool debug) +{ + uint8_t i; + + for (i = 0; i < PIPES_ARRAY_SIZE; i++) + { + aci_stat->pipes_open_bitmap[i] = 0; + aci_stat->pipes_closed_bitmap[i] = 0; + aci_cmd_params_open_adv_pipe.pipes[i] = 0; + } + + hal_aci_tl_init(&aci_stat->aci_pins, debug); + + lib_aci_board_init(aci_stat); +} + + +uint8_t lib_aci_get_nb_available_credits(aci_state_t *aci_stat) +{ + return aci_stat->data_credit_available; +} + +uint16_t lib_aci_get_cx_interval_ms(aci_state_t *aci_stat) +{ + uint32_t cx_rf_interval_ms_32bits; + uint16_t cx_rf_interval_ms; + + cx_rf_interval_ms_32bits = aci_stat->connection_interval; + cx_rf_interval_ms_32bits *= 125; // the connection interval is given in multiples of 0.125 milliseconds + cx_rf_interval_ms = cx_rf_interval_ms_32bits / 100; + + return cx_rf_interval_ms; +} + + +uint16_t lib_aci_get_cx_interval(aci_state_t *aci_stat) +{ + return aci_stat->connection_interval; +} + + +uint16_t lib_aci_get_slave_latency(aci_state_t *aci_stat) +{ + return aci_stat->slave_latency; +} + + +bool lib_aci_set_app_latency(uint16_t latency, aci_app_latency_mode_t latency_mode) +{ + aci_cmd_params_set_app_latency_t aci_set_app_latency; + + aci_set_app_latency.mode = latency_mode; + aci_set_app_latency.latency = latency; + acil_encode_cmd_set_app_latency(&(msg_to_send.buffer[0]), &aci_set_app_latency); + + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_test(aci_test_mode_change_t enter_exit_test_mode) +{ + aci_cmd_params_test_t aci_cmd_params_test; + aci_cmd_params_test.test_mode_change = enter_exit_test_mode; + acil_encode_cmd_set_test_mode(&(msg_to_send.buffer[0]), &aci_cmd_params_test); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_sleep() +{ + acil_encode_cmd_sleep(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_radio_reset() +{ + acil_encode_baseband_reset(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_direct_connect() +{ + acil_encode_direct_connect(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_device_version() +{ + acil_encode_cmd_get_device_version(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_set_local_data(aci_state_t * /*aci_stat*/, uint8_t pipe, uint8_t *p_value, uint8_t size) +{ + aci_cmd_params_set_local_data_t aci_cmd_params_set_local_data; + + aci_cmd_params_set_local_data.tx_data.pipe_number = pipe; + memcpy(&(aci_cmd_params_set_local_data.tx_data.aci_data[0]), p_value, size); + acil_encode_cmd_set_local_data(&(msg_to_send.buffer[0]), &aci_cmd_params_set_local_data, size); + return hal_aci_tl_send(&msg_to_send); +} + +bool lib_aci_connect(uint16_t run_timeout, uint16_t adv_interval) +{ + aci_cmd_params_connect_t aci_cmd_params_connect; + aci_cmd_params_connect.timeout = run_timeout; + aci_cmd_params_connect.adv_interval = adv_interval; + acil_encode_cmd_connect(&(msg_to_send.buffer[0]), &aci_cmd_params_connect); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_disconnect(aci_state_t *aci_stat, aci_disconnect_reason_t reason) +{ + bool ret_val; + uint8_t i; + aci_cmd_params_disconnect_t aci_cmd_params_disconnect; + aci_cmd_params_disconnect.reason = reason; + acil_encode_cmd_disconnect(&(msg_to_send.buffer[0]), &aci_cmd_params_disconnect); + ret_val = hal_aci_tl_send(&msg_to_send); + // If we have actually sent the disconnect + if (ret_val) + { + // Update pipes immediately so that while the disconnect is happening, + // the application can't attempt sending another message + // If the application sends another message before we updated this + // a ACI Pipe Error Event will be received from nRF8001 + for (i=0; i < PIPES_ARRAY_SIZE; i++) + { + aci_stat->pipes_open_bitmap[i] = 0; + aci_stat->pipes_closed_bitmap[i] = 0; + } + } + return ret_val; +} + + +bool lib_aci_bond(uint16_t run_timeout, uint16_t adv_interval) +{ + aci_cmd_params_bond_t aci_cmd_params_bond; + aci_cmd_params_bond.timeout = run_timeout; + aci_cmd_params_bond.adv_interval = adv_interval; + acil_encode_cmd_bond(&(msg_to_send.buffer[0]), &aci_cmd_params_bond); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_wakeup() +{ + acil_encode_cmd_wakeup(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_set_tx_power(aci_device_output_power_t tx_power) +{ + aci_cmd_params_set_tx_power_t aci_cmd_params_set_tx_power; + aci_cmd_params_set_tx_power.device_power = tx_power; + acil_encode_cmd_set_radio_tx_power(&(msg_to_send.buffer[0]), &aci_cmd_params_set_tx_power); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_get_address() +{ + acil_encode_cmd_get_address(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_get_temperature() +{ + acil_encode_cmd_temparature(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_get_battery_level() +{ + acil_encode_cmd_battery_level(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_send_data(uint8_t pipe, uint8_t *p_value, uint8_t size) +{ + bool ret_val = false; + aci_cmd_params_send_data_t aci_cmd_params_send_data; + + if (size > ACI_PIPE_TX_DATA_MAX_LEN) + { + return false; + } + { + aci_cmd_params_send_data.tx_data.pipe_number = pipe; + memcpy(&(aci_cmd_params_send_data.tx_data.aci_data[0]), p_value, size); + acil_encode_cmd_send_data(&(msg_to_send.buffer[0]), &aci_cmd_params_send_data, size); + + ret_val = hal_aci_tl_send(&msg_to_send); + } + return ret_val; +} + + +bool lib_aci_request_data(aci_state_t * /*aci_stat*/, uint8_t pipe) +{ + bool ret_val = false; + aci_cmd_params_request_data_t aci_cmd_params_request_data; + + { + + { + + + + aci_cmd_params_request_data.pipe_number = pipe; + acil_encode_cmd_request_data(&(msg_to_send.buffer[0]), &aci_cmd_params_request_data); + + ret_val = hal_aci_tl_send(&msg_to_send); + } + } + return ret_val; +} + + +bool lib_aci_change_timing(uint16_t minimun_cx_interval, uint16_t maximum_cx_interval, uint16_t slave_latency, uint16_t timeout) +{ + aci_cmd_params_change_timing_t aci_cmd_params_change_timing; + aci_cmd_params_change_timing.conn_params.min_conn_interval = minimun_cx_interval; + aci_cmd_params_change_timing.conn_params.max_conn_interval = maximum_cx_interval; + aci_cmd_params_change_timing.conn_params.slave_latency = slave_latency; + aci_cmd_params_change_timing.conn_params.timeout_mult = timeout; + acil_encode_cmd_change_timing_req(&(msg_to_send.buffer[0]), &aci_cmd_params_change_timing); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_change_timing_GAP_PPCP() +{ + acil_encode_cmd_change_timing_req_GAP_PPCP(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_open_remote_pipe(aci_state_t * /*aci_stat*/, uint8_t pipe) +{ + bool ret_val = false; + aci_cmd_params_open_remote_pipe_t aci_cmd_params_open_remote_pipe; + + { + + // is_request_operation_pending = true; + // is_open_remote_pipe_pending = true; + // request_operation_pipe = pipe; + aci_cmd_params_open_remote_pipe.pipe_number = pipe; + acil_encode_cmd_open_remote_pipe(&(msg_to_send.buffer[0]), &aci_cmd_params_open_remote_pipe); + ret_val = hal_aci_tl_send(&msg_to_send); + } + return ret_val; +} + + +bool lib_aci_close_remote_pipe(aci_state_t * /*aci_stat*/, uint8_t pipe) +{ + bool ret_val = false; + aci_cmd_params_close_remote_pipe_t aci_cmd_params_close_remote_pipe; + + { + + // is_request_operation_pending = true; + // is_close_remote_pipe_pending = true; + // request_operation_pipe = pipe; + aci_cmd_params_close_remote_pipe.pipe_number = pipe; + acil_encode_cmd_close_remote_pipe(&(msg_to_send.buffer[0]), &aci_cmd_params_close_remote_pipe); + ret_val = hal_aci_tl_send(&msg_to_send); + } + return ret_val; +} + + +bool lib_aci_set_key(aci_key_type_t key_rsp_type, uint8_t *key, uint8_t len) +{ + aci_cmd_params_set_key_t aci_cmd_params_set_key; + aci_cmd_params_set_key.key_type = key_rsp_type; + memcpy((uint8_t*)&(aci_cmd_params_set_key.key), key, len); + acil_encode_cmd_set_key(&(msg_to_send.buffer[0]), &aci_cmd_params_set_key); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_echo_msg(uint8_t msg_size, uint8_t *p_msg_data) +{ + aci_cmd_params_echo_t aci_cmd_params_echo; + if(msg_size > (ACI_ECHO_DATA_MAX_LEN)) + { + return false; + } + + if (msg_size > (ACI_ECHO_DATA_MAX_LEN)) + { + msg_size = ACI_ECHO_DATA_MAX_LEN; + } + + memcpy(&(aci_cmd_params_echo.echo_data[0]), p_msg_data, msg_size); + acil_encode_cmd_echo_msg(&(msg_to_send.buffer[0]), &aci_cmd_params_echo, msg_size); + + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_bond_request() +{ + acil_encode_cmd_bond_security_request(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + +bool lib_aci_event_peek(hal_aci_evt_t *p_aci_evt_data) +{ + return hal_aci_tl_event_peek((hal_aci_data_t *)p_aci_evt_data); +} + +bool lib_aci_event_get(aci_state_t *aci_stat, hal_aci_evt_t *p_aci_evt_data) +{ + bool status = false; + + status = hal_aci_tl_event_get((hal_aci_data_t *)p_aci_evt_data); + + /** + Update the state of the ACI with the + ACI Events -> Pipe Status, Disconnected, Connected, Bond Status, Pipe Error + */ + if (true == status) + { + aci_evt_t * aci_evt; + + aci_evt = &p_aci_evt_data->evt; + + switch(aci_evt->evt_opcode) + { + case ACI_EVT_PIPE_STATUS: + { + uint8_t i=0; + + for (i=0; i < PIPES_ARRAY_SIZE; i++) + { + aci_stat->pipes_open_bitmap[i] = aci_evt->params.pipe_status.pipes_open_bitmap[i]; + aci_stat->pipes_closed_bitmap[i] = aci_evt->params.pipe_status.pipes_closed_bitmap[i]; + } + } + break; + + case ACI_EVT_DISCONNECTED: + { + uint8_t i=0; + + for (i=0; i < PIPES_ARRAY_SIZE; i++) + { + aci_stat->pipes_open_bitmap[i] = 0; + aci_stat->pipes_closed_bitmap[i] = 0; + } + aci_stat->confirmation_pending = false; + aci_stat->data_credit_available = aci_stat->data_credit_total; + + } + break; + + case ACI_EVT_TIMING: + aci_stat->connection_interval = aci_evt->params.timing.conn_rf_interval; + aci_stat->slave_latency = aci_evt->params.timing.conn_slave_rf_latency; + aci_stat->supervision_timeout = aci_evt->params.timing.conn_rf_timeout; + break; + + case ACI_EVT_CONNECTED: + aci_stat->connection_interval = aci_evt->params.connected.conn_rf_interval; + aci_stat->slave_latency = aci_evt->params.connected.conn_slave_rf_latency; + aci_stat->supervision_timeout = aci_evt->params.connected.conn_rf_timeout; + break; + + default: + /* Need default case to avoid compiler warnings about missing enum + * values on some platforms. + */ + break; + + + + } + } + return status; +} + + +bool lib_aci_send_ack(aci_state_t * /*aci_stat*/, const uint8_t pipe) +{ + bool ret_val = false; + { + acil_encode_cmd_send_data_ack(&(msg_to_send.buffer[0]), pipe); + + ret_val = hal_aci_tl_send(&msg_to_send); + } + return ret_val; +} + + +bool lib_aci_send_nack(aci_state_t * /*aci_stat*/, const uint8_t pipe, const uint8_t error_code) +{ + bool ret_val = false; + + { + + acil_encode_cmd_send_data_nack(&(msg_to_send.buffer[0]), pipe, error_code); + ret_val = hal_aci_tl_send(&msg_to_send); + } + return ret_val; +} + + +bool lib_aci_broadcast(const uint16_t timeout, const uint16_t adv_interval) +{ + aci_cmd_params_broadcast_t aci_cmd_params_broadcast; + if (timeout > 16383) + { + return false; + } + + // The adv_interval should be between 160 and 16384 (which translates to the advertisement + // interval values 100 ms and 10.24 s. + if ((160 > adv_interval) || (adv_interval > 16384)) + { + return false; + } + + aci_cmd_params_broadcast.timeout = timeout; + aci_cmd_params_broadcast.adv_interval = adv_interval; + acil_encode_cmd_broadcast(&(msg_to_send.buffer[0]), &aci_cmd_params_broadcast); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_open_adv_pipes(const uint8_t * const adv_service_data_pipes) +{ + uint8_t i; + + for (i = 0; i < PIPES_ARRAY_SIZE; i++) + { + aci_cmd_params_open_adv_pipe.pipes[i] = adv_service_data_pipes[i]; + } + + acil_encode_cmd_open_adv_pipes(&(msg_to_send.buffer[0]), &aci_cmd_params_open_adv_pipe); + return hal_aci_tl_send(&msg_to_send); +} + +bool lib_aci_open_adv_pipe(const uint8_t pipe) +{ + uint8_t byte_idx = pipe / 8; + + aci_cmd_params_open_adv_pipe.pipes[byte_idx] |= (0x01 << (pipe % 8)); + acil_encode_cmd_open_adv_pipes(&(msg_to_send.buffer[0]), &aci_cmd_params_open_adv_pipe); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_read_dynamic_data() +{ + acil_encode_cmd_read_dynamic_data(&(msg_to_send.buffer[0])); + return hal_aci_tl_send(&msg_to_send); +} + + +bool lib_aci_write_dynamic_data(uint8_t sequence_number, uint8_t* dynamic_data, uint8_t length) +{ + acil_encode_cmd_write_dynamic_data(&(msg_to_send.buffer[0]), sequence_number, dynamic_data, length); + return hal_aci_tl_send(&msg_to_send); +} + +bool lib_aci_dtm_command(uint8_t dtm_command_msbyte, uint8_t dtm_command_lsbyte) +{ + aci_cmd_params_dtm_cmd_t aci_cmd_params_dtm_cmd; + aci_cmd_params_dtm_cmd.cmd_msb = dtm_command_msbyte; + aci_cmd_params_dtm_cmd.cmd_lsb = dtm_command_lsbyte; + acil_encode_cmd_dtm_cmd(&(msg_to_send.buffer[0]), &aci_cmd_params_dtm_cmd); + return hal_aci_tl_send(&msg_to_send); +} + +void lib_aci_flush(void) +{ + hal_aci_tl_q_flush(); +} + +void lib_aci_debug_print(bool enable) +{ + hal_aci_tl_debug_print(enable); + +} + +void lib_aci_pin_reset(void) +{ + hal_aci_tl_pin_reset(); +} + +bool lib_aci_event_queue_empty(void) +{ + return hal_aci_tl_rx_q_empty(); +} + +bool lib_aci_event_queue_full(void) +{ + return hal_aci_tl_rx_q_full(); +} + +bool lib_aci_command_queue_empty(void) +{ + return hal_aci_tl_tx_q_empty(); +} + +bool lib_aci_command_queue_full(void) +{ + return hal_aci_tl_tx_q_full(); +} + +#endif diff --git a/cores/nRF5/utility/lib_aci.h b/cores/nRF5/utility/lib_aci.h new file mode 100644 index 00000000..84889778 --- /dev/null +++ b/cores/nRF5/utility/lib_aci.h @@ -0,0 +1,540 @@ +/* Copyright (c) 2014, Nordic Semiconductor ASA + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIB_ACI_H__ +#define LIB_ACI_H__ + +/** @file +* @brief ACI library +*/ + +/** @addtogroup lib_aci +@{ +@brief Library for the logical part of the Application Controller Interface (ACI) +*/ + +#include "hal_platform.h" +#include "hal_aci_tl.h" +#include "aci_queue.h" +#include "aci.h" +#include "aci_cmds.h" +#include "aci_evts.h" + + +#define EVT_CMD_RESPONSE_MIN_LENGTH 3 + +#define PIPES_ARRAY_SIZE ((ACI_DEVICE_MAX_PIPES + 7)/8) + +/* Same size as a hal_aci_data_t */ +typedef struct { + uint8_t debug_byte; + aci_evt_t evt; +} _aci_packed_ hal_aci_evt_t; + +ACI_ASSERT_SIZE(hal_aci_evt_t, 34); + +// aci_struct that will contain +// total initial credits +// current credit +// current state of the aci (setup/standby/active/sleep) +// open remote pipe pending +// close remote pipe pending +// Current pipe available bitmap +// Current pipe closed bitmap +// Current connection interval, slave latency and link supervision timeout +// Current State of the the GATT client (Service Discovery status) +// Relationship of bond to peer address +typedef struct aci_state_t +{ + aci_pins_t aci_pins; /* Pins on the MCU used to connect to the nRF8001 */ + uint8_t bonded; /* ( aci_bond_status_code_t ) Is the nRF8001 bonded to a peer device */ + uint8_t data_credit_total; /* Total data credit available for the specific version of the nRF8001, total equals available when a link is established */ + aci_device_operation_mode_t device_state; /* Operating mode of the nRF8001 */ + + /* */ + + /* Start : Variables that are valid only when in a connection */ + uint8_t data_credit_available; /* Available data credits at a specific point of time, ACI_EVT_DATA_CREDIT updates the available credits */ + + uint16_t connection_interval; /* Multiply by 1.25 to get the connection interval in milliseconds*/ + uint16_t slave_latency; /* Number of consecutive connection intervals that the nRF8001 is not required to transmit. Use this to save power */ + uint16_t supervision_timeout; /* Multiply by 10 to get the supervision timeout in milliseconds */ + + uint8_t pipes_open_bitmap[PIPES_ARRAY_SIZE]; /* Bitmap -> pipes are open and can be used for sending data over the air */ + uint8_t pipes_closed_bitmap[PIPES_ARRAY_SIZE]; /* Bitmap -> pipes are closed and cannot be used for sending data over the air */ + bool confirmation_pending; /* Attribute protocol Handle Value confirmation is pending for a Handle Value Indication + (ACK is pending for a TX_ACK pipe) on local GATT Server*/ + /* End : Variables that are valid only when in a connection */ + +} aci_state_t; + + + +#define DISCONNECT_REASON_CX_TIMEOUT 0x08 +#define DISCONNECT_REASON_CX_CLOSED_BY_PEER_DEVICE 0x13 +#define DISCONNECT_REASON_POWER_LOSS 0x14 +#define DISCONNECT_REASON_CX_CLOSED_BY_LOCAL_DEVICE 0x16 +#define DISCONNECT_REASON_ADVERTISER_TIMEOUT 0x50 + + +/** @name Functions for library management */ +//@{ + +/** @brief Function to enable printing of all ACI commands sent and ACI events received + * @details This function shall be used to enable or disable the debug printing. + Debug printing is disabled by default. + */ +void lib_aci_debug_print(bool enable); + +/** @brief Function to pin reset the nRF8001 + * @details Pin resets the nRF8001 also handles differences between development boards + */ +void lib_aci_pin_reset(void); + +/** @brief Initialization function. + * @details This function shall be used to initialize/reset ACI Library and also Resets the + * nRF8001 by togging the reset pin of the nRF8001. This function will reset + * all the variables locally used by ACI library to their respective default values. + * @param bool True if the data was successfully queued for sending, + * false if there is no more space to store messages to send. + */ +void lib_aci_init(aci_state_t *aci_stat, bool debug); + + +/** @brief Gets the number of currently available ACI credits. + * @return Number of ACI credits. + */ +uint8_t lib_aci_get_nb_available_credits(aci_state_t *aci_stat); + +/** @brief Gets the connection interval in milliseconds. + * @return Connection interval in milliseconds. + */ +uint16_t lib_aci_get_cx_interval_ms(aci_state_t *aci_stat); + +/** @brief Gets the connection interval in multiple of 1.25 ms. + * @return Connection interval in multiple of 1.25 ms. + */ +uint16_t lib_aci_get_cx_interval(aci_state_t *aci_stat); + +/** @brief Gets the current slave latency. + * @return Current slave latency. + */ +uint16_t lib_aci_get_slave_latency(aci_state_t *aci_stat); + +/** @brief Checks if a given pipe is available. + * @param pipe Pipe to check. + * @return True if the pipe is available, otherwise false. + */ +bool lib_aci_is_pipe_available(aci_state_t *aci_stat, uint8_t pipe); + +/** @brief Checks if a given pipe is closed. + * @param pipe Pipe to check. + * @return True if the pipe is closed, otherwise false. + */ +bool lib_aci_is_pipe_closed(aci_state_t *aci_stat, uint8_t pipe); + +/** @brief Checks if the discovery operation is finished. + * @return True if the discovery is finished. + */ +bool lib_aci_is_discovery_finished(aci_state_t *aci_stat); + + + +//@} + +/** @name ACI Commands available in all modes */ +//@{ + +/** @brief Sets the radio in sleep mode. + * @details The function sends a @c sleep command to the radio. + * If the radio is advertising or connected, it sends back an error, then use lib_aci_radio_reset + * if advertising or disconnect if in a connection. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_sleep(void); + +/** @brief Resets the radio. + * @details The function sends a @c BasebandReset command to the radio. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_radio_reset(void); + +/** @brief Radio starts directed advertising to bonded device. + * @details The function sends a @c DirectedConnect command to the radio. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_direct_connect(void); + +/** @brief Gets the radio's version. + * @details This function sends a @c GetDeviceVersion command. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_device_version(void); + +/** @brief Gets the device address. + * @details This function sends a @c GetDeviceAddress command. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_get_address(void); + +/** @brief Gets the temperature. + * @details This function sends a @c GetTemperature command. lib_aci + * calls the @ref lib_aci_transaction_finished_hook() function when the temperature is received. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_get_temperature(void); + +/** @brief Gets the battery level. + * @details This function sends a @c GetBatteryLevel command. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_get_battery_level(void); + +//@} + +/** @name ACI commands available in Sleep mode */ +//@{ + +/** @brief Wakes up the radio. + * @details This function sends a @c Wakeup command to wake up the radio from + * sleep mode. When woken up the radio sends a @c DeviceStartedEvent and + * a @c CommandResponseEvent. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_wakeup(void); + +//@} + +/** @name ACI commands available in Active mode */ +//@{ + +/** @brief Sets the radio in test mode. + * @details This function sends a @c Test command to the radio. There are two + * Test modes available: + * - UART: DTM commands are received over UART. + * - ACI: DTM commands are received over ACI. + * The same command is used to exit the test mode When receiving + * a @c DeviceStartedEvent the radio has entered the new mode. + * @param enter_exit_test_mode Enter a Test mode, or exit Test mode. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_test(aci_test_mode_change_t enter_exit_test_mode); + +/** @brief Sets the radio's TX power. + * @details This function sends a @c SetTxPower command. + * @param tx_power TX power to be used by the radio. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_set_tx_power(aci_device_output_power_t tx_power); + +/** @brief Tries to connect to a peer device. + * @details This function sends a @c Connect command to the radio. + * @param run_timeout Maximum advertising time in seconds (0 means infinite). + * @param adv_interval Advertising interval (in multiple of 0.625 ms). + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_connect(uint16_t run_timeout, uint16_t adv_interval); + +/** @brief Tries to bond with a peer device. + * @details This function sends a @c Bond command to the radio. + * @param run_timeout Maximum advertising time in seconds (0 means infinite). + * @param adv_interval Advertising interval (in multiple of 0.625 ms). + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_bond(uint16_t run_timeout, uint16_t adv_interval); + +/** @brief Disconnects from peer device. + * @details This function sends a @c Disconnect command to the radio. + * @param reason Reason for disconnecting. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_disconnect(aci_state_t *aci_stat, aci_disconnect_reason_t reason); + +/**@brief Sets Local Data. + * @details + * This command updates the value of the characteristic value or the characteristic descriptor stored locally on the device. + * Can be called for all types of pipes as long as the data is stored locally. + * @param ACI state structure + * @param pipe Pipe number on which the data should be set. + * @param value Pointer to the data to set. + * @param size Size of the data to set. + * @return True if the transaction is successfully initiated. +*/ +bool lib_aci_set_local_data(aci_state_t *aci_stat, uint8_t pipe, uint8_t *value, uint8_t size); + +/** @brief Sends Broadcast message to the radio. + * @details The Broadcast message starts advertisement procedure + * using the given interval with the intention of broadcasting data to a peer device. + * @param timeout Time, in seconds, to advertise before exiting to standby mode (0 means infinite). + * Valid values: 0 to 16383. + * @param adv_interval Advertising interval (in multiple of 0.625 ms). + * Valid values: 160 to 16384 (which corresponds to an interval from 100 ms to 10.24 s). + * @return True if the broadcast message is sent successfully to the radio. +*/ +bool lib_aci_broadcast(const uint16_t timeout, const uint16_t adv_interval); + +/** @name Open Advertising Pipes. */ + +/** @brief Sends a command to the radio to set the input pipe to be placed in Advertisement Service Data. + * @details This function sends a command to the radio that places the pipe in + * advertisement service data. To start advertising service data, call this function before + * Connecting, Broadcasting or Bonding to peer. The data that should be sent in the advertisement packets + * must be set using the @c lib_aci_set_local_data function. This function can be called during + * advertising to enable/disable broadcast pipes. + * @param pipe The pipe that has to be placed in advertising service data. + * @return True if the Open Adv Pipe message is sent successfully to the radio. +*/ +bool lib_aci_open_adv_pipe(const uint8_t pipe); + + +/** @name Open Advertising Pipes */ + +/** @brief Sends a command to the radio to set the pipes to be placed in Advertisement Service Data. + * @details This function will send a command to the radio that will set the pipes to be placed in + * advertisement Service Data. To start advertising service data, this function should be called before + * Connecting, Broadcasting or Bonding to peer. This function can be called during + * advertising to enable/disable broadcast pipes. Use this as an alternative to @ref lib_aci_open_adv_pipe + * to avoid multiple function calls for placing multiple pipes in the adv data. + * @param adv_service_data_pipes Pipe bitmap, where '1' indicates that the corresponding + * Valid Values: 0000000000000000 to FEFFFFFFFFFFFF7F (See the ACI Pipe Status Evt bitmap in the nRF8001 datasheet + * TX_BROADCAST pipe data is to be placed in Advertising Service Data fields + * @return true if the Open Adv Pipe message was sent successfully to the radio. +*/ +bool lib_aci_open_adv_pipes(const uint8_t * const adv_service_data_pipes); + + +//@} + +/** @name ACI commands available in Connected mode */ +//@{ + + +/** @brief Sets a given application latency. + * @details This function sends a @c setApplicationLatency command. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_set_app_latency(uint16_t latency, aci_app_latency_mode_t latency_mode); + +/** @brief Opens a remote pipe. + * @details This function sends an @c OpenRemotePipe command. + * @param pipe Number of the pipe to open. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_open_remote_pipe(aci_state_t *aci_stat, uint8_t pipe); + +/** @brief Closes a remote pipe. + * @details This function sends an @c CloseRemotePipe command. + * @param pipe Pipe number to close. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_close_remote_pipe(aci_state_t *aci_stat, uint8_t pipe); + +/** @brief Sends data on a given pipe. + * @details This function sends a @c SendData command with application data to + * the radio. This function memorizes credit use, and checks that + * enough credits are available. + * @param pipe Pipe number on which the data should be sent. + * @param value Pointer to the data to send. + * @param size Size of the data to send. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_send_data(uint8_t pipe, uint8_t *value, uint8_t size); + +/** @brief Requests data from a given pipe. + * @details This function sends a @c RequestData command to the radio. This + * function memorizes credit uses, and check that enough credits are available. + * After this command, the radio sends back either a @c DataReceivedEvent + * or a @c PipeErrorEvent. + * @param pipe Pipe number on which the data is requested. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_request_data(aci_state_t *aci_stat, uint8_t pipe); + +/** @brief Sends a L2CAP change connection parameters request. + * @details This function sends a @c ChangeTiming command to the radio. This command triggers a "L2CAP change connection parameters" request + * to the master. If the master rejects or accepts but doesn't change the connection parameters within + * 30 seconds, a timing event with the unchanged connection parameters is sent by the radio. + * If the request is accepted and the master changes connection parameters, a timing event with + * the new connection parameters is sent by the radio. + * If the master doesn't reply to the request within 60 seconds, the radio disconnects. + * @param minimun_cx_interval Minimum connection interval requested, in multiple of 1.25 ms. + * @param maximum_cx_interval Maximum connection interval requested, in multiple of 1.25 ms. + * @param slave_latency requested slave latency. + * @param timeout requested slave timeout, in multiple of 10 ms. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_change_timing(uint16_t minimun_cx_interval, uint16_t maximum_cx_interval, uint16_t slave_latency, uint16_t timeout); + +/** @brief Sends a L2CAP change connection parameters request with the connection predefined preffered connection parameters. + * @details This function sends a @c ChangeTiming command to the radio. This command triggers a "L2CAP change connection parameters" request + * to the master. If the master rejects or accepts but doesn't change the connection parameters within + * 30 seconds, a timing event with the unchanged connection parameters is sent by the radio. + * If the request is accepted and the master changes connection parameters, a timing event with + * the new connection parameters is sent by the radio. + * If the master doesn't reply to the request within 60 seconds, the radio disconnects. + * The timing parameters used are the Timing parameters in the GAP settings in the nRFgo Studio. + * The Timing parameters as stored as the GAP Preferred Peripheral Connection Parameters. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_change_timing_GAP_PPCP(void); + +/** @brief Sends acknowledgement message to peer. + * @details This function sends @c SendDataAck command to radio. The radio is expected + * to send either Handle Value Confirmation or Write response depending + * on whether the data is stored remotely or locally. + * @param pipe Pipe number for which the acknowledgement is to be sent. + * @return True if the ack was sent successfully. False otherwise. +*/ +bool lib_aci_send_ack(aci_state_t *aci_stat, const uint8_t pipe); + +/** @brief Sends negative acknowledgement message to peer. + * @details This function sends @c SendDataNack command to radio. The radio is expected + * to send Error Response to the peer. + * @param pipe Pipe number for which the nack is to be sent. + * @param error_code Error code to be sent in the NACk. + * @return True if the nack was sent successfully. False otherwise. +*/ +bool lib_aci_send_nack(aci_state_t *aci_stat, const uint8_t pipe, const uint8_t error_code); + +/** @brief Sends ReadDynamicData command to the host. + * @details This function sends @c ReadDynamicData command to host. The host is expected + * to send @c CommandResponse back with the dynamic data. The application is expected to + * call this function in a loop until all the dynamic data is read out from the host. + * As long as there is dynamic data to be read from the host, the command response + * for this message has its status field set to ACI_STATUS_TRANSACTION_CONTINUE (0x01). + * The application may chose to store this read out data in a non-volatile memory location + * and later chose to write it back using the function lib_aci_write_dynamic_data. + * @return True if the command was sent successfully through the ACI. False otherwise. +*/ +bool lib_aci_read_dynamic_data(void); + +/** @brief Sends WriteDynamicData command to the host. + * @details This function sends @c WriteDynamicData command to host. The host is expected + * to send @c CommandResponse with the status of this operation. As long as the status field + * in the @c CommandResponse is ACI_STATUS_TRANSACTION_CONTINUE (0x01), the hosts expects + * more dynamic data to be written. This function should ideally be called in a cycle, + * until all the stored dynamic data is sent to the host. This function should be + * called with the dynamic data obtained from the response to a @c ReadDynamicData + * (see @c lib_aci_read_dynamic_data) command. + * @param sequence_number Sequence number of the dynamic data to be sent. + * @param dynamic_data Pointer to the dynamic data. + * @param length Length of the dynamic data. + * @return True if the command was sent successfully through the ACI. False otherwise. +*/ +bool lib_aci_write_dynamic_data(uint8_t sequence_number, uint8_t* dynamic_data, uint8_t length); +//@} + +/** @name ACI commands available while connected in Bond mode */ +//@{ + +/** @brief Sends a SMP Security Request. + * @details This function send a @c BondRequest command to the radio. + * This command triggers a SMP Security Request to the master. If the + * master rejects with a pairing failed or if the bond timer expires the connection is closed. + * @return True if the transaction is successfully initiated. + */ +bool lib_aci_bond_request(void); + +/** @brief Set the key requested by the 8001. + * @details This function sends an @c SetKey command to the radio. + * @param key_rsp_type Type of key. + * @param key Pointer to the key to set. + * @param len Length of the key. + * @return True if the transaction is successfully initiated. +*/ +bool lib_aci_set_key(aci_key_type_t key_rsp_type, uint8_t *key, uint8_t len); + +//@} + + + +/** @name ACI commands available in Test mode */ +//@{ + +/** @brief Sends an echo message + * @details This function sends an @c Echo command to the radio. lib_aci + * places the Echp ACI command in the ACI command queue + * @param message_size Length of the data to send. + * @param message_data Pointer to the data to send. + * @return True if the transaction is successfully initiated. +*/ +bool lib_aci_echo_msg(uint8_t message_size, uint8_t *message_data); + +/** @brief Sends an DTM command + * @details This function sends an @c DTM command to the radio. + * @param dtm_command_msbyte Most significant byte of the DTM command. + * @param dtm_command_lsbyte Least significant byte of the DTM command. + * @return True if the transaction is successfully initiated. +*/ +bool lib_aci_dtm_command(uint8_t dtm_command_msbyte, uint8_t dtm_command_lsbyte); + +/** @brief Gets an ACI event from the ACI Event Queue + * @details This function gets an ACI event from the ACI event queue. + * The queue is updated by the SPI driver for the ACI running in the interrupt context + * @param aci_stat pointer to the state of the ACI. + * @param p_aci_data pointer to the ACI Event. The ACI Event received will be copied into this pointer. + * @return True if an ACI Event was copied to the pointer. +*/ +bool lib_aci_event_get(aci_state_t *aci_stat, hal_aci_evt_t * aci_evt); + +/** @brief Peeks an ACI event from the ACI Event Queue + * @details This function peeks at the top event in the ACI event queue. + * In polling mode, this function will query the nRF8001 for pending events, but unlike + * lib_aci_event_get() it will not dequeue the event from the local queue, but will instead + * only peek at it. + * @return True if an ACI Event was copied to the pointer. +*/ +bool lib_aci_event_peek(hal_aci_evt_t *p_aci_evt_data); + +/** @brief Flushes the events in the ACI command queues and ACI Event queue + * +*/ +void lib_aci_flush(void); + +/** @brief Return full status of the Event queue + * @details + * + */ + bool lib_aci_event_queue_full(void); + + /** @brief Return empty status of the Event queue + * @details + * + */ + bool lib_aci_event_queue_empty(void); + +/** @brief Return full status of Command queue + * @details + * + */ + bool lib_aci_command_queue_full(void); + + /** @brief Return empty status of Command queue + * @details + * + */ + bool lib_aci_command_queue_empty(void); + +//@} + +/** @} */ + +#endif /* LIB_ACI_H__ */ diff --git a/cores/nRF5/utility/lp_timer_speed.h b/cores/nRF5/utility/lp_timer_speed.h new file mode 100644 index 00000000..fb91a3fc --- /dev/null +++ b/cores/nRF5/utility/lp_timer_speed.h @@ -0,0 +1,20 @@ +#ifndef LP_TIMER_SPEED +#define LP_TIMER_SPEED +// this file sets the lp_timer speed/resolution +// uncomment the LP_TIMER_US define for lp_timers specified in us +// else if commented out, the timers are in ms +// see notes in lp_timer.h + +#define LP_TIMER_US + +// the lp_timer.h has this code +//#ifdef LP_TIMER_US +// const static uint32_t MAX_TIMEOUT = 511000000; // i.e. 511sec +// minimum timeout 156us if argument <156 // i.e. 5*31.5us if argument <156us +//#else +// const static uint32_t MAX_TIMEOUT = 4095000; // i.e. 4095sec +// minimum timeout 1220us (1.22ms) if argument <2 // i.e. 5*244us if argument <2ms +//#endif + +#endif + diff --git a/cores/nRF5/utility/nordic_common.h b/cores/nRF5/utility/nordic_common.h new file mode 100644 index 00000000..8458319d --- /dev/null +++ b/cores/nRF5/utility/nordic_common.h @@ -0,0 +1,212 @@ +/** + * Copyright (c) 2008 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @file + * @brief Common defines and macros for firmware developed by Nordic Semiconductor. + */ + +#ifndef NORDIC_COMMON_H__ +#define NORDIC_COMMON_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Check if selected module is enabled + * + * This is save function for driver enable checking. + * Correct from Lint point of view (not using default of undefined value). + * + * Usage: + * @code + #if NRF_MODULE_ENABLED(UART) + ... + #endif + * @endcode + * + * @param module The module name. + * + * @retval 1 The macro _ENABLE is defined and is non-zero. + * @retval 0 The macro _ENABLE is not defined or it equals zero. + * + * @note + * This macro intentionally does not implement second expansion level. + * The name of the module to be checked has to be given directly as a parameter. + * And given parameter would be connected with @c _ENABLED postfix directly + * without evaluating its value. + */ +//lint -e491 // Suppers warning 491 "non-standard use of 'defined' preprocessor operator" +#define NRF_MODULE_ENABLED(module) \ + ((defined(module ## _ENABLED) && (module ## _ENABLED)) ? 1 : 0) + +/** The upper 8 bits of a 32 bit value */ +//lint -emacro(572,MSB) // Suppress warning 572 "Excessive shift value" +#define MSB_32(a) (((a) & 0xFF000000) >> 24) +/** The lower 8 bits (of a 32 bit value) */ +#define LSB_32(a) ((a) & 0x000000FF) + +/** The upper 8 bits of a 16 bit value */ +//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value" +#define MSB_16(a) (((a) & 0xFF00) >> 8) +/** The lower 8 bits (of a 16 bit value) */ +#define LSB_16(a) ((a) & 0x00FF) + +/** Leaves the minimum of the two 32-bit arguments */ +/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */ +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +/** Leaves the maximum of the two 32-bit arguments */ +/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */ +#define MAX(a, b) ((a) < (b) ? (b) : (a)) + +/**@brief Concatenates two parameters. + * + * It realizes two level expansion to make it sure that all the parameters + * are actually expanded before gluing them together. + * + * @param p1 First parameter to concatenating + * @param p2 Second parameter to concatenating + * + * @return Two parameters glued together. + * They have to create correct C mnemonic in other case + * preprocessor error would be generated. + * + * @sa CONCAT_3 + */ +#define CONCAT_2(p1, p2) CONCAT_2_(p1, p2) +/** Auxiliary macro used by @ref CONCAT_2 */ +#define CONCAT_2_(p1, p2) p1##p2 + +/**@brief Concatenates three parameters. + * + * It realizes two level expansion to make it sure that all the parameters + * are actually expanded before gluing them together. + * + * @param p1 First parameter to concatenating + * @param p2 Second parameter to concatenating + * @param p3 Third parameter to concatenating + * + * @return Three parameters glued together. + * They have to create correct C mnemonic in other case + * preprocessor error would be generated. + * + * @sa CONCAT_2 + */ +#define CONCAT_3(p1, p2, p3) CONCAT_3_(p1, p2, p3) +/** Auxiliary macro used by @ref CONCAT_3 */ +#define CONCAT_3_(p1, p2, p3) p1##p2##p3 + +#define NUM_TO_STR_INTERNAL(val) #val +/** Converts numeric value to string. + */ +#define NUM_TO_STR(val) NUM_TO_STR_INTERNAL(val) + +/** Counts number of elements inside the array + */ +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +/**@brief Set a bit in the uint32 word. + * + * @param[in] W Word whose bit is being set. + * @param[in] B Bit number in the word to be set. + */ +#define SET_BIT(W,B) ((W) |= (uint32_t)(1U << (B))) + + +/**@brief Clears a bit in the uint32 word. + * + * @param[in] W Word whose bit is to be cleared. + * @param[in] B Bit number in the word to be cleared. + */ +#define CLR_BIT(W, B) ((W) &= (~((uint32_t)1 << (B)))) + + +/**@brief Checks if a bit is set. + * + * @param[in] W Word whose bit is to be checked. + * @param[in] B Bit number in the word to be checked. + * + * @retval 1 if bit is set. + * @retval 0 if bit is not set. + */ +#define IS_SET(W,B) (((W) >> (B)) & 1) + +#define BIT_0 0x01 /**< The value of bit 0 */ +#define BIT_1 0x02 /**< The value of bit 1 */ +#define BIT_2 0x04 /**< The value of bit 2 */ +#define BIT_3 0x08 /**< The value of bit 3 */ +#define BIT_4 0x10 /**< The value of bit 4 */ +#define BIT_5 0x20 /**< The value of bit 5 */ +#define BIT_6 0x40 /**< The value of bit 6 */ +#define BIT_7 0x80 /**< The value of bit 7 */ +#define BIT_8 0x0100 /**< The value of bit 8 */ +#define BIT_9 0x0200 /**< The value of bit 9 */ +#define BIT_10 0x0400 /**< The value of bit 10 */ +#define BIT_11 0x0800 /**< The value of bit 11 */ +#define BIT_12 0x1000 /**< The value of bit 12 */ +#define BIT_13 0x2000 /**< The value of bit 13 */ +#define BIT_14 0x4000 /**< The value of bit 14 */ +#define BIT_15 0x8000 /**< The value of bit 15 */ +#define BIT_16 0x00010000 /**< The value of bit 16 */ +#define BIT_17 0x00020000 /**< The value of bit 17 */ +#define BIT_18 0x00040000 /**< The value of bit 18 */ +#define BIT_19 0x00080000 /**< The value of bit 19 */ +#define BIT_20 0x00100000 /**< The value of bit 20 */ +#define BIT_21 0x00200000 /**< The value of bit 21 */ +#define BIT_22 0x00400000 /**< The value of bit 22 */ +#define BIT_23 0x00800000 /**< The value of bit 23 */ +#define BIT_24 0x01000000 /**< The value of bit 24 */ +#define BIT_25 0x02000000 /**< The value of bit 25 */ +#define BIT_26 0x04000000 /**< The value of bit 26 */ +#define BIT_27 0x08000000 /**< The value of bit 27 */ +#define BIT_28 0x10000000 /**< The value of bit 28 */ +#define BIT_29 0x20000000 /**< The value of bit 29 */ +#define BIT_30 0x40000000 /**< The value of bit 30 */ +#define BIT_31 0x80000000 /**< The value of bit 31 */ + +#define UNUSED_VARIABLE(X) ((void)(X)) +#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X) +#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X) + +#ifdef __cplusplus +} +#endif + +#endif // NORDIC_COMMON_H__ diff --git a/cores/nRF5/utility/nrf_assert.h b/cores/nRF5/utility/nrf_assert.h new file mode 100644 index 00000000..c3c2c3b9 --- /dev/null +++ b/cores/nRF5/utility/nrf_assert.h @@ -0,0 +1,131 @@ +/** + * Copyright (c) 2006 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @file + * @brief Utilities for verifying program logic + */ + +#ifndef NRF_ASSERT_H_ +#define NRF_ASSERT_H_ + +#include +#include "nrf.h" +#include "app_error.h" + +#define ASSERT(expr) + +// comment out all the code below +#define _REMOVED_CODE_ +#ifdef _REMOVED_CODE_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @brief Function for handling assertions. + * + * + * @note + * This function is called when an assertion has triggered. + * + * @note + * This function is deprecated and will be removed in future releases. + * Use app_error_fault_handler instead. + * + * + * @post + * All hardware is put into an idle non-emitting state (in particular the radio is highly + * important to switch off since the radio might be in a state that makes it send + * packets continiously while a typical final infinit ASSERT loop is executing). + * + * + * @param line_num The line number where the assertion is called + * @param file_name Pointer to the file name + */ +//lint -save -esym(14, assert_nrf_callback) +void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name); +//lint -restore + +#if (defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)) +#define NRF_ASSERT_PRESENT 1 +#else +#define NRF_ASSERT_PRESENT 0 +#endif + +//#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) + +/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */ +/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \ + +/** @brief Function for checking intended for production code. + * + * Check passes if "expr" evaluates to true. */ + +#ifdef _lint +#define ASSERT(expr) \ +if (expr) \ +{ \ +} \ +else \ +{ \ + while(1); \ +} +#else //_lint +#define ASSERT(expr) \ +if (NRF_ASSERT_PRESENT) \ +{ \ + if (expr) \ + { \ + } \ + else \ + { \ + assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__); \ + } \ +} +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_ASSERT_H_ */ + +#endif // #ifdef _REMOVED_CODE_ diff --git a/cores/nRF5/utility/nrf_clock.h b/cores/nRF5/utility/nrf_clock.h new file mode 100644 index 00000000..7534bfce --- /dev/null +++ b/cores/nRF5/utility/nrf_clock.h @@ -0,0 +1,402 @@ +/** + * Copyright (c) 2015 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_CLOCK_H__ +#define NRF_CLOCK_H__ + +#include +#include + +#include "nrf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_clock_hal Clock HAL + * @{ + * @ingroup nrf_clock + * @brief Hardware access layer for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK). + */ + +#define NRF_CLOCK_TASK_TRIGGER (1UL) +#define NRF_CLOCK_EVENT_CLEAR (0UL) + +/** + * @brief Low-frequency clock sources. + * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers. + */ +typedef enum +{ + NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */ + NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */ + NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */ +} nrf_clock_lfclk_t; + +/** + * @brief High-frequency clock sources. + */ +typedef enum +{ + NRF_CLOCK_HFCLK_LOW_ACCURACY = CLOCK_HFCLKSTAT_SRC_RC, /**< Internal 16 MHz RC oscillator. */ + NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */ +} nrf_clock_hfclk_t; + +/** + * @brief Trigger status of task LFCLKSTART/HFCLKSTART. + * @details Used by LFCLKRUN and HFCLKRUN registers. + */ +typedef enum +{ + NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */ + NRF_CLOCK_START_TASK_TRIGGERED = CLOCK_LFCLKRUN_STATUS_Triggered /**< Task LFCLKSTART/HFCLKSTART has been triggered. */ +} nrf_clock_start_task_status_t; + +/** + * @brief Interrupts. + */ +typedef enum +{ + NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */ + NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */ + NRF_CLOCK_INT_DONE_MASK = CLOCK_INTENSET_DONE_Msk, /**< Interrupt on DONE event. */ + NRF_CLOCK_INT_CTTO_MASK = CLOCK_INTENSET_CTTO_Msk /**< Interrupt on CTTO event. */ +} nrf_clock_int_mask_t; + +/** + * @brief Tasks. + * + * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running. + * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/ + NRF_CLOCK_TASK_HFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP), /**< Stop HFCLK clock source.*/ + NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/ + NRF_CLOCK_TASK_LFCLKSTOP = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP), /**< Stop LFCLK clock source.*/ + NRF_CLOCK_TASK_CAL = offsetof(NRF_CLOCK_Type, TASKS_CAL), /**< Start calibration of LFCLK RC oscillator.*/ + NRF_CLOCK_TASK_CTSTART = offsetof(NRF_CLOCK_Type, TASKS_CTSTART), /**< Start calibration timer.*/ + NRF_CLOCK_TASK_CTSTOP = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP) /**< Stop calibration timer.*/ +} nrf_clock_task_t; /*lint -restore */ + +/** + * @brief Events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/ + NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/ + NRF_CLOCK_EVENT_DONE = offsetof(NRF_CLOCK_Type, EVENTS_DONE), /**< Calibration of LFCLK RC oscillator completed.*/ + NRF_CLOCK_EVENT_CTTO = offsetof(NRF_CLOCK_Type, EVENTS_CTTO) /**< Calibration timer time-out.*/ +} nrf_clock_event_t; /*lint -restore */ + +/** + * @brief Function for enabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask); + +/** + * @brief Function for disabling a specific interrupt. + * + * @param[in] int_mask Interrupt. + */ +__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask); + +/** + * @brief Function for retrieving the state of a specific interrupt. + * + * @param[in] int_mask Interrupt. + * + * @retval true If the interrupt is enabled. + * @retval false If the interrupt is not enabled. + */ +__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask); + +/** + * @brief Function for retrieving the address of a specific task. + * @details This function can be used by the PPI module. + * + * @param[in] task Task. + * + * @return Address of the requested task register. + */ +__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task); + +/** + * @brief Function for setting a specific task. + * + * @param[in] task Task. + */ +__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task); + +/** + * @brief Function for retrieving the address of a specific event. + * @details This function can be used by the PPI module. + * + * @param[in] event Event. + * + * @return Address of the requested event register. + */ +__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event); + +/** + * @brief Function for clearing a specific event. + * + * @param[in] event Event. + */ +__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event); + +/** + * @brief Function for retrieving the state of a specific event. + * + * @param[in] event Event. + * + * @retval true If the event is set. + * @retval false If the event is not set. + */ +__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event); + +/** + * @brief Function for changing the low-frequency clock source. + * @details This function cannot be called when the low-frequency clock is running. + * + * @param[in] source New low-frequency clock source. + * + */ +__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source); + +/** + * @brief Function for retrieving the selected source for the low-frequency clock. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void); + +/** + * @brief Function for retrieving the active source of the low-frequency clock. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is the active source of the low-frequency clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void); + +/** + * @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered. + * + * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Xtal If an external 32 kHz crystal oscillator is running and generating the LFCLK clock. + * @retval NRF_CLOCK_LFCLK_Synth If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock. + */ +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void); + +/** + * @brief Function for retrieving the state of the LFCLK clock. + * + * @retval false If the LFCLK clock is not running. + * @retval true If the LFCLK clock is running. + */ +__STATIC_INLINE bool nrf_clock_lf_is_running(void); + +/** + * @brief Function for retrieving the trigger status of the task LFCLKSTART. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task LFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task LFCLKSTART has been triggered. + */ +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void); + +/** + * @brief Function for retrieving the active source of the high-frequency clock. + * + * @retval NRF_CLOCK_HFCLK_LOW_ACCURACY If the internal 16 MHz RC oscillator is the active source of the high-frequency clock. + * @retval NRF_CLOCK_HFCLK_HIGH_ACCURACY If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock. + */ +__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void); + +/** + * @brief Function for retrieving the state of the HFCLK clock. + * + * @param[in] clk_src Clock source to be checked. + * + * @retval false If the HFCLK clock is not running. + * @retval true If the HFCLK clock is running. + */ +__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src); + +/** + * @brief Function for retrieving the trigger status of the task HFCLKSTART. + * + * @retval NRF_CLOCK_START_TASK_NOT_TRIGGERED If the task HFCLKSTART has not been triggered. + * @retval NRF_CLOCK_START_TASK_TRIGGERED If the task HFCLKSTART has been triggered. + */ +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void); + +/** + * @brief Function for changing the calibration timer interval. + * + * @param[in] interval New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds). + */ +__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask) +{ + NRF_CLOCK->INTENSET = int_mask; +} + +__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask) +{ + NRF_CLOCK->INTENCLR = int_mask; +} + +__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask) +{ + return (bool)(NRF_CLOCK->INTENCLR & int_mask); +} + +__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task) +{ + return ((uint32_t )NRF_CLOCK + task); +} + +__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER; +} + +__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event) +{ + return ((uint32_t)NRF_CLOCK + event); +} + +__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR; +//#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); + (void)dummy; +//#endif +} + +__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event) +{ + return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)); +} + +__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source) +{ + NRF_CLOCK->LFCLKSRC = + (uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC & + CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT & + CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos); +} + +__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void) +{ + return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY & + CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos); +} + +__STATIC_INLINE bool nrf_clock_lf_is_running(void) +{ + return ((NRF_CLOCK->LFCLKSTAT & + CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos); +} + +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void) +{ + return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN & + CLOCK_LFCLKRUN_STATUS_Msk) >> + CLOCK_LFCLKRUN_STATUS_Pos); +} + +__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void) +{ + return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT & + CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos); +} + +__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src) +{ + return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) == + (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos)); +} + +__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void) +{ + return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN & + CLOCK_HFCLKRUN_STATUS_Msk) >> + CLOCK_HFCLKRUN_STATUS_Pos); +} + +__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval) +{ + NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + +/** + *@} + **/ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_CLOCK_H__ diff --git a/cores/nRF5/utility/nrf_drv_clock.c b/cores/nRF5/utility/nrf_drv_clock.c new file mode 100644 index 00000000..3a71109f --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_clock.c @@ -0,0 +1,599 @@ +/** + * Copyright (c) 2016 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(CLOCK) + +#include "nrf_drv_clock.h" +#include "nrf_error.h" +#include "app_util_platform.h" +#ifdef SOFTDEVICE_PRESENT +#include "softdevice_handler.h" +#include "nrf_sdm.h" +#include "nrf_soc.h" +#endif + +#define NRF_LOG_MODULE_NAME "CLOCK" + +#if CLOCK_CONFIG_LOG_ENABLED +#define NRF_LOG_LEVEL CLOCK_CONFIG_LOG_LEVEL +#define NRF_LOG_INFO_COLOR CLOCK_CONFIG_INFO_COLOR +#define NRF_LOG_DEBUG_COLOR CLOCK_CONFIG_DEBUG_COLOR +#define EVT_TO_STR(event) (event == NRF_CLOCK_EVENT_HFCLKSTARTED ? "NRF_CLOCK_EVENT_HFCLKSTARTED" : \ + (event == NRF_CLOCK_EVENT_LFCLKSTARTED ? "NRF_CLOCK_EVENT_LFCLKSTARTED" : \ + (event == NRF_CLOCK_EVENT_DONE ? "NRF_CLOCK_EVENT_DONE" : \ + (event == NRF_CLOCK_EVENT_CTTO ? "NRF_CLOCK_EVENT_CTTO" : "UNKNOWN EVENT")))) +#else //CLOCK_CONFIG_LOG_ENABLED +#define EVT_TO_STR(event) "" +#define NRF_LOG_LEVEL 0 +#endif //CLOCK_CONFIG_LOG_ENABLED +#include "nrf_log.h" +#include "nrf_log_ctrl.h" + + +/* Validate configuration */ +INTERRUPT_PRIORITY_VALIDATION(CLOCK_CONFIG_IRQ_PRIORITY); + +/*lint -save -e652 */ +#define NRF_CLOCK_LFCLK_RC CLOCK_LFCLKSRC_SRC_RC +#define NRF_CLOCK_LFCLK_Xtal CLOCK_LFCLKSRC_SRC_Xtal +#define NRF_CLOCK_LFCLK_Synth CLOCK_LFCLKSRC_SRC_Synth +/*lint -restore */ + +#if (CLOCK_CONFIG_LF_SRC == NRF_CLOCK_LFCLK_RC) && !defined(SOFTDEVICE_PRESENT) +#define CALIBRATION_SUPPORT 1 +#else +#define CALIBRATION_SUPPORT 0 +#endif +typedef enum +{ + CAL_STATE_IDLE, + CAL_STATE_CT, + CAL_STATE_HFCLK_REQ, + CAL_STATE_CAL, + CAL_STATE_ABORT, +} nrf_drv_clock_cal_state_t; + +/**@brief CLOCK control block. */ +typedef struct +{ + bool module_initialized; /*< Indicate the state of module */ + volatile bool hfclk_on; /*< High-frequency clock state. */ + volatile bool lfclk_on; /*< Low-frequency clock state. */ + volatile uint32_t hfclk_requests; /*< High-frequency clock request counter. */ + volatile nrf_drv_clock_handler_item_t * p_hf_head; + volatile uint32_t lfclk_requests; /*< Low-frequency clock request counter. */ + volatile nrf_drv_clock_handler_item_t * p_lf_head; +#if CALIBRATION_SUPPORT + nrf_drv_clock_handler_item_t cal_hfclk_started_handler_item; + nrf_drv_clock_event_handler_t cal_done_handler; + volatile nrf_drv_clock_cal_state_t cal_state; +#endif // CALIBRATION_SUPPORT +} nrf_drv_clock_cb_t; + +static nrf_drv_clock_cb_t m_clock_cb; + + +/**@brief Function for starting LFCLK. This function will return immediately without waiting for start. + */ +static void lfclk_start(void) +{ + nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED); + nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK); + nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTART); +} + +/**@brief Function for stopping LFCLK and calibration (if it was set up). + */ +static void lfclk_stop(void) +{ +#if CALIBRATION_SUPPORT + (void)nrf_drv_clock_calibration_abort(); +#endif + +#ifdef SOFTDEVICE_PRESENT + // If LFCLK is requested to stop while SD is still enabled, + // it indicates an error in the application. + // Enabling SD should increment the LFCLK request. + ASSERT(!softdevice_handler_is_enabled()); +#endif // SOFTDEVICE_PRESENT + + nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTOP); + while (nrf_clock_lf_is_running()) + {} + m_clock_cb.lfclk_on = false; +} + +static void hfclk_start(void) +{ +#ifdef SOFTDEVICE_PRESENT + if (softdevice_handler_is_enabled()) + { + (void)sd_clock_hfclk_request(); + return; + } +#endif // SOFTDEVICE_PRESENT + + nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED); + nrf_clock_int_enable(NRF_CLOCK_INT_HF_STARTED_MASK); + nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART); +} + +static void hfclk_stop(void) +{ +#ifdef SOFTDEVICE_PRESENT + if (softdevice_handler_is_enabled()) + { + (void)sd_clock_hfclk_release(); + return; + } +#endif // SOFTDEVICE_PRESENT + + nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP); + while (nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY)) + {} + m_clock_cb.hfclk_on = false; +} + +bool nrf_drv_clock_init_check(void) +{ + return m_clock_cb.module_initialized; +} + +ret_code_t nrf_drv_clock_init(void) +{ + ret_code_t err_code = NRF_SUCCESS; + if (m_clock_cb.module_initialized) + { + err_code = NRF_ERROR_MODULE_ALREADY_INITIALIZED; + } + else + { + m_clock_cb.p_hf_head = NULL; + m_clock_cb.hfclk_requests = 0; + m_clock_cb.p_lf_head = NULL; + m_clock_cb.lfclk_requests = 0; + nrf_drv_common_power_clock_irq_init(); +#ifdef SOFTDEVICE_PRESENT + if (!softdevice_handler_is_enabled()) +#endif + { + nrf_clock_lf_src_set((nrf_clock_lfclk_t)CLOCK_CONFIG_LF_SRC); + } + +#if CALIBRATION_SUPPORT + m_clock_cb.cal_state = CAL_STATE_IDLE; +#endif + + m_clock_cb.module_initialized = true; + } + + NRF_LOG_INFO("Function: %s, error code: %s.\r\n", + (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} + +void nrf_drv_clock_uninit(void) +{ + ASSERT(m_clock_cb.module_initialized); + nrf_drv_common_clock_irq_disable(); + nrf_clock_int_disable(0xFFFFFFFF); + + lfclk_stop(); + hfclk_stop(); + m_clock_cb.module_initialized = false; + NRF_LOG_INFO("Uninitialized.\r\n"); +} + +static void item_enqueue(nrf_drv_clock_handler_item_t ** p_head, + nrf_drv_clock_handler_item_t * p_item) +{ + nrf_drv_clock_handler_item_t * p_next = *p_head; + while(p_next) + { + if(p_next == p_item) + { + return; + } + p_next = p_next->p_next; + } + + p_item->p_next = (*p_head ? *p_head : NULL); + *p_head = p_item; +} + +static nrf_drv_clock_handler_item_t * item_dequeue(nrf_drv_clock_handler_item_t ** p_head) +{ + nrf_drv_clock_handler_item_t * p_item = *p_head; + if (p_item) + { + *p_head = p_item->p_next; + } + return p_item; +} + +void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item) +{ + ASSERT(m_clock_cb.module_initialized); + + if (m_clock_cb.lfclk_on) + { + if (p_handler_item) + { + p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_LFCLK_STARTED); + } + CRITICAL_REGION_ENTER(); + ++(m_clock_cb.lfclk_requests); + CRITICAL_REGION_EXIT(); + } + else + { + CRITICAL_REGION_ENTER(); + if (p_handler_item) + { + item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head, + p_handler_item); + } + if (m_clock_cb.lfclk_requests == 0) + { + lfclk_start(); + } + ++(m_clock_cb.lfclk_requests); + CRITICAL_REGION_EXIT(); + } + + ASSERT(m_clock_cb.lfclk_requests > 0); +} + +void nrf_drv_clock_lfclk_release(void) +{ + ASSERT(m_clock_cb.module_initialized); + ASSERT(m_clock_cb.lfclk_requests > 0); + + CRITICAL_REGION_ENTER(); + --(m_clock_cb.lfclk_requests); + if (m_clock_cb.lfclk_requests == 0) + { + lfclk_stop(); + } + CRITICAL_REGION_EXIT(); +} + +bool nrf_drv_clock_lfclk_is_running(void) +{ + ASSERT(m_clock_cb.module_initialized); + +#ifdef SOFTDEVICE_PRESENT + if (softdevice_handler_is_enabled()) + { + return true; + } +#endif // SOFTDEVICE_PRESENT + + return nrf_clock_lf_is_running(); +} + +void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item) +{ + ASSERT(m_clock_cb.module_initialized); + + if (m_clock_cb.hfclk_on) + { + if (p_handler_item) + { + p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_HFCLK_STARTED); + } + CRITICAL_REGION_ENTER(); + ++(m_clock_cb.hfclk_requests); + CRITICAL_REGION_EXIT(); + } + else + { + CRITICAL_REGION_ENTER(); + if (p_handler_item) + { + item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head, + p_handler_item); + } + if (m_clock_cb.hfclk_requests == 0) + { + hfclk_start(); + } + ++(m_clock_cb.hfclk_requests); + CRITICAL_REGION_EXIT(); + } + + ASSERT(m_clock_cb.hfclk_requests > 0); +} + +void nrf_drv_clock_hfclk_release(void) +{ + ASSERT(m_clock_cb.module_initialized); + ASSERT(m_clock_cb.hfclk_requests > 0); + + CRITICAL_REGION_ENTER(); + --(m_clock_cb.hfclk_requests); + if (m_clock_cb.hfclk_requests == 0) + { + hfclk_stop(); + } + CRITICAL_REGION_EXIT(); +} + +bool nrf_drv_clock_hfclk_is_running(void) +{ + ASSERT(m_clock_cb.module_initialized); + +#ifdef SOFTDEVICE_PRESENT + if (softdevice_handler_is_enabled()) + { + uint32_t is_running; + UNUSED_VARIABLE(sd_clock_hfclk_is_running(&is_running)); + return (is_running ? true : false); + } +#endif // SOFTDEVICE_PRESENT + + return nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY); +} + +#if CALIBRATION_SUPPORT +static void clock_calibration_hf_started(nrf_drv_clock_evt_type_t event) +{ + if (m_clock_cb.cal_state == CAL_STATE_ABORT) + { + nrf_drv_clock_hfclk_release(); + m_clock_cb.cal_state = CAL_STATE_IDLE; + if (m_clock_cb.cal_done_handler) + { + m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED); + } + } + else + { + nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE); + nrf_clock_int_enable(NRF_CLOCK_INT_DONE_MASK); + m_clock_cb.cal_state = CAL_STATE_CAL; + nrf_clock_task_trigger(NRF_CLOCK_TASK_CAL); + } +} +#endif // CALIBRATION_SUPPORT + +ret_code_t nrf_drv_clock_calibration_start(uint8_t interval, nrf_drv_clock_event_handler_t handler) +{ + ret_code_t err_code = NRF_SUCCESS; +#if CALIBRATION_SUPPORT + ASSERT(m_clock_cb.cal_state == CAL_STATE_IDLE); + if (m_clock_cb.lfclk_on == false) + { + err_code = NRF_ERROR_INVALID_STATE; + } + else if (m_clock_cb.cal_state == CAL_STATE_IDLE) + { + m_clock_cb.cal_done_handler = handler; + m_clock_cb.cal_hfclk_started_handler_item.event_handler = clock_calibration_hf_started; + if (interval == 0) + { + m_clock_cb.cal_state = CAL_STATE_HFCLK_REQ; + nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item); + } + else + { + m_clock_cb.cal_state = CAL_STATE_CT; + nrf_clock_cal_timer_timeout_set(interval); + nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO); + nrf_clock_int_enable(NRF_CLOCK_INT_CTTO_MASK); + nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTART); + } + } + else + { + err_code = NRF_ERROR_BUSY; + } + NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +#else + err_code = NRF_ERROR_FORBIDDEN; + NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +#endif // CALIBRATION_SUPPORT +} + +ret_code_t nrf_drv_clock_calibration_abort(void) +{ + ret_code_t err_code = NRF_SUCCESS; +#if CALIBRATION_SUPPORT + CRITICAL_REGION_ENTER(); + switch (m_clock_cb.cal_state) + { + case CAL_STATE_CT: + nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK); + nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTOP); + m_clock_cb.cal_state = CAL_STATE_IDLE; + if (m_clock_cb.cal_done_handler) + { + m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED); + } + break; + case CAL_STATE_HFCLK_REQ: + /* fall through. */ + case CAL_STATE_CAL: + m_clock_cb.cal_state = CAL_STATE_ABORT; + break; + default: + break; + } + CRITICAL_REGION_EXIT(); + + NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +#else + err_code = NRF_ERROR_FORBIDDEN; + NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +#endif // CALIBRATION_SUPPORT +} + +ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating) +{ + ret_code_t err_code = NRF_SUCCESS; +#if CALIBRATION_SUPPORT + ASSERT(m_clock_cb.module_initialized); + *p_is_calibrating = (m_clock_cb.cal_state != CAL_STATE_IDLE); + NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +#else + err_code = NRF_ERROR_FORBIDDEN; + NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +#endif // CALIBRATION_SUPPORT +} + +__STATIC_INLINE void clock_clk_started_notify(nrf_drv_clock_evt_type_t evt_type) +{ + nrf_drv_clock_handler_item_t **p_head; + if (evt_type == NRF_DRV_CLOCK_EVT_HFCLK_STARTED) + { + p_head = (nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head; + } + else + { + p_head = (nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head; + } + + while (1) + { + nrf_drv_clock_handler_item_t * p_item = item_dequeue(p_head); + if (!p_item) + { + break; + } + + p_item->event_handler(evt_type); + } +} + +#if NRF_DRV_COMMON_POWER_CLOCK_ISR +void nrf_drv_clock_onIRQ(void) +#else +void POWER_CLOCK_IRQHandler(void) +#endif +{ + if (nrf_clock_event_check(NRF_CLOCK_EVENT_HFCLKSTARTED)) + { + nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED); + NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_HFCLKSTARTED)); + nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK); + m_clock_cb.hfclk_on = true; + clock_clk_started_notify(NRF_DRV_CLOCK_EVT_HFCLK_STARTED); + } + if (nrf_clock_event_check(NRF_CLOCK_EVENT_LFCLKSTARTED)) + { + nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED); + NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_LFCLKSTARTED)); + nrf_clock_int_disable(NRF_CLOCK_INT_LF_STARTED_MASK); + m_clock_cb.lfclk_on = true; + clock_clk_started_notify(NRF_DRV_CLOCK_EVT_LFCLK_STARTED); + } +#if CALIBRATION_SUPPORT + if (nrf_clock_event_check(NRF_CLOCK_EVENT_CTTO)) + { + nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO); + NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_CTTO)); + nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK); + nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item); + } + + if (nrf_clock_event_check(NRF_CLOCK_EVENT_DONE)) + { + nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE); + NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(NRF_CLOCK_EVENT_DONE)); + nrf_clock_int_disable(NRF_CLOCK_INT_DONE_MASK); + nrf_drv_clock_hfclk_release(); + bool aborted = (m_clock_cb.cal_state == CAL_STATE_ABORT); + m_clock_cb.cal_state = CAL_STATE_IDLE; + if (m_clock_cb.cal_done_handler) + { + m_clock_cb.cal_done_handler(aborted ? + NRF_DRV_CLOCK_EVT_CAL_ABORTED : NRF_DRV_CLOCK_EVT_CAL_DONE); + } + } +#endif // CALIBRATION_SUPPORT +} + +#ifdef SOFTDEVICE_PRESENT + +void nrf_drv_clock_on_soc_event(uint32_t evt_id) +{ + if (evt_id == NRF_EVT_HFCLKSTARTED) + { + clock_clk_started_notify(NRF_DRV_CLOCK_EVT_HFCLK_STARTED); + } +} + +void nrf_drv_clock_on_sd_enable(void) +{ + CRITICAL_REGION_ENTER(); + /* Make sure that nrf_drv_clock module is initialized */ + if (!m_clock_cb.module_initialized) + { + (void)nrf_drv_clock_init(); + } + /* SD is one of the LFCLK requesters, but it will enable it by itself. */ + ++(m_clock_cb.lfclk_requests); + m_clock_cb.lfclk_on = true; + CRITICAL_REGION_EXIT(); +} + +void nrf_drv_clock_on_sd_disable(void) +{ + /* Reinit interrupts */ + ASSERT(m_clock_cb.module_initialized); + nrf_drv_common_irq_enable(POWER_CLOCK_IRQn, CLOCK_CONFIG_IRQ_PRIORITY); + + /* SD leaves LFCLK enabled - disable it if it is no longer required. */ + nrf_drv_clock_lfclk_release(); +} + +#endif // SOFTDEVICE_PRESENT + +#undef NRF_CLOCK_LFCLK_RC +#undef NRF_CLOCK_LFCLK_Xtal +#undef NRF_CLOCK_LFCLK_Synth + +#endif // NRF_MODULE_ENABLED(CLOCK) diff --git a/cores/nRF5/utility/nrf_drv_clock.h b/cores/nRF5/utility/nrf_drv_clock.h new file mode 100644 index 00000000..263500d4 --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_clock.h @@ -0,0 +1,315 @@ +/** + * Copyright (c) 2016 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_CLOCK_H__ +#define NRF_DRV_CLOCK_H__ + +#include +#include +#include "sdk_errors.h" +#include "nrf_assert.h" +#include "nrf_clock.h" +#include "sdk_config.h" +#include "nrf_drv_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * + * @addtogroup nrf_clock Clock HAL and driver + * @ingroup nrf_drivers + * @brief Clock APIs. + * @details The clock HAL provides basic APIs for accessing the registers of the clock. + * The clock driver provides APIs on a higher level. + * + * @defgroup nrf_drv_clock Clock driver + * @{ + * @ingroup nrf_clock + * @brief Driver for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK). + */ + +/** + * @brief Clock events. + */ +typedef enum +{ + NRF_DRV_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started. + NRF_DRV_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started. + NRF_DRV_CLOCK_EVT_CAL_DONE, ///< Calibration is done. + NRF_DRV_CLOCK_EVT_CAL_ABORTED, ///< Calibration has been aborted. +} nrf_drv_clock_evt_type_t; + +/** + * @brief Clock event handler. + * + * @param[in] event Event. + */ +typedef void (*nrf_drv_clock_event_handler_t)(nrf_drv_clock_evt_type_t event); + +// Forward declaration of the nrf_drv_clock_handler_item_t type. +typedef struct nrf_drv_clock_handler_item_s nrf_drv_clock_handler_item_t; + +struct nrf_drv_clock_handler_item_s +{ + nrf_drv_clock_handler_item_t * p_next; ///< A pointer to the next handler that should be called when the clock is started. + nrf_drv_clock_event_handler_t event_handler; ///< Function to be called when the clock is started. +}; + +/** + * @brief Function for checking if driver is already initialized + * + * This function is used to check whatever common POWER_CLOCK common interrupt + * should be disabled or not if @ref nrf_drv_power tries to disable the interrupt. + * + * @retval true Driver is initialized + * @retval false Driver is uninitialized + */ +bool nrf_drv_clock_init_check(void); + +/** + * @brief Function for initializing the nrf_drv_clock module. + * + * After initialization, the module is in power off state (clocks are not requested). + * + * @retval NRF_SUCCESS If the procedure was successful. + * @retval NRF_ERROR_MODULE_ALREADY_INITIALIZED If the driver was already initialized. + */ +ret_code_t nrf_drv_clock_init(void); + +/** + * @brief Function for uninitializing the clock module. + * + */ +void nrf_drv_clock_uninit(void); + +/** + * @brief Function for requesting the LFCLK. + * + * The low-frequency clock can be requested by different modules + * or contexts. The driver ensures that the clock will be started only when it is requested + * the first time. If the clock is not ready but it was already started, the handler item that is + * provided as an input parameter is added to the list of handlers that will be notified + * when the clock is started. If the clock is already enabled, user callback is called from the + * current context. + * + * The first request will start the selected LFCLK source. If an event handler is + * provided, it will be called once the LFCLK is started. If the LFCLK was already started at this + * time, the event handler will be called from the context of this function. Additionally, + * the @ref nrf_drv_clock_lfclk_is_running function can be polled to check if the clock has started. + * + * @note When a SoftDevice is enabled, the LFCLK is always running and the driver cannot control it. + * + * @note The handler item provided by the user cannot be an automatic variable. + * + * @param[in] p_handler_item A pointer to the event handler structure. + */ +void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item); + +/** + * @brief Function for releasing the LFCLK. + * + * If there are no more requests, the LFCLK source will be stopped. + * + * @note When a SoftDevice is enabled, the LFCLK is always running. + */ +void nrf_drv_clock_lfclk_release(void); + +/** + * @brief Function for checking the LFCLK state. + * + * @retval true If the LFCLK is running. + * @retval false If the LFCLK is not running. + */ +bool nrf_drv_clock_lfclk_is_running(void); + +/** + * @brief Function for requesting the high-accuracy source HFCLK. + * + * The high-accuracy source + * can be requested by different modules or contexts. The driver ensures that the high-accuracy + * clock will be started only when it is requested the first time. If the clock is not ready + * but it was already started, the handler item that is provided as an input parameter is added + * to the list of handlers that will be notified when the clock is started. + * + * If an event handler is provided, it will be called once the clock is started. If the clock was already + * started at this time, the event handler will be called from the context of this function. Additionally, + * the @ref nrf_drv_clock_hfclk_is_running function can be polled to check if the clock has started. + * + * @note If a SoftDevice is running, the clock is managed by the SoftDevice and all requests are handled by + * the SoftDevice. This function cannot be called from all interrupt priority levels in that case. + * @note The handler item provided by the user cannot be an automatic variable. + * + * @param[in] p_handler_item A pointer to the event handler structure. + */ +void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item); + +/** + * @brief Function for releasing the high-accuracy source HFCLK. + * + * If there are no more requests, the high-accuracy source will be released. + */ +void nrf_drv_clock_hfclk_release(void); + +/** + * @brief Function for checking the HFCLK state. + * + * @retval true If the HFCLK is running (for \nRFXX XTAL source). + * @retval false If the HFCLK is not running. + */ +bool nrf_drv_clock_hfclk_is_running(void); + +/** + * @brief Function for starting a single calibration process. + * + * This function can also delay the start of calibration by a user-specified value. The delay will use + * a low-power timer that is part of the CLOCK module. @ref nrf_drv_clock_is_calibrating can be called to + * check if calibration is still in progress. If a handler is provided, the user can be notified when + * calibration is completed. The ext calibration can be started from the handler context. + * + * The calibration process consists of three phases: + * - Delay (optional) + * - Requesting the high-accuracy HFCLK + * - Hardware-supported calibration + * + * @param[in] delay Time after which the calibration will be started (in 0.25 s units). + * @param[in] handler NULL or user function to be called when calibration is completed or aborted. + * + * @retval NRF_SUCCESS If the procedure was successful. + * @retval NRF_ERROR_FORBIDDEN If a SoftDevice is present or the selected LFCLK source is not an RC oscillator. + * @retval NRF_ERROR_INVALID_STATE If the low-frequency clock is off. + * @retval NRF_ERROR_BUSY If calibration is in progress. + */ +ret_code_t nrf_drv_clock_calibration_start(uint8_t delay, nrf_drv_clock_event_handler_t handler); + +/** + * @brief Function for aborting calibration. + * + * This function aborts on-going calibration. If calibration was started, it cannot be stopped. If a handler + * was provided by @ref nrf_drv_clock_calibration_start, this handler will be called once + * aborted calibration is completed. @ref nrf_drv_clock_is_calibrating can also be used to check + * if the system is calibrating. + * + * @retval NRF_SUCCESS If the procedure was successful. + * @retval NRF_ERROR_FORBIDDEN If a SoftDevice is present or the selected LFCLK source is not an RC oscillator. + */ +ret_code_t nrf_drv_clock_calibration_abort(void); + +/** + * @brief Function for checking if calibration is in progress. + * + * This function indicates that the system is + * in calibration if it is in any of the calibration process phases (see @ref nrf_drv_clock_calibration_start). + * + * @param[out] p_is_calibrating True if calibration is in progress, false if not. + * + * @retval NRF_SUCCESS If the procedure was successful. + * @retval NRF_ERROR_FORBIDDEN If a SoftDevice is present or the selected LFCLK source is not an RC oscillator. + */ +ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating); + +/**@brief Function for returning a requested task address for the clock driver module. + * + * @param[in] task One of the peripheral tasks. + * + * @return Task address. + */ +__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task); + +/**@brief Function for returning a requested event address for the clock driver module. + * + * @param[in] event One of the peripheral events. + * + * @return Event address. + */ +__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event); + + +#ifdef SOFTDEVICE_PRESENT +/** + * @brief Function called by the SoftDevice handler if an @ref nrf_soc event is received from the SoftDevice. + * + * @param[in] evt_id One of NRF_SOC_EVTS values. + */ +void nrf_drv_clock_on_soc_event(uint32_t evt_id); + +/** + * @brief Function called by the SoftDevice handler when the SoftDevice has been enabled. + * + * This function is called just after the SoftDevice has been properly enabled. + * Its main purpose is to mark that LFCLK has been requested by SD. + */ +void nrf_drv_clock_on_sd_enable(void); + +/** + * @brief Function called by the SoftDevice handler when the SoftDevice has been disabled. + * + * This function is called just after the SoftDevice has been properly disabled. + * It has two purposes: + * 1. Releases the LFCLK from the SD. + * 2. Reinitializes an interrupt after the SD releases POWER_CLOCK_IRQ. + */ +void nrf_drv_clock_on_sd_disable(void); + +#endif +/** + *@} + **/ + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION +__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task) +{ + return nrf_clock_task_address_get(task); +} + +__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event) +{ + return nrf_clock_event_address_get(event); +} +#endif //SUPPRESS_INLINE_IMPLEMENTATION + +/*lint --flb "Leave library region" */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_CLOCK_H__ diff --git a/cores/nRF5/utility/nrf_drv_common.c b/cores/nRF5/utility/nrf_drv_common.c new file mode 100644 index 00000000..c02af427 --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_common.c @@ -0,0 +1,298 @@ +/** + * Copyright (c) 2015 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#define SOFTDEVICE_PRESENT + +#include +#include "nrf_drv_common.h" +#include "nrf_assert.h" +#include "app_util_platform.h" +#include "nrf_peripherals.h" + +#if NRF_DRV_COMMON_POWER_CLOCK_ISR +#include "nrf_drv_power.h" +#include "nrf_drv_clock.h" +#endif +#ifdef SOFTDEVICE_PRESENT +#include "nrf_soc.h" +#endif + +#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + +#define NRF_LOG_MODULE_NAME "COMMON" + +#if COMMON_CONFIG_LOG_ENABLED +#define NRF_LOG_LEVEL COMMON_CONFIG_LOG_LEVEL +#define NRF_LOG_INFO_COLOR COMMON_CONFIG_INFO_COLOR +#define NRF_LOG_DEBUG_COLOR COMMON_CONFIG_DEBUG_COLOR +#else //COMMON_CONFIG_LOG_ENABLED +#define NRF_LOG_LEVEL 0 +#endif //COMMON_CONFIG_LOG_ENABLED +#include "nrf_log.h" +#include "nrf_log_ctrl.h" + +typedef struct { + nrf_drv_irq_handler_t handler; + bool acquired; +} shared_resource_t; + +// SPIM0, SPIS0, SPI0, TWIM0, TWIS0, TWI0 +#if (NRF_MODULE_ENABLED(SPI0) || NRF_MODULE_ENABLED(SPIS0) || NRF_MODULE_ENABLED(TWI0) || NRF_MODULE_ENABLED(TWIS0)) + #define SERIAL_BOX_0_IN_USE + // [this checking may need a different form in unit tests, hence macro] + #ifndef IS_SERIAL_BOX_0 + #define IS_SERIAL_BOX_0(p_per_base) (p_per_base == NRF_SPI0) + #endif + + static shared_resource_t m_serial_box_0 = { .acquired = false }; + void SPI0_TWI0_IRQHandler(void) + { + // ASSERT(m_serial_box_0.handler); + m_serial_box_0.handler(); + } +#endif // (NRF_MODULE_ENABLED(SPI0) || NRF_MODULE_ENABLED(SPIS0) || NRF_MODULE_ENABLED(TWI0) || NRF_MODULE_ENABLED(TWIS0)) + +// SPIM1, SPIS1, SPI1, TWIM1, TWIS1, TWI1 +#if (NRF_MODULE_ENABLED(SPI1) || NRF_MODULE_ENABLED(SPIS1) || NRF_MODULE_ENABLED(TWI1) || NRF_MODULE_ENABLED(TWIS1)) + #define SERIAL_BOX_1_IN_USE + // [this checking may need a different form in unit tests, hence macro] + #ifndef IS_SERIAL_BOX_1 + #define IS_SERIAL_BOX_1(p_per_base) (p_per_base == NRF_SPI1) + #endif + + static shared_resource_t m_serial_box_1 = { .acquired = false }; +#ifdef TWIM_PRESENT + void SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler(void) +#else + void SPI1_TWI1_IRQHandler(void) +#endif + { + // ASSERT(m_serial_box_1.handler); + m_serial_box_1.handler(); + } +#endif // (NRF_MODULE_ENABLED(SPI1) || NRF_MODULE_ENABLED(SPIS1) || NRF_MODULE_ENABLED(TWI1) || NRF_MODULE_ENABLED(TWIS1)) + +// SPIM2, SPIS2, SPI2 +#if (NRF_MODULE_ENABLED(SPI2) || NRF_MODULE_ENABLED(SPIS2)) + #define SERIAL_BOX_2_IN_USE + // [this checking may need a different form in unit tests, hence macro] + #ifndef IS_SERIAL_BOX_2 + #define IS_SERIAL_BOX_2(p_per_base) (p_per_base == NRF_SPI2) + #endif + + static shared_resource_t m_serial_box_2 = { .acquired = false }; + void SPIM2_SPIS2_SPI2_IRQHandler(void) + { + // ASSERT(m_serial_box_2.handler); + m_serial_box_2.handler(); + } +#endif // (NRF_MODULE_ENABLED(SPI2) || NRF_MODULE_ENABLED(SPIS2)) + +// COMP, LPCOMP +#if (NRF_MODULE_ENABLED(COMP) || NRF_MODULE_ENABLED(LPCOMP)) + #define COMP_LPCOMP_IN_USE + + #ifndef IS_COMP_LPCOMP + #define IS_COMP_LPCOMP(p_per_base) ((p_per_base) == NRF_LPCOMP) + #endif + + static shared_resource_t m_comp_lpcomp = { .acquired = false }; + void LPCOMP_IRQHandler(void) + { + // ASSERT(m_comp_lpcomp.handler); + m_comp_lpcomp.handler(); + } +#endif // (NRF_MODULE_ENABLED(COMP) || NRF_MODULE_ENABLED(LPCOMP)) + +#if defined(SERIAL_BOX_0_IN_USE) || \ + defined(SERIAL_BOX_1_IN_USE) || \ + defined(SERIAL_BOX_2_IN_USE) || \ + defined(COMP_LPCOMP_IN_USE) +static ret_code_t acquire_shared_resource(shared_resource_t * p_resource, + nrf_drv_irq_handler_t handler) +{ + ret_code_t err_code; + + bool busy = false; + + CRITICAL_REGION_ENTER(); + if (p_resource->acquired) + { + busy = true; + } + else + { + p_resource->acquired = true; + } + CRITICAL_REGION_EXIT(); + + if (busy) + { + err_code = NRF_ERROR_BUSY; + // NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; + } + + p_resource->handler = handler; + err_code = NRF_SUCCESS; + // NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} +#endif + +ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base, + nrf_drv_irq_handler_t handler) +{ +#ifdef SERIAL_BOX_0_IN_USE + if (IS_SERIAL_BOX_0(p_per_base)) + { + return acquire_shared_resource(&m_serial_box_0, handler); + } +#endif + +#ifdef SERIAL_BOX_1_IN_USE + if (IS_SERIAL_BOX_1(p_per_base)) + { + return acquire_shared_resource(&m_serial_box_1, handler); + } +#endif + +#ifdef SERIAL_BOX_2_IN_USE + if (IS_SERIAL_BOX_2(p_per_base)) + { + return acquire_shared_resource(&m_serial_box_2, handler); + } +#endif + +#ifdef COMP_LPCOMP_IN_USE + if (IS_COMP_LPCOMP(p_per_base)) + { + return acquire_shared_resource(&m_comp_lpcomp, handler); + } +#endif + ret_code_t err_code; + + err_code = NRF_ERROR_INVALID_PARAM; + // NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} + +void nrf_drv_common_per_res_release(void const * p_per_base) +{ +#ifdef SERIAL_BOX_0_IN_USE + if (IS_SERIAL_BOX_0(p_per_base)) + { + m_serial_box_0.acquired = false; + } + else +#endif + +#ifdef SERIAL_BOX_1_IN_USE + if (IS_SERIAL_BOX_1(p_per_base)) + { + m_serial_box_1.acquired = false; + } + else +#endif + +#ifdef SERIAL_BOX_2_IN_USE + if (IS_SERIAL_BOX_2(p_per_base)) + { + m_serial_box_2.acquired = false; + } + else +#endif + +#ifdef COMP_LPCOMP_IN_USE + if (IS_COMP_LPCOMP(p_per_base)) + { + m_comp_lpcomp.acquired = false; + } + else +#endif + + {} +} + +#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + +#if NRF_MODULE_ENABLED(POWER) +void nrf_drv_common_power_irq_disable(void) +{ +#if NRF_DRV_COMMON_POWER_CLOCK_ISR + if(!nrf_drv_clock_init_check()) +#endif + { + nrf_drv_common_irq_disable(POWER_CLOCK_IRQn); + } +} +#endif + +#if NRF_MODULE_ENABLED(CLOCK) +void nrf_drv_common_clock_irq_disable(void) +{ +#if NRF_DRV_COMMON_POWER_CLOCK_ISR + if(!nrf_drv_power_init_check()) +#endif + { + nrf_drv_common_irq_disable(POWER_CLOCK_IRQn); + } +} +#endif + +#if NRF_DRV_COMMON_POWER_CLOCK_ISR +void POWER_CLOCK_IRQHandler(void) +{ + extern void nrf_drv_clock_onIRQ(void); + extern void nrf_drv_power_onIRQ(void); + + nrf_drv_clock_onIRQ(); + nrf_drv_power_onIRQ(); +} +#endif // NRF_DRV_COMMON_POWER_CLOCK_ISR + + +void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority) +{ + INTERRUPT_PRIORITY_ASSERT(priority); + + NVIC_SetPriority(IRQn, priority); + NVIC_ClearPendingIRQ(IRQn); + NVIC_EnableIRQ(IRQn); +} diff --git a/cores/nRF5/utility/nrf_drv_common.h b/cores/nRF5/utility/nrf_drv_common.h new file mode 100644 index 00000000..524596fa --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_common.h @@ -0,0 +1,358 @@ +/** + Copyright (c) 2015 - 2017, Nordic Semiconductor ASA + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, + are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + + 2. Redistributions in binary form, except as embedded into a Nordic + Semiconductor ASA integrated circuit in a product or a software update for + such product, must reproduce the above copyright notice, this list of + conditions and the following disclaimer in the documentation and/or other + materials provided with the distribution. + + 3. Neither the name of Nordic Semiconductor ASA nor the names of its + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + 4. This software, with or without modification, must only be used with a + Nordic Semiconductor ASA integrated circuit. + + 5. Any software provided in binary form under this license must not be reverse + engineered, decompiled, modified and/or disassembled. + + THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + +#ifndef NRF_DRV_COMMON_H__ +#define NRF_DRV_COMMON_H__ + +#include +#include +#include "nrf.h" +#include "sdk_errors.h" +#include "sdk_common.h" +#include "nrf_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef NRF51 + #ifdef SOFTDEVICE_PRESENT + #define INTERRUPT_PRIORITY_IS_VALID(pri) (((pri) == 1) || ((pri) == 3)) + #else + #define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 4) + #endif //SOFTDEVICE_PRESENT +#else + #ifdef SOFTDEVICE_PRESENT + #define INTERRUPT_PRIORITY_IS_VALID(pri) ((((pri) > 1) && ((pri) < 4)) || (((pri) > 5) && ((pri) < 8))) + #else + #define INTERRUPT_PRIORITY_IS_VALID(pri) ((pri) < 8) + #endif //SOFTDEVICE_PRESENT +#endif //NRF52 + +#define INTERRUPT_PRIORITY_VALIDATION(pri) STATIC_ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri))) +#define INTERRUPT_PRIORITY_ASSERT(pri) ASSERT(INTERRUPT_PRIORITY_IS_VALID((pri))) + +/** + @defgroup nrf_drv_common Peripheral drivers common module + @{ + @ingroup nrf_drivers +*/ + +/** + @brief Offset of event registers in every peripheral instance. + + This is the offset where event registers start in every peripheral. +*/ +#define NRF_DRV_COMMON_EVREGS_OFFSET 0x100U + +/** + @brief The flag that is set when POWER_CLOCK ISR is implemented in common module + + This flag means that the function POWER_CLOCK_IRQHandler is implemented in + nrf_drv_common.c file. In the @c clock and @c power modules functions + nrf_drv_clock_onIRQ nrf_drv_power_onIRQ should be implemented + and they would be called from common implementation. + + None of the checking is done here. + The implementation functions in @c clock and @c power are required to handle + correctly the case when they are called without any event bit set. +*/ +#define NRF_DRV_COMMON_POWER_CLOCK_ISR (NRF_MODULE_ENABLED(CLOCK) && NRF_MODULE_ENABLED(POWER)) + +/** + @brief Driver state. +*/ +typedef enum +{ + NRF_DRV_STATE_UNINITIALIZED, /**< Uninitialized. */ + NRF_DRV_STATE_INITIALIZED, /**< Initialized but powered off. */ + NRF_DRV_STATE_POWERED_ON +} nrf_drv_state_t; + +/** + @brief Driver power state selection. +*/ +typedef enum +{ + NRF_DRV_PWR_CTRL_ON, /**< Power on request. */ + NRF_DRV_PWR_CTRL_OFF /**< Power off request. */ +} nrf_drv_pwr_ctrl_t; + +/** + @brief IRQ handler type. +*/ +typedef void (*nrf_drv_irq_handler_t)(void); + + +#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + +/** + @brief Function for acquiring shared peripheral resources associated with + the specified peripheral. + + Certain resources and registers are shared among peripherals that have + the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0). + Only one of them can be utilized at a given time. This function reserves + proper resources to be used by the specified peripheral. + If PERIPHERAL_RESOURCE_SHARING_ENABLED is set to a non-zero value, IRQ + handlers for peripherals that are sharing resources with others are + implemented by the nrf_drv_common module instead of individual drivers. + The drivers must then specify their interrupt handling routines and + register them by using this function. + + @param[in] p_per_base Requested peripheral base pointer. + @param[in] handler Interrupt handler to register. May be NULL + if interrupts are not used for the peripheral. + + @retval NRF_SUCCESS If resources were acquired successfully. + @retval NRF_ERROR_BUSY If resources were already acquired. + @retval NRF_ERROR_INVALID_PARAM If the specified peripheral is not enabled + or the peripheral does not share resources + with other peripherals. +*/ +ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base, + nrf_drv_irq_handler_t handler); + +/** + @brief Function for releasing shared resources reserved previously by + @ref nrf_drv_common_per_res_acquire() for the specified peripheral. + + @param[in] p_per_base Requested peripheral base pointer. +*/ +void nrf_drv_common_per_res_release(void const * p_per_base); + +#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + + +/** + @brief Function sets priority and enables NVIC interrupt + + @note Function checks if correct priority is used when softdevice is present + + @param[in] IRQn Interrupt id + @param[in] priority Interrupt priority +*/ +void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority); + +#if NRF_MODULE_ENABLED(POWER) +/** + @brief Disable power IRQ + + Power and clock peripheral uses the same IRQ. + This function disables POWER_CLOCK IRQ only if CLOCK driver + is uninitialized. + + @sa nrf_drv_common_power_clock_irq_init +*/ +void nrf_drv_common_power_irq_disable(void); +#endif + +#if NRF_MODULE_ENABLED(CLOCK) +/** + @brief Disable clock IRQ + + Power and clock peripheral uses the same IRQ. + This function disables POWER_CLOCK IRQ only if POWER driver + is uninitialized. + + @sa nrf_drv_common_power_clock_irq_init +*/ +void nrf_drv_common_clock_irq_disable(void); +#endif + +/** + @brief Check if interrupt is enabled + + Function that checks if selected interrupt is enabled. + + @param[in] IRQn Interrupt id + + @retval true Selected IRQ is enabled. + @retval false Selected IRQ is disabled. +*/ +__STATIC_INLINE bool nrf_drv_common_irq_enable_check(IRQn_Type IRQn); + +/** + @brief Function disables NVIC interrupt + + @param[in] IRQn Interrupt id +*/ +__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn); + +/** + @brief Convert bit position to event code + + Function for converting the bit position in INTEN register to event code + that is equivalent to the offset of the event register from the beginning + of peripheral instance. + + For example the result of this function can be casted directly to + the types like @ref nrf_twis_event_t or @ref nrf_rng_event_t + + @param bit Bit position in INTEN register + @return Event code to be casted to the right enum type or to be used in functions like + @ref nrf_rng_event_get + + @sa nrf_drv_event_to_bitpos +*/ +__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit); + +/** + @brief Convert event code to bit position + + This function can be used to get bit position in INTEN register from event code. + + @param event Event code that may be casted from enum values from types like + @ref nrf_twis_event_t or @ref nrf_rng_event_t + @return Bit position in INTEN register that corresponds to the given code. + + @sa nrf_drv_bitpos_to_event +*/ +__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event); + +/** + @brief Get interrupt number connected with given instance + + Function returns interrupt number for a given instance of any peripheral. + @param[in] pinst Pointer to peripheral registry + @return Interrupt number +*/ +__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst); + +#if NRF_MODULE_ENABLED(CLOCK) || NRF_MODULE_ENABLED(POWER) +/** + @brief Enable and setup power clock IRQ + + This function would be called from @ref nrf_drv_clock and @ref nrf_drv_power + to enable related interrupt. + This function avoids multiple interrupt configuration. + + @note + This function is aviable only if @ref nrf_drv_clock or @ref nrf_drv_power + module is enabled. + + @note + If both @ref nrf_drv_clock and @ref nrf_drv_power modules are enabled, + during the compilation the check is made that + @ref CLOCK_CONFIG_IRQ_PRIORITY equals @ref POWER_CONFIG_IRQ_PRIORITY. + + @sa nrf_drv_common_power_irq_disable + @sa nrf_drv_common_clock_irq_disable +*/ +__STATIC_INLINE void nrf_drv_common_power_clock_irq_init(void); +#endif + +/** + @brief Check if given object is in RAM + + Function for analyzing if given location is placed in RAM. + This function is used to determine if we have address that can be supported by EasyDMA. + @param[in] ptr Pointer to the object + @retval true Object is located in RAM + @retval false Object is not located in RAM +*/ +__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr); + +#ifndef SUPPRESS_INLINE_IMPLEMENTATION + +__STATIC_INLINE bool nrf_drv_common_irq_enable_check(IRQn_Type IRQn) +{ + return 0 != (NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & + (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); +} + +__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn) +{ + NVIC_DisableIRQ(IRQn); +} + +__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit) +{ + return NRF_DRV_COMMON_EVREGS_OFFSET + bit * sizeof(uint32_t); +} + +__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event) +{ + return (event - NRF_DRV_COMMON_EVREGS_OFFSET) / sizeof(uint32_t); +} + +__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst) +{ + uint8_t ret = (uint8_t)((uint32_t)pinst >> 12U); + return (IRQn_Type) ret; +} + +#if NRF_MODULE_ENABLED(CLOCK) || NRF_MODULE_ENABLED(POWER) +__STATIC_INLINE void nrf_drv_common_power_clock_irq_init(void) +{ + if (!nrf_drv_common_irq_enable_check(POWER_CLOCK_IRQn)) + { + nrf_drv_common_irq_enable( + POWER_CLOCK_IRQn, +#if NRF_DRV_COMMON_POWER_CLOCK_ISR +#if CLOCK_CONFIG_IRQ_PRIORITY != POWER_CONFIG_IRQ_PRIORITY +#error CLOCK_CONFIG_IRQ_PRIORITY and POWER_CONFIG_IRQ_PRIORITY have to be the same. +#endif + CLOCK_CONFIG_IRQ_PRIORITY +#elif NRF_MODULE_ENABLED(CLOCK) + CLOCK_CONFIG_IRQ_PRIORITY +#elif NRF_MODULE_ENABLED(POWER) + POWER_CONFIG_IRQ_PRIORITY +#endif + ); + } +} +#endif + +__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr) +{ + return ((((uintptr_t)ptr) & 0xE0000000u) == 0x20000000u); +} + +#endif // SUPPRESS_INLINE_IMPLEMENTATION + + +#ifdef __cplusplus +} +#endif + +#endif // NRF_DRV_COMMON_H__ + +/** @} */ diff --git a/cores/nRF5/utility/nrf_drv_gpiote.c b/cores/nRF5/utility/nrf_drv_gpiote.c new file mode 100644 index 00000000..3fce9c34 --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_gpiote.c @@ -0,0 +1,809 @@ +/** + * Copyright (c) 2015 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sdk_common.h" +#if NRF_MODULE_ENABLED(GPIOTE) +#include "nrf_drv_gpiote.h" +#include "nrf_drv_common.h" +#include "app_util_platform.h" +#include "nrf_assert.h" +#include "nrf_bitmask.h" +#include + +#define NRF_LOG_MODULE_NAME "GPIOTE" + +#if GPIOTE_CONFIG_LOG_ENABLED +#define NRF_LOG_LEVEL GPIOTE_CONFIG_LOG_LEVEL +#define NRF_LOG_INFO_COLOR GPIOTE_CONFIG_INFO_COLOR +#define NRF_LOG_DEBUG_COLOR GPIOTE_CONFIG_DEBUG_COLOR +#else // GPIOTE_CONFIG_LOG_ENABLED +#define NRF_LOG_LEVEL 0 +#endif // GPIOTE_CONFIG_LOG_ENABLED +#include "nrf_log.h" +#include "nrf_log_ctrl.h" + +/* Validate configuration */ +INTERRUPT_PRIORITY_VALIDATION(GPIOTE_CONFIG_IRQ_PRIORITY); + +#define FORBIDDEN_HANDLER_ADDRESS ((nrf_drv_gpiote_evt_handler_t)UINT32_MAX) +#define PIN_NOT_USED (-1) +#define PIN_USED (-2) +#define NO_CHANNELS (-1) +#define SENSE_FIELD_POS (6) +#define SENSE_FIELD_MASK (0xC0) + +/** + * @brief Macro for converting task-event index to an address of an event register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_IDX_TO_EVENT_ADDR(idx) (nrf_gpiote_events_t)((uint32_t)NRF_GPIOTE_EVENTS_IN_0 + \ + (sizeof(uint32_t) * (idx))) + +/** + * @brief Macro for converting task-event index of OUT task to an address of a task register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_OUT_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_OUT_0 + \ + (sizeof(uint32_t) * (idx))) + +#if defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__SDK_DOXYGEN__) +/** + * @brief Macro for converting task-event index of SET task to an address of a task register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_SET_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_SET_0 + \ + (sizeof(uint32_t) * (idx))) + +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) || defined(__SDK_DOXYGEN__) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__SDK_DOXYGEN__) +/** + * @brief Macro for converting task-event index of CLR task to an address of a task register. + * + * Macro utilizes the fact that registers are grouped together in ascending order. + */ +#define TE_CLR_IDX_TO_TASK_ADDR(idx) (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_CLR_0 + \ + (sizeof(uint32_t) * (idx))) + +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) || defined(__SDK_DOXYGEN__) + +/*lint -save -e661*/ +typedef struct +{ + nrf_drv_gpiote_evt_handler_t handlers[GPIOTE_CH_NUM + GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; + int8_t pin_assignments[NUMBER_OF_PINS]; + int8_t port_handlers_pins[GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS]; + nrf_drv_state_t state; +} gpiote_control_block_t; + +static gpiote_control_block_t m_cb; + +__STATIC_INLINE bool pin_in_use(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] != PIN_NOT_USED); +} + + +__STATIC_INLINE bool pin_in_use_as_non_task_out(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] == PIN_USED); +} + + +__STATIC_INLINE bool pin_in_use_by_te(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] >= 0 && m_cb.pin_assignments[pin] < + GPIOTE_CH_NUM) ? true : false; +} + + +__STATIC_INLINE bool pin_in_use_by_port(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] >= GPIOTE_CH_NUM); +} + + +__STATIC_INLINE bool pin_in_use_by_gpiote(uint32_t pin) +{ + return (m_cb.pin_assignments[pin] >= 0); +} + + +__STATIC_INLINE void pin_in_use_by_te_set(uint32_t pin, + uint32_t channel_id, + nrf_drv_gpiote_evt_handler_t handler, + bool is_channel) +{ + m_cb.pin_assignments[pin] = channel_id; + m_cb.handlers[channel_id] = handler; + if (!is_channel) + { + m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)pin; + } +} + + +__STATIC_INLINE void pin_in_use_set(uint32_t pin) +{ + m_cb.pin_assignments[pin] = PIN_USED; +} + + +__STATIC_INLINE void pin_in_use_clear(uint32_t pin) +{ + m_cb.pin_assignments[pin] = PIN_NOT_USED; +} + + +__STATIC_INLINE int8_t channel_port_get(uint32_t pin) +{ + return m_cb.pin_assignments[pin]; +} + + +__STATIC_INLINE nrf_drv_gpiote_evt_handler_t channel_handler_get(uint32_t channel) +{ + return m_cb.handlers[channel]; +} + + +static int8_t channel_port_alloc(uint32_t pin, nrf_drv_gpiote_evt_handler_t handler, bool channel) +{ + int8_t channel_id = NO_CHANNELS; + uint32_t i; + + uint32_t start_idx = channel ? 0 : GPIOTE_CH_NUM; + uint32_t end_idx = + channel ? GPIOTE_CH_NUM : (GPIOTE_CH_NUM + GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); + + // critical section + + for (i = start_idx; i < end_idx; i++) + { + if (m_cb.handlers[i] == FORBIDDEN_HANDLER_ADDRESS) + { + pin_in_use_by_te_set(pin, i, handler, channel); + channel_id = i; + break; + } + } + // critical section + return channel_id; +} + + +static void channel_free(uint8_t channel_id) +{ + m_cb.handlers[channel_id] = FORBIDDEN_HANDLER_ADDRESS; + if (channel_id >= GPIOTE_CH_NUM) + { + m_cb.port_handlers_pins[channel_id - GPIOTE_CH_NUM] = (int8_t)PIN_NOT_USED; + } +} + + +ret_code_t nrf_drv_gpiote_init(void) +{ + ret_code_t err_code; + + if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) + { + err_code = NRF_ERROR_INVALID_STATE; + NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", + (uint32_t)__func__, + (uint32_t)ERR_TO_STR(err_code)); + return err_code; + } + + uint8_t i; + + for (i = 0; i < NUMBER_OF_PINS; i++) + { + pin_in_use_clear(i); + } + + for (i = 0; i < (GPIOTE_CH_NUM + GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++) + { + channel_free(i); + } + + nrf_drv_common_irq_enable(GPIOTE_IRQn, GPIOTE_CONFIG_IRQ_PRIORITY); + nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT); + nrf_gpiote_int_enable(GPIOTE_INTENSET_PORT_Msk); + m_cb.state = NRF_DRV_STATE_INITIALIZED; + + err_code = NRF_SUCCESS; + NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, + (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} + + +bool nrf_drv_gpiote_is_init(void) +{ + return (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) ? true : false; +} + + +void nrf_drv_gpiote_uninit(void) +{ + ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); + + uint32_t i; + + for (i = 0; i < NUMBER_OF_PINS; i++) + { + if (pin_in_use_as_non_task_out(i)) + { + nrf_drv_gpiote_out_uninit(i); + } + else if ( pin_in_use_by_gpiote(i)) + { + /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on + * so it can be called on all pins used by GPIOTE. + */ + nrf_drv_gpiote_in_uninit(i); + } + } + m_cb.state = NRF_DRV_STATE_UNINITIALIZED; + NRF_LOG_INFO("Uninitialized.\r\n"); +} + + +ret_code_t nrf_drv_gpiote_out_init(nrf_drv_gpiote_pin_t pin, + nrf_drv_gpiote_out_config_t const * p_config) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED); + ASSERT(p_config); + + ret_code_t err_code = NRF_SUCCESS; + + if (pin_in_use(pin)) + { + err_code = NRF_ERROR_INVALID_STATE; + } + else + { + if (p_config->task_pin) + { + int8_t channel = channel_port_alloc(pin, NULL, true); + + if (channel != NO_CHANNELS) + { + nrf_gpiote_task_configure(channel, pin, p_config->action, p_config->init_state); + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + else + { + pin_in_use_set(pin); + } + + if (err_code == NRF_SUCCESS) + { + if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH) + { + nrf_gpio_pin_set(pin); + } + else + { + nrf_gpio_pin_clear(pin); + } + + nrf_gpio_cfg_output(pin); + } + } + + NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, + (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} + + +void nrf_drv_gpiote_out_uninit(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + + if (pin_in_use_by_te(pin)) + { + channel_free((uint8_t)channel_port_get(pin)); + nrf_gpiote_te_default(channel_port_get(pin)); + } + pin_in_use_clear(pin); + + nrf_gpio_cfg_default(pin); +} + + +void nrf_drv_gpiote_out_set(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(!pin_in_use_by_te(pin)) + + nrf_gpio_pin_set(pin); +} + + +void nrf_drv_gpiote_out_clear(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(!pin_in_use_by_te(pin)) + + nrf_gpio_pin_clear(pin); +} + + +void nrf_drv_gpiote_out_toggle(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(!pin_in_use_by_te(pin)) + + nrf_gpio_pin_toggle(pin); +} + + +void nrf_drv_gpiote_out_task_enable(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(pin_in_use_by_te(pin)) + + nrf_gpiote_task_enable(m_cb.pin_assignments[pin]); +} + + +void nrf_drv_gpiote_out_task_disable(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(pin_in_use_by_te(pin)) + + nrf_gpiote_task_disable(m_cb.pin_assignments[pin]); +} + + +uint32_t nrf_drv_gpiote_out_task_addr_get(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR(channel_port_get(pin)); + return nrf_gpiote_task_addr_get(task); +} + + +#if defined(GPIOTE_FEATURE_SET_PRESENT) +uint32_t nrf_drv_gpiote_set_task_addr_get(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR(channel_port_get(pin)); + return nrf_gpiote_task_addr_get(task); +} + + +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) +uint32_t nrf_drv_gpiote_clr_task_addr_get(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR(channel_port_get(pin)); + return nrf_gpiote_task_addr_get(task); +} + + +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) + +void nrf_drv_gpiote_out_task_force(nrf_drv_gpiote_pin_t pin, uint8_t state) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_outinit_t init_val = + state ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW; + nrf_gpiote_task_force(m_cb.pin_assignments[pin], init_val); +} + + +void nrf_drv_gpiote_out_task_trigger(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_OUT_IDX_TO_TASK_ADDR(channel_port_get(pin)); + nrf_gpiote_task_set(task); +} + + +#if defined(GPIOTE_FEATURE_SET_PRESENT) +void nrf_drv_gpiote_set_task_trigger(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_SET_IDX_TO_TASK_ADDR(channel_port_get(pin)); + nrf_gpiote_task_set(task); +} + + +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) +void nrf_drv_gpiote_clr_task_trigger(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use(pin)); + ASSERT(pin_in_use_by_te(pin)); + + nrf_gpiote_tasks_t task = TE_CLR_IDX_TO_TASK_ADDR(channel_port_get(pin)); + nrf_gpiote_task_set(task); +} + + +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) + +ret_code_t nrf_drv_gpiote_in_init(nrf_drv_gpiote_pin_t pin, + nrf_drv_gpiote_in_config_t const * p_config, + nrf_drv_gpiote_evt_handler_t evt_handler) +{ + ASSERT(pin < NUMBER_OF_PINS); + ret_code_t err_code = NRF_SUCCESS; + + /* Only one GPIOTE channel can be assigned to one physical pin. */ + if (pin_in_use_by_gpiote(pin)) + { + err_code = NRF_ERROR_INVALID_STATE; + } + else + { + int8_t channel = channel_port_alloc(pin, evt_handler, p_config->hi_accuracy); + if (channel != NO_CHANNELS) + { + if (p_config->is_watcher) + { + nrf_gpio_cfg_watcher(pin); + } + else + { + nrf_gpio_cfg_input(pin, p_config->pull); + } + + if (p_config->hi_accuracy) + { + nrf_gpiote_event_configure(channel, pin, p_config->sense); + } + else + { + m_cb.port_handlers_pins[channel - + GPIOTE_CH_NUM] |= (p_config->sense) << SENSE_FIELD_POS; + } + } + else + { + err_code = NRF_ERROR_NO_MEM; + } + } + + NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, + (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} + + +void nrf_drv_gpiote_in_event_enable(nrf_drv_gpiote_pin_t pin, bool int_enable) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_gpiote(pin)); + if (pin_in_use_by_port(pin)) + { + uint8_t pin_and_sense = + m_cb.port_handlers_pins[channel_port_get(pin) - GPIOTE_CH_NUM]; + nrf_gpiote_polarity_t polarity = + (nrf_gpiote_polarity_t)(pin_and_sense >> SENSE_FIELD_POS); + nrf_gpio_pin_sense_t sense; + if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) + { + /* read current pin state and set for next sense to oposit */ + sense = (nrf_gpio_pin_read(pin)) ? + NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH; + } + else + { + sense = (polarity == NRF_GPIOTE_POLARITY_LOTOHI) ? + NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW; + } + nrf_gpio_cfg_sense_set(pin, sense); + } + else if (pin_in_use_by_te(pin)) + { + int32_t channel = (int32_t)channel_port_get(pin); + nrf_gpiote_events_t event = TE_IDX_TO_EVENT_ADDR(channel); + + nrf_gpiote_event_enable(channel); + + nrf_gpiote_event_clear(event); + if (int_enable) + { + nrf_drv_gpiote_evt_handler_t handler = channel_handler_get(channel_port_get(pin)); + // Enable the interrupt only if event handler was provided. + if (handler) + { + nrf_gpiote_int_enable(1 << channel); + } + } + } +} + + +void nrf_drv_gpiote_in_event_disable(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_gpiote(pin)); + if (pin_in_use_by_port(pin)) + { + nrf_gpio_cfg_sense_set(pin, NRF_GPIO_PIN_NOSENSE); + } + else if (pin_in_use_by_te(pin)) + { + int32_t channel = (int32_t)channel_port_get(pin); + nrf_gpiote_event_disable(channel); + nrf_gpiote_int_disable(1 << channel); + } +} + + +void nrf_drv_gpiote_in_uninit(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_gpiote(pin)); + nrf_drv_gpiote_in_event_disable(pin); + if (pin_in_use_by_te(pin)) + { + nrf_gpiote_te_default(channel_port_get(pin)); + } + nrf_gpio_cfg_default(pin); + channel_free((uint8_t)channel_port_get(pin)); + pin_in_use_clear(pin); +} + + +bool nrf_drv_gpiote_in_is_set(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + return nrf_gpio_pin_read(pin) ? true : false; +} + + +uint32_t nrf_drv_gpiote_in_event_addr_get(nrf_drv_gpiote_pin_t pin) +{ + ASSERT(pin < NUMBER_OF_PINS); + ASSERT(pin_in_use_by_port(pin) || pin_in_use_by_te(pin)); + + nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_PORT; + + if (pin_in_use_by_te(pin)) + { + event = TE_IDX_TO_EVENT_ADDR(channel_port_get(pin)); + } + return nrf_gpiote_event_addr_get(event); +} + + +void GPIOTE_IRQHandler(void) +{ + uint32_t status = 0; + uint32_t input[GPIO_COUNT] = {0}; + + /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/ + uint32_t i; + nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_IN_0; + uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; + + for (i = 0; i < GPIOTE_CH_NUM; i++) + { + if (nrf_gpiote_event_is_set(event) && nrf_gpiote_int_is_enabled(mask)) + { + nrf_gpiote_event_clear(event); + status |= mask; + } + mask <<= 1; + /* Incrementing to next event, utilizing the fact that events are grouped together + * in ascending order. */ + event = (nrf_gpiote_events_t)((uint32_t)event + sizeof(uint32_t)); + } + + /* collect PORT status event, if event is set read pins state. Processing is postponed to the + * end of interrupt. */ + if (nrf_gpiote_event_is_set(NRF_GPIOTE_EVENTS_PORT)) + { + nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT); + status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK; + nrf_gpio_ports_read(0, GPIO_COUNT, input); + } + + /* Process pin events. */ + if (status & NRF_GPIOTE_INT_IN_MASK) + { + mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK; + + for (i = 0; i < GPIOTE_CH_NUM; i++) + { + if (mask & status) + { + nrf_drv_gpiote_pin_t pin = nrf_gpiote_event_pin_get(i); + NRF_LOG_DEBUG("Event in number: %d.\r\n", i); + nrf_gpiote_polarity_t polarity = nrf_gpiote_event_polarity_get(i); + nrf_drv_gpiote_evt_handler_t handler = channel_handler_get(i); + NRF_LOG_DEBUG("Pin: %d, polarity: %d.\r\n", pin, polarity); + if (handler) + { + handler(pin, polarity); + } + } + mask <<= 1; + } + } + + if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK) + { + /* Process port event. */ + uint32_t port_idx; + uint8_t repeat = 0; + uint32_t toggle_mask[GPIO_COUNT] = {0}; + uint32_t pins_to_check[GPIO_COUNT]; + + // Faster way of doing memset because in interrupt context. + for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + pins_to_check[port_idx] = 0xFFFFFFFF; + } + + do + { + repeat = 0; + + for (i = 0; i < GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++) + { + uint8_t pin_and_sense = m_cb.port_handlers_pins[i]; + nrf_drv_gpiote_pin_t pin = (pin_and_sense & ~SENSE_FIELD_MASK); + + if ((m_cb.port_handlers_pins[i] != PIN_NOT_USED) + && nrf_bitmask_bit_is_set(pin, pins_to_check)) + { + nrf_gpiote_polarity_t polarity = + (nrf_gpiote_polarity_t)((pin_and_sense & + SENSE_FIELD_MASK) >> SENSE_FIELD_POS); + nrf_drv_gpiote_evt_handler_t handler = + channel_handler_get(channel_port_get(pin)); + if (handler || (polarity == NRF_GPIOTE_POLARITY_TOGGLE)) + { + if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) + { + nrf_bitmask_bit_set(pin, toggle_mask); + } + nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); + uint32_t pin_state = nrf_bitmask_bit_is_set(pin, input); + if ((pin_state && (sense == NRF_GPIO_PIN_SENSE_HIGH)) || + (!pin_state && (sense == NRF_GPIO_PIN_SENSE_LOW)) ) + { + NRF_LOG_DEBUG("PORT event for pin: %d, polarity: %d.\r\n", pin, + polarity); + if (polarity == NRF_GPIOTE_POLARITY_TOGGLE) + { + nrf_gpio_pin_sense_t next_sense = + (sense == NRF_GPIO_PIN_SENSE_HIGH) ? + NRF_GPIO_PIN_SENSE_LOW : + NRF_GPIO_PIN_SENSE_HIGH; + nrf_gpio_cfg_sense_set(pin, next_sense); + ++repeat; + + } + if (handler) + { + handler(pin, polarity); + } + } + } + } + } + + if (repeat) + { + // When one of the pins in low-accuracy and toggle mode becomes active, + // it's sense mode is inverted to clear the internal SENSE signal. + // State of any other enabled low-accuracy input in toggle mode must be checked + // explicitly, because it does not trigger the interrput when SENSE signal is active. + // For more information about SENSE functionality, refer to Product Specification. + + uint32_t new_input[GPIO_COUNT]; + bool input_unchanged = true; + nrf_gpio_ports_read(0, GPIO_COUNT, new_input); + + // Faster way of doing memcmp because in interrupt context. + for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + if (new_input[port_idx] != input[port_idx]) + { + input_unchanged = false; + break; + } + } + + if (input_unchanged) + { + // No change. + repeat = 0; + } + else + { + // Faster way of doing memcpy because in interrupt context. + for (port_idx = 0; port_idx < GPIO_COUNT; port_idx++) + { + input[port_idx] = new_input[port_idx]; + pins_to_check[port_idx] = toggle_mask[port_idx]; + } + } + } + } + while (repeat); + } +} + + +/*lint -restore*/ +#endif // NRF_MODULE_ENABLED(GPIOTE) diff --git a/cores/nRF5/utility/nrf_drv_gpiote.h b/cores/nRF5/utility/nrf_drv_gpiote.h new file mode 100644 index 00000000..3570d7a5 --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_gpiote.h @@ -0,0 +1,397 @@ +/** + * Copyright (c) 2015 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + /** + As long as a SET[n], CLR[n] and OUT[n] task or an IN[n] event is configured to control a pin n, the pin's output value will only be updated by the GPIOTE module. + The pin's output value as specified in the GPIO will therefore be ignored as long as the pin is controlled by GPIOTE. + Attempting to write a pin as a normal GPIO pin will have no effect. + When the GPIOTE is disconnected from a pin, see MODE field in CONFIG[n] register, the associated pin will get the output and configuration values specified in the GPIO module. + + In order to prevent spurious interrupts from the PORT event while configuring the sources, + the user shall first disable interrupts on the PORT event (through INTENCLR.PORT), then configure the sources (PIN_CNF[n].SENSE), + clear any potential event that could have occurred during configuration (write '1' to EVENTS_PORT), and finally enable interrupts (through INTENSET.PORT). + ***/ + +#ifndef NRF_DRV_GPIOTE__ +#define NRF_DRV_GPIOTE__ + +/** + * @addtogroup nrf_gpiote GPIOTE abstraction and driver + * @ingroup nrf_drivers + * @brief GPIOTE APIs. + * @defgroup nrf_drv_gpiote GPIOTE driver + * @{ + * @ingroup nrf_gpiote + * @brief GPIOTE driver for managing input and output pins. + */ + +#include "nrf_gpiote.h" +#include "nrf_gpio.h" +#include "sdk_errors.h" +#include +#include +#include "sdk_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/**@brief Input pin configuration. */ +typedef struct +{ + nrf_gpiote_polarity_t sense; /**< Transition that triggers interrupt. */ + nrf_gpio_pin_pull_t pull; /**< Pulling mode. */ + bool is_watcher; /**< True when the input pin is tracking an output pin. */ + bool hi_accuracy;/**< True when high accuracy (IN_EVENT) is used. */ +} nrf_drv_gpiote_in_config_t; + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition. + * @details Set hi_accu to true to use IN_EVENT. */ +#define GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_LOTOHI, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition. + * @details Set hi_accu to true to use IN_EVENT. */ +#define GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_HITOLO, \ + } + +/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin. + * @details Set hi_accu to true to use IN_EVENT.*/ +#define GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu) \ + { \ + .is_watcher = false, \ + .hi_accuracy = hi_accu, \ + .pull = NRF_GPIO_PIN_NOPULL, \ + .sense = NRF_GPIOTE_POLARITY_TOGGLE, \ + } + +/**@brief Output pin configuration. */ +typedef struct +{ + nrf_gpiote_polarity_t action; /**< Configuration of the pin task. */ + nrf_gpiote_outinit_t init_state; /**< Initial state of the output pin. */ + bool task_pin; /**< True if the pin is controlled by a GPIOTE task. */ +} nrf_drv_gpiote_out_config_t; + +/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */ +#define GPIOTE_CONFIG_OUT_SIMPLE(init_high) \ + { \ + .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = false, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low. + * @details The task will clear the pin. Therefore, the pin is set initially. */ +#define GPIOTE_CONFIG_OUT_TASK_LOW \ + { \ + .init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_HITOLO, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high. + * @details The task will set the pin. Therefore, the pin is cleared initially. */ +#define GPIOTE_CONFIG_OUT_TASK_HIGH \ + { \ + .init_state = NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_LOTOHI, \ + } + +/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state. + * @details The initial pin state must be provided. */ +#define GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high) \ + { \ + .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW, \ + .task_pin = true, \ + .action = NRF_GPIOTE_POLARITY_TOGGLE, \ + } + +/** @brief Pin. */ +typedef uint32_t nrf_drv_gpiote_pin_t; + +/** + * @brief Pin event handler prototype. + * @param pin Pin that triggered this event. + * @param action Action that lead to triggering this event. + */ +typedef void (*nrf_drv_gpiote_evt_handler_t)(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action); + +/** + * @brief Function for initializing the GPIOTE module. + * + * @details Only static configuration is supported to prevent the shared + * resource being customized by the initiator. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized. + */ +ret_code_t nrf_drv_gpiote_init(void); + +/** + * @brief Function for checking if the GPIOTE module is initialized. + * + * @details The GPIOTE module is a shared module. Therefore, you should check if + * the module is already initialized and skip initialization if it is. + * + * @retval true If the module is already initialized. + * @retval false If the module is not initialized. + */ +bool nrf_drv_gpiote_is_init(void); + +/** + * @brief Function for uninitializing the GPIOTE module. + */ +void nrf_drv_gpiote_uninit(void); + +/** + * @brief Function for initializing a GPIOTE output pin. + * @details The output pin can be controlled by the CPU or by PPI. The initial + * configuration specifies which mode is used. If PPI mode is used, the driver + * attempts to allocate one of the available GPIOTE channels. If no channel is + * available, an error is returned. + * + * @param[in] pin Pin. + * @param[in] p_config Initial configuration. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. + * @retval NRF_ERROR_NO_MEM If no GPIOTE channel is available. + */ +ret_code_t nrf_drv_gpiote_out_init(nrf_drv_gpiote_pin_t pin, + nrf_drv_gpiote_out_config_t const * p_config); + +/** + * @brief Function for uninitializing a GPIOTE output pin. + * @details The driver frees the GPIOTE channel if the output pin was using one. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_uninit(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for setting a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_set(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for clearing a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_clear(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for toggling a GPIOTE output pin. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_toggle(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for enabling a GPIOTE output pin task. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_task_enable(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for disabling a GPIOTE output pin task. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_task_disable(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of OUT task. + */ +uint32_t nrf_drv_gpiote_out_task_addr_get(nrf_drv_gpiote_pin_t pin); + +#if defined(GPIOTE_FEATURE_SET_PRESENT) +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of SET task. + */ +uint32_t nrf_drv_gpiote_set_task_addr_get(nrf_drv_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_SET_PRESENT) + +#if defined(GPIOTE_FEATURE_CLR_PRESENT) +/** + * @brief Function for getting the address of a configurable GPIOTE task. + * + * @param[in] pin Pin. + * + * @return Address of CLR task. + */ +uint32_t nrf_drv_gpiote_clr_task_addr_get(nrf_drv_gpiote_pin_t pin); +#endif // defined(GPIOTE_FEATURE_CLR_PRESENT) + +/** + * @brief Function for initializing a GPIOTE input pin. + * @details The input pin can act in two ways: + * - lower accuracy but low power (high frequency clock not needed) + * - higher accuracy (high frequency clock required) + * + * The initial configuration specifies which mode is used. + * If high-accuracy mode is used, the driver attempts to allocate one + * of the available GPIOTE channels. If no channel is + * available, an error is returned. + * In low accuracy mode SENSE feature is used. In this case only one active pin + * can be detected at a time. It can be worked around by setting all of the used + * low accuracy pins to toggle mode. + * For more information about SENSE functionality, refer to Product Specification. + * + * @param[in] pin Pin. + * @param[in] p_config Initial configuration. + * @param[in] evt_handler User function to be called when the configured transition occurs. + * + * @retval NRF_SUCCESS If initialization was successful. + * @retval NRF_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used. + * @retval NRF_ERROR_NO_MEM If no GPIOTE channel is available. + */ +ret_code_t nrf_drv_gpiote_in_init(nrf_drv_gpiote_pin_t pin, + nrf_drv_gpiote_in_config_t const * p_config, + nrf_drv_gpiote_evt_handler_t evt_handler); + +/** + * @brief Function for uninitializing a GPIOTE input pin. + * @details The driver frees the GPIOTE channel if the input pin was using one. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_in_uninit(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for enabling sensing of a GPIOTE input pin. + * + * @details If the input pin is configured as high-accuracy pin, the function + * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism. + * Note that a PORT event is shared between multiple pins, therefore the + * interrupt is always enabled. + * + * @param[in] pin Pin. + * @param[in] int_enable True to enable the interrupt. Always valid for a high-accuracy pin. + */ +void nrf_drv_gpiote_in_event_enable(nrf_drv_gpiote_pin_t pin, bool int_enable); + +/** + * @brief Function for disabling a GPIOTE input pin. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_in_event_disable(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for checking if a GPIOTE input pin is set. + * + * @param[in] pin Pin. + * @retval true If the input pin is set. + * @retval false If the input pin is not set. + */ +bool nrf_drv_gpiote_in_is_set(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for getting the address of a GPIOTE input pin event. + * @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned. + * + * @param[in] pin Pin. + */ +uint32_t nrf_drv_gpiote_in_event_addr_get(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for forcing a specific state on the pin configured as task. + * + * @param[in] pin Pin. + * @param[in] state Pin state. + */ +void nrf_drv_gpiote_out_task_force(nrf_drv_gpiote_pin_t pin, uint8_t state); + +/** + * @brief Function for triggering the task OUT manually. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_out_task_trigger(nrf_drv_gpiote_pin_t pin); + +#ifdef NRF52_SERIES +/** + * @brief Function for triggering the task SET manually. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_set_task_trigger(nrf_drv_gpiote_pin_t pin); + +/** + * @brief Function for triggering the task CLR manually. + * + * @param[in] pin Pin. + */ +void nrf_drv_gpiote_clr_task_trigger(nrf_drv_gpiote_pin_t pin); +#endif + +/** + *@} + **/ + + +#ifdef __cplusplus +} +#endif + +#endif //NRF_DRV_GPIOTE__ diff --git a/cores/nRF5/utility/nrf_drv_lpcomp.c b/cores/nRF5/utility/nrf_drv_lpcomp.c new file mode 100644 index 00000000..934d9728 --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_lpcomp.c @@ -0,0 +1,213 @@ +/** + * Copyright (c) 2015 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sdk_common.h" +//#if NRF_MODULE_ENABLED(LPCOMP) +#include "nrf_drv_lpcomp.h" +#include "nrf_assert.h" +#include "nrf_error.h" +#include "nrf_soc.h" +#include "nrf_drv_common.h" +#include "app_util_platform.h" +#include +#include +#include + +#define NRF_LOG_MODULE_NAME "LPCOMP" + +#if LPCOMP_CONFIG_LOG_ENABLED +#define NRF_LOG_LEVEL LPCOMP_CONFIG_LOG_LEVEL +#define // NRF_LOG_INFO_COLOR LPCOMP_CONFIG_INFO_COLOR +#define NRF_LOG_DEBUG_COLOR LPCOMP_CONFIG_DEBUG_COLOR +#define EVT_TO_STR(event) (event == NRF_LPCOMP_EVENT_READY ? "NRF_LPCOMP_EVENT_READY" : \ + (event == NRF_LPCOMP_EVENT_DOWN ? "NRF_LPCOMP_EVENT_DOWN" : \ + (event == NRF_LPCOMP_EVENT_UP ? "NRF_LPCOMP_EVENT_UP" : \ + (event == NRF_LPCOMP_EVENT_CROSS ? "NRF_LPCOMP_EVENT_CROSS" : "UNKNOWN EVENT")))) +#else //LPCOMP_CONFIG_LOG_ENABLED +#define EVT_TO_STR(event) "" +#define NRF_LOG_LEVEL 0 +#endif //LPCOMP_CONFIG_LOG_ENABLED +//#include "nrf_log.h" +//#include "nrf_log_ctrl.h" + + +static lpcomp_events_handler_t m_lpcomp_events_handler = NULL; +static nrf_drv_state_t m_state = NRF_DRV_STATE_UNINITIALIZED; + +/******** +#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + #define IRQ_HANDLER_NAME irq_handler_for_lpcomp + #define IRQ_HANDLER static void IRQ_HANDLER_NAME(void) + + IRQ_HANDLER; +#else +*******/ + #define IRQ_HANDLER void LPCOMP_IRQHandler(void) +/******* +#endif // NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) +*****/ + +static void lpcomp_execute_handler(nrf_lpcomp_event_t event, uint32_t event_mask) +{ + if ( nrf_lpcomp_event_check(event) && nrf_lpcomp_int_enable_check(event_mask) ) + { + nrf_lpcomp_event_clear(event); + // NRF_LOG_DEBUG("Event: %s.\r\n", (uint32_t)EVT_TO_STR(event)); + + m_lpcomp_events_handler(event); + } +} + + +IRQ_HANDLER +{ + lpcomp_execute_handler(NRF_LPCOMP_EVENT_READY, LPCOMP_INTENSET_READY_Msk); + lpcomp_execute_handler(NRF_LPCOMP_EVENT_DOWN, LPCOMP_INTENSET_DOWN_Msk); + lpcomp_execute_handler(NRF_LPCOMP_EVENT_UP, LPCOMP_INTENSET_UP_Msk); + lpcomp_execute_handler(NRF_LPCOMP_EVENT_CROSS, LPCOMP_INTENSET_CROSS_Msk); +} + + +ret_code_t nrf_drv_lpcomp_init(const nrf_drv_lpcomp_config_t * p_config, + lpcomp_events_handler_t events_handler) +{ + // ASSERT(p_config); + ret_code_t err_code; + + if (m_state != NRF_DRV_STATE_UNINITIALIZED) + { // LPCOMP driver is already initialized + err_code = NRF_ERROR_INVALID_STATE; + // NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; + } + +/********* +#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + if (nrf_drv_common_per_res_acquire(NRF_LPCOMP, IRQ_HANDLER_NAME) != NRF_SUCCESS) + { + err_code = NRF_ERROR_BUSY; + // NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; + } +#endif +***********/ + nrf_lpcomp_configure(&(p_config->hal) ); + + if (events_handler) + { + m_lpcomp_events_handler = events_handler; + } + else + { + err_code = NRF_ERROR_INVALID_PARAM; + // NRF_LOG_WARNING("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; + } + + nrf_lpcomp_input_select(p_config->input); + + switch (p_config->hal.detection) + { + case NRF_LPCOMP_DETECT_UP: + nrf_lpcomp_int_enable(LPCOMP_INTENSET_UP_Msk|LPCOMP_INTENSET_READY_Msk); + break; + + case NRF_LPCOMP_DETECT_DOWN: + nrf_lpcomp_int_enable(LPCOMP_INTENSET_DOWN_Msk|LPCOMP_INTENSET_READY_Msk); + break; + + case NRF_LPCOMP_DETECT_CROSS: + nrf_lpcomp_int_enable(LPCOMP_INTENSET_CROSS_Msk|LPCOMP_INTENSET_READY_Msk); + break; + + default: + break; + } + // nrf_lpcomp_shorts_enable(NRF_LPCOMP_SHORT_READY_SAMPLE_MASK); + + nrf_drv_common_irq_enable(LPCOMP_IRQn, p_config->interrupt_priority); + + m_state = NRF_DRV_STATE_INITIALIZED; + + err_code = NRF_SUCCESS; + // NRF_LOG_INFO("Function: %s, error code: %s.\r\n", (uint32_t)__func__, (uint32_t)ERR_TO_STR(err_code)); + return err_code; +} + + +void nrf_drv_lpcomp_uninit(void) +{ + // ASSERT(m_state != NRF_DRV_STATE_UNINITIALIZED); + nrf_drv_common_irq_disable(LPCOMP_IRQn); + nrf_drv_lpcomp_disable(); +/**************** +#if NRF_MODULE_ENABLED(PERIPHERAL_RESOURCE_SHARING) + nrf_drv_common_per_res_release(NRF_LPCOMP); +#endif +***********/ + m_state = NRF_DRV_STATE_UNINITIALIZED; + m_lpcomp_events_handler = NULL; + // NRF_LOG_INFO("Uninitialized.\r\n"); +} + +void nrf_drv_lpcomp_enable(void) +{ + // ASSERT(m_state == NRF_DRV_STATE_INITIALIZED); + nrf_lpcomp_enable(); + nrf_lpcomp_task_trigger(NRF_LPCOMP_TASK_START); + m_state = NRF_DRV_STATE_POWERED_ON; + // NRF_LOG_INFO("Enabled.\r\n"); +} + +void nrf_drv_lpcomp_disable(void) +{ + // ASSERT(m_state == NRF_DRV_STATE_POWERED_ON); + nrf_lpcomp_disable(); + nrf_lpcomp_task_trigger(NRF_LPCOMP_TASK_STOP); + m_state = NRF_DRV_STATE_POWERED_ON; + // NRF_LOG_INFO("Disabled.\r\n"); +} + +void nrf_drv_lpcomp_event_handler_register(lpcomp_events_handler_t lpcomp_events_handler) +{ + m_lpcomp_events_handler = lpcomp_events_handler; +} + +//#endif //NRF_MODULE_ENABLED(LPCOMP) diff --git a/cores/nRF5/utility/nrf_drv_lpcomp.h b/cores/nRF5/utility/nrf_drv_lpcomp.h new file mode 100644 index 00000000..6b56129a --- /dev/null +++ b/cores/nRF5/utility/nrf_drv_lpcomp.h @@ -0,0 +1,154 @@ +/** + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_DRV_LPCOMP_H__ +#define NRF_DRV_LPCOMP_H__ + +#include "nrf_lpcomp.h" +#include "sdk_errors.h" +#include "nrf_drv_common.h" +#include "sdk_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @addtogroup nrf_lpcomp LPCOMP HAL and driver + * @ingroup nrf_drivers + * @brief Low Power Comparator (LPCOMP) APIs. + * @details The LPCOMP HAL provides basic APIs for accessing the registers of Low Power Comparator. + * The LPCOMP driver provides APIs on a higher level. + * + * @defgroup nrf_drv_lpcomp LPCOMP driver + * @{ + * @ingroup nrf_lpcomp + * @brief Low Power Comparator (LPCOMP) driver. + */ + +/**@brief LPCOMP event handler function type. + * @param[in] event LPCOMP event. + */ +typedef void (* lpcomp_events_handler_t)(nrf_lpcomp_event_t event); + +/**@brief LPCOMP configuration. + */ +typedef struct +{ + nrf_lpcomp_config_t hal; /**< LPCOMP HAL configuration. */ + nrf_lpcomp_input_t input; /**< Input to be monitored. */ + uint8_t interrupt_priority; /**< LPCOMP interrupt priority. */ +} nrf_drv_lpcomp_config_t; + +/** @brief LPCOMP driver default configuration including the LPCOMP HAL configuration. */ +#ifdef NRF52_SERIES +#define NRF_DRV_LPCOMP_DEFAULT_CONFIG \ + { \ + .hal = {(nrf_lpcomp_ref_t)LPCOMP_CONFIG_REFERENCE , (nrf_lpcomp_detect_t)LPCOMP_CONFIG_DETECTION, \ + (nrf_lpcomp_hysteresis_t)LPCOMP_CONFIG_HYST}, \ + .input = (nrf_lpcomp_input_t)LPCOMP_CONFIG_INPUT, \ + .interrupt_priority = LPCOMP_CONFIG_IRQ_PRIORITY \ + } +#else +#define NRF_DRV_LPCOMP_DEFAULT_CONFIG \ + { \ + .hal = {(nrf_lpcomp_ref_t)LPCOMP_CONFIG_REFERENCE , (nrf_lpcomp_detect_t)LPCOMP_CONFIG_DETECTION}, \ + .input = (nrf_lpcomp_input_t)LPCOMP_CONFIG_INPUT, \ + .interrupt_priority = LPCOMP_CONFIG_IRQ_PRIORITY \ + } +#endif + +/** + * @brief Function for initializing the LPCOMP driver. + * + * This function initializes the LPCOMP driver, but does not enable the peripheral or any interrupts. + * To start the driver, call the function nrf_drv_lpcomp_enable() after initialization. + * + * If no configuration structure is provided, the driver is initialized with the default settings. + * + * @param[in] p_config Initial configuration. If NULL, the default configuration is used. + * @param[in] events_handler Handler function. + * @retval NRF_ERROR_INVALID_PARAM If the configuration is invalid. + * @retval NRF_ERROR_INVALID_STATE If the driver has already been initialized. + */ +ret_code_t nrf_drv_lpcomp_init(const nrf_drv_lpcomp_config_t * p_config, + lpcomp_events_handler_t events_handler); + + +/** + * @brief Function for uninitializing the LCOMP driver. + * + * This function uninitializes the LPCOMP driver. The LPCOMP peripheral and + * its interrupts are disabled, and local variables are cleaned. After this call, you must + * initialize the driver again by calling nrf_drv_lpcomp_init() if you want to use it. + * + * @sa nrf_drv_lpcomp_disable() + * @sa nrf_drv_lpcomp_init() + */ +void nrf_drv_lpcomp_uninit(void); + +/**@brief Function for enabling the LPCOMP peripheral and interrupts. + * + * Before calling this function, the driver must be initialized. This function + * enables the LPCOMP peripheral and its interrupts. + * + * @sa nrf_drv_lpcomp_disable() + */ +void nrf_drv_lpcomp_enable(void); + +/**@brief Function for disabling the LPCOMP peripheral. + * + * Before calling this function, the driver must be initialized. This function disables the LPCOMP + * peripheral and its interrupts. + * + * @sa nrf_drv_lpcomp_enable() + */ +void nrf_drv_lpcomp_disable(void); + +/** + *@} + **/ + + +#ifdef __cplusplus +} +#endif + + #endif /* NRF_DRV_LPCOMP_H__ */ diff --git a/cores/nRF5/utility/nrf_lpcomp.h b/cores/nRF5/utility/nrf_lpcomp.h new file mode 100644 index 00000000..b47b08bd --- /dev/null +++ b/cores/nRF5/utility/nrf_lpcomp.h @@ -0,0 +1,430 @@ +/** + * Copyright (c) 2014 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** + * @file + * @brief LPCOMP HAL API. + */ + +#ifndef NRF_LPCOMP_H_ +#define NRF_LPCOMP_H_ + +/** + * @defgroup nrf_lpcomp_hal LPCOMP HAL + * @{ + * @ingroup nrf_lpcomp + * @brief Hardware access layer for managing the Low Power Comparator (LPCOMP). + */ + +#include "nrf.h" +#include "nrf_peripherals.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @enum nrf_lpcomp_ref_t + * @brief LPCOMP reference selection. + */ +enum LPCOMP_REF { + /** +#if (LPCOMP_REFSEL_RESOLUTION == 8) || defined(__SDK_DOXYGEN__) + NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling, // Use supply with a 1/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling, // Use supply with a 2/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling, // Use supply with a 3/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling, // Use supply with a 4/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling, // Use supply with a 5/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling, // Use supply with a 6/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling, // Use supply with a 7/8 prescaler as reference. +#elif (LPCOMP_REFSEL_RESOLUTION == 16) || defined(__SDK_DOXYGEN__) +**/ + NRF_LPCOMP_REF_SUPPLY_1_8 = LPCOMP_REFSEL_REFSEL_Ref1_8Vdd, // Use supply with a 1/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_2_8 = LPCOMP_REFSEL_REFSEL_Ref2_8Vdd, // Use supply with a 2/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_3_8 = LPCOMP_REFSEL_REFSEL_Ref3_8Vdd, // Use supply with a 3/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_4_8 = LPCOMP_REFSEL_REFSEL_Ref4_8Vdd, // Use supply with a 4/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_5_8 = LPCOMP_REFSEL_REFSEL_Ref5_8Vdd, // Use supply with a 5/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_6_8 = LPCOMP_REFSEL_REFSEL_Ref6_8Vdd, // Use supply with a 6/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_7_8 = LPCOMP_REFSEL_REFSEL_Ref7_8Vdd, // Use supply with a 7/8 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_1_16 = LPCOMP_REFSEL_REFSEL_Ref1_16Vdd, // Use supply with a 1/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_3_16 = LPCOMP_REFSEL_REFSEL_Ref3_16Vdd, // Use supply with a 3/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_5_16 = LPCOMP_REFSEL_REFSEL_Ref5_16Vdd, // Use supply with a 5/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_7_16 = LPCOMP_REFSEL_REFSEL_Ref7_16Vdd, // Use supply with a 7/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_9_16 = LPCOMP_REFSEL_REFSEL_Ref9_16Vdd, // Use supply with a 9/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_11_16 = LPCOMP_REFSEL_REFSEL_Ref11_16Vdd, // Use supply with a 11/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_13_16 = LPCOMP_REFSEL_REFSEL_Ref13_16Vdd, // Use supply with a 13/16 prescaler as reference. + NRF_LPCOMP_REF_SUPPLY_15_16 = LPCOMP_REFSEL_REFSEL_Ref15_16Vdd, // Use supply with a 15/16 prescaler as reference. +//#endif + NRF_LPCOMP_REF_EXT_REF0 = LPCOMP_REFSEL_REFSEL_ARef | + (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 << 16), // External reference 0. + NRF_LPCOMP_CONFIG_REF_EXT_REF1 = LPCOMP_REFSEL_REFSEL_ARef | + (LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 << 16), // External reference 1. +}; + +extern enum LPCOMP_REF lp_comp_ref; + typedef enum LPCOMP_REF nrf_lpcomp_ref_t; + +/** + * @enum nrf_lpcomp_input_t + * @brief LPCOMP input selection. + */ +typedef enum +{ + NRF_LPCOMP_INPUT_0 = LPCOMP_PSEL_PSEL_AnalogInput0, /**< Input 0. */ + NRF_LPCOMP_INPUT_1 = LPCOMP_PSEL_PSEL_AnalogInput1, /**< Input 1. */ + NRF_LPCOMP_INPUT_2 = LPCOMP_PSEL_PSEL_AnalogInput2, /**< Input 2. */ + NRF_LPCOMP_INPUT_3 = LPCOMP_PSEL_PSEL_AnalogInput3, /**< Input 3. */ + NRF_LPCOMP_INPUT_4 = LPCOMP_PSEL_PSEL_AnalogInput4, /**< Input 4. */ + NRF_LPCOMP_INPUT_5 = LPCOMP_PSEL_PSEL_AnalogInput5, /**< Input 5. */ + NRF_LPCOMP_INPUT_6 = LPCOMP_PSEL_PSEL_AnalogInput6, /**< Input 6. */ + NRF_LPCOMP_INPUT_7 = LPCOMP_PSEL_PSEL_AnalogInput7 /**< Input 7. */ +} nrf_lpcomp_input_t; + +/** + * @enum nrf_lpcomp_detect_t + * @brief LPCOMP detection type selection. + */ +typedef enum +{ + NRF_LPCOMP_DETECT_CROSS = LPCOMP_ANADETECT_ANADETECT_Cross, /**< Generate ANADETEC on crossing, both upwards and downwards crossing. */ + NRF_LPCOMP_DETECT_UP = LPCOMP_ANADETECT_ANADETECT_Up, /**< Generate ANADETEC on upwards crossing only. */ + NRF_LPCOMP_DETECT_DOWN = LPCOMP_ANADETECT_ANADETECT_Down /**< Generate ANADETEC on downwards crossing only. */ +} nrf_lpcomp_detect_t; + +/** + * @enum nrf_lpcomp_task_t + * @brief LPCOMP tasks. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_LPCOMP_TASK_START = offsetof(NRF_LPCOMP_Type, TASKS_START), /**< LPCOMP start sampling task. */ + NRF_LPCOMP_TASK_STOP = offsetof(NRF_LPCOMP_Type, TASKS_STOP), /**< LPCOMP stop sampling task. */ + NRF_LPCOMP_TASK_SAMPLE = offsetof(NRF_LPCOMP_Type, TASKS_SAMPLE) /**< Sample comparator value. */ +} nrf_lpcomp_task_t; /*lint -restore*/ + + +/** + * @enum nrf_lpcomp_event_t + * @brief LPCOMP events. + */ +typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */ +{ + NRF_LPCOMP_EVENT_READY = offsetof(NRF_LPCOMP_Type, EVENTS_READY), /**< LPCOMP is ready and output is valid. */ + NRF_LPCOMP_EVENT_DOWN = offsetof(NRF_LPCOMP_Type, EVENTS_DOWN), /**< Input voltage crossed the threshold going down. */ + NRF_LPCOMP_EVENT_UP = offsetof(NRF_LPCOMP_Type, EVENTS_UP), /**< Input voltage crossed the threshold going up. */ + NRF_LPCOMP_EVENT_CROSS = offsetof(NRF_LPCOMP_Type, EVENTS_CROSS) /**< Input voltage crossed the threshold in any direction. */ +} nrf_lpcomp_event_t; /*lint -restore*/ + +/** + * @enum nrf_lpcomp_short_mask_t + * @brief LPCOMP shorts masks. + */ +typedef enum +{ + NRF_LPCOMP_SHORT_CROSS_STOP_MASK = LPCOMP_SHORTS_CROSS_STOP_Msk, /*!< Short between CROSS event and STOP task. */ + NRF_LPCOMP_SHORT_UP_STOP_MASK = LPCOMP_SHORTS_UP_STOP_Msk, /*!< Short between UP event and STOP task. */ + NRF_LPCOMP_SHORT_DOWN_STOP_MASK = LPCOMP_SHORTS_DOWN_STOP_Msk, /*!< Short between DOWN event and STOP task. */ + NRF_LPCOMP_SHORT_READY_STOP_MASK = LPCOMP_SHORTS_READY_STOP_Msk, /*!< Short between READY event and STOP task. */ + NRF_LPCOMP_SHORT_READY_SAMPLE_MASK = LPCOMP_SHORTS_READY_SAMPLE_Msk /*!< Short between READY event and SAMPLE task. */ +} nrf_lpcomp_short_mask_t; + +#ifdef NRF52_SERIES +/** + * @enum nrf_lpcomp_hysteresis_t + * @brief LPCOMP hysteresis. + */ +typedef enum +{ + NRF_LPCOMP_HYST_NOHYST = LPCOMP_HYST_HYST_NoHyst, /**< Comparator hysteresis disabled. */ + NRF_LPCOMP_HYST_50mV = LPCOMP_HYST_HYST_Hyst50mV /**< Comparator hysteresis enabled (typ. 50 mV). */ +}nrf_lpcomp_hysteresis_t; +#endif // NRF52 + +/** @brief LPCOMP configuration. */ +typedef struct +{ + nrf_lpcomp_ref_t reference; /**< LPCOMP reference. */ + nrf_lpcomp_detect_t detection; /**< LPCOMP detection type. */ +#ifdef NRF52_SERIES + nrf_lpcomp_hysteresis_t hyst; /**< LPCOMP hysteresis. */ +#endif // NRF52 +} nrf_lpcomp_config_t; + +/** Default LPCOMP configuration. */ +#define NRF_LPCOMP_CONFIG_DEFAULT { NRF_LPCOMP_REF_SUPPLY_FOUR_EIGHT, NRF_LPCOMP_DETECT_DOWN } + +/** + * @brief Function for configuring LPCOMP. + * + * This function powers on LPCOMP and configures it. LPCOMP is in DISABLE state after configuration, + * so it must be enabled before using it. All shorts are inactive, events are cleared, and LPCOMP is stopped. + * + * @param[in] p_config Configuration. + */ +__STATIC_INLINE void nrf_lpcomp_configure(const nrf_lpcomp_config_t * p_config) +{ + NRF_LPCOMP->TASKS_STOP = 1; + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->REFSEL = + (p_config->reference << LPCOMP_REFSEL_REFSEL_Pos) & LPCOMP_REFSEL_REFSEL_Msk; + + //If external source is choosen extract analog reference index. + if ((p_config->reference & LPCOMP_REFSEL_REFSEL_ARef)==LPCOMP_REFSEL_REFSEL_ARef) + { + uint32_t extref = p_config->reference >> 16; + NRF_LPCOMP->EXTREFSEL = (extref << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) & LPCOMP_EXTREFSEL_EXTREFSEL_Msk; + } + + NRF_LPCOMP->ANADETECT = + (p_config->detection << LPCOMP_ANADETECT_ANADETECT_Pos) & LPCOMP_ANADETECT_ANADETECT_Msk; +#ifdef NRF52_SERIES + NRF_LPCOMP->HYST = ((p_config->hyst) << LPCOMP_HYST_HYST_Pos) & LPCOMP_HYST_HYST_Msk; +#endif + NRF_LPCOMP->SHORTS = 0; + NRF_LPCOMP->INTENCLR = LPCOMP_INTENCLR_CROSS_Msk | LPCOMP_INTENCLR_UP_Msk | + LPCOMP_INTENCLR_DOWN_Msk | LPCOMP_INTENCLR_READY_Msk; +} + + +/** + * @brief Function for selecting the LPCOMP input. + * + * This function selects the active input of LPCOMP. + * + * @param[in] input Input to be selected. + */ +__STATIC_INLINE void nrf_lpcomp_input_select(nrf_lpcomp_input_t input) +{ + uint32_t lpcomp_enable_state = NRF_LPCOMP->ENABLE; + + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->PSEL = + ((uint32_t)input << LPCOMP_PSEL_PSEL_Pos) | (NRF_LPCOMP->PSEL & ~LPCOMP_PSEL_PSEL_Msk); + NRF_LPCOMP->ENABLE = lpcomp_enable_state; +} + + +/** + * @brief Function for enabling the Low Power Comparator. + * + * This function enables LPCOMP. + * + */ +__STATIC_INLINE void nrf_lpcomp_enable(void) +{ + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Enabled << LPCOMP_ENABLE_ENABLE_Pos; + NRF_LPCOMP->EVENTS_READY = 0; + NRF_LPCOMP->EVENTS_DOWN = 0; + NRF_LPCOMP->EVENTS_UP = 0; + NRF_LPCOMP->EVENTS_CROSS = 0; +} + + +/** + * @brief Function for disabling the Low Power Comparator. + * + * This function disables LPCOMP. + * + */ +__STATIC_INLINE void nrf_lpcomp_disable(void) +{ + NRF_LPCOMP->ENABLE = LPCOMP_ENABLE_ENABLE_Disabled << LPCOMP_ENABLE_ENABLE_Pos; +} + + +/** + * @brief Function for getting the last LPCOMP compare result. + * + * @return The last compare result. If 0 then VIN+ < VIN-, if 1 then the opposite. + */ +__STATIC_INLINE uint32_t nrf_lpcomp_result_get(void) +{ + return (uint32_t)NRF_LPCOMP->RESULT; +} + + +/** + * @brief Function for enabling interrupts from LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be enabled. + * + * @sa nrf_lpcomp_int_disable() + * @sa nrf_lpcomp_int_enable_check() + */ +__STATIC_INLINE void nrf_lpcomp_int_enable(uint32_t lpcomp_int_mask) +{ + NRF_LPCOMP->INTENSET = lpcomp_int_mask; +} + + +/** + * @brief Function for disabling interrupts from LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be disabled. + * + * @sa nrf_lpcomp_int_enable() + * @sa nrf_lpcomp_int_enable_check() + */ +__STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask) +{ + NRF_LPCOMP->INTENCLR = lpcomp_int_mask; +} + + +/** + * @brief Function for getting the enabled interrupts of LPCOMP. + * + * @param[in] lpcomp_int_mask Mask of interrupts to be checked. + * + * @retval true If any of interrupts of the specified mask are enabled. + * + * @sa nrf_lpcomp_int_enable() + * @sa nrf_lpcomp_int_disable() + */ +__STATIC_INLINE bool nrf_lpcomp_int_enable_check(uint32_t lpcomp_int_mask) +{ + return (NRF_LPCOMP->INTENSET & lpcomp_int_mask); // when read this register will return the value of INTEN. +} + + +/** + * @brief Function for getting the address of a specific LPCOMP task register. + * + * @param[in] lpcomp_task LPCOMP task. + * + * @return The address of the specified LPCOMP task. + */ +__STATIC_INLINE uint32_t * nrf_lpcomp_task_address_get(nrf_lpcomp_task_t lpcomp_task) +{ + return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_task); +} + + +/** + * @brief Function for getting the address of a specific LPCOMP event register. + * + * @param[in] lpcomp_event LPCOMP event. + * + * @return The address of the specified LPCOMP event. + */ +__STATIC_INLINE uint32_t * nrf_lpcomp_event_address_get(nrf_lpcomp_event_t lpcomp_event) +{ + return (uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event); +} + + +/** + * @brief Function for setting LPCOMP shorts. + * + * @param[in] lpcomp_short_mask LPCOMP shorts by mask. + * + */ +__STATIC_INLINE void nrf_lpcomp_shorts_enable(uint32_t lpcomp_short_mask) +{ + NRF_LPCOMP->SHORTS |= lpcomp_short_mask; +} + + +/** + * @brief Function for clearing LPCOMP shorts by mask. + * + * @param[in] lpcomp_short_mask LPCOMP shorts to be cleared. + * + */ +__STATIC_INLINE void nrf_lpcomp_shorts_disable(uint32_t lpcomp_short_mask) +{ + NRF_LPCOMP->SHORTS &= ~lpcomp_short_mask; +} + + +/** + * @brief Function for setting a specific LPCOMP task. + * + * @param[in] lpcomp_task LPCOMP task to be set. + * + */ +__STATIC_INLINE void nrf_lpcomp_task_trigger(nrf_lpcomp_task_t lpcomp_task) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_task) ) = 1; +} + + +/** + * @brief Function for clearing a specific LPCOMP event. + * + * @param[in] lpcomp_event LPCOMP event to be cleared. + * + */ +__STATIC_INLINE void nrf_lpcomp_event_clear(nrf_lpcomp_event_t lpcomp_event) +{ + *( (volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event) ) = 0; +//#if __CORTEX_M == 0x04 + volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_LPCOMP + lpcomp_event)); + (void)dummy; +//#endif +} + + +/** + * @brief Function for getting the state of a specific LPCOMP event. + * + * @retval true If the specified LPCOMP event is active. + * + */ +__STATIC_INLINE bool nrf_lpcomp_event_check(nrf_lpcomp_event_t lpcomp_event) +{ + return (bool) (*(volatile uint32_t *)( (uint8_t *)NRF_LPCOMP + lpcomp_event)); +} + + +/** + *@} + **/ + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF_LPCOMP_H_ */ diff --git a/cores/nRF5/utility/nrf_peripherals.h b/cores/nRF5/utility/nrf_peripherals.h new file mode 100644 index 00000000..3e56bce0 --- /dev/null +++ b/cores/nRF5/utility/nrf_peripherals.h @@ -0,0 +1,70 @@ +/** + * Copyright (c) 2016 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NRF_PERIPHERALS_H +#define NRF_PERIPHERALS_H + +/*lint ++flb "Enter library region */ + +#ifdef NRF51422 +#include "nrf51422_peripherals.h" +#endif + +#ifdef NRF51802 +#include "nrf51802_peripherals.h" +#endif + +#ifdef NRF51822 +#include "nrf51822_peripherals.h" +#endif + +#ifdef NRF52832 +#include "nrf52832_peripherals.h" +#endif + +#ifdef NRF52840_XXAA +#include "nrf52840_peripherals.h" +#endif + + +/*lint --flb "Leave library region" */ + +#endif /* NRF_PERIPHERALS_H */ + diff --git a/cores/nRF5/utility/sdk_common.h b/cores/nRF5/utility/sdk_common.h new file mode 100644 index 00000000..cd13ab5a --- /dev/null +++ b/cores/nRF5/utility/sdk_common.h @@ -0,0 +1,78 @@ +/** + * Copyright (c) 2013 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/** @cond */ +/**@file + * + * @ingroup experimental_api + * @defgroup sdk_common SDK Common Header + * @brief All common headers needed for SDK examples will be included here so that application + * developer does not have to include headers on him/herself. + * @{ + */ + +#ifndef SDK_COMMON_H__ +#define SDK_COMMON_H__ + +#include +#include +#include +#include "sdk_config.h" +#include "nordic_common.h" +#include "compiler_abstraction.h" +#include "sdk_os.h" +#include "sdk_errors.h" +#include "app_util.h" +#include "sdk_macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @} */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_COMMON_H__ + diff --git a/cores/nRF5/utility/sdk_config.h b/cores/nRF5/utility/sdk_config.h new file mode 100644 index 00000000..a453761b --- /dev/null +++ b/cores/nRF5/utility/sdk_config.h @@ -0,0 +1,3751 @@ + +#ifndef SDK_CONFIG_H +#define SDK_CONFIG_H + +#define RTC1_ENABLED 1 +#define RTC2_ENABLED 1 + +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 +#define GPIOTE_CONFIG_IRQ_PRIORITY 3 + +/*************** +// <<< Use Configuration Wizard in Context Menu >>>\n +#ifdef USE_APP_CONFIG +#include "app_config.h" +#endif +// nRF_BLE + +//========================================================== +// BLE_ADVERTISING_ENABLED - ble_advertising - Advertising module + + +#ifndef BLE_ADVERTISING_ENABLED +#define BLE_ADVERTISING_ENABLED 0 +#endif + +// BLE_DB_DISCOVERY_ENABLED - ble_db_discovery - Database discovery module + + +#ifndef BLE_DB_DISCOVERY_ENABLED +#define BLE_DB_DISCOVERY_ENABLED 1 +#endif + +// BLE_DTM_ENABLED - ble_dtm - Module for testing RF/PHY using DTM commands + + +#ifndef BLE_DTM_ENABLED +#define BLE_DTM_ENABLED 0 +#endif + +// BLE_RACP_ENABLED - ble_racp - Record Access Control Point library + + +#ifndef BLE_RACP_ENABLED +#define BLE_RACP_ENABLED 0 +#endif + +// NRF_BLE_QWR_ENABLED - nrf_ble_qwr - Queued writes support module (prepare/execute write) + + +#ifndef NRF_BLE_QWR_ENABLED +#define NRF_BLE_QWR_ENABLED 0 +#endif + +// PEER_MANAGER_ENABLED - peer_manager - Peer Manager + + +#ifndef PEER_MANAGER_ENABLED +#define PEER_MANAGER_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_BLE_Services + +//========================================================== +// BLE_ANCS_C_ENABLED - ble_ancs_c - Apple Notification Service Client + + +#ifndef BLE_ANCS_C_ENABLED +#define BLE_ANCS_C_ENABLED 0 +#endif + +// BLE_ANS_C_ENABLED - ble_ans_c - Alert Notification Service Client + + +#ifndef BLE_ANS_C_ENABLED +#define BLE_ANS_C_ENABLED 0 +#endif + +// BLE_BAS_C_ENABLED - ble_bas_c - Battery Service Client + + +#ifndef BLE_BAS_C_ENABLED +#define BLE_BAS_C_ENABLED 0 +#endif + +// BLE_BAS_ENABLED - ble_bas - Battery Service + + +#ifndef BLE_BAS_ENABLED +#define BLE_BAS_ENABLED 0 +#endif + +// BLE_CSCS_ENABLED - ble_cscs - Cycling Speed and Cadence Service + + +#ifndef BLE_CSCS_ENABLED +#define BLE_CSCS_ENABLED 0 +#endif + +// BLE_CTS_C_ENABLED - ble_cts_c - Current Time Service Client + + +#ifndef BLE_CTS_C_ENABLED +#define BLE_CTS_C_ENABLED 0 +#endif + +// BLE_DIS_ENABLED - ble_dis - Device Information Service + + +#ifndef BLE_DIS_ENABLED +#define BLE_DIS_ENABLED 0 +#endif + +// BLE_GLS_ENABLED - ble_gls - Glucose Service + + +#ifndef BLE_GLS_ENABLED +#define BLE_GLS_ENABLED 0 +#endif + +// BLE_HIDS_ENABLED - ble_hids - Human Interface Device Service + + +#ifndef BLE_HIDS_ENABLED +#define BLE_HIDS_ENABLED 0 +#endif + +// BLE_HRS_C_ENABLED - ble_hrs_c - Heart Rate Service Client +//========================================================== +#ifndef BLE_HRS_C_ENABLED +#define BLE_HRS_C_ENABLED 0 +#endif +#if BLE_HRS_C_ENABLED +// BLE_HRS_C_RR_INTERVALS_MAX_CNT - Maximum number of RR_INTERVALS per notification to be decoded +#ifndef BLE_HRS_C_RR_INTERVALS_MAX_CNT +#define BLE_HRS_C_RR_INTERVALS_MAX_CNT 30 +#endif + +#endif //BLE_HRS_C_ENABLED +// + +// BLE_HRS_ENABLED - ble_hrs - Heart Rate Service + + +#ifndef BLE_HRS_ENABLED +#define BLE_HRS_ENABLED 0 +#endif + +// BLE_HTS_ENABLED - ble_hts - Health Thermometer Service + + +#ifndef BLE_HTS_ENABLED +#define BLE_HTS_ENABLED 0 +#endif + +// BLE_IAS_C_ENABLED - ble_ias_c - Immediate Alert Service Client + + +#ifndef BLE_IAS_C_ENABLED +#define BLE_IAS_C_ENABLED 0 +#endif + +// BLE_IAS_ENABLED - ble_ias - Immediate Alert Service + + +#ifndef BLE_IAS_ENABLED +#define BLE_IAS_ENABLED 0 +#endif + +// BLE_LBS_C_ENABLED - ble_lbs_c - Nordic LED Button Service Client + + +#ifndef BLE_LBS_C_ENABLED +#define BLE_LBS_C_ENABLED 0 +#endif + +// BLE_LBS_ENABLED - ble_lbs - LED Button Service + + +#ifndef BLE_LBS_ENABLED +#define BLE_LBS_ENABLED 0 +#endif + +// BLE_LLS_ENABLED - ble_lls - Link Loss Service + + +#ifndef BLE_LLS_ENABLED +#define BLE_LLS_ENABLED 0 +#endif + +// BLE_NUS_C_ENABLED - ble_nus_c - Nordic UART Central Service + + +#ifndef BLE_NUS_C_ENABLED +#define BLE_NUS_C_ENABLED 1 +#endif + +// BLE_NUS_ENABLED - ble_nus - Nordic UART Service + + +#ifndef BLE_NUS_ENABLED +#define BLE_NUS_ENABLED 0 +#endif + +// BLE_RSCS_C_ENABLED - ble_rscs_c - Running Speed and Cadence Client + + +#ifndef BLE_RSCS_C_ENABLED +#define BLE_RSCS_C_ENABLED 0 +#endif + +// BLE_RSCS_ENABLED - ble_rscs - Running Speed and Cadence Service + + +#ifndef BLE_RSCS_ENABLED +#define BLE_RSCS_ENABLED 0 +#endif + +// BLE_TPS_ENABLED - ble_tps - TX Power Service + + +#ifndef BLE_TPS_ENABLED +#define BLE_TPS_ENABLED 0 +#endif + +// +//========================================================== + +// nRF_Drivers + +//========================================================== +// ADC_ENABLED - nrf_drv_adc - Driver for ADC peripheral (nRF51) +//========================================================== +#ifndef ADC_ENABLED +#define ADC_ENABLED 0 +#endif +#if ADC_ENABLED +// ADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef ADC_CONFIG_IRQ_PRIORITY +#define ADC_CONFIG_IRQ_PRIORITY 3 +#endif + +// ADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef ADC_CONFIG_LOG_ENABLED +#define ADC_CONFIG_LOG_ENABLED 0 +#endif +#if ADC_CONFIG_LOG_ENABLED +// ADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef ADC_CONFIG_LOG_LEVEL +#define ADC_CONFIG_LOG_LEVEL 3 +#endif + +// ADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef ADC_CONFIG_INFO_COLOR +#define ADC_CONFIG_INFO_COLOR 0 +#endif + +// ADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef ADC_CONFIG_DEBUG_COLOR +#define ADC_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //ADC_CONFIG_LOG_ENABLED +// + +#endif //ADC_ENABLED +// + +// APP_USBD_ENABLED - app_usbd - USB Device library +//========================================================== +#ifndef APP_USBD_ENABLED +#define APP_USBD_ENABLED 0 +#endif +#if APP_USBD_ENABLED +// APP_USBD_VID - Vendor ID <0x0000-0xFFFF> + + +// Vendor ID ordered from USB IF: http://www.usb.org/developers/vendor/ + +#ifndef APP_USBD_VID +#define APP_USBD_VID 0 +#endif + +// APP_USBD_PID - Product ID <0x0000-0xFFFF> + + +// Selected Product ID + +#ifndef APP_USBD_PID +#define APP_USBD_PID 0 +#endif + +// APP_USBD_DEVICE_VER_MAJOR - Device version, major part <0-99> + + +// Device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MAJOR +#define APP_USBD_DEVICE_VER_MAJOR 1 +#endif + +// APP_USBD_DEVICE_VER_MINOR - Device version, minor part <0-99> + + +// Device version, will be converted automatically to BCD notation. Use just decimal values. + +#ifndef APP_USBD_DEVICE_VER_MINOR +#define APP_USBD_DEVICE_VER_MINOR 0 +#endif + +#endif //APP_USBD_ENABLED +// + +// CLOCK_ENABLED - nrf_drv_clock - CLOCK peripheral driver +//========================================================== +#ifndef CLOCK_ENABLED +#define CLOCK_ENABLED 1 +#endif +#if CLOCK_ENABLED +// CLOCK_CONFIG_XTAL_FREQ - HF XTAL Frequency + +// <0=> Default (64 MHz) +// <255=> Default (16 MHz) +// <0=> 32 MHz + +#ifndef CLOCK_CONFIG_XTAL_FREQ +#define CLOCK_CONFIG_XTAL_FREQ 255 +#endif + +// CLOCK_CONFIG_LF_SRC - LF Clock Source + +// <0=> RC +// <1=> XTAL +// <2=> Synth + +#ifndef CLOCK_CONFIG_LF_SRC +#define CLOCK_CONFIG_LF_SRC 1 +#endif + +// CLOCK_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef CLOCK_CONFIG_IRQ_PRIORITY +#define CLOCK_CONFIG_IRQ_PRIORITY 3 +#endif + +// CLOCK_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef CLOCK_CONFIG_LOG_ENABLED +#define CLOCK_CONFIG_LOG_ENABLED 0 +#endif +#if CLOCK_CONFIG_LOG_ENABLED +// CLOCK_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef CLOCK_CONFIG_LOG_LEVEL +#define CLOCK_CONFIG_LOG_LEVEL 3 +#endif + +// CLOCK_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_INFO_COLOR +#define CLOCK_CONFIG_INFO_COLOR 0 +#endif + +// CLOCK_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef CLOCK_CONFIG_DEBUG_COLOR +#define CLOCK_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //CLOCK_CONFIG_LOG_ENABLED +// + +#endif //CLOCK_ENABLED +// + +// COMP_ENABLED - nrf_drv_comp - COMP peripheral driver +//========================================================== +#ifndef COMP_ENABLED +#define COMP_ENABLED 0 +#endif +#if COMP_ENABLED +// COMP_CONFIG_REF - Reference voltage + +// <0=> Internal 1.2V +// <1=> Internal 1.8V +// <2=> Internal 2.4V +// <4=> VDD +// <7=> ARef + +#ifndef COMP_CONFIG_REF +#define COMP_CONFIG_REF 1 +#endif + +// COMP_CONFIG_MAIN_MODE - Main mode + +// <0=> Single ended +// <1=> Differential + +#ifndef COMP_CONFIG_MAIN_MODE +#define COMP_CONFIG_MAIN_MODE 0 +#endif + +// COMP_CONFIG_SPEED_MODE - Speed mode + +// <0=> Low power +// <1=> Normal +// <2=> High speed + +#ifndef COMP_CONFIG_SPEED_MODE +#define COMP_CONFIG_SPEED_MODE 2 +#endif + +// COMP_CONFIG_HYST - Hystheresis + +// <0=> No +// <1=> 50mV + +#ifndef COMP_CONFIG_HYST +#define COMP_CONFIG_HYST 0 +#endif + +// COMP_CONFIG_ISOURCE - Current Source + +// <0=> Off +// <1=> 2.5 uA +// <2=> 5 uA +// <3=> 10 uA + +#ifndef COMP_CONFIG_ISOURCE +#define COMP_CONFIG_ISOURCE 0 +#endif + +// COMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef COMP_CONFIG_INPUT +#define COMP_CONFIG_INPUT 0 +#endif + +// COMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef COMP_CONFIG_IRQ_PRIORITY +#define COMP_CONFIG_IRQ_PRIORITY 3 +#endif + +// COMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMP_CONFIG_LOG_ENABLED +#define COMP_CONFIG_LOG_ENABLED 0 +#endif +#if COMP_CONFIG_LOG_ENABLED +// COMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMP_CONFIG_LOG_LEVEL +#define COMP_CONFIG_LOG_LEVEL 3 +#endif + +// COMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_INFO_COLOR +#define COMP_CONFIG_INFO_COLOR 0 +#endif + +// COMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMP_CONFIG_DEBUG_COLOR +#define COMP_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //COMP_CONFIG_LOG_ENABLED +// + +#endif //COMP_ENABLED +// + +// EGU_ENABLED - nrf_drv_swi - SWI(EGU) peripheral driver +//========================================================== +#ifndef EGU_ENABLED +#define EGU_ENABLED 0 +#endif +#if EGU_ENABLED +// SWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SWI_CONFIG_LOG_ENABLED +#define SWI_CONFIG_LOG_ENABLED 0 +#endif +#if SWI_CONFIG_LOG_ENABLED +// SWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SWI_CONFIG_LOG_LEVEL +#define SWI_CONFIG_LOG_LEVEL 3 +#endif + +// SWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SWI_CONFIG_INFO_COLOR +#define SWI_CONFIG_INFO_COLOR 0 +#endif + +// SWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SWI_CONFIG_DEBUG_COLOR +#define SWI_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //SWI_CONFIG_LOG_ENABLED +// + +#endif //EGU_ENABLED +// + +// GPIOTE_ENABLED - nrf_drv_gpiote - GPIOTE peripheral driver +//========================================================== +#ifndef GPIOTE_ENABLED +#define GPIOTE_ENABLED 1 +#endif +#if GPIOTE_ENABLED +// GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS - Number of lower power input pins +#ifndef GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS +#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 4 +#endif + +// GPIOTE_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef GPIOTE_CONFIG_IRQ_PRIORITY +#define GPIOTE_CONFIG_IRQ_PRIORITY 3 +#endif + +// GPIOTE_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef GPIOTE_CONFIG_LOG_ENABLED +#define GPIOTE_CONFIG_LOG_ENABLED 0 +#endif +#if GPIOTE_CONFIG_LOG_ENABLED +// GPIOTE_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef GPIOTE_CONFIG_LOG_LEVEL +#define GPIOTE_CONFIG_LOG_LEVEL 3 +#endif + +// GPIOTE_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_INFO_COLOR +#define GPIOTE_CONFIG_INFO_COLOR 0 +#endif + +// GPIOTE_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef GPIOTE_CONFIG_DEBUG_COLOR +#define GPIOTE_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //GPIOTE_CONFIG_LOG_ENABLED +// + +#endif //GPIOTE_ENABLED +// + +// I2S_ENABLED - nrf_drv_i2s - I2S peripheral driver +//========================================================== +#ifndef I2S_ENABLED +#define I2S_ENABLED 0 +#endif +#if I2S_ENABLED +// I2S_CONFIG_SCK_PIN - SCK pin <0-31> + + +#ifndef I2S_CONFIG_SCK_PIN +#define I2S_CONFIG_SCK_PIN 31 +#endif + +// I2S_CONFIG_LRCK_PIN - LRCK pin <1-31> + + +#ifndef I2S_CONFIG_LRCK_PIN +#define I2S_CONFIG_LRCK_PIN 30 +#endif + +// I2S_CONFIG_MCK_PIN - MCK pin +#ifndef I2S_CONFIG_MCK_PIN +#define I2S_CONFIG_MCK_PIN 255 +#endif + +// I2S_CONFIG_SDOUT_PIN - SDOUT pin <0-31> + + +#ifndef I2S_CONFIG_SDOUT_PIN +#define I2S_CONFIG_SDOUT_PIN 29 +#endif + +// I2S_CONFIG_SDIN_PIN - SDIN pin <0-31> + + +#ifndef I2S_CONFIG_SDIN_PIN +#define I2S_CONFIG_SDIN_PIN 28 +#endif + +// I2S_CONFIG_MASTER - Mode + +// <0=> Master +// <1=> Slave + +#ifndef I2S_CONFIG_MASTER +#define I2S_CONFIG_MASTER 0 +#endif + +// I2S_CONFIG_FORMAT - Format + +// <0=> I2S +// <1=> Aligned + +#ifndef I2S_CONFIG_FORMAT +#define I2S_CONFIG_FORMAT 0 +#endif + +// I2S_CONFIG_ALIGN - Alignment + +// <0=> Left +// <1=> Right + +#ifndef I2S_CONFIG_ALIGN +#define I2S_CONFIG_ALIGN 0 +#endif + +// I2S_CONFIG_SWIDTH - Sample width (bits) + +// <0=> 8 +// <1=> 16 +// <2=> 24 + +#ifndef I2S_CONFIG_SWIDTH +#define I2S_CONFIG_SWIDTH 1 +#endif + +// I2S_CONFIG_CHANNELS - Channels + +// <0=> Stereo +// <1=> Left +// <2=> Right + +#ifndef I2S_CONFIG_CHANNELS +#define I2S_CONFIG_CHANNELS 1 +#endif + +// I2S_CONFIG_MCK_SETUP - MCK behavior + +// <0=> Disabled +// <2147483648=> 32MHz/2 +// <1342177280=> 32MHz/3 +// <1073741824=> 32MHz/4 +// <805306368=> 32MHz/5 +// <671088640=> 32MHz/6 +// <536870912=> 32MHz/8 +// <402653184=> 32MHz/10 +// <369098752=> 32MHz/11 +// <285212672=> 32MHz/15 +// <268435456=> 32MHz/16 +// <201326592=> 32MHz/21 +// <184549376=> 32MHz/23 +// <142606336=> 32MHz/30 +// <138412032=> 32MHz/31 +// <134217728=> 32MHz/32 +// <100663296=> 32MHz/42 +// <68157440=> 32MHz/63 +// <34340864=> 32MHz/125 + +#ifndef I2S_CONFIG_MCK_SETUP +#define I2S_CONFIG_MCK_SETUP 536870912 +#endif + +// I2S_CONFIG_RATIO - MCK/LRCK ratio + +// <0=> 32x +// <1=> 48x +// <2=> 64x +// <3=> 96x +// <4=> 128x +// <5=> 192x +// <6=> 256x +// <7=> 384x +// <8=> 512x + +#ifndef I2S_CONFIG_RATIO +#define I2S_CONFIG_RATIO 2000 +#endif + +// I2S_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef I2S_CONFIG_IRQ_PRIORITY +#define I2S_CONFIG_IRQ_PRIORITY 3 +#endif + +// I2S_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef I2S_CONFIG_LOG_ENABLED +#define I2S_CONFIG_LOG_ENABLED 0 +#endif +#if I2S_CONFIG_LOG_ENABLED +// I2S_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef I2S_CONFIG_LOG_LEVEL +#define I2S_CONFIG_LOG_LEVEL 3 +#endif + +// I2S_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_INFO_COLOR +#define I2S_CONFIG_INFO_COLOR 0 +#endif + +// I2S_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef I2S_CONFIG_DEBUG_COLOR +#define I2S_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //I2S_CONFIG_LOG_ENABLED +// + +#endif //I2S_ENABLED +// + +// LPCOMP_ENABLED - nrf_drv_lpcomp - LPCOMP peripheral driver +//========================================================== +#ifndef LPCOMP_ENABLED +#define LPCOMP_ENABLED 0 +#endif +#if LPCOMP_ENABLED +// LPCOMP_CONFIG_REFERENCE - Reference voltage + +// <0=> Supply 1/8 +// <1=> Supply 2/8 +// <2=> Supply 3/8 +// <3=> Supply 4/8 +// <4=> Supply 5/8 +// <5=> Supply 6/8 +// <6=> Supply 7/8 +// <8=> Supply 1/16 (nRF52) +// <9=> Supply 3/16 (nRF52) +// <10=> Supply 5/16 (nRF52) +// <11=> Supply 7/16 (nRF52) +// <12=> Supply 9/16 (nRF52) +// <13=> Supply 11/16 (nRF52) +// <14=> Supply 13/16 (nRF52) +// <15=> Supply 15/16 (nRF52) +// <7=> External Ref 0 +// <65543=> External Ref 1 + +#ifndef LPCOMP_CONFIG_REFERENCE +#define LPCOMP_CONFIG_REFERENCE 3 +#endif + +// LPCOMP_CONFIG_DETECTION - Detection + +// <0=> Crossing +// <1=> Up +// <2=> Down + +#ifndef LPCOMP_CONFIG_DETECTION +#define LPCOMP_CONFIG_DETECTION 2 +#endif + +// LPCOMP_CONFIG_INPUT - Analog input + +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef LPCOMP_CONFIG_INPUT +#define LPCOMP_CONFIG_INPUT 0 +#endif + +// LPCOMP_CONFIG_HYST - Hysteresis + + +#ifndef LPCOMP_CONFIG_HYST +#define LPCOMP_CONFIG_HYST 0 +#endif + +// LPCOMP_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef LPCOMP_CONFIG_IRQ_PRIORITY +#define LPCOMP_CONFIG_IRQ_PRIORITY 3 +#endif + +// LPCOMP_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef LPCOMP_CONFIG_LOG_ENABLED +#define LPCOMP_CONFIG_LOG_ENABLED 0 +#endif +#if LPCOMP_CONFIG_LOG_ENABLED +// LPCOMP_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef LPCOMP_CONFIG_LOG_LEVEL +#define LPCOMP_CONFIG_LOG_LEVEL 3 +#endif + +// LPCOMP_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_INFO_COLOR +#define LPCOMP_CONFIG_INFO_COLOR 0 +#endif + +// LPCOMP_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef LPCOMP_CONFIG_DEBUG_COLOR +#define LPCOMP_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //LPCOMP_CONFIG_LOG_ENABLED +// + +#endif //LPCOMP_ENABLED +// + +// PDM_ENABLED - nrf_drv_pdm - PDM peripheral driver +//========================================================== +#ifndef PDM_ENABLED +#define PDM_ENABLED 0 +#endif +#if PDM_ENABLED +// PDM_CONFIG_MODE - Mode + +// <0=> Stereo +// <1=> Mono + +#ifndef PDM_CONFIG_MODE +#define PDM_CONFIG_MODE 1 +#endif + +// PDM_CONFIG_EDGE - Edge + +// <0=> Left falling +// <1=> Left rising + +#ifndef PDM_CONFIG_EDGE +#define PDM_CONFIG_EDGE 0 +#endif + +// PDM_CONFIG_CLOCK_FREQ - Clock frequency + +// <134217728=> 1000k +// <138412032=> 1032k (default) +// <142606336=> 1067k + +#ifndef PDM_CONFIG_CLOCK_FREQ +#define PDM_CONFIG_CLOCK_FREQ 138412032 +#endif + +// PDM_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef PDM_CONFIG_IRQ_PRIORITY +#define PDM_CONFIG_IRQ_PRIORITY 3 +#endif + +// PDM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PDM_CONFIG_LOG_ENABLED +#define PDM_CONFIG_LOG_ENABLED 0 +#endif +#if PDM_CONFIG_LOG_ENABLED +// PDM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PDM_CONFIG_LOG_LEVEL +#define PDM_CONFIG_LOG_LEVEL 3 +#endif + +// PDM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_INFO_COLOR +#define PDM_CONFIG_INFO_COLOR 0 +#endif + +// PDM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PDM_CONFIG_DEBUG_COLOR +#define PDM_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //PDM_CONFIG_LOG_ENABLED +// + +#endif //PDM_ENABLED +// + +// PERIPHERAL_RESOURCE_SHARING_ENABLED - nrf_drv_common - Peripheral drivers common module +//========================================================== +#ifndef PERIPHERAL_RESOURCE_SHARING_ENABLED +#define PERIPHERAL_RESOURCE_SHARING_ENABLED 0 +#endif +#if PERIPHERAL_RESOURCE_SHARING_ENABLED +// COMMON_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef COMMON_CONFIG_LOG_ENABLED +#define COMMON_CONFIG_LOG_ENABLED 0 +#endif +#if COMMON_CONFIG_LOG_ENABLED +// COMMON_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef COMMON_CONFIG_LOG_LEVEL +#define COMMON_CONFIG_LOG_LEVEL 3 +#endif + +// COMMON_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMMON_CONFIG_INFO_COLOR +#define COMMON_CONFIG_INFO_COLOR 0 +#endif + +// COMMON_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef COMMON_CONFIG_DEBUG_COLOR +#define COMMON_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //COMMON_CONFIG_LOG_ENABLED +// + +#endif //PERIPHERAL_RESOURCE_SHARING_ENABLED +// + +// POWER_ENABLED - nrf_drv_power - POWER peripheral driver +//========================================================== +#ifndef POWER_ENABLED +#define POWER_ENABLED 0 +#endif +#if POWER_ENABLED +// POWER_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef POWER_CONFIG_IRQ_PRIORITY +#define POWER_CONFIG_IRQ_PRIORITY 3 +#endif + +// POWER_CONFIG_DEFAULT_DCDCEN - The default configuration of main DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCEN +#define POWER_CONFIG_DEFAULT_DCDCEN 0 +#endif + +// POWER_CONFIG_DEFAULT_DCDCENHV - The default configuration of High Voltage DCDC regulator + + +// This settings means only that components for DCDC regulator are installed and it can be enabled. + +#ifndef POWER_CONFIG_DEFAULT_DCDCENHV +#define POWER_CONFIG_DEFAULT_DCDCENHV 0 +#endif + +#endif //POWER_ENABLED +// + +// PPI_ENABLED - nrf_drv_ppi - PPI peripheral driver +//========================================================== +#ifndef PPI_ENABLED +#define PPI_ENABLED 0 +#endif +#if PPI_ENABLED +// PPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PPI_CONFIG_LOG_ENABLED +#define PPI_CONFIG_LOG_ENABLED 0 +#endif +#if PPI_CONFIG_LOG_ENABLED +// PPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PPI_CONFIG_LOG_LEVEL +#define PPI_CONFIG_LOG_LEVEL 3 +#endif + +// PPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_INFO_COLOR +#define PPI_CONFIG_INFO_COLOR 0 +#endif + +// PPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PPI_CONFIG_DEBUG_COLOR +#define PPI_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //PPI_CONFIG_LOG_ENABLED +// + +#endif //PPI_ENABLED +// + +// PWM_ENABLED - nrf_drv_pwm - PWM peripheral driver +//========================================================== +#ifndef PWM_ENABLED +#define PWM_ENABLED 0 +#endif +#if PWM_ENABLED +// PWM_DEFAULT_CONFIG_OUT0_PIN - Out0 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT0_PIN +#define PWM_DEFAULT_CONFIG_OUT0_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT1_PIN - Out1 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT1_PIN +#define PWM_DEFAULT_CONFIG_OUT1_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT2_PIN - Out2 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT2_PIN +#define PWM_DEFAULT_CONFIG_OUT2_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_OUT3_PIN - Out3 pin <0-31> + + +#ifndef PWM_DEFAULT_CONFIG_OUT3_PIN +#define PWM_DEFAULT_CONFIG_OUT3_PIN 31 +#endif + +// PWM_DEFAULT_CONFIG_BASE_CLOCK - Base clock + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 MHz + +#ifndef PWM_DEFAULT_CONFIG_BASE_CLOCK +#define PWM_DEFAULT_CONFIG_BASE_CLOCK 4 +#endif + +// PWM_DEFAULT_CONFIG_COUNT_MODE - Count mode + +// <0=> Up +// <1=> Up and Down + +#ifndef PWM_DEFAULT_CONFIG_COUNT_MODE +#define PWM_DEFAULT_CONFIG_COUNT_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_TOP_VALUE - Top value +#ifndef PWM_DEFAULT_CONFIG_TOP_VALUE +#define PWM_DEFAULT_CONFIG_TOP_VALUE 1000 +#endif + +// PWM_DEFAULT_CONFIG_LOAD_MODE - Load mode + +// <0=> Common +// <1=> Grouped +// <2=> Individual +// <3=> Waveform + +#ifndef PWM_DEFAULT_CONFIG_LOAD_MODE +#define PWM_DEFAULT_CONFIG_LOAD_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_STEP_MODE - Step mode + +// <0=> Auto +// <1=> Triggered + +#ifndef PWM_DEFAULT_CONFIG_STEP_MODE +#define PWM_DEFAULT_CONFIG_STEP_MODE 0 +#endif + +// PWM_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 + +#ifndef PWM_DEFAULT_CONFIG_IRQ_PRIORITY +#define PWM_DEFAULT_CONFIG_IRQ_PRIORITY 7 +#endif + +// PWM0_ENABLED - Enable PWM0 instance + + +#ifndef PWM0_ENABLED +#define PWM0_ENABLED 0 +#endif + +// PWM1_ENABLED - Enable PWM1 instance + + +#ifndef PWM1_ENABLED +#define PWM1_ENABLED 0 +#endif + +// PWM2_ENABLED - Enable PWM2 instance + + +#ifndef PWM2_ENABLED +#define PWM2_ENABLED 0 +#endif + +// PWM_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef PWM_CONFIG_LOG_ENABLED +#define PWM_CONFIG_LOG_ENABLED 0 +#endif +#if PWM_CONFIG_LOG_ENABLED +// PWM_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef PWM_CONFIG_LOG_LEVEL +#define PWM_CONFIG_LOG_LEVEL 3 +#endif + +// PWM_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_INFO_COLOR +#define PWM_CONFIG_INFO_COLOR 0 +#endif + +// PWM_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef PWM_CONFIG_DEBUG_COLOR +#define PWM_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //PWM_CONFIG_LOG_ENABLED +// + +#endif //PWM_ENABLED +// + +// QDEC_ENABLED - nrf_drv_qdec - QDEC peripheral driver +//========================================================== +#ifndef QDEC_ENABLED +#define QDEC_ENABLED 0 +#endif +#if QDEC_ENABLED +// QDEC_CONFIG_REPORTPER - Report period + +// <0=> 10 Samples +// <1=> 40 Samples +// <2=> 80 Samples +// <3=> 120 Samples +// <4=> 160 Samples +// <5=> 200 Samples +// <6=> 240 Samples +// <7=> 280 Samples + +#ifndef QDEC_CONFIG_REPORTPER +#define QDEC_CONFIG_REPORTPER 0 +#endif + +// QDEC_CONFIG_SAMPLEPER - Sample period + +// <0=> 128 us +// <1=> 256 us +// <2=> 512 us +// <3=> 1024 us +// <4=> 2048 us +// <5=> 4096 us +// <6=> 8192 us +// <7=> 16384 us + +#ifndef QDEC_CONFIG_SAMPLEPER +#define QDEC_CONFIG_SAMPLEPER 7 +#endif + +// QDEC_CONFIG_PIO_A - A pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_A +#define QDEC_CONFIG_PIO_A 31 +#endif + +// QDEC_CONFIG_PIO_B - B pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_B +#define QDEC_CONFIG_PIO_B 31 +#endif + +// QDEC_CONFIG_PIO_LED - LED pin <0-31> + + +#ifndef QDEC_CONFIG_PIO_LED +#define QDEC_CONFIG_PIO_LED 31 +#endif + +// QDEC_CONFIG_LEDPRE - LED pre +#ifndef QDEC_CONFIG_LEDPRE +#define QDEC_CONFIG_LEDPRE 511 +#endif + +// QDEC_CONFIG_LEDPOL - LED polarity + +// <0=> Active low +// <1=> Active high + +#ifndef QDEC_CONFIG_LEDPOL +#define QDEC_CONFIG_LEDPOL 1 +#endif + +// QDEC_CONFIG_DBFEN - Debouncing enable + + +#ifndef QDEC_CONFIG_DBFEN +#define QDEC_CONFIG_DBFEN 0 +#endif + +// QDEC_CONFIG_SAMPLE_INTEN - Sample ready interrupt enable + + +#ifndef QDEC_CONFIG_SAMPLE_INTEN +#define QDEC_CONFIG_SAMPLE_INTEN 0 +#endif + +// QDEC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef QDEC_CONFIG_IRQ_PRIORITY +#define QDEC_CONFIG_IRQ_PRIORITY 3 +#endif + +// QDEC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef QDEC_CONFIG_LOG_ENABLED +#define QDEC_CONFIG_LOG_ENABLED 0 +#endif +#if QDEC_CONFIG_LOG_ENABLED +// QDEC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef QDEC_CONFIG_LOG_LEVEL +#define QDEC_CONFIG_LOG_LEVEL 3 +#endif + +// QDEC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_INFO_COLOR +#define QDEC_CONFIG_INFO_COLOR 0 +#endif + +// QDEC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef QDEC_CONFIG_DEBUG_COLOR +#define QDEC_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //QDEC_CONFIG_LOG_ENABLED +// + +#endif //QDEC_ENABLED +// + +// RNG_ENABLED - nrf_drv_rng - RNG peripheral driver +//========================================================== +#ifndef RNG_ENABLED +#define RNG_ENABLED 0 +#endif +#if RNG_ENABLED +// RNG_CONFIG_ERROR_CORRECTION - Error correction + + +#ifndef RNG_CONFIG_ERROR_CORRECTION +#define RNG_CONFIG_ERROR_CORRECTION 0 +#endif + +// RNG_CONFIG_POOL_SIZE - Pool size +#ifndef RNG_CONFIG_POOL_SIZE +#define RNG_CONFIG_POOL_SIZE 32 +#endif + +// RNG_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef RNG_CONFIG_IRQ_PRIORITY +#define RNG_CONFIG_IRQ_PRIORITY 3 +#endif + +// RNG_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RNG_CONFIG_LOG_ENABLED +#define RNG_CONFIG_LOG_ENABLED 0 +#endif +#if RNG_CONFIG_LOG_ENABLED +// RNG_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RNG_CONFIG_LOG_LEVEL +#define RNG_CONFIG_LOG_LEVEL 3 +#endif + +// RNG_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_INFO_COLOR +#define RNG_CONFIG_INFO_COLOR 0 +#endif + +// RNG_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RNG_CONFIG_DEBUG_COLOR +#define RNG_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //RNG_CONFIG_LOG_ENABLED +// + +#endif //RNG_ENABLED +// + +// RTC_ENABLED - nrf_drv_rtc - RTC peripheral driver +//========================================================== +#ifndef RTC_ENABLED +#define RTC_ENABLED 0 +#endif +#if RTC_ENABLED +// RTC_DEFAULT_CONFIG_FREQUENCY - Frequency <16-32768> + + +#ifndef RTC_DEFAULT_CONFIG_FREQUENCY +#define RTC_DEFAULT_CONFIG_FREQUENCY 32768 +#endif + +// RTC_DEFAULT_CONFIG_RELIABLE - Ensures safe compare event triggering + + +#ifndef RTC_DEFAULT_CONFIG_RELIABLE +#define RTC_DEFAULT_CONFIG_RELIABLE 0 +#endif + +// RTC_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef RTC_DEFAULT_CONFIG_IRQ_PRIORITY +#define RTC_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// RTC0_ENABLED - Enable RTC0 instance + + +#ifndef RTC0_ENABLED +#define RTC0_ENABLED 0 +#endif + +// RTC1_ENABLED - Enable RTC1 instance + + +#ifndef RTC1_ENABLED +#define RTC1_ENABLED 0 +#endif + +// RTC2_ENABLED - Enable RTC2 instance + + +#ifndef RTC2_ENABLED +#define RTC2_ENABLED 0 +#endif + +// NRF_MAXIMUM_LATENCY_US - Maximum possible time[us] in highest priority interrupt +#ifndef NRF_MAXIMUM_LATENCY_US +#define NRF_MAXIMUM_LATENCY_US 2000 +#endif + +// RTC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef RTC_CONFIG_LOG_ENABLED +#define RTC_CONFIG_LOG_ENABLED 0 +#endif +#if RTC_CONFIG_LOG_ENABLED +// RTC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef RTC_CONFIG_LOG_LEVEL +#define RTC_CONFIG_LOG_LEVEL 3 +#endif + +// RTC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_INFO_COLOR +#define RTC_CONFIG_INFO_COLOR 0 +#endif + +// RTC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef RTC_CONFIG_DEBUG_COLOR +#define RTC_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //RTC_CONFIG_LOG_ENABLED +// + +#endif //RTC_ENABLED +// + +// SAADC_ENABLED - nrf_drv_saadc - SAADC peripheral driver +//========================================================== +#ifndef SAADC_ENABLED +#define SAADC_ENABLED 0 +#endif +#if SAADC_ENABLED +// SAADC_CONFIG_RESOLUTION - Resolution + +// <0=> 8 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit + +#ifndef SAADC_CONFIG_RESOLUTION +#define SAADC_CONFIG_RESOLUTION 1 +#endif + +// SAADC_CONFIG_OVERSAMPLE - Sample period + +// <0=> Disabled +// <1=> 2x +// <2=> 4x +// <3=> 8x +// <4=> 16x +// <5=> 32x +// <6=> 64x +// <7=> 128x +// <8=> 256x + +#ifndef SAADC_CONFIG_OVERSAMPLE +#define SAADC_CONFIG_OVERSAMPLE 0 +#endif + +// SAADC_CONFIG_LP_MODE - Enabling low power mode + + +#ifndef SAADC_CONFIG_LP_MODE +#define SAADC_CONFIG_LP_MODE 0 +#endif + +// SAADC_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef SAADC_CONFIG_IRQ_PRIORITY +#define SAADC_CONFIG_IRQ_PRIORITY 3 +#endif + +// SAADC_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SAADC_CONFIG_LOG_ENABLED +#define SAADC_CONFIG_LOG_ENABLED 0 +#endif +#if SAADC_CONFIG_LOG_ENABLED +// SAADC_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SAADC_CONFIG_LOG_LEVEL +#define SAADC_CONFIG_LOG_LEVEL 3 +#endif + +// SAADC_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_INFO_COLOR +#define SAADC_CONFIG_INFO_COLOR 0 +#endif + +// SAADC_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SAADC_CONFIG_DEBUG_COLOR +#define SAADC_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //SAADC_CONFIG_LOG_ENABLED +// + +#endif //SAADC_ENABLED +// + +// SPIS_ENABLED - nrf_drv_spis - SPI Slave driver +//========================================================== +#ifndef SPIS_ENABLED +#define SPIS_ENABLED 0 +#endif +#if SPIS_ENABLED +// SPIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef SPIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// SPIS_DEFAULT_MODE - Mode + +// <0=> MODE_0 +// <1=> MODE_1 +// <2=> MODE_2 +// <3=> MODE_3 + +#ifndef SPIS_DEFAULT_MODE +#define SPIS_DEFAULT_MODE 0 +#endif + +// SPIS_DEFAULT_BIT_ORDER - SPIS default bit order + +// <0=> MSB first +// <1=> LSB first + +#ifndef SPIS_DEFAULT_BIT_ORDER +#define SPIS_DEFAULT_BIT_ORDER 0 +#endif + +// SPIS_DEFAULT_DEF - SPIS default DEF character <0-255> + + +#ifndef SPIS_DEFAULT_DEF +#define SPIS_DEFAULT_DEF 255 +#endif + +// SPIS_DEFAULT_ORC - SPIS default ORC character <0-255> + + +#ifndef SPIS_DEFAULT_ORC +#define SPIS_DEFAULT_ORC 255 +#endif + +// SPIS0_ENABLED - Enable SPIS0 instance + + +#ifndef SPIS0_ENABLED +#define SPIS0_ENABLED 0 +#endif + +// SPIS1_ENABLED - Enable SPIS1 instance + + +#ifndef SPIS1_ENABLED +#define SPIS1_ENABLED 0 +#endif + +// SPIS2_ENABLED - Enable SPIS2 instance + + +#ifndef SPIS2_ENABLED +#define SPIS2_ENABLED 0 +#endif + +// SPIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPIS_CONFIG_LOG_ENABLED +#define SPIS_CONFIG_LOG_ENABLED 0 +#endif +#if SPIS_CONFIG_LOG_ENABLED +// SPIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPIS_CONFIG_LOG_LEVEL +#define SPIS_CONFIG_LOG_LEVEL 3 +#endif + +// SPIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_INFO_COLOR +#define SPIS_CONFIG_INFO_COLOR 0 +#endif + +// SPIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPIS_CONFIG_DEBUG_COLOR +#define SPIS_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //SPIS_CONFIG_LOG_ENABLED +// + +#endif //SPIS_ENABLED +// + +// SPI_ENABLED - nrf_drv_spi - SPI/SPIM peripheral driver +//========================================================== +#ifndef SPI_ENABLED +#define SPI_ENABLED 0 +#endif +#if SPI_ENABLED +// SPI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef SPI_DEFAULT_CONFIG_IRQ_PRIORITY +#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// SPI0_ENABLED - Enable SPI0 instance +//========================================================== +#ifndef SPI0_ENABLED +#define SPI0_ENABLED 0 +#endif +#if SPI0_ENABLED +// SPI0_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI0_USE_EASY_DMA +#define SPI0_USE_EASY_DMA 0 +#endif + +// SPI0_DEFAULT_FREQUENCY - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef SPI0_DEFAULT_FREQUENCY +#define SPI0_DEFAULT_FREQUENCY 1073741824 +#endif + +#endif //SPI0_ENABLED +// + +// SPI1_ENABLED - Enable SPI1 instance +//========================================================== +#ifndef SPI1_ENABLED +#define SPI1_ENABLED 0 +#endif +#if SPI1_ENABLED +// SPI1_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI1_USE_EASY_DMA +#define SPI1_USE_EASY_DMA 0 +#endif + +// SPI1_DEFAULT_FREQUENCY - SPI frequency + +// <33554432=> 125 kHz +// <67108864=> 250 kHz +// <134217728=> 500 kHz +// <268435456=> 1 MHz +// <536870912=> 2 MHz +// <1073741824=> 4 MHz +// <2147483648=> 8 MHz + +#ifndef SPI1_DEFAULT_FREQUENCY +#define SPI1_DEFAULT_FREQUENCY 1073741824 +#endif + +#endif //SPI1_ENABLED +// + +// SPI2_ENABLED - Enable SPI2 instance +//========================================================== +#ifndef SPI2_ENABLED +#define SPI2_ENABLED 0 +#endif +#if SPI2_ENABLED +// SPI2_USE_EASY_DMA - Use EasyDMA + + +#ifndef SPI2_USE_EASY_DMA +#define SPI2_USE_EASY_DMA 0 +#endif + +// SPI2_DEFAULT_FREQUENCY - Use EasyDMA + + +#ifndef SPI2_DEFAULT_FREQUENCY +#define SPI2_DEFAULT_FREQUENCY 0 +#endif + +#endif //SPI2_ENABLED +// + +// SPI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef SPI_CONFIG_LOG_ENABLED +#define SPI_CONFIG_LOG_ENABLED 0 +#endif +#if SPI_CONFIG_LOG_ENABLED +// SPI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef SPI_CONFIG_LOG_LEVEL +#define SPI_CONFIG_LOG_LEVEL 3 +#endif + +// SPI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_INFO_COLOR +#define SPI_CONFIG_INFO_COLOR 0 +#endif + +// SPI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef SPI_CONFIG_DEBUG_COLOR +#define SPI_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //SPI_CONFIG_LOG_ENABLED +// + +#endif //SPI_ENABLED +// + +// TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver +//========================================================== +#ifndef TIMER_ENABLED +#define TIMER_ENABLED 0 +#endif +#if TIMER_ENABLED +// TIMER_DEFAULT_CONFIG_FREQUENCY - Timer frequency if in Timer mode + +// <0=> 16 MHz +// <1=> 8 MHz +// <2=> 4 MHz +// <3=> 2 MHz +// <4=> 1 MHz +// <5=> 500 kHz +// <6=> 250 kHz +// <7=> 125 kHz +// <8=> 62.5 kHz +// <9=> 31.25 kHz + +#ifndef TIMER_DEFAULT_CONFIG_FREQUENCY +#define TIMER_DEFAULT_CONFIG_FREQUENCY 0 +#endif + +// TIMER_DEFAULT_CONFIG_MODE - Timer mode or operation + +// <0=> Timer +// <1=> Counter + +#ifndef TIMER_DEFAULT_CONFIG_MODE +#define TIMER_DEFAULT_CONFIG_MODE 0 +#endif + +// TIMER_DEFAULT_CONFIG_BIT_WIDTH - Timer counter bit width + +// <0=> 16 bit +// <1=> 8 bit +// <2=> 24 bit +// <3=> 32 bit + +#ifndef TIMER_DEFAULT_CONFIG_BIT_WIDTH +#define TIMER_DEFAULT_CONFIG_BIT_WIDTH 0 +#endif + +// TIMER_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef TIMER_DEFAULT_CONFIG_IRQ_PRIORITY +#define TIMER_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// TIMER0_ENABLED - Enable TIMER0 instance + + +#ifndef TIMER0_ENABLED +#define TIMER0_ENABLED 0 +#endif + +// TIMER1_ENABLED - Enable TIMER1 instance + + +#ifndef TIMER1_ENABLED +#define TIMER1_ENABLED 0 +#endif + +// TIMER2_ENABLED - Enable TIMER2 instance + + +#ifndef TIMER2_ENABLED +#define TIMER2_ENABLED 0 +#endif + +// TIMER3_ENABLED - Enable TIMER3 instance + + +#ifndef TIMER3_ENABLED +#define TIMER3_ENABLED 0 +#endif + +// TIMER4_ENABLED - Enable TIMER4 instance + + +#ifndef TIMER4_ENABLED +#define TIMER4_ENABLED 0 +#endif + +// TIMER_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TIMER_CONFIG_LOG_ENABLED +#define TIMER_CONFIG_LOG_ENABLED 0 +#endif +#if TIMER_CONFIG_LOG_ENABLED +// TIMER_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TIMER_CONFIG_LOG_LEVEL +#define TIMER_CONFIG_LOG_LEVEL 3 +#endif + +// TIMER_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_INFO_COLOR +#define TIMER_CONFIG_INFO_COLOR 0 +#endif + +// TIMER_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TIMER_CONFIG_DEBUG_COLOR +#define TIMER_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //TIMER_CONFIG_LOG_ENABLED +// + +#endif //TIMER_ENABLED +// + +// TWIS_ENABLED - nrf_drv_twis - TWIS peripheral driver +//========================================================== +#ifndef TWIS_ENABLED +#define TWIS_ENABLED 0 +#endif +#if TWIS_ENABLED +// TWIS_DEFAULT_CONFIG_ADDR0 - Address0 +#ifndef TWIS_DEFAULT_CONFIG_ADDR0 +#define TWIS_DEFAULT_CONFIG_ADDR0 0 +#endif + +// TWIS_DEFAULT_CONFIG_ADDR1 - Address1 +#ifndef TWIS_DEFAULT_CONFIG_ADDR1 +#define TWIS_DEFAULT_CONFIG_ADDR1 0 +#endif + +// TWIS_DEFAULT_CONFIG_SCL_PULL - SCL pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SCL_PULL +#define TWIS_DEFAULT_CONFIG_SCL_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_SDA_PULL - SDA pin pull configuration + +// <0=> Disabled +// <1=> Pull down +// <3=> Pull up + +#ifndef TWIS_DEFAULT_CONFIG_SDA_PULL +#define TWIS_DEFAULT_CONFIG_SDA_PULL 0 +#endif + +// TWIS_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef TWIS_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWIS_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// TWIS0_ENABLED - Enable TWIS0 instance + + +#ifndef TWIS0_ENABLED +#define TWIS0_ENABLED 0 +#endif + +// TWIS1_ENABLED - Enable TWIS1 instance + + +#ifndef TWIS1_ENABLED +#define TWIS1_ENABLED 0 +#endif + +// TWIS_ASSUME_INIT_AFTER_RESET_ONLY - Assume that any instance would be initialized only once + + +// Optimization flag. Registers used by TWIS are shared by other peripherals. Normally, during initialization driver tries to clear all registers to known state before doing the initialization itself. This gives initialization safe procedure, no matter when it would be called. If you activate TWIS only once and do never uninitialize it - set this flag to 1 what gives more optimal code. + +#ifndef TWIS_ASSUME_INIT_AFTER_RESET_ONLY +#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 +#endif + +// TWIS_NO_SYNC_MODE - Remove support for synchronous mode + + +// Synchronous mode would be used in specific situations. And it uses some additional code and data memory to safely process state machine by polling it in status functions. If this functionality is not required it may be disabled to free some resources. + +#ifndef TWIS_NO_SYNC_MODE +#define TWIS_NO_SYNC_MODE 0 +#endif + +// TWIS_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWIS_CONFIG_LOG_ENABLED +#define TWIS_CONFIG_LOG_ENABLED 0 +#endif +#if TWIS_CONFIG_LOG_ENABLED +// TWIS_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWIS_CONFIG_LOG_LEVEL +#define TWIS_CONFIG_LOG_LEVEL 3 +#endif + +// TWIS_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_INFO_COLOR +#define TWIS_CONFIG_INFO_COLOR 0 +#endif + +// TWIS_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWIS_CONFIG_DEBUG_COLOR +#define TWIS_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //TWIS_CONFIG_LOG_ENABLED +// + +#endif //TWIS_ENABLED +// + +// TWI_ENABLED - nrf_drv_twi - TWI/TWIM peripheral driver +//========================================================== +#ifndef TWI_ENABLED +#define TWI_ENABLED 0 +#endif +#if TWI_ENABLED +// TWI_DEFAULT_CONFIG_FREQUENCY - Frequency + +// <26738688=> 100k +// <67108864=> 250k +// <104857600=> 400k + +#ifndef TWI_DEFAULT_CONFIG_FREQUENCY +#define TWI_DEFAULT_CONFIG_FREQUENCY 26738688 +#endif + +// TWI_DEFAULT_CONFIG_CLR_BUS_INIT - Enables bus clearing procedure during init + + +#ifndef TWI_DEFAULT_CONFIG_CLR_BUS_INIT +#define TWI_DEFAULT_CONFIG_CLR_BUS_INIT 0 +#endif + +// TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT - Enables bus holding after uninit + + +#ifndef TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT +#define TWI_DEFAULT_CONFIG_HOLD_BUS_UNINIT 0 +#endif + +// TWI_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef TWI_DEFAULT_CONFIG_IRQ_PRIORITY +#define TWI_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// TWI0_ENABLED - Enable TWI0 instance +//========================================================== +#ifndef TWI0_ENABLED +#define TWI0_ENABLED 0 +#endif +#if TWI0_ENABLED +// TWI0_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI0_USE_EASY_DMA +#define TWI0_USE_EASY_DMA 0 +#endif + +#endif //TWI0_ENABLED +// + +// TWI1_ENABLED - Enable TWI1 instance +//========================================================== +#ifndef TWI1_ENABLED +#define TWI1_ENABLED 0 +#endif +#if TWI1_ENABLED +// TWI1_USE_EASY_DMA - Use EasyDMA (if present) + + +#ifndef TWI1_USE_EASY_DMA +#define TWI1_USE_EASY_DMA 0 +#endif + +#endif //TWI1_ENABLED +// + +// TWI_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef TWI_CONFIG_LOG_ENABLED +#define TWI_CONFIG_LOG_ENABLED 0 +#endif +#if TWI_CONFIG_LOG_ENABLED +// TWI_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef TWI_CONFIG_LOG_LEVEL +#define TWI_CONFIG_LOG_LEVEL 3 +#endif + +// TWI_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_INFO_COLOR +#define TWI_CONFIG_INFO_COLOR 0 +#endif + +// TWI_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef TWI_CONFIG_DEBUG_COLOR +#define TWI_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //TWI_CONFIG_LOG_ENABLED +// + +#endif //TWI_ENABLED +// + +// UART_ENABLED - nrf_drv_uart - UART/UARTE peripheral driver +//========================================================== +#ifndef UART_ENABLED +#define UART_ENABLED 1 +#endif +#if UART_ENABLED +// UART_DEFAULT_CONFIG_HWFC - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef UART_DEFAULT_CONFIG_HWFC +#define UART_DEFAULT_CONFIG_HWFC 0 +#endif + +// UART_DEFAULT_CONFIG_PARITY - Parity + +// <0=> Excluded +// <14=> Included + +#ifndef UART_DEFAULT_CONFIG_PARITY +#define UART_DEFAULT_CONFIG_PARITY 0 +#endif + +// UART_DEFAULT_CONFIG_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud + +#ifndef UART_DEFAULT_CONFIG_BAUDRATE +#define UART_DEFAULT_CONFIG_BAUDRATE 30924800 +#endif + +// UART_DEFAULT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef UART_DEFAULT_CONFIG_IRQ_PRIORITY +#define UART_DEFAULT_CONFIG_IRQ_PRIORITY 3 +#endif + +// UART_EASY_DMA_SUPPORT - Driver supporting EasyDMA + + +#ifndef UART_EASY_DMA_SUPPORT +#define UART_EASY_DMA_SUPPORT 1 +#endif + +// UART_LEGACY_SUPPORT - Driver supporting Legacy mode + + +#ifndef UART_LEGACY_SUPPORT +#define UART_LEGACY_SUPPORT 1 +#endif + +// UART0_ENABLED - Enable UART0 instance +//========================================================== +#ifndef UART0_ENABLED +#define UART0_ENABLED 1 +#endif +#if UART0_ENABLED +// UART0_CONFIG_USE_EASY_DMA - Default setting for using EasyDMA + + +#ifndef UART0_CONFIG_USE_EASY_DMA +#define UART0_CONFIG_USE_EASY_DMA 1 +#endif + +#endif //UART0_ENABLED +// + +// UART_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef UART_CONFIG_LOG_ENABLED +#define UART_CONFIG_LOG_ENABLED 0 +#endif +#if UART_CONFIG_LOG_ENABLED +// UART_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef UART_CONFIG_LOG_LEVEL +#define UART_CONFIG_LOG_LEVEL 3 +#endif + +// UART_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_INFO_COLOR +#define UART_CONFIG_INFO_COLOR 0 +#endif + +// UART_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef UART_CONFIG_DEBUG_COLOR +#define UART_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //UART_CONFIG_LOG_ENABLED +// + +#endif //UART_ENABLED +// + +// USBD_ENABLED - nrf_drv_usbd - USB driver +//========================================================== +#ifndef USBD_ENABLED +#define USBD_ENABLED 0 +#endif +#if USBD_ENABLED +// NRF_DRV_USBD_DMASCHEDULER_MODE - USBD SMA scheduler working scheme + +// <0=> Prioritized access +// <1=> Round Robin + +#ifndef NRF_DRV_USBD_DMASCHEDULER_MODE +#define NRF_DRV_USBD_DMASCHEDULER_MODE 0 +#endif + +// NRF_USBD_DRV_LOG_ENABLED - Enable logging. + + +#ifndef NRF_USBD_DRV_LOG_ENABLED +#define NRF_USBD_DRV_LOG_ENABLED 0 +#endif + +#endif //USBD_ENABLED +// + +// WDT_ENABLED - nrf_drv_wdt - WDT peripheral driver +//========================================================== +#ifndef WDT_ENABLED +#define WDT_ENABLED 0 +#endif +#if WDT_ENABLED +// WDT_CONFIG_BEHAVIOUR - WDT behavior in CPU SLEEP or HALT mode + +// <1=> Run in SLEEP, Pause in HALT +// <8=> Pause in SLEEP, Run in HALT +// <9=> Run in SLEEP and HALT +// <0=> Pause in SLEEP and HALT + +#ifndef WDT_CONFIG_BEHAVIOUR +#define WDT_CONFIG_BEHAVIOUR 1 +#endif + +// WDT_CONFIG_RELOAD_VALUE - Reload value <15-4294967295> + + +#ifndef WDT_CONFIG_RELOAD_VALUE +#define WDT_CONFIG_RELOAD_VALUE 2000 +#endif + +// WDT_CONFIG_IRQ_PRIORITY - Interrupt priority + + +// Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice +// <0=> 0 (highest) +// <1=> 1 +// <2=> 2 +// <3=> 3 + +#ifndef WDT_CONFIG_IRQ_PRIORITY +#define WDT_CONFIG_IRQ_PRIORITY 3 +#endif + +// WDT_CONFIG_LOG_ENABLED - Enables logging in the module. +//========================================================== +#ifndef WDT_CONFIG_LOG_ENABLED +#define WDT_CONFIG_LOG_ENABLED 0 +#endif +#if WDT_CONFIG_LOG_ENABLED +// WDT_CONFIG_LOG_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef WDT_CONFIG_LOG_LEVEL +#define WDT_CONFIG_LOG_LEVEL 3 +#endif + +// WDT_CONFIG_INFO_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_INFO_COLOR +#define WDT_CONFIG_INFO_COLOR 0 +#endif + +// WDT_CONFIG_DEBUG_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef WDT_CONFIG_DEBUG_COLOR +#define WDT_CONFIG_DEBUG_COLOR 0 +#endif + +#endif //WDT_CONFIG_LOG_ENABLED +// + +#endif //WDT_ENABLED +// + +// +//========================================================== + +// nRF_Libraries + +//========================================================== +// APP_FIFO_ENABLED - app_fifo - Software FIFO implementation + + +#ifndef APP_FIFO_ENABLED +#define APP_FIFO_ENABLED 1 +#endif + +// APP_GPIOTE_ENABLED - app_gpiote - GPIOTE events dispatcher + + +#ifndef APP_GPIOTE_ENABLED +#define APP_GPIOTE_ENABLED 0 +#endif + +// APP_PWM_ENABLED - app_pwm - PWM functionality + + +#ifndef APP_PWM_ENABLED +#define APP_PWM_ENABLED 0 +#endif + +// APP_SCHEDULER_ENABLED - app_scheduler - Events scheduler +//========================================================== +#ifndef APP_SCHEDULER_ENABLED +#define APP_SCHEDULER_ENABLED 0 +#endif +#if APP_SCHEDULER_ENABLED +// APP_SCHEDULER_WITH_PAUSE - Enabling pause feature + + +#ifndef APP_SCHEDULER_WITH_PAUSE +#define APP_SCHEDULER_WITH_PAUSE 0 +#endif + +// APP_SCHEDULER_WITH_PROFILER - Enabling scheduler profiling + + +#ifndef APP_SCHEDULER_WITH_PROFILER +#define APP_SCHEDULER_WITH_PROFILER 0 +#endif + +#endif //APP_SCHEDULER_ENABLED +// + +// APP_TIMER_ENABLED - app_timer - Application timer functionality +//========================================================== +#ifndef APP_TIMER_ENABLED +#define APP_TIMER_ENABLED 1 +#endif +#if APP_TIMER_ENABLED +// APP_TIMER_WITH_PROFILER - Enable app_timer profiling + + +#ifndef APP_TIMER_WITH_PROFILER +#define APP_TIMER_WITH_PROFILER 0 +#endif + +// APP_TIMER_KEEPS_RTC_ACTIVE - Enable RTC always on + + +// If option is enabled RTC is kept running even if there is no active timers. +// This option can be used when app_timer is used for timestamping. + +#ifndef APP_TIMER_KEEPS_RTC_ACTIVE +#define APP_TIMER_KEEPS_RTC_ACTIVE 0 +#endif + +#endif //APP_TIMER_ENABLED +// + +// APP_TWI_ENABLED - app_twi - TWI transaction manager + + +#ifndef APP_TWI_ENABLED +#define APP_TWI_ENABLED 0 +#endif + +// APP_UART_ENABLED - app_uart - UART driver +//========================================================== +#ifndef APP_UART_ENABLED +#define APP_UART_ENABLED 1 +#endif +#if APP_UART_ENABLED +// APP_UART_DRIVER_INSTANCE - UART instance used + +// <0=> 0 + +#ifndef APP_UART_DRIVER_INSTANCE +#define APP_UART_DRIVER_INSTANCE 0 +#endif + +#endif //APP_UART_ENABLED +// + +// APP_USBD_CLASS_AUDIO_ENABLED - app_usbd_audio - USB AUDIO class + + +#ifndef APP_USBD_CLASS_AUDIO_ENABLED +#define APP_USBD_CLASS_AUDIO_ENABLED 0 +#endif + +// APP_USBD_CLASS_HID_ENABLED - app_usbd_hid - USB HID class + + +#ifndef APP_USBD_CLASS_HID_ENABLED +#define APP_USBD_CLASS_HID_ENABLED 0 +#endif + +// APP_USBD_HID_GENERIC_ENABLED - app_usbd_hid_generic - USB HID generic + + +#ifndef APP_USBD_HID_GENERIC_ENABLED +#define APP_USBD_HID_GENERIC_ENABLED 0 +#endif + +// APP_USBD_HID_KBD_ENABLED - app_usbd_hid_kbd - USB HID keyboard + + +#ifndef APP_USBD_HID_KBD_ENABLED +#define APP_USBD_HID_KBD_ENABLED 0 +#endif + +// APP_USBD_HID_MOUSE_ENABLED - app_usbd_hid_mouse - USB HID mouse + + +#ifndef APP_USBD_HID_MOUSE_ENABLED +#define APP_USBD_HID_MOUSE_ENABLED 0 +#endif + +// BUTTON_ENABLED - app_button - buttons handling module + + +#ifndef BUTTON_ENABLED +#define BUTTON_ENABLED 1 +#endif + +// CRC16_ENABLED - crc16 - CRC16 calculation routines + + +#ifndef CRC16_ENABLED +#define CRC16_ENABLED 0 +#endif + +// CRC32_ENABLED - crc32 - CRC32 calculation routines + + +#ifndef CRC32_ENABLED +#define CRC32_ENABLED 0 +#endif + +// ECC_ENABLED - ecc - Elliptic Curve Cryptography Library + + +#ifndef ECC_ENABLED +#define ECC_ENABLED 0 +#endif + +// FDS_ENABLED - fds - Flash data storage module +//========================================================== +#ifndef FDS_ENABLED +#define FDS_ENABLED 0 +#endif +#if FDS_ENABLED +// FDS_OP_QUEUE_SIZE - Size of the internal queue. +#ifndef FDS_OP_QUEUE_SIZE +#define FDS_OP_QUEUE_SIZE 4 +#endif + +// FDS_CHUNK_QUEUE_SIZE - Determines how many @ref fds_record_chunk_t structures can be buffered at any time. +#ifndef FDS_CHUNK_QUEUE_SIZE +#define FDS_CHUNK_QUEUE_SIZE 8 +#endif + +// FDS_MAX_USERS - Maximum number of callbacks that can be registered. +#ifndef FDS_MAX_USERS +#define FDS_MAX_USERS 8 +#endif + +// FDS_VIRTUAL_PAGES - Number of virtual flash pages to use. +// One of the virtual pages is reserved by the system for garbage collection. +// Therefore, the minimum is two virtual pages: one page to store data and +// one page to be used by the system for garbage collection. The total amount +// of flash memory that is used by FDS amounts to @ref FDS_VIRTUAL_PAGES +// @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes. + +#ifndef FDS_VIRTUAL_PAGES +#define FDS_VIRTUAL_PAGES 3 +#endif + +// FDS_VIRTUAL_PAGE_SIZE - The size of a virtual page of flash memory, expressed in number of 4-byte words. + + +// By default, a virtual page is the same size as a physical page. +// The size of a virtual page must be a multiple of the size of a physical page. +// <256=> 256 +// <512=> 512 +// <1024=> 1024 + +#ifndef FDS_VIRTUAL_PAGE_SIZE +#define FDS_VIRTUAL_PAGE_SIZE 256 +#endif + +#endif //FDS_ENABLED +// + +// FSTORAGE_ENABLED - fstorage - Flash storage module +//========================================================== +#ifndef FSTORAGE_ENABLED +#define FSTORAGE_ENABLED 0 +#endif +#if FSTORAGE_ENABLED +// FS_QUEUE_SIZE - Configures the size of the internal queue. +// Increase this if there are many users, or if it is likely that many +// operation will be queued at once without waiting for the previous operations +// to complete. In general, increase the queue size if you frequently receive +// @ref FS_ERR_QUEUE_FULL errors when calling @ref fs_store or @ref fs_erase. + +#ifndef FS_QUEUE_SIZE +#define FS_QUEUE_SIZE 4 +#endif + +// FS_OP_MAX_RETRIES - Number attempts to execute an operation if the SoftDevice fails. +// Increase this value if events return the @ref FS_ERR_OPERATION_TIMEOUT +// error often. The SoftDevice may fail to schedule flash access due to high BLE activity. + +#ifndef FS_OP_MAX_RETRIES +#define FS_OP_MAX_RETRIES 3 +#endif + +// FS_MAX_WRITE_SIZE_WORDS - Maximum number of words to be written to flash in a single operation. +// Tweaking this value can increase the chances of the SoftDevice being +// able to fit flash operations in between radio activity. This value is bound by the +// maximum number of words which the SoftDevice can write to flash in a single call to +// @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs. + +#ifndef FS_MAX_WRITE_SIZE_WORDS +#define FS_MAX_WRITE_SIZE_WORDS 256 +#endif + +#endif //FSTORAGE_ENABLED +// + +// HARDFAULT_HANDLER_ENABLED - hardfault_default - HardFault default handler for debugging and release + + +#ifndef HARDFAULT_HANDLER_ENABLED +#define HARDFAULT_HANDLER_ENABLED 0 +#endif + +// HCI_MEM_POOL_ENABLED - hci_mem_pool - memory pool implementation used by HCI +//========================================================== +#ifndef HCI_MEM_POOL_ENABLED +#define HCI_MEM_POOL_ENABLED 0 +#endif +#if HCI_MEM_POOL_ENABLED +// HCI_TX_BUF_SIZE - TX buffer size in bytes. +#ifndef HCI_TX_BUF_SIZE +#define HCI_TX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_SIZE - RX buffer size in bytes. +#ifndef HCI_RX_BUF_SIZE +#define HCI_RX_BUF_SIZE 600 +#endif + +// HCI_RX_BUF_QUEUE_SIZE - RX buffer queue size. +#ifndef HCI_RX_BUF_QUEUE_SIZE +#define HCI_RX_BUF_QUEUE_SIZE 4 +#endif + +#endif //HCI_MEM_POOL_ENABLED +// + +// HCI_SLIP_ENABLED - hci_slip - SLIP protocol implementation used by HCI +//========================================================== +#ifndef HCI_SLIP_ENABLED +#define HCI_SLIP_ENABLED 0 +#endif +#if HCI_SLIP_ENABLED +// HCI_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud + +#ifndef HCI_UART_BAUDRATE +#define HCI_UART_BAUDRATE 30924800 +#endif + +// HCI_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef HCI_UART_FLOW_CONTROL +#define HCI_UART_FLOW_CONTROL 0 +#endif + +// HCI_UART_RX_PIN - UART RX pin +#ifndef HCI_UART_RX_PIN +#define HCI_UART_RX_PIN 11 +#endif + +// HCI_UART_TX_PIN - UART TX pin +#ifndef HCI_UART_TX_PIN +#define HCI_UART_TX_PIN 9 +#endif + +// HCI_UART_RTS_PIN - UART RTS pin +#ifndef HCI_UART_RTS_PIN +#define HCI_UART_RTS_PIN 8 +#endif + +// HCI_UART_CTS_PIN - UART CTS pin +#ifndef HCI_UART_CTS_PIN +#define HCI_UART_CTS_PIN 10 +#endif + +#endif //HCI_SLIP_ENABLED +// + +// HCI_TRANSPORT_ENABLED - hci_transport - HCI transport +//========================================================== +#ifndef HCI_TRANSPORT_ENABLED +#define HCI_TRANSPORT_ENABLED 0 +#endif +#if HCI_TRANSPORT_ENABLED +// HCI_MAX_PACKET_SIZE_IN_BITS - Maximum size of a single application packet in bits. +#ifndef HCI_MAX_PACKET_SIZE_IN_BITS +#define HCI_MAX_PACKET_SIZE_IN_BITS 8000 +#endif + +#endif //HCI_TRANSPORT_ENABLED +// + +// LED_SOFTBLINK_ENABLED - led_softblink - led_softblink module + + +#ifndef LED_SOFTBLINK_ENABLED +#define LED_SOFTBLINK_ENABLED 0 +#endif + +// LOW_POWER_PWM_ENABLED - low_power_pwm - low_power_pwm module + + +#ifndef LOW_POWER_PWM_ENABLED +#define LOW_POWER_PWM_ENABLED 0 +#endif + +// MEM_MANAGER_ENABLED - mem_manager - Dynamic memory allocator +//========================================================== +#ifndef MEM_MANAGER_ENABLED +#define MEM_MANAGER_ENABLED 0 +#endif +#if MEM_MANAGER_ENABLED +// MEMORY_MANAGER_SMALL_BLOCK_COUNT - Size of each memory blocks identified as 'small' block. <0-255> + + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_COUNT +#define MEMORY_MANAGER_SMALL_BLOCK_COUNT 1 +#endif + +// MEMORY_MANAGER_SMALL_BLOCK_SIZE - Size of each memory blocks identified as 'small' block. +// Size of each memory blocks identified as 'small' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_SMALL_BLOCK_SIZE +#define MEMORY_MANAGER_SMALL_BLOCK_SIZE 32 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_COUNT - Size of each memory blocks identified as 'medium' block. <0-255> + + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_COUNT +#define MEMORY_MANAGER_MEDIUM_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_MEDIUM_BLOCK_SIZE - Size of each memory blocks identified as 'medium' block. +// Size of each memory blocks identified as 'medium' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_MEDIUM_BLOCK_SIZE +#define MEMORY_MANAGER_MEDIUM_BLOCK_SIZE 256 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_COUNT - Size of each memory blocks identified as 'large' block. <0-255> + + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_COUNT +#define MEMORY_MANAGER_LARGE_BLOCK_COUNT 0 +#endif + +// MEMORY_MANAGER_LARGE_BLOCK_SIZE - Size of each memory blocks identified as 'large' block. +// Size of each memory blocks identified as 'large' block. Memory block are recommended to be word-sized. + +#ifndef MEMORY_MANAGER_LARGE_BLOCK_SIZE +#define MEMORY_MANAGER_LARGE_BLOCK_SIZE 256 +#endif + +// MEM_MANAGER_ENABLE_LOGS - Enable debug trace in the module. + + +#ifndef MEM_MANAGER_ENABLE_LOGS +#define MEM_MANAGER_ENABLE_LOGS 0 +#endif + +// MEM_MANAGER_DISABLE_API_PARAM_CHECK - Disable API parameter checks in the module. + + +#ifndef MEM_MANAGER_DISABLE_API_PARAM_CHECK +#define MEM_MANAGER_DISABLE_API_PARAM_CHECK 0 +#endif + +#endif //MEM_MANAGER_ENABLED +// + +// NRF_CSENSE_ENABLED - nrf_csense - nrf_csense module +//========================================================== +#ifndef NRF_CSENSE_ENABLED +#define NRF_CSENSE_ENABLED 0 +#endif +#if NRF_CSENSE_ENABLED +// NRF_CSENSE_PAD_HYSTERESIS - Minimal value of change to decide that pad was touched. +#ifndef NRF_CSENSE_PAD_HYSTERESIS +#define NRF_CSENSE_PAD_HYSTERESIS 15 +#endif + +// NRF_CSENSE_PAD_DEVIATION - Minimal value measured on pad to take its value while calculating step. +#ifndef NRF_CSENSE_PAD_DEVIATION +#define NRF_CSENSE_PAD_DEVIATION 70 +#endif + +// NRF_CSENSE_MIN_PAD_VALUE - Minimum normalized value on pad to take its value into account. +#ifndef NRF_CSENSE_MIN_PAD_VALUE +#define NRF_CSENSE_MIN_PAD_VALUE 20 +#endif + +// NRF_CSENSE_MAX_PADS_NUMBER - Maximum number of pads used for one instance. +#ifndef NRF_CSENSE_MAX_PADS_NUMBER +#define NRF_CSENSE_MAX_PADS_NUMBER 20 +#endif + +// NRF_CSENSE_MAX_VALUE - Maximum normalized value got from measurement. +#ifndef NRF_CSENSE_MAX_VALUE +#define NRF_CSENSE_MAX_VALUE 1000 +#endif + +// NRF_CSENSE_OUTPUT_PIN - Output pin used by lower module. +// This is only used when running on NRF51. + +#ifndef NRF_CSENSE_OUTPUT_PIN +#define NRF_CSENSE_OUTPUT_PIN 30 +#endif + +#endif //NRF_CSENSE_ENABLED +// + +// NRF_DRV_CSENSE_ENABLED - nrf_drv_csense - Capacitive sensor module +//========================================================== +#ifndef NRF_DRV_CSENSE_ENABLED +#define NRF_DRV_CSENSE_ENABLED 0 +#endif +#if NRF_DRV_CSENSE_ENABLED +// TIMER0_FOR_CSENSE - First TIMER instance used by the driver (except nRF51) +#ifndef TIMER0_FOR_CSENSE +#define TIMER0_FOR_CSENSE 1 +#endif + +// TIMER1_FOR_CSENSE - Second TIMER instance used by the driver (except nRF51) +#ifndef TIMER1_FOR_CSENSE +#define TIMER1_FOR_CSENSE 2 +#endif + +// MEASUREMENT_PERIOD - Single measurement period. +// Time of single measurement can be calculated as T = (1/2)*MEASUREMENT_PERIOD*(1/f_OSC) where f_OSC = I_SOURCE / (2C*(VUP-VDOWN) ). I_SOURCE, VUP and VDOWN are values used to initialize COMP and C is capacitance of used pad. + +#ifndef MEASUREMENT_PERIOD +#define MEASUREMENT_PERIOD 20 +#endif + +#endif //NRF_DRV_CSENSE_ENABLED +// + +// NRF_QUEUE_ENABLED - nrf_queue - Queue module + + +#ifndef NRF_QUEUE_ENABLED +#define NRF_QUEUE_ENABLED 0 +#endif + +// RETARGET_ENABLED - retarget - Retargeting stdio functions + + +#ifndef RETARGET_ENABLED +#define RETARGET_ENABLED 1 +#endif + +// SLIP_ENABLED - slip - SLIP encoding decoding + + +#ifndef SLIP_ENABLED +#define SLIP_ENABLED 0 +#endif + +// app_usbd_cdc_acm - USB CDC ACM class + +//========================================================== +// APP_USBD_CLASS_CDC_ACM_ENABLED - Enabling USBD CDC ACM Class library + + +#ifndef APP_USBD_CLASS_CDC_ACM_ENABLED +#define APP_USBD_CLASS_CDC_ACM_ENABLED 0 +#endif + +// APP_USBD_CDC_ACM_LOG_ENABLED - Enables logging in the module. + + +#ifndef APP_USBD_CDC_ACM_LOG_ENABLED +#define APP_USBD_CDC_ACM_LOG_ENABLED 0 +#endif + +// +//========================================================== + +// app_usbd_msc - USB MSC class + +//========================================================== +// APP_USBD_CLASS_MSC_ENABLED - Enabling USBD MSC Class library + + +#ifndef APP_USBD_CLASS_MSC_ENABLED +#define APP_USBD_CLASS_MSC_ENABLED 0 +#endif + +// APP_USBD_MSC_CLASS_LOG_ENABLED - Enables logging in the module. + + +#ifndef APP_USBD_MSC_CLASS_LOG_ENABLED +#define APP_USBD_MSC_CLASS_LOG_ENABLED 0 +#endif + +// +//========================================================== + +// +//========================================================== + +// nRF_Log + +//========================================================== +// NRF_LOG_ENABLED - nrf_log - Logging +//========================================================== +#ifndef NRF_LOG_ENABLED +#define NRF_LOG_ENABLED 0 +#endif +#if NRF_LOG_ENABLED +// NRF_LOG_USES_COLORS - If enabled then ANSI escape code for colors is prefixed to every string +//========================================================== +#ifndef NRF_LOG_USES_COLORS +#define NRF_LOG_USES_COLORS 0 +#endif +#if NRF_LOG_USES_COLORS +// NRF_LOG_COLOR_DEFAULT - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_COLOR_DEFAULT +#define NRF_LOG_COLOR_DEFAULT 0 +#endif + +// NRF_LOG_ERROR_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_ERROR_COLOR +#define NRF_LOG_ERROR_COLOR 0 +#endif + +// NRF_LOG_WARNING_COLOR - ANSI escape code prefix. + +// <0=> Default +// <1=> Black +// <2=> Red +// <3=> Green +// <4=> Yellow +// <5=> Blue +// <6=> Magenta +// <7=> Cyan +// <8=> White + +#ifndef NRF_LOG_WARNING_COLOR +#define NRF_LOG_WARNING_COLOR 0 +#endif + +#endif //NRF_LOG_USES_COLORS +// + +// NRF_LOG_DEFAULT_LEVEL - Default Severity level + +// <0=> Off +// <1=> Error +// <2=> Warning +// <3=> Info +// <4=> Debug + +#ifndef NRF_LOG_DEFAULT_LEVEL +#define NRF_LOG_DEFAULT_LEVEL 3 +#endif + +// NRF_LOG_DEFERRED - Enable deffered logger. + +// Log data is buffered and can be processed in idle. +//========================================================== +#ifndef NRF_LOG_DEFERRED +#define NRF_LOG_DEFERRED 1 +#endif +#if NRF_LOG_DEFERRED +// NRF_LOG_DEFERRED_BUFSIZE - Size of the buffer for logs in words. +// Must be power of 2 + +#ifndef NRF_LOG_DEFERRED_BUFSIZE +#define NRF_LOG_DEFERRED_BUFSIZE 256 +#endif + +#endif //NRF_LOG_DEFERRED +// + +// NRF_LOG_USES_TIMESTAMP - Enable timestamping + + +// Function for getting the timestamp is provided by the user + +#ifndef NRF_LOG_USES_TIMESTAMP +#define NRF_LOG_USES_TIMESTAMP 0 +#endif + +#endif //NRF_LOG_ENABLED +// + +// nrf_log_backend - Logging sink + +//========================================================== +// NRF_LOG_BACKEND_MAX_STRING_LENGTH - Buffer for storing single output string +// Logger backend RAM usage is determined by this value. + +#ifndef NRF_LOG_BACKEND_MAX_STRING_LENGTH +#define NRF_LOG_BACKEND_MAX_STRING_LENGTH 256 +#endif + +// NRF_LOG_TIMESTAMP_DIGITS - Number of digits for timestamp +// If higher resolution timestamp source is used it might be needed to increase that + +#ifndef NRF_LOG_TIMESTAMP_DIGITS +#define NRF_LOG_TIMESTAMP_DIGITS 8 +#endif + +// NRF_LOG_BACKEND_SERIAL_USES_UART - If enabled data is printed over UART +//========================================================== +#ifndef NRF_LOG_BACKEND_SERIAL_USES_UART +#define NRF_LOG_BACKEND_SERIAL_USES_UART 1 +#endif +#if NRF_LOG_BACKEND_SERIAL_USES_UART +// NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE - Default Baudrate + +// <323584=> 1200 baud +// <643072=> 2400 baud +// <1290240=> 4800 baud +// <2576384=> 9600 baud +// <3862528=> 14400 baud +// <5152768=> 19200 baud +// <7716864=> 28800 baud +// <10289152=> 38400 baud +// <15400960=> 57600 baud +// <20615168=> 76800 baud +// <30924800=> 115200 baud +// <61865984=> 230400 baud +// <67108864=> 250000 baud +// <121634816=> 460800 baud +// <251658240=> 921600 baud +// <268435456=> 57600 baud + +#ifndef NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE +#define NRF_LOG_BACKEND_SERIAL_UART_BAUDRATE 30924800 +#endif + +// NRF_LOG_BACKEND_SERIAL_UART_TX_PIN - UART TX pin +#ifndef NRF_LOG_BACKEND_SERIAL_UART_TX_PIN +#define NRF_LOG_BACKEND_SERIAL_UART_TX_PIN 9 +#endif + +// NRF_LOG_BACKEND_SERIAL_UART_RX_PIN - UART RX pin +#ifndef NRF_LOG_BACKEND_SERIAL_UART_RX_PIN +#define NRF_LOG_BACKEND_SERIAL_UART_RX_PIN 11 +#endif + +// NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN - UART RTS pin +#ifndef NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN +#define NRF_LOG_BACKEND_SERIAL_UART_RTS_PIN 8 +#endif + +// NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN - UART CTS pin +#ifndef NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN +#define NRF_LOG_BACKEND_SERIAL_UART_CTS_PIN 10 +#endif + +// NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL - Hardware Flow Control + +// <0=> Disabled +// <1=> Enabled + +#ifndef NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL +#define NRF_LOG_BACKEND_SERIAL_UART_FLOW_CONTROL 0 +#endif + +// NRF_LOG_BACKEND_UART_INSTANCE - UART instance used + +// <0=> 0 + +#ifndef NRF_LOG_BACKEND_UART_INSTANCE +#define NRF_LOG_BACKEND_UART_INSTANCE 0 +#endif + +#endif //NRF_LOG_BACKEND_SERIAL_USES_UART +// + +// NRF_LOG_BACKEND_SERIAL_USES_RTT - If enabled data is printed using RTT +//========================================================== +#ifndef NRF_LOG_BACKEND_SERIAL_USES_RTT +#define NRF_LOG_BACKEND_SERIAL_USES_RTT 0 +#endif +#if NRF_LOG_BACKEND_SERIAL_USES_RTT +// NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE - RTT output buffer size. +// Should be equal or bigger than \ref NRF_LOG_BACKEND_MAX_STRING_LENGTH. +// This value is used in Segger RTT configuration to set the buffer size +// if it is bigger than default RTT buffer size. + +#ifndef NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE +#define NRF_LOG_BACKEND_RTT_OUTPUT_BUFFER_SIZE 512 +#endif + +#endif //NRF_LOG_BACKEND_SERIAL_USES_RTT +// + +// +//========================================================== + +// +//========================================================== + +// nRF_Segger_RTT + +//========================================================== +// segger_rtt - SEGGER RTT + +//========================================================== +// SEGGER_RTT_CONFIG_BUFFER_SIZE_UP - Size of upstream buffer. +#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_UP +#define SEGGER_RTT_CONFIG_BUFFER_SIZE_UP 64 +#endif + +// SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS - Size of upstream buffer. +#ifndef SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS +#define SEGGER_RTT_CONFIG_MAX_NUM_UP_BUFFERS 2 +#endif + +// SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN - Size of upstream buffer. +#ifndef SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN +#define SEGGER_RTT_CONFIG_BUFFER_SIZE_DOWN 16 +#endif + +// SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS - Size of upstream buffer. +#ifndef SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS +#define SEGGER_RTT_CONFIG_MAX_NUM_DOWN_BUFFERS 2 +#endif + +// +//========================================================== + +// +//========================================================== +**************/ +// <<< end of configuration section >>> +#endif //SDK_CONFIG_H diff --git a/cores/nRF5/utility/sdk_errors.c b/cores/nRF5/utility/sdk_errors.c new file mode 100644 index 00000000..8f7031dc --- /dev/null +++ b/cores/nRF5/utility/sdk_errors.c @@ -0,0 +1,91 @@ +/** + * Copyright (c) 2016 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sdk_errors.h" +#include "nordic_common.h" + +#if defined(NRF_LOG_ENABLED) && NRF_LOG_ENABLED +/** + * @defgroup err_strings Arrays with error codes as strings. + * @{ + */ +const char * m_sdk_errors_name[ERR_NAMES_SIZE] = +{ + "NRF_SUCCESS", + "NRF_ERROR_SVC_HANDLER_MISSING", + "NRF_ERROR_SOFTDEVICE_NOT_ENABLED", + "NRF_ERROR_INTERNAL", + "NRF_ERROR_NO_MEM", + "NRF_ERROR_NOT_FOUND", + "NRF_ERROR_NOT_SUPPORTED", + "NRF_ERROR_INVALID_PARAM", + "NRF_ERROR_INVALID_STATE", + "NRF_ERROR_INVALID_LENGTH", + "NRF_ERROR_INVALID_FLAGS", + "NRF_ERROR_INVALID_DATA", + "NRF_ERROR_DATA_SIZE", + "NRF_ERROR_TIMEOUT", + "NRF_ERROR_NULL", + "NRF_ERROR_FORBIDDEN", + "NRF_ERROR_INVALID_ADDR", + "NRF_ERROR_BUSY" +}; + +const char * m_sdk_errors_name_common[ERR_NAMES_COMMON_SIZE] = +{ + "NRF_ERROR_MODULE_NOT_INITIALZED", + "NRF_ERROR_MUTEX_INIT_FAILED", + "NRF_ERROR_MUTEX_LOCK_FAILED", + "NRF_ERROR_MUTEX_UNLOCK_FAILED", + "NRF_ERROR_MUTEX_COND_INIT_FAILED", + "NRF_ERROR_MODULE_ALREADY_INITIALIZED", + "NRF_ERROR_STORAGE_FULL", + "NRF_ERROR_API_NOT_IMPLEMENTED", + "NRF_ERROR_FEATURE_NOT_ENABLED" +}; + +const char * m_sdk_errors_name_twi[ERR_NAMES_TWI_SIZE] = +{ + "NRF_ERROR_DRV_TWI_ERR_OVERRUN", + "NRF_ERROR_DRV_TWI_ERR_ANACK", + "NRF_ERROR_DRV_TWI_ERR_DNACK" +}; +/* @} */ +#endif // NRF_LOG_ENABLED diff --git a/cores/nRF5/utility/sdk_errors.h b/cores/nRF5/utility/sdk_errors.h new file mode 100644 index 00000000..2466a48d --- /dev/null +++ b/cores/nRF5/utility/sdk_errors.h @@ -0,0 +1,181 @@ +/** + * Copyright (c) 2013 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/**@file + * + * @defgroup sdk_error SDK Error codes + * @{ + * @ingroup app_common + * @{ + * @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for + * identifying the module where the error occurred while the least least significant LSB + * are used to provide the cause or nature of error. Each module is assigned a 16-bit + * unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit + * LSB range is with module id as the MSB in the 32-bit error code is reserved for the + * module. As an example, if 0x8800 identifies a certain SDK module, all values from + * 0x88000000 - 0x8800FFFF are reserved for this module. + * It should be noted that common error reasons have been assigned values to make it + * possible to decode error reason easily. As an example, lets module uninitialized has + * been assigned an error code 0x000A0. Then, if application encounters an error code + * 0xZZZZ00A0, it knows that it accessing a certain module without initializing it. + * Apart from this, each module is allowed to define error codes that are not covered by + * the common ones, however, these values are defined in a range that does not conflict + * with common error values. For module, specific error however, it is possible that the + * same error value is used by two different modules to indicated errors of very different + * nature. If error is already defined by the NRF common error codes, these are reused. + * A range is reserved for application as well, it can use this range for defining + * application specific errors. + * + * @note Success code, NRF_SUCCESS, does not include any module identifier. + + */ + +#ifndef SDK_ERRORS_H__ +#define SDK_ERRORS_H__ + +#include +#include "nrf_error.h" +#include "sdk_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup sdk_err_base Base defined for SDK Modules + * @{ + */ +#define NRF_ERROR_SDK_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x8000) /**< Base value defined for SDK module identifiers. */ +#define NRF_ERROR_SDK_COMMON_ERROR_BASE (NRF_ERROR_BASE_NUM + 0x0080) /**< Base error value to be used for SDK error values. */ +/* @} */ + +/** + * @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred. + * @{ + */ +#define NRF_ERROR_MEMORY_MANAGER_ERR_BASE (0x8100) +#define NRF_ERROR_PERIPH_DRIVERS_ERR_BASE (0x8200) +#define NRF_ERROR_GAZELLE_ERR_BASE (0x8300) +/* @} */ + + +/** + * @defgroup sdk_iot_errors Codes reserved as identification for IoT errors. + * @{ + */ +#define NRF_ERROR_IOT_ERR_BASE_START (0xA000) +#define NRF_ERROR_IOT_ERR_BASE_STOP (0xAFFF) +/* @} */ + + +/** + * @defgroup sdk_common_errors Codes reserved as identification for common errors. + * @{ + */ +#define NRF_ERROR_MODULE_NOT_INITIALZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0000) +#define NRF_ERROR_MUTEX_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0001) +#define NRF_ERROR_MUTEX_LOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0002) +#define NRF_ERROR_MUTEX_UNLOCK_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0003) +#define NRF_ERROR_MUTEX_COND_INIT_FAILED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0004) +#define NRF_ERROR_MODULE_ALREADY_INITIALIZED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0005) +#define NRF_ERROR_STORAGE_FULL (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0006) +#define NRF_ERROR_API_NOT_IMPLEMENTED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0010) +#define NRF_ERROR_FEATURE_NOT_ENABLED (NRF_ERROR_SDK_COMMON_ERROR_BASE + 0x0011) +/* @} */ + + +/** + * @defgroup drv_specific_errors Error / status codes specific to drivers. + * @{ + */ +#define NRF_ERROR_DRV_TWI_ERR_OVERRUN (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0000) +#define NRF_ERROR_DRV_TWI_ERR_ANACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0001) +#define NRF_ERROR_DRV_TWI_ERR_DNACK (NRF_ERROR_PERIPH_DRIVERS_ERR_BASE + 0x0002) +/* @} */ + +/** + * @brief API Result. + * + * @details Indicates success or failure of an API procedure. In case of failure, a comprehensive + * error code indicating cause or reason for failure is provided. + * + * Though called an API result, it could used in Asynchronous notifications callback along + * with asynchronous callback as event result. This mechanism is employed when an event + * marks the end of procedure initiated using API. API result, in this case, will only be + * an indicative of whether the procedure has been requested successfully. + */ +typedef uint32_t ret_code_t; + +#if defined(NRF_LOG_ENABLED) && NRF_LOG_ENABLED +/** + * @defgroup err_sizes Sizes of error code arrays. + * @{ + */ +#define ERR_NAMES_SIZE 18 +#define ERR_NAMES_COMMON_SIZE 9 +#define ERR_NAMES_TWI_SIZE 3 +/* @} */ + +extern const char * m_sdk_errors_name[ERR_NAMES_SIZE]; +extern const char * m_sdk_errors_name_common[ERR_NAMES_COMMON_SIZE]; +extern const char * m_sdk_errors_name_twi[ERR_NAMES_TWI_SIZE]; + +/** + * @defgroup err_to_string Macros for converting error codes to strings. + * @{ + */ +#define ERR_TO_STR(err_code) m_sdk_errors_name[err_code] +#define ERR_TO_STR_COMMON(err_code) m_sdk_errors_name_common[err_code - NRF_ERROR_SDK_COMMON_ERROR_BASE] +#define ERR_TO_STR_TWI(err_code) m_sdk_errors_name_twi[err_code - NRF_ERROR_PERIPH_DRIVERS_ERR_BASE] +#else +#define ERR_TO_STR(err_code) "" +#define ERR_TO_STR_COMMON(err_code) "" +#define ERR_TO_STR_TWI(err_code) "" +#endif // NRF_LOG_ENABLED + +/* @} */ +/** @} */ +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_ERRORS_H__ diff --git a/cores/nRF5/utility/sdk_macros.h b/cores/nRF5/utility/sdk_macros.h new file mode 100644 index 00000000..e228e713 --- /dev/null +++ b/cores/nRF5/utility/sdk_macros.h @@ -0,0 +1,192 @@ +/** + * Copyright (c) 2013 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/**@file + * + + * @defgroup sdk_common_macros SDK Common Header + * @ingroup app_common + * @brief Macros for parameter checking and similar tasks + * @{ + */ + +#ifndef SDK_MACROS_H__ +#define SDK_MACROS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/**@brief Macro for verifying statement to be true. It will cause the exterior function to return + * err_code if the statement is not true. + * + * @param[in] statement Statement to test. + * @param[in] err_code Error value to return if test was invalid. + * + * @retval nothing, but will cause the exterior function to return @p err_code if @p statement + * is false. + */ +#define VERIFY_TRUE(statement, err_code) \ +do \ +{ \ + if (!(statement)) \ + { \ + return err_code; \ + } \ +} while (0) + + +/**@brief Macro for verifying statement to be true. It will cause the exterior function to return + * if the statement is not true. + * + * @param[in] statement Statement to test. + */ +#define VERIFY_TRUE_VOID(statement) VERIFY_TRUE((statement), ) + + +/**@brief Macro for verifying statement to be false. It will cause the exterior function to return + * err_code if the statement is not false. + * + * @param[in] statement Statement to test. + * @param[in] err_code Error value to return if test was invalid. + * + * @retval nothing, but will cause the exterior function to return @p err_code if @p statement + * is true. + */ +#define VERIFY_FALSE(statement, err_code) \ +do \ +{ \ + if ((statement)) \ + { \ + return err_code; \ + } \ +} while (0) + + +/**@brief Macro for verifying statement to be false. It will cause the exterior function to return + * if the statement is not false. + * + * @param[in] statement Statement to test. + */ +#define VERIFY_FALSE_VOID(statement) VERIFY_FALSE((statement), ) + + +/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior + * function to return err_code if the err_code is not @ref NRF_SUCCESS. + * + * @param[in] err_code The error code to check. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_SUCCESS() +#else +#define VERIFY_SUCCESS(err_code) VERIFY_TRUE((err_code) == NRF_SUCCESS, (err_code)) +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that a function returned NRF_SUCCESS. It will cause the exterior + * function to return if the err_code is not @ref NRF_SUCCESS. + * + * @param[in] err_code The error code to check. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_SUCCESS_VOID() +#else +#define VERIFY_SUCCESS_VOID(err_code) VERIFY_TRUE_VOID((err_code) == NRF_SUCCESS) +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return @ref NRF_ERROR_INVALID_STATE if not. + * + * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED + * should be true if the module is initialized, false if not. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_MODULE_INITIALIZED() +#else +#define VERIFY_MODULE_INITIALIZED() VERIFY_TRUE((MODULE_INITIALIZED), NRF_ERROR_INVALID_STATE) +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return if not. + * + * @note MODULE_INITIALIZED must be defined in each module using this macro. MODULE_INITIALIZED + * should be true if the module is initialized, false if not. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_MODULE_INITIALIZED_VOID() +#else +#define VERIFY_MODULE_INITIALIZED_VOID() VERIFY_TRUE_VOID((MODULE_INITIALIZED)) +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return if not. + * + * @param[in] param The variable to check if is NULL. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_PARAM_NOT_NULL() +#else +#define VERIFY_PARAM_NOT_NULL(param) VERIFY_FALSE(((param) == NULL), NRF_ERROR_NULL) +#endif /* DISABLE_PARAM_CHECK */ + + +/**@brief Macro for verifying that the module is initialized. It will cause the exterior function to + * return if not. + * + * @param[in] param The variable to check if is NULL. + */ +#ifdef DISABLE_PARAM_CHECK +#define VERIFY_PARAM_NOT_NULL_VOID() +#else +#define VERIFY_PARAM_NOT_NULL_VOID(param) VERIFY_FALSE_VOID(((param) == NULL)) +#endif /* DISABLE_PARAM_CHECK */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_MACROS_H__ + diff --git a/cores/nRF5/utility/sdk_os.h b/cores/nRF5/utility/sdk_os.h new file mode 100644 index 00000000..903aaf77 --- /dev/null +++ b/cores/nRF5/utility/sdk_os.h @@ -0,0 +1,76 @@ +/** + * Copyright (c) 2013 - 2017, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + + /** @cond */ +/**@file + * + * @defgroup sdk_os SDK OS Abstraction + * @ingroup experimental_api + * @details In order to made SDK modules independent of use of an embedded OS, and permit + * application with varied task architecture, SDK abstracts the OS specific + * elements here in order to make all other modules agnostic to the OS or task + * architecture. + * @{ + */ + +#ifndef SDK_OS_H__ +#define SDK_OS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define SDK_MUTEX_DEFINE(X) +#define SDK_MUTEX_INIT(X) +#define SDK_MUTEX_LOCK(X) +#define SDK_MUTEX_UNLOCK(X) + +/** + * @defgroup os_data_type Data types. + */ + +/** @} */ +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif // SDK_OS_H__ diff --git a/cores/nRF5/wiring.c b/cores/nRF5/wiring.c index b9be09b2..9bad2b7f 100644 --- a/cores/nRF5/wiring.c +++ b/cores/nRF5/wiring.c @@ -25,12 +25,14 @@ extern "C" { #endif -void init( void ) -{ - NVIC_SetPriority(RTC1_IRQn, 15); - NVIC_ClearPendingIRQ(RTC1_IRQn); - NVIC_EnableIRQ(RTC1_IRQn); - +void init( void ) { +/** Rev 3 moved millis() to RTC1 with lp_timer + NVIC_SetPriority(RTC2_IRQn, 15); + NVIC_ClearPendingIRQ(RTC2_IRQn); + NVIC_EnableIRQ(RTC2_IRQn); +**/ +/** + Rev 8 start clock when starting softdevice #if defined(USE_LFXO) NRF_CLOCK->LFCLKSRC = (uint32_t)((CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); #elif defined(USE_LFSYNT) @@ -38,27 +40,20 @@ void init( void ) #else //USE_LFRC NRF_CLOCK->LFCLKSRC = (uint32_t)((CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk); #endif - NRF_CLOCK->TASKS_LFCLKSTART = 1UL; - - NRF_RTC1->PRESCALER = 0; - NRF_RTC1->INTENSET = RTC_INTENSET_OVRFLW_Msk; - NRF_RTC1->EVTENSET = RTC_EVTEN_OVRFLW_Msk; - NRF_RTC1->TASKS_START = 1; - #if defined(RESET_PIN) - if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) || - ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){ - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[0] = RESET_PIN; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_UICR->PSELRESET[1] = RESET_PIN; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - } - #endif + NRF_CLOCK->TASKS_LFCLKSTART = 1UL; +**/ +/** Rev 3 moved millis() to RTC1 with lp_timer + NRF_RTC2->PRESCALER = 0; + NRF_RTC2->INTENSET = RTC_INTENSET_OVRFLW_Msk; + NRF_RTC2->EVTENSET = RTC_EVTEN_OVRFLW_Msk; + NRF_RTC2->TASKS_START = 1; + **/ + + /** No Reset Pin. This define did not work for me. Needs extra linker script like NFC-GPIO pins? + Reset pin code is in system_nrf52.c and needs the define -DCONFIG_GPIO_AS_PINRESET added to the + xxx.menu.softdevice.s132.build.extra_flags in boards.txt for the particular board + **/ } #ifdef __cplusplus diff --git a/cores/nRF5/wiring_analog.h b/cores/nRF5/wiring_analog.h index f183b57a..7708b7a1 100644 --- a/cores/nRF5/wiring_analog.h +++ b/cores/nRF5/wiring_analog.h @@ -25,12 +25,10 @@ extern "C" { #endif -#include "nrf.h" - /* * \brief nRF51 and nRF52 have different reference options. */ -#if defined(NRF52_SERIES) +#ifdef NRF52 typedef enum _eAnalogReference { AR_DEFAULT, diff --git a/cores/nRF5/wiring_analog_nRF51.c b/cores/nRF5/wiring_analog_nRF51.c index bd9e7c93..f22a8b5d 100644 --- a/cores/nRF5/wiring_analog_nRF51.c +++ b/cores/nRF5/wiring_analog_nRF51.c @@ -17,11 +17,13 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifdef NRF51 + +#include "nrf.h" + #include "Arduino.h" #include "wiring_private.h" -#if defined(NRF51_SERIES) - #ifdef __cplusplus extern "C" { #endif diff --git a/cores/nRF5/wiring_analog_nRF52.c b/cores/nRF5/wiring_analog_nRF52.c index e7db64a5..a5bc0ef5 100644 --- a/cores/nRF5/wiring_analog_nRF52.c +++ b/cores/nRF5/wiring_analog_nRF52.c @@ -1,3 +1,7 @@ +// modified by Matthew Ford +// (c)2022 Forward Computing and Control Pty. Ltd, NSW, Australia +// changed SAADC_CH_CONFIG_TACQ_3us to SAADC_CH_CONFIG_TACQ_10us to match lp_ADC settings + /* Copyright (c) 2014 Arduino LLC. All right reserved. Copyright (c) 2016 Sandeep Mistry All right reserved. @@ -17,43 +21,55 @@ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifdef NRF52 + +#include "nrf.h" + #include "Arduino.h" #include "wiring_private.h" -#if defined(NRF52_SERIES) - #ifdef __cplusplus extern "C" { #endif -static uint32_t saadcReference = SAADC_CH_CONFIG_REFSEL_Internal; -static uint32_t saadcGain = SAADC_CH_CONFIG_GAIN_Gain1_5; +uint32_t saadcReference = SAADC_CH_CONFIG_REFSEL_Internal; +uint32_t saadcGain = SAADC_CH_CONFIG_GAIN_Gain1_5; + +unsigned long adc_settling_time = SAADC_CH_CONFIG_TACQ_10us; // < 10 us good for <100K source resisance. +// i.e. a less than 200K + less than 200K voltage divider connected to the ADC pin +// The calculated source resistance == the value of two resistors if they were connected in parallel. + +/** choice depends on the source resistance and are +SAADC_CH_CONFIG_TACQ_3us (0UL) < 3 us for < 10K +SAADC_CH_CONFIG_TACQ_5us (1UL) < 5 us for < 40K +SAADC_CH_CONFIG_TACQ_10us (2UL) < 10 us for <100K +SAADC_CH_CONFIG_TACQ_15us (3UL) < 15 us for <200K +SAADC_CH_CONFIG_TACQ_20us (4UL) < 20 us for <400K +SAADC_CH_CONFIG_TACQ_40us (5UL) < 40 us for <800K +*/ + + +#define PWM_COUNT 3 static NRF_PWM_Type* pwms[PWM_COUNT] = { NRF_PWM0, NRF_PWM1, - NRF_PWM2, -#if PWM_COUNT > 3 - NRF_PWM3 -#endif + NRF_PWM2 }; static uint32_t pwmChannelPins[PWM_COUNT] = { 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, -#if PWM_COUNT > 3 - 0xFFFFFFFF, -#endif + 0xFFFFFFFF }; static uint16_t pwmChannelSequence[PWM_COUNT]; -static int readResolution = 10; +int ADC_readResolution = 10; static int writeResolution = 8; void analogReadResolution( int res ) { - readResolution = res; + ADC_readResolution = res; } void analogWriteResolution( int res ) @@ -151,13 +167,13 @@ uint32_t analogRead( uint32_t ulPin ) return 0; } - if (readResolution <= 8) { + if (ADC_readResolution <= 8) { resolution = 8; saadcResolution = SAADC_RESOLUTION_VAL_8bit; - } else if (readResolution <= 10) { + } else if (ADC_readResolution <= 10) { resolution = 10; saadcResolution = SAADC_RESOLUTION_VAL_10bit; - } else if (readResolution <= 12) { + } else if (ADC_readResolution <= 12) { resolution = 12; saadcResolution = SAADC_RESOLUTION_VAL_12bit; } else { @@ -176,7 +192,7 @@ uint32_t analogRead( uint32_t ulPin ) | ((SAADC_CH_CONFIG_RESP_Bypass << SAADC_CH_CONFIG_RESN_Pos) & SAADC_CH_CONFIG_RESN_Msk) | ((saadcGain << SAADC_CH_CONFIG_GAIN_Pos) & SAADC_CH_CONFIG_GAIN_Msk) | ((saadcReference << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk) - | ((SAADC_CH_CONFIG_TACQ_3us << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) + | ((adc_settling_time << SAADC_CH_CONFIG_TACQ_Pos) & SAADC_CH_CONFIG_TACQ_Msk) | ((SAADC_CH_CONFIG_MODE_SE << SAADC_CH_CONFIG_MODE_Pos) & SAADC_CH_CONFIG_MODE_Msk); NRF_SAADC->CH[0].PSELN = pin; NRF_SAADC->CH[0].PSELP = pin; @@ -206,7 +222,7 @@ uint32_t analogRead( uint32_t ulPin ) NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos); - return mapResolution(value, resolution, readResolution); + return mapResolution(value, resolution, ADC_readResolution); } // Right now, PWM output only works on the pins with diff --git a/cores/nRF5/wiring_constants.h b/cores/nRF5/wiring_constants.h index e8573aed..0e8970e3 100644 --- a/cores/nRF5/wiring_constants.h +++ b/cores/nRF5/wiring_constants.h @@ -31,6 +31,27 @@ extern "C"{ #define INPUT_PULLUP (0x2) #define INPUT_PULLDOWN (0x3) +/*** from nrf52_bitfields.h +#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) //!< Standard '0', standard '1' +#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) //!< High drive '0', standard '1' +#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) //!< Standard '0', high drive '1' +#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) //!< High drive '0', high 'drive '1'' +#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) //!< Disconnect '0' standard '1' (normally used for wired-or connections) +#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) //!< Disconnect '0', high drive '1' (normally used for wired-or connections) +#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) //!< Standard '0'. disconnect '1' (normally used for wired-and connections) +#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) //!< High drive '0', disconnect '1' (normally used for wired-and connections) +*********************/ + +// The default OUTPUT is SOS1 +#define OUTPUT_S0S1 (0x10+0x0) +#define OUTPUT_H0S1 (0x10+0x1) +#define OUTPUT_S0H1 (0x10+0x2) +#define OUTPUT_H0H1 (0x10+0x3) +#define OUTPUT_D0S1 (0x10+0x4) +#define OUTPUT_D0H1 (0x10+0x5) +#define OUTPUT_S0D1 (0x10+0x6) +#define OUTPUT_H0D1 (0x10+0x7) + #define PI 3.1415926535897932384626433832795 #define HALF_PI 1.5707963267948966192313216916398 #define TWO_PI 6.283185307179586476925286766559 diff --git a/cores/nRF5/wiring_digital.c b/cores/nRF5/wiring_digital.c index 2cf92565..d78a6ea9 100644 --- a/cores/nRF5/wiring_digital.c +++ b/cores/nRF5/wiring_digital.c @@ -31,49 +31,57 @@ void pinMode( uint32_t ulPin, uint32_t ulMode ) return; } - NRF_GPIO_Type* port = digitalPinToPort(ulPin); - uint32_t pin = digitalPinToPin(ulPin); + ulPin = g_ADigitalPinMap[ulPin]; // Set pin mode according to chapter '22.6.3 I/O Pin Configuration' switch ( ulMode ) { case INPUT: // Set pin to input mode - port->PIN_CNF[pin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_GPIO->PIN_CNF[ulPin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); break ; case INPUT_PULLUP: // Set pin to input mode with pull-up resistor enabled - port->PIN_CNF[pin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_GPIO->PIN_CNF[ulPin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); break ; case INPUT_PULLDOWN: // Set pin to input mode with pull-down resistor enabled - port->PIN_CNF[pin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_GPIO->PIN_CNF[ulPin] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Pulldown << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); break ; case OUTPUT: // Set pin to output mode - port->PIN_CNF[pin] = ((uint32_t)GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_GPIO->PIN_CNF[ulPin] = ((uint32_t)GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); break ; default: + if ((ulMode >= OUTPUT_S0S1) && (ulMode <= OUTPUT_H0D1)) { + uint32_t drive = ulMode - OUTPUT_S0S1; + // Set pin to output mode with specified drive + NRF_GPIO->PIN_CNF[ulPin] = ((uint32_t)GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + } // else // do nothing break ; } @@ -85,17 +93,16 @@ void digitalWrite( uint32_t ulPin, uint32_t ulVal ) return; } - NRF_GPIO_Type* port = digitalPinToPort(ulPin); - uint32_t mask = digitalPinToBitMask(ulPin); + ulPin = g_ADigitalPinMap[ulPin]; switch ( ulVal ) { case LOW: - port->OUTCLR = mask; + NRF_GPIO->OUTCLR = (1UL << ulPin); break ; default: - port->OUTSET = mask; + NRF_GPIO->OUTSET = (1UL << ulPin); break ; } @@ -108,10 +115,9 @@ int digitalRead( uint32_t ulPin ) return 0; } - NRF_GPIO_Type* port = digitalPinToPort(ulPin); - uint32_t pin = digitalPinToPin(ulPin); + ulPin = g_ADigitalPinMap[ulPin]; - return ((port->IN >> pin) & 1UL) ? HIGH : LOW ; + return ((NRF_GPIO->IN >> ulPin) & 1UL) ? HIGH : LOW ; } #ifdef __cplusplus diff --git a/cores/nRF5/wiring_digital.h b/cores/nRF5/wiring_digital.h index 27b46a6b..11e6ab5b 100644 --- a/cores/nRF5/wiring_digital.h +++ b/cores/nRF5/wiring_digital.h @@ -27,9 +27,22 @@ /** * \brief Configures the specified pin to behave either as an input or an output. See the description of digital pins for details. + * For nRF52 extra modes are available. + * Standard drive is typically 2mA (min 1mA) '0' sink (low) or '1' source (high). High drive (VDD > 2.7V) is typically 10mA low, 9mA high (min 6mA) + * + * OUTPUT_S0S1 Standard '0', standard '1' same as OUTPUT + * OUTPUT_H0S1 High drive '0', standard '1' + * OUTPUT_S0H1 Standard '0', high drive '1' + * OUTPUT_H0H1 High drive '0', high 'drive '1'' + * OUTPUT_D0S1 Disconnect '0' standard '1' (normally used for wired-or connections) + * OUTPUT_D0H1 Disconnect '0', high drive '1' (normally used for wired-or connections) + * OUTPUT_S0D1 Standard '0'. disconnect '1' (normally used for wired-and connections) + * OUTPUT_H0D1 High drive '0', disconnect '1' (normally used for wired-and connections) + * NOTE P0.27 should be only low (standard) drive, low frequency * * \param ulPin The number of the pin whose mode you wish to set * \param ulMode Can be INPUT, OUTPUT, INPUT_PULLUP or INPUT_PULLDOWN + * or OUTPUT_S0S1, OUTPUT_H0S1, OUTPUT_S0H1, OUTPUT_H1H1, OUTPUT_D0S1, OUTPUT_D0H1, OUTPUT_S0D1, OUTPUT_H0D1 */ extern void pinMode( uint32_t dwPin, uint32_t dwMode ) ; diff --git a/extras/ide-tools/readme.txt b/extras/ide-tools/readme.txt new file mode 100644 index 00000000..8ceb6fa6 --- /dev/null +++ b/extras/ide-tools/readme.txt @@ -0,0 +1,9 @@ +nRF5FlashSoftDevice.jar is the compiled version of nRF5FlashSoftDevice.java + +Install nRF5FlashSoftDevice.jar in + +\tools\nRF5FlashSoftDevice\tool dir i.e. + +\tools\nRF5FlashSoftDevice\tool\nRF5FlashSoftDevice.jar + +and restart the IDE \ No newline at end of file diff --git a/libraries/SPI/SPI.cpp b/libraries/SPI/SPI.cpp index d803c953..5c3add1b 100644 --- a/libraries/SPI/SPI.cpp +++ b/libraries/SPI/SPI.cpp @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include - #include "SPI.h" #include #include @@ -256,13 +254,8 @@ void SPIClass::detachInterrupt() { } #if SPI_INTERFACES_COUNT > 0 -#if defined(NRF52_SERIES) -SPIClass SPI (NRF_SPI2, PIN_SPI_MISO, PIN_SPI_SCK, PIN_SPI_MOSI); -#else SPIClass SPI (NRF_SPI0, PIN_SPI_MISO, PIN_SPI_SCK, PIN_SPI_MOSI); #endif -#endif - #if SPI_INTERFACES_COUNT > 1 SPIClass SPI1(NRF_SPI1, PIN_SPI1_MISO, PIN_SPI1_SCK, PIN_SPI1_MOSI); #endif diff --git a/libraries/SPI/SPI.h b/libraries/SPI/SPI.h index 259571a2..42f8aff8 100644 --- a/libraries/SPI/SPI.h +++ b/libraries/SPI/SPI.h @@ -145,15 +145,14 @@ extern SPIClass SPI1; // For compatibility with sketches designed for AVR @ 16 MHz // New programs should use SPI.beginTransaction to set the SPI clock -#ifdef F_CPU -#define DIVISOR F_CPU / 16000000 -#define SPI_CLOCK_DIV2 2 * DIVISOR -#define SPI_CLOCK_DIV4 4 * DIVISOR -#define SPI_CLOCK_DIV8 8 * DIVISOR -#define SPI_CLOCK_DIV16 16 * DIVISOR -#define SPI_CLOCK_DIV32 32 * DIVISOR -#define SPI_CLOCK_DIV64 64 * DIVISOR -#define SPI_CLOCK_DIV128 128 * DIVISOR +#if F_CPU == 16000000 + #define SPI_CLOCK_DIV2 2 + #define SPI_CLOCK_DIV4 4 + #define SPI_CLOCK_DIV8 8 + #define SPI_CLOCK_DIV16 16 + #define SPI_CLOCK_DIV32 32 + #define SPI_CLOCK_DIV64 64 + #define SPI_CLOCK_DIV128 128 #endif -#endif \ No newline at end of file +#endif diff --git a/libraries/Wire/Wire.h b/libraries/Wire/Wire.h index 56e4ab29..356bbf12 100755 --- a/libraries/Wire/Wire.h +++ b/libraries/Wire/Wire.h @@ -34,16 +34,17 @@ class TwoWire : public Stream { public: -#if defined(NRF52_SERIES) +#ifdef NRF52 TwoWire(NRF_TWIM_Type * p_twim, NRF_TWIS_Type * p_twis, IRQn_Type IRQn, uint8_t pinSDA, uint8_t pinSCL); -#else - TwoWire(NRF_TWI_Type * p_twi, uint8_t pinSDA, uint8_t pinSCL); -#endif #ifdef ARDUINO_GENERIC void setPins(uint8_t pinSDA, uint8_t pinSCL); #endif // ARDUINO_GENERIC + +#else + TwoWire(NRF_TWI_Type * p_twi, uint8_t pinSDA, uint8_t pinSCL); +#endif void begin(); -#if defined(NRF52_SERIES) +#ifdef NRF52 void begin(uint8_t); #endif void end(); @@ -63,7 +64,7 @@ class TwoWire : public Stream virtual int read(void); virtual int peek(void); virtual void flush(void); -#if defined(NRF52_SERIES) +#ifdef NRF52 void onReceive(void(*)(int)); void onRequest(void(*)(void)); void onService(void); @@ -72,7 +73,7 @@ class TwoWire : public Stream using Print::write; private: -#if defined(NRF52_SERIES) +#ifdef NRF52 NRF_TWIM_Type * _p_twim; NRF_TWIS_Type * _p_twis; #else @@ -108,8 +109,4 @@ class TwoWire : public Stream extern TwoWire Wire; #endif -#if WIRE_INTERFACES_COUNT > 1 -extern TwoWire Wire1; -#endif - #endif diff --git a/libraries/Wire/Wire_nRF52.cpp b/libraries/Wire/Wire_nRF52.cpp index a54c201e..08b450e9 100755 --- a/libraries/Wire/Wire_nRF52.cpp +++ b/libraries/Wire/Wire_nRF52.cpp @@ -18,9 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "nrf.h" - -#if defined(NRF52_SERIES) +#ifdef NRF52 extern "C" { #include @@ -31,21 +29,21 @@ extern "C" { #include "Wire.h" + TwoWire::TwoWire(NRF_TWIM_Type * p_twim, NRF_TWIS_Type * p_twis, IRQn_Type IRQn, uint8_t pinSDA, uint8_t pinSCL) { this->_p_twim = p_twim; this->_p_twis = p_twis; this->_IRQn = IRQn; - this->_uc_pinSDA = pinSDA; - this->_uc_pinSCL = pinSCL; + this->_uc_pinSDA = g_ADigitalPinMap[pinSDA]; + this->_uc_pinSCL = g_ADigitalPinMap[pinSCL]; transmissionBegun = false; } #ifdef ARDUINO_GENERIC -void TwoWire::setPins(uint8_t pinSDA, uint8_t pinSCL) -{ - this->_uc_pinSDA = pinSDA; - this->_uc_pinSCL = pinSCL; +void TwoWire::setPins(uint8_t pinSDA, uint8_t pinSCL) { + this->_uc_pinSDA = g_ADigitalPinMap[pinSDA]; + this->_uc_pinSCL = g_ADigitalPinMap[pinSCL]; } #endif // ARDUINO_GENERIC @@ -53,27 +51,22 @@ void TwoWire::begin(void) { //Master Mode master = true; - NRF_GPIO_Type* portSCL = digitalPinToPort(_uc_pinSCL); - NRF_GPIO_Type* portSDA = digitalPinToPort(_uc_pinSDA); - uint32_t pinSCL = digitalPinToPin(_uc_pinSCL); - uint32_t pinSDA = digitalPinToPin(_uc_pinSDA); - - portSCL->PIN_CNF[pinSCL] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_GPIO->PIN_CNF[_uc_pinSCL] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); - portSDA->PIN_CNF[pinSDA] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) - | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) - | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) - | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); + NRF_GPIO->PIN_CNF[_uc_pinSDA] = ((uint32_t)GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) + | ((uint32_t)GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) + | ((uint32_t)GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) + | ((uint32_t)GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) + | ((uint32_t)GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos); _p_twim->FREQUENCY = TWIM_FREQUENCY_FREQUENCY_K100; _p_twim->ENABLE = (TWIM_ENABLE_ENABLE_Enabled << TWIM_ENABLE_ENABLE_Pos); - _p_twim->PSEL.SCL = g_ADigitalPinMap[_uc_pinSCL]; - _p_twim->PSEL.SDA = g_ADigitalPinMap[_uc_pinSDA]; + _p_twim->PSEL.SCL = _uc_pinSCL; + _p_twim->PSEL.SDA = _uc_pinSDA; NVIC_ClearPendingIRQ(_IRQn); NVIC_SetPriority(_IRQn, 2); @@ -98,8 +91,8 @@ void TwoWire::begin(uint8_t address) { _p_twis->ADDRESS[0] = address; _p_twis->CONFIG = TWIS_CONFIG_ADDRESS0_Msk; - _p_twis->PSEL.SCL = g_ADigitalPinMap[_uc_pinSCL]; - _p_twis->PSEL.SDA = g_ADigitalPinMap[_uc_pinSDA]; + _p_twis->PSEL.SCL = _uc_pinSCL; + _p_twis->PSEL.SDA = _uc_pinSDA; _p_twis->ORC = 0xff; @@ -137,6 +130,10 @@ void TwoWire::setClock(uint32_t baudrate) { } void TwoWire::end() { + NVIC_ClearPendingIRQ(_IRQn); + NVIC_DisableIRQ(_IRQn); + // leave pins as set, for master input with pullup + // for slave input no pullup depends on external pullup if (master) { _p_twim->ENABLE = (TWIM_ENABLE_ENABLE_Disabled << TWIM_ENABLE_ENABLE_Pos); @@ -413,17 +410,4 @@ extern "C" } #endif -#if WIRE_INTERFACES_COUNT > 1 - -TwoWire Wire1(NRF_TWIM0, NRF_TWIS0, SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn, PIN_WIRE1_SDA, PIN_WIRE1_SCL); - -extern "C" -{ - void SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler(void) - { - Wire1.onService(); - } -} -#endif - #endif diff --git a/libraries/Wire/library.properties b/libraries/Wire/library.properties index 7a6dd905..0f88005c 100755 --- a/libraries/Wire/library.properties +++ b/libraries/Wire/library.properties @@ -1,8 +1,8 @@ name=Wire -version=1.0 -author= +version=1.1 +author=Matthew Ford, mod to add Wire.setPins() maintainer= -sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus. Specific implementation for nRF52. +sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus. Specific implementation for nRF52. V1.1 added setPins() paragraph= category=Communication url=http://www.arduino.cc/en/Reference/Wire diff --git a/package.json b/package.json new file mode 100644 index 00000000..4aa4078d --- /dev/null +++ b/package.json @@ -0,0 +1,16 @@ +{ + "name": "framework-arduinonordicnrf5", + "version": "1.700.201209", + "description": "Arduino Wiring-based Framework for Nordic Semiconductor nRF5 based boards", + "keywords": [ + "framework", + "arduino", + "nordic semiconductor", + "nrf5" + ], + "license": "LGPL-2.1-or-later", + "repository": { + "type": "git", + "url": "https://github.com/sandeepmistry/arduino-nRF5" + } +} \ No newline at end of file diff --git a/platform.txt b/platform.txt index be9cb6a4..1ea0e52e 100644 --- a/platform.txt +++ b/platform.txt @@ -1,3 +1,4 @@ +# modifications by Forward Computing and Control Copyright (c) 2018 All rights resevered. # Copyright (c) 2014-2015 Arduino LLC. All right reserved. # Copyright (c) 2016 Sandeep Mistry All right reserved. # @@ -15,7 +16,7 @@ # License along with this library; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -name=Nordic Semiconductor nRF5 Boards +name=pfod Low Power nRF52 (Rev 10) 2022 version=0.7.0 # Compile variables @@ -49,8 +50,7 @@ compiler.size.cmd=arm-none-eabi-size compiler.define=-DARDUINO= # this can be overriden in boards.txt -build.extra_flags= -build.lfclk_flags= +build.more_flags= nrf.sdk.path={build.core.path}/SDK @@ -70,13 +70,13 @@ compiler.elf2hex.extra_flags= # ---------------- ## Compile c files -recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {compiler.nrf.flags} {build.lfclk_flags} {includes} "{source_file}" -o "{object_file}" +recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.more_flags} {compiler.nrf.flags} {includes} "{source_file}" -o "{object_file}" ## Compile c++ files -recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {compiler.nrf.flags} {build.lfclk_flags} {includes} "{source_file}" -o "{object_file}" +recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.more_flags} {compiler.nrf.flags} {includes} "{source_file}" -o "{object_file}" ## Compile S files -recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.lfclk_flags} {includes} "{source_file}" -o "{object_file}" +recipe.S.o.pattern="{compiler.path}{compiler.S.cmd}" {compiler.S.flags} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.more_flags} {includes} "{source_file}" -o "{object_file}" ## Create archives recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}" diff --git a/softdevices.txt b/softdevices.txt index 728c8551..ca0a3b1f 100644 --- a/softdevices.txt +++ b/softdevices.txt @@ -1,10 +1,7 @@ -names=s110,s130,s132 +# the s132 softdevice is included in the pfod_lp_nrf52_2022 zip and so does not need to be downloaded +# later versions of s132 may not be compatible -s110.url=https://www.nordicsemi.com/-/media/Software-and-other-downloads/SoftDevices/S110/s110nrf51800.zip -s110.filename=s110_nrf51_8.0.0_softdevice.hex - -s130.url=https://www.nordicsemi.com/-/media/Software-and-other-downloads/SoftDevices/S130/s130nrf51201.zip -s130.filename=s130_nrf51_2.0.1_softdevice.hex +names=s132 s132.url=https://www.nordicsemi.com/-/media/Software-and-other-downloads/SoftDevices/S132/s132nrf52201.zip s132.filename=s132_nrf52_2.0.1_softdevice.hex diff --git a/variants/BBCmicrobit/pins_arduino.h b/variants/BBCmicrobit/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/BBCmicrobit/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/BBCmicrobit/variant.cpp b/variants/BBCmicrobit/variant.cpp deleted file mode 100644 index fb637e0c..00000000 --- a/variants/BBCmicrobit/variant.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // 0 - 4 - 3, // A0 - left pad - 2, // A1 - middle pad - 1, // A2 - right pad - 4, // A3 - COL1 - 5, // A4 - COL2 - - // 5 - 9 - 17, // BTN A - 12, // COL9 - 11, // COL8 - 18, - 10, // COL7 - - 6, // A5 - COL3 - - 26, // BTN B - 20, - 23, // SCK - 22, // MISO - 21, // MOSI - 16, - - // 17 + 18 - (uint32_t)-1, // 3.3V - (uint32_t)-1, // 3.3V - - 0, // SCL - 30, // SDA - - 25, // RX - 24, // TX - - 7, // COL4 - 8, // COL5 - 9, // COL6 - 13, // ROW1 - 14, // ROW2 - 15, // ROW3 - - 28, // ACCEL INT 1 - 27, // ACCEL INT 2 - 29, // MAG INT 2 - - 19 // RST -}; diff --git a/variants/BBCmicrobit/variant.h b/variants/BBCmicrobit/variant.h deleted file mode 100644 index 35c7d720..00000000 --- a/variants/BBCmicrobit/variant.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_BBC_MICROBIT_ -#define _VARIANT_BBC_MICROBIT_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (33u) -#define NUM_DIGITAL_PINS (20u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (13) -#define LED_BUILTIN PIN_LED -// #define - -// Buttons -#define PIN_BUTTON_A (5) -#define PIN_BUTTON_B (11) - -/* - * Analog pins - */ -#define PIN_A0 (0) -#define PIN_A1 (1) -#define PIN_A2 (2) -#define PIN_A3 (3) -#define PIN_A4 (4) -#define PIN_A5 (10) - - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (21) -#define PIN_SERIAL_TX (22) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (14) -#define PIN_SPI_MOSI (15) -#define PIN_SPI_SCK (13) - -static const uint8_t SS = 16 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (20u) -#define PIN_WIRE_SCL (19u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/BBCmicrobitV2/pins_arduino.h b/variants/BBCmicrobitV2/pins_arduino.h deleted file mode 100755 index 3ef4d4a9..00000000 --- a/variants/BBCmicrobitV2/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/BBCmicrobitV2/variant.cpp b/variants/BBCmicrobitV2/variant.cpp deleted file mode 100755 index 11e6d08d..00000000 --- a/variants/BBCmicrobitV2/variant.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* Pins for micro:bit V2 */ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // 0 - 4 - 2, // A0, LEFT PAD - 3, // A1, MIDDLE PAD - 4, // A2, RIGHT PAD - 31, // A3, COL3 - 28, // A4, COL1 - - // 5 - 9 - 14, // BTN A - 37, // COL4, P1.05 - 11, // COL2 - 10, // NFC2 - 9, // NFC1 - - // 10-16 - 30, // A5, COL5 - 23, // BTN B - 12, - 17, // SCK - 1, // MISO - 13, // MOSI - 34, // P1.02 - - // 17 + 18 - (uint32_t)-1, // 3.3V - (uint32_t)-1, // 3.3V - - // 19 + 20 - 26, // SCL - 32, // SDA, P1.00 - - // 21 - 25 - 21, // ROW1 - 22, // ROW2 - 15, // ROW3 - 24, // ROW4 - 19, // ROW5 - - // 26 - 29 - 36, // LOGO (touch sensor) - 0, // SPEAKER (Note: Must use synthesized LF clock to make this pin available) - 20, // RUN_MIC - 5, // A6, MIC_IN - - // 30 - 31 - 16, // I2C_INT_SDA - 8, // I2C_INT_SCL - - // 32 - 34 - 25, // COMBINED_SENSOR_INT - 40, // RX, P1.08 - 6, // TX - -}; diff --git a/variants/BBCmicrobitV2/variant.h b/variants/BBCmicrobitV2/variant.h deleted file mode 100755 index 22253760..00000000 --- a/variants/BBCmicrobitV2/variant.h +++ /dev/null @@ -1,78 +0,0 @@ -#ifndef _MICROBIT_V2_ -#define _MICROBIT_V2_ - -// Master clock frequency - -#define VARIANT_MCK (64000000ul) - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array - -#define PINS_COUNT (35) -#define NUM_DIGITAL_PINS (35) -#define NUM_ANALOG_INPUTS (7) -#define NUM_ANALOG_OUTPUTS (0) - -// LEDs - -#define PIN_LED (13) -#define LED_BUILTIN PIN_LED - -// Buttons - -#define PIN_BUTTON_A (5) -#define PIN_BUTTON_B (11) - -// Analog pins - -#define PIN_A0 (0) -#define PIN_A1 (1) -#define PIN_A2 (2) -#define PIN_A3 (3) -#define PIN_A4 (4) -#define PIN_A5 (10) -#define PIN_A6 (29) - -#define ADC_RESOLUTION 10 -static const uint8_t A0 = PIN_A0; -static const uint8_t A1 = PIN_A1; -static const uint8_t A2 = PIN_A2; -static const uint8_t A3 = PIN_A3; -static const uint8_t A4 = PIN_A4; -static const uint8_t A5 = PIN_A5; -static const uint8_t A6 = PIN_A6; - -// Serial - -#define PIN_SERIAL_RX (33) -#define PIN_SERIAL_TX (34) - -// SPI - -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (14) -#define PIN_SPI_MOSI (15) -#define PIN_SPI_SCK (13) - -// Wire Interfaces (external and internal) - -#define WIRE_INTERFACES_COUNT 2 - -#define PIN_WIRE_SDA (20) -#define PIN_WIRE_SCL (19) - -#define PIN_WIRE1_SDA (30) -#define PIN_WIRE1_SCL (31) - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif diff --git a/variants/BLENano/pins_arduino.h b/variants/BLENano/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/BLENano/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/BLENano/variant.cpp b/variants/BLENano/variant.cpp deleted file mode 100644 index 9d1b6864..00000000 --- a/variants/BLENano/variant.cpp +++ /dev/null @@ -1,45 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 - 11, - 9, - 10, - 8, - 28, - 29, - 15, - 17, - - // A0 - A4 / D8 - D12 - 1, - 2, - 3, - 4, - 5, - - // D13 - 19, - - // A5 / D14 - 6 -}; diff --git a/variants/BLENano/variant.h b/variants/BLENano/variant.h deleted file mode 100644 index d39fc28b..00000000 --- a/variants/BLENano/variant.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_BLE_NANO_ -#define _VARIANT_BLE_NANO_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (14u) -#define NUM_DIGITAL_PINS (14u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (13) -#define LED_BUILTIN PIN_LED - -/* - * Analog pins - */ -#define PIN_A0 (8) -#define PIN_A1 (9) -#define PIN_A2 (10) -#define PIN_A3 (11) -#define PIN_A4 (12) -#define PIN_A5 (14) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) -#define PIN_SERIAL_TX (1) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (0) -#define PIN_SPI_MOSI (1) -#define PIN_SPI_SCK (3) - -static const uint8_t SS = 2 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (2u) -#define PIN_WIRE_SCL (3u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/BluzDK/pins_arduino.h b/variants/BluzDK/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/BluzDK/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/BluzDK/variant.cpp b/variants/BluzDK/variant.cpp deleted file mode 100644 index f6e9a9e6..00000000 --- a/variants/BluzDK/variant.cpp +++ /dev/null @@ -1,63 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 - 21, - 22, - 23, - 24, - 25, - 28, - 29, - 30, - - // ?? - // ?? - - // A0 - A7 - 6, - 5, - 4, - 3, - 2, - 1, - 0, - 13, - - // RX, TX - 12, - 8, - - // SS1, MOSI1, MISO1, SCK1 - 15, - 9, - 14, - 10, - - // BTN - 7, - - // RBG - 19, - 18, - 17 -}; diff --git a/variants/BluzDK/variant.h b/variants/BluzDK/variant.h deleted file mode 100644 index 495140a4..00000000 --- a/variants/BluzDK/variant.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_BLUZ_DK_ -#define _VARIANT_BLUZ_DK_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (26u) -#define NUM_DIGITAL_PINS (22u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (7) -#define PIN_LEDR (23) -#define PIN_LEDG (24) -#define PIN_LEDB (25) -#define LED_BUILTIN PIN_LED - -// Buttons -#define PIN_BUTTON (22) - -/* - * Analog pins - */ -#define PIN_A0 (8) -#define PIN_A1 (9) -#define PIN_A2 (10) -#define PIN_A3 (11) -#define PIN_A4 (12) -#define PIN_A5 (13) -#define PIN_A6 (14) -#define PIN_A7 (15) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -static const uint8_t A6 = PIN_A6 ; -static const uint8_t A7 = PIN_A7 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (16) -#define PIN_SERIAL_TX (17) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 2 - -#define PIN_SPI_MISO (PIN_A4) -#define PIN_SPI_MOSI (PIN_A5) -#define PIN_SPI_SCK (PIN_A3) - -static const uint8_t SS = PIN_A2 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -#define PIN_SPI1_MISO (19) -#define PIN_SPI1_MOSI (20) -#define PIN_SPI1_SCK (21) - -static const uint8_t SS1 = 18 ; -static const uint8_t MOSI1 = PIN_SPI1_MOSI ; -static const uint8_t MISO1 = PIN_SPI1_MISO ; -static const uint8_t SCK1 = PIN_SPI1_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (0u) -#define PIN_WIRE_SCL (1u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/CalliopeMini/pins_arduino.h b/variants/CalliopeMini/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/CalliopeMini/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/CalliopeMini/variant.cpp b/variants/CalliopeMini/variant.cpp deleted file mode 100644 index 87eaba6c..00000000 --- a/variants/CalliopeMini/variant.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // 0 - 19 (available on expension connector) - 0, // left pad (not analog) - 1, // bottom left pad; A1 - 2, // bottom right pad; A2 - 22, // right pad; SPI SCLK (not analog) - 4, // LED row 1; A3 - 5, // LED row 2; A4 - 6, // LED row 3; A5 - 7, // LED row 4 - 8, // LED row 5 - 9, // LED row 6 - 10, // LED row 7 - 11, // LED row 8 - 12, // LED row 9 - 13, // LED column 1 - 14, // LED column 2 - 15, // LED column 3 - 26, // serial RX; SPI MISO, A6 - 27, // serial TX; SPI MOSI, A7 - 20, // SDA - 19, // SCL - - // 20-25 (internal; not available on external connector) - 17, // button A - 23, // unassigned - 16, // button B - 28, // motor driver enable - 29, // motor driver in1 - 30, // motor driver in2 - - // 26-30 - 18, // neopixel - 21, // accelerometer chip interrupt - 3, // microphone; A0 - 24, // usb serial TX - 25, // usb serial RX -}; diff --git a/variants/CalliopeMini/variant.h b/variants/CalliopeMini/variant.h deleted file mode 100644 index ee88c16e..00000000 --- a/variants/CalliopeMini/variant.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_CALLIOPE_MINI_ -#define _VARIANT_CALLIOPE_MINI_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array - -#define PINS_COUNT (31) -#define NUM_DIGITAL_PINS (26) -#define NUM_ANALOG_INPUTS (6) -#define NUM_ANALOG_OUTPUTS (0) - -// LEDs - -#define PIN_LED (0) // no user LED; use pad 0 -#define LED_BUILTIN PIN_LED - -// Buttons - -#define PIN_BUTTON_A (20) -#define PIN_BUTTON_B (22) - -// Analog pins - -#define PIN_A0 (28) // microphone (note: pad 0 is not an analog input!) -#define PIN_A1 (1) // pad 1 -#define PIN_A2 (2) // pad 2 -#define PIN_A3 (4) // connector pin 4 -#define PIN_A4 (5) // connector pin 5 -#define PIN_A5 (6) // connector pin 6 -#define PIN_A6 (16) // connector pin 16 -#define PIN_A7 (17) // connector pin 17 - -static const uint8_t A0 = PIN_A0; -static const uint8_t A1 = PIN_A1; -static const uint8_t A2 = PIN_A2; -static const uint8_t A3 = PIN_A3; -static const uint8_t A4 = PIN_A4; -static const uint8_t A5 = PIN_A5; -static const uint8_t A6 = PIN_A6; -static const uint8_t A7 = PIN_A7; -#define ADC_RESOLUTION 10 - -// Serial interface - -#define PIN_SERIAL_TX (29) -#define PIN_SERIAL_RX (30) - -// SPI Interfaces - -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (16) -#define PIN_SPI_MOSI (17) -#define PIN_SPI_SCK (22) - -static const uint8_t MOSI = PIN_SPI_MOSI; -static const uint8_t MISO = PIN_SPI_MISO; -static const uint8_t SCK = PIN_SPI_SCK; - -// Wire Interfaces - -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (18) -#define PIN_WIRE_SCL (19) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -// I2C device IDs - -#define ACCEL_ID 24 -#define GYRO_ID 104 -#define MAG_ID 24 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/CalliopeminiV3/pins_arduino.h b/variants/CalliopeminiV3/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/CalliopeminiV3/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/CalliopeminiV3/variant.cpp b/variants/CalliopeminiV3/variant.cpp deleted file mode 100644 index 70ad464c..00000000 --- a/variants/CalliopeminiV3/variant.cpp +++ /dev/null @@ -1,69 +0,0 @@ -/* Pins for Calliope mini V3 -This file connects the hardware pin numbers on the left to the array position. -In Arduino IDE this array position is usually used when calling a pin by number, -e.g. pinMode(5, INPUT) sets BTN A to input mode */ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // 0 - 4 - 2, // A0, PAD 0 - 3, // A1, PAD 1 - 4, // A2, PAD 2 - 35, // Pad 3, not analog (Calliope exclusive pin) - 28, // A4, COL1 - - // 5 - 9 - 14, // BTN A - 37, // COL4, P1.05 - 11, // COL2 - 10, // NFC2 - 9, // NFC1 - - // 10-16 - 30, // A5, COL5 - 23, // BTN B - 12, - 17, // SCK - 1, // MISO - 13, // MOSI - 29, // A5, C16_A1RX (Calliope change) - - // 17 + 18 - 34, // P1.02 C17 (Calliope exclusive pin) - 31, // A3, COL3 (Calliope changed pin number) - - // 19 + 20 - 26, // SCL - 32, // SDA, P1.00 - - // 21 - 25 - 21, // ROW1 - 22, // ROW2 - 15, // ROW3 - 24, // ROW4 - 19, // ROW5 - - // 26 - 29 - 36, // LOGO (touch sensor) - 0, // SPEAKER (Note: Must use synthesized LF clock to make this pin available) - 20, // RUN_MIC - 5, // A6, MIC_IN - - // 30 - 31 - 16, // I2C_INT_SDA - 8, // I2C_INT_SCL - - // 32 - 34 - 25, // COMBINED_SENSOR_INT - 40, // RX, P1.08 - 6, // TX - - // 35 - 40 internal Calliope mini pins - 7, // RGB - 38, // MOTOR_MODE - 33, // M0_DIR - 27, // M0_SPEED - 39, // M1_DIR - 41, // M1_SPEED -}; diff --git a/variants/CalliopeminiV3/variant.h b/variants/CalliopeminiV3/variant.h deleted file mode 100644 index ee8d5050..00000000 --- a/variants/CalliopeminiV3/variant.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef _CALLIOPE_MINI_V3_ -#define _CALLIOPE_MINI_V3_ - -// Master clock frequency - -#define VARIANT_MCK (64000000ul) - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array - -#define PINS_COUNT (41) -#define NUM_DIGITAL_PINS (41) -#define NUM_ANALOG_INPUTS (7) -#define NUM_ANALOG_OUTPUTS (0) - -// LEDs - -#define PIN_LED (13) // This goes to Calliope mini header C12 (not a built in LED) -#define LED_BUILTIN PIN_LED - -// Buttons - -#define PIN_BUTTON_A (5) -#define PIN_BUTTON_B (11) - -// Analog pins - -#define PIN_A0 (0) -#define PIN_A1 (1) -#define PIN_A2 (2) -#define PIN_A3 (3) -#define PIN_A4 (4) -#define PIN_A5 (10) -#define PIN_A6 (29) - -#define ADC_RESOLUTION 10 -static const uint8_t A0 = PIN_A0; -static const uint8_t A1 = PIN_A1; -static const uint8_t A2 = PIN_A2; -static const uint8_t A3 = PIN_A3; -static const uint8_t A4 = PIN_A4; -static const uint8_t A5 = PIN_A5; -static const uint8_t A6 = PIN_A6; - -// Serial - -#define PIN_SERIAL_RX (33) -#define PIN_SERIAL_TX (34) - -// SPI - -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (14) -#define PIN_SPI_MOSI (15) -#define PIN_SPI_SCK (13) - -// Wire Interfaces (external and internal) - -#define WIRE_INTERFACES_COUNT 2 - -#define PIN_WIRE_SDA (20) -#define PIN_WIRE_SCL (19) - -#define PIN_WIRE1_SDA (30) -#define PIN_WIRE1_SCL (31) - -#ifdef __cplusplus - -// Calliope internal pins -#define PIN_RGB (35) -#define PIN_M_MODE (36) -#define PIN_M0_DIR (37) -#define PIN_M0_SPEED (38) -#define PIN_M1_DIR (39) -#define PIN_M1_SPEED (40) -} -#endif // __cplusplus - -#endif diff --git a/variants/DWM1001-DEV/pins_arduino.h b/variants/DWM1001-DEV/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/DWM1001-DEV/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/DWM1001-DEV/variant.cpp b/variants/DWM1001-DEV/variant.cpp deleted file mode 100644 index c5790a28..00000000 --- a/variants/DWM1001-DEV/variant.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D8 - 12, - 27, - 23, - 13, - 15, - 8, - 26, - 6, - 7, - - // A0, A1 - 4, - 3, - - // SDA, SCL - 29, - 28, - - // RX, TX - 11, - 5, - - // DWM1000 - // SPI SS1, MISO1, MOSI1, SCK1 - 17, - 18, - 20, - 16, - // RST, IRQ - 24, - 19, - - // ACC IRQ - 25, - - // LEDS - 14, - 22, - 30, - 31, - - // BTN - 2 - -}; diff --git a/variants/DWM1001-DEV/variant.h b/variants/DWM1001-DEV/variant.h deleted file mode 100644 index 78a8d3d1..00000000 --- a/variants/DWM1001-DEV/variant.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_DWM1001_DEV_ -#define _VARIANT_DWM1001_DEV_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (27u) -#define NUM_DIGITAL_PINS (11u) -#define NUM_ANALOG_INPUTS (2u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LEDRT (22) -#define PIN_LEDRB (23) -#define PIN_LEDG (24) -#define PIN_LEDB (25) -#define LED_BUILTIN PIN_LEDRT -static const uint8_t LED_RED_TOP = PIN_LEDRT ; -static const uint8_t LED_RED_BOT = PIN_LEDRB ; -static const uint8_t LED_GREEN = PIN_LEDG ; -static const uint8_t LED_BLUE = PIN_LEDB ; - -// Button -#define PIN_BUTTON (26) - -static const uint8_t BTN = PIN_BUTTON ; - -/* - * Analog pins - */ -#define PIN_A0 (9) -#define PIN_A1 (10) - -static const uint8_t A0 = PIN_A0 ; // AIN2 -static const uint8_t A1 = PIN_A1 ; // AIN1 -#define ADC_RESOLUTION 14 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (13) -#define PIN_SERIAL_TX (14) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 2 - -#define PIN_SPI_MISO (8) -#define PIN_SPI_MOSI (7) -#define PIN_SPI_SCK (PIN_A0) - -static const uint8_t SS = PIN_A1 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -#define PIN_SPI1_SS (15) -#define PIN_SPI1_MISO (16) -#define PIN_SPI1_MOSI (17) -#define PIN_SPI1_SCK (18) - -static const uint8_t SS1 = PIN_SPI1_SS ; -static const uint8_t MOSI1 = PIN_SPI1_MOSI ; -static const uint8_t MISO1 = PIN_SPI1_MISO ; -static const uint8_t SCK1 = PIN_SPI1_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (11) -#define PIN_WIRE_SCL (12) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -/* - * Other DWM1001 internal IOs - */ -#define PIN_DW_RST (19) -#define PIN_DW_IRQ (20) - -static const uint8_t DW_RST = PIN_DW_RST; -static const uint8_t DW_IRQ = PIN_DW_IRQ; - -#define PIN_ACC_IRQ (21) - -static const uint8_t ACC_IRQ = PIN_ACC_IRQ; - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/Generic/pins_arduino.h b/variants/Generic/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/Generic/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/Generic/variant.cpp b/variants/Generic/variant.cpp deleted file mode 100644 index 9b7b7cd7..00000000 --- a/variants/Generic/variant.cpp +++ /dev/null @@ -1,89 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31, -#if GPIO_COUNT > 1 - 32, - 33, - 34, - 35, - 36, - 37, - 38, - 39, - 40, - 41, - 42, - 43, - 44, - 45, - 46, - 47, - 48, - 49, - 50, - 51, - 52, - 53, - 54, - 55, - 56, - 57, - 58, - 59, - 60, - 61, - 62, - 63, -#endif -}; diff --git a/variants/Generic/variant.h b/variants/Generic/variant.h deleted file mode 100644 index 387ddecd..00000000 --- a/variants/Generic/variant.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_GENERIC_ -#define _VARIANT_GENERIC_ - -#include "nrf.h" -#include "nrf_peripherals.h" - -/** Master clock frequency */ -#if defined(NRF52_SERIES) -#define VARIANT_MCK (64000000ul) -#else -#define VARIANT_MCK (16000000ul) -#endif - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#if GPIO_COUNT == 1 -#define PINS_COUNT (32u) -#define NUM_DIGITAL_PINS (32u) -#elif GPIO_COUNT == 2 -#define PINS_COUNT (64u) -#define NUM_DIGITAL_PINS (64u) -#else -#error "Unsupported GPIO_COUNT" -#endif -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (13) // P0.13 -#define LED_BUILTIN PIN_LED - -/* - * Analog pins - */ -#define PIN_A0 (1) // P0.01 -#define PIN_A1 (2) // P0.02 -#define PIN_A2 (3) // P0.03 -#define PIN_A3 (4) // P0.04 -#define PIN_A4 (5) // P0.05 -#define PIN_A5 (6) // P0.06 - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#if defined(NRF52_SERIES) -#define ADC_RESOLUTION 14 -#else -#define ADC_RESOLUTION 10 -#endif - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) // P0.00 -#define PIN_SERIAL_TX (1) // P0.01 - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (22) // P0.22 -#define PIN_SPI_MOSI (23) // P0.23 -#define PIN_SPI_SCK (24) // P0.24 - -static const uint8_t SS = 25 ; // P0.25 -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (20u) // P0.20 -#define PIN_WIRE_SCL (21u) // P0.21 - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/OSHChip/pins_arduino.h b/variants/OSHChip/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/OSHChip/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/OSHChip/variant.cpp b/variants/OSHChip/variant.cpp deleted file mode 100644 index 04f013e6..00000000 --- a/variants/OSHChip/variant.cpp +++ /dev/null @@ -1,43 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - 20, // TX/D0 - 18, // RX/D1 - 16, // D2 - 15, // D3 - 12, // D4 - 11, // D5 - 9, // D6 - - 24, // D7 - 21, // D8 - 0, // D9/AREF - - 26, // A0 - 27, // A1 - 2, // A2 - 1, // A3 - - 8, // R - 5, // G - 3 // B -}; diff --git a/variants/OSHChip/variant.h b/variants/OSHChip/variant.h deleted file mode 100644 index c3766857..00000000 --- a/variants/OSHChip/variant.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_OSHCHIP_ -#define _VARIANT_OSHCHIP_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (17u) -#define NUM_DIGITAL_PINS (14u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (PIN_LEDR) -#define PIN_LEDR (14) -#define PIN_LEDG (15) -#define PIN_LEDB (16) -#define LED_BUILTIN PIN_LED - -/* - * Analog pins - */ -#define PIN_A0 (10) -#define PIN_A1 (11) -#define PIN_A2 (12) -#define PIN_A3 (13) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (1) -#define PIN_SERIAL_TX (0) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 0 - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 0 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/PCA1000X/pins_arduino.h b/variants/PCA1000X/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/PCA1000X/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/PCA1000X/variant.cpp b/variants/PCA1000X/variant.cpp deleted file mode 100644 index 9245d400..00000000 --- a/variants/PCA1000X/variant.cpp +++ /dev/null @@ -1,68 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - Copyright (c) 2016 Frank Holtz. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -#ifdef PCA10000 -const uint32_t g_ADigitalPinMap[] = { - 8, // RTS - 9, // TxD - 10, // CTS - 11, // RxD - 21, // LED Red - 22, // LED Green - 23, // LED Blue -}; -#else -const uint32_t g_ADigitalPinMap[] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31 -}; -#endif diff --git a/variants/PCA1000X/variant.h b/variants/PCA1000X/variant.h deleted file mode 100644 index e2484ddf..00000000 --- a/variants/PCA1000X/variant.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - Copyright (c) 2016 Frank Holtz. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_PCA1000X_ -#define _VARIANT_PCA1000X_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#ifdef PCA10000 - /* PCA10000 - * *********/ - - #define PINS_COUNT (7u) - #define NUM_DIGITAL_PINS (7u) - #define NUM_ANALOG_INPUTS (0u) - #define NUM_ANALOG_OUTPUTS (0u) - - // LEDs - #define PIN_LED1 (4) - #define PIN_LED2 (5) - #define PIN_LED3 (6) - #define LED_BUILTIN PIN_LED1 - - /* - * Serial interfaces - */ - #define PIN_SERIAL_RX (3) - #define PIN_SERIAL_CTS (2) - #define PIN_SERIAL_TX (1) - #define PIN_SERIAL_RTS (0) -#elif defined(PCA10001) - /* PCA10001 - * *********/ - - #define PINS_COUNT (32u) - #define NUM_DIGITAL_PINS (32u) - #define NUM_ANALOG_INPUTS (0u) - #define NUM_ANALOG_OUTPUTS (0u) - - // LEDs - #define PIN_LED0 (18) - #define PIN_LED1 (19) - #define LED_BUILTIN PIN_LED0 - - // Buttons - #define PIN_BUTTON0 (16) - #define PIN_BUTTON1 (17) - - /* - * Serial interfaces - */ - #define PIN_SERIAL_RX (11) - #define PIN_SERIAL_CTS (10) - #define PIN_SERIAL_TX (9) - #define PIN_SERIAL_RTS (8) -#else - /* PCA1000[1,2,3,4] on nRF6310 - * ****************************/ - #define PINS_COUNT (32u) - #define NUM_DIGITAL_PINS (32u) - #define NUM_ANALOG_INPUTS (6u) - #define NUM_ANALOG_OUTPUTS (0u) - - // LEDs - #define PIN_LED1 (8) - #define PIN_LED2 (9) - #define PIN_LED3 (10) - #define PIN_LED4 (11) - #define PIN_LED5 (12) - #define PIN_LED6 (13) - #define PIN_LED7 (14) - #define PIN_LED8 (15) - #define LED_BUILTIN PIN_LED1 - - // Buttons - #define PIN_BUTTON1 (0) - #define PIN_BUTTON2 (1) - #define PIN_BUTTON3 (2) - #define PIN_BUTTON4 (3) - #define PIN_BUTTON5 (4) - #define PIN_BUTTON6 (5) - #define PIN_BUTTON7 (6) - #define PIN_BUTTON8 (7) - - /* - * Analog pins - */ - #define PIN_A0 (26) - #define PIN_A1 (27) - #define PIN_A2 (28) - #define PIN_A3 (29) - #define PIN_A4 (30) - #define PIN_A5 (31) - - static const uint8_t A0 = PIN_A0 ; - static const uint8_t A1 = PIN_A1 ; - static const uint8_t A2 = PIN_A2 ; - static const uint8_t A3 = PIN_A3 ; - static const uint8_t A4 = PIN_A4 ; - static const uint8_t A5 = PIN_A5 ; - - #define ADC_RESOLUTION 10 - - /* - * Serial interfaces - */ - #define PIN_SERIAL_RX (16) - #define PIN_SERIAL_TX (17) - - /* - * SPI Interfaces - */ - #define SPI_INTERFACES_COUNT 1 - - #define PIN_SPI_MISO (18) - #define PIN_SPI_MOSI (19) - #define PIN_SPI_SCK (20) - - static const uint8_t SS = 25 ; - static const uint8_t MOSI = PIN_SPI_MOSI ; - static const uint8_t MISO = PIN_SPI_MISO ; - static const uint8_t SCK = PIN_SPI_SCK ; - - /* - * Wire Interfaces - */ - #define WIRE_INTERFACES_COUNT 1 - - #define PIN_WIRE_SDA (25u) - #define PIN_WIRE_SCL (24u) - - static const uint8_t SDA = PIN_WIRE_SDA; - static const uint8_t SCL = PIN_WIRE_SCL; - -#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/PCA20006/pins_arduino.h b/variants/PCA20006/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/PCA20006/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/PCA20006/variant.cpp b/variants/PCA20006/variant.cpp deleted file mode 100644 index bf54fc6b..00000000 --- a/variants/PCA20006/variant.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - 0, - 1, - 2, - 3, - (uint32_t)-1, - 5, - (uint32_t)-1, - (uint32_t)-1, - 8, - 9, - (uint32_t)-1, - 11, - 12, - (uint32_t)-1, - (uint32_t)-1, - 15, - 16, - (uint32_t)-1, - 18, - (uint32_t)-1, - 20, - 21, - (uint32_t)-1, - (uint32_t)-1, - 24, - (uint32_t)-1, - (uint32_t)-1, - (uint32_t)-1, - (uint32_t)-1, - (uint32_t)-1, - (uint32_t)-1, - (uint32_t)-1 -}; diff --git a/variants/PCA20006/variant.h b/variants/PCA20006/variant.h deleted file mode 100644 index 04990452..00000000 --- a/variants/PCA20006/variant.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_BOARD_PCA20006_ -#define _VARIANT_BOARD_PCA20006_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (32u) -#define NUM_DIGITAL_PINS (32u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (15) -#define PIN_LEDR (16) -#define PIN_LEDG (12) -#define PIN_LEDB (15) -#define LED_BUILTIN PIN_LED - -// Buttons -#define PIN_BUTTON (08) -#define PIN_SW1 (08) -#define PIN_SW2 (18) - -/* - * Analog pins - */ -#define PIN_A0 (1) -#define PIN_A1 (2) -#define PIN_A2 (3) -#define PIN_A3 (4) -#define PIN_A4 (5) -#define PIN_A5 (6) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; - -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (11) -#define PIN_SERIAL_TX (9) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (0) -#define PIN_SPI_MOSI (1) -#define PIN_SPI_SCK (2) - -static const uint8_t SS = 3 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (21u) -#define PIN_WIRE_SCL (24u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/RedBearLab_nRF51822/pins_arduino.h b/variants/RedBearLab_nRF51822/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/RedBearLab_nRF51822/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/RedBearLab_nRF51822/variant.cpp b/variants/RedBearLab_nRF51822/variant.cpp deleted file mode 100644 index 9a718bd9..00000000 --- a/variants/RedBearLab_nRF51822/variant.cpp +++ /dev/null @@ -1,61 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 - 11, - 9, - 10, - 8, - 21, - 23, - 16, - 17, - - // D8 - D13 - 19, - 18, - 14, - 12, - 13, - 15, - - // A0 - A5 - 1, - 2, - 3, - 4, - 5, - 6, - - // SDA, SCL - 29, - 28, - - // MISO, SCK, MOSI - 22, - 25, - 30, - - - // AREF - 0 -}; diff --git a/variants/RedBearLab_nRF51822/variant.h b/variants/RedBearLab_nRF51822/variant.h deleted file mode 100644 index 3cceae5c..00000000 --- a/variants/RedBearLab_nRF51822/variant.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _REDBEARLAB_NRF51822_ -#define _REDBEARLAB_NRF51822_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (26u) -#define NUM_DIGITAL_PINS (20u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (13) -#define LED_BUILTIN PIN_LED - -/* - * Analog pins - */ -#define PIN_A0 (14) -#define PIN_A1 (15) -#define PIN_A2 (16) -#define PIN_A3 (17) -#define PIN_A4 (18) -#define PIN_A5 (19) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) -#define PIN_SERIAL_TX (1) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (22) -#define PIN_SPI_MOSI (24) -#define PIN_SPI_SCK (23) - -static const uint8_t SS = 10 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (20u) -#define PIN_WIRE_SCL (21u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/RedBear_BLENano2/pins_arduino.h b/variants/RedBear_BLENano2/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/RedBear_BLENano2/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/RedBear_BLENano2/variant.cpp b/variants/RedBear_BLENano2/variant.cpp deleted file mode 100644 index dc3c48b3..00000000 --- a/variants/RedBear_BLENano2/variant.cpp +++ /dev/null @@ -1,44 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // A0/D0 - A5/D5 - 30, - 29, - 28, - 2, - 5, - 4, - - // D6 - D10 - 3, - 6, - 7, - 8, - 21, - - // D11 - D12 - (uint32_t)-1, - (uint32_t)-1, - - // D13 - 11 -}; diff --git a/variants/RedBear_BLENano2/variant.h b/variants/RedBear_BLENano2/variant.h deleted file mode 100644 index 8fc4c73f..00000000 --- a/variants/RedBear_BLENano2/variant.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_REDBEAR_BLE_NANO2_ -#define _VARIANT_REDBEAR_BLE_NANO2_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (14u) -#define NUM_DIGITAL_PINS (14u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define LED_BUILTIN 13 - -/* - * Analog pins - */ -#define PIN_A0 (0) -#define PIN_A1 (1) -#define PIN_A2 (2) -#define PIN_A3 (3) -#define PIN_A4 (4) -#define PIN_A5 (5) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 14 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) -#define PIN_SERIAL_TX (1) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (8) -#define PIN_SPI_MOSI (7) -#define PIN_SPI_SCK (9) - -static const uint8_t SS = 6 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (2u) -#define PIN_WIRE_SCL (3u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/RedBear_Blend2/pins_arduino.h b/variants/RedBear_Blend2/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/RedBear_Blend2/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/RedBear_Blend2/variant.cpp b/variants/RedBear_Blend2/variant.cpp deleted file mode 100644 index ffc82a68..00000000 --- a/variants/RedBear_Blend2/variant.cpp +++ /dev/null @@ -1,59 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - - // D8 - D13 - 19, - 20, - 22, - 23, - 24, - 25, - - // A0 - A5 - 3, - 4, - 28, - 29, - 30, - 31, - - // SDA, SCL - 26, - 27, - - // RX, TX - 8, - 6, - - // AREF - 2 -}; diff --git a/variants/RedBear_Blend2/variant.h b/variants/RedBear_Blend2/variant.h deleted file mode 100644 index 7d9e3fa6..00000000 --- a/variants/RedBear_Blend2/variant.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_REDBEAR_BLEND2_ -#define _VARIANT_REDBEAR_BLEND2_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (25u) -#define NUM_DIGITAL_PINS (20u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define LED_BUILTIN 13 - -/* - * Analog pins - */ -#define PIN_A0 (14) -#define PIN_A1 (15) -#define PIN_A2 (16) -#define PIN_A3 (17) -#define PIN_A4 (18) -#define PIN_A5 (19) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 14 - -// Other pins -#define PIN_AREF (24) -static const uint8_t AREF = PIN_AREF; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (22) -#define PIN_SERIAL_TX (23) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (12) -#define PIN_SPI_MOSI (11) -#define PIN_SPI_SCK (13) - -static const uint8_t SS = 10 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (20u) -#define PIN_WIRE_SCL (21u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/SeeedArchLink/pins_arduino.h b/variants/SeeedArchLink/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/SeeedArchLink/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/SeeedArchLink/variant.cpp b/variants/SeeedArchLink/variant.cpp deleted file mode 100644 index 242783ed..00000000 --- a/variants/SeeedArchLink/variant.cpp +++ /dev/null @@ -1,53 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - - // D0 - D7 - 7, //RX - 8, //TX - 9, //W5500 interrupt - 10, - 11, //SS_SDCARD - 12, - 13, - 17, //W5500 reset - - // D8 - D13 - 18, - 23, - 24, //SS_W5500 - 25, //SPI MOSI - 28, //SPI MISO - 29, //SPI SCK - - // A0 - A6 - 1, - 2, - 3, - 4, - 5, //I2C SDA - 6, //I2C SDA - 30, //LED - - // AREF - 0, -}; diff --git a/variants/SeeedArchLink/variant.h b/variants/SeeedArchLink/variant.h deleted file mode 100644 index 15a7e7ae..00000000 --- a/variants/SeeedArchLink/variant.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_ARCHLINK_ -#define _VARIANT_ARCHLINK_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (22u) -#define NUM_DIGITAL_PINS (22u) -#define NUM_ANALOG_INPUTS (7u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED1 (20) - -#define LED_BUILTIN PIN_LED1 - -/* - * Analog pins - */ -#define PIN_A0 (14) -#define PIN_A1 (15) -#define PIN_A2 (16) -#define PIN_A3 (17) -#define PIN_A4 (18) -#define PIN_A5 (19) -#define PIN_A6 (20) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -static const uint8_t A6 = PIN_A6 ; -#define ADC_RESOLUTION 10 - -// Other pins -#define PIN_AREF (21) -static const uint8_t AREF = PIN_AREF; - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (12) -#define PIN_SPI_MOSI (11) -#define PIN_SPI_SCK (13) - -static const uint8_t SS = 10 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -static const uint8_t SDCARD_SS = 4 ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (18) -#define PIN_WIRE_SCL (19) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) -#define PIN_SERIAL_TX (1) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/Sinobit/README.md b/variants/Sinobit/README.md deleted file mode 100644 index b666efc2..00000000 --- a/variants/Sinobit/README.md +++ /dev/null @@ -1,6 +0,0 @@ -# Sino:Bit support files for Arduino -Contributed by Tomas Lubkowitz @sceptic_int for Sino:Bit - -For LED Matrix functionality please look at https://learn.adafruit.com/sino-bit-with-arduino/dastels-overview - - diff --git a/variants/Sinobit/pins_arduino.h b/variants/Sinobit/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/Sinobit/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/Sinobit/variant.cpp b/variants/Sinobit/variant.cpp deleted file mode 100644 index 93111220..00000000 --- a/variants/Sinobit/variant.cpp +++ /dev/null @@ -1,57 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - - 3, // A0 - left pad - 2, // A1 - middle pad - 1, // A2 - right pad - 4, // A3 - COL1 - 5, // A4 - COL2 - 17, // BTN A - 12, // COL9 - 11, // COL8 - 18, - 10, // COL7 - 6, // A5 - COL3 - 26, // BTN B - 20, - 23, // SCK - 22, // MISO - 21, // MOSI - 16, - (uint32_t)-1, // 3.3V - (uint32_t)-1, // 3.3V - 0, // SCL - 30, // SDA - 25, // RX - 24, // TX - 7, // COL4 - 8, // COL5 - 9, // COL6 - 13, // ROW1 - 14, // ROW2 - 15, // ROW3 - 28, // ACCEL INT 1 - 27, // ACCEL INT 2 - 29, // MAG INT 2 - 19 // RST -}; diff --git a/variants/Sinobit/variant.h b/variants/Sinobit/variant.h deleted file mode 100644 index 2e048b72..00000000 --- a/variants/Sinobit/variant.h +++ /dev/null @@ -1,103 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_SINOBIT_ -#define _VARIANT_SINOBIT_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (33u) -#define NUM_DIGITAL_PINS (20u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (13) -#define LED_BUILTIN PIN_LED - -// Buttons -#define PIN_BUTTON_A (5) -#define PIN_BUTTON_B (11) - -/* - * Analog pins - */ -#define PIN_A0 (0) -#define PIN_A1 (1) -#define PIN_A2 (2) -#define PIN_A3 (3) -#define PIN_A4 (4) -#define PIN_A5 (10) - - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (21) -#define PIN_SERIAL_TX (22) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (14) -#define PIN_SPI_MOSI (15) -#define PIN_SPI_SCK (13) - -static const uint8_t SS = 16 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (20u) -#define PIN_WIRE_SCL (19u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/Taida_Century_nRF52_minidev/pins_arduino.h b/variants/Taida_Century_nRF52_minidev/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/Taida_Century_nRF52_minidev/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/Taida_Century_nRF52_minidev/variant.cpp b/variants/Taida_Century_nRF52_minidev/variant.cpp deleted file mode 100644 index 9d804924..00000000 --- a/variants/Taida_Century_nRF52_minidev/variant.cpp +++ /dev/null @@ -1,62 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - Copyright (c) 2016 Frank Holtz. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 - 25, // D0, near Radio! -> Low drive, low frequency I/O only. - 26, // D1, near Radio! -> Low drive, low frequency I/O only. - 27, // D2, near Radio! -> Low drive, low frequency I/O only. - 28, // D3, near Radio! -> Low drive, low frequency I/O only. - 29, // D4, NOT CONNECTED, near Radio! -> Low drive, low frequency I/O only. - 30, // D5, LED1, near Radio! -> Low drive, low frequency I/O only. - 31, // D6, LED2, near Radio! -> Low drive, low frequency I/O only. - 2, // D7, PIN_WIRE_SDA - - // D8 - D13 - 3, // D8, PIN_WIRE_SCL - 4, // D9, BUTTON1, NFC-Antenna 1 - 5, // D10 - 0, // D11, NOT CONNECTED - 1, // D12, NOT CONNECTED - 6, // D13 - - // D14 - D30 - 7, // D14 - 8, // D15 - 9, // D16, NOT CONNECTED - 10, // D17, NFC-Antenna 2, NOT CONNECTED - 11, // D18, RXD - 12, // D19, TXD - 13, // D20, SS - 14, // D21, MISO - 15, // D22, MOSI - 16, // D23, SCK - 17, // D24, A0 - 18, // D25, A1 - 19, // D26, A2 - 20, // D27, A3 - 22, // D28, A4, near Radio! -> Low drive, low frequency I/O only. - 23, // D29, A5, near Radio! -> Low drive, low frequency I/O only. - 24, // D30, - - 21, // RESET -}; diff --git a/variants/Taida_Century_nRF52_minidev/variant.h b/variants/Taida_Century_nRF52_minidev/variant.h deleted file mode 100644 index 71f46f46..00000000 --- a/variants/Taida_Century_nRF52_minidev/variant.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - Copyright (c) 2016 Frank Holtz. All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_NRF52_MINIDEV_ -#define _VARIANT_NRF52_MINIDEV_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (32u) -#define NUM_DIGITAL_PINS (20u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED1 (5) -#define PIN_LED2 (6) -#define LED_BUILTIN PIN_LED1 - -// Buttons -// KEY -#define PIN_BUTTON1 (9) -// Reset -> read nordic documentation for disabling reset function -#define PIN_BUTTON2 (31) - -/* - * Analog pins - */ -#define PIN_A0 (25) -#define PIN_A1 (26) -#define PIN_A2 (27) -#define PIN_A3 (28) -#define PIN_A4 (29) -#define PIN_A5 (30) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 14 - -// Other pins -#define PIN_AREF (24) -static const uint8_t AREF = PIN_AREF; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (18) -#define PIN_SERIAL_TX (19) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (21) -#define PIN_SPI_MOSI (22) -#define PIN_SPI_SCK (23) - -static const uint8_t SS = 20 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (2u) -#define PIN_WIRE_SCL (3u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/TinyBLE/pins_arduino.h b/variants/TinyBLE/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/TinyBLE/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/TinyBLE/variant.cpp b/variants/TinyBLE/variant.cpp deleted file mode 100644 index 02d405b6..00000000 --- a/variants/TinyBLE/variant.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31 -}; diff --git a/variants/TinyBLE/variant.h b/variants/TinyBLE/variant.h deleted file mode 100644 index 2ab0c0a7..00000000 --- a/variants/TinyBLE/variant.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_TINYBLE_ -#define _VARIANT_TINYBLE_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (32u) -//3 LEDS, 1 Button, 4 exposed pins -#define NUM_DIGITAL_PINS (8u) -#define NUM_ANALOG_INPUTS (4u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED1 (21) -#define PIN_LED2 (22) -#define PIN_LED3 (23) - -#define LED_BUILTIN PIN_LED1 - -// Buttons -#define PIN_BUTTON (17) - -/* - * Analog pins - */ -#define PIN_A0 (3) -#define PIN_A1 (4) -#define PIN_A2 (5) -#define PIN_A3 (6) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -#define ADC_RESOLUTION 10 - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (3) -#define PIN_SPI_MOSI (4) -#define PIN_SPI_SCK (5) - -static const uint8_t SS = 6 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -//MPU6050_INT_PIN (20) -#define PIN_WIRE_SDA (12) -#define PIN_WIRE_SCL (13) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (11) -#define PIN_SERIAL_TX (9) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/Waveshare_BLE400/pins_arduino.h b/variants/Waveshare_BLE400/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/Waveshare_BLE400/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/Waveshare_BLE400/variant.cpp b/variants/Waveshare_BLE400/variant.cpp deleted file mode 100644 index 02d405b6..00000000 --- a/variants/Waveshare_BLE400/variant.cpp +++ /dev/null @@ -1,55 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31 -}; diff --git a/variants/Waveshare_BLE400/variant.h b/variants/Waveshare_BLE400/variant.h deleted file mode 100644 index c640daab..00000000 --- a/variants/Waveshare_BLE400/variant.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_GENERIC_ -#define _VARIANT_GENERIC_ - -#include "nrf.h" - -/** Master clock frequency */ -#if defined(NRF52_SERIES) -#define VARIANT_MCK (64000000ul) -#else -#define VARIANT_MCK (16000000ul) -#endif - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (31u) -#define NUM_DIGITAL_PINS (31u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED1 (18) -#define PIN_LED2 (19) -#define PIN_LED3 (20) -#define PIN_LED4 (21) -#define PIN_LED5 (22) -#define LED_BUILTIN PIN_LED1 - -// Buttons -#define PIN_BUTTON1 (16) -#define PIN_BUTTON2 (17) - -/* - * Analog pins - */ -#define PIN_A0 (2) -#define PIN_A1 (3) -#define PIN_A2 (4) -#define PIN_A3 (5) -#define PIN_A4 (6) -#define PIN_A5 (7) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#ifdef NRF52 -#define ADC_RESOLUTION 14 -#else -#define ADC_RESOLUTION 10 -#endif - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (11) -#define PIN_SERIAL_TX (9) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (23) -#define PIN_SPI_MOSI (24) -#define PIN_SPI_SCK (25) - -static const uint8_t SS = 30 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (0u) -#define PIN_WIRE_SCL (1u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/bluey/pins_arduino.h b/variants/bluey/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/bluey/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/bluey/variant.cpp b/variants/bluey/variant.cpp deleted file mode 100644 index 4dcd9dd1..00000000 --- a/variants/bluey/variant.cpp +++ /dev/null @@ -1,85 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -/* - - A0 P0.02/AIN0 | 1 2 | P0.26 D0 - A1 P0.03/AIN1 | 3 4 | P0.27 D1 - A2 P0.04/AIN2 | 5 6 | P0.24/AIN4 A3 - D2 P0.22 | 7 8 | P0.29/AIN5 A4 - D3 P0.23 | 9 10 | P0.30/AIN6 A5 - D4 P0.24 | 11 12 | P0.31/AIN7 A6 - D5 P0.25 | 13 14 | Ex_vin - GND | 15 16 | 3v3 - GND | 17 18 | GND - - - button D6 - P0.16 - R D7 - P0.19 - G D8 - P0.18 - B D9 - P0.17 - - D10 SCL - P0.11 DRDYn - P0.12 D11 - D12 SDA - P0.13 INT - P0.14 D13 - D14 INT1 - P0.15 INT2 - P0.20 D15 - - RXD - P0.08 TXD - P0.06 - RTS - P0.05 CTS - P0.07 - - SS - P0.22 SCK - P0.25 - MISO - P0.24 MOSI - P0.23 -*/ - - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D15 - 26, - 27, - 22, // SS - 23, // MOSI - 24, // MISO - 25, // SCK - 16, // Button - 19, // R - 18, // G - 17, // B - 11, // SCL - 12, // DRDYn - 13, // SDA - 14, // INT - 15, // INT1 - 20, // INT2 - - // A0 - A6 - 2, - 3, - 4, - 24, - 29, - 30, - 31, - - // RX, TX, RTS, CTS - 8, - 6, - 5, - 7, -}; diff --git a/variants/bluey/variant.h b/variants/bluey/variant.h deleted file mode 100644 index 192a2f48..00000000 --- a/variants/bluey/variant.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_ELECTRONUT_BLUEY_ -#define _VARIANT_ELECTRONUT_BLUEY_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (27u) -#define NUM_DIGITAL_PINS (27u) -#define NUM_ANALOG_INPUTS (7u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LEDR (7) -#define PIN_LEDG (8) -#define PIN_LEDB (9) -#define LED_BUILTIN PIN_LEDR - -// Buttons -#define PIN_BUTTON (6) - -/* - * Analog pins - */ -#define PIN_A0 (16) -#define PIN_A1 (17) -#define PIN_A2 (18) -#define PIN_A3 (19) -#define PIN_A4 (20) -#define PIN_A5 (21) -#define PIN_A6 (22) - -static const uint8_t A0 = PIN_A0 ; // AIN0 / AREF / P0.02 -static const uint8_t A1 = PIN_A1 ; // AIN1 -static const uint8_t A2 = PIN_A2 ; // AIN2 -static const uint8_t A3 = PIN_A3 ; // AIN4 -static const uint8_t A4 = PIN_A4 ; // AIN5 -static const uint8_t A5 = PIN_A5 ; // AIN6 -static const uint8_t A6 = PIN_A6 ; // AIN7 -#define ADC_RESOLUTION 10 - -// Other pins -#define PIN_AREF (16) -static const uint8_t AREF = PIN_AREF; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (23) -#define PIN_SERIAL_TX (24) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (4) -#define PIN_SPI_MOSI (3) -#define PIN_SPI_SCK (5) - -static const uint8_t SS = 2 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (12u) -#define PIN_WIRE_SCL (10u) - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/hackaBLE/pins_arduino.h b/variants/hackaBLE/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/hackaBLE/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/hackaBLE/variant.cpp b/variants/hackaBLE/variant.cpp deleted file mode 100644 index 791a312d..00000000 --- a/variants/hackaBLE/variant.cpp +++ /dev/null @@ -1,78 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -/* - Top view - RX - D0 | P0.14 P0.27 | D7 - SDA - Tx - D1 | P0.13 P0.26 | D8 - SCL - D2 | P0.12 P0.25 | D9 - SS - D3 | P0.11 AIN3/P0.05 | D10 - A3 - MISO - D4 | P0.08 AIN2/P0.04 | D11 - A2 - MOSI - D5 | P0.07 AIN1/P0.03 | D12 - A1 - SCK - D6 | P0.06 AIN0/P0.02 | D13 - A0 - | NFC2/P0.10 Vin | - | NFC1/P0.09 Gnd | - - - Bottom view (smt pads) - D19 | P0.24 P0.23 | D14 - A4 - D20 | P0.28/AIN4 P0.22 | D15 - A5 - D21 | P0.29/AIN5 P0.18 | D16 - A6 - D22 | P0.30/AIN6 P0.16 | D17 - A7 - D23 | P0.31/AIN7 P0.15 | D18 - - - LEDs - Red - P0.19 | D24 - Green - P0.19 | D25 - Blue - P0.19 | D26 - LED_BUILTIN - -*/ - -const uint32_t g_ADigitalPinMap[] = { - 14, - 13, - 12, - 11, - 8, - 7, - 6, - 27, - 26, - 25, - 5, - 4, - 3, - 2, - 23, - 22, - 18, - 16, - 15, - 24, - 28, - 29, - 30, - 31, - 19, - 20, - 17, -}; diff --git a/variants/hackaBLE/variant.h b/variants/hackaBLE/variant.h deleted file mode 100644 index 0d11608d..00000000 --- a/variants/hackaBLE/variant.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_ELECTRONUT_HACKABLE_ -#define _VARIANT_ELECTRONUT_HACKABLE_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (27u) -#define NUM_DIGITAL_PINS (27u) -#define NUM_ANALOG_INPUTS (8u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LEDR (24) -#define PIN_LEDG (25) -#define PIN_LEDB (26) -#define LED_BUILTIN PIN_LEDB - -/* - * Analog pins - */ -#define PIN_A0 (13) -#define PIN_A1 (12) -#define PIN_A2 (11) -#define PIN_A3 (10) -#define PIN_A4 (20) -#define PIN_A5 (21) -#define PIN_A6 (22) -#define PIN_A7 (23) - -static const uint8_t A0 = PIN_A0 ; // AIN0 / AREF / P0.02 -static const uint8_t A1 = PIN_A1 ; // AIN1 -static const uint8_t A2 = PIN_A2 ; // AIN2 -static const uint8_t A3 = PIN_A3 ; // AIN3 -static const uint8_t A4 = PIN_A4 ; // AIN4 -static const uint8_t A5 = PIN_A5 ; // AIN5 -static const uint8_t A6 = PIN_A6 ; // AIN6 -static const uint8_t A7 = PIN_A7 ; // AIN7 -#define ADC_RESOLUTION 10 - -// Other pins -#define PIN_AREF (PIN_A0) -static const uint8_t AREF = PIN_AREF; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) -#define PIN_SERIAL_TX (1) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (4) -#define PIN_SPI_MOSI (5) -#define PIN_SPI_SCK (6) -#define PIN_SPI_SS (3) - -static const uint8_t SS = PIN_SPI_SS ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (7) -#define PIN_WIRE_SCL (8) - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/hackaBLE_v2/pins_arduino.h b/variants/hackaBLE_v2/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/hackaBLE_v2/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/hackaBLE_v2/variant.cpp b/variants/hackaBLE_v2/variant.cpp deleted file mode 100644 index e25feed7..00000000 --- a/variants/hackaBLE_v2/variant.cpp +++ /dev/null @@ -1,56 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - - -const uint32_t g_ADigitalPinMap[] = { - 0, - 1, - 2, - 3, - 4, - 5, - 6, - 7, - 8, - 9, - 10, - 11, - 12, - 13, - 14, - 15, - 16, - 17, - 18, - 19, - 20, - 21, - 22, - 23, - 24, - 25, - 26, - 27, - 28, - 29, - 30, - 31 -}; diff --git a/variants/hackaBLE_v2/variant.h b/variants/hackaBLE_v2/variant.h deleted file mode 100644 index 6f7d7c09..00000000 --- a/variants/hackaBLE_v2/variant.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_ELECTRONUT_HACKABLE_V2_ -#define _VARIANT_ELECTRONUT_HACKABLE_V2_ - -/** Master clock frequency */ -#define VARIANT_MCK (64000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (32u) -#define NUM_DIGITAL_PINS (32u) -#define NUM_ANALOG_INPUTS (8u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LEDR (19) -#define PIN_LEDG (20) -#define PIN_LEDB (17) -#define LED_BUILTIN PIN_LEDB - -/* - * Analog pins - */ -#define PIN_A0 (2) -#define PIN_A1 (3) -#define PIN_A2 (4) -#define PIN_A3 (5) -#define PIN_A4 (28) -#define PIN_A5 (29) -#define PIN_A6 (30) -#define PIN_A7 (31) - -static const uint8_t A0 = PIN_A0 ; // AIN0 / AREF / P0.02 -static const uint8_t A1 = PIN_A1 ; // AIN1 -static const uint8_t A2 = PIN_A2 ; // AIN2 -static const uint8_t A3 = PIN_A3 ; // AIN3 -static const uint8_t A4 = PIN_A4 ; // AIN4 -static const uint8_t A5 = PIN_A5 ; // AIN5 -static const uint8_t A6 = PIN_A6 ; // AIN6 -static const uint8_t A7 = PIN_A7 ; // AIN7 -#define ADC_RESOLUTION 10 - -// Other pins -#define PIN_AREF (PIN_A0) -static const uint8_t AREF = PIN_AREF; - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (7) -#define PIN_SERIAL_TX (8) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (11) -#define PIN_SPI_MOSI (12) -#define PIN_SPI_SCK (13) -#define PIN_SPI_SS (14) - -static const uint8_t SS = PIN_SPI_SS ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (2) -#define PIN_WIRE_SCL (3) - -/* - * Reset Button at P0.21 - */ -#define RESET_PIN 21 - -#ifdef __cplusplus -} -#endif - -/*---------------------------------------------------------------------------- - * Arduino objects - C++ only - *----------------------------------------------------------------------------*/ - -#endif diff --git a/variants/nRF51Dongle/pins_arduino.h b/variants/nRF51Dongle/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/nRF51Dongle/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/nRF51Dongle/variant.cpp b/variants/nRF51Dongle/variant.cpp deleted file mode 100644 index abaa1983..00000000 --- a/variants/nRF51Dongle/variant.cpp +++ /dev/null @@ -1,37 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - //LEDs - 21, - 22, - 23, - //A0-6 - 15, - 16, - 17, - 18, - 19, - 20, - //Serial - 9, - 11 -}; diff --git a/variants/nRF51Dongle/variant.h b/variants/nRF51Dongle/variant.h deleted file mode 100644 index 15064678..00000000 --- a/variants/nRF51Dongle/variant.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_NRF51_DONGLE_ -#define _VARIANT_NRF51_DONGLE_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (11u) -#define NUM_DIGITAL_PINS (11u) -#define NUM_ANALOG_INPUTS (6u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED1 (21) -#define PIN_LED2 (22) -#define PIN_LED3 (23) - -#define LED_BUILTIN PIN_LED1 - -/* - * Analog pins - */ -#define PIN_A0 (15) -#define PIN_A1 (16) -#define PIN_A2 (17) -#define PIN_A3 (18) -#define PIN_A4 (19) -#define PIN_A5 (20) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -static const uint8_t A2 = PIN_A2 ; -static const uint8_t A3 = PIN_A3 ; -static const uint8_t A4 = PIN_A4 ; -static const uint8_t A5 = PIN_A5 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (11) -#define PIN_SERIAL_TX (9) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/variants/nRF52DK/variant.cpp b/variants/nRF52DK/variant.cpp index 60a1cc1c..02d405b6 100644 --- a/variants/nRF52DK/variant.cpp +++ b/variants/nRF52DK/variant.cpp @@ -20,7 +20,17 @@ #include "variant.h" const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, 11, 12, 13, @@ -29,30 +39,17 @@ const uint32_t g_ADigitalPinMap[] = { 16, 17, 18, - - // D8 - D13 19, 20, + 21, 22, 23, 24, 25, - - // A0 - A7 - 3, - 4, + 26, + 27, 28, 29, 30, - 31, - 5, // AIN3 (P0.05) - 2, // AIN0 (P0.02) / AREF - - // SDA, SCL - 26, - 27, - - // RX, TX - 8, - 6 + 31 }; diff --git a/variants/nRF52DK/variant.h b/variants/nRF52DK/variant.h index cfbd3002..3213d170 100644 --- a/variants/nRF52DK/variant.h +++ b/variants/nRF52DK/variant.h @@ -32,65 +32,65 @@ extern "C" #endif // __cplusplus // Number of pins defined in PinDescription array -#define PINS_COUNT (26u) -#define NUM_DIGITAL_PINS (20u) -#define NUM_ANALOG_INPUTS (8u) +#define PINS_COUNT (32u) +#define NUM_DIGITAL_PINS (28u) +#define NUM_ANALOG_INPUTS (4u) #define NUM_ANALOG_OUTPUTS (0u) -// LEDs -#define PIN_LED1 (6) -#define PIN_LED2 (7) -#define PIN_LED3 (8) -#define PIN_LED4 (9) -#define LED_BUILTIN PIN_LED1 - -// Buttons -#define PIN_BUTTON1 (2) -#define PIN_BUTTON2 (3) -#define PIN_BUTTON3 (4) -#define PIN_BUTTON4 (5) - /* * Analog pins */ -#define PIN_A0 (14) -#define PIN_A1 (15) -#define PIN_A2 (16) -#define PIN_A3 (17) -#define PIN_A4 (18) -#define PIN_A5 (19) -#define PIN_A6 (20) /* AIN3 (P0.05) */ -#define PIN_A7 (21) /* AIN0 (P0.02) / AREF */ - -static const uint8_t A0 = PIN_A0 ; // AIN1 -static const uint8_t A1 = PIN_A1 ; // AIN2 -static const uint8_t A2 = PIN_A2 ; // AIN4 -static const uint8_t A3 = PIN_A3 ; // AIN5 -static const uint8_t A4 = PIN_A4 ; // AIN6 -static const uint8_t A5 = PIN_A5 ; // AIN7 -static const uint8_t A6 = PIN_A6 ; // AIN3 (P0.05) -static const uint8_t A7 = PIN_A7 ; // AIN0 (P0.02) / AREF +#define PIN_A0 (2) +#define PIN_A1 (3) +#define PIN_A2 (4) +#define PIN_A3 (5) +#define PIN_A4 (28) +#define PIN_A5 (29) +#define PIN_A6 (30) /* AIN3 (P0.05) */ +#define PIN_A7 (31) /* AIN0 (P0.02) / AREF */ + +static const uint8_t A0 = PIN_A0 ; +static const uint8_t A1 = PIN_A1 ; +static const uint8_t A2 = PIN_A2 ; +static const uint8_t A3 = PIN_A3 ; +static const uint8_t A4 = PIN_A4 ; +static const uint8_t A5 = PIN_A5 ; +static const uint8_t A6 = PIN_A6 ; +static const uint8_t A7 = PIN_A7 ; #define ADC_RESOLUTION 14 +// LEDs +#define PIN_LED1 (25) +#define PIN_LED2 (26) +#define PIN_LED3 (27) +#define PIN_LED_ROUGE (25) +#define PIN_LED_BLEU (26) +#define PIN_LED_VERT (27) +#define LED_BUILTIN PIN_LED1 + +// Buttons +#define PIN_BUTTON1 (PIN_A5) +#define PIN_BUTTON2 (PIN_A4) + // Other pins -#define PIN_AREF (21) +#define PIN_AREF (PIN_A0) static const uint8_t AREF = PIN_AREF; /* * Serial interfaces */ // Serial -#define PIN_SERIAL_RX (24) -#define PIN_SERIAL_TX (25) +#define PIN_SERIAL_RX (7) +#define PIN_SERIAL_TX (8) /* * SPI Interfaces */ #define SPI_INTERFACES_COUNT 1 -#define PIN_SPI_MISO (12) -#define PIN_SPI_MOSI (11) -#define PIN_SPI_SCK (13) +#define PIN_SPI_MISO (16) +#define PIN_SPI_MOSI (15) +#define PIN_SPI_SCK (17) static const uint8_t SS = 10 ; static const uint8_t MOSI = PIN_SPI_MOSI ; @@ -100,13 +100,17 @@ static const uint8_t SCK = PIN_SPI_SCK ; /* * Wire Interfaces */ -#define WIRE_INTERFACES_COUNT 1 +#define WIRE_INTERFACES_COUNT 2 -#define PIN_WIRE_SDA (22u) -#define PIN_WIRE_SCL (23u) +#define PIN_WIRE_SDA (14) +#define PIN_WIRE_SCL (13) +#define PIN_WIRE1_SDA (12) +#define PIN_WIRE1_SCL (11) static const uint8_t SDA = PIN_WIRE_SDA; static const uint8_t SCL = PIN_WIRE_SCL; +static const uint8_t SDA1 = PIN_WIRE1_SDA; +static const uint8_t SCL1 = PIN_WIRE1_SCL; /* * Reset Button at P0.21 diff --git a/variants/ng-beacon/pins_arduino.h b/variants/ng-beacon/pins_arduino.h deleted file mode 100644 index 3ef4d4a9..00000000 --- a/variants/ng-beacon/pins_arduino.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -// API compatibility -#include "variant.h" diff --git a/variants/ng-beacon/variant.cpp b/variants/ng-beacon/variant.cpp deleted file mode 100644 index 311f5f76..00000000 --- a/variants/ng-beacon/variant.cpp +++ /dev/null @@ -1,36 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#include "variant.h" - -const uint32_t g_ADigitalPinMap[] = { - // D0 - D7 - 8, - 9, - 12, - 17, - 19, - 25, - 28, - 29, - - // A0 - A1 - 26, - 27, -}; diff --git a/variants/ng-beacon/variant.h b/variants/ng-beacon/variant.h deleted file mode 100644 index cc465e33..00000000 --- a/variants/ng-beacon/variant.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - Copyright (c) 2014-2015 Arduino LLC. All right reserved. - Copyright (c) 2016 Sandeep Mistry All right reserved. - This library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - This library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - See the GNU Lesser General Public License for more details. - You should have received a copy of the GNU Lesser General Public - License along with this library; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -*/ - -#ifndef _VARIANT_NG_BEACON_ -#define _VARIANT_NG_BEACON_ - -/** Master clock frequency */ -#define VARIANT_MCK (16000000ul) - -/*---------------------------------------------------------------------------- - * Headers - *----------------------------------------------------------------------------*/ - -#include "WVariant.h" - -#ifdef __cplusplus -extern "C" -{ -#endif // __cplusplus - -// Number of pins defined in PinDescription array -#define PINS_COUNT (10u) -#define NUM_DIGITAL_PINS (10u) -#define NUM_ANALOG_INPUTS (2u) -#define NUM_ANALOG_OUTPUTS (0u) - -// LEDs -#define PIN_LED (2) -#define LED_BUILTIN PIN_LED - -/* - * Analog pins - */ -#define PIN_A0 (8) -#define PIN_A1 (9) - -static const uint8_t A0 = PIN_A0 ; -static const uint8_t A1 = PIN_A1 ; -#define ADC_RESOLUTION 10 - -/* - * Serial interfaces - */ -// Serial -#define PIN_SERIAL_RX (0) -#define PIN_SERIAL_TX (1) - -/* - * SPI Interfaces - */ -#define SPI_INTERFACES_COUNT 1 - -#define PIN_SPI_MISO (5) -#define PIN_SPI_MOSI (8) -#define PIN_SPI_SCK (9) - -static const uint8_t SS = 3 ; -static const uint8_t MOSI = PIN_SPI_MOSI ; -static const uint8_t MISO = PIN_SPI_MISO ; -static const uint8_t SCK = PIN_SPI_SCK ; - -/* - * Wire Interfaces - */ -#define WIRE_INTERFACES_COUNT 1 - -#define PIN_WIRE_SDA (6u) -#define PIN_WIRE_SCL (7u) - -static const uint8_t SDA = PIN_WIRE_SDA; -static const uint8_t SCL = PIN_WIRE_SCL; - -#ifdef __cplusplus -} -#endif - -#endif