Updating cores to Arduino samd 1.6.11 cores

Author: Jim Lindblom

sparkfun/samd/cores/arduino/Arduino.h

@@ -55,6 +55,10 @@ extern "C"{
 
 void yield( void ) ;
 
+/* system functions */
+int main( void );
+void init( void );
+
 /* sketch */
 void setup( void ) ;
 void loop( void ) ;

sparkfun/samd/cores/arduino/Reset.cpp

@@ -24,7 +24,15 @@ extern "C" {
 #endif
 
 #define NVM_MEMORY ((volatile uint16_t *)0x000000)
+
+#if (ARDUINO_SAMD_VARIANT_COMPLIANCE >= 10610)
+
+extern const uint32_t __text_start__;
+#define APP_START ((volatile uint32_t)(&__text_start__) + 4)
+
+#else
 #define APP_START 0x00002004
+#endif
 
 static inline bool nvmReady(void) {
         return NVMCTRL->INTFLAG.reg & NVMCTRL_INTFLAG_READY;
@@ -35,6 +43,13 @@ static void banzai() {
 	// Disable all interrupts
 	__disable_irq();
 
+	// Avoid erasing the application if APP_START is < than the minimum bootloader size
+	// This could happen if without_bootloader linker script was chosen
+	// Minimum bootloader size in SAMD21 family is 512bytes (RM section 22.6.5)
+	if (APP_START < (0x200 + 4)) {
+		goto reset;
+	}
+
 	// Erase application
 	while (!nvmReady())
 		;
@@ -44,6 +59,7 @@ static void banzai() {
 	while (!nvmReady())
 		;
 
+reset:
 	// Reset the device
 	NVIC_SystemReset() ;
 

sparkfun/samd/cores/arduino/USB/SAMD21_USBDevice.h

@@ -106,7 +106,7 @@ class USBDevice_SAMD21G18x {
 	inline void epBank0EnableStalled(ep_t ep)          { usb.DeviceEndpoint[ep].EPINTENSET.bit.STALL0 = 1; }
 	inline void epBank1EnableStalled(ep_t ep)          { usb.DeviceEndpoint[ep].EPINTENSET.bit.STALL1 = 1; }
 	inline void epBank0EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
-	inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT0 = 1; }
+	inline void epBank1EnableTransferComplete(ep_t ep) { usb.DeviceEndpoint[ep].EPINTENSET.bit.TRCPT1 = 1; }
 
 	inline void epBank0DisableSetupReceived(ep_t ep)    { usb.DeviceEndpoint[ep].EPINTENCLR.bit.RXSTP = 1; }
 	inline void epBank0DisableStalled(ep_t ep)          { usb.DeviceEndpoint[ep].EPINTENCLR.bit.STALL0 = 1; }

sparkfun/samd/cores/arduino/USB/USBDesc.h

@@ -41,7 +41,7 @@
 #define CDC_TX CDC_ENDPOINT_IN
 #endif
 
-#define ISERIAL_MAX_LEN        20
+#define ISERIAL_MAX_LEN        33
 
 // Defined string description
 #define IMANUFACTURER	1

sparkfun/samd/cores/arduino/startup.c

@@ -38,6 +38,7 @@
 // Constants for Clock generators
 #define GENERIC_CLOCK_GENERATOR_MAIN      (0u)
 #define GENERIC_CLOCK_GENERATOR_XOSC32K   (1u)
+#define GENERIC_CLOCK_GENERATOR_OSC32K    (1u)
 #define GENERIC_CLOCK_GENERATOR_OSCULP32K (2u) /* Initialized at reset for WDT */
 #define GENERIC_CLOCK_GENERATOR_OSC8M     (3u)
 // Constants for Clock multiplexers
@@ -51,6 +52,24 @@ void SystemInit( void )
   /* Turn on the digital interface clock */
   PM->APBAMASK.reg |= PM_APBAMASK_GCLK ;
 
+
+#if defined(CRYSTALLESS)
+
+  /* ----------------------------------------------------------------------------------------------
+   * 1) Enable OSC32K clock (Internal 32.768Hz oscillator)
+   */
+
+  uint32_t calib = (*((uint32_t *) FUSES_OSC32K_CAL_ADDR) & FUSES_OSC32K_CAL_Msk) >> FUSES_OSC32K_CAL_Pos;
+
+  SYSCTRL->OSC32K.reg = SYSCTRL_OSC32K_CALIB(calib) |
+                        SYSCTRL_OSC32K_STARTUP( 0x6u ) | // cf table 15.10 of product datasheet in chapter 15.8.6
+                        SYSCTRL_OSC32K_EN32K |
+                        SYSCTRL_OSC32K_ENABLE;
+
+  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) == 0 ); // Wait for oscillator stabilization
+
+#else // has crystal
+
   /* ----------------------------------------------------------------------------------------------
    * 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
    */
@@ -63,6 +82,8 @@ void SystemInit( void )
     /* Wait for oscillator stabilization */
   }
 
+#endif
+
   /* Software reset the module to ensure it is re-initialized correctly */
   /* Note: Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
    * CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete, as described in chapter 13.8.1
@@ -85,8 +106,12 @@ void SystemInit( void )
   }
 
   /* Write Generic Clock Generator 1 configuration */
-  GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_XOSC32K ) | // Generic Clock Generator 1
+  GCLK->GENCTRL.reg = GCLK_GENCTRL_ID( GENERIC_CLOCK_GENERATOR_OSC32K ) | // Generic Clock Generator 1
+#if defined(CRYSTALLESS)
+                      GCLK_GENCTRL_SRC_OSC32K | // Selected source is Internal 32KHz Oscillator
+#else
                       GCLK_GENCTRL_SRC_XOSC32K | // Selected source is External 32KHz Oscillator
+#endif
 //                      GCLK_GENCTRL_OE | // Output clock to a pin for tests
                       GCLK_GENCTRL_GENEN ;
 
@@ -130,6 +155,41 @@ void SystemInit( void )
     /* Wait for synchronization */
   }
 
+#if defined(CRYSTALLESS)
+
+  #define NVM_SW_CALIB_DFLL48M_COARSE_VAL 58
+  #define NVM_SW_CALIB_DFLL48M_FINE_VAL   64
+
+  // Turn on DFLL
+  uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) + (NVM_SW_CALIB_DFLL48M_COARSE_VAL / 32)) >> (NVM_SW_CALIB_DFLL48M_COARSE_VAL % 32) )
+                   & ((1 << 6) - 1);
+  if (coarse == 0x3f) {
+    coarse = 0x1f;
+  }
+  uint32_t fine =( *((uint32_t *)(NVMCTRL_OTP4) + (NVM_SW_CALIB_DFLL48M_FINE_VAL / 32)) >> (NVM_SW_CALIB_DFLL48M_FINE_VAL % 32) )
+                 & ((1 << 10) - 1);
+  if (fine == 0x3ff) {
+    fine = 0x1ff;
+  }
+
+  SYSCTRL->DFLLVAL.bit.COARSE = coarse;
+  SYSCTRL->DFLLVAL.bit.FINE = fine;
+  /* Write full configuration to DFLL control register */
+  SYSCTRL->DFLLCTRL.reg =  SYSCTRL_DFLLCTRL_USBCRM | /* USB correction */
+                           SYSCTRL_DFLLCTRL_CCDIS |
+                           SYSCTRL_DFLLCTRL_WAITLOCK |
+                           SYSCTRL_DFLLCTRL_QLDIS ; /* Disable Quick lock */
+
+  while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
+  {
+    /* Wait for synchronization */
+  }
+
+  /* Enable the DFLL */
+  SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE ;
+
+#else   // has crystal
+
   /* Write full configuration to DFLL control register */
   SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE | /* Enable the closed loop mode */
                            SYSCTRL_DFLLCTRL_WAITLOCK |
@@ -149,6 +209,8 @@ void SystemInit( void )
     /* Wait for locks flags */
   }
 
+#endif
+
   while ( (SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0 )
   {
     /* Wait for synchronization */