SystemVerilog constraints solve before with multiple variables

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SystemVerilog allows the following syntax which allows you to use multiple variables in a solve-before statement.

constraint c_solve {
     solve m, n before k, j;
     solve x, y before z;
}

From section 18.5.10 of the SystemVerilog LRM 1800-2017

constraint_block_item ::=
    solve solve_before_list before solve_before_list ;
   | constraint_expression
solve_before_list ::= solve_before_primary { , solve_before_primary }
solve_before_primary ::= [ implicit_class_handle . | class_scope ] hierarchical_identifier select