[Gotcha] Using functions in SystemVerilog constraints #15
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While SystemVerilog does allow using functions within constraints, you have to be careful while using it.
Consider this example from section 18.5.12 of SystemVerilog LRM 1800-2017:
Here are some things to note - once again from the LRM,
So watch out while using functions in constraints, it could end up behaving differently from your expectations
Also, the Cadence simulator throws a warning like this when you use a function in your constraint:
Here's another good article:
https://www.amiq.com/consulting/2015/03/12/gotcha-function-calls-in-systemverilog-constraints/
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