modified from ASIC website

Author: vlsi1217

verilog_tutorial/cnt_tb.v

@@ -0,0 +1,38 @@
+//`include "first_counter.v"         /*don't need to include it if do the iverilog compile*/
+module first_counter_tb();
+// Declare inputs as regs and outputs as wires
+reg clock, reset, enable;
+wire [3:0] counter_out;
+
+// Initialize all variables
+initial begin        
+  $display ("time\t clk reset enable counter");         //Need to add these two lines to 
+  $dumpfile ("first_counter_tb.vcd");                   //generate VCD file so as to gtkwave it
+  $dumpvars (1, first_counter_tb);	
+  $monitor ("%g\t %b   %b     %b      %b", 
+	  $time, clock, reset, enable, counter_out);	
+  clock = 1;       // initial value of clock
+  reset = 0;       // initial value of reset
+  enable = 0;      // initial value of enable
+  #5 reset = 1;    // Assert the reset
+  #10 reset = 0;   // De-assert the reset
+  #10 enable = 1;  // Assert enable
+  #150 enable = 0; // De-assert enable
+  #5 $finish;      // Terminate simulation
+end
+
+// Clock generator
+always begin
+  #5 clock = ~clock; // Toggle clock every 5 ticks
+end
+
+// Connect DUT to test bench
+first_counter U_counter (
+clock,
+reset,
+enable,
+counter_out
+);
+
+endmodule
+

verilog_tutorial/count.pdf

@@ -0,0 +1,48 @@
+//-----------------------------------------------------
+// This is my second Verilog Design
+// Design Name : first_counter
+// File Name : first_counter.v
+// Function : This is a 4 bit up-counter with
+// Synchronous active high reset and
+// with active high enable signal
+//-----------------------------------------------------
+module first_counter (
+clock , // Clock input of the design
+reset , // active high, synchronous Reset input
+enable , // Active high enable signal for counter
+counter_out // 4 bit vector output of the counter
+); // End of port list
+//-------------Input Ports-----------------------------
+input clock ;
+input reset ;
+input enable ;
+//-------------Output Ports----------------------------
+output [3:0] counter_out ;
+//-------------Input ports Data Type-------------------
+// By rule all the input ports should be wires   
+wire clock ;
+wire reset ;
+wire enable ;
+//-------------Output Ports Data Type------------------
+// Output port can be a storage element (reg) or a wire
+reg [3:0] counter_out ;
+
+//------------Code Starts Here-------------------------
+// Since this counter is a positive edge trigged one,
+// We trigger the below block with respect to positive
+// edge of the clock.
+always @ (posedge clock)
+begin : COUNTER // Block Name
+  // At every rising edge of clock we check if reset is active
+  // If active, we load the counter output with 4'b0000
+  if (reset == 1'b1) begin
+    counter_out <= #1 4'b0000;
+  end
+  // If enable is active, then we increment the counter
+  else if (enable == 1'b1) begin
+    counter_out <= #1 counter_out + 1;
+  end
+end // End of Block COUNTER
+
+endmodule // End of Module counter
+