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troyhackstroyhacks
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Test build with newer fixes to 5.3
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160 files changed

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‎esp32p4/bin/bootloader_qio_80m.elf

18.1 KB
Binary file not shown.

‎esp32p4/flags/defines

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
1-
-DESP_PLATFORM -DIDF_VER=\"v5.3.1-244-g4d0db7045d-dirty\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DSOC_XTAL_FREQ_MHZ=CONFIG_XTAL_FREQ -DUNITY_INCLUDE_CONFIG_H -D_GLIBCXX_HAVE_POSIX_SEMAPHORE -D_GLIBCXX_USE_POSIX_SEMAPHORE -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DESP32=ESP32
1+
-DESP_PLATFORM -DIDF_VER=\"v5.3.1-638-ga0f798cfc4-dirty\" -DMBEDTLS_CONFIG_FILE=\"mbedtls/esp_config.h\" -DSOC_MMU_PAGE_SIZE=CONFIG_MMU_PAGE_SIZE -DSOC_XTAL_FREQ_MHZ=CONFIG_XTAL_FREQ -DUNITY_INCLUDE_CONFIG_H -D_GLIBCXX_HAVE_POSIX_SEMAPHORE -D_GLIBCXX_USE_POSIX_SEMAPHORE -D_GNU_SOURCE -D_POSIX_READER_WRITER_LOCKS -DESP32=ESP32

‎esp32p4/include/efuse/esp32p4/include/esp_efuse_table.h

Lines changed: 49 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ extern "C" {
1010

1111
#include "esp_efuse.h"
1212

13-
// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381
13+
// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
1414
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
1515
// If you want to change some fields, you need to change esp_efuse_table.csv file
1616
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -19,6 +19,29 @@ extern "C" {
1919

2020
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
2121
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
22+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
23+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
24+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
25+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
26+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[];
27+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
28+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
29+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
30+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
31+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
32+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
33+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
34+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
35+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
36+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
37+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
38+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[];
39+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[];
40+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[];
41+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[];
42+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[];
43+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[];
44+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[];
2245
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
2346
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
2447
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
@@ -35,7 +58,26 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
3558
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
3659
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
3760
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
61+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
62+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
3863
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
64+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
65+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[];
66+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
67+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
68+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
69+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
70+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
71+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
72+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
73+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
74+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
75+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
76+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
77+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
78+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
79+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
80+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[];
3981
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
4082
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
4183
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
@@ -45,11 +87,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
4587
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
4688
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
4789
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
48-
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
49-
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
50-
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
5190
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
52-
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[];
91+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
5392
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
5493
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
5594
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
@@ -73,6 +112,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
73112
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
74113
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
75114
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
115+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
116+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
117+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
118+
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
76119
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
77120
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
78121
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
@@ -162,11 +205,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
162205
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
163206
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
164207
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
165-
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
166-
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
167-
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
168208
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
169-
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[];
209+
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
170210
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
171211
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
172212
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];

‎esp32p4/include/esp_coex/include/esp_coexist.h

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -116,7 +116,7 @@ const char *esp_coex_version_get(void);
116116
* @deprecated Use esp_coex_status_bit_set() and esp_coex_status_bit_clear() instead.
117117
* Set coexist preference of performance
118118
* For example, if prefer to bluetooth, then it will make A2DP(play audio via classic bt)
119-
* more smooth while wifi is runnning something.
119+
* more smooth while wifi is running something.
120120
* If prefer to wifi, it will do similar things as prefer to bluetooth.
121121
* Default, it prefer to balance.
122122
*
@@ -219,6 +219,15 @@ esp_err_t esp_external_coex_set_validate_high(bool is_high_valid);
219219
esp_err_t esp_coex_wifi_i154_enable(void);
220220
#endif
221221

222+
#if CONFIG_ESP_COEX_GPIO_DEBUG
223+
/**
224+
* @brief Enable coexist GPIO debug.
225+
* To fully enable this feature, make sure functions in rom_funcs are out of ROM.
226+
* @return : ESP_OK - success, other - failed
227+
*/
228+
esp_err_t esp_coexist_debug_init(void);
229+
#endif
230+
222231
#ifdef __cplusplus
223232
}
224233
#endif

‎esp32p4/include/esp_coex/include/private/esp_coexist_adapter.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ typedef struct {
4646
void (* _timer_done)(void *ptimer);
4747
void (* _timer_setfn)(void *ptimer, void *pfunction, void *parg);
4848
void (* _timer_arm_us)(void *ptimer, uint32_t us, bool repeat);
49+
int (* _debug_matrix_init)(int event, int signal, bool rev);
50+
int (* _xtal_freq_get)(void);
4951
int32_t _magic;
5052
} coex_adapter_funcs_t;
5153

‎esp32p4/include/esp_coex/include/private/esp_coexist_debug.h

Lines changed: 152 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,152 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#pragma once
8+
9+
#include "sdkconfig.h"
10+
11+
#if CONFIG_ESP_COEX_GPIO_DEBUG
12+
#include "esp_err.h"
13+
#include "stdbool.h"
14+
#include "soc/soc_caps.h"
15+
16+
#define COEX_GPIO_DEBUG_IO_INVALID SOC_GPIO_PIN_COUNT
17+
18+
/* Debug signal */
19+
#define COEX_GPIO_DEBUG_SIG_RES_US 10
20+
typedef enum {
21+
COEX_GPIO_DEBUG_SIG_POSE,
22+
COEX_GPIO_DEBUG_SIG_NEGA,
23+
} coex_gpio_debug_sig_t;
24+
#define COEX_GPIO_DEBUG_SIG_TO_DURATION(sig) ((sig - COEX_GPIO_DEBUG_SIG_NEGA) * COEX_GPIO_DEBUG_SIG_RES_US)
25+
#define COEX_GPIO_DEBUG_SIG_CHECK_US 100
26+
27+
/* User diagram */
28+
#ifdef CONFIG_ESP_COEX_GPIO_DEBUG_DIAG_GENERAL
29+
#define COEX_GPIO_DEBUG_DIAG_GENERAL 1
30+
#elif defined(CONFIG_ESP_COEX_GPIO_DEBUG_DIAG_WIFI)
31+
#define COEX_GPIO_DEBUG_DIAG_WIFI 1
32+
#endif
33+
34+
/* User configuration validity check */
35+
#define COEX_GPIO_DEBUG_IO_COUNT_MAX 12
36+
#define COEX_GPIO_DEBUG_IO_COUNT CONFIG_ESP_COEX_GPIO_DEBUG_IO_COUNT
37+
38+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX0)
39+
#define COEX_GPIO_DEBUG_IO_IDX0 COEX_GPIO_DEBUG_IO_INVALID
40+
#else
41+
#define COEX_GPIO_DEBUG_IO_IDX0 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX0
42+
#endif
43+
44+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX1)
45+
#define COEX_GPIO_DEBUG_IO_IDX1 COEX_GPIO_DEBUG_IO_INVALID
46+
#else
47+
#define COEX_GPIO_DEBUG_IO_IDX1 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX1
48+
#endif
49+
50+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX2)
51+
#define COEX_GPIO_DEBUG_IO_IDX2 COEX_GPIO_DEBUG_IO_INVALID
52+
#else
53+
#define COEX_GPIO_DEBUG_IO_IDX2 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX2
54+
#endif
55+
56+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX3)
57+
#define COEX_GPIO_DEBUG_IO_IDX3 COEX_GPIO_DEBUG_IO_INVALID
58+
#else
59+
#define COEX_GPIO_DEBUG_IO_IDX3 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX3
60+
#endif
61+
62+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX4)
63+
#define COEX_GPIO_DEBUG_IO_IDX4 COEX_GPIO_DEBUG_IO_INVALID
64+
#else
65+
#define COEX_GPIO_DEBUG_IO_IDX4 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX4
66+
#endif
67+
68+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX5)
69+
#define COEX_GPIO_DEBUG_IO_IDX5 COEX_GPIO_DEBUG_IO_INVALID
70+
#else
71+
#define COEX_GPIO_DEBUG_IO_IDX5 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX5
72+
#endif
73+
74+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX6)
75+
#define COEX_GPIO_DEBUG_IO_IDX6 COEX_GPIO_DEBUG_IO_INVALID
76+
#else
77+
#define COEX_GPIO_DEBUG_IO_IDX6 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX6
78+
#endif
79+
80+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX7)
81+
#define COEX_GPIO_DEBUG_IO_IDX7 COEX_GPIO_DEBUG_IO_INVALID
82+
#else
83+
#define COEX_GPIO_DEBUG_IO_IDX7 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX7
84+
#endif
85+
86+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX8)
87+
#define COEX_GPIO_DEBUG_IO_IDX8 COEX_GPIO_DEBUG_IO_INVALID
88+
#else
89+
#define COEX_GPIO_DEBUG_IO_IDX8 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX8
90+
#endif
91+
92+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX9)
93+
#define COEX_GPIO_DEBUG_IO_IDX9 COEX_GPIO_DEBUG_IO_INVALID
94+
#else
95+
#define COEX_GPIO_DEBUG_IO_IDX9 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX9
96+
#endif
97+
98+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX10)
99+
#define COEX_GPIO_DEBUG_IO_IDX10 COEX_GPIO_DEBUG_IO_INVALID
100+
#else
101+
#define COEX_GPIO_DEBUG_IO_IDX10 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX10
102+
#endif
103+
104+
#if !defined(CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX11)
105+
#define COEX_GPIO_DEBUG_IO_IDX11 COEX_GPIO_DEBUG_IO_INVALID
106+
#else
107+
#define COEX_GPIO_DEBUG_IO_IDX11 CONFIG_ESP_COEX_GPIO_DEBUG_IO_IDX11
108+
#endif
109+
110+
/* wifi callback -> debug */
111+
void wifi_set_gpio_debug_cb(void (* cb)(int, coex_gpio_debug_sig_t));
112+
int wifi_gpio_debug_max_event_get(void);
113+
114+
/* functions to check if in ROM */
115+
void lmacProcessTxComplete(void);
116+
void lmacTxFrame(void);
117+
void pm_update_by_connectionless_status(void);
118+
void pm_sleep(void);
119+
void pm_dream(void);
120+
void pm_beacon_monitor_timeout_process(void);
121+
void pm_connectionless_wake_window_timeout_process(void);
122+
void pm_coex_schm_process(void);
123+
void pm_tbtt_process(void);
124+
void pm_rx_beacon_process(void);
125+
void ppTask(void);
126+
void wDev_IndicateFrame(void);
127+
void pm_check_state(void);
128+
void pm_tx_null_data_done_process(void);
129+
void pm_start(void);
130+
void pm_stop(void);
131+
void pm_disconnected_wake(void);
132+
133+
/* coex callback -> debug */
134+
void coex_set_gpio_debug_cb(void (*cb)(int, coex_gpio_debug_sig_t));
135+
int coex_gpio_debug_max_event_get(void);
136+
esp_err_t coex_gpio_debug_matrix_init(void);
137+
138+
/* debug -> coex wrapper */
139+
esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev);
140+
141+
/* debug <-> diagram */
142+
void wifi_bind_io_to_evt(uint8_t io_idx, uint8_t evt);
143+
void coex_bind_io_to_evt(uint8_t io_idx, uint8_t evt);
144+
void diagram_bind_io_to_evt(void);
145+
146+
/* coex -> debug
147+
* configure single gpio debug event */
148+
esp_err_t coex_gpio_debug_matrix_config(int event);
149+
/* debug -> internal use */
150+
esp_err_t esp_coexist_gpio_debug_matrix_config(int event);
151+
152+
#endif

‎esp32p4/include/esp_coex/include/private/esp_coexist_internal.h

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,16 @@ typedef enum {
2828
COEX_SCHM_CALLBACK_TYPE_I154,
2929
} coex_schm_callback_type_t;
3030

31+
typedef enum {
32+
COEX_SCHM_ST_TYPE_WIFI = 0,
33+
COEX_SCHM_ST_TYPE_BLE,
34+
COEX_SCHM_ST_TYPE_BT,
35+
} coex_schm_st_type_t;
36+
37+
#define COEX_STATUS_GET_WIFI_BITMAP (1 << COEX_SCHM_ST_TYPE_WIFI)
38+
#define COEX_STATUS_GET_BLE_BITMAP (1 << COEX_SCHM_ST_TYPE_BLE)
39+
#define COEX_STATUS_GET_BT_BITMAP (1 << COEX_SCHM_ST_TYPE_BT)
40+
3141
typedef void (* coex_func_cb_t)(uint32_t event, int sched_cnt);
3242
typedef esp_err_t (* coex_set_lpclk_source_callback_t)(void);
3343
typedef void (* coex_wifi_channel_change_cb_t)(uint8_t primary, uint8_t secondary);
@@ -94,9 +104,11 @@ esp_err_t coex_preference_set(coex_prefer_t prefer);
94104

95105
/**
96106
* @brief Get software coexist status.
107+
*
108+
* @param bitmap : bitmap of the module getting status.
97109
* @return : software coexist status
98110
*/
99-
uint32_t coex_status_get(void);
111+
uint32_t coex_status_get(uint8_t bitmap);
100112

101113
/**
102114
* @brief WiFi requests coexistence.

‎esp32p4/include/esp_driver_parlio/include/driver/parlio_tx.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ typedef struct {
3232
Note that, the valid signal will always occupy the MSB data bit */
3333
size_t trans_queue_depth; /*!< Depth of internal transaction queue */
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size_t max_transfer_size; /*!< Maximum transfer size in one transaction, in bytes. This decides the number of DMA nodes will be used for each transaction */
35+
size_t dma_burst_size; /*!< DMA burst size, in bytes */
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parlio_sample_edge_t sample_edge; /*!< Parallel IO sample edge */
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parlio_bit_pack_order_t bit_pack_order; /*!< Set the order of packing the bits into bytes (only works when `data_width` < 8) */
3738
struct {

‎esp32p4/include/esp_eth/include/esp_eth_mac_esp.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,8 @@ typedef enum {
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/**
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* @brief RMII Clock GPIO number Options for ESP32
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*
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* @warning If you want the Ethernet to work with WiFi, don’t select ESP32 as RMII CLK output as it would result in clock instability.
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*
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*/
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typedef enum {
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/**
@@ -64,10 +66,8 @@ typedef enum {
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/**
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* @brief Output RMII Clock from internal APLL Clock available at GPIO0
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*
67-
* @note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock.
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* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip.
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* You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice.
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* If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.
69+
* @note GPIO0 can be set to output a pre-divided PLL clock. Enabling this option will configure GPIO0 to output a 50MHz clock.
70+
* In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock may not work well with your PHY chip.
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*
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*/
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EMAC_APPL_CLK_OUT_GPIO = 0,

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