Describe the bug

On RT1XXX platforms, the spi loopback test reports the spi_complete_loop_mode_0 and spi_complete_loop_mode_2 tests. This is when clock phase is set to 0. This happens on both the interrupt based and DMA based drivers. It specifically fails when spi frequency is fast.

Regression

• This is a regression.

Steps to reproduce

west build -p always -b mimxrt1050_evk tests/drivers/spi/spi_loopback
west flash

Relevant log output

- FLAKY - [spi_loopback.test_spi_complete_loop_mode_0] - (Failed 1 of 2 attempts) - duration = 0.020 sec
onds
 - PASS - [spi_loopback.test_spi_complete_loop_mode_1] duration = 0.001 seconds
 - FLAKY - [spi_loopback.test_spi_complete_loop_mode_2] - (Failed 1 of 2 attempts) - duration = 0.020 sec
onds
 - PASS - [spi_loopback.test_spi_complete_loop_mode_3] duration = 0.001 seconds

Impact

Functional Limitation – Some features not working as expected, but system usable.

Environment

Zephyr SDK

Additional Context

These clock mode test cases are new.