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The system includes sensors embedded in textile and connected by conductive yarns. Synchronization is based on the open\u2010loop selection of the correct phase of the receiver clock synchronously with the incoming signal. The clock generator of the receiver is an autonomous oscillator set to operate at the same nominal frequency. The circuit lock time is at most one clock cycle, faster than all methods based on phase\u2010locked loops or delay\u2010locked loops. The circuit can be used for baseband communication independently of the signal coding method used in the physical layer, making it suitable for many applications. The fully digital circuit (including non\u2010return\u2010to\u2010zero inverted decoder) occupies 0.0022 in a 0.35 complementary metal\u2010oxide semiconductor (CMOS) process, a smaller implementation than many existing circuits, and supports a maximum system clock frequency of 70 for a 35\u2010data rate. Experimental results demonstrate that the proposed circuit robustly generates a synchronous clock for data recovery. The circuit is suitable for systems that tolerate some jitter but requires fast lock time, small size, and low energy consumption. Copyright \u00a9 2015 John Wiley &amp; Sons, Ltd.<\/jats:p>","DOI":"10.1002\/cta.2092","type":"journal-article","created":{"date-parts":[[2015,4,27]],"date-time":"2015-04-27T09:05:33Z","timestamp":1430125533000},"page":"530-548","source":"Crossref","is-referenced-by-count":1,"title":["A small fully digital open\u2010loop clock and data recovery circuit for wired BANs"],"prefix":"10.1002","volume":"44","author":[{"given":"Fardin","family":"Derogarian","sequence":"first","affiliation":[{"name":"INESC TEC Faculdade de Engenharia da Universidade do Porto Rua Dr. Roberto Frias Porto 4200\u2010465 Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jo\u00e3o Canas","family":"Ferreira","sequence":"additional","affiliation":[{"name":"INESC TEC Faculdade de Engenharia da Universidade do Porto Rua Dr. Roberto Frias Porto 4200\u2010465 Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V\u00edtor Grade","family":"Tavares","sequence":"additional","affiliation":[{"name":"INESC TEC Faculdade de Engenharia da Universidade do Porto Rua Dr. Roberto Frias Porto 4200\u2010465 Portugal"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2015,4,27]]},"reference":[{"key":"e_1_2_9_2_1","doi-asserted-by":"publisher","DOI":"10.1201\/9781420041163"},{"key":"e_1_2_9_3_1","doi-asserted-by":"publisher","DOI":"10.1002\/0470087803"},{"key":"e_1_2_9_4_1","doi-asserted-by":"publisher","DOI":"10.1002\/0471200573"},{"key":"e_1_2_9_5_1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511807046"},{"key":"e_1_2_9_6_1","first-page":"1","article-title":"Design and performance study of phase\u2010locked loop using fractional\u2010order loop filter","author":"Tripathy MC","year":"2014","journal-title":"Int. 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