{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,19]],"date-time":"2024-12-19T05:21:09Z","timestamp":1734585669551,"version":"3.30.2"},"reference-count":17,"publisher":"Wiley","issue":"11","license":[{"start":{"date-parts":[[2004,8,24]],"date-time":"2004-08-24T00:00:00Z","timestamp":1093305600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Systems &amp;amp; Computers in Japan"],"published-print":{"date-parts":[[2004,10]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>The cerebellar model arithmetic computer (CMAC) is a kind of neural network that is capable of high\u2010speed learning. In the use of the CMAC, various parameters must be defined, but it is difficult to set the parameters adequately. The pseudo\u2010bacterial genetic algorithm (PBGA) is a kind of evolutionary computation which offers local search. This paper considers adequate determination of the location of the boundary line, which is one of the parameters of the CMAC. For that purpose the PBGA is applied, and PBGA\/CMAC, which realizes the efficient search of the boundary line of the CMAC, is proposed. Furthermore, since PBGA\/CMAC requires a large amount of computation, a hardware implementation is considered in order to improve the computation speed. The computation involved in the learning rules of the CMAC is divided into four stages, and the structure is implemented as a pipeline. The pipeline implementation produces read\u2010after\u2010write hazards for the granular cell values. However, it is shown that the difference in performance from conventional CMAC learning rule is small, indicating the possibility of achieving high\u2010speed learning. The speed of PBGA\/CMAC hardware is improved to 140 times the speed of operation by software. In order to present a guide for PBGA\/CMAC hardware, the hardware volume is evaluated, and it is shown that it can be implemented with precision sufficient for practice. \u00a9 2004 Wiley Periodicals, Inc. Syst Comp Jpn, 35(11): 14\u201323, 2004; Published online in Wiley InterScience (<jats:ext-link xmlns:xlink=\"http:\/\/www.w3.org\/1999\/xlink\" xlink:href=\"http:\/\/www.interscience.wiley.com\">www.interscience.wiley.com<\/jats:ext-link>). DOI 10.1002\/scj.10437<\/jats:p>","DOI":"10.1002\/scj.10437","type":"journal-article","created":{"date-parts":[[2004,8,24]],"date-time":"2004-08-24T15:08:25Z","timestamp":1093360105000},"page":"14-23","source":"Crossref","is-referenced-by-count":1,"title":["Cerebellar model arithmetic computer with pseudo\u2010bacterial genetic algorithm and its hardware acceleration"],"prefix":"10.1002","volume":"35","author":[{"given":"Masahiro","family":"Miwa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Takeshi","family":"Furuhashi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Motoaki","family":"Matsuzaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shigeru","family":"Okuma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"311","published-online":{"date-parts":[[2004,8,24]]},"reference":[{"volume-title":"Brains, behavior and robotics","year":"1981","author":"Albus JS","key":"e_1_2_1_2_2"},{"unstructured":"OzawaJ HayashiI WakamiN.A proposal of examination method of input\u2013output data using CMAC\u2010algorithm for fuzzy modeling. 7th Fuzzy System Symposium p435\u2013438 1991.","key":"e_1_2_1_3_2"},{"doi-asserted-by":"publisher","key":"e_1_2_1_4_2","DOI":"10.1007\/978-3-642-82153-0_3"},{"doi-asserted-by":"crossref","unstructured":"GrahamP NelsonB.A hardware genetic algorithm for the traveling salesman problem on splash 2. Field Programmable Logic and Applications p352\u2013361 1995.","key":"e_1_2_1_5_2","DOI":"10.1007\/3-540-60294-1_129"},{"doi-asserted-by":"crossref","unstructured":"ScottSD SamalA SethS.HGA: A hardware based genetic algorithm. Proc 3rd Int Symp on FPGA p53\u201359 1995.","key":"e_1_2_1_6_2","DOI":"10.1109\/FPGA.1995.241945"},{"key":"e_1_2_1_7_2","first-page":"249","volume-title":"Multiple genetic algorithm processor for hardware optimization. Lecture Notes in Evolvable Systems: From Biology to Hardware","author":"Salami M","year":"1996"},{"unstructured":"YoshidaN MorikiT YasuokaT.GAP: Genetic VLSI processor for genetic algorithms. 2nd Int Symp on Soft Computing p341\u2013345 1997.","key":"e_1_2_1_8_2"},{"key":"e_1_2_1_9_2","first-page":"962","article-title":"Hardware framework for accelerating the execution speed of genetic algorithms","volume":"80","author":"Shackleford B","year":"1997","journal-title":"IEICE Trans Electron"},{"unstructured":"AsadaH SugiuraH KawaiT AndoH ShimadaT.H3: High\u2010speed hardware for human\u2010like genetic algorithm. 3rd Int Symp on Artificial Life and Robotics (AROB III '98) p190\u2013195.","key":"e_1_2_1_10_2"},{"volume-title":"Genetic algorithm and optimization","year":"1998","author":"Mitsumiya N","key":"e_1_2_1_11_2"},{"doi-asserted-by":"crossref","unstructured":"NawaNE FuruhashiT.A study on the effect of genes for the bacterial evolutionary algorithm. Proc Second Int Conf on Knowledge Based Electronic Systems (KES'98) Vol. 3 p585\u2013590.","key":"e_1_2_1_12_2","DOI":"10.1109\/KES.1998.726026"},{"doi-asserted-by":"publisher","key":"e_1_2_1_13_2","DOI":"10.1109\/41.807990"},{"volume-title":"Introduction to neural computing","year":"1993","author":"Peele R","key":"e_1_2_1_14_2"},{"unstructured":"YangJ HorngJ KaoC.A continuous genetic algorithm for global optimization. Proc Seventh Int Conference on Genetic Algorithms p230\u2013237 1997.","key":"e_1_2_1_15_2"},{"unstructured":"MahfoudSW.A comparison of parallel and aequential niching methods. Proc Sixth Int Conference on Genetic Algorithms p136\u2013143 1995.","key":"e_1_2_1_16_2"},{"volume-title":"Introduction to statistical analysis with Excel","year":"1999","author":"Suga T","key":"e_1_2_1_17_2"},{"volume-title":"Computer hardware","year":"1995","author":"Tomita S","key":"e_1_2_1_18_2"}],"container-title":["Systems and Computers in Japan"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.wiley.com\/onlinelibrary\/tdm\/v1\/articles\/10.1002%2Fscj.10437","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/scj.10437","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,18]],"date-time":"2024-12-18T10:22:14Z","timestamp":1734517334000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/scj.10437"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2004,8,24]]},"references-count":17,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2004,10]]}},"alternative-id":["10.1002\/scj.10437"],"URL":"https:\/\/doi.org\/10.1002\/scj.10437","archive":["Portico"],"relation":{},"ISSN":["0882-1666","1520-684X"],"issn-type":[{"type":"print","value":"0882-1666"},{"type":"electronic","value":"1520-684X"}],"subject":[],"published":{"date-parts":[[2004,8,24]]}}}