{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,17]],"date-time":"2026-06-17T16:38:32Z","timestamp":1781714312548,"version":"3.54.5"},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/micro.2004.9","type":"proceedings-article","created":{"date-parts":[[2005,12,13]],"date-time":"2005-12-13T20:55:52Z","timestamp":1134507352000},"page":"331-342","source":"Crossref","is-referenced-by-count":16,"title":["Cache Refill\/Access Decoupling for Vector Machines"],"prefix":"10.1109","author":[{"given":"C.","family":"Batten","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"R.","family":"Krashinsky","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"S.","family":"Gerding","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"K.","family":"Asanovic","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310763"},{"key":"17","first-page":"2","article-title":"A hardware overview of SX-6 and SX-7 supercomputer","volume":"44","author":"kitagawa","year":"2003","journal-title":"NEC Res Develop"},{"key":"18","article-title":"Overcoming the limitations of conventional vector processors","author":"kozyrakis","year":"2003","journal-title":"ISCA-30"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/40.755465"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/40.918001"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10007"},{"key":"14","doi-asserted-by":"crossref","DOI":"10.1145\/325164.325162","article-title":"Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers","author":"jouppi","year":"1990","journal-title":"ISCA-15"},{"key":"11","article-title":"A CMOS vector processor with a custom streaming cache","volume":"10","author":"faanes","year":"1998","journal-title":"Proc Hot Chips"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/115952.115959"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1261383"},{"key":"20","first-page":"81","article-title":"Lockup-free instruction fetch\/prefetch cache organization","author":"kroft","year":"1981","journal-title":"ISCA-8"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1994.288164"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/359327.359336"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604703"},{"key":"25","article-title":"Supercomputing past, present, and future","author":"scott","year":"2004","journal-title":"ICS-18 Keynote Address"},{"key":"26","article-title":"Decoupled access\/execute computer architecture","author":"smith","year":"1982","journal-title":"ISCA-9"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/2.30730"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1147\/sj.251.0004"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1016\/0167-8191(87)90021-4"},{"key":"3","doi-asserted-by":"crossref","DOI":"10.1145\/325164.325145","article-title":"VAX vector architecture","author":"bhandarkar","year":"1990","journal-title":"ISCA-15"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645807"},{"key":"1","article-title":"So many states, so little time: Verifying memory coherence in the Cray XI","author":"abts","year":"2003","journal-title":"IPDPS"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/2.596622"},{"key":"7","first-page":"68","article-title":"Improving data cache performance by pre-executing instructions under a cache miss","author":"dundas","year":"1997","journal-title":"Proc ICS"},{"key":"6","year":"2002","journal-title":"Cray Launches X1 for Extreme Supercomputing"},{"key":"5","author":"cray","year":"2003"},{"key":"4","first-page":"141","article-title":"The reconfigurable streaming vector processor (RSVP)","author":"ciricescu","year":"2003","journal-title":"MICRO-36"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1996.501193"},{"key":"8","article-title":"Tarantula: A vector extension to the Alpha architecture","author":"espasa","year":"2002","journal-title":"1SCA-29"}],"event":{"name":"37th International Symposium on Microarchitecture (MICRO-37'04)","location":"Portland, OR, USA"},"container-title":["37th International Symposium on Microarchitecture (MICRO-37'04)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10398\/33048\/01551005.pdf?arnumber=1551005","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T01:41:30Z","timestamp":1497663690000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1551005\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/micro.2004.9","relation":{},"subject":[]}}