{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T04:13:26Z","timestamp":1742357606375,"version":"3.40.1"},"reference-count":53,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/tc.2012.115","type":"journal-article","created":{"date-parts":[[2012,6,5]],"date-time":"2012-06-05T19:19:52Z","timestamp":1338923992000},"page":"1732-1744","source":"Crossref","is-referenced-by-count":2,"title":["LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging"],"prefix":"10.1109","volume":"62","author":[{"given":"Yunji","family":"Chen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianshi","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ling","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lei","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Menghao","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Weiwu","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1450135.1450163"},{"article-title":"Deterministic Process Groups in dOS","volume-title":"Proc. Ninth USENIX Conf. Operating Systems Design and Implementation (OSDI \u201910)","author":"Bergan","key":"ref2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169043"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815985"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508255"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950376"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373608"},{"volume-title":"ZeBu Server","year":"2013","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.896905"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1998.672552"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/mtv.2003.1250272"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268881"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.203"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/hotchips.2008.7476554"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.30"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2011.5746226"},{"volume-title":"Intel Core 2 Duo Processor and Intel GM45 Express Chipset (with DDR3 System Memory) Development Kit User\u2019s Manual","year":"2013","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146915"},{"article-title":"An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-Based SoC Integration","volume-title":"Proc. ACM\/IEEE 44th Design Automation Conf. (DAC \u201907)","author":"Kao","key":"ref19"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014023"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/359545.359563"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1145\/1391469.1391687","article-title":"A Multi-Resolution AHB Bus Tracer for Real-Time Compression of Forward\/Backward Traces in a Circular Buffer","volume-title":"Proc. ACM\/IEEE 45th Design Automation Conf. (DAC \u201908)","author":"Lin"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2003.1197642"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382146"},{"issue":"8","key":"ref25","first-page":"114","article-title":"Cramming More Components onto Integrated Circuits","volume":"38","author":"Moore","year":"1965","journal-title":"Electronics"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168886"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373611"},{"key":"ref28","first-page":"798","article-title":"Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface","volume":"E79-C","author":"Okajima","year":"1996","journal-title":"IEICE Trans. Electronics"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1646353.1646377"},{"journal-title":"Product Specifications","article-title":"Pll pg 1360x cmos065lp Speccification","year":"2009","key":"ref30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270848"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373610"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2006.19"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.19"},{"article-title":"A 32nm Westmere-EX Xeon Enterprise Processor","volume-title":"Proc. IEEE Int\u2019l Conf. Solid-State Circuits (ISSCC \u201911)","author":"Sawant","key":"ref35"},{"key":"ref36","first-page":"37","article-title":"System Level Validation of the Intel Pentium-M Processor","volume":"7","author":"Silas","year":"2003","journal-title":"Intel Technology J."},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003568"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910963"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457045"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696202"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373606"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950370"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815986"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524546"},{"key":"ref45","doi-asserted-by":"crossref","DOI":"10.1109\/ISSCC.2001.912693","article-title":"The Design and Analysis of the Clock Distribution Network for a 1.2 GHz Alpha Microprocessor","volume-title":"Proc. Int\u2019l Symp. Computer Architecture (ISSCC \u201902)","author":"Xanthopoulos"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168865"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2010760"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883325"},{"article-title":"Non-Intrusive On-Chip Debug Hardware Accelerates Development for MIPS RISC Processors","year":"2013","author":"Zilmer","key":"ref49"},{"volume-title":"TLB Bug of Barcelona","year":"2013","key":"ref50"},{"volume-title":"Intel Pentium 4 Processor on 90 nm Process, Intel Std. Order No. 302 352-024, Intel","year":"2005","key":"ref51"},{"volume-title":"Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Std. Publication 25759, Rev. 3.57, Advanced Micro Devices","year":"2005","key":"ref52"},{"volume-title":"Intel Itanium 2 Specification Update, Intel Std. Document No. 251 141-030, Intel","year":"2005","key":"ref53"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/6568861\/06212446.pdf?arnumber=6212446","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T06:04:01Z","timestamp":1742277841000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6212446\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":53,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tc.2012.115","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2013,9]]}}}