{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T05:40:08Z","timestamp":1742190008602,"version":"3.38.0"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2013,4,1]],"date-time":"2013-04-01T00:00:00Z","timestamp":1364774400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Comput."],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/tc.2012.34","type":"journal-article","created":{"date-parts":[[2012,1,25]],"date-time":"2012-01-25T21:34:34Z","timestamp":1327527274000},"page":"813-826","source":"Crossref","is-referenced-by-count":6,"title":["SMT Malleability in IBM POWER5 and POWER6 Processors"],"prefix":"10.1109","volume":"62","author":[{"given":"A.","family":"Morari","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Boneti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F. J.","family":"Cazorla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Gioiosa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chen-Yong Cher","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Buyuktosunoglu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Bose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Valero","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.8"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536293"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2008.5217785"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.108"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.37"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2006.1639374"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2002.1105971"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508260"},{"volume-title":"Advanced POWER Virtualization on IBM eServer p5 ServersP: Architecture and Performance Considerations.","year":"2005","author":"Gibbs","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.17"},{"volume-title":"IBM, Power ISA V2.03: Book III","year":"2012","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1269899.1254886"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2005.06.016"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1289290"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1147\/rd.516.0639"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2009.3"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.33"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1531793.1531806"},{"volume-title":"NASA, NAS Parallel Benchmarks","year":"2012","key":"ref19"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250671"},{"key":"ref21","first-page":"2","article-title":"Architectural Support for Operating System-Driven CMP Cache Management","volume-title":"Proc. 15th Int\u2019l Conf. Parallel Architectures and Compilation Techniques (PACT \u201906)","author":"Rafique"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0505"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/511334.511343"},{"volume-title":"Standard Performance Evaluation Corporation, SPEC CPU2006","year":"2012","key":"ref24"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2003.1237999"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2001.991129"},{"article-title":"Measuring the Performance of Multithreaded Processors","volume-title":"Proc. SPEC Benchmark Workshop","author":"Vera","key":"ref27"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2007.4336221"}],"container-title":["IEEE Transactions on Computers"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/12\/6471716\/06138854.pdf?arnumber=6138854","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T04:59:29Z","timestamp":1742187569000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6138854\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":28,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tc.2012.34","relation":{},"ISSN":["0018-9340"],"issn-type":[{"type":"print","value":"0018-9340"}],"subject":[],"published":{"date-parts":[[2013,4]]}}}