{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T04:11:23Z","timestamp":1742357483419,"version":"3.40.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2013,11,1]],"date-time":"2013-11-01T00:00:00Z","timestamp":1383264000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. Parallel Distrib. Syst."],"published-print":{"date-parts":[[2013,11]]},"DOI":"10.1109\/tpds.2012.315","type":"journal-article","created":{"date-parts":[[2012,11,15]],"date-time":"2012-11-15T15:53:14Z","timestamp":1352994794000},"page":"2192-2201","source":"Crossref","is-referenced-by-count":7,"title":["Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory"],"prefix":"10.1109","volume":"24","author":[{"given":"Ruben","family":"Titos-Gil","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anurag","family":"Negi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manuel E.","family":"Acacio","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jose M.","family":"Garcia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Per","family":"Stenstrom","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2002.1106014"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250674"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636089"},{"key":"ref4","first-page":"506","article-title":"Transaction Synchronization Extensions (TSX)","year":"2012","journal-title":"Intel Architecture Instruction Set Extensions Programming Reference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698549"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1006\/jpdc.1995.1059"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508263"},{"article-title":"Predicting the Scalability of an STM","volume-title":"TRANSACT \u201910: Proc. Fifth ACM SIGPLAN Workshop Transactional Computing","author":"Dragojevic","key":"ref8"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.91"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698569"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744359"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2009.19"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1105734.1105747"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598134"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2011.63"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/pact.2011.41"},{"article-title":"Hardware Support for Transactional Memory and Thread-Level Speculation in the IBM Blue Gene\/Q System (Keynote Speech)","volume-title":"Proc. Workshop Wild and Sane Ideas in Speculation and Trans.","author":"Ohmacht","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2009.84"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542299"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.17"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/195473.195572"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1993.698550"},{"key":"ref24","first-page":"145","article-title":"EazyHTM: Eager-Lazy Hardware Transactional Memory","volume-title":"Proc. 42nd Int\u2019l Symp. Microarchitecture","author":"Tomic"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346204"}],"container-title":["IEEE Transactions on Parallel and Distributed Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/71\/6613497\/06342882.pdf?arnumber=6342882","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,18]],"date-time":"2025-03-18T05:17:13Z","timestamp":1742275033000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6342882\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,11]]},"references-count":25,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tpds.2012.315","relation":{},"ISSN":["1045-9219"],"issn-type":[{"type":"print","value":"1045-9219"}],"subject":[],"published":{"date-parts":[[2013,11]]}}}