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Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2016,1,28]]},"abstract":"<jats:p>Voltage-frequency island (VFI)-based design has been widely exploited for optimizing system energy of embedded multicore chip in recent years. The existing work either constructed a single static VFI partition for all kinds of applications or required per-core voltage domain configuration. However, the former solution is hard to find one optimal VFI partition for diverse applications while the latter one suffers from high hardware cost. In this article, we propose a cost effective energy optimization framework based on dynamically reconfigurable VFI (D-VFI). Our framework treats a small number of cores as dynamic cores (D-cores) and configures each of them with an independent voltage domain. At runtime, the D-cores can be pieced together with neighboring static VFIs by scaling their operating voltages. This can dynamically construct the optimal VFI partitions for different kinds of applications, thus achieving more aggressive energy optimization under low cost. To identify the D-cores, we propose a rules constrained task scheduling and VFI partitioning algorithm. Moreover, we analyze the task schedules to determine the optimal scaling intervals which can accommodate voltage scaling induced latency. Experimental results demonstrate that the effectiveness of the proposed scheme.<\/jats:p>","DOI":"10.1145\/2817207","type":"journal-article","created":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T20:37:54Z","timestamp":1454359074000},"page":"1-14","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands"],"prefix":"10.1145","volume":"21","author":[{"given":"Song","family":"Jin","sequence":"first","affiliation":[{"name":"North China Electric Power University, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Songwei","family":"Pei","sequence":"additional","affiliation":[{"name":"Beijing University of Chemical Technology, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yinhe","family":"Han","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huawei","family":"Li","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, P. R. China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2016,1,28]]},"reference":[{"key":"e_1_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024774"},{"volume-title":"Proceedings of the IEEE Computer Society Workshop on VLSI. 119--126","author":"Chelcea T.","key":"e_1_2_1_2_1","unstructured":"T. Chelcea and S. M. Nowick . 2000. A low latency FIFO for mixed-clock systems . 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