{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T20:10:31Z","timestamp":1741119031384,"version":"3.38.0"},"reference-count":22,"publisher":"Institute of Electronics, Information and Communications Engineers (IEICE)","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEICE Trans. Fundamentals"],"published-print":{"date-parts":[[2011]]},"DOI":"10.1587\/transfun.e94.a.1067","type":"journal-article","created":{"date-parts":[[2011,4,1]],"date-time":"2011-04-01T06:30:05Z","timestamp":1301639405000},"page":"1067-1081","source":"Crossref","is-referenced-by-count":0,"title":["Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis"],"prefix":"10.1587","volume":"E94-A","author":[{"given":"Keisuke","family":"INOUE","sequence":"first","affiliation":[{"name":"School of Information Science, Japan Advanced Institute of Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mineo","family":"KANEKO","sequence":"additional","affiliation":[{"name":"School of Information Science, Japan Advanced Institute of Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsuyoshi","family":"IWAGAKI","sequence":"additional","affiliation":[{"name":"School of Information Science, Japan Advanced Institute of Science and Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"532","reference":[{"unstructured":"[1] S. Matsumoto, H.J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, &ldquo;Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability,&rdquo; Proc. Custom Integrated Circuits Conference (CICC), pp.582-585, May 2001.","key":"1"},{"doi-asserted-by":"crossref","unstructured":"[2] B. Chen, H. Yang, R. Luo, and H. Wang, &ldquo;A novel method for worst-case interconnect delay estimation,&rdquo; IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.50, no.6, pp.778-781, June 2003.","key":"2","DOI":"10.1109\/TCSI.2003.812619"},{"unstructured":"[3] J.-L. Tsai, D. Baik, C.C.-P. Chen, and K.K. Saluja, &ldquo;A yield improvement methodology using pre- and post-silicon statistical clock scheduling,&rdquo; Proc. International Conference on Computer-Aided Design (ICCAD), pp.611-618, Nov. 2004.","key":"3"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1093\/ietfec\/e91-a.9.2322"},{"doi-asserted-by":"crossref","unstructured":"[5] W.-L. Hung, X. Wu, and Y. Xie, &ldquo;Guaranteeing performance yield in high-level synthesis,&rdquo; Proc. International Conference on Computer-Aided Design (ICCAD), pp.303-309, Nov. 2006.","key":"5","DOI":"10.1109\/ICCAD.2006.320050"},{"doi-asserted-by":"crossref","unstructured":"[6] J. Jung and T. Kim, &ldquo;Timing variation-aware high-level synthesis,&rdquo; Proc. International Conference on Computer-Aided Design (ICCAD), pp.424-428, Nov. 2007.","key":"6","DOI":"10.1109\/ICCAD.2007.4397302"},{"doi-asserted-by":"crossref","unstructured":"[7] K. Ohashi and M. Kaneko, &ldquo;Statistical analysis driven synthesis of application specific asynchronous systems,&rdquo; IEICE Trans. Fundamentals, vol.E90-A, no.3, pp.659-669, March 2007.","key":"7","DOI":"10.1093\/ietfec\/e90-a.3.659"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/TCAD.2007.896305"},{"unstructured":"[9] D. Ernar, N.S. Kim, A. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, &ldquo;Razor: A low-power pipeline based on circuit-level timing speculation,&rdquo; Proc. International Symposium on Microarchitecture (MICRO), pp.7-18, Dec. 2003.","key":"9"},{"doi-asserted-by":"crossref","unstructured":"[10] T. Sato and Y. Kunitake, &ldquo;A simple flip-flop circuit for typical-case designs for DFM,&rdquo; Proc. International Symposium on Quality Electronic Design (ISQED), pp.539-544, March 2007.","key":"10","DOI":"10.1109\/ISQED.2007.23"},{"unstructured":"[11] Z. Wang, M. M-Sadowska, K.-H. Tsai, and J. Rajski, &ldquo;Diagnosis of hold time defects,&rdquo; Proc. International Conference on Computer Design (ICCD), pp.192-199, Oct. 2004.","key":"11"},{"doi-asserted-by":"crossref","unstructured":"[12] J. Xi and W.W.-M. Dai, &ldquo;Jitter-tolerant clock routing in two-phase synchronous systems,&rdquo; Proc. International Conference on Computer-Aided Design (ICCAD), pp.316-320, Nov. 1996.","key":"12","DOI":"10.1109\/ICCAD.1996.569719"},{"unstructured":"[13] N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design &mdash; System Perspective, second ed., Addison-Wesley Publishing Company, 1994.","key":"13"},{"unstructured":"[14] K. Inoue, M. Kaneko, and T. Iwagaki, &ldquo;Structural robustness of datapaths against delay-variation,&rdquo; Proc. Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), pp.272-279, Oct. 2007.","key":"14"},{"doi-asserted-by":"publisher","key":"15","DOI":"10.1093\/ietfec\/e91-a.4.1044"},{"doi-asserted-by":"crossref","unstructured":"[16] A. Hashimoto and S. Stevens, &ldquo;Wire routing by optimizing channel assignment within large apertures,&rdquo; Proc. Design Automation Conference (DAC), pp.155-169, June 1971.","key":"16","DOI":"10.1145\/800158.805069"},{"doi-asserted-by":"crossref","unstructured":"[17] M.R. Garey, D.S. Johnson, G.L. Miller, and C.H. Papadimitriou, &ldquo;The complexity of coloring circular arcs and chords,&rdquo; SIAM J. Algebr. Discrete Methods, vol.1, no.2, pp.216-227, 1980.","key":"17","DOI":"10.1137\/0601025"},{"doi-asserted-by":"crossref","unstructured":"[18] B. Mulgrew, P. Grant, and J. Thompson, Digital Signal Processing, Macmillan Press, 1999.","key":"18","DOI":"10.1007\/978-1-349-14944-5"},{"doi-asserted-by":"crossref","unstructured":"[19] P. Michel, U. Lauther, and P. Duzy, The Synthesis Approach to Digital System Design, Kluwer Academic Publishers, 1992.","key":"19","DOI":"10.1007\/978-1-4615-3632-1"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1093\/comjnl\/43.2.152"},{"unstructured":"[21] R.R. Hoare, A.K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung, and M. McCloud, &ldquo;Rapid VLIW processor customization for signal processing applications using combinational hardware functions,&rdquo; Proc. EURASIP J. Appl. Signal Process., vol.2006, no.1, pp.1-23, Jan. 2008.","key":"21"},{"unstructured":"[22] IBM ILOG, CPLEX, http:\/\/www.ilog.com","key":"22"}],"container-title":["IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/www.jstage.jst.go.jp\/article\/transfun\/E94.A\/4\/E94.A_4_1067\/_pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,4]],"date-time":"2025-03-04T19:40:00Z","timestamp":1741117200000},"score":1,"resource":{"primary":{"URL":"http:\/\/www.jstage.jst.go.jp\/article\/transfun\/E94.A\/4\/E94.A_4_1067\/_article"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011]]},"references-count":22,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2011]]}},"URL":"https:\/\/doi.org\/10.1587\/transfun.e94.a.1067","relation":{},"ISSN":["0916-8508","1745-1337"],"issn-type":[{"type":"print","value":"0916-8508"},{"type":"electronic","value":"1745-1337"}],"subject":[],"published":{"date-parts":[[2011]]}}}