verilog HDLBits刷题[Counters]“Countslow”---Slow decade counter

一、题目

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

Module Declaration

module top_module (
    input clk,
    input slowena,
    input reset,
    output [3:0] q);

二、分析

 复位计数归0；slowena为0时，暂停计数递增；计数满9为0

三、代码实现

 module top_module (
    input clk,
    input slowena,
    input reset,
    output reg[3:0] q);
    always@(posedge clk)
        if(reset)
            q<=4'd0;
    else if(slowena==0)
        q<=q;
    else if(q==4'd9)
        q<=4'd0;
    else 
        q<=q+4'd1;
endmodule

四、时序