Verilog中的Latch

Latch介绍

功能描述

• Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
• However, they are still sequential elements, so should use non-blocking assignments.
• A D-latch acts like a wire (or non-inverting buffer) when enabled, and preserves the current value when disabled.

代码实现

module top_module (
    input d, 
    input ena,
    output q);
    assign q=(ena)?d:q;
endmodule

生成电路

module top_module (
    input d,