（自用）乒乓操作和简易实现：双口RAM版

原创已于 2023-07-16 21:47:13 修改 · 288 阅读

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IP核笔记

于 2023-07-16 21:45:38 首次发布

该模块描述了一个FPGA设计，包含两个双端口RAM（RAM_ARAM_A_inst0和RAM_BRAM_B_inst0），分别用写地址(write_Addr_A,write_Addr_B)和读地址(Read_addr_A,Read_addr_B)进行操作。同时，有一个PLL(pllpll_50mhz2100mhz)用于时钟频率转换，将Sys_clk转换为CLK_OUT1。数据在写入和读取过程中通过write_A和write_B信号同步，并在Out_data输出。

module top (
    input   wire            Sys_clk,
    input   wire            Rst_n  ,
    output  wire    [7:0]   Out_data
);
            wire   [7:0]    Out_A;
            wire   [7:0]    Out_B;
            reg    [9:0]    write_Addr_A;
            reg    [9:0]    write_Addr_B;
            reg    [9:0]    Read_addr_A ;
            reg    [9:0]    Read_addr_B ;
            reg             write_A;
            reg             write_B;
            reg    [7:0]    data_a ;
            reg    [7:0]    data_b ; 
           wire             CLK_OUT1;
    assign Out_data = (write_A==0) ? (Out_A):
                      (write_B==0) ? (Out_B):8'd0;
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            write_A <= 1'b1;
        else if(write_Addr_A == 10'd1023)
            write_A <= 1'b0;
        else if(write_Addr_B == 10'd1023)
            write_A <= 1'b1;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            write_B <= 1'b0;
        else if(write_Addr_A == 10'd1023)
            write_B <= 1'b1;
        else if(write_Addr_B == 10'd1023)
            write_B <= 1'b0;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            write_Addr_A <= 10'd0;
        else if(write_A)
            write_Addr_A <= write_Addr_A + 1'b1;
        else
            write_Addr_A <= 10'd0;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            write_Addr_B <= 10'd0;
        else if(write_B)
            write_Addr_B <= write_Addr_B + 1'b1;
        else
            write_Addr_B <= 10'd0;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            Read_addr_A <= 10'd0;
        else if(write_B)
            Read_addr_A <= Read_addr_A + 1'b1;
        else
            Read_addr_A <= 10'd0;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            Read_addr_B <= 10'd0;
        else if(write_A)
            Read_addr_B <= Read_addr_B + 1'b1;
        else
            Read_addr_B <= 10'd0;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            data_a <= 8'd0;
        else if(write_A)
            data_a <= data_a + 1'd1;
        else
            data_a <= 1'd0;
    end
    always @(posedge Sys_clk or negedge Rst_n) begin
        if(!Rst_n)
            data_b <= 8'd255;
        else if(write_B)
            data_b <= data_b - 1'd1;
        else
            data_b <= 8'd255;
    end

pll pll_50mhz2100mhz
   (// Clock in ports
    .CLK_IN1(Sys_clk),      // IN
    // Clock out ports
    .CLK_OUT1(CLK_OUT1));    // OUT


RAM_A RAM_A_inst0 (
  .clka     (CLK_OUT1), // input clka
  .wea      (write_A ), // input [0 : 0] wea
  .addra    (write_Addr_A), // input [9 : 0] addra
  .dina     (data_a), // input [7 : 0] dina
  .clkb     (CLK_OUT1), // input clkb
  .addrb    (Read_addr_A), // input [9 : 0] addrb
  .doutb    (Out_A) // output [7 : 0] doutb
);
RAM_B RAM_B_inst0 (
  .clka     (CLK_OUT1), // input clka
  .wea      (write_B), // input [0 : 0] wea
  .addra    (write_Addr_B), // input [9 : 0] addra
  .dina     (data_b), // input [7 : 0] dina
  .clkb     (CLK_OUT1), // input clkb
  .addrb    (Read_addr_B), // input [9 : 0] addrb
  .doutb    (Out_B) // output [7 : 0] doutb
);
endmodule

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