目录
目录
一、颜色主题
低对比度的颜色主题有利于代码编写时，透过代码看到它本身的内涵。这里我的偏好是深色，但vscode的默认深色主题黑白亮暗的对比度偏高，因此用solarized dark主题取代default的深色主题。
这只是系统自带的，相关主题更好的可以另行搜索安装。
有些显示屏上使用solarized dark对比度会有些过低，看不清，此时可用 One Dark Pro，对比度更高一点。（我在小米pro上用的solarized dark，ThinkPad上用 One Dark Pro）
二、字体
原理同颜色主题，好的字体可以让设计师更容易理解代码。参考某位代码大佬的建议，选用了comic code作为主力字体。（事实上vscode 默认使用的consolas字体也很优秀，不一定非得换）
comic code 有些是免费可下载的，下载地址：
Comic Mono | comic-mono-font (dtinth.github.io)
https://dtinth.github.io/comic-mono-font/下载文件后可以直接安装，在vscode中修改字体为：comic mono，效果如下：
第二个链接需要手动操做：
Comic Sans Font - Free Downloads | FontSpacehttps://www.fontspace.com/category/comic-sans下载完成后，解压， 将文件名修改得好记一些：
将comicsan.ttf文件移入windows/fonts路径下，即可在vscode中修改字体为文件名，效果如下：
个人认为GitHub下载的comic code字体更适合于阅读。
在不同显示器和系统分辨率下，行间距和字体之间的关系不一定会有和谐的呈现，在settings.json中使用如下语句更改行间距和字体大小，调整以适合coding：
"editor.lineHeight":20,//行间距，H大写
"editor.fontSize":13,//字体大小，S大写附本人settings.json全部代码，以便后期配置：
{
"highlight-icemode.borderColor": "yellow",
"highlight-icemode.backgroundColor": "red",
"editor.minimap.enabled": false,
"verilog.ctags.path": "C:\\Users\\Adminstrator\\.vscode\\extensions\\ctags.exe",
"workbench.colorCustomizations": {
"editor.selectionBackground": "#f3ef1633",
"editor.selectionHighlightBackground": "#f009336a"
},
"verilog.linting.linter": "xvlog",
"json.schemas": [
],
"editor.detectIndentation": false, //制表符显示->
"editor.renderControlCharacters": true,//显示tab
"editor.renderWhitespace": "all", //显示空格
"editor.tabSize": 4,//tab为四个空格
"editor.insertSpaces": true, //按下tab键时转为插入空格
"terminal.integrated.localEchoStyle": "dim",
"editor.fontWeight": "100",
"editor.lineHeight":20,//行间距，H大写
"editor.fontSize":14,//字体大小，S大写
"editor.fontFamily": "comic mono, 'Courier New', comic mono",//字体comic mono
"editor.fontLigatures": true,
"verilog.linting.iverilog.runAtFileLocation": true,
"security.workspace.trust.untrustedFiles": "open",
"editor.tokenColorCustomizations": {
"comments": "#41b458"//注释颜色设置
},
"files.encoding": "gbk",
"files.autoGuessEncoding": true,
"workbench.colorTheme": "Solarized Dark",
"settingsSync.ignoredExtensions": [
],
"[matlab]":{
"files.encoding": "gbk"
},
"code-runner.runInTerminal":true,
"matlab.mlintpath":"C:\\Program Files\\Polyspace\\R2021a\\bin\\win64\\mlint.exe",
"matlab.matlabpath": "C:\\Program Files\\Polyspace\\R2021a\\bin\\matlab.exe",
"code-runner.executorMap":{
"matlab":"cd $dir && matlab -nosplash -nodesktop -r $fileNameWithoutExt"
},
"stylelint.snippet": [
"css",
"less",
"postcss",
"verilog"
],
"stylelint.validate": [
"css",
"less",
"postcss",
"verilog"
],
"tabnine.experimentalAutoImports": true,
"workbench.preferredDarkColorTheme": "One Dark Pro",
"files.trimTrailingWhitespace": true,//保存文件时删除行末空格
"editor.inlineSuggest.enabled": true,
"cSpell.enableFiletypes": [
"!asciidoc",
"!jupyter",
"!php",
"!plaintext",
"!yaml",
"!yml"
],
"github.copilot.enable": {
"*": true,
"yaml": false,
"plaintext": false,
"markdown": false
}
}三、语法检查
语法检查使用vivado的检查器xvlog，其正确配置过程为：
首先确保插件Verilog-HDL/SystemVerilog/Bluespec SystemVerilog 已经正确安装。
修改Verilog linter设定为：xvlog
将vivado安装路径下的xvlog所在bin文件夹的路径，添加到系统环境变量path中
（注意不是新建一个xvlog变量然后给它修改成bin文件夹的地址）：
添加完成后，为确保vscode更新，关闭后重新打开vscode，在终端中写入命令 xvlog --version ,
以检查前文操做是否生效。
检测到xvlog，说明操做生效，写一个错误代码，保存后可实时看语法检查结果：
至此，自动检测配置完毕。
四、ModelSim环境配置
以10.6d se 版本为例，默认安装完成后，破解过程较简单，在readme中可依样完成，不赘述。
win10以上的系统会出现的一个常见的问题是：破解过程中，运行patch.dll后，弹窗一闪而过，没有生成license.txt。解决办法为：
解决modelsim破解在win10下运行patch失败-百度经验 (baidu.com)
https://jingyan.baidu.com/article/8cdccae9258b1c315413cdf2.html用命令窗取代管理员打开，可以生成license，重新保存好这个txt文件，将它的license添加到环境变量中去。
与vivado联合仿真的步骤：
- 用本机的vivado ，compile出所需的library；
- 将library放入modelsim中的lib文件夹中，将library中的modelsim.ini文件添加为新的用户环境变量，变量名为MODELSIM；
- 在vivado中打开settings，在第三方仿真器中将modelsim安装路径填写至win64一级，将library path设置为库所在地址，在仿真设置中将仿真器设置为modelsim，即可。
附：一个写得很详细的网址配置 VS Code 的 Verilog 开发环境 | Fitz's Blog (zhouyuqian.com)https://zhouyuqian.com/2021/03/15/VerilogOnVscode/
五、自动补全代码
对于常用代码片段，例如计数器、文件头，可以通过自动代码补全减轻代码量。
首先安装插件snippets，安装完毕后，打开路径 C:\Users\Adminstrator\.vscode\extensions\mshr-h.veriloghdl-1.5.3\snippets，打开文件verilog.json,添加如下行：
"counter": {
"prefix": "cntmodule",
"body": [
"//--counter code start--//" ,
"localparam\t${1:RANGE_CNT}\t=\t$2;",
"reg \t\t[ 7 : 0] ${3:cnt}\t;\t//default width . redefine width if necessary.",
"wire \t\tadd_cnt,end_cnt\t;",
"assign \tadd_cnt\t=\t\t\t\t\t\t\t$4;//+1 condition" ,
"assign \tend_cnt\t=\t( add_cnt == 1'b1 )&& (cnt == RANGE_CNT - 1);//end condition" ,
"always @(posedge ${5:Clk_Name} ) begin",
"\tif ( ${6:Rst_Name} ) begin",
"\t\tcnt\t<=\t0;",
"\tend",
"\telse if(add_cnt) begin",
"\t\tif ( end_cnt ) begin",
"\t\t\tcnt\t<=\t0;",
"\t\tend",
"\t\telse begin",
"\t\t\tcnt\t<=\tcnt + 1 ;",
"\t\tend",
"\tend",
"end",
"//--counter code end--//"
],
"description": "general counter module"
},
"vlog_header": {
"prefix": "vlog_header",
"body":[
"//----------------------------------Header--------------------------------",
"//\tCopyright @ administrator . All rights reserved.",
"//\t@author\t\t\t\t: administrator ",
"//\t@date\t\t\t\t: $CURRENT_YEAR-$CURRENT_MONTH-$CURRENT_DATE",
"//***********************************************************",
"//\tmodule name\t\t\t: $TM_FILENAME ",
"//\tencoding \t\t\t: GBK",
"//\tmodule location\t\t: $TM_FILEPATH ",
"//\tmodule description\t:",
"//\tbe used in\t\t\t:",
"//\tversion\t\t\t\t:",
"/*\tfunction\t\t\t:" ,
"*/",
"//-----------------------------------Body---------------------------------",
"`timescale 1ns/1ns"
],
"description": "header description contaning ralative messages"
}保存后退出，再次打开vscode，敲入prefix部分，回车即可补全。
本人ctags verilog代码：
{
"module with parameters": {
"prefix": ["paramod", "module #"],
"body": [
"module ${1:moduleName} #( parameter",
"\t",
") (\\ports",
"\t",
");",
"\t$0",
"endmodule"
],
"description": "Insert a module with parameter"
},
"module without parameters": {
"prefix": "module",
"body": [
"module ${1:moduleName} (",
"\t${2:ports}",
");",
"\t$0",
"endmodule"
],
"description": "Insert a module without parameter"
},
"instantiate module": {
"prefix": ["set module", "instantiate module"],
"body": [
"${1:mod_name} ${2:instance_name} (${3:.*}$0);"
],
"description": "set module, mod i0 (.*);"
},
"always": {
"prefix": ["al", "always"],
"body": [
"always @($1) begin",
"\t$2",
"end"
],
"description": "Insert an always block"
},
"alwaysposclk": {
"prefix": ["alclk", "alwaysposclk"],
"body": [
"always @(posedge clk $1) begin",
"\t$2",
"end"
],
"description": "always @(posedge clk)"
},
"alwaysnegclk": {
"prefix": ["alnegclk", "alwaysnegclk"],
"body": [
"always @(negedge clk $1) begin",
"\t$2",
"end"
],
"description": "always @(negedge clk)"
},
"begin/end": {
"prefix": "begin",
"body": [
"begin",
"\t$1",
"end"
],
"description": "Insert a begin ... end block"
},
"end": {
"prefix": "end",
"body": "end",
"description": "Insert end keyword"
},
"initial": {
"prefix": "initial",
"body": [
"initial begin",
"\t$0",
"end"
],
"description": "initial begin ... end"
},
"case": {
"prefix": "case",
"body": [
"case (${1:param})",
"\t$2: $3",
"\tdefault: $4",
"endcase"
],
"description": "case () ... endcase"
},
"casex": {
"prefix": "casex",
"body": [
"casex (${1:param})",
"\t$2: $3",
"\tdefault: $4",
"endcase"
],
"description": "casex () ... endcase"
},
"casez": {
"prefix": "casez",
"body": [
"casez (${1:param})",
"\t$2: $3",
"\tdefault: $4",
"endcase"
],
"description": "casez () ... endcase"
},
"reg": {
"prefix": "reg",
"body": [
"reg $1;"
],
"description": "reg reg_name;"
},
"regarray": {
"prefix": ["regarray", "reg ["],
"body": [
"reg [$1:$2] $3;"
],
"description": "reg [N:0] reg_name;"
},
"regmemory": {
"prefix": ["regmemory","memory"],
"body": [
"reg [$1:$2] $3 [$4:$5];"
],
"description": "reg [N:0] reg_name [0:M];"
},
"wire": {
"prefix": "wire",
"body": [
"wire $1;"
],
"description": "wire wire_name;"
},
"wirearray": {
"prefix": ["wirearray", "wire ["],
"body": [
"wire [$1:$2] $3;"
],
"description": "wire [N:0] wire_name;"
},
"array": {
"prefix": "array",
"body": "[${1:8}:${2:0}]$0",
"description": "insert [x:y]"
},
"parameter": {
"prefix": "parameter",
"body": [
"parameter $1 = $2;"
],
"description": "paramter var = val;"
},
"localparam": {
"prefix": "localparam",
"body": "localparam $1 = $2;",
"description": "localparam var = val"
},
"integer": {
"prefix": "integer",
"body": "integer $1;",
"description": "integer int_name"
},
"signed": {
"prefix": "signed",
"body": "signed $1 $2;",
"description": "signed datatype name"
},
"include": {
"prefix": ["include", "`include"],
"body": [
"`include \"$1\""
],
"description": "`include \"..\""
},
"define": {
"prefix": ["def", "define", "`define"],
"body": [
"`define ${1:macro}"
],
"description": "`define macro"
},
"ifdef": {
"prefix": ["ifdef", "`ifdef"],
"body": "`ifdef ${1:macro}",
"description": "`ifdef macro"
},
"ifndef": {
"prefix": ["ifndef", "`ifndef"],
"body": "`ifndef ${1:macro}",
"description": "`ifndef macro"
},
"elsif": {
"prefix": ["elsif", "`elsif"],
"body": "`elsif ${1:macro}",
"description": "`elsif macro"
},
"endif": {
"prefix": ["endif", "`endif"],
"body": "`endif ${1:macro}",
"description": "`endif macro"
},
"undef": {
"prefix": ["undef", "`undef"],
"body": "`undef ${1:macro}",
"description": "`undef macro"
},
"timescale": {
"prefix": ["ts", "timescale", "`timescale"],
"body": [
"`timescale ${1:1ps}/${2:1ps}$0"
]
},
"default_nettype": {
"prefix": ["default_nettype", "`default_nettype"],
"body": "`default_nettype ${1:none}",
"description": "Set default nettype"
},
"ternary": {
"prefix": "ternary",
"body": [
"$1 ? $2 : $3"
],
"description": "a ? b : c"
},
"if": {
"prefix": "if",
"body": [
"if (${1:conditions}) begin",
"\t$0",
"end"
],
"description": "if (...) begin ... end"
},
"ifelse": {
"prefix": "ifelse",
"body": [
"if (${1:conditions}) begin",
"\t$2",
"end else begin",
"\t$3",
"end"
],
"description": "if (...) begin ... end else begin ... end"
},
"for loop": {
"prefix": "for",
"body": [
"for ($1 = $2; $3; $4) begin",
"\t$0",
"end"
],
"description": "for (...) begin ... end"
},
"while loop": {
"prefix": "while",
"body": [
"while ($1) begin",
"\t$2",
"end"
],
"description": "while (...) begin ... end"
},
"forever": {
"prefix": "forever",
"body": [
"forever begin",
"\t$0",
"end"
],
"description": "forever begin ... end"
},
"function": {
"prefix": "function",
"body": [
"function $1;",
"\t$2;",
"\t$3",
"endfunction"
],
"description": "function (...) ... endfunction"
},
"generate": {
"prefix": "generate",
"body": [
"generate",
"\t$1",
"endgenerate"
],
"description": "generate (...) ... endgenerate"
},
"genvar": {
"prefix": "genvar",
"body": "genvar $1",
"description": "genvar i"
},
"testbench template": {
"prefix": ["tb", "testbench"],
"body": [
"`include \"$1.v\"",
"`default_nettype none",
"",
"module tb_$1;",
"reg clk;",
"reg rst_n;",
"",
"$1 $3",
"(",
"\t.rst_n (rst_n),",
"\t.clk (clk),",
");",
"",
"localparam CLK_PERIOD = 10;",
"always #(CLK_PERIOD/2) clk=~clk;",
"",
"initial begin",
"\t\\$dumpfile(\"tb_$1.vcd\");",
"\t\\$dumpvars(0, tb_$1);",
"end",
"",
"initial begin",
"\t#1 rst_n<=1'bx;clk<=1'bx;",
"\t#(CLK_PERIOD*3) rst_n<=1;",
"\t#(CLK_PERIOD*3) rst_n<=0;clk<=0;",
"\trepeat(5) @(posedge clk);",
"\trst_n<=1;",
"\t@(posedge clk);",
"\trepeat(2) @(posedge clk);",
"\t\\$finish(2);",
"end",
"",
"endmodule",
"`default_nettype wire"
],
"description": "testbench template"
},
"sinmplecounter": {
"prefix": "simplecntmodule",
"body": [
"//--counter code start--//" ,
"localparam\t${1:RANGE_CNT}\t=\t$2;",
"//--add '$' before clog2--//" ,
"reg \t\t[ clog2(RANGE_CNT) - 1 : 0] ${3:cnt_}\t;",
"always @(posedge ${4:Clk_Name} ) begin",
"\tif \t\t( ${5:Rst_Name} ) begin",
"\t\tcnt_\t<=\t0;",
"\tend",
"\telse if\t( cnt_ >= RANGE_CNT - 1) begin",
"\t\tcnt_\t<=\t0;",
"\tend",
"\telse begin",
"\t\tcnt_\t<=\tcnt_ + 1 ;",
"\tend",
"end",
"//--counter code end--//"
],
"description": "simple counter module"
},
"complicatecounter": {
"prefix": "complicatecntmodule",
"body": [
"//--counter code start--//" ,
"localparam\t${1:RANGE_CNT}\t=\t$2;",
"reg \t\t[ 7 : 0] ${3:cnt}\t;\t//default width . redefine width if necessary.",
"wire \t\tadd_cnt,end_cnt\t;",
"assign \tadd_cnt\t=\t\t\t\t\t\t\t$4;//+1 condition" ,
"assign \tend_cnt\t=\t( add_cnt == 1'b1 )&& (cnt == RANGE_CNT - 1);//end condition" ,
"always @(posedge ${5:Clk_Name} ) begin",
"\tif ( ${6:Rst_Name} ) begin",
"\t\tcnt\t<=\t0;",
"\tend",
"\telse if(add_cnt) begin",
"\t\tif ( end_cnt ) begin",
"\t\t\tcnt\t<=\t0;",
"\t\tend",
"\t\telse begin",
"\t\t\tcnt\t<=\tcnt + 1 ;",
"\t\tend",
"\tend",
"end",
"//--counter code end--//"
],
"description": "complicate counter module"
},
"vlog_header": {
"prefix": "vlog_header",
"body":[
"//----------------------------------------------------Header----------------------------------------------------------",
"//\tCopyright (C) 804 . All rights reserved.",
"//\t@author\t\t\t\t: LC ",
"//\t@date\t\t\t\t: $CURRENT_YEAR-$CURRENT_MONTH-$CURRENT_DATE",
"//************************************************************************",
"//\tencoding \t\t\t: GBK",
"//\tmodule name\t\t\t: $TM_FILENAME ",
"//\tmodule location\t\t: $TM_FILEPATH ",
"//\tmodule description\t:",
"//\tbe used in\t\t\t:",
"//\tversion\t\t\t\t:",
"/*\tfunction\t\t\t:" ,
"*/",
"//-----------------------------------------------------Body-----------------------------------------------------------",
"`timescale 1ns/1ps"
],
"description": "header description contaning ralative messages"
},
"changfengexian": {
"prefix": "changfengexian",
"body":[
"//----------------------------------------------------${1:part_name}--------------------------------------------------"
],
"description": "divide paragraghs"
},
"duanfengexian": {
"prefix": "duanfengexian",
"body":[
"//--------------------------------------${1:part_name}-----------------------------------"
],
"description": "divide paragraghs"
},
"yiwen":{
"prefix":"yiwen",
"body":[
"//=====???@__@???${1:question}====="
],
"descrition":"have questions for the code"
}
}
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