Vivado: 解决Vivado中管脚属性不兼容导致无法生成bit的问题

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已于 2022-04-02 04:33:10 修改 · 3.8k 阅读

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#xilinx #vivado #fpga #zynq

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于 2021-10-27 08:46:51 首次发布

博客讲述了在FPGA设计中遇到的DRCUCIO-1警告，该警告提示未指定特定位置约束的逻辑端口可能导致性能、信号完整性和设备损坏问题。问题源于RGMII信号phy_rxclk被错误地连接到SRCC的负端，而在新版本中，这种分配不再被允许。解决方法是创建一个test-hook.tcl脚本，设置警告级别为警告，并在GenerateBitstream步骤前应用该脚本，从而能够正常生成bit文件。

一、问题

1. 错误信息

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 158 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_r